linux/drivers/net/ethernet/amd/pcnet32.c
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   1/* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */
   2/*
   3 *      Copyright 1996-1999 Thomas Bogendoerfer
   4 *
   5 *      Derived from the lance driver written 1993,1994,1995 by Donald Becker.
   6 *
   7 *      Copyright 1993 United States Government as represented by the
   8 *      Director, National Security Agency.
   9 *
  10 *      This software may be used and distributed according to the terms
  11 *      of the GNU General Public License, incorporated herein by reference.
  12 *
  13 *      This driver is for PCnet32 and PCnetPCI based ethercards
  14 */
  15/**************************************************************************
  16 *  23 Oct, 2000.
  17 *  Fixed a few bugs, related to running the controller in 32bit mode.
  18 *
  19 *  Carsten Langgaard, carstenl@mips.com
  20 *  Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
  21 *
  22 *************************************************************************/
  23
  24#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  25
  26#define DRV_NAME        "pcnet32"
  27#define DRV_VERSION     "1.35"
  28#define DRV_RELDATE     "21.Apr.2008"
  29#define PFX             DRV_NAME ": "
  30
  31static const char *const version =
  32    DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " tsbogend@alpha.franken.de\n";
  33
  34#include <linux/module.h>
  35#include <linux/kernel.h>
  36#include <linux/sched.h>
  37#include <linux/string.h>
  38#include <linux/errno.h>
  39#include <linux/ioport.h>
  40#include <linux/slab.h>
  41#include <linux/interrupt.h>
  42#include <linux/pci.h>
  43#include <linux/delay.h>
  44#include <linux/init.h>
  45#include <linux/ethtool.h>
  46#include <linux/mii.h>
  47#include <linux/crc32.h>
  48#include <linux/netdevice.h>
  49#include <linux/etherdevice.h>
  50#include <linux/if_ether.h>
  51#include <linux/skbuff.h>
  52#include <linux/spinlock.h>
  53#include <linux/moduleparam.h>
  54#include <linux/bitops.h>
  55#include <linux/io.h>
  56#include <linux/uaccess.h>
  57
  58#include <asm/dma.h>
  59#include <asm/irq.h>
  60
  61/*
  62 * PCI device identifiers for "new style" Linux PCI Device Drivers
  63 */
  64static const struct pci_device_id pcnet32_pci_tbl[] = {
  65        { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE_HOME), },
  66        { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE), },
  67
  68        /*
  69         * Adapters that were sold with IBM's RS/6000 or pSeries hardware have
  70         * the incorrect vendor id.
  71         */
  72        { PCI_DEVICE(PCI_VENDOR_ID_TRIDENT, PCI_DEVICE_ID_AMD_LANCE),
  73          .class = (PCI_CLASS_NETWORK_ETHERNET << 8), .class_mask = 0xffff00, },
  74
  75        { }     /* terminate list */
  76};
  77
  78MODULE_DEVICE_TABLE(pci, pcnet32_pci_tbl);
  79
  80static int cards_found;
  81
  82/*
  83 * VLB I/O addresses
  84 */
  85static unsigned int pcnet32_portlist[] =
  86    { 0x300, 0x320, 0x340, 0x360, 0 };
  87
  88static int pcnet32_debug;
  89static int tx_start = 1;        /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */
  90static int pcnet32vlb;          /* check for VLB cards ? */
  91
  92static struct net_device *pcnet32_dev;
  93
  94static int max_interrupt_work = 2;
  95static int rx_copybreak = 200;
  96
  97#define PCNET32_PORT_AUI      0x00
  98#define PCNET32_PORT_10BT     0x01
  99#define PCNET32_PORT_GPSI     0x02
 100#define PCNET32_PORT_MII      0x03
 101
 102#define PCNET32_PORT_PORTSEL  0x03
 103#define PCNET32_PORT_ASEL     0x04
 104#define PCNET32_PORT_100      0x40
 105#define PCNET32_PORT_FD       0x80
 106
 107#define PCNET32_DMA_MASK 0xffffffff
 108
 109#define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ))
 110#define PCNET32_BLINK_TIMEOUT   (jiffies + (HZ/4))
 111
 112/*
 113 * table to translate option values from tulip
 114 * to internal options
 115 */
 116static const unsigned char options_mapping[] = {
 117        PCNET32_PORT_ASEL,                      /*  0 Auto-select      */
 118        PCNET32_PORT_AUI,                       /*  1 BNC/AUI          */
 119        PCNET32_PORT_AUI,                       /*  2 AUI/BNC          */
 120        PCNET32_PORT_ASEL,                      /*  3 not supported    */
 121        PCNET32_PORT_10BT | PCNET32_PORT_FD,    /*  4 10baseT-FD       */
 122        PCNET32_PORT_ASEL,                      /*  5 not supported    */
 123        PCNET32_PORT_ASEL,                      /*  6 not supported    */
 124        PCNET32_PORT_ASEL,                      /*  7 not supported    */
 125        PCNET32_PORT_ASEL,                      /*  8 not supported    */
 126        PCNET32_PORT_MII,                       /*  9 MII 10baseT      */
 127        PCNET32_PORT_MII | PCNET32_PORT_FD,     /* 10 MII 10baseT-FD   */
 128        PCNET32_PORT_MII,                       /* 11 MII (autosel)    */
 129        PCNET32_PORT_10BT,                      /* 12 10BaseT          */
 130        PCNET32_PORT_MII | PCNET32_PORT_100,    /* 13 MII 100BaseTx    */
 131                                                /* 14 MII 100BaseTx-FD */
 132        PCNET32_PORT_MII | PCNET32_PORT_100 | PCNET32_PORT_FD,
 133        PCNET32_PORT_ASEL                       /* 15 not supported    */
 134};
 135
 136static const char pcnet32_gstrings_test[][ETH_GSTRING_LEN] = {
 137        "Loopback test  (offline)"
 138};
 139
 140#define PCNET32_TEST_LEN        ARRAY_SIZE(pcnet32_gstrings_test)
 141
 142#define PCNET32_NUM_REGS 136
 143
 144#define MAX_UNITS 8             /* More are supported, limit only on options */
 145static int options[MAX_UNITS];
 146static int full_duplex[MAX_UNITS];
 147static int homepna[MAX_UNITS];
 148
 149/*
 150 *                              Theory of Operation
 151 *
 152 * This driver uses the same software structure as the normal lance
 153 * driver. So look for a verbose description in lance.c. The differences
 154 * to the normal lance driver is the use of the 32bit mode of PCnet32
 155 * and PCnetPCI chips. Because these chips are 32bit chips, there is no
 156 * 16MB limitation and we don't need bounce buffers.
 157 */
 158
 159/*
 160 * Set the number of Tx and Rx buffers, using Log_2(# buffers).
 161 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
 162 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
 163 */
 164#ifndef PCNET32_LOG_TX_BUFFERS
 165#define PCNET32_LOG_TX_BUFFERS          4
 166#define PCNET32_LOG_RX_BUFFERS          5
 167#define PCNET32_LOG_MAX_TX_BUFFERS      9       /* 2^9 == 512 */
 168#define PCNET32_LOG_MAX_RX_BUFFERS      9
 169#endif
 170
 171#define TX_RING_SIZE            (1 << (PCNET32_LOG_TX_BUFFERS))
 172#define TX_MAX_RING_SIZE        (1 << (PCNET32_LOG_MAX_TX_BUFFERS))
 173
 174#define RX_RING_SIZE            (1 << (PCNET32_LOG_RX_BUFFERS))
 175#define RX_MAX_RING_SIZE        (1 << (PCNET32_LOG_MAX_RX_BUFFERS))
 176
 177#define PKT_BUF_SKB             1544
 178/* actual buffer length after being aligned */
 179#define PKT_BUF_SIZE            (PKT_BUF_SKB - NET_IP_ALIGN)
 180/* chip wants twos complement of the (aligned) buffer length */
 181#define NEG_BUF_SIZE            (NET_IP_ALIGN - PKT_BUF_SKB)
 182
 183/* Offsets from base I/O address. */
 184#define PCNET32_WIO_RDP         0x10
 185#define PCNET32_WIO_RAP         0x12
 186#define PCNET32_WIO_RESET       0x14
 187#define PCNET32_WIO_BDP         0x16
 188
 189#define PCNET32_DWIO_RDP        0x10
 190#define PCNET32_DWIO_RAP        0x14
 191#define PCNET32_DWIO_RESET      0x18
 192#define PCNET32_DWIO_BDP        0x1C
 193
 194#define PCNET32_TOTAL_SIZE      0x20
 195
 196#define CSR0            0
 197#define CSR0_INIT       0x1
 198#define CSR0_START      0x2
 199#define CSR0_STOP       0x4
 200#define CSR0_TXPOLL     0x8
 201#define CSR0_INTEN      0x40
 202#define CSR0_IDON       0x0100
 203#define CSR0_NORMAL     (CSR0_START | CSR0_INTEN)
 204#define PCNET32_INIT_LOW        1
 205#define PCNET32_INIT_HIGH       2
 206#define CSR3            3
 207#define CSR4            4
 208#define CSR5            5
 209#define CSR5_SUSPEND    0x0001
 210#define CSR15           15
 211#define PCNET32_MC_FILTER       8
 212
 213#define PCNET32_79C970A 0x2621
 214
 215/* The PCNET32 Rx and Tx ring descriptors. */
 216struct pcnet32_rx_head {
 217        __le32  base;
 218        __le16  buf_length;     /* two`s complement of length */
 219        __le16  status;
 220        __le32  msg_length;
 221        __le32  reserved;
 222};
 223
 224struct pcnet32_tx_head {
 225        __le32  base;
 226        __le16  length;         /* two`s complement of length */
 227        __le16  status;
 228        __le32  misc;
 229        __le32  reserved;
 230};
 231
 232/* The PCNET32 32-Bit initialization block, described in databook. */
 233struct pcnet32_init_block {
 234        __le16  mode;
 235        __le16  tlen_rlen;
 236        u8      phys_addr[6];
 237        __le16  reserved;
 238        __le32  filter[2];
 239        /* Receive and transmit ring base, along with extra bits. */
 240        __le32  rx_ring;
 241        __le32  tx_ring;
 242};
 243
 244/* PCnet32 access functions */
 245struct pcnet32_access {
 246        u16     (*read_csr) (unsigned long, int);
 247        void    (*write_csr) (unsigned long, int, u16);
 248        u16     (*read_bcr) (unsigned long, int);
 249        void    (*write_bcr) (unsigned long, int, u16);
 250        u16     (*read_rap) (unsigned long);
 251        void    (*write_rap) (unsigned long, u16);
 252        void    (*reset) (unsigned long);
 253};
 254
 255/*
 256 * The first field of pcnet32_private is read by the ethernet device
 257 * so the structure should be allocated using pci_alloc_consistent().
 258 */
 259struct pcnet32_private {
 260        struct pcnet32_init_block *init_block;
 261        /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */
 262        struct pcnet32_rx_head  *rx_ring;
 263        struct pcnet32_tx_head  *tx_ring;
 264        dma_addr_t              init_dma_addr;/* DMA address of beginning of the init block,
 265                                   returned by pci_alloc_consistent */
 266        struct pci_dev          *pci_dev;
 267        const char              *name;
 268        /* The saved address of a sent-in-place packet/buffer, for skfree(). */
 269        struct sk_buff          **tx_skbuff;
 270        struct sk_buff          **rx_skbuff;
 271        dma_addr_t              *tx_dma_addr;
 272        dma_addr_t              *rx_dma_addr;
 273        const struct pcnet32_access *a;
 274        spinlock_t              lock;           /* Guard lock */
 275        unsigned int            cur_rx, cur_tx; /* The next free ring entry */
 276        unsigned int            rx_ring_size;   /* current rx ring size */
 277        unsigned int            tx_ring_size;   /* current tx ring size */
 278        unsigned int            rx_mod_mask;    /* rx ring modular mask */
 279        unsigned int            tx_mod_mask;    /* tx ring modular mask */
 280        unsigned short          rx_len_bits;
 281        unsigned short          tx_len_bits;
 282        dma_addr_t              rx_ring_dma_addr;
 283        dma_addr_t              tx_ring_dma_addr;
 284        unsigned int            dirty_rx,       /* ring entries to be freed. */
 285                                dirty_tx;
 286
 287        struct net_device       *dev;
 288        struct napi_struct      napi;
 289        char                    tx_full;
 290        char                    phycount;       /* number of phys found */
 291        int                     options;
 292        unsigned int            shared_irq:1,   /* shared irq possible */
 293                                dxsuflo:1,   /* disable transmit stop on uflo */
 294                                mii:1;          /* mii port available */
 295        struct net_device       *next;
 296        struct mii_if_info      mii_if;
 297        struct timer_list       watchdog_timer;
 298        u32                     msg_enable;     /* debug message level */
 299
 300        /* each bit indicates an available PHY */
 301        u32                     phymask;
 302        unsigned short          chip_version;   /* which variant this is */
 303
 304        /* saved registers during ethtool blink */
 305        u16                     save_regs[4];
 306};
 307
 308static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *);
 309static int pcnet32_probe1(unsigned long, int, struct pci_dev *);
 310static int pcnet32_open(struct net_device *);
 311static int pcnet32_init_ring(struct net_device *);
 312static netdev_tx_t pcnet32_start_xmit(struct sk_buff *,
 313                                      struct net_device *);
 314static void pcnet32_tx_timeout(struct net_device *dev);
 315static irqreturn_t pcnet32_interrupt(int, void *);
 316static int pcnet32_close(struct net_device *);
 317static struct net_device_stats *pcnet32_get_stats(struct net_device *);
 318static void pcnet32_load_multicast(struct net_device *dev);
 319static void pcnet32_set_multicast_list(struct net_device *);
 320static int pcnet32_ioctl(struct net_device *, struct ifreq *, int);
 321static void pcnet32_watchdog(struct net_device *);
 322static int mdio_read(struct net_device *dev, int phy_id, int reg_num);
 323static void mdio_write(struct net_device *dev, int phy_id, int reg_num,
 324                       int val);
 325static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits);
 326static void pcnet32_ethtool_test(struct net_device *dev,
 327                                 struct ethtool_test *eth_test, u64 * data);
 328static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1);
 329static int pcnet32_get_regs_len(struct net_device *dev);
 330static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
 331                             void *ptr);
 332static void pcnet32_purge_tx_ring(struct net_device *dev);
 333static int pcnet32_alloc_ring(struct net_device *dev, const char *name);
 334static void pcnet32_free_ring(struct net_device *dev);
 335static void pcnet32_check_media(struct net_device *dev, int verbose);
 336
 337static u16 pcnet32_wio_read_csr(unsigned long addr, int index)
 338{
 339        outw(index, addr + PCNET32_WIO_RAP);
 340        return inw(addr + PCNET32_WIO_RDP);
 341}
 342
 343static void pcnet32_wio_write_csr(unsigned long addr, int index, u16 val)
 344{
 345        outw(index, addr + PCNET32_WIO_RAP);
 346        outw(val, addr + PCNET32_WIO_RDP);
 347}
 348
 349static u16 pcnet32_wio_read_bcr(unsigned long addr, int index)
 350{
 351        outw(index, addr + PCNET32_WIO_RAP);
 352        return inw(addr + PCNET32_WIO_BDP);
 353}
 354
 355static void pcnet32_wio_write_bcr(unsigned long addr, int index, u16 val)
 356{
 357        outw(index, addr + PCNET32_WIO_RAP);
 358        outw(val, addr + PCNET32_WIO_BDP);
 359}
 360
 361static u16 pcnet32_wio_read_rap(unsigned long addr)
 362{
 363        return inw(addr + PCNET32_WIO_RAP);
 364}
 365
 366static void pcnet32_wio_write_rap(unsigned long addr, u16 val)
 367{
 368        outw(val, addr + PCNET32_WIO_RAP);
 369}
 370
 371static void pcnet32_wio_reset(unsigned long addr)
 372{
 373        inw(addr + PCNET32_WIO_RESET);
 374}
 375
 376static int pcnet32_wio_check(unsigned long addr)
 377{
 378        outw(88, addr + PCNET32_WIO_RAP);
 379        return inw(addr + PCNET32_WIO_RAP) == 88;
 380}
 381
 382static const struct pcnet32_access pcnet32_wio = {
 383        .read_csr = pcnet32_wio_read_csr,
 384        .write_csr = pcnet32_wio_write_csr,
 385        .read_bcr = pcnet32_wio_read_bcr,
 386        .write_bcr = pcnet32_wio_write_bcr,
 387        .read_rap = pcnet32_wio_read_rap,
 388        .write_rap = pcnet32_wio_write_rap,
 389        .reset = pcnet32_wio_reset
 390};
 391
 392static u16 pcnet32_dwio_read_csr(unsigned long addr, int index)
 393{
 394        outl(index, addr + PCNET32_DWIO_RAP);
 395        return inl(addr + PCNET32_DWIO_RDP) & 0xffff;
 396}
 397
 398static void pcnet32_dwio_write_csr(unsigned long addr, int index, u16 val)
 399{
 400        outl(index, addr + PCNET32_DWIO_RAP);
 401        outl(val, addr + PCNET32_DWIO_RDP);
 402}
 403
 404static u16 pcnet32_dwio_read_bcr(unsigned long addr, int index)
 405{
 406        outl(index, addr + PCNET32_DWIO_RAP);
 407        return inl(addr + PCNET32_DWIO_BDP) & 0xffff;
 408}
 409
 410static void pcnet32_dwio_write_bcr(unsigned long addr, int index, u16 val)
 411{
 412        outl(index, addr + PCNET32_DWIO_RAP);
 413        outl(val, addr + PCNET32_DWIO_BDP);
 414}
 415
 416static u16 pcnet32_dwio_read_rap(unsigned long addr)
 417{
 418        return inl(addr + PCNET32_DWIO_RAP) & 0xffff;
 419}
 420
 421static void pcnet32_dwio_write_rap(unsigned long addr, u16 val)
 422{
 423        outl(val, addr + PCNET32_DWIO_RAP);
 424}
 425
 426static void pcnet32_dwio_reset(unsigned long addr)
 427{
 428        inl(addr + PCNET32_DWIO_RESET);
 429}
 430
 431static int pcnet32_dwio_check(unsigned long addr)
 432{
 433        outl(88, addr + PCNET32_DWIO_RAP);
 434        return (inl(addr + PCNET32_DWIO_RAP) & 0xffff) == 88;
 435}
 436
 437static const struct pcnet32_access pcnet32_dwio = {
 438        .read_csr = pcnet32_dwio_read_csr,
 439        .write_csr = pcnet32_dwio_write_csr,
 440        .read_bcr = pcnet32_dwio_read_bcr,
 441        .write_bcr = pcnet32_dwio_write_bcr,
 442        .read_rap = pcnet32_dwio_read_rap,
 443        .write_rap = pcnet32_dwio_write_rap,
 444        .reset = pcnet32_dwio_reset
 445};
 446
 447static void pcnet32_netif_stop(struct net_device *dev)
 448{
 449        struct pcnet32_private *lp = netdev_priv(dev);
 450
 451        netif_trans_update(dev); /* prevent tx timeout */
 452        napi_disable(&lp->napi);
 453        netif_tx_disable(dev);
 454}
 455
 456static void pcnet32_netif_start(struct net_device *dev)
 457{
 458        struct pcnet32_private *lp = netdev_priv(dev);
 459        ulong ioaddr = dev->base_addr;
 460        u16 val;
 461
 462        netif_wake_queue(dev);
 463        val = lp->a->read_csr(ioaddr, CSR3);
 464        val &= 0x00ff;
 465        lp->a->write_csr(ioaddr, CSR3, val);
 466        napi_enable(&lp->napi);
 467}
 468
 469/*
 470 * Allocate space for the new sized tx ring.
 471 * Free old resources
 472 * Save new resources.
 473 * Any failure keeps old resources.
 474 * Must be called with lp->lock held.
 475 */
 476static void pcnet32_realloc_tx_ring(struct net_device *dev,
 477                                    struct pcnet32_private *lp,
 478                                    unsigned int size)
 479{
 480        dma_addr_t new_ring_dma_addr;
 481        dma_addr_t *new_dma_addr_list;
 482        struct pcnet32_tx_head *new_tx_ring;
 483        struct sk_buff **new_skb_list;
 484        unsigned int entries = BIT(size);
 485
 486        pcnet32_purge_tx_ring(dev);
 487
 488        new_tx_ring =
 489                pci_zalloc_consistent(lp->pci_dev,
 490                                      sizeof(struct pcnet32_tx_head) * entries,
 491                                      &new_ring_dma_addr);
 492        if (new_tx_ring == NULL)
 493                return;
 494
 495        new_dma_addr_list = kcalloc(entries, sizeof(dma_addr_t), GFP_ATOMIC);
 496        if (!new_dma_addr_list)
 497                goto free_new_tx_ring;
 498
 499        new_skb_list = kcalloc(entries, sizeof(struct sk_buff *), GFP_ATOMIC);
 500        if (!new_skb_list)
 501                goto free_new_lists;
 502
 503        kfree(lp->tx_skbuff);
 504        kfree(lp->tx_dma_addr);
 505        pci_free_consistent(lp->pci_dev,
 506                            sizeof(struct pcnet32_tx_head) * lp->tx_ring_size,
 507                            lp->tx_ring, lp->tx_ring_dma_addr);
 508
 509        lp->tx_ring_size = entries;
 510        lp->tx_mod_mask = lp->tx_ring_size - 1;
 511        lp->tx_len_bits = (size << 12);
 512        lp->tx_ring = new_tx_ring;
 513        lp->tx_ring_dma_addr = new_ring_dma_addr;
 514        lp->tx_dma_addr = new_dma_addr_list;
 515        lp->tx_skbuff = new_skb_list;
 516        return;
 517
 518free_new_lists:
 519        kfree(new_dma_addr_list);
 520free_new_tx_ring:
 521        pci_free_consistent(lp->pci_dev,
 522                            sizeof(struct pcnet32_tx_head) * entries,
 523                            new_tx_ring,
 524                            new_ring_dma_addr);
 525}
 526
 527/*
 528 * Allocate space for the new sized rx ring.
 529 * Re-use old receive buffers.
 530 *   alloc extra buffers
 531 *   free unneeded buffers
 532 *   free unneeded buffers
 533 * Save new resources.
 534 * Any failure keeps old resources.
 535 * Must be called with lp->lock held.
 536 */
 537static void pcnet32_realloc_rx_ring(struct net_device *dev,
 538                                    struct pcnet32_private *lp,
 539                                    unsigned int size)
 540{
 541        dma_addr_t new_ring_dma_addr;
 542        dma_addr_t *new_dma_addr_list;
 543        struct pcnet32_rx_head *new_rx_ring;
 544        struct sk_buff **new_skb_list;
 545        int new, overlap;
 546        unsigned int entries = BIT(size);
 547
 548        new_rx_ring =
 549                pci_zalloc_consistent(lp->pci_dev,
 550                                      sizeof(struct pcnet32_rx_head) * entries,
 551                                      &new_ring_dma_addr);
 552        if (new_rx_ring == NULL)
 553                return;
 554
 555        new_dma_addr_list = kcalloc(entries, sizeof(dma_addr_t), GFP_ATOMIC);
 556        if (!new_dma_addr_list)
 557                goto free_new_rx_ring;
 558
 559        new_skb_list = kcalloc(entries, sizeof(struct sk_buff *), GFP_ATOMIC);
 560        if (!new_skb_list)
 561                goto free_new_lists;
 562
 563        /* first copy the current receive buffers */
 564        overlap = min(entries, lp->rx_ring_size);
 565        for (new = 0; new < overlap; new++) {
 566                new_rx_ring[new] = lp->rx_ring[new];
 567                new_dma_addr_list[new] = lp->rx_dma_addr[new];
 568                new_skb_list[new] = lp->rx_skbuff[new];
 569        }
 570        /* now allocate any new buffers needed */
 571        for (; new < entries; new++) {
 572                struct sk_buff *rx_skbuff;
 573                new_skb_list[new] = netdev_alloc_skb(dev, PKT_BUF_SKB);
 574                rx_skbuff = new_skb_list[new];
 575                if (!rx_skbuff) {
 576                        /* keep the original lists and buffers */
 577                        netif_err(lp, drv, dev, "%s netdev_alloc_skb failed\n",
 578                                  __func__);
 579                        goto free_all_new;
 580                }
 581                skb_reserve(rx_skbuff, NET_IP_ALIGN);
 582
 583                new_dma_addr_list[new] =
 584                            pci_map_single(lp->pci_dev, rx_skbuff->data,
 585                                           PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
 586                if (pci_dma_mapping_error(lp->pci_dev,
 587                                          new_dma_addr_list[new])) {
 588                        netif_err(lp, drv, dev, "%s dma mapping failed\n",
 589                                  __func__);
 590                        dev_kfree_skb(new_skb_list[new]);
 591                        goto free_all_new;
 592                }
 593                new_rx_ring[new].base = cpu_to_le32(new_dma_addr_list[new]);
 594                new_rx_ring[new].buf_length = cpu_to_le16(NEG_BUF_SIZE);
 595                new_rx_ring[new].status = cpu_to_le16(0x8000);
 596        }
 597        /* and free any unneeded buffers */
 598        for (; new < lp->rx_ring_size; new++) {
 599                if (lp->rx_skbuff[new]) {
 600                        if (!pci_dma_mapping_error(lp->pci_dev,
 601                                                   lp->rx_dma_addr[new]))
 602                                pci_unmap_single(lp->pci_dev,
 603                                                 lp->rx_dma_addr[new],
 604                                                 PKT_BUF_SIZE,
 605                                                 PCI_DMA_FROMDEVICE);
 606                        dev_kfree_skb(lp->rx_skbuff[new]);
 607                }
 608        }
 609
 610        kfree(lp->rx_skbuff);
 611        kfree(lp->rx_dma_addr);
 612        pci_free_consistent(lp->pci_dev,
 613                            sizeof(struct pcnet32_rx_head) *
 614                            lp->rx_ring_size, lp->rx_ring,
 615                            lp->rx_ring_dma_addr);
 616
 617        lp->rx_ring_size = entries;
 618        lp->rx_mod_mask = lp->rx_ring_size - 1;
 619        lp->rx_len_bits = (size << 4);
 620        lp->rx_ring = new_rx_ring;
 621        lp->rx_ring_dma_addr = new_ring_dma_addr;
 622        lp->rx_dma_addr = new_dma_addr_list;
 623        lp->rx_skbuff = new_skb_list;
 624        return;
 625
 626free_all_new:
 627        while (--new >= lp->rx_ring_size) {
 628                if (new_skb_list[new]) {
 629                        if (!pci_dma_mapping_error(lp->pci_dev,
 630                                                   new_dma_addr_list[new]))
 631                                pci_unmap_single(lp->pci_dev,
 632                                                 new_dma_addr_list[new],
 633                                                 PKT_BUF_SIZE,
 634                                                 PCI_DMA_FROMDEVICE);
 635                        dev_kfree_skb(new_skb_list[new]);
 636                }
 637        }
 638        kfree(new_skb_list);
 639free_new_lists:
 640        kfree(new_dma_addr_list);
 641free_new_rx_ring:
 642        pci_free_consistent(lp->pci_dev,
 643                            sizeof(struct pcnet32_rx_head) * entries,
 644                            new_rx_ring,
 645                            new_ring_dma_addr);
 646}
 647
 648static void pcnet32_purge_rx_ring(struct net_device *dev)
 649{
 650        struct pcnet32_private *lp = netdev_priv(dev);
 651        int i;
 652
 653        /* free all allocated skbuffs */
 654        for (i = 0; i < lp->rx_ring_size; i++) {
 655                lp->rx_ring[i].status = 0;      /* CPU owns buffer */
 656                wmb();          /* Make sure adapter sees owner change */
 657                if (lp->rx_skbuff[i]) {
 658                        if (!pci_dma_mapping_error(lp->pci_dev,
 659                                                   lp->rx_dma_addr[i]))
 660                                pci_unmap_single(lp->pci_dev,
 661                                                 lp->rx_dma_addr[i],
 662                                                 PKT_BUF_SIZE,
 663                                                 PCI_DMA_FROMDEVICE);
 664                        dev_kfree_skb_any(lp->rx_skbuff[i]);
 665                }
 666                lp->rx_skbuff[i] = NULL;
 667                lp->rx_dma_addr[i] = 0;
 668        }
 669}
 670
 671#ifdef CONFIG_NET_POLL_CONTROLLER
 672static void pcnet32_poll_controller(struct net_device *dev)
 673{
 674        disable_irq(dev->irq);
 675        pcnet32_interrupt(0, dev);
 676        enable_irq(dev->irq);
 677}
 678#endif
 679
 680static int pcnet32_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 681{
 682        struct pcnet32_private *lp = netdev_priv(dev);
 683        unsigned long flags;
 684        int r = -EOPNOTSUPP;
 685
 686        if (lp->mii) {
 687                spin_lock_irqsave(&lp->lock, flags);
 688                mii_ethtool_gset(&lp->mii_if, cmd);
 689                spin_unlock_irqrestore(&lp->lock, flags);
 690                r = 0;
 691        }
 692        return r;
 693}
 694
 695static int pcnet32_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 696{
 697        struct pcnet32_private *lp = netdev_priv(dev);
 698        unsigned long flags;
 699        int r = -EOPNOTSUPP;
 700
 701        if (lp->mii) {
 702                spin_lock_irqsave(&lp->lock, flags);
 703                r = mii_ethtool_sset(&lp->mii_if, cmd);
 704                spin_unlock_irqrestore(&lp->lock, flags);
 705        }
 706        return r;
 707}
 708
 709static void pcnet32_get_drvinfo(struct net_device *dev,
 710                                struct ethtool_drvinfo *info)
 711{
 712        struct pcnet32_private *lp = netdev_priv(dev);
 713
 714        strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
 715        strlcpy(info->version, DRV_VERSION, sizeof(info->version));
 716        if (lp->pci_dev)
 717                strlcpy(info->bus_info, pci_name(lp->pci_dev),
 718                        sizeof(info->bus_info));
 719        else
 720                snprintf(info->bus_info, sizeof(info->bus_info),
 721                        "VLB 0x%lx", dev->base_addr);
 722}
 723
 724static u32 pcnet32_get_link(struct net_device *dev)
 725{
 726        struct pcnet32_private *lp = netdev_priv(dev);
 727        unsigned long flags;
 728        int r;
 729
 730        spin_lock_irqsave(&lp->lock, flags);
 731        if (lp->mii) {
 732                r = mii_link_ok(&lp->mii_if);
 733        } else if (lp->chip_version >= PCNET32_79C970A) {
 734                ulong ioaddr = dev->base_addr;  /* card base I/O address */
 735                r = (lp->a->read_bcr(ioaddr, 4) != 0xc0);
 736        } else {        /* can not detect link on really old chips */
 737                r = 1;
 738        }
 739        spin_unlock_irqrestore(&lp->lock, flags);
 740
 741        return r;
 742}
 743
 744static u32 pcnet32_get_msglevel(struct net_device *dev)
 745{
 746        struct pcnet32_private *lp = netdev_priv(dev);
 747        return lp->msg_enable;
 748}
 749
 750static void pcnet32_set_msglevel(struct net_device *dev, u32 value)
 751{
 752        struct pcnet32_private *lp = netdev_priv(dev);
 753        lp->msg_enable = value;
 754}
 755
 756static int pcnet32_nway_reset(struct net_device *dev)
 757{
 758        struct pcnet32_private *lp = netdev_priv(dev);
 759        unsigned long flags;
 760        int r = -EOPNOTSUPP;
 761
 762        if (lp->mii) {
 763                spin_lock_irqsave(&lp->lock, flags);
 764                r = mii_nway_restart(&lp->mii_if);
 765                spin_unlock_irqrestore(&lp->lock, flags);
 766        }
 767        return r;
 768}
 769
 770static void pcnet32_get_ringparam(struct net_device *dev,
 771                                  struct ethtool_ringparam *ering)
 772{
 773        struct pcnet32_private *lp = netdev_priv(dev);
 774
 775        ering->tx_max_pending = TX_MAX_RING_SIZE;
 776        ering->tx_pending = lp->tx_ring_size;
 777        ering->rx_max_pending = RX_MAX_RING_SIZE;
 778        ering->rx_pending = lp->rx_ring_size;
 779}
 780
 781static int pcnet32_set_ringparam(struct net_device *dev,
 782                                 struct ethtool_ringparam *ering)
 783{
 784        struct pcnet32_private *lp = netdev_priv(dev);
 785        unsigned long flags;
 786        unsigned int size;
 787        ulong ioaddr = dev->base_addr;
 788        int i;
 789
 790        if (ering->rx_mini_pending || ering->rx_jumbo_pending)
 791                return -EINVAL;
 792
 793        if (netif_running(dev))
 794                pcnet32_netif_stop(dev);
 795
 796        spin_lock_irqsave(&lp->lock, flags);
 797        lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);      /* stop the chip */
 798
 799        size = min(ering->tx_pending, (unsigned int)TX_MAX_RING_SIZE);
 800
 801        /* set the minimum ring size to 4, to allow the loopback test to work
 802         * unchanged.
 803         */
 804        for (i = 2; i <= PCNET32_LOG_MAX_TX_BUFFERS; i++) {
 805                if (size <= (1 << i))
 806                        break;
 807        }
 808        if ((1 << i) != lp->tx_ring_size)
 809                pcnet32_realloc_tx_ring(dev, lp, i);
 810
 811        size = min(ering->rx_pending, (unsigned int)RX_MAX_RING_SIZE);
 812        for (i = 2; i <= PCNET32_LOG_MAX_RX_BUFFERS; i++) {
 813                if (size <= (1 << i))
 814                        break;
 815        }
 816        if ((1 << i) != lp->rx_ring_size)
 817                pcnet32_realloc_rx_ring(dev, lp, i);
 818
 819        lp->napi.weight = lp->rx_ring_size / 2;
 820
 821        if (netif_running(dev)) {
 822                pcnet32_netif_start(dev);
 823                pcnet32_restart(dev, CSR0_NORMAL);
 824        }
 825
 826        spin_unlock_irqrestore(&lp->lock, flags);
 827
 828        netif_info(lp, drv, dev, "Ring Param Settings: RX: %d, TX: %d\n",
 829                   lp->rx_ring_size, lp->tx_ring_size);
 830
 831        return 0;
 832}
 833
 834static void pcnet32_get_strings(struct net_device *dev, u32 stringset,
 835                                u8 *data)
 836{
 837        memcpy(data, pcnet32_gstrings_test, sizeof(pcnet32_gstrings_test));
 838}
 839
 840static int pcnet32_get_sset_count(struct net_device *dev, int sset)
 841{
 842        switch (sset) {
 843        case ETH_SS_TEST:
 844                return PCNET32_TEST_LEN;
 845        default:
 846                return -EOPNOTSUPP;
 847        }
 848}
 849
 850static void pcnet32_ethtool_test(struct net_device *dev,
 851                                 struct ethtool_test *test, u64 * data)
 852{
 853        struct pcnet32_private *lp = netdev_priv(dev);
 854        int rc;
 855
 856        if (test->flags == ETH_TEST_FL_OFFLINE) {
 857                rc = pcnet32_loopback_test(dev, data);
 858                if (rc) {
 859                        netif_printk(lp, hw, KERN_DEBUG, dev,
 860                                     "Loopback test failed\n");
 861                        test->flags |= ETH_TEST_FL_FAILED;
 862                } else
 863                        netif_printk(lp, hw, KERN_DEBUG, dev,
 864                                     "Loopback test passed\n");
 865        } else
 866                netif_printk(lp, hw, KERN_DEBUG, dev,
 867                             "No tests to run (specify 'Offline' on ethtool)\n");
 868}                               /* end pcnet32_ethtool_test */
 869
 870static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1)
 871{
 872        struct pcnet32_private *lp = netdev_priv(dev);
 873        const struct pcnet32_access *a = lp->a; /* access to registers */
 874        ulong ioaddr = dev->base_addr;  /* card base I/O address */
 875        struct sk_buff *skb;    /* sk buff */
 876        int x, i;               /* counters */
 877        int numbuffs = 4;       /* number of TX/RX buffers and descs */
 878        u16 status = 0x8300;    /* TX ring status */
 879        __le16 teststatus;      /* test of ring status */
 880        int rc;                 /* return code */
 881        int size;               /* size of packets */
 882        unsigned char *packet;  /* source packet data */
 883        static const int data_len = 60; /* length of source packets */
 884        unsigned long flags;
 885        unsigned long ticks;
 886
 887        rc = 1;                 /* default to fail */
 888
 889        if (netif_running(dev))
 890                pcnet32_netif_stop(dev);
 891
 892        spin_lock_irqsave(&lp->lock, flags);
 893        lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);      /* stop the chip */
 894
 895        numbuffs = min(numbuffs, (int)min(lp->rx_ring_size, lp->tx_ring_size));
 896
 897        /* Reset the PCNET32 */
 898        lp->a->reset(ioaddr);
 899        lp->a->write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
 900
 901        /* switch pcnet32 to 32bit mode */
 902        lp->a->write_bcr(ioaddr, 20, 2);
 903
 904        /* purge & init rings but don't actually restart */
 905        pcnet32_restart(dev, 0x0000);
 906
 907        lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);      /* Set STOP bit */
 908
 909        /* Initialize Transmit buffers. */
 910        size = data_len + 15;
 911        for (x = 0; x < numbuffs; x++) {
 912                skb = netdev_alloc_skb(dev, size);
 913                if (!skb) {
 914                        netif_printk(lp, hw, KERN_DEBUG, dev,
 915                                     "Cannot allocate skb at line: %d!\n",
 916                                     __LINE__);
 917                        goto clean_up;
 918                }
 919                packet = skb->data;
 920                skb_put(skb, size);     /* create space for data */
 921                lp->tx_skbuff[x] = skb;
 922                lp->tx_ring[x].length = cpu_to_le16(-skb->len);
 923                lp->tx_ring[x].misc = 0;
 924
 925                /* put DA and SA into the skb */
 926                for (i = 0; i < 6; i++)
 927                        *packet++ = dev->dev_addr[i];
 928                for (i = 0; i < 6; i++)
 929                        *packet++ = dev->dev_addr[i];
 930                /* type */
 931                *packet++ = 0x08;
 932                *packet++ = 0x06;
 933                /* packet number */
 934                *packet++ = x;
 935                /* fill packet with data */
 936                for (i = 0; i < data_len; i++)
 937                        *packet++ = i;
 938
 939                lp->tx_dma_addr[x] =
 940                        pci_map_single(lp->pci_dev, skb->data, skb->len,
 941                                       PCI_DMA_TODEVICE);
 942                if (pci_dma_mapping_error(lp->pci_dev, lp->tx_dma_addr[x])) {
 943                        netif_printk(lp, hw, KERN_DEBUG, dev,
 944                                     "DMA mapping error at line: %d!\n",
 945                                     __LINE__);
 946                        goto clean_up;
 947                }
 948                lp->tx_ring[x].base = cpu_to_le32(lp->tx_dma_addr[x]);
 949                wmb();  /* Make sure owner changes after all others are visible */
 950                lp->tx_ring[x].status = cpu_to_le16(status);
 951        }
 952
 953        x = a->read_bcr(ioaddr, 32);    /* set internal loopback in BCR32 */
 954        a->write_bcr(ioaddr, 32, x | 0x0002);
 955
 956        /* set int loopback in CSR15 */
 957        x = a->read_csr(ioaddr, CSR15) & 0xfffc;
 958        lp->a->write_csr(ioaddr, CSR15, x | 0x0044);
 959
 960        teststatus = cpu_to_le16(0x8000);
 961        lp->a->write_csr(ioaddr, CSR0, CSR0_START);     /* Set STRT bit */
 962
 963        /* Check status of descriptors */
 964        for (x = 0; x < numbuffs; x++) {
 965                ticks = 0;
 966                rmb();
 967                while ((lp->rx_ring[x].status & teststatus) && (ticks < 200)) {
 968                        spin_unlock_irqrestore(&lp->lock, flags);
 969                        msleep(1);
 970                        spin_lock_irqsave(&lp->lock, flags);
 971                        rmb();
 972                        ticks++;
 973                }
 974                if (ticks == 200) {
 975                        netif_err(lp, hw, dev, "Desc %d failed to reset!\n", x);
 976                        break;
 977                }
 978        }
 979
 980        lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);      /* Set STOP bit */
 981        wmb();
 982        if (netif_msg_hw(lp) && netif_msg_pktdata(lp)) {
 983                netdev_printk(KERN_DEBUG, dev, "RX loopback packets:\n");
 984
 985                for (x = 0; x < numbuffs; x++) {
 986                        netdev_printk(KERN_DEBUG, dev, "Packet %d: ", x);
 987                        skb = lp->rx_skbuff[x];
 988                        for (i = 0; i < size; i++)
 989                                pr_cont(" %02x", *(skb->data + i));
 990                        pr_cont("\n");
 991                }
 992        }
 993
 994        x = 0;
 995        rc = 0;
 996        while (x < numbuffs && !rc) {
 997                skb = lp->rx_skbuff[x];
 998                packet = lp->tx_skbuff[x]->data;
 999                for (i = 0; i < size; i++) {
1000                        if (*(skb->data + i) != packet[i]) {
1001                                netif_printk(lp, hw, KERN_DEBUG, dev,
1002                                             "Error in compare! %2x - %02x %02x\n",
1003                                             i, *(skb->data + i), packet[i]);
1004                                rc = 1;
1005                                break;
1006                        }
1007                }
1008                x++;
1009        }
1010
1011clean_up:
1012        *data1 = rc;
1013        pcnet32_purge_tx_ring(dev);
1014
1015        x = a->read_csr(ioaddr, CSR15);
1016        a->write_csr(ioaddr, CSR15, (x & ~0x0044));     /* reset bits 6 and 2 */
1017
1018        x = a->read_bcr(ioaddr, 32);    /* reset internal loopback */
1019        a->write_bcr(ioaddr, 32, (x & ~0x0002));
1020
1021        if (netif_running(dev)) {
1022                pcnet32_netif_start(dev);
1023                pcnet32_restart(dev, CSR0_NORMAL);
1024        } else {
1025                pcnet32_purge_rx_ring(dev);
1026                lp->a->write_bcr(ioaddr, 20, 4);        /* return to 16bit mode */
1027        }
1028        spin_unlock_irqrestore(&lp->lock, flags);
1029
1030        return rc;
1031}                               /* end pcnet32_loopback_test  */
1032
1033static int pcnet32_set_phys_id(struct net_device *dev,
1034                               enum ethtool_phys_id_state state)
1035{
1036        struct pcnet32_private *lp = netdev_priv(dev);
1037        const struct pcnet32_access *a = lp->a;
1038        ulong ioaddr = dev->base_addr;
1039        unsigned long flags;
1040        int i;
1041
1042        switch (state) {
1043        case ETHTOOL_ID_ACTIVE:
1044                /* Save the current value of the bcrs */
1045                spin_lock_irqsave(&lp->lock, flags);
1046                for (i = 4; i < 8; i++)
1047                        lp->save_regs[i - 4] = a->read_bcr(ioaddr, i);
1048                spin_unlock_irqrestore(&lp->lock, flags);
1049                return 2;       /* cycle on/off twice per second */
1050
1051        case ETHTOOL_ID_ON:
1052        case ETHTOOL_ID_OFF:
1053                /* Blink the led */
1054                spin_lock_irqsave(&lp->lock, flags);
1055                for (i = 4; i < 8; i++)
1056                        a->write_bcr(ioaddr, i, a->read_bcr(ioaddr, i) ^ 0x4000);
1057                spin_unlock_irqrestore(&lp->lock, flags);
1058                break;
1059
1060        case ETHTOOL_ID_INACTIVE:
1061                /* Restore the original value of the bcrs */
1062                spin_lock_irqsave(&lp->lock, flags);
1063                for (i = 4; i < 8; i++)
1064                        a->write_bcr(ioaddr, i, lp->save_regs[i - 4]);
1065                spin_unlock_irqrestore(&lp->lock, flags);
1066        }
1067        return 0;
1068}
1069
1070/*
1071 * lp->lock must be held.
1072 */
1073static int pcnet32_suspend(struct net_device *dev, unsigned long *flags,
1074                int can_sleep)
1075{
1076        int csr5;
1077        struct pcnet32_private *lp = netdev_priv(dev);
1078        const struct pcnet32_access *a = lp->a;
1079        ulong ioaddr = dev->base_addr;
1080        int ticks;
1081
1082        /* really old chips have to be stopped. */
1083        if (lp->chip_version < PCNET32_79C970A)
1084                return 0;
1085
1086        /* set SUSPEND (SPND) - CSR5 bit 0 */
1087        csr5 = a->read_csr(ioaddr, CSR5);
1088        a->write_csr(ioaddr, CSR5, csr5 | CSR5_SUSPEND);
1089
1090        /* poll waiting for bit to be set */
1091        ticks = 0;
1092        while (!(a->read_csr(ioaddr, CSR5) & CSR5_SUSPEND)) {
1093                spin_unlock_irqrestore(&lp->lock, *flags);
1094                if (can_sleep)
1095                        msleep(1);
1096                else
1097                        mdelay(1);
1098                spin_lock_irqsave(&lp->lock, *flags);
1099                ticks++;
1100                if (ticks > 200) {
1101                        netif_printk(lp, hw, KERN_DEBUG, dev,
1102                                     "Error getting into suspend!\n");
1103                        return 0;
1104                }
1105        }
1106        return 1;
1107}
1108
1109/*
1110 * process one receive descriptor entry
1111 */
1112
1113static void pcnet32_rx_entry(struct net_device *dev,
1114                             struct pcnet32_private *lp,
1115                             struct pcnet32_rx_head *rxp,
1116                             int entry)
1117{
1118        int status = (short)le16_to_cpu(rxp->status) >> 8;
1119        int rx_in_place = 0;
1120        struct sk_buff *skb;
1121        short pkt_len;
1122
1123        if (status != 0x03) {   /* There was an error. */
1124                /*
1125                 * There is a tricky error noted by John Murphy,
1126                 * <murf@perftech.com> to Russ Nelson: Even with full-sized
1127                 * buffers it's possible for a jabber packet to use two
1128                 * buffers, with only the last correctly noting the error.
1129                 */
1130                if (status & 0x01)      /* Only count a general error at the */
1131                        dev->stats.rx_errors++; /* end of a packet. */
1132                if (status & 0x20)
1133                        dev->stats.rx_frame_errors++;
1134                if (status & 0x10)
1135                        dev->stats.rx_over_errors++;
1136                if (status & 0x08)
1137                        dev->stats.rx_crc_errors++;
1138                if (status & 0x04)
1139                        dev->stats.rx_fifo_errors++;
1140                return;
1141        }
1142
1143        pkt_len = (le32_to_cpu(rxp->msg_length) & 0xfff) - 4;
1144
1145        /* Discard oversize frames. */
1146        if (unlikely(pkt_len > PKT_BUF_SIZE)) {
1147                netif_err(lp, drv, dev, "Impossible packet size %d!\n",
1148                          pkt_len);
1149                dev->stats.rx_errors++;
1150                return;
1151        }
1152        if (pkt_len < 60) {
1153                netif_err(lp, rx_err, dev, "Runt packet!\n");
1154                dev->stats.rx_errors++;
1155                return;
1156        }
1157
1158        if (pkt_len > rx_copybreak) {
1159                struct sk_buff *newskb;
1160                dma_addr_t new_dma_addr;
1161
1162                newskb = netdev_alloc_skb(dev, PKT_BUF_SKB);
1163                /*
1164                 * map the new buffer, if mapping fails, drop the packet and
1165                 * reuse the old buffer
1166                 */
1167                if (newskb) {
1168                        skb_reserve(newskb, NET_IP_ALIGN);
1169                        new_dma_addr = pci_map_single(lp->pci_dev,
1170                                                      newskb->data,
1171                                                      PKT_BUF_SIZE,
1172                                                      PCI_DMA_FROMDEVICE);
1173                        if (pci_dma_mapping_error(lp->pci_dev, new_dma_addr)) {
1174                                netif_err(lp, rx_err, dev,
1175                                          "DMA mapping error.\n");
1176                                dev_kfree_skb(newskb);
1177                                skb = NULL;
1178                        } else {
1179                                skb = lp->rx_skbuff[entry];
1180                                pci_unmap_single(lp->pci_dev,
1181                                                 lp->rx_dma_addr[entry],
1182                                                 PKT_BUF_SIZE,
1183                                                 PCI_DMA_FROMDEVICE);
1184                                skb_put(skb, pkt_len);
1185                                lp->rx_skbuff[entry] = newskb;
1186                                lp->rx_dma_addr[entry] = new_dma_addr;
1187                                rxp->base = cpu_to_le32(new_dma_addr);
1188                                rx_in_place = 1;
1189                        }
1190                } else
1191                        skb = NULL;
1192        } else
1193                skb = netdev_alloc_skb(dev, pkt_len + NET_IP_ALIGN);
1194
1195        if (skb == NULL) {
1196                dev->stats.rx_dropped++;
1197                return;
1198        }
1199        if (!rx_in_place) {
1200                skb_reserve(skb, NET_IP_ALIGN);
1201                skb_put(skb, pkt_len);  /* Make room */
1202                pci_dma_sync_single_for_cpu(lp->pci_dev,
1203                                            lp->rx_dma_addr[entry],
1204                                            pkt_len,
1205                                            PCI_DMA_FROMDEVICE);
1206                skb_copy_to_linear_data(skb,
1207                                 (unsigned char *)(lp->rx_skbuff[entry]->data),
1208                                 pkt_len);
1209                pci_dma_sync_single_for_device(lp->pci_dev,
1210                                               lp->rx_dma_addr[entry],
1211                                               pkt_len,
1212                                               PCI_DMA_FROMDEVICE);
1213        }
1214        dev->stats.rx_bytes += skb->len;
1215        skb->protocol = eth_type_trans(skb, dev);
1216        netif_receive_skb(skb);
1217        dev->stats.rx_packets++;
1218}
1219
1220static int pcnet32_rx(struct net_device *dev, int budget)
1221{
1222        struct pcnet32_private *lp = netdev_priv(dev);
1223        int entry = lp->cur_rx & lp->rx_mod_mask;
1224        struct pcnet32_rx_head *rxp = &lp->rx_ring[entry];
1225        int npackets = 0;
1226
1227        /* If we own the next entry, it's a new packet. Send it up. */
1228        while (npackets < budget && (short)le16_to_cpu(rxp->status) >= 0) {
1229                pcnet32_rx_entry(dev, lp, rxp, entry);
1230                npackets += 1;
1231                /*
1232                 * The docs say that the buffer length isn't touched, but Andrew
1233                 * Boyd of QNX reports that some revs of the 79C965 clear it.
1234                 */
1235                rxp->buf_length = cpu_to_le16(NEG_BUF_SIZE);
1236                wmb();  /* Make sure owner changes after others are visible */
1237                rxp->status = cpu_to_le16(0x8000);
1238                entry = (++lp->cur_rx) & lp->rx_mod_mask;
1239                rxp = &lp->rx_ring[entry];
1240        }
1241
1242        return npackets;
1243}
1244
1245static int pcnet32_tx(struct net_device *dev)
1246{
1247        struct pcnet32_private *lp = netdev_priv(dev);
1248        unsigned int dirty_tx = lp->dirty_tx;
1249        int delta;
1250        int must_restart = 0;
1251
1252        while (dirty_tx != lp->cur_tx) {
1253                int entry = dirty_tx & lp->tx_mod_mask;
1254                int status = (short)le16_to_cpu(lp->tx_ring[entry].status);
1255
1256                if (status < 0)
1257                        break;  /* It still hasn't been Txed */
1258
1259                lp->tx_ring[entry].base = 0;
1260
1261                if (status & 0x4000) {
1262                        /* There was a major error, log it. */
1263                        int err_status = le32_to_cpu(lp->tx_ring[entry].misc);
1264                        dev->stats.tx_errors++;
1265                        netif_err(lp, tx_err, dev,
1266                                  "Tx error status=%04x err_status=%08x\n",
1267                                  status, err_status);
1268                        if (err_status & 0x04000000)
1269                                dev->stats.tx_aborted_errors++;
1270                        if (err_status & 0x08000000)
1271                                dev->stats.tx_carrier_errors++;
1272                        if (err_status & 0x10000000)
1273                                dev->stats.tx_window_errors++;
1274#ifndef DO_DXSUFLO
1275                        if (err_status & 0x40000000) {
1276                                dev->stats.tx_fifo_errors++;
1277                                /* Ackk!  On FIFO errors the Tx unit is turned off! */
1278                                /* Remove this verbosity later! */
1279                                netif_err(lp, tx_err, dev, "Tx FIFO error!\n");
1280                                must_restart = 1;
1281                        }
1282#else
1283                        if (err_status & 0x40000000) {
1284                                dev->stats.tx_fifo_errors++;
1285                                if (!lp->dxsuflo) {     /* If controller doesn't recover ... */
1286                                        /* Ackk!  On FIFO errors the Tx unit is turned off! */
1287                                        /* Remove this verbosity later! */
1288                                        netif_err(lp, tx_err, dev, "Tx FIFO error!\n");
1289                                        must_restart = 1;
1290                                }
1291                        }
1292#endif
1293                } else {
1294                        if (status & 0x1800)
1295                                dev->stats.collisions++;
1296                        dev->stats.tx_packets++;
1297                }
1298
1299                /* We must free the original skb */
1300                if (lp->tx_skbuff[entry]) {
1301                        pci_unmap_single(lp->pci_dev,
1302                                         lp->tx_dma_addr[entry],
1303                                         lp->tx_skbuff[entry]->
1304                                         len, PCI_DMA_TODEVICE);
1305                        dev_kfree_skb_any(lp->tx_skbuff[entry]);
1306                        lp->tx_skbuff[entry] = NULL;
1307                        lp->tx_dma_addr[entry] = 0;
1308                }
1309                dirty_tx++;
1310        }
1311
1312        delta = (lp->cur_tx - dirty_tx) & (lp->tx_mod_mask + lp->tx_ring_size);
1313        if (delta > lp->tx_ring_size) {
1314                netif_err(lp, drv, dev, "out-of-sync dirty pointer, %d vs. %d, full=%d\n",
1315                          dirty_tx, lp->cur_tx, lp->tx_full);
1316                dirty_tx += lp->tx_ring_size;
1317                delta -= lp->tx_ring_size;
1318        }
1319
1320        if (lp->tx_full &&
1321            netif_queue_stopped(dev) &&
1322            delta < lp->tx_ring_size - 2) {
1323                /* The ring is no longer full, clear tbusy. */
1324                lp->tx_full = 0;
1325                netif_wake_queue(dev);
1326        }
1327        lp->dirty_tx = dirty_tx;
1328
1329        return must_restart;
1330}
1331
1332static int pcnet32_poll(struct napi_struct *napi, int budget)
1333{
1334        struct pcnet32_private *lp = container_of(napi, struct pcnet32_private, napi);
1335        struct net_device *dev = lp->dev;
1336        unsigned long ioaddr = dev->base_addr;
1337        unsigned long flags;
1338        int work_done;
1339        u16 val;
1340
1341        work_done = pcnet32_rx(dev, budget);
1342
1343        spin_lock_irqsave(&lp->lock, flags);
1344        if (pcnet32_tx(dev)) {
1345                /* reset the chip to clear the error condition, then restart */
1346                lp->a->reset(ioaddr);
1347                lp->a->write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
1348                pcnet32_restart(dev, CSR0_START);
1349                netif_wake_queue(dev);
1350        }
1351        spin_unlock_irqrestore(&lp->lock, flags);
1352
1353        if (work_done < budget) {
1354                spin_lock_irqsave(&lp->lock, flags);
1355
1356                __napi_complete(napi);
1357
1358                /* clear interrupt masks */
1359                val = lp->a->read_csr(ioaddr, CSR3);
1360                val &= 0x00ff;
1361                lp->a->write_csr(ioaddr, CSR3, val);
1362
1363                /* Set interrupt enable. */
1364                lp->a->write_csr(ioaddr, CSR0, CSR0_INTEN);
1365
1366                spin_unlock_irqrestore(&lp->lock, flags);
1367        }
1368        return work_done;
1369}
1370
1371#define PCNET32_REGS_PER_PHY    32
1372#define PCNET32_MAX_PHYS        32
1373static int pcnet32_get_regs_len(struct net_device *dev)
1374{
1375        struct pcnet32_private *lp = netdev_priv(dev);
1376        int j = lp->phycount * PCNET32_REGS_PER_PHY;
1377
1378        return (PCNET32_NUM_REGS + j) * sizeof(u16);
1379}
1380
1381static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1382                             void *ptr)
1383{
1384        int i, csr0;
1385        u16 *buff = ptr;
1386        struct pcnet32_private *lp = netdev_priv(dev);
1387        const struct pcnet32_access *a = lp->a;
1388        ulong ioaddr = dev->base_addr;
1389        unsigned long flags;
1390
1391        spin_lock_irqsave(&lp->lock, flags);
1392
1393        csr0 = a->read_csr(ioaddr, CSR0);
1394        if (!(csr0 & CSR0_STOP))        /* If not stopped */
1395                pcnet32_suspend(dev, &flags, 1);
1396
1397        /* read address PROM */
1398        for (i = 0; i < 16; i += 2)
1399                *buff++ = inw(ioaddr + i);
1400
1401        /* read control and status registers */
1402        for (i = 0; i < 90; i++)
1403                *buff++ = a->read_csr(ioaddr, i);
1404
1405        *buff++ = a->read_csr(ioaddr, 112);
1406        *buff++ = a->read_csr(ioaddr, 114);
1407
1408        /* read bus configuration registers */
1409        for (i = 0; i < 30; i++)
1410                *buff++ = a->read_bcr(ioaddr, i);
1411
1412        *buff++ = 0;            /* skip bcr30 so as not to hang 79C976 */
1413
1414        for (i = 31; i < 36; i++)
1415                *buff++ = a->read_bcr(ioaddr, i);
1416
1417        /* read mii phy registers */
1418        if (lp->mii) {
1419                int j;
1420                for (j = 0; j < PCNET32_MAX_PHYS; j++) {
1421                        if (lp->phymask & (1 << j)) {
1422                                for (i = 0; i < PCNET32_REGS_PER_PHY; i++) {
1423                                        lp->a->write_bcr(ioaddr, 33,
1424                                                        (j << 5) | i);
1425                                        *buff++ = lp->a->read_bcr(ioaddr, 34);
1426                                }
1427                        }
1428                }
1429        }
1430
1431        if (!(csr0 & CSR0_STOP)) {      /* If not stopped */
1432                int csr5;
1433
1434                /* clear SUSPEND (SPND) - CSR5 bit 0 */
1435                csr5 = a->read_csr(ioaddr, CSR5);
1436                a->write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
1437        }
1438
1439        spin_unlock_irqrestore(&lp->lock, flags);
1440}
1441
1442static const struct ethtool_ops pcnet32_ethtool_ops = {
1443        .get_settings           = pcnet32_get_settings,
1444        .set_settings           = pcnet32_set_settings,
1445        .get_drvinfo            = pcnet32_get_drvinfo,
1446        .get_msglevel           = pcnet32_get_msglevel,
1447        .set_msglevel           = pcnet32_set_msglevel,
1448        .nway_reset             = pcnet32_nway_reset,
1449        .get_link               = pcnet32_get_link,
1450        .get_ringparam          = pcnet32_get_ringparam,
1451        .set_ringparam          = pcnet32_set_ringparam,
1452        .get_strings            = pcnet32_get_strings,
1453        .self_test              = pcnet32_ethtool_test,
1454        .set_phys_id            = pcnet32_set_phys_id,
1455        .get_regs_len           = pcnet32_get_regs_len,
1456        .get_regs               = pcnet32_get_regs,
1457        .get_sset_count         = pcnet32_get_sset_count,
1458};
1459
1460/* only probes for non-PCI devices, the rest are handled by
1461 * pci_register_driver via pcnet32_probe_pci */
1462
1463static void pcnet32_probe_vlbus(unsigned int *pcnet32_portlist)
1464{
1465        unsigned int *port, ioaddr;
1466
1467        /* search for PCnet32 VLB cards at known addresses */
1468        for (port = pcnet32_portlist; (ioaddr = *port); port++) {
1469                if (request_region
1470                    (ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_vlbus")) {
1471                        /* check if there is really a pcnet chip on that ioaddr */
1472                        if ((inb(ioaddr + 14) == 0x57) &&
1473                            (inb(ioaddr + 15) == 0x57)) {
1474                                pcnet32_probe1(ioaddr, 0, NULL);
1475                        } else {
1476                                release_region(ioaddr, PCNET32_TOTAL_SIZE);
1477                        }
1478                }
1479        }
1480}
1481
1482static int
1483pcnet32_probe_pci(struct pci_dev *pdev, const struct pci_device_id *ent)
1484{
1485        unsigned long ioaddr;
1486        int err;
1487
1488        err = pci_enable_device(pdev);
1489        if (err < 0) {
1490                if (pcnet32_debug & NETIF_MSG_PROBE)
1491                        pr_err("failed to enable device -- err=%d\n", err);
1492                return err;
1493        }
1494        pci_set_master(pdev);
1495
1496        ioaddr = pci_resource_start(pdev, 0);
1497        if (!ioaddr) {
1498                if (pcnet32_debug & NETIF_MSG_PROBE)
1499                        pr_err("card has no PCI IO resources, aborting\n");
1500                return -ENODEV;
1501        }
1502
1503        err = pci_set_dma_mask(pdev, PCNET32_DMA_MASK);
1504        if (err) {
1505                if (pcnet32_debug & NETIF_MSG_PROBE)
1506                        pr_err("architecture does not support 32bit PCI busmaster DMA\n");
1507                return err;
1508        }
1509        if (!request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_pci")) {
1510                if (pcnet32_debug & NETIF_MSG_PROBE)
1511                        pr_err("io address range already allocated\n");
1512                return -EBUSY;
1513        }
1514
1515        err = pcnet32_probe1(ioaddr, 1, pdev);
1516        if (err < 0)
1517                pci_disable_device(pdev);
1518
1519        return err;
1520}
1521
1522static const struct net_device_ops pcnet32_netdev_ops = {
1523        .ndo_open               = pcnet32_open,
1524        .ndo_stop               = pcnet32_close,
1525        .ndo_start_xmit         = pcnet32_start_xmit,
1526        .ndo_tx_timeout         = pcnet32_tx_timeout,
1527        .ndo_get_stats          = pcnet32_get_stats,
1528        .ndo_set_rx_mode        = pcnet32_set_multicast_list,
1529        .ndo_do_ioctl           = pcnet32_ioctl,
1530        .ndo_change_mtu         = eth_change_mtu,
1531        .ndo_set_mac_address    = eth_mac_addr,
1532        .ndo_validate_addr      = eth_validate_addr,
1533#ifdef CONFIG_NET_POLL_CONTROLLER
1534        .ndo_poll_controller    = pcnet32_poll_controller,
1535#endif
1536};
1537
1538/* pcnet32_probe1
1539 *  Called from both pcnet32_probe_vlbus and pcnet_probe_pci.
1540 *  pdev will be NULL when called from pcnet32_probe_vlbus.
1541 */
1542static int
1543pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev)
1544{
1545        struct pcnet32_private *lp;
1546        int i, media;
1547        int fdx, mii, fset, dxsuflo, sram;
1548        int chip_version;
1549        char *chipname;
1550        struct net_device *dev;
1551        const struct pcnet32_access *a = NULL;
1552        u8 promaddr[ETH_ALEN];
1553        int ret = -ENODEV;
1554
1555        /* reset the chip */
1556        pcnet32_wio_reset(ioaddr);
1557
1558        /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */
1559        if (pcnet32_wio_read_csr(ioaddr, 0) == 4 && pcnet32_wio_check(ioaddr)) {
1560                a = &pcnet32_wio;
1561        } else {
1562                pcnet32_dwio_reset(ioaddr);
1563                if (pcnet32_dwio_read_csr(ioaddr, 0) == 4 &&
1564                    pcnet32_dwio_check(ioaddr)) {
1565                        a = &pcnet32_dwio;
1566                } else {
1567                        if (pcnet32_debug & NETIF_MSG_PROBE)
1568                                pr_err("No access methods\n");
1569                        goto err_release_region;
1570                }
1571        }
1572
1573        chip_version =
1574            a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr, 89) << 16);
1575        if ((pcnet32_debug & NETIF_MSG_PROBE) && (pcnet32_debug & NETIF_MSG_HW))
1576                pr_info("  PCnet chip version is %#x\n", chip_version);
1577        if ((chip_version & 0xfff) != 0x003) {
1578                if (pcnet32_debug & NETIF_MSG_PROBE)
1579                        pr_info("Unsupported chip version\n");
1580                goto err_release_region;
1581        }
1582
1583        /* initialize variables */
1584        fdx = mii = fset = dxsuflo = sram = 0;
1585        chip_version = (chip_version >> 12) & 0xffff;
1586
1587        switch (chip_version) {
1588        case 0x2420:
1589                chipname = "PCnet/PCI 79C970";  /* PCI */
1590                break;
1591        case 0x2430:
1592                if (shared)
1593                        chipname = "PCnet/PCI 79C970";  /* 970 gives the wrong chip id back */
1594                else
1595                        chipname = "PCnet/32 79C965";   /* 486/VL bus */
1596                break;
1597        case 0x2621:
1598                chipname = "PCnet/PCI II 79C970A";      /* PCI */
1599                fdx = 1;
1600                break;
1601        case 0x2623:
1602                chipname = "PCnet/FAST 79C971"; /* PCI */
1603                fdx = 1;
1604                mii = 1;
1605                fset = 1;
1606                break;
1607        case 0x2624:
1608                chipname = "PCnet/FAST+ 79C972";        /* PCI */
1609                fdx = 1;
1610                mii = 1;
1611                fset = 1;
1612                break;
1613        case 0x2625:
1614                chipname = "PCnet/FAST III 79C973";     /* PCI */
1615                fdx = 1;
1616                mii = 1;
1617                sram = 1;
1618                break;
1619        case 0x2626:
1620                chipname = "PCnet/Home 79C978"; /* PCI */
1621                fdx = 1;
1622                /*
1623                 * This is based on specs published at www.amd.com.  This section
1624                 * assumes that a card with a 79C978 wants to go into standard
1625                 * ethernet mode.  The 79C978 can also go into 1Mb HomePNA mode,
1626                 * and the module option homepna=1 can select this instead.
1627                 */
1628                media = a->read_bcr(ioaddr, 49);
1629                media &= ~3;    /* default to 10Mb ethernet */
1630                if (cards_found < MAX_UNITS && homepna[cards_found])
1631                        media |= 1;     /* switch to home wiring mode */
1632                if (pcnet32_debug & NETIF_MSG_PROBE)
1633                        printk(KERN_DEBUG PFX "media set to %sMbit mode\n",
1634                               (media & 1) ? "1" : "10");
1635                a->write_bcr(ioaddr, 49, media);
1636                break;
1637        case 0x2627:
1638                chipname = "PCnet/FAST III 79C975";     /* PCI */
1639                fdx = 1;
1640                mii = 1;
1641                sram = 1;
1642                break;
1643        case 0x2628:
1644                chipname = "PCnet/PRO 79C976";
1645                fdx = 1;
1646                mii = 1;
1647                break;
1648        default:
1649                if (pcnet32_debug & NETIF_MSG_PROBE)
1650                        pr_info("PCnet version %#x, no PCnet32 chip\n",
1651                                chip_version);
1652                goto err_release_region;
1653        }
1654
1655        /*
1656         *  On selected chips turn on the BCR18:NOUFLO bit. This stops transmit
1657         *  starting until the packet is loaded. Strike one for reliability, lose
1658         *  one for latency - although on PCI this isn't a big loss. Older chips
1659         *  have FIFO's smaller than a packet, so you can't do this.
1660         *  Turn on BCR18:BurstRdEn and BCR18:BurstWrEn.
1661         */
1662
1663        if (fset) {
1664                a->write_bcr(ioaddr, 18, (a->read_bcr(ioaddr, 18) | 0x0860));
1665                a->write_csr(ioaddr, 80,
1666                             (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00);
1667                dxsuflo = 1;
1668        }
1669
1670        /*
1671         * The Am79C973/Am79C975 controllers come with 12K of SRAM
1672         * which we can use for the Tx/Rx buffers but most importantly,
1673         * the use of SRAM allow us to use the BCR18:NOUFLO bit to avoid
1674         * Tx fifo underflows.
1675         */
1676        if (sram) {
1677                /*
1678                 * The SRAM is being configured in two steps. First we
1679                 * set the SRAM size in the BCR25:SRAM_SIZE bits. According
1680                 * to the datasheet, each bit corresponds to a 512-byte
1681                 * page so we can have at most 24 pages. The SRAM_SIZE
1682                 * holds the value of the upper 8 bits of the 16-bit SRAM size.
1683                 * The low 8-bits start at 0x00 and end at 0xff. So the
1684                 * address range is from 0x0000 up to 0x17ff. Therefore,
1685                 * the SRAM_SIZE is set to 0x17. The next step is to set
1686                 * the BCR26:SRAM_BND midway through so the Tx and Rx
1687                 * buffers can share the SRAM equally.
1688                 */
1689                a->write_bcr(ioaddr, 25, 0x17);
1690                a->write_bcr(ioaddr, 26, 0xc);
1691                /* And finally enable the NOUFLO bit */
1692                a->write_bcr(ioaddr, 18, a->read_bcr(ioaddr, 18) | (1 << 11));
1693        }
1694
1695        dev = alloc_etherdev(sizeof(*lp));
1696        if (!dev) {
1697                ret = -ENOMEM;
1698                goto err_release_region;
1699        }
1700
1701        if (pdev)
1702                SET_NETDEV_DEV(dev, &pdev->dev);
1703
1704        if (pcnet32_debug & NETIF_MSG_PROBE)
1705                pr_info("%s at %#3lx,", chipname, ioaddr);
1706
1707        /* In most chips, after a chip reset, the ethernet address is read from the
1708         * station address PROM at the base address and programmed into the
1709         * "Physical Address Registers" CSR12-14.
1710         * As a precautionary measure, we read the PROM values and complain if
1711         * they disagree with the CSRs.  If they miscompare, and the PROM addr
1712         * is valid, then the PROM addr is used.
1713         */
1714        for (i = 0; i < 3; i++) {
1715                unsigned int val;
1716                val = a->read_csr(ioaddr, i + 12) & 0x0ffff;
1717                /* There may be endianness issues here. */
1718                dev->dev_addr[2 * i] = val & 0x0ff;
1719                dev->dev_addr[2 * i + 1] = (val >> 8) & 0x0ff;
1720        }
1721
1722        /* read PROM address and compare with CSR address */
1723        for (i = 0; i < ETH_ALEN; i++)
1724                promaddr[i] = inb(ioaddr + i);
1725
1726        if (!ether_addr_equal(promaddr, dev->dev_addr) ||
1727            !is_valid_ether_addr(dev->dev_addr)) {
1728                if (is_valid_ether_addr(promaddr)) {
1729                        if (pcnet32_debug & NETIF_MSG_PROBE) {
1730                                pr_cont(" warning: CSR address invalid,\n");
1731                                pr_info("    using instead PROM address of");
1732                        }
1733                        memcpy(dev->dev_addr, promaddr, ETH_ALEN);
1734                }
1735        }
1736
1737        /* if the ethernet address is not valid, force to 00:00:00:00:00:00 */
1738        if (!is_valid_ether_addr(dev->dev_addr))
1739                eth_zero_addr(dev->dev_addr);
1740
1741        if (pcnet32_debug & NETIF_MSG_PROBE) {
1742                pr_cont(" %pM", dev->dev_addr);
1743
1744                /* Version 0x2623 and 0x2624 */
1745                if (((chip_version + 1) & 0xfffe) == 0x2624) {
1746                        i = a->read_csr(ioaddr, 80) & 0x0C00;   /* Check tx_start_pt */
1747                        pr_info("    tx_start_pt(0x%04x):", i);
1748                        switch (i >> 10) {
1749                        case 0:
1750                                pr_cont("  20 bytes,");
1751                                break;
1752                        case 1:
1753                                pr_cont("  64 bytes,");
1754                                break;
1755                        case 2:
1756                                pr_cont(" 128 bytes,");
1757                                break;
1758                        case 3:
1759                                pr_cont("~220 bytes,");
1760                                break;
1761                        }
1762                        i = a->read_bcr(ioaddr, 18);    /* Check Burst/Bus control */
1763                        pr_cont(" BCR18(%x):", i & 0xffff);
1764                        if (i & (1 << 5))
1765                                pr_cont("BurstWrEn ");
1766                        if (i & (1 << 6))
1767                                pr_cont("BurstRdEn ");
1768                        if (i & (1 << 7))
1769                                pr_cont("DWordIO ");
1770                        if (i & (1 << 11))
1771                                pr_cont("NoUFlow ");
1772                        i = a->read_bcr(ioaddr, 25);
1773                        pr_info("    SRAMSIZE=0x%04x,", i << 8);
1774                        i = a->read_bcr(ioaddr, 26);
1775                        pr_cont(" SRAM_BND=0x%04x,", i << 8);
1776                        i = a->read_bcr(ioaddr, 27);
1777                        if (i & (1 << 14))
1778                                pr_cont("LowLatRx");
1779                }
1780        }
1781
1782        dev->base_addr = ioaddr;
1783        lp = netdev_priv(dev);
1784        /* pci_alloc_consistent returns page-aligned memory, so we do not have to check the alignment */
1785        lp->init_block = pci_alloc_consistent(pdev, sizeof(*lp->init_block),
1786                                              &lp->init_dma_addr);
1787        if (!lp->init_block) {
1788                if (pcnet32_debug & NETIF_MSG_PROBE)
1789                        pr_err("Consistent memory allocation failed\n");
1790                ret = -ENOMEM;
1791                goto err_free_netdev;
1792        }
1793        lp->pci_dev = pdev;
1794
1795        lp->dev = dev;
1796
1797        spin_lock_init(&lp->lock);
1798
1799        lp->name = chipname;
1800        lp->shared_irq = shared;
1801        lp->tx_ring_size = TX_RING_SIZE;        /* default tx ring size */
1802        lp->rx_ring_size = RX_RING_SIZE;        /* default rx ring size */
1803        lp->tx_mod_mask = lp->tx_ring_size - 1;
1804        lp->rx_mod_mask = lp->rx_ring_size - 1;
1805        lp->tx_len_bits = (PCNET32_LOG_TX_BUFFERS << 12);
1806        lp->rx_len_bits = (PCNET32_LOG_RX_BUFFERS << 4);
1807        lp->mii_if.full_duplex = fdx;
1808        lp->mii_if.phy_id_mask = 0x1f;
1809        lp->mii_if.reg_num_mask = 0x1f;
1810        lp->dxsuflo = dxsuflo;
1811        lp->mii = mii;
1812        lp->chip_version = chip_version;
1813        lp->msg_enable = pcnet32_debug;
1814        if ((cards_found >= MAX_UNITS) ||
1815            (options[cards_found] >= sizeof(options_mapping)))
1816                lp->options = PCNET32_PORT_ASEL;
1817        else
1818                lp->options = options_mapping[options[cards_found]];
1819        lp->mii_if.dev = dev;
1820        lp->mii_if.mdio_read = mdio_read;
1821        lp->mii_if.mdio_write = mdio_write;
1822
1823        /* napi.weight is used in both the napi and non-napi cases */
1824        lp->napi.weight = lp->rx_ring_size / 2;
1825
1826        netif_napi_add(dev, &lp->napi, pcnet32_poll, lp->rx_ring_size / 2);
1827
1828        if (fdx && !(lp->options & PCNET32_PORT_ASEL) &&
1829            ((cards_found >= MAX_UNITS) || full_duplex[cards_found]))
1830                lp->options |= PCNET32_PORT_FD;
1831
1832        lp->a = a;
1833
1834        /* prior to register_netdev, dev->name is not yet correct */
1835        if (pcnet32_alloc_ring(dev, pci_name(lp->pci_dev))) {
1836                ret = -ENOMEM;
1837                goto err_free_ring;
1838        }
1839        /* detect special T1/E1 WAN card by checking for MAC address */
1840        if (dev->dev_addr[0] == 0x00 && dev->dev_addr[1] == 0xe0 &&
1841            dev->dev_addr[2] == 0x75)
1842                lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI;
1843
1844        lp->init_block->mode = cpu_to_le16(0x0003);     /* Disable Rx and Tx. */
1845        lp->init_block->tlen_rlen =
1846            cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits);
1847        for (i = 0; i < 6; i++)
1848                lp->init_block->phys_addr[i] = dev->dev_addr[i];
1849        lp->init_block->filter[0] = 0x00000000;
1850        lp->init_block->filter[1] = 0x00000000;
1851        lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr);
1852        lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr);
1853
1854        /* switch pcnet32 to 32bit mode */
1855        a->write_bcr(ioaddr, 20, 2);
1856
1857        a->write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));
1858        a->write_csr(ioaddr, 2, (lp->init_dma_addr >> 16));
1859
1860        if (pdev) {             /* use the IRQ provided by PCI */
1861                dev->irq = pdev->irq;
1862                if (pcnet32_debug & NETIF_MSG_PROBE)
1863                        pr_cont(" assigned IRQ %d\n", dev->irq);
1864        } else {
1865                unsigned long irq_mask = probe_irq_on();
1866
1867                /*
1868                 * To auto-IRQ we enable the initialization-done and DMA error
1869                 * interrupts. For ISA boards we get a DMA error, but VLB and PCI
1870                 * boards will work.
1871                 */
1872                /* Trigger an initialization just for the interrupt. */
1873                a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_INIT);
1874                mdelay(1);
1875
1876                dev->irq = probe_irq_off(irq_mask);
1877                if (!dev->irq) {
1878                        if (pcnet32_debug & NETIF_MSG_PROBE)
1879                                pr_cont(", failed to detect IRQ line\n");
1880                        ret = -ENODEV;
1881                        goto err_free_ring;
1882                }
1883                if (pcnet32_debug & NETIF_MSG_PROBE)
1884                        pr_cont(", probed IRQ %d\n", dev->irq);
1885        }
1886
1887        /* Set the mii phy_id so that we can query the link state */
1888        if (lp->mii) {
1889                /* lp->phycount and lp->phymask are set to 0 by memset above */
1890
1891                lp->mii_if.phy_id = ((lp->a->read_bcr(ioaddr, 33)) >> 5) & 0x1f;
1892                /* scan for PHYs */
1893                for (i = 0; i < PCNET32_MAX_PHYS; i++) {
1894                        unsigned short id1, id2;
1895
1896                        id1 = mdio_read(dev, i, MII_PHYSID1);
1897                        if (id1 == 0xffff)
1898                                continue;
1899                        id2 = mdio_read(dev, i, MII_PHYSID2);
1900                        if (id2 == 0xffff)
1901                                continue;
1902                        if (i == 31 && ((chip_version + 1) & 0xfffe) == 0x2624)
1903                                continue;       /* 79C971 & 79C972 have phantom phy at id 31 */
1904                        lp->phycount++;
1905                        lp->phymask |= (1 << i);
1906                        lp->mii_if.phy_id = i;
1907                        if (pcnet32_debug & NETIF_MSG_PROBE)
1908                                pr_info("Found PHY %04x:%04x at address %d\n",
1909                                        id1, id2, i);
1910                }
1911                lp->a->write_bcr(ioaddr, 33, (lp->mii_if.phy_id) << 5);
1912                if (lp->phycount > 1)
1913                        lp->options |= PCNET32_PORT_MII;
1914        }
1915
1916        init_timer(&lp->watchdog_timer);
1917        lp->watchdog_timer.data = (unsigned long)dev;
1918        lp->watchdog_timer.function = (void *)&pcnet32_watchdog;
1919
1920        /* The PCNET32-specific entries in the device structure. */
1921        dev->netdev_ops = &pcnet32_netdev_ops;
1922        dev->ethtool_ops = &pcnet32_ethtool_ops;
1923        dev->watchdog_timeo = (5 * HZ);
1924
1925        /* Fill in the generic fields of the device structure. */
1926        if (register_netdev(dev))
1927                goto err_free_ring;
1928
1929        if (pdev) {
1930                pci_set_drvdata(pdev, dev);
1931        } else {
1932                lp->next = pcnet32_dev;
1933                pcnet32_dev = dev;
1934        }
1935
1936        if (pcnet32_debug & NETIF_MSG_PROBE)
1937                pr_info("%s: registered as %s\n", dev->name, lp->name);
1938        cards_found++;
1939
1940        /* enable LED writes */
1941        a->write_bcr(ioaddr, 2, a->read_bcr(ioaddr, 2) | 0x1000);
1942
1943        return 0;
1944
1945err_free_ring:
1946        pcnet32_free_ring(dev);
1947        pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
1948                            lp->init_block, lp->init_dma_addr);
1949err_free_netdev:
1950        free_netdev(dev);
1951err_release_region:
1952        release_region(ioaddr, PCNET32_TOTAL_SIZE);
1953        return ret;
1954}
1955
1956/* if any allocation fails, caller must also call pcnet32_free_ring */
1957static int pcnet32_alloc_ring(struct net_device *dev, const char *name)
1958{
1959        struct pcnet32_private *lp = netdev_priv(dev);
1960
1961        lp->tx_ring = pci_alloc_consistent(lp->pci_dev,
1962                                           sizeof(struct pcnet32_tx_head) *
1963                                           lp->tx_ring_size,
1964                                           &lp->tx_ring_dma_addr);
1965        if (lp->tx_ring == NULL) {
1966                netif_err(lp, drv, dev, "Consistent memory allocation failed\n");
1967                return -ENOMEM;
1968        }
1969
1970        lp->rx_ring = pci_alloc_consistent(lp->pci_dev,
1971                                           sizeof(struct pcnet32_rx_head) *
1972                                           lp->rx_ring_size,
1973                                           &lp->rx_ring_dma_addr);
1974        if (lp->rx_ring == NULL) {
1975                netif_err(lp, drv, dev, "Consistent memory allocation failed\n");
1976                return -ENOMEM;
1977        }
1978
1979        lp->tx_dma_addr = kcalloc(lp->tx_ring_size, sizeof(dma_addr_t),
1980                                  GFP_ATOMIC);
1981        if (!lp->tx_dma_addr)
1982                return -ENOMEM;
1983
1984        lp->rx_dma_addr = kcalloc(lp->rx_ring_size, sizeof(dma_addr_t),
1985                                  GFP_ATOMIC);
1986        if (!lp->rx_dma_addr)
1987                return -ENOMEM;
1988
1989        lp->tx_skbuff = kcalloc(lp->tx_ring_size, sizeof(struct sk_buff *),
1990                                GFP_ATOMIC);
1991        if (!lp->tx_skbuff)
1992                return -ENOMEM;
1993
1994        lp->rx_skbuff = kcalloc(lp->rx_ring_size, sizeof(struct sk_buff *),
1995                                GFP_ATOMIC);
1996        if (!lp->rx_skbuff)
1997                return -ENOMEM;
1998
1999        return 0;
2000}
2001
2002static void pcnet32_free_ring(struct net_device *dev)
2003{
2004        struct pcnet32_private *lp = netdev_priv(dev);
2005
2006        kfree(lp->tx_skbuff);
2007        lp->tx_skbuff = NULL;
2008
2009        kfree(lp->rx_skbuff);
2010        lp->rx_skbuff = NULL;
2011
2012        kfree(lp->tx_dma_addr);
2013        lp->tx_dma_addr = NULL;
2014
2015        kfree(lp->rx_dma_addr);
2016        lp->rx_dma_addr = NULL;
2017
2018        if (lp->tx_ring) {
2019                pci_free_consistent(lp->pci_dev,
2020                                    sizeof(struct pcnet32_tx_head) *
2021                                    lp->tx_ring_size, lp->tx_ring,
2022                                    lp->tx_ring_dma_addr);
2023                lp->tx_ring = NULL;
2024        }
2025
2026        if (lp->rx_ring) {
2027                pci_free_consistent(lp->pci_dev,
2028                                    sizeof(struct pcnet32_rx_head) *
2029                                    lp->rx_ring_size, lp->rx_ring,
2030                                    lp->rx_ring_dma_addr);
2031                lp->rx_ring = NULL;
2032        }
2033}
2034
2035static int pcnet32_open(struct net_device *dev)
2036{
2037        struct pcnet32_private *lp = netdev_priv(dev);
2038        struct pci_dev *pdev = lp->pci_dev;
2039        unsigned long ioaddr = dev->base_addr;
2040        u16 val;
2041        int i;
2042        int rc;
2043        unsigned long flags;
2044
2045        if (request_irq(dev->irq, pcnet32_interrupt,
2046                        lp->shared_irq ? IRQF_SHARED : 0, dev->name,
2047                        (void *)dev)) {
2048                return -EAGAIN;
2049        }
2050
2051        spin_lock_irqsave(&lp->lock, flags);
2052        /* Check for a valid station address */
2053        if (!is_valid_ether_addr(dev->dev_addr)) {
2054                rc = -EINVAL;
2055                goto err_free_irq;
2056        }
2057
2058        /* Reset the PCNET32 */
2059        lp->a->reset(ioaddr);
2060
2061        /* switch pcnet32 to 32bit mode */
2062        lp->a->write_bcr(ioaddr, 20, 2);
2063
2064        netif_printk(lp, ifup, KERN_DEBUG, dev,
2065                     "%s() irq %d tx/rx rings %#x/%#x init %#x\n",
2066                     __func__, dev->irq, (u32) (lp->tx_ring_dma_addr),
2067                     (u32) (lp->rx_ring_dma_addr),
2068                     (u32) (lp->init_dma_addr));
2069
2070        /* set/reset autoselect bit */
2071        val = lp->a->read_bcr(ioaddr, 2) & ~2;
2072        if (lp->options & PCNET32_PORT_ASEL)
2073                val |= 2;
2074        lp->a->write_bcr(ioaddr, 2, val);
2075
2076        /* handle full duplex setting */
2077        if (lp->mii_if.full_duplex) {
2078                val = lp->a->read_bcr(ioaddr, 9) & ~3;
2079                if (lp->options & PCNET32_PORT_FD) {
2080                        val |= 1;
2081                        if (lp->options == (PCNET32_PORT_FD | PCNET32_PORT_AUI))
2082                                val |= 2;
2083                } else if (lp->options & PCNET32_PORT_ASEL) {
2084                        /* workaround of xSeries250, turn on for 79C975 only */
2085                        if (lp->chip_version == 0x2627)
2086                                val |= 3;
2087                }
2088                lp->a->write_bcr(ioaddr, 9, val);
2089        }
2090
2091        /* set/reset GPSI bit in test register */
2092        val = lp->a->read_csr(ioaddr, 124) & ~0x10;
2093        if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI)
2094                val |= 0x10;
2095        lp->a->write_csr(ioaddr, 124, val);
2096
2097        /* Allied Telesyn AT 2700/2701 FX are 100Mbit only and do not negotiate */
2098        if (pdev && pdev->subsystem_vendor == PCI_VENDOR_ID_AT &&
2099            (pdev->subsystem_device == PCI_SUBDEVICE_ID_AT_2700FX ||
2100             pdev->subsystem_device == PCI_SUBDEVICE_ID_AT_2701FX)) {
2101                if (lp->options & PCNET32_PORT_ASEL) {
2102                        lp->options = PCNET32_PORT_FD | PCNET32_PORT_100;
2103                        netif_printk(lp, link, KERN_DEBUG, dev,
2104                                     "Setting 100Mb-Full Duplex\n");
2105                }
2106        }
2107        if (lp->phycount < 2) {
2108                /*
2109                 * 24 Jun 2004 according AMD, in order to change the PHY,
2110                 * DANAS (or DISPM for 79C976) must be set; then select the speed,
2111                 * duplex, and/or enable auto negotiation, and clear DANAS
2112                 */
2113                if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) {
2114                        lp->a->write_bcr(ioaddr, 32,
2115                                        lp->a->read_bcr(ioaddr, 32) | 0x0080);
2116                        /* disable Auto Negotiation, set 10Mpbs, HD */
2117                        val = lp->a->read_bcr(ioaddr, 32) & ~0xb8;
2118                        if (lp->options & PCNET32_PORT_FD)
2119                                val |= 0x10;
2120                        if (lp->options & PCNET32_PORT_100)
2121                                val |= 0x08;
2122                        lp->a->write_bcr(ioaddr, 32, val);
2123                } else {
2124                        if (lp->options & PCNET32_PORT_ASEL) {
2125                                lp->a->write_bcr(ioaddr, 32,
2126                                                lp->a->read_bcr(ioaddr,
2127                                                               32) | 0x0080);
2128                                /* enable auto negotiate, setup, disable fd */
2129                                val = lp->a->read_bcr(ioaddr, 32) & ~0x98;
2130                                val |= 0x20;
2131                                lp->a->write_bcr(ioaddr, 32, val);
2132                        }
2133                }
2134        } else {
2135                int first_phy = -1;
2136                u16 bmcr;
2137                u32 bcr9;
2138                struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
2139
2140                /*
2141                 * There is really no good other way to handle multiple PHYs
2142                 * other than turning off all automatics
2143                 */
2144                val = lp->a->read_bcr(ioaddr, 2);
2145                lp->a->write_bcr(ioaddr, 2, val & ~2);
2146                val = lp->a->read_bcr(ioaddr, 32);
2147                lp->a->write_bcr(ioaddr, 32, val & ~(1 << 7));  /* stop MII manager */
2148
2149                if (!(lp->options & PCNET32_PORT_ASEL)) {
2150                        /* setup ecmd */
2151                        ecmd.port = PORT_MII;
2152                        ecmd.transceiver = XCVR_INTERNAL;
2153                        ecmd.autoneg = AUTONEG_DISABLE;
2154                        ethtool_cmd_speed_set(&ecmd,
2155                                              (lp->options & PCNET32_PORT_100) ?
2156                                              SPEED_100 : SPEED_10);
2157                        bcr9 = lp->a->read_bcr(ioaddr, 9);
2158
2159                        if (lp->options & PCNET32_PORT_FD) {
2160                                ecmd.duplex = DUPLEX_FULL;
2161                                bcr9 |= (1 << 0);
2162                        } else {
2163                                ecmd.duplex = DUPLEX_HALF;
2164                                bcr9 |= ~(1 << 0);
2165                        }
2166                        lp->a->write_bcr(ioaddr, 9, bcr9);
2167                }
2168
2169                for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2170                        if (lp->phymask & (1 << i)) {
2171                                /* isolate all but the first PHY */
2172                                bmcr = mdio_read(dev, i, MII_BMCR);
2173                                if (first_phy == -1) {
2174                                        first_phy = i;
2175                                        mdio_write(dev, i, MII_BMCR,
2176                                                   bmcr & ~BMCR_ISOLATE);
2177                                } else {
2178                                        mdio_write(dev, i, MII_BMCR,
2179                                                   bmcr | BMCR_ISOLATE);
2180                                }
2181                                /* use mii_ethtool_sset to setup PHY */
2182                                lp->mii_if.phy_id = i;
2183                                ecmd.phy_address = i;
2184                                if (lp->options & PCNET32_PORT_ASEL) {
2185                                        mii_ethtool_gset(&lp->mii_if, &ecmd);
2186                                        ecmd.autoneg = AUTONEG_ENABLE;
2187                                }
2188                                mii_ethtool_sset(&lp->mii_if, &ecmd);
2189                        }
2190                }
2191                lp->mii_if.phy_id = first_phy;
2192                netif_info(lp, link, dev, "Using PHY number %d\n", first_phy);
2193        }
2194
2195#ifdef DO_DXSUFLO
2196        if (lp->dxsuflo) {      /* Disable transmit stop on underflow */
2197                val = lp->a->read_csr(ioaddr, CSR3);
2198                val |= 0x40;
2199                lp->a->write_csr(ioaddr, CSR3, val);
2200        }
2201#endif
2202
2203        lp->init_block->mode =
2204            cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7);
2205        pcnet32_load_multicast(dev);
2206
2207        if (pcnet32_init_ring(dev)) {
2208                rc = -ENOMEM;
2209                goto err_free_ring;
2210        }
2211
2212        napi_enable(&lp->napi);
2213
2214        /* Re-initialize the PCNET32, and start it when done. */
2215        lp->a->write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));
2216        lp->a->write_csr(ioaddr, 2, (lp->init_dma_addr >> 16));
2217
2218        lp->a->write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
2219        lp->a->write_csr(ioaddr, CSR0, CSR0_INIT);
2220
2221        netif_start_queue(dev);
2222
2223        if (lp->chip_version >= PCNET32_79C970A) {
2224                /* Print the link status and start the watchdog */
2225                pcnet32_check_media(dev, 1);
2226                mod_timer(&lp->watchdog_timer, PCNET32_WATCHDOG_TIMEOUT);
2227        }
2228
2229        i = 0;
2230        while (i++ < 100)
2231                if (lp->a->read_csr(ioaddr, CSR0) & CSR0_IDON)
2232                        break;
2233        /*
2234         * We used to clear the InitDone bit, 0x0100, here but Mark Stockton
2235         * reports that doing so triggers a bug in the '974.
2236         */
2237        lp->a->write_csr(ioaddr, CSR0, CSR0_NORMAL);
2238
2239        netif_printk(lp, ifup, KERN_DEBUG, dev,
2240                     "pcnet32 open after %d ticks, init block %#x csr0 %4.4x\n",
2241                     i,
2242                     (u32) (lp->init_dma_addr),
2243                     lp->a->read_csr(ioaddr, CSR0));
2244
2245        spin_unlock_irqrestore(&lp->lock, flags);
2246
2247        return 0;               /* Always succeed */
2248
2249err_free_ring:
2250        /* free any allocated skbuffs */
2251        pcnet32_purge_rx_ring(dev);
2252
2253        /*
2254         * Switch back to 16bit mode to avoid problems with dumb
2255         * DOS packet driver after a warm reboot
2256         */
2257        lp->a->write_bcr(ioaddr, 20, 4);
2258
2259err_free_irq:
2260        spin_unlock_irqrestore(&lp->lock, flags);
2261        free_irq(dev->irq, dev);
2262        return rc;
2263}
2264
2265/*
2266 * The LANCE has been halted for one reason or another (busmaster memory
2267 * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure,
2268 * etc.).  Modern LANCE variants always reload their ring-buffer
2269 * configuration when restarted, so we must reinitialize our ring
2270 * context before restarting.  As part of this reinitialization,
2271 * find all packets still on the Tx ring and pretend that they had been
2272 * sent (in effect, drop the packets on the floor) - the higher-level
2273 * protocols will time out and retransmit.  It'd be better to shuffle
2274 * these skbs to a temp list and then actually re-Tx them after
2275 * restarting the chip, but I'm too lazy to do so right now.  dplatt@3do.com
2276 */
2277
2278static void pcnet32_purge_tx_ring(struct net_device *dev)
2279{
2280        struct pcnet32_private *lp = netdev_priv(dev);
2281        int i;
2282
2283        for (i = 0; i < lp->tx_ring_size; i++) {
2284                lp->tx_ring[i].status = 0;      /* CPU owns buffer */
2285                wmb();          /* Make sure adapter sees owner change */
2286                if (lp->tx_skbuff[i]) {
2287                        if (!pci_dma_mapping_error(lp->pci_dev,
2288                                                   lp->tx_dma_addr[i]))
2289                                pci_unmap_single(lp->pci_dev,
2290                                                 lp->tx_dma_addr[i],
2291                                                 lp->tx_skbuff[i]->len,
2292                                                 PCI_DMA_TODEVICE);
2293                        dev_kfree_skb_any(lp->tx_skbuff[i]);
2294                }
2295                lp->tx_skbuff[i] = NULL;
2296                lp->tx_dma_addr[i] = 0;
2297        }
2298}
2299
2300/* Initialize the PCNET32 Rx and Tx rings. */
2301static int pcnet32_init_ring(struct net_device *dev)
2302{
2303        struct pcnet32_private *lp = netdev_priv(dev);
2304        int i;
2305
2306        lp->tx_full = 0;
2307        lp->cur_rx = lp->cur_tx = 0;
2308        lp->dirty_rx = lp->dirty_tx = 0;
2309
2310        for (i = 0; i < lp->rx_ring_size; i++) {
2311                struct sk_buff *rx_skbuff = lp->rx_skbuff[i];
2312                if (rx_skbuff == NULL) {
2313                        lp->rx_skbuff[i] = netdev_alloc_skb(dev, PKT_BUF_SKB);
2314                        rx_skbuff = lp->rx_skbuff[i];
2315                        if (!rx_skbuff) {
2316                                /* there is not much we can do at this point */
2317                                netif_err(lp, drv, dev, "%s netdev_alloc_skb failed\n",
2318                                          __func__);
2319                                return -1;
2320                        }
2321                        skb_reserve(rx_skbuff, NET_IP_ALIGN);
2322                }
2323
2324                rmb();
2325                if (lp->rx_dma_addr[i] == 0) {
2326                        lp->rx_dma_addr[i] =
2327                            pci_map_single(lp->pci_dev, rx_skbuff->data,
2328                                           PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
2329                        if (pci_dma_mapping_error(lp->pci_dev,
2330                                                  lp->rx_dma_addr[i])) {
2331                                /* there is not much we can do at this point */
2332                                netif_err(lp, drv, dev,
2333                                          "%s pci dma mapping error\n",
2334                                          __func__);
2335                                return -1;
2336                        }
2337                }
2338                lp->rx_ring[i].base = cpu_to_le32(lp->rx_dma_addr[i]);
2339                lp->rx_ring[i].buf_length = cpu_to_le16(NEG_BUF_SIZE);
2340                wmb();          /* Make sure owner changes after all others are visible */
2341                lp->rx_ring[i].status = cpu_to_le16(0x8000);
2342        }
2343        /* The Tx buffer address is filled in as needed, but we do need to clear
2344         * the upper ownership bit. */
2345        for (i = 0; i < lp->tx_ring_size; i++) {
2346                lp->tx_ring[i].status = 0;      /* CPU owns buffer */
2347                wmb();          /* Make sure adapter sees owner change */
2348                lp->tx_ring[i].base = 0;
2349                lp->tx_dma_addr[i] = 0;
2350        }
2351
2352        lp->init_block->tlen_rlen =
2353            cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits);
2354        for (i = 0; i < 6; i++)
2355                lp->init_block->phys_addr[i] = dev->dev_addr[i];
2356        lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr);
2357        lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr);
2358        wmb();                  /* Make sure all changes are visible */
2359        return 0;
2360}
2361
2362/* the pcnet32 has been issued a stop or reset.  Wait for the stop bit
2363 * then flush the pending transmit operations, re-initialize the ring,
2364 * and tell the chip to initialize.
2365 */
2366static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits)
2367{
2368        struct pcnet32_private *lp = netdev_priv(dev);
2369        unsigned long ioaddr = dev->base_addr;
2370        int i;
2371
2372        /* wait for stop */
2373        for (i = 0; i < 100; i++)
2374                if (lp->a->read_csr(ioaddr, CSR0) & CSR0_STOP)
2375                        break;
2376
2377        if (i >= 100)
2378                netif_err(lp, drv, dev, "%s timed out waiting for stop\n",
2379                          __func__);
2380
2381        pcnet32_purge_tx_ring(dev);
2382        if (pcnet32_init_ring(dev))
2383                return;
2384
2385        /* ReInit Ring */
2386        lp->a->write_csr(ioaddr, CSR0, CSR0_INIT);
2387        i = 0;
2388        while (i++ < 1000)
2389                if (lp->a->read_csr(ioaddr, CSR0) & CSR0_IDON)
2390                        break;
2391
2392        lp->a->write_csr(ioaddr, CSR0, csr0_bits);
2393}
2394
2395static void pcnet32_tx_timeout(struct net_device *dev)
2396{
2397        struct pcnet32_private *lp = netdev_priv(dev);
2398        unsigned long ioaddr = dev->base_addr, flags;
2399
2400        spin_lock_irqsave(&lp->lock, flags);
2401        /* Transmitter timeout, serious problems. */
2402        if (pcnet32_debug & NETIF_MSG_DRV)
2403                pr_err("%s: transmit timed out, status %4.4x, resetting\n",
2404                       dev->name, lp->a->read_csr(ioaddr, CSR0));
2405        lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);
2406        dev->stats.tx_errors++;
2407        if (netif_msg_tx_err(lp)) {
2408                int i;
2409                printk(KERN_DEBUG
2410                       " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.",
2411                       lp->dirty_tx, lp->cur_tx, lp->tx_full ? " (full)" : "",
2412                       lp->cur_rx);
2413                for (i = 0; i < lp->rx_ring_size; i++)
2414                        printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2415                               le32_to_cpu(lp->rx_ring[i].base),
2416                               (-le16_to_cpu(lp->rx_ring[i].buf_length)) &
2417                               0xffff, le32_to_cpu(lp->rx_ring[i].msg_length),
2418                               le16_to_cpu(lp->rx_ring[i].status));
2419                for (i = 0; i < lp->tx_ring_size; i++)
2420                        printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2421                               le32_to_cpu(lp->tx_ring[i].base),
2422                               (-le16_to_cpu(lp->tx_ring[i].length)) & 0xffff,
2423                               le32_to_cpu(lp->tx_ring[i].misc),
2424                               le16_to_cpu(lp->tx_ring[i].status));
2425                printk("\n");
2426        }
2427        pcnet32_restart(dev, CSR0_NORMAL);
2428
2429        netif_trans_update(dev); /* prevent tx timeout */
2430        netif_wake_queue(dev);
2431
2432        spin_unlock_irqrestore(&lp->lock, flags);
2433}
2434
2435static netdev_tx_t pcnet32_start_xmit(struct sk_buff *skb,
2436                                      struct net_device *dev)
2437{
2438        struct pcnet32_private *lp = netdev_priv(dev);
2439        unsigned long ioaddr = dev->base_addr;
2440        u16 status;
2441        int entry;
2442        unsigned long flags;
2443
2444        spin_lock_irqsave(&lp->lock, flags);
2445
2446        netif_printk(lp, tx_queued, KERN_DEBUG, dev,
2447                     "%s() called, csr0 %4.4x\n",
2448                     __func__, lp->a->read_csr(ioaddr, CSR0));
2449
2450        /* Default status -- will not enable Successful-TxDone
2451         * interrupt when that option is available to us.
2452         */
2453        status = 0x8300;
2454
2455        /* Fill in a Tx ring entry */
2456
2457        /* Mask to ring buffer boundary. */
2458        entry = lp->cur_tx & lp->tx_mod_mask;
2459
2460        /* Caution: the write order is important here, set the status
2461         * with the "ownership" bits last. */
2462
2463        lp->tx_ring[entry].length = cpu_to_le16(-skb->len);
2464
2465        lp->tx_ring[entry].misc = 0x00000000;
2466
2467        lp->tx_dma_addr[entry] =
2468            pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
2469        if (pci_dma_mapping_error(lp->pci_dev, lp->tx_dma_addr[entry])) {
2470                dev_kfree_skb_any(skb);
2471                dev->stats.tx_dropped++;
2472                goto drop_packet;
2473        }
2474        lp->tx_skbuff[entry] = skb;
2475        lp->tx_ring[entry].base = cpu_to_le32(lp->tx_dma_addr[entry]);
2476        wmb();                  /* Make sure owner changes after all others are visible */
2477        lp->tx_ring[entry].status = cpu_to_le16(status);
2478
2479        lp->cur_tx++;
2480        dev->stats.tx_bytes += skb->len;
2481
2482        /* Trigger an immediate send poll. */
2483        lp->a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_TXPOLL);
2484
2485        if (lp->tx_ring[(entry + 1) & lp->tx_mod_mask].base != 0) {
2486                lp->tx_full = 1;
2487                netif_stop_queue(dev);
2488        }
2489drop_packet:
2490        spin_unlock_irqrestore(&lp->lock, flags);
2491        return NETDEV_TX_OK;
2492}
2493
2494/* The PCNET32 interrupt handler. */
2495static irqreturn_t
2496pcnet32_interrupt(int irq, void *dev_id)
2497{
2498        struct net_device *dev = dev_id;
2499        struct pcnet32_private *lp;
2500        unsigned long ioaddr;
2501        u16 csr0;
2502        int boguscnt = max_interrupt_work;
2503
2504        ioaddr = dev->base_addr;
2505        lp = netdev_priv(dev);
2506
2507        spin_lock(&lp->lock);
2508
2509        csr0 = lp->a->read_csr(ioaddr, CSR0);
2510        while ((csr0 & 0x8f00) && --boguscnt >= 0) {
2511                if (csr0 == 0xffff)
2512                        break;  /* PCMCIA remove happened */
2513                /* Acknowledge all of the current interrupt sources ASAP. */
2514                lp->a->write_csr(ioaddr, CSR0, csr0 & ~0x004f);
2515
2516                netif_printk(lp, intr, KERN_DEBUG, dev,
2517                             "interrupt  csr0=%#2.2x new csr=%#2.2x\n",
2518                             csr0, lp->a->read_csr(ioaddr, CSR0));
2519
2520                /* Log misc errors. */
2521                if (csr0 & 0x4000)
2522                        dev->stats.tx_errors++; /* Tx babble. */
2523                if (csr0 & 0x1000) {
2524                        /*
2525                         * This happens when our receive ring is full. This
2526                         * shouldn't be a problem as we will see normal rx
2527                         * interrupts for the frames in the receive ring.  But
2528                         * there are some PCI chipsets (I can reproduce this
2529                         * on SP3G with Intel saturn chipset) which have
2530                         * sometimes problems and will fill up the receive
2531                         * ring with error descriptors.  In this situation we
2532                         * don't get a rx interrupt, but a missed frame
2533                         * interrupt sooner or later.
2534                         */
2535                        dev->stats.rx_errors++; /* Missed a Rx frame. */
2536                }
2537                if (csr0 & 0x0800) {
2538                        netif_err(lp, drv, dev, "Bus master arbitration failure, status %4.4x\n",
2539                                  csr0);
2540                        /* unlike for the lance, there is no restart needed */
2541                }
2542                if (napi_schedule_prep(&lp->napi)) {
2543                        u16 val;
2544                        /* set interrupt masks */
2545                        val = lp->a->read_csr(ioaddr, CSR3);
2546                        val |= 0x5f00;
2547                        lp->a->write_csr(ioaddr, CSR3, val);
2548
2549                        __napi_schedule(&lp->napi);
2550                        break;
2551                }
2552                csr0 = lp->a->read_csr(ioaddr, CSR0);
2553        }
2554
2555        netif_printk(lp, intr, KERN_DEBUG, dev,
2556                     "exiting interrupt, csr0=%#4.4x\n",
2557                     lp->a->read_csr(ioaddr, CSR0));
2558
2559        spin_unlock(&lp->lock);
2560
2561        return IRQ_HANDLED;
2562}
2563
2564static int pcnet32_close(struct net_device *dev)
2565{
2566        unsigned long ioaddr = dev->base_addr;
2567        struct pcnet32_private *lp = netdev_priv(dev);
2568        unsigned long flags;
2569
2570        del_timer_sync(&lp->watchdog_timer);
2571
2572        netif_stop_queue(dev);
2573        napi_disable(&lp->napi);
2574
2575        spin_lock_irqsave(&lp->lock, flags);
2576
2577        dev->stats.rx_missed_errors = lp->a->read_csr(ioaddr, 112);
2578
2579        netif_printk(lp, ifdown, KERN_DEBUG, dev,
2580                     "Shutting down ethercard, status was %2.2x\n",
2581                     lp->a->read_csr(ioaddr, CSR0));
2582
2583        /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */
2584        lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);
2585
2586        /*
2587         * Switch back to 16bit mode to avoid problems with dumb
2588         * DOS packet driver after a warm reboot
2589         */
2590        lp->a->write_bcr(ioaddr, 20, 4);
2591
2592        spin_unlock_irqrestore(&lp->lock, flags);
2593
2594        free_irq(dev->irq, dev);
2595
2596        spin_lock_irqsave(&lp->lock, flags);
2597
2598        pcnet32_purge_rx_ring(dev);
2599        pcnet32_purge_tx_ring(dev);
2600
2601        spin_unlock_irqrestore(&lp->lock, flags);
2602
2603        return 0;
2604}
2605
2606static struct net_device_stats *pcnet32_get_stats(struct net_device *dev)
2607{
2608        struct pcnet32_private *lp = netdev_priv(dev);
2609        unsigned long ioaddr = dev->base_addr;
2610        unsigned long flags;
2611
2612        spin_lock_irqsave(&lp->lock, flags);
2613        dev->stats.rx_missed_errors = lp->a->read_csr(ioaddr, 112);
2614        spin_unlock_irqrestore(&lp->lock, flags);
2615
2616        return &dev->stats;
2617}
2618
2619/* taken from the sunlance driver, which it took from the depca driver */
2620static void pcnet32_load_multicast(struct net_device *dev)
2621{
2622        struct pcnet32_private *lp = netdev_priv(dev);
2623        volatile struct pcnet32_init_block *ib = lp->init_block;
2624        volatile __le16 *mcast_table = (__le16 *)ib->filter;
2625        struct netdev_hw_addr *ha;
2626        unsigned long ioaddr = dev->base_addr;
2627        int i;
2628        u32 crc;
2629
2630        /* set all multicast bits */
2631        if (dev->flags & IFF_ALLMULTI) {
2632                ib->filter[0] = cpu_to_le32(~0U);
2633                ib->filter[1] = cpu_to_le32(~0U);
2634                lp->a->write_csr(ioaddr, PCNET32_MC_FILTER, 0xffff);
2635                lp->a->write_csr(ioaddr, PCNET32_MC_FILTER+1, 0xffff);
2636                lp->a->write_csr(ioaddr, PCNET32_MC_FILTER+2, 0xffff);
2637                lp->a->write_csr(ioaddr, PCNET32_MC_FILTER+3, 0xffff);
2638                return;
2639        }
2640        /* clear the multicast filter */
2641        ib->filter[0] = 0;
2642        ib->filter[1] = 0;
2643
2644        /* Add addresses */
2645        netdev_for_each_mc_addr(ha, dev) {
2646                crc = ether_crc_le(6, ha->addr);
2647                crc = crc >> 26;
2648                mcast_table[crc >> 4] |= cpu_to_le16(1 << (crc & 0xf));
2649        }
2650        for (i = 0; i < 4; i++)
2651                lp->a->write_csr(ioaddr, PCNET32_MC_FILTER + i,
2652                                le16_to_cpu(mcast_table[i]));
2653}
2654
2655/*
2656 * Set or clear the multicast filter for this adaptor.
2657 */
2658static void pcnet32_set_multicast_list(struct net_device *dev)
2659{
2660        unsigned long ioaddr = dev->base_addr, flags;
2661        struct pcnet32_private *lp = netdev_priv(dev);
2662        int csr15, suspended;
2663
2664        spin_lock_irqsave(&lp->lock, flags);
2665        suspended = pcnet32_suspend(dev, &flags, 0);
2666        csr15 = lp->a->read_csr(ioaddr, CSR15);
2667        if (dev->flags & IFF_PROMISC) {
2668                /* Log any net taps. */
2669                netif_info(lp, hw, dev, "Promiscuous mode enabled\n");
2670                lp->init_block->mode =
2671                    cpu_to_le16(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) <<
2672                                7);
2673                lp->a->write_csr(ioaddr, CSR15, csr15 | 0x8000);
2674        } else {
2675                lp->init_block->mode =
2676                    cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7);
2677                lp->a->write_csr(ioaddr, CSR15, csr15 & 0x7fff);
2678                pcnet32_load_multicast(dev);
2679        }
2680
2681        if (suspended) {
2682                int csr5;
2683                /* clear SUSPEND (SPND) - CSR5 bit 0 */
2684                csr5 = lp->a->read_csr(ioaddr, CSR5);
2685                lp->a->write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
2686        } else {
2687                lp->a->write_csr(ioaddr, CSR0, CSR0_STOP);
2688                pcnet32_restart(dev, CSR0_NORMAL);
2689                netif_wake_queue(dev);
2690        }
2691
2692        spin_unlock_irqrestore(&lp->lock, flags);
2693}
2694
2695/* This routine assumes that the lp->lock is held */
2696static int mdio_read(struct net_device *dev, int phy_id, int reg_num)
2697{
2698        struct pcnet32_private *lp = netdev_priv(dev);
2699        unsigned long ioaddr = dev->base_addr;
2700        u16 val_out;
2701
2702        if (!lp->mii)
2703                return 0;
2704
2705        lp->a->write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2706        val_out = lp->a->read_bcr(ioaddr, 34);
2707
2708        return val_out;
2709}
2710
2711/* This routine assumes that the lp->lock is held */
2712static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val)
2713{
2714        struct pcnet32_private *lp = netdev_priv(dev);
2715        unsigned long ioaddr = dev->base_addr;
2716
2717        if (!lp->mii)
2718                return;
2719
2720        lp->a->write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2721        lp->a->write_bcr(ioaddr, 34, val);
2722}
2723
2724static int pcnet32_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2725{
2726        struct pcnet32_private *lp = netdev_priv(dev);
2727        int rc;
2728        unsigned long flags;
2729
2730        /* SIOC[GS]MIIxxx ioctls */
2731        if (lp->mii) {
2732                spin_lock_irqsave(&lp->lock, flags);
2733                rc = generic_mii_ioctl(&lp->mii_if, if_mii(rq), cmd, NULL);
2734                spin_unlock_irqrestore(&lp->lock, flags);
2735        } else {
2736                rc = -EOPNOTSUPP;
2737        }
2738
2739        return rc;
2740}
2741
2742static int pcnet32_check_otherphy(struct net_device *dev)
2743{
2744        struct pcnet32_private *lp = netdev_priv(dev);
2745        struct mii_if_info mii = lp->mii_if;
2746        u16 bmcr;
2747        int i;
2748
2749        for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2750                if (i == lp->mii_if.phy_id)
2751                        continue;       /* skip active phy */
2752                if (lp->phymask & (1 << i)) {
2753                        mii.phy_id = i;
2754                        if (mii_link_ok(&mii)) {
2755                                /* found PHY with active link */
2756                                netif_info(lp, link, dev, "Using PHY number %d\n",
2757                                           i);
2758
2759                                /* isolate inactive phy */
2760                                bmcr =
2761                                    mdio_read(dev, lp->mii_if.phy_id, MII_BMCR);
2762                                mdio_write(dev, lp->mii_if.phy_id, MII_BMCR,
2763                                           bmcr | BMCR_ISOLATE);
2764
2765                                /* de-isolate new phy */
2766                                bmcr = mdio_read(dev, i, MII_BMCR);
2767                                mdio_write(dev, i, MII_BMCR,
2768                                           bmcr & ~BMCR_ISOLATE);
2769
2770                                /* set new phy address */
2771                                lp->mii_if.phy_id = i;
2772                                return 1;
2773                        }
2774                }
2775        }
2776        return 0;
2777}
2778
2779/*
2780 * Show the status of the media.  Similar to mii_check_media however it
2781 * correctly shows the link speed for all (tested) pcnet32 variants.
2782 * Devices with no mii just report link state without speed.
2783 *
2784 * Caller is assumed to hold and release the lp->lock.
2785 */
2786
2787static void pcnet32_check_media(struct net_device *dev, int verbose)
2788{
2789        struct pcnet32_private *lp = netdev_priv(dev);
2790        int curr_link;
2791        int prev_link = netif_carrier_ok(dev) ? 1 : 0;
2792        u32 bcr9;
2793
2794        if (lp->mii) {
2795                curr_link = mii_link_ok(&lp->mii_if);
2796        } else {
2797                ulong ioaddr = dev->base_addr;  /* card base I/O address */
2798                curr_link = (lp->a->read_bcr(ioaddr, 4) != 0xc0);
2799        }
2800        if (!curr_link) {
2801                if (prev_link || verbose) {
2802                        netif_carrier_off(dev);
2803                        netif_info(lp, link, dev, "link down\n");
2804                }
2805                if (lp->phycount > 1) {
2806                        curr_link = pcnet32_check_otherphy(dev);
2807                        prev_link = 0;
2808                }
2809        } else if (verbose || !prev_link) {
2810                netif_carrier_on(dev);
2811                if (lp->mii) {
2812                        if (netif_msg_link(lp)) {
2813                                struct ethtool_cmd ecmd = {
2814                                        .cmd = ETHTOOL_GSET };
2815                                mii_ethtool_gset(&lp->mii_if, &ecmd);
2816                                netdev_info(dev, "link up, %uMbps, %s-duplex\n",
2817                                            ethtool_cmd_speed(&ecmd),
2818                                            (ecmd.duplex == DUPLEX_FULL)
2819                                            ? "full" : "half");
2820                        }
2821                        bcr9 = lp->a->read_bcr(dev->base_addr, 9);
2822                        if ((bcr9 & (1 << 0)) != lp->mii_if.full_duplex) {
2823                                if (lp->mii_if.full_duplex)
2824                                        bcr9 |= (1 << 0);
2825                                else
2826                                        bcr9 &= ~(1 << 0);
2827                                lp->a->write_bcr(dev->base_addr, 9, bcr9);
2828                        }
2829                } else {
2830                        netif_info(lp, link, dev, "link up\n");
2831                }
2832        }
2833}
2834
2835/*
2836 * Check for loss of link and link establishment.
2837 * Could possibly be changed to use mii_check_media instead.
2838 */
2839
2840static void pcnet32_watchdog(struct net_device *dev)
2841{
2842        struct pcnet32_private *lp = netdev_priv(dev);
2843        unsigned long flags;
2844
2845        /* Print the link status if it has changed */
2846        spin_lock_irqsave(&lp->lock, flags);
2847        pcnet32_check_media(dev, 0);
2848        spin_unlock_irqrestore(&lp->lock, flags);
2849
2850        mod_timer(&lp->watchdog_timer, round_jiffies(PCNET32_WATCHDOG_TIMEOUT));
2851}
2852
2853static int pcnet32_pm_suspend(struct pci_dev *pdev, pm_message_t state)
2854{
2855        struct net_device *dev = pci_get_drvdata(pdev);
2856
2857        if (netif_running(dev)) {
2858                netif_device_detach(dev);
2859                pcnet32_close(dev);
2860        }
2861        pci_save_state(pdev);
2862        pci_set_power_state(pdev, pci_choose_state(pdev, state));
2863        return 0;
2864}
2865
2866static int pcnet32_pm_resume(struct pci_dev *pdev)
2867{
2868        struct net_device *dev = pci_get_drvdata(pdev);
2869
2870        pci_set_power_state(pdev, PCI_D0);
2871        pci_restore_state(pdev);
2872
2873        if (netif_running(dev)) {
2874                pcnet32_open(dev);
2875                netif_device_attach(dev);
2876        }
2877        return 0;
2878}
2879
2880static void pcnet32_remove_one(struct pci_dev *pdev)
2881{
2882        struct net_device *dev = pci_get_drvdata(pdev);
2883
2884        if (dev) {
2885                struct pcnet32_private *lp = netdev_priv(dev);
2886
2887                unregister_netdev(dev);
2888                pcnet32_free_ring(dev);
2889                release_region(dev->base_addr, PCNET32_TOTAL_SIZE);
2890                pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
2891                                    lp->init_block, lp->init_dma_addr);
2892                free_netdev(dev);
2893                pci_disable_device(pdev);
2894        }
2895}
2896
2897static struct pci_driver pcnet32_driver = {
2898        .name = DRV_NAME,
2899        .probe = pcnet32_probe_pci,
2900        .remove = pcnet32_remove_one,
2901        .id_table = pcnet32_pci_tbl,
2902        .suspend = pcnet32_pm_suspend,
2903        .resume = pcnet32_pm_resume,
2904};
2905
2906/* An additional parameter that may be passed in... */
2907static int debug = -1;
2908static int tx_start_pt = -1;
2909static int pcnet32_have_pci;
2910
2911module_param(debug, int, 0);
2912MODULE_PARM_DESC(debug, DRV_NAME " debug level");
2913module_param(max_interrupt_work, int, 0);
2914MODULE_PARM_DESC(max_interrupt_work,
2915                 DRV_NAME " maximum events handled per interrupt");
2916module_param(rx_copybreak, int, 0);
2917MODULE_PARM_DESC(rx_copybreak,
2918                 DRV_NAME " copy breakpoint for copy-only-tiny-frames");
2919module_param(tx_start_pt, int, 0);
2920MODULE_PARM_DESC(tx_start_pt, DRV_NAME " transmit start point (0-3)");
2921module_param(pcnet32vlb, int, 0);
2922MODULE_PARM_DESC(pcnet32vlb, DRV_NAME " Vesa local bus (VLB) support (0/1)");
2923module_param_array(options, int, NULL, 0);
2924MODULE_PARM_DESC(options, DRV_NAME " initial option setting(s) (0-15)");
2925module_param_array(full_duplex, int, NULL, 0);
2926MODULE_PARM_DESC(full_duplex, DRV_NAME " full duplex setting(s) (1)");
2927/* Module Parameter for HomePNA cards added by Patrick Simmons, 2004 */
2928module_param_array(homepna, int, NULL, 0);
2929MODULE_PARM_DESC(homepna,
2930                 DRV_NAME
2931                 " mode for 79C978 cards (1 for HomePNA, 0 for Ethernet, default Ethernet");
2932
2933MODULE_AUTHOR("Thomas Bogendoerfer");
2934MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards");
2935MODULE_LICENSE("GPL");
2936
2937#define PCNET32_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
2938
2939static int __init pcnet32_init_module(void)
2940{
2941        pr_info("%s", version);
2942
2943        pcnet32_debug = netif_msg_init(debug, PCNET32_MSG_DEFAULT);
2944
2945        if ((tx_start_pt >= 0) && (tx_start_pt <= 3))
2946                tx_start = tx_start_pt;
2947
2948        /* find the PCI devices */
2949        if (!pci_register_driver(&pcnet32_driver))
2950                pcnet32_have_pci = 1;
2951
2952        /* should we find any remaining VLbus devices ? */
2953        if (pcnet32vlb)
2954                pcnet32_probe_vlbus(pcnet32_portlist);
2955
2956        if (cards_found && (pcnet32_debug & NETIF_MSG_PROBE))
2957                pr_info("%d cards_found\n", cards_found);
2958
2959        return (pcnet32_have_pci + cards_found) ? 0 : -ENODEV;
2960}
2961
2962static void __exit pcnet32_cleanup_module(void)
2963{
2964        struct net_device *next_dev;
2965
2966        while (pcnet32_dev) {
2967                struct pcnet32_private *lp = netdev_priv(pcnet32_dev);
2968                next_dev = lp->next;
2969                unregister_netdev(pcnet32_dev);
2970                pcnet32_free_ring(pcnet32_dev);
2971                release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE);
2972                pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
2973                                    lp->init_block, lp->init_dma_addr);
2974                free_netdev(pcnet32_dev);
2975                pcnet32_dev = next_dev;
2976        }
2977
2978        if (pcnet32_have_pci)
2979                pci_unregister_driver(&pcnet32_driver);
2980}
2981
2982module_init(pcnet32_init_module);
2983module_exit(pcnet32_cleanup_module);
2984
2985/*
2986 * Local variables:
2987 *  c-indent-level: 4
2988 *  tab-width: 8
2989 * End:
2990 */
2991