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10#ifndef _MACB_H
11#define _MACB_H
12
13#define MACB_GREGS_NBR 16
14#define MACB_GREGS_VERSION 2
15#define MACB_MAX_QUEUES 8
16
17
18#define MACB_NCR 0x0000
19#define MACB_NCFGR 0x0004
20#define MACB_NSR 0x0008
21#define MACB_TAR 0x000c
22#define MACB_TCR 0x0010
23#define MACB_TSR 0x0014
24#define MACB_RBQP 0x0018
25#define MACB_TBQP 0x001c
26#define MACB_RSR 0x0020
27#define MACB_ISR 0x0024
28#define MACB_IER 0x0028
29#define MACB_IDR 0x002c
30#define MACB_IMR 0x0030
31#define MACB_MAN 0x0034
32#define MACB_PTR 0x0038
33#define MACB_PFR 0x003c
34#define MACB_FTO 0x0040
35#define MACB_SCF 0x0044
36#define MACB_MCF 0x0048
37#define MACB_FRO 0x004c
38#define MACB_FCSE 0x0050
39#define MACB_ALE 0x0054
40#define MACB_DTF 0x0058
41#define MACB_LCOL 0x005c
42#define MACB_EXCOL 0x0060
43#define MACB_TUND 0x0064
44#define MACB_CSE 0x0068
45#define MACB_RRE 0x006c
46#define MACB_ROVR 0x0070
47#define MACB_RSE 0x0074
48#define MACB_ELE 0x0078
49#define MACB_RJA 0x007c
50#define MACB_USF 0x0080
51#define MACB_STE 0x0084
52#define MACB_RLE 0x0088
53#define MACB_TPF 0x008c
54#define MACB_HRB 0x0090
55#define MACB_HRT 0x0094
56#define MACB_SA1B 0x0098
57#define MACB_SA1T 0x009c
58#define MACB_SA2B 0x00a0
59#define MACB_SA2T 0x00a4
60#define MACB_SA3B 0x00a8
61#define MACB_SA3T 0x00ac
62#define MACB_SA4B 0x00b0
63#define MACB_SA4T 0x00b4
64#define MACB_TID 0x00b8
65#define MACB_TPQ 0x00bc
66#define MACB_USRIO 0x00c0
67#define MACB_WOL 0x00c4
68#define MACB_MID 0x00fc
69
70
71#define GEM_NCFGR 0x0004
72#define GEM_USRIO 0x000c
73#define GEM_DMACFG 0x0010
74#define GEM_JML 0x0048
75#define GEM_HRB 0x0080
76#define GEM_HRT 0x0084
77#define GEM_SA1B 0x0088
78#define GEM_SA1T 0x008C
79#define GEM_SA2B 0x0090
80#define GEM_SA2T 0x0094
81#define GEM_SA3B 0x0098
82#define GEM_SA3T 0x009C
83#define GEM_SA4B 0x00A0
84#define GEM_SA4T 0x00A4
85#define GEM_OTX 0x0100
86#define GEM_OCTTXL 0x0100
87#define GEM_OCTTXH 0x0104
88#define GEM_TXCNT 0x0108
89#define GEM_TXBCCNT 0x010c
90#define GEM_TXMCCNT 0x0110
91#define GEM_TXPAUSECNT 0x0114
92#define GEM_TX64CNT 0x0118
93#define GEM_TX65CNT 0x011c
94#define GEM_TX128CNT 0x0120
95#define GEM_TX256CNT 0x0124
96#define GEM_TX512CNT 0x0128
97#define GEM_TX1024CNT 0x012c
98#define GEM_TX1519CNT 0x0130
99#define GEM_TXURUNCNT 0x0134
100#define GEM_SNGLCOLLCNT 0x0138
101#define GEM_MULTICOLLCNT 0x013c
102#define GEM_EXCESSCOLLCNT 0x0140
103#define GEM_LATECOLLCNT 0x0144
104#define GEM_TXDEFERCNT 0x0148
105#define GEM_TXCSENSECNT 0x014c
106#define GEM_ORX 0x0150
107#define GEM_OCTRXL 0x0150
108#define GEM_OCTRXH 0x0154
109#define GEM_RXCNT 0x0158
110#define GEM_RXBROADCNT 0x015c
111#define GEM_RXMULTICNT 0x0160
112#define GEM_RXPAUSECNT 0x0164
113#define GEM_RX64CNT 0x0168
114#define GEM_RX65CNT 0x016c
115#define GEM_RX128CNT 0x0170
116#define GEM_RX256CNT 0x0174
117#define GEM_RX512CNT 0x0178
118#define GEM_RX1024CNT 0x017c
119#define GEM_RX1519CNT 0x0180
120#define GEM_RXUNDRCNT 0x0184
121#define GEM_RXOVRCNT 0x0188
122#define GEM_RXJABCNT 0x018c
123#define GEM_RXFCSCNT 0x0190
124#define GEM_RXLENGTHCNT 0x0194
125#define GEM_RXSYMBCNT 0x0198
126#define GEM_RXALIGNCNT 0x019c
127#define GEM_RXRESERRCNT 0x01a0
128#define GEM_RXORCNT 0x01a4
129#define GEM_RXIPCCNT 0x01a8
130#define GEM_RXTCPCCNT 0x01ac
131#define GEM_RXUDPCCNT 0x01b0
132#define GEM_DCFG1 0x0280
133#define GEM_DCFG2 0x0284
134#define GEM_DCFG3 0x0288
135#define GEM_DCFG4 0x028c
136#define GEM_DCFG5 0x0290
137#define GEM_DCFG6 0x0294
138#define GEM_DCFG7 0x0298
139
140#define GEM_ISR(hw_q) (0x0400 + ((hw_q) << 2))
141#define GEM_TBQP(hw_q) (0x0440 + ((hw_q) << 2))
142#define GEM_RBQP(hw_q) (0x0480 + ((hw_q) << 2))
143#define GEM_IER(hw_q) (0x0600 + ((hw_q) << 2))
144#define GEM_IDR(hw_q) (0x0620 + ((hw_q) << 2))
145#define GEM_IMR(hw_q) (0x0640 + ((hw_q) << 2))
146
147
148#define MACB_LB_OFFSET 0
149#define MACB_LB_SIZE 1
150#define MACB_LLB_OFFSET 1
151#define MACB_LLB_SIZE 1
152#define MACB_RE_OFFSET 2
153#define MACB_RE_SIZE 1
154#define MACB_TE_OFFSET 3
155#define MACB_TE_SIZE 1
156#define MACB_MPE_OFFSET 4
157#define MACB_MPE_SIZE 1
158#define MACB_CLRSTAT_OFFSET 5
159#define MACB_CLRSTAT_SIZE 1
160#define MACB_INCSTAT_OFFSET 6
161#define MACB_INCSTAT_SIZE 1
162#define MACB_WESTAT_OFFSET 7
163#define MACB_WESTAT_SIZE 1
164#define MACB_BP_OFFSET 8
165#define MACB_BP_SIZE 1
166#define MACB_TSTART_OFFSET 9
167#define MACB_TSTART_SIZE 1
168#define MACB_THALT_OFFSET 10
169#define MACB_THALT_SIZE 1
170#define MACB_NCR_TPF_OFFSET 11
171#define MACB_NCR_TPF_SIZE 1
172#define MACB_TZQ_OFFSET 12
173#define MACB_TZQ_SIZE 1
174
175
176#define MACB_SPD_OFFSET 0
177#define MACB_SPD_SIZE 1
178#define MACB_FD_OFFSET 1
179#define MACB_FD_SIZE 1
180#define MACB_BIT_RATE_OFFSET 2
181#define MACB_BIT_RATE_SIZE 1
182#define MACB_JFRAME_OFFSET 3
183#define MACB_JFRAME_SIZE 1
184#define MACB_CAF_OFFSET 4
185#define MACB_CAF_SIZE 1
186#define MACB_NBC_OFFSET 5
187#define MACB_NBC_SIZE 1
188#define MACB_NCFGR_MTI_OFFSET 6
189#define MACB_NCFGR_MTI_SIZE 1
190#define MACB_UNI_OFFSET 7
191#define MACB_UNI_SIZE 1
192#define MACB_BIG_OFFSET 8
193#define MACB_BIG_SIZE 1
194#define MACB_EAE_OFFSET 9
195#define MACB_EAE_SIZE 1
196#define MACB_CLK_OFFSET 10
197#define MACB_CLK_SIZE 2
198#define MACB_RTY_OFFSET 12
199#define MACB_RTY_SIZE 1
200#define MACB_PAE_OFFSET 13
201#define MACB_PAE_SIZE 1
202#define MACB_RM9200_RMII_OFFSET 13
203#define MACB_RM9200_RMII_SIZE 1
204#define MACB_RBOF_OFFSET 14
205#define MACB_RBOF_SIZE 2
206#define MACB_RLCE_OFFSET 16
207#define MACB_RLCE_SIZE 1
208#define MACB_DRFCS_OFFSET 17
209#define MACB_DRFCS_SIZE 1
210#define MACB_EFRHD_OFFSET 18
211#define MACB_EFRHD_SIZE 1
212#define MACB_IRXFCS_OFFSET 19
213#define MACB_IRXFCS_SIZE 1
214
215
216#define GEM_GBE_OFFSET 10
217#define GEM_GBE_SIZE 1
218#define GEM_PCSSEL_OFFSET 11
219#define GEM_PCSSEL_SIZE 1
220#define GEM_CLK_OFFSET 18
221#define GEM_CLK_SIZE 3
222#define GEM_DBW_OFFSET 21
223#define GEM_DBW_SIZE 2
224#define GEM_RXCOEN_OFFSET 24
225#define GEM_RXCOEN_SIZE 1
226#define GEM_SGMIIEN_OFFSET 27
227#define GEM_SGMIIEN_SIZE 1
228
229
230
231#define GEM_DBW32 0
232#define GEM_DBW64 1
233#define GEM_DBW128 2
234
235
236#define GEM_FBLDO_OFFSET 0
237#define GEM_FBLDO_SIZE 5
238#define GEM_ENDIA_DESC_OFFSET 6
239#define GEM_ENDIA_DESC_SIZE 1
240#define GEM_ENDIA_PKT_OFFSET 7
241#define GEM_ENDIA_PKT_SIZE 1
242#define GEM_RXBMS_OFFSET 8
243#define GEM_RXBMS_SIZE 2
244#define GEM_TXPBMS_OFFSET 10
245#define GEM_TXPBMS_SIZE 1
246#define GEM_TXCOEN_OFFSET 11
247#define GEM_TXCOEN_SIZE 1
248#define GEM_RXBS_OFFSET 16
249#define GEM_RXBS_SIZE 8
250#define GEM_DDRP_OFFSET 24
251#define GEM_DDRP_SIZE 1
252
253
254
255#define MACB_NSR_LINK_OFFSET 0
256#define MACB_NSR_LINK_SIZE 1
257#define MACB_MDIO_OFFSET 1
258#define MACB_MDIO_SIZE 1
259#define MACB_IDLE_OFFSET 2
260#define MACB_IDLE_SIZE 1
261
262
263#define MACB_UBR_OFFSET 0
264#define MACB_UBR_SIZE 1
265#define MACB_COL_OFFSET 1
266#define MACB_COL_SIZE 1
267#define MACB_TSR_RLE_OFFSET 2
268#define MACB_TSR_RLE_SIZE 1
269#define MACB_TGO_OFFSET 3
270#define MACB_TGO_SIZE 1
271#define MACB_BEX_OFFSET 4
272#define MACB_BEX_SIZE 1
273#define MACB_RM9200_BNQ_OFFSET 4
274#define MACB_RM9200_BNQ_SIZE 1
275#define MACB_COMP_OFFSET 5
276#define MACB_COMP_SIZE 1
277#define MACB_UND_OFFSET 6
278#define MACB_UND_SIZE 1
279
280
281#define MACB_BNA_OFFSET 0
282#define MACB_BNA_SIZE 1
283#define MACB_REC_OFFSET 1
284#define MACB_REC_SIZE 1
285#define MACB_OVR_OFFSET 2
286#define MACB_OVR_SIZE 1
287
288
289#define MACB_MFD_OFFSET 0
290#define MACB_MFD_SIZE 1
291#define MACB_RCOMP_OFFSET 1
292#define MACB_RCOMP_SIZE 1
293#define MACB_RXUBR_OFFSET 2
294#define MACB_RXUBR_SIZE 1
295#define MACB_TXUBR_OFFSET 3
296#define MACB_TXUBR_SIZE 1
297#define MACB_ISR_TUND_OFFSET 4
298#define MACB_ISR_TUND_SIZE 1
299#define MACB_ISR_RLE_OFFSET 5
300#define MACB_ISR_RLE_SIZE 1
301#define MACB_TXERR_OFFSET 6
302#define MACB_TXERR_SIZE 1
303#define MACB_TCOMP_OFFSET 7
304#define MACB_TCOMP_SIZE 1
305#define MACB_ISR_LINK_OFFSET 9
306#define MACB_ISR_LINK_SIZE 1
307#define MACB_ISR_ROVR_OFFSET 10
308#define MACB_ISR_ROVR_SIZE 1
309#define MACB_HRESP_OFFSET 11
310#define MACB_HRESP_SIZE 1
311#define MACB_PFR_OFFSET 12
312#define MACB_PFR_SIZE 1
313#define MACB_PTZ_OFFSET 13
314#define MACB_PTZ_SIZE 1
315#define MACB_WOL_OFFSET 14
316#define MACB_WOL_SIZE 1
317
318
319#define MACB_DATA_OFFSET 0
320#define MACB_DATA_SIZE 16
321#define MACB_CODE_OFFSET 16
322#define MACB_CODE_SIZE 2
323#define MACB_REGA_OFFSET 18
324#define MACB_REGA_SIZE 5
325#define MACB_PHYA_OFFSET 23
326#define MACB_PHYA_SIZE 5
327#define MACB_RW_OFFSET 28
328#define MACB_RW_SIZE 2
329#define MACB_SOF_OFFSET 30
330#define MACB_SOF_SIZE 2
331
332
333#define MACB_MII_OFFSET 0
334#define MACB_MII_SIZE 1
335#define MACB_EAM_OFFSET 1
336#define MACB_EAM_SIZE 1
337#define MACB_TX_PAUSE_OFFSET 2
338#define MACB_TX_PAUSE_SIZE 1
339#define MACB_TX_PAUSE_ZERO_OFFSET 3
340#define MACB_TX_PAUSE_ZERO_SIZE 1
341
342
343#define MACB_RMII_OFFSET 0
344#define MACB_RMII_SIZE 1
345#define GEM_RGMII_OFFSET 0
346#define GEM_RGMII_SIZE 1
347#define MACB_CLKEN_OFFSET 1
348#define MACB_CLKEN_SIZE 1
349
350
351#define MACB_IP_OFFSET 0
352#define MACB_IP_SIZE 16
353#define MACB_MAG_OFFSET 16
354#define MACB_MAG_SIZE 1
355#define MACB_ARP_OFFSET 17
356#define MACB_ARP_SIZE 1
357#define MACB_SA1_OFFSET 18
358#define MACB_SA1_SIZE 1
359#define MACB_WOL_MTI_OFFSET 19
360#define MACB_WOL_MTI_SIZE 1
361
362
363#define MACB_IDNUM_OFFSET 16
364#define MACB_IDNUM_SIZE 12
365#define MACB_REV_OFFSET 0
366#define MACB_REV_SIZE 16
367
368
369#define GEM_IRQCOR_OFFSET 23
370#define GEM_IRQCOR_SIZE 1
371#define GEM_DBWDEF_OFFSET 25
372#define GEM_DBWDEF_SIZE 3
373
374
375#define GEM_RX_PKT_BUFF_OFFSET 20
376#define GEM_RX_PKT_BUFF_SIZE 1
377#define GEM_TX_PKT_BUFF_OFFSET 21
378#define GEM_TX_PKT_BUFF_SIZE 1
379
380
381#define MACB_CLK_DIV8 0
382#define MACB_CLK_DIV16 1
383#define MACB_CLK_DIV32 2
384#define MACB_CLK_DIV64 3
385
386
387#define GEM_CLK_DIV8 0
388#define GEM_CLK_DIV16 1
389#define GEM_CLK_DIV32 2
390#define GEM_CLK_DIV48 3
391#define GEM_CLK_DIV64 4
392#define GEM_CLK_DIV96 5
393
394
395#define MACB_MAN_SOF 1
396#define MACB_MAN_WRITE 1
397#define MACB_MAN_READ 2
398#define MACB_MAN_CODE 2
399
400
401#define MACB_CAPS_ISR_CLEAR_ON_WRITE 0x00000001
402#define MACB_CAPS_USRIO_HAS_CLKEN 0x00000002
403#define MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII 0x00000004
404#define MACB_CAPS_NO_GIGABIT_HALF 0x00000008
405#define MACB_CAPS_USRIO_DISABLED 0x00000010
406#define MACB_CAPS_JUMBO 0x00000020
407#define MACB_CAPS_FIFO_MODE 0x10000000
408#define MACB_CAPS_GIGABIT_MODE_AVAILABLE 0x20000000
409#define MACB_CAPS_SG_DISABLED 0x40000000
410#define MACB_CAPS_MACB_IS_GEM 0x80000000
411
412
413#define MACB_BIT(name) \
414 (1 << MACB_##name##_OFFSET)
415#define MACB_BF(name,value) \
416 (((value) & ((1 << MACB_##name##_SIZE) - 1)) \
417 << MACB_##name##_OFFSET)
418#define MACB_BFEXT(name,value)\
419 (((value) >> MACB_##name##_OFFSET) \
420 & ((1 << MACB_##name##_SIZE) - 1))
421#define MACB_BFINS(name,value,old) \
422 (((old) & ~(((1 << MACB_##name##_SIZE) - 1) \
423 << MACB_##name##_OFFSET)) \
424 | MACB_BF(name,value))
425
426#define GEM_BIT(name) \
427 (1 << GEM_##name##_OFFSET)
428#define GEM_BF(name, value) \
429 (((value) & ((1 << GEM_##name##_SIZE) - 1)) \
430 << GEM_##name##_OFFSET)
431#define GEM_BFEXT(name, value)\
432 (((value) >> GEM_##name##_OFFSET) \
433 & ((1 << GEM_##name##_SIZE) - 1))
434#define GEM_BFINS(name, value, old) \
435 (((old) & ~(((1 << GEM_##name##_SIZE) - 1) \
436 << GEM_##name##_OFFSET)) \
437 | GEM_BF(name, value))
438
439
440#define macb_readl(port, reg) (port)->macb_reg_readl((port), MACB_##reg)
441#define macb_writel(port, reg, value) (port)->macb_reg_writel((port), MACB_##reg, (value))
442#define gem_readl(port, reg) (port)->macb_reg_readl((port), GEM_##reg)
443#define gem_writel(port, reg, value) (port)->macb_reg_writel((port), GEM_##reg, (value))
444#define queue_readl(queue, reg) (queue)->bp->macb_reg_readl((queue)->bp, (queue)->reg)
445#define queue_writel(queue, reg, value) (queue)->bp->macb_reg_writel((queue)->bp, (queue)->reg, (value))
446
447
448
449
450
451
452#define macb_or_gem_writel(__bp, __reg, __value) \
453 ({ \
454 if (macb_is_gem((__bp))) \
455 gem_writel((__bp), __reg, __value); \
456 else \
457 macb_writel((__bp), __reg, __value); \
458 })
459
460#define macb_or_gem_readl(__bp, __reg) \
461 ({ \
462 u32 __v; \
463 if (macb_is_gem((__bp))) \
464 __v = gem_readl((__bp), __reg); \
465 else \
466 __v = macb_readl((__bp), __reg); \
467 __v; \
468 })
469
470
471
472
473
474struct macb_dma_desc {
475 u32 addr;
476 u32 ctrl;
477};
478
479
480#define MACB_RX_USED_OFFSET 0
481#define MACB_RX_USED_SIZE 1
482#define MACB_RX_WRAP_OFFSET 1
483#define MACB_RX_WRAP_SIZE 1
484#define MACB_RX_WADDR_OFFSET 2
485#define MACB_RX_WADDR_SIZE 30
486
487#define MACB_RX_FRMLEN_OFFSET 0
488#define MACB_RX_FRMLEN_SIZE 12
489#define MACB_RX_OFFSET_OFFSET 12
490#define MACB_RX_OFFSET_SIZE 2
491#define MACB_RX_SOF_OFFSET 14
492#define MACB_RX_SOF_SIZE 1
493#define MACB_RX_EOF_OFFSET 15
494#define MACB_RX_EOF_SIZE 1
495#define MACB_RX_CFI_OFFSET 16
496#define MACB_RX_CFI_SIZE 1
497#define MACB_RX_VLAN_PRI_OFFSET 17
498#define MACB_RX_VLAN_PRI_SIZE 3
499#define MACB_RX_PRI_TAG_OFFSET 20
500#define MACB_RX_PRI_TAG_SIZE 1
501#define MACB_RX_VLAN_TAG_OFFSET 21
502#define MACB_RX_VLAN_TAG_SIZE 1
503#define MACB_RX_TYPEID_MATCH_OFFSET 22
504#define MACB_RX_TYPEID_MATCH_SIZE 1
505#define MACB_RX_SA4_MATCH_OFFSET 23
506#define MACB_RX_SA4_MATCH_SIZE 1
507#define MACB_RX_SA3_MATCH_OFFSET 24
508#define MACB_RX_SA3_MATCH_SIZE 1
509#define MACB_RX_SA2_MATCH_OFFSET 25
510#define MACB_RX_SA2_MATCH_SIZE 1
511#define MACB_RX_SA1_MATCH_OFFSET 26
512#define MACB_RX_SA1_MATCH_SIZE 1
513#define MACB_RX_EXT_MATCH_OFFSET 28
514#define MACB_RX_EXT_MATCH_SIZE 1
515#define MACB_RX_UHASH_MATCH_OFFSET 29
516#define MACB_RX_UHASH_MATCH_SIZE 1
517#define MACB_RX_MHASH_MATCH_OFFSET 30
518#define MACB_RX_MHASH_MATCH_SIZE 1
519#define MACB_RX_BROADCAST_OFFSET 31
520#define MACB_RX_BROADCAST_SIZE 1
521
522#define MACB_RX_FRMLEN_MASK 0xFFF
523#define MACB_RX_JFRMLEN_MASK 0x3FFF
524
525
526#define GEM_RX_TYPEID_MATCH_OFFSET 22
527#define GEM_RX_TYPEID_MATCH_SIZE 2
528
529
530#define GEM_RX_CSUM_OFFSET 22
531#define GEM_RX_CSUM_SIZE 2
532
533#define MACB_TX_FRMLEN_OFFSET 0
534#define MACB_TX_FRMLEN_SIZE 11
535#define MACB_TX_LAST_OFFSET 15
536#define MACB_TX_LAST_SIZE 1
537#define MACB_TX_NOCRC_OFFSET 16
538#define MACB_TX_NOCRC_SIZE 1
539#define MACB_TX_BUF_EXHAUSTED_OFFSET 27
540#define MACB_TX_BUF_EXHAUSTED_SIZE 1
541#define MACB_TX_UNDERRUN_OFFSET 28
542#define MACB_TX_UNDERRUN_SIZE 1
543#define MACB_TX_ERROR_OFFSET 29
544#define MACB_TX_ERROR_SIZE 1
545#define MACB_TX_WRAP_OFFSET 30
546#define MACB_TX_WRAP_SIZE 1
547#define MACB_TX_USED_OFFSET 31
548#define MACB_TX_USED_SIZE 1
549
550#define GEM_TX_FRMLEN_OFFSET 0
551#define GEM_TX_FRMLEN_SIZE 14
552
553
554#define GEM_RX_CSUM_NONE 0
555#define GEM_RX_CSUM_IP_ONLY 1
556#define GEM_RX_CSUM_IP_TCP 2
557#define GEM_RX_CSUM_IP_UDP 3
558
559
560#define GEM_RX_CSUM_CHECKED_MASK 2
561
562
563
564
565
566
567
568
569
570struct macb_tx_skb {
571 struct sk_buff *skb;
572 dma_addr_t mapping;
573 size_t size;
574 bool mapped_as_page;
575};
576
577
578
579
580struct macb_stats {
581 u32 rx_pause_frames;
582 u32 tx_ok;
583 u32 tx_single_cols;
584 u32 tx_multiple_cols;
585 u32 rx_ok;
586 u32 rx_fcs_errors;
587 u32 rx_align_errors;
588 u32 tx_deferred;
589 u32 tx_late_cols;
590 u32 tx_excessive_cols;
591 u32 tx_underruns;
592 u32 tx_carrier_errors;
593 u32 rx_resource_errors;
594 u32 rx_overruns;
595 u32 rx_symbol_errors;
596 u32 rx_oversize_pkts;
597 u32 rx_jabbers;
598 u32 rx_undersize_pkts;
599 u32 sqe_test_errors;
600 u32 rx_length_mismatch;
601 u32 tx_pause_frames;
602};
603
604struct gem_stats {
605 u32 tx_octets_31_0;
606 u32 tx_octets_47_32;
607 u32 tx_frames;
608 u32 tx_broadcast_frames;
609 u32 tx_multicast_frames;
610 u32 tx_pause_frames;
611 u32 tx_64_byte_frames;
612 u32 tx_65_127_byte_frames;
613 u32 tx_128_255_byte_frames;
614 u32 tx_256_511_byte_frames;
615 u32 tx_512_1023_byte_frames;
616 u32 tx_1024_1518_byte_frames;
617 u32 tx_greater_than_1518_byte_frames;
618 u32 tx_underrun;
619 u32 tx_single_collision_frames;
620 u32 tx_multiple_collision_frames;
621 u32 tx_excessive_collisions;
622 u32 tx_late_collisions;
623 u32 tx_deferred_frames;
624 u32 tx_carrier_sense_errors;
625 u32 rx_octets_31_0;
626 u32 rx_octets_47_32;
627 u32 rx_frames;
628 u32 rx_broadcast_frames;
629 u32 rx_multicast_frames;
630 u32 rx_pause_frames;
631 u32 rx_64_byte_frames;
632 u32 rx_65_127_byte_frames;
633 u32 rx_128_255_byte_frames;
634 u32 rx_256_511_byte_frames;
635 u32 rx_512_1023_byte_frames;
636 u32 rx_1024_1518_byte_frames;
637 u32 rx_greater_than_1518_byte_frames;
638 u32 rx_undersized_frames;
639 u32 rx_oversize_frames;
640 u32 rx_jabbers;
641 u32 rx_frame_check_sequence_errors;
642 u32 rx_length_field_frame_errors;
643 u32 rx_symbol_errors;
644 u32 rx_alignment_errors;
645 u32 rx_resource_errors;
646 u32 rx_overruns;
647 u32 rx_ip_header_checksum_errors;
648 u32 rx_tcp_checksum_errors;
649 u32 rx_udp_checksum_errors;
650};
651
652
653
654
655
656struct gem_statistic {
657 char stat_string[ETH_GSTRING_LEN];
658 int offset;
659 u32 stat_bits;
660};
661
662
663#define GEM_NDS_RXERR_OFFSET 0
664#define GEM_NDS_RXLENERR_OFFSET 1
665#define GEM_NDS_RXOVERERR_OFFSET 2
666#define GEM_NDS_RXCRCERR_OFFSET 3
667#define GEM_NDS_RXFRAMEERR_OFFSET 4
668#define GEM_NDS_RXFIFOERR_OFFSET 5
669#define GEM_NDS_TXERR_OFFSET 6
670#define GEM_NDS_TXABORTEDERR_OFFSET 7
671#define GEM_NDS_TXCARRIERERR_OFFSET 8
672#define GEM_NDS_TXFIFOERR_OFFSET 9
673#define GEM_NDS_COLLISIONS_OFFSET 10
674
675#define GEM_STAT_TITLE(name, title) GEM_STAT_TITLE_BITS(name, title, 0)
676#define GEM_STAT_TITLE_BITS(name, title, bits) { \
677 .stat_string = title, \
678 .offset = GEM_##name, \
679 .stat_bits = bits \
680}
681
682
683
684
685static const struct gem_statistic gem_statistics[] = {
686 GEM_STAT_TITLE(OCTTXL, "tx_octets"),
687 GEM_STAT_TITLE(TXCNT, "tx_frames"),
688 GEM_STAT_TITLE(TXBCCNT, "tx_broadcast_frames"),
689 GEM_STAT_TITLE(TXMCCNT, "tx_multicast_frames"),
690 GEM_STAT_TITLE(TXPAUSECNT, "tx_pause_frames"),
691 GEM_STAT_TITLE(TX64CNT, "tx_64_byte_frames"),
692 GEM_STAT_TITLE(TX65CNT, "tx_65_127_byte_frames"),
693 GEM_STAT_TITLE(TX128CNT, "tx_128_255_byte_frames"),
694 GEM_STAT_TITLE(TX256CNT, "tx_256_511_byte_frames"),
695 GEM_STAT_TITLE(TX512CNT, "tx_512_1023_byte_frames"),
696 GEM_STAT_TITLE(TX1024CNT, "tx_1024_1518_byte_frames"),
697 GEM_STAT_TITLE(TX1519CNT, "tx_greater_than_1518_byte_frames"),
698 GEM_STAT_TITLE_BITS(TXURUNCNT, "tx_underrun",
699 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_TXFIFOERR)),
700 GEM_STAT_TITLE_BITS(SNGLCOLLCNT, "tx_single_collision_frames",
701 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
702 GEM_STAT_TITLE_BITS(MULTICOLLCNT, "tx_multiple_collision_frames",
703 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
704 GEM_STAT_TITLE_BITS(EXCESSCOLLCNT, "tx_excessive_collisions",
705 GEM_BIT(NDS_TXERR)|
706 GEM_BIT(NDS_TXABORTEDERR)|
707 GEM_BIT(NDS_COLLISIONS)),
708 GEM_STAT_TITLE_BITS(LATECOLLCNT, "tx_late_collisions",
709 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
710 GEM_STAT_TITLE(TXDEFERCNT, "tx_deferred_frames"),
711 GEM_STAT_TITLE_BITS(TXCSENSECNT, "tx_carrier_sense_errors",
712 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
713 GEM_STAT_TITLE(OCTRXL, "rx_octets"),
714 GEM_STAT_TITLE(RXCNT, "rx_frames"),
715 GEM_STAT_TITLE(RXBROADCNT, "rx_broadcast_frames"),
716 GEM_STAT_TITLE(RXMULTICNT, "rx_multicast_frames"),
717 GEM_STAT_TITLE(RXPAUSECNT, "rx_pause_frames"),
718 GEM_STAT_TITLE(RX64CNT, "rx_64_byte_frames"),
719 GEM_STAT_TITLE(RX65CNT, "rx_65_127_byte_frames"),
720 GEM_STAT_TITLE(RX128CNT, "rx_128_255_byte_frames"),
721 GEM_STAT_TITLE(RX256CNT, "rx_256_511_byte_frames"),
722 GEM_STAT_TITLE(RX512CNT, "rx_512_1023_byte_frames"),
723 GEM_STAT_TITLE(RX1024CNT, "rx_1024_1518_byte_frames"),
724 GEM_STAT_TITLE(RX1519CNT, "rx_greater_than_1518_byte_frames"),
725 GEM_STAT_TITLE_BITS(RXUNDRCNT, "rx_undersized_frames",
726 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)),
727 GEM_STAT_TITLE_BITS(RXOVRCNT, "rx_oversize_frames",
728 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)),
729 GEM_STAT_TITLE_BITS(RXJABCNT, "rx_jabbers",
730 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)),
731 GEM_STAT_TITLE_BITS(RXFCSCNT, "rx_frame_check_sequence_errors",
732 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXCRCERR)),
733 GEM_STAT_TITLE_BITS(RXLENGTHCNT, "rx_length_field_frame_errors",
734 GEM_BIT(NDS_RXERR)),
735 GEM_STAT_TITLE_BITS(RXSYMBCNT, "rx_symbol_errors",
736 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXFRAMEERR)),
737 GEM_STAT_TITLE_BITS(RXALIGNCNT, "rx_alignment_errors",
738 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXOVERERR)),
739 GEM_STAT_TITLE_BITS(RXRESERRCNT, "rx_resource_errors",
740 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXOVERERR)),
741 GEM_STAT_TITLE_BITS(RXORCNT, "rx_overruns",
742 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXFIFOERR)),
743 GEM_STAT_TITLE_BITS(RXIPCCNT, "rx_ip_header_checksum_errors",
744 GEM_BIT(NDS_RXERR)),
745 GEM_STAT_TITLE_BITS(RXTCPCCNT, "rx_tcp_checksum_errors",
746 GEM_BIT(NDS_RXERR)),
747 GEM_STAT_TITLE_BITS(RXUDPCCNT, "rx_udp_checksum_errors",
748 GEM_BIT(NDS_RXERR)),
749};
750
751#define GEM_STATS_LEN ARRAY_SIZE(gem_statistics)
752
753struct macb;
754
755struct macb_or_gem_ops {
756 int (*mog_alloc_rx_buffers)(struct macb *bp);
757 void (*mog_free_rx_buffers)(struct macb *bp);
758 void (*mog_init_rings)(struct macb *bp);
759 int (*mog_rx)(struct macb *bp, int budget);
760};
761
762struct macb_config {
763 u32 caps;
764 unsigned int dma_burst_length;
765 int (*clk_init)(struct platform_device *pdev, struct clk **pclk,
766 struct clk **hclk, struct clk **tx_clk);
767 int (*init)(struct platform_device *pdev);
768 int jumbo_max_len;
769};
770
771struct macb_queue {
772 struct macb *bp;
773 int irq;
774
775 unsigned int ISR;
776 unsigned int IER;
777 unsigned int IDR;
778 unsigned int IMR;
779 unsigned int TBQP;
780
781 unsigned int tx_head, tx_tail;
782 struct macb_dma_desc *tx_ring;
783 struct macb_tx_skb *tx_skb;
784 dma_addr_t tx_ring_dma;
785 struct work_struct tx_error_task;
786};
787
788struct macb {
789 void __iomem *regs;
790 bool native_io;
791
792
793 u32 (*macb_reg_readl)(struct macb *bp, int offset);
794 void (*macb_reg_writel)(struct macb *bp, int offset, u32 value);
795
796 unsigned int rx_tail;
797 unsigned int rx_prepared_head;
798 struct macb_dma_desc *rx_ring;
799 struct sk_buff **rx_skbuff;
800 void *rx_buffers;
801 size_t rx_buffer_size;
802
803 unsigned int num_queues;
804 unsigned int queue_mask;
805 struct macb_queue queues[MACB_MAX_QUEUES];
806
807 spinlock_t lock;
808 struct platform_device *pdev;
809 struct clk *pclk;
810 struct clk *hclk;
811 struct clk *tx_clk;
812 struct net_device *dev;
813 struct napi_struct napi;
814 struct net_device_stats stats;
815 union {
816 struct macb_stats macb;
817 struct gem_stats gem;
818 } hw_stats;
819
820 dma_addr_t rx_ring_dma;
821 dma_addr_t rx_buffers_dma;
822
823 struct macb_or_gem_ops macbgem_ops;
824
825 struct mii_bus *mii_bus;
826 int link;
827 int speed;
828 int duplex;
829
830 u32 caps;
831 unsigned int dma_burst_length;
832
833 phy_interface_t phy_interface;
834 struct gpio_desc *reset_gpio;
835
836
837 struct sk_buff *skb;
838 dma_addr_t skb_physaddr;
839 int skb_length;
840 unsigned int max_tx_length;
841
842 u64 ethtool_stats[GEM_STATS_LEN];
843
844 unsigned int rx_frm_len_mask;
845 unsigned int jumbo_max_len;
846
847 u32 wol;
848};
849
850static inline bool macb_is_gem(struct macb *bp)
851{
852 return !!(bp->caps & MACB_CAPS_MACB_IS_GEM);
853}
854
855#endif
856