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34
35#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
36
37#include <linux/bitmap.h>
38#include <linux/crc32.h>
39#include <linux/ctype.h>
40#include <linux/debugfs.h>
41#include <linux/err.h>
42#include <linux/etherdevice.h>
43#include <linux/firmware.h>
44#include <linux/if.h>
45#include <linux/if_vlan.h>
46#include <linux/init.h>
47#include <linux/log2.h>
48#include <linux/mdio.h>
49#include <linux/module.h>
50#include <linux/moduleparam.h>
51#include <linux/mutex.h>
52#include <linux/netdevice.h>
53#include <linux/pci.h>
54#include <linux/aer.h>
55#include <linux/rtnetlink.h>
56#include <linux/sched.h>
57#include <linux/seq_file.h>
58#include <linux/sockios.h>
59#include <linux/vmalloc.h>
60#include <linux/workqueue.h>
61#include <net/neighbour.h>
62#include <net/netevent.h>
63#include <net/addrconf.h>
64#include <net/bonding.h>
65#include <net/addrconf.h>
66#include <asm/uaccess.h>
67#include <linux/crash_dump.h>
68
69#include "cxgb4.h"
70#include "t4_regs.h"
71#include "t4_values.h"
72#include "t4_msg.h"
73#include "t4fw_api.h"
74#include "t4fw_version.h"
75#include "cxgb4_dcb.h"
76#include "cxgb4_debugfs.h"
77#include "clip_tbl.h"
78#include "l2t.h"
79
80char cxgb4_driver_name[] = KBUILD_MODNAME;
81
82#ifdef DRV_VERSION
83#undef DRV_VERSION
84#endif
85#define DRV_VERSION "2.0.0-ko"
86const char cxgb4_driver_version[] = DRV_VERSION;
87#define DRV_DESC "Chelsio T4/T5/T6 Network Driver"
88
89
90
91
92
93
94
95struct filter_entry {
96
97
98 u32 valid:1;
99 u32 locked:1;
100
101 u32 pending:1;
102 u32 smtidx:8;
103 struct l2t_entry *l2t;
104
105
106
107
108
109
110 struct ch_filter_specification fs;
111};
112
113#define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
114 NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
115 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
116
117
118
119#define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
120 static const struct pci_device_id cxgb4_pci_tbl[] = {
121#define CH_PCI_DEVICE_ID_FUNCTION 0x4
122
123
124
125
126#define CH_PCI_DEVICE_ID_FUNCTION2 0x0
127
128#define CH_PCI_ID_TABLE_ENTRY(devid) \
129 {PCI_VDEVICE(CHELSIO, (devid)), 4}
130
131#define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
132 { 0, } \
133 }
134
135#include "t4_pci_id_tbl.h"
136
137#define FW4_FNAME "cxgb4/t4fw.bin"
138#define FW5_FNAME "cxgb4/t5fw.bin"
139#define FW6_FNAME "cxgb4/t6fw.bin"
140#define FW4_CFNAME "cxgb4/t4-config.txt"
141#define FW5_CFNAME "cxgb4/t5-config.txt"
142#define FW6_CFNAME "cxgb4/t6-config.txt"
143#define PHY_AQ1202_FIRMWARE "cxgb4/aq1202_fw.cld"
144#define PHY_BCM84834_FIRMWARE "cxgb4/bcm8483.bin"
145#define PHY_AQ1202_DEVICEID 0x4409
146#define PHY_BCM84834_DEVICEID 0x4486
147
148MODULE_DESCRIPTION(DRV_DESC);
149MODULE_AUTHOR("Chelsio Communications");
150MODULE_LICENSE("Dual BSD/GPL");
151MODULE_VERSION(DRV_VERSION);
152MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl);
153MODULE_FIRMWARE(FW4_FNAME);
154MODULE_FIRMWARE(FW5_FNAME);
155MODULE_FIRMWARE(FW6_FNAME);
156
157
158
159
160
161
162
163static uint force_init;
164
165module_param(force_init, uint, 0644);
166MODULE_PARM_DESC(force_init, "Forcibly become Master PF and initialize adapter,"
167 "deprecated parameter");
168
169static int dflt_msg_enable = DFLT_MSG_ENABLE;
170
171module_param(dflt_msg_enable, int, 0644);
172MODULE_PARM_DESC(dflt_msg_enable, "Chelsio T4 default message enable bitmap, "
173 "deprecated parameter");
174
175
176
177
178
179
180
181
182
183
184static int msi = 2;
185
186module_param(msi, int, 0644);
187MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)");
188
189
190
191
192
193
194
195
196
197
198
199
200
201static int rx_dma_offset = 2;
202
203#ifdef CONFIG_PCI_IOV
204
205
206
207static unsigned int num_vf[NUM_OF_PF_WITH_SRIOV];
208
209module_param_array(num_vf, uint, NULL, 0644);
210MODULE_PARM_DESC(num_vf, "number of VFs for each of PFs 0-3, deprecated parameter - please use the pci sysfs interface.");
211#endif
212
213
214
215
216
217
218
219static int select_queue;
220module_param(select_queue, int, 0644);
221MODULE_PARM_DESC(select_queue,
222 "Select between kernel provided method of selecting or driver method of selecting TX queue. Default is kernel method.");
223
224static struct dentry *cxgb4_debugfs_root;
225
226static LIST_HEAD(adapter_list);
227static DEFINE_MUTEX(uld_mutex);
228
229static LIST_HEAD(adap_rcu_list);
230static DEFINE_SPINLOCK(adap_rcu_lock);
231static struct cxgb4_uld_info ulds[CXGB4_ULD_MAX];
232static const char *const uld_str[] = { "RDMA", "iSCSI", "iSCSIT" };
233
234static void link_report(struct net_device *dev)
235{
236 if (!netif_carrier_ok(dev))
237 netdev_info(dev, "link down\n");
238 else {
239 static const char *fc[] = { "no", "Rx", "Tx", "Tx/Rx" };
240
241 const char *s;
242 const struct port_info *p = netdev_priv(dev);
243
244 switch (p->link_cfg.speed) {
245 case 10000:
246 s = "10Gbps";
247 break;
248 case 1000:
249 s = "1000Mbps";
250 break;
251 case 100:
252 s = "100Mbps";
253 break;
254 case 40000:
255 s = "40Gbps";
256 break;
257 default:
258 pr_info("%s: unsupported speed: %d\n",
259 dev->name, p->link_cfg.speed);
260 return;
261 }
262
263 netdev_info(dev, "link up, %s, full-duplex, %s PAUSE\n", s,
264 fc[p->link_cfg.fc]);
265 }
266}
267
268#ifdef CONFIG_CHELSIO_T4_DCB
269
270static void dcb_tx_queue_prio_enable(struct net_device *dev, int enable)
271{
272 struct port_info *pi = netdev_priv(dev);
273 struct adapter *adap = pi->adapter;
274 struct sge_eth_txq *txq = &adap->sge.ethtxq[pi->first_qset];
275 int i;
276
277
278
279
280 for (i = 0; i < pi->nqsets; i++, txq++) {
281 u32 name, value;
282 int err;
283
284 name = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
285 FW_PARAMS_PARAM_X_V(
286 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH) |
287 FW_PARAMS_PARAM_YZ_V(txq->q.cntxt_id));
288 value = enable ? i : 0xffffffff;
289
290
291
292
293
294 err = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
295 &name, &value,
296 -FW_CMD_MAX_TIMEOUT);
297
298 if (err)
299 dev_err(adap->pdev_dev,
300 "Can't %s DCB Priority on port %d, TX Queue %d: err=%d\n",
301 enable ? "set" : "unset", pi->port_id, i, -err);
302 else
303 txq->dcb_prio = value;
304 }
305}
306#endif
307
308int cxgb4_dcb_enabled(const struct net_device *dev)
309{
310#ifdef CONFIG_CHELSIO_T4_DCB
311 struct port_info *pi = netdev_priv(dev);
312
313 if (!pi->dcb.enabled)
314 return 0;
315
316 return ((pi->dcb.state == CXGB4_DCB_STATE_FW_ALLSYNCED) ||
317 (pi->dcb.state == CXGB4_DCB_STATE_HOST));
318#else
319 return 0;
320#endif
321}
322EXPORT_SYMBOL(cxgb4_dcb_enabled);
323
324void t4_os_link_changed(struct adapter *adapter, int port_id, int link_stat)
325{
326 struct net_device *dev = adapter->port[port_id];
327
328
329 if (netif_running(dev) && link_stat != netif_carrier_ok(dev)) {
330 if (link_stat)
331 netif_carrier_on(dev);
332 else {
333#ifdef CONFIG_CHELSIO_T4_DCB
334 if (cxgb4_dcb_enabled(dev)) {
335 cxgb4_dcb_state_init(dev);
336 dcb_tx_queue_prio_enable(dev, false);
337 }
338#endif
339 netif_carrier_off(dev);
340 }
341
342 link_report(dev);
343 }
344}
345
346void t4_os_portmod_changed(const struct adapter *adap, int port_id)
347{
348 static const char *mod_str[] = {
349 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
350 };
351
352 const struct net_device *dev = adap->port[port_id];
353 const struct port_info *pi = netdev_priv(dev);
354
355 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
356 netdev_info(dev, "port module unplugged\n");
357 else if (pi->mod_type < ARRAY_SIZE(mod_str))
358 netdev_info(dev, "%s module inserted\n", mod_str[pi->mod_type]);
359 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
360 netdev_info(dev, "%s: unsupported port module inserted\n",
361 dev->name);
362 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
363 netdev_info(dev, "%s: unknown port module inserted\n",
364 dev->name);
365 else if (pi->mod_type == FW_PORT_MOD_TYPE_ERROR)
366 netdev_info(dev, "%s: transceiver module error\n", dev->name);
367 else
368 netdev_info(dev, "%s: unknown module type %d inserted\n",
369 dev->name, pi->mod_type);
370}
371
372int dbfifo_int_thresh = 10;
373module_param(dbfifo_int_thresh, int, 0644);
374MODULE_PARM_DESC(dbfifo_int_thresh, "doorbell fifo interrupt threshold");
375
376
377
378
379static int dbfifo_drain_delay = 1000;
380module_param(dbfifo_drain_delay, int, 0644);
381MODULE_PARM_DESC(dbfifo_drain_delay,
382 "usecs to sleep while draining the dbfifo");
383
384static inline int cxgb4_set_addr_hash(struct port_info *pi)
385{
386 struct adapter *adap = pi->adapter;
387 u64 vec = 0;
388 bool ucast = false;
389 struct hash_mac_addr *entry;
390
391
392 list_for_each_entry(entry, &adap->mac_hlist, list) {
393 ucast |= is_unicast_ether_addr(entry->addr);
394 vec |= (1ULL << hash_mac_addr(entry->addr));
395 }
396 return t4_set_addr_hash(adap, adap->mbox, pi->viid, ucast,
397 vec, false);
398}
399
400static int cxgb4_mac_sync(struct net_device *netdev, const u8 *mac_addr)
401{
402 struct port_info *pi = netdev_priv(netdev);
403 struct adapter *adap = pi->adapter;
404 int ret;
405 u64 mhash = 0;
406 u64 uhash = 0;
407 bool free = false;
408 bool ucast = is_unicast_ether_addr(mac_addr);
409 const u8 *maclist[1] = {mac_addr};
410 struct hash_mac_addr *new_entry;
411
412 ret = t4_alloc_mac_filt(adap, adap->mbox, pi->viid, free, 1, maclist,
413 NULL, ucast ? &uhash : &mhash, false);
414 if (ret < 0)
415 goto out;
416
417
418
419
420 if (uhash || mhash) {
421 new_entry = kzalloc(sizeof(*new_entry), GFP_ATOMIC);
422 if (!new_entry)
423 return -ENOMEM;
424 ether_addr_copy(new_entry->addr, mac_addr);
425 list_add_tail(&new_entry->list, &adap->mac_hlist);
426 ret = cxgb4_set_addr_hash(pi);
427 }
428out:
429 return ret < 0 ? ret : 0;
430}
431
432static int cxgb4_mac_unsync(struct net_device *netdev, const u8 *mac_addr)
433{
434 struct port_info *pi = netdev_priv(netdev);
435 struct adapter *adap = pi->adapter;
436 int ret;
437 const u8 *maclist[1] = {mac_addr};
438 struct hash_mac_addr *entry, *tmp;
439
440
441
442
443 list_for_each_entry_safe(entry, tmp, &adap->mac_hlist, list) {
444 if (ether_addr_equal(entry->addr, mac_addr)) {
445 list_del(&entry->list);
446 kfree(entry);
447 return cxgb4_set_addr_hash(pi);
448 }
449 }
450
451 ret = t4_free_mac_filt(adap, adap->mbox, pi->viid, 1, maclist, false);
452 return ret < 0 ? -EINVAL : 0;
453}
454
455
456
457
458
459static int set_rxmode(struct net_device *dev, int mtu, bool sleep_ok)
460{
461 struct port_info *pi = netdev_priv(dev);
462 struct adapter *adapter = pi->adapter;
463
464 __dev_uc_sync(dev, cxgb4_mac_sync, cxgb4_mac_unsync);
465 __dev_mc_sync(dev, cxgb4_mac_sync, cxgb4_mac_unsync);
466
467 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, mtu,
468 (dev->flags & IFF_PROMISC) ? 1 : 0,
469 (dev->flags & IFF_ALLMULTI) ? 1 : 0, 1, -1,
470 sleep_ok);
471}
472
473
474
475
476
477
478
479static int link_start(struct net_device *dev)
480{
481 int ret;
482 struct port_info *pi = netdev_priv(dev);
483 unsigned int mb = pi->adapter->pf;
484
485
486
487
488
489 ret = t4_set_rxmode(pi->adapter, mb, pi->viid, dev->mtu, -1, -1, -1,
490 !!(dev->features & NETIF_F_HW_VLAN_CTAG_RX), true);
491 if (ret == 0) {
492 ret = t4_change_mac(pi->adapter, mb, pi->viid,
493 pi->xact_addr_filt, dev->dev_addr, true,
494 true);
495 if (ret >= 0) {
496 pi->xact_addr_filt = ret;
497 ret = 0;
498 }
499 }
500 if (ret == 0)
501 ret = t4_link_l1cfg(pi->adapter, mb, pi->tx_chan,
502 &pi->link_cfg);
503 if (ret == 0) {
504 local_bh_disable();
505 ret = t4_enable_vi_params(pi->adapter, mb, pi->viid, true,
506 true, CXGB4_DCB_ENABLED);
507 local_bh_enable();
508 }
509
510 return ret;
511}
512
513#ifdef CONFIG_CHELSIO_T4_DCB
514
515static void dcb_rpl(struct adapter *adap, const struct fw_port_cmd *pcmd)
516{
517 int port = FW_PORT_CMD_PORTID_G(ntohl(pcmd->op_to_portid));
518 struct net_device *dev = adap->port[adap->chan_map[port]];
519 int old_dcb_enabled = cxgb4_dcb_enabled(dev);
520 int new_dcb_enabled;
521
522 cxgb4_dcb_handle_fw_update(adap, pcmd);
523 new_dcb_enabled = cxgb4_dcb_enabled(dev);
524
525
526
527
528
529 if (new_dcb_enabled != old_dcb_enabled)
530 dcb_tx_queue_prio_enable(dev, new_dcb_enabled);
531}
532#endif
533
534
535
536
537static void clear_filter(struct adapter *adap, struct filter_entry *f)
538{
539
540
541
542
543
544
545 if (f->l2t)
546 cxgb4_l2t_release(f->l2t);
547
548
549
550
551
552 memset(f, 0, sizeof(*f));
553}
554
555
556
557static void filter_rpl(struct adapter *adap, const struct cpl_set_tcb_rpl *rpl)
558{
559 unsigned int idx = GET_TID(rpl);
560 unsigned int nidx = idx - adap->tids.ftid_base;
561 unsigned int ret;
562 struct filter_entry *f;
563
564 if (idx >= adap->tids.ftid_base && nidx <
565 (adap->tids.nftids + adap->tids.nsftids)) {
566 idx = nidx;
567 ret = TCB_COOKIE_G(rpl->cookie);
568 f = &adap->tids.ftid_tab[idx];
569
570 if (ret == FW_FILTER_WR_FLT_DELETED) {
571
572
573
574 clear_filter(adap, f);
575 } else if (ret == FW_FILTER_WR_SMT_TBL_FULL) {
576 dev_err(adap->pdev_dev, "filter %u setup failed due to full SMT\n",
577 idx);
578 clear_filter(adap, f);
579 } else if (ret == FW_FILTER_WR_FLT_ADDED) {
580 f->smtidx = (be64_to_cpu(rpl->oldval) >> 24) & 0xff;
581 f->pending = 0;
582 f->valid = 1;
583 } else {
584
585
586
587 dev_err(adap->pdev_dev, "filter %u setup failed with error %u\n",
588 idx, ret);
589 clear_filter(adap, f);
590 }
591 }
592}
593
594
595
596static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
597 const struct pkt_gl *gl)
598{
599 u8 opcode = ((const struct rss_header *)rsp)->opcode;
600
601 rsp++;
602
603
604
605 if (unlikely(opcode == CPL_FW4_MSG &&
606 ((const struct cpl_fw4_msg *)rsp)->type == FW_TYPE_RSSCPL)) {
607 rsp++;
608 opcode = ((const struct rss_header *)rsp)->opcode;
609 rsp++;
610 if (opcode != CPL_SGE_EGR_UPDATE) {
611 dev_err(q->adap->pdev_dev, "unexpected FW4/CPL %#x on FW event queue\n"
612 , opcode);
613 goto out;
614 }
615 }
616
617 if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
618 const struct cpl_sge_egr_update *p = (void *)rsp;
619 unsigned int qid = EGR_QID_G(ntohl(p->opcode_qid));
620 struct sge_txq *txq;
621
622 txq = q->adap->sge.egr_map[qid - q->adap->sge.egr_start];
623 txq->restarts++;
624 if ((u8 *)txq < (u8 *)q->adap->sge.ofldtxq) {
625 struct sge_eth_txq *eq;
626
627 eq = container_of(txq, struct sge_eth_txq, q);
628 netif_tx_wake_queue(eq->txq);
629 } else {
630 struct sge_ofld_txq *oq;
631
632 oq = container_of(txq, struct sge_ofld_txq, q);
633 tasklet_schedule(&oq->qresume_tsk);
634 }
635 } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
636 const struct cpl_fw6_msg *p = (void *)rsp;
637
638#ifdef CONFIG_CHELSIO_T4_DCB
639 const struct fw_port_cmd *pcmd = (const void *)p->data;
640 unsigned int cmd = FW_CMD_OP_G(ntohl(pcmd->op_to_portid));
641 unsigned int action =
642 FW_PORT_CMD_ACTION_G(ntohl(pcmd->action_to_len16));
643
644 if (cmd == FW_PORT_CMD &&
645 action == FW_PORT_ACTION_GET_PORT_INFO) {
646 int port = FW_PORT_CMD_PORTID_G(
647 be32_to_cpu(pcmd->op_to_portid));
648 struct net_device *dev =
649 q->adap->port[q->adap->chan_map[port]];
650 int state_input = ((pcmd->u.info.dcbxdis_pkd &
651 FW_PORT_CMD_DCBXDIS_F)
652 ? CXGB4_DCB_INPUT_FW_DISABLED
653 : CXGB4_DCB_INPUT_FW_ENABLED);
654
655 cxgb4_dcb_state_fsm(dev, state_input);
656 }
657
658 if (cmd == FW_PORT_CMD &&
659 action == FW_PORT_ACTION_L2_DCB_CFG)
660 dcb_rpl(q->adap, pcmd);
661 else
662#endif
663 if (p->type == 0)
664 t4_handle_fw_rpl(q->adap, p->data);
665 } else if (opcode == CPL_L2T_WRITE_RPL) {
666 const struct cpl_l2t_write_rpl *p = (void *)rsp;
667
668 do_l2t_write_rpl(q->adap, p);
669 } else if (opcode == CPL_SET_TCB_RPL) {
670 const struct cpl_set_tcb_rpl *p = (void *)rsp;
671
672 filter_rpl(q->adap, p);
673 } else
674 dev_err(q->adap->pdev_dev,
675 "unexpected CPL %#x on FW event queue\n", opcode);
676out:
677 return 0;
678}
679
680
681static void uldrx_flush_handler(struct sge_rspq *q)
682{
683 if (ulds[q->uld].lro_flush)
684 ulds[q->uld].lro_flush(&q->lro_mgr);
685}
686
687
688
689
690
691
692
693
694
695
696static int uldrx_handler(struct sge_rspq *q, const __be64 *rsp,
697 const struct pkt_gl *gl)
698{
699 struct sge_ofld_rxq *rxq = container_of(q, struct sge_ofld_rxq, rspq);
700 int ret;
701
702
703
704 if (((const struct rss_header *)rsp)->opcode == CPL_FW4_MSG &&
705 ((const struct cpl_fw4_msg *)(rsp + 1))->type == FW_TYPE_RSSCPL)
706 rsp += 2;
707
708 if (q->flush_handler)
709 ret = ulds[q->uld].lro_rx_handler(q->adap->uld_handle[q->uld],
710 rsp, gl, &q->lro_mgr,
711 &q->napi);
712 else
713 ret = ulds[q->uld].rx_handler(q->adap->uld_handle[q->uld],
714 rsp, gl);
715
716 if (ret) {
717 rxq->stats.nomem++;
718 return -1;
719 }
720
721 if (gl == NULL)
722 rxq->stats.imm++;
723 else if (gl == CXGB4_MSG_AN)
724 rxq->stats.an++;
725 else
726 rxq->stats.pkts++;
727 return 0;
728}
729
730static void disable_msi(struct adapter *adapter)
731{
732 if (adapter->flags & USING_MSIX) {
733 pci_disable_msix(adapter->pdev);
734 adapter->flags &= ~USING_MSIX;
735 } else if (adapter->flags & USING_MSI) {
736 pci_disable_msi(adapter->pdev);
737 adapter->flags &= ~USING_MSI;
738 }
739}
740
741
742
743
744static irqreturn_t t4_nondata_intr(int irq, void *cookie)
745{
746 struct adapter *adap = cookie;
747 u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A));
748
749 if (v & PFSW_F) {
750 adap->swintr = 1;
751 t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A), v);
752 }
753 if (adap->flags & MASTER_PF)
754 t4_slow_intr_handler(adap);
755 return IRQ_HANDLED;
756}
757
758
759
760
761static void name_msix_vecs(struct adapter *adap)
762{
763 int i, j, msi_idx = 2, n = sizeof(adap->msix_info[0].desc);
764
765
766 snprintf(adap->msix_info[0].desc, n, "%s", adap->port[0]->name);
767
768
769 snprintf(adap->msix_info[1].desc, n, "%s-FWeventq",
770 adap->port[0]->name);
771
772
773 for_each_port(adap, j) {
774 struct net_device *d = adap->port[j];
775 const struct port_info *pi = netdev_priv(d);
776
777 for (i = 0; i < pi->nqsets; i++, msi_idx++)
778 snprintf(adap->msix_info[msi_idx].desc, n, "%s-Rx%d",
779 d->name, i);
780 }
781
782
783 for_each_iscsirxq(&adap->sge, i)
784 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-iscsi%d",
785 adap->port[0]->name, i);
786
787 for_each_iscsitrxq(&adap->sge, i)
788 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-iSCSIT%d",
789 adap->port[0]->name, i);
790
791 for_each_rdmarxq(&adap->sge, i)
792 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-rdma%d",
793 adap->port[0]->name, i);
794
795 for_each_rdmaciq(&adap->sge, i)
796 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-rdma-ciq%d",
797 adap->port[0]->name, i);
798}
799
800static int request_msix_queue_irqs(struct adapter *adap)
801{
802 struct sge *s = &adap->sge;
803 int err, ethqidx, iscsiqidx = 0, rdmaqidx = 0, rdmaciqqidx = 0;
804 int iscsitqidx = 0;
805 int msi_index = 2;
806
807 err = request_irq(adap->msix_info[1].vec, t4_sge_intr_msix, 0,
808 adap->msix_info[1].desc, &s->fw_evtq);
809 if (err)
810 return err;
811
812 for_each_ethrxq(s, ethqidx) {
813 err = request_irq(adap->msix_info[msi_index].vec,
814 t4_sge_intr_msix, 0,
815 adap->msix_info[msi_index].desc,
816 &s->ethrxq[ethqidx].rspq);
817 if (err)
818 goto unwind;
819 msi_index++;
820 }
821 for_each_iscsirxq(s, iscsiqidx) {
822 err = request_irq(adap->msix_info[msi_index].vec,
823 t4_sge_intr_msix, 0,
824 adap->msix_info[msi_index].desc,
825 &s->iscsirxq[iscsiqidx].rspq);
826 if (err)
827 goto unwind;
828 msi_index++;
829 }
830 for_each_iscsitrxq(s, iscsitqidx) {
831 err = request_irq(adap->msix_info[msi_index].vec,
832 t4_sge_intr_msix, 0,
833 adap->msix_info[msi_index].desc,
834 &s->iscsitrxq[iscsitqidx].rspq);
835 if (err)
836 goto unwind;
837 msi_index++;
838 }
839 for_each_rdmarxq(s, rdmaqidx) {
840 err = request_irq(adap->msix_info[msi_index].vec,
841 t4_sge_intr_msix, 0,
842 adap->msix_info[msi_index].desc,
843 &s->rdmarxq[rdmaqidx].rspq);
844 if (err)
845 goto unwind;
846 msi_index++;
847 }
848 for_each_rdmaciq(s, rdmaciqqidx) {
849 err = request_irq(adap->msix_info[msi_index].vec,
850 t4_sge_intr_msix, 0,
851 adap->msix_info[msi_index].desc,
852 &s->rdmaciq[rdmaciqqidx].rspq);
853 if (err)
854 goto unwind;
855 msi_index++;
856 }
857 return 0;
858
859unwind:
860 while (--rdmaciqqidx >= 0)
861 free_irq(adap->msix_info[--msi_index].vec,
862 &s->rdmaciq[rdmaciqqidx].rspq);
863 while (--rdmaqidx >= 0)
864 free_irq(adap->msix_info[--msi_index].vec,
865 &s->rdmarxq[rdmaqidx].rspq);
866 while (--iscsitqidx >= 0)
867 free_irq(adap->msix_info[--msi_index].vec,
868 &s->iscsitrxq[iscsitqidx].rspq);
869 while (--iscsiqidx >= 0)
870 free_irq(adap->msix_info[--msi_index].vec,
871 &s->iscsirxq[iscsiqidx].rspq);
872 while (--ethqidx >= 0)
873 free_irq(adap->msix_info[--msi_index].vec,
874 &s->ethrxq[ethqidx].rspq);
875 free_irq(adap->msix_info[1].vec, &s->fw_evtq);
876 return err;
877}
878
879static void free_msix_queue_irqs(struct adapter *adap)
880{
881 int i, msi_index = 2;
882 struct sge *s = &adap->sge;
883
884 free_irq(adap->msix_info[1].vec, &s->fw_evtq);
885 for_each_ethrxq(s, i)
886 free_irq(adap->msix_info[msi_index++].vec, &s->ethrxq[i].rspq);
887 for_each_iscsirxq(s, i)
888 free_irq(adap->msix_info[msi_index++].vec,
889 &s->iscsirxq[i].rspq);
890 for_each_iscsitrxq(s, i)
891 free_irq(adap->msix_info[msi_index++].vec,
892 &s->iscsitrxq[i].rspq);
893 for_each_rdmarxq(s, i)
894 free_irq(adap->msix_info[msi_index++].vec, &s->rdmarxq[i].rspq);
895 for_each_rdmaciq(s, i)
896 free_irq(adap->msix_info[msi_index++].vec, &s->rdmaciq[i].rspq);
897}
898
899
900
901
902
903
904
905
906
907
908int cxgb4_write_rss(const struct port_info *pi, const u16 *queues)
909{
910 u16 *rss;
911 int i, err;
912 struct adapter *adapter = pi->adapter;
913 const struct sge_eth_rxq *rxq;
914
915 rxq = &adapter->sge.ethrxq[pi->first_qset];
916 rss = kmalloc(pi->rss_size * sizeof(u16), GFP_KERNEL);
917 if (!rss)
918 return -ENOMEM;
919
920
921 for (i = 0; i < pi->rss_size; i++, queues++)
922 rss[i] = rxq[*queues].rspq.abs_id;
923
924 err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0,
925 pi->rss_size, rss, pi->rss_size);
926
927
928
929
930
931 if (!err)
932 err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid,
933 FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F |
934 FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F |
935 FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F |
936 FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F |
937 FW_RSS_VI_CONFIG_CMD_UDPEN_F,
938 rss[0]);
939 kfree(rss);
940 return err;
941}
942
943
944
945
946
947
948
949static int setup_rss(struct adapter *adap)
950{
951 int i, j, err;
952
953 for_each_port(adap, i) {
954 const struct port_info *pi = adap2pinfo(adap, i);
955
956
957 for (j = 0; j < pi->rss_size; j++)
958 pi->rss[j] = j % pi->nqsets;
959
960 err = cxgb4_write_rss(pi, pi->rss);
961 if (err)
962 return err;
963 }
964 return 0;
965}
966
967
968
969
970static unsigned int rxq_to_chan(const struct sge *p, unsigned int qid)
971{
972 qid -= p->ingr_start;
973 return netdev2pinfo(p->ingr_map[qid]->netdev)->tx_chan;
974}
975
976
977
978
979static void quiesce_rx(struct adapter *adap)
980{
981 int i;
982
983 for (i = 0; i < adap->sge.ingr_sz; i++) {
984 struct sge_rspq *q = adap->sge.ingr_map[i];
985
986 if (q && q->handler) {
987 napi_disable(&q->napi);
988 local_bh_disable();
989 while (!cxgb_poll_lock_napi(q))
990 mdelay(1);
991 local_bh_enable();
992 }
993
994 }
995}
996
997
998static void disable_interrupts(struct adapter *adap)
999{
1000 if (adap->flags & FULL_INIT_DONE) {
1001 t4_intr_disable(adap);
1002 if (adap->flags & USING_MSIX) {
1003 free_msix_queue_irqs(adap);
1004 free_irq(adap->msix_info[0].vec, adap);
1005 } else {
1006 free_irq(adap->pdev->irq, adap);
1007 }
1008 quiesce_rx(adap);
1009 }
1010}
1011
1012
1013
1014
1015static void enable_rx(struct adapter *adap)
1016{
1017 int i;
1018
1019 for (i = 0; i < adap->sge.ingr_sz; i++) {
1020 struct sge_rspq *q = adap->sge.ingr_map[i];
1021
1022 if (!q)
1023 continue;
1024 if (q->handler) {
1025 cxgb_busy_poll_init_lock(q);
1026 napi_enable(&q->napi);
1027 }
1028
1029 t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A),
1030 SEINTARM_V(q->intr_params) |
1031 INGRESSQID_V(q->cntxt_id));
1032 }
1033}
1034
1035static int alloc_ofld_rxqs(struct adapter *adap, struct sge_ofld_rxq *q,
1036 unsigned int nq, unsigned int per_chan, int msi_idx,
1037 u16 *ids, bool lro)
1038{
1039 int i, err;
1040
1041 for (i = 0; i < nq; i++, q++) {
1042 if (msi_idx > 0)
1043 msi_idx++;
1044 err = t4_sge_alloc_rxq(adap, &q->rspq, false,
1045 adap->port[i / per_chan],
1046 msi_idx, q->fl.size ? &q->fl : NULL,
1047 uldrx_handler,
1048 lro ? uldrx_flush_handler : NULL,
1049 0);
1050 if (err)
1051 return err;
1052 memset(&q->stats, 0, sizeof(q->stats));
1053 if (ids)
1054 ids[i] = q->rspq.abs_id;
1055 }
1056 return 0;
1057}
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067static int setup_sge_queues(struct adapter *adap)
1068{
1069 int err, msi_idx, i, j;
1070 struct sge *s = &adap->sge;
1071
1072 bitmap_zero(s->starving_fl, s->egr_sz);
1073 bitmap_zero(s->txq_maperr, s->egr_sz);
1074
1075 if (adap->flags & USING_MSIX)
1076 msi_idx = 1;
1077 else {
1078 err = t4_sge_alloc_rxq(adap, &s->intrq, false, adap->port[0], 0,
1079 NULL, NULL, NULL, -1);
1080 if (err)
1081 return err;
1082 msi_idx = -((int)s->intrq.abs_id + 1);
1083 }
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098 err = t4_sge_alloc_rxq(adap, &s->fw_evtq, true, adap->port[0],
1099 msi_idx, NULL, fwevtq_handler, NULL, -1);
1100 if (err) {
1101freeout: t4_free_sge_resources(adap);
1102 return err;
1103 }
1104
1105 for_each_port(adap, i) {
1106 struct net_device *dev = adap->port[i];
1107 struct port_info *pi = netdev_priv(dev);
1108 struct sge_eth_rxq *q = &s->ethrxq[pi->first_qset];
1109 struct sge_eth_txq *t = &s->ethtxq[pi->first_qset];
1110
1111 for (j = 0; j < pi->nqsets; j++, q++) {
1112 if (msi_idx > 0)
1113 msi_idx++;
1114 err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev,
1115 msi_idx, &q->fl,
1116 t4_ethrx_handler,
1117 NULL,
1118 t4_get_mps_bg_map(adap,
1119 pi->tx_chan));
1120 if (err)
1121 goto freeout;
1122 q->rspq.idx = j;
1123 memset(&q->stats, 0, sizeof(q->stats));
1124 }
1125 for (j = 0; j < pi->nqsets; j++, t++) {
1126 err = t4_sge_alloc_eth_txq(adap, t, dev,
1127 netdev_get_tx_queue(dev, j),
1128 s->fw_evtq.cntxt_id);
1129 if (err)
1130 goto freeout;
1131 }
1132 }
1133
1134 j = s->iscsiqsets / adap->params.nports;
1135 for_each_iscsirxq(s, i) {
1136 err = t4_sge_alloc_ofld_txq(adap, &s->ofldtxq[i],
1137 adap->port[i / j],
1138 s->fw_evtq.cntxt_id);
1139 if (err)
1140 goto freeout;
1141 }
1142
1143#define ALLOC_OFLD_RXQS(firstq, nq, per_chan, ids, lro) do { \
1144 err = alloc_ofld_rxqs(adap, firstq, nq, per_chan, msi_idx, ids, lro); \
1145 if (err) \
1146 goto freeout; \
1147 if (msi_idx > 0) \
1148 msi_idx += nq; \
1149} while (0)
1150
1151 ALLOC_OFLD_RXQS(s->iscsirxq, s->iscsiqsets, j, s->iscsi_rxq, false);
1152 ALLOC_OFLD_RXQS(s->iscsitrxq, s->niscsitq, j, s->iscsit_rxq, true);
1153 ALLOC_OFLD_RXQS(s->rdmarxq, s->rdmaqs, 1, s->rdma_rxq, false);
1154 j = s->rdmaciqs / adap->params.nports;
1155 ALLOC_OFLD_RXQS(s->rdmaciq, s->rdmaciqs, j, s->rdma_ciq, false);
1156
1157#undef ALLOC_OFLD_RXQS
1158
1159 for_each_port(adap, i) {
1160
1161
1162
1163
1164 err = t4_sge_alloc_ctrl_txq(adap, &s->ctrlq[i], adap->port[i],
1165 s->fw_evtq.cntxt_id,
1166 s->rdmarxq[i].rspq.cntxt_id);
1167 if (err)
1168 goto freeout;
1169 }
1170
1171 t4_write_reg(adap, is_t4(adap->params.chip) ?
1172 MPS_TRC_RSS_CONTROL_A :
1173 MPS_T5_TRC_RSS_CONTROL_A,
1174 RSSCONTROL_V(netdev2pinfo(adap->port[0])->tx_chan) |
1175 QUEUENUMBER_V(s->ethrxq[0].rspq.abs_id));
1176 return 0;
1177}
1178
1179
1180
1181
1182
1183void *t4_alloc_mem(size_t size)
1184{
1185 void *p = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
1186
1187 if (!p)
1188 p = vzalloc(size);
1189 return p;
1190}
1191
1192
1193
1194
1195void t4_free_mem(void *addr)
1196{
1197 kvfree(addr);
1198}
1199
1200
1201
1202
1203
1204
1205
1206static int set_filter_wr(struct adapter *adapter, int fidx)
1207{
1208 struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
1209 struct sk_buff *skb;
1210 struct fw_filter_wr *fwr;
1211 unsigned int ftid;
1212
1213 skb = alloc_skb(sizeof(*fwr), GFP_KERNEL);
1214 if (!skb)
1215 return -ENOMEM;
1216
1217
1218
1219
1220
1221 if (f->fs.newdmac || f->fs.newvlan) {
1222
1223 f->l2t = t4_l2t_alloc_switching(adapter, f->fs.vlan,
1224 f->fs.eport, f->fs.dmac);
1225 if (f->l2t == NULL) {
1226 kfree_skb(skb);
1227 return -ENOMEM;
1228 }
1229 }
1230
1231 ftid = adapter->tids.ftid_base + fidx;
1232
1233 fwr = (struct fw_filter_wr *)__skb_put(skb, sizeof(*fwr));
1234 memset(fwr, 0, sizeof(*fwr));
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244 fwr->op_pkd = htonl(FW_WR_OP_V(FW_FILTER_WR));
1245 fwr->len16_pkd = htonl(FW_WR_LEN16_V(sizeof(*fwr)/16));
1246 fwr->tid_to_iq =
1247 htonl(FW_FILTER_WR_TID_V(ftid) |
1248 FW_FILTER_WR_RQTYPE_V(f->fs.type) |
1249 FW_FILTER_WR_NOREPLY_V(0) |
1250 FW_FILTER_WR_IQ_V(f->fs.iq));
1251 fwr->del_filter_to_l2tix =
1252 htonl(FW_FILTER_WR_RPTTID_V(f->fs.rpttid) |
1253 FW_FILTER_WR_DROP_V(f->fs.action == FILTER_DROP) |
1254 FW_FILTER_WR_DIRSTEER_V(f->fs.dirsteer) |
1255 FW_FILTER_WR_MASKHASH_V(f->fs.maskhash) |
1256 FW_FILTER_WR_DIRSTEERHASH_V(f->fs.dirsteerhash) |
1257 FW_FILTER_WR_LPBK_V(f->fs.action == FILTER_SWITCH) |
1258 FW_FILTER_WR_DMAC_V(f->fs.newdmac) |
1259 FW_FILTER_WR_SMAC_V(f->fs.newsmac) |
1260 FW_FILTER_WR_INSVLAN_V(f->fs.newvlan == VLAN_INSERT ||
1261 f->fs.newvlan == VLAN_REWRITE) |
1262 FW_FILTER_WR_RMVLAN_V(f->fs.newvlan == VLAN_REMOVE ||
1263 f->fs.newvlan == VLAN_REWRITE) |
1264 FW_FILTER_WR_HITCNTS_V(f->fs.hitcnts) |
1265 FW_FILTER_WR_TXCHAN_V(f->fs.eport) |
1266 FW_FILTER_WR_PRIO_V(f->fs.prio) |
1267 FW_FILTER_WR_L2TIX_V(f->l2t ? f->l2t->idx : 0));
1268 fwr->ethtype = htons(f->fs.val.ethtype);
1269 fwr->ethtypem = htons(f->fs.mask.ethtype);
1270 fwr->frag_to_ovlan_vldm =
1271 (FW_FILTER_WR_FRAG_V(f->fs.val.frag) |
1272 FW_FILTER_WR_FRAGM_V(f->fs.mask.frag) |
1273 FW_FILTER_WR_IVLAN_VLD_V(f->fs.val.ivlan_vld) |
1274 FW_FILTER_WR_OVLAN_VLD_V(f->fs.val.ovlan_vld) |
1275 FW_FILTER_WR_IVLAN_VLDM_V(f->fs.mask.ivlan_vld) |
1276 FW_FILTER_WR_OVLAN_VLDM_V(f->fs.mask.ovlan_vld));
1277 fwr->smac_sel = 0;
1278 fwr->rx_chan_rx_rpl_iq =
1279 htons(FW_FILTER_WR_RX_CHAN_V(0) |
1280 FW_FILTER_WR_RX_RPL_IQ_V(adapter->sge.fw_evtq.abs_id));
1281 fwr->maci_to_matchtypem =
1282 htonl(FW_FILTER_WR_MACI_V(f->fs.val.macidx) |
1283 FW_FILTER_WR_MACIM_V(f->fs.mask.macidx) |
1284 FW_FILTER_WR_FCOE_V(f->fs.val.fcoe) |
1285 FW_FILTER_WR_FCOEM_V(f->fs.mask.fcoe) |
1286 FW_FILTER_WR_PORT_V(f->fs.val.iport) |
1287 FW_FILTER_WR_PORTM_V(f->fs.mask.iport) |
1288 FW_FILTER_WR_MATCHTYPE_V(f->fs.val.matchtype) |
1289 FW_FILTER_WR_MATCHTYPEM_V(f->fs.mask.matchtype));
1290 fwr->ptcl = f->fs.val.proto;
1291 fwr->ptclm = f->fs.mask.proto;
1292 fwr->ttyp = f->fs.val.tos;
1293 fwr->ttypm = f->fs.mask.tos;
1294 fwr->ivlan = htons(f->fs.val.ivlan);
1295 fwr->ivlanm = htons(f->fs.mask.ivlan);
1296 fwr->ovlan = htons(f->fs.val.ovlan);
1297 fwr->ovlanm = htons(f->fs.mask.ovlan);
1298 memcpy(fwr->lip, f->fs.val.lip, sizeof(fwr->lip));
1299 memcpy(fwr->lipm, f->fs.mask.lip, sizeof(fwr->lipm));
1300 memcpy(fwr->fip, f->fs.val.fip, sizeof(fwr->fip));
1301 memcpy(fwr->fipm, f->fs.mask.fip, sizeof(fwr->fipm));
1302 fwr->lp = htons(f->fs.val.lport);
1303 fwr->lpm = htons(f->fs.mask.lport);
1304 fwr->fp = htons(f->fs.val.fport);
1305 fwr->fpm = htons(f->fs.mask.fport);
1306 if (f->fs.newsmac)
1307 memcpy(fwr->sma, f->fs.smac, sizeof(fwr->sma));
1308
1309
1310
1311
1312 f->pending = 1;
1313 set_wr_txq(skb, CPL_PRIORITY_CONTROL, f->fs.val.iport & 0x3);
1314 t4_ofld_send(adapter, skb);
1315 return 0;
1316}
1317
1318
1319
1320static int del_filter_wr(struct adapter *adapter, int fidx)
1321{
1322 struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
1323 struct sk_buff *skb;
1324 struct fw_filter_wr *fwr;
1325 unsigned int len, ftid;
1326
1327 len = sizeof(*fwr);
1328 ftid = adapter->tids.ftid_base + fidx;
1329
1330 skb = alloc_skb(len, GFP_KERNEL);
1331 if (!skb)
1332 return -ENOMEM;
1333
1334 fwr = (struct fw_filter_wr *)__skb_put(skb, len);
1335 t4_mk_filtdelwr(ftid, fwr, adapter->sge.fw_evtq.abs_id);
1336
1337
1338
1339
1340 f->pending = 1;
1341 t4_mgmt_tx(adapter, skb);
1342 return 0;
1343}
1344
1345static u16 cxgb_select_queue(struct net_device *dev, struct sk_buff *skb,
1346 void *accel_priv, select_queue_fallback_t fallback)
1347{
1348 int txq;
1349
1350#ifdef CONFIG_CHELSIO_T4_DCB
1351
1352
1353
1354
1355
1356 if (cxgb4_dcb_enabled(dev)) {
1357 u16 vlan_tci;
1358 int err;
1359
1360 err = vlan_get_tag(skb, &vlan_tci);
1361 if (unlikely(err)) {
1362 if (net_ratelimit())
1363 netdev_warn(dev,
1364 "TX Packet without VLAN Tag on DCB Link\n");
1365 txq = 0;
1366 } else {
1367 txq = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT;
1368#ifdef CONFIG_CHELSIO_T4_FCOE
1369 if (skb->protocol == htons(ETH_P_FCOE))
1370 txq = skb->priority & 0x7;
1371#endif
1372 }
1373 return txq;
1374 }
1375#endif
1376
1377 if (select_queue) {
1378 txq = (skb_rx_queue_recorded(skb)
1379 ? skb_get_rx_queue(skb)
1380 : smp_processor_id());
1381
1382 while (unlikely(txq >= dev->real_num_tx_queues))
1383 txq -= dev->real_num_tx_queues;
1384
1385 return txq;
1386 }
1387
1388 return fallback(dev, skb) % dev->real_num_tx_queues;
1389}
1390
1391static int closest_timer(const struct sge *s, int time)
1392{
1393 int i, delta, match = 0, min_delta = INT_MAX;
1394
1395 for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
1396 delta = time - s->timer_val[i];
1397 if (delta < 0)
1398 delta = -delta;
1399 if (delta < min_delta) {
1400 min_delta = delta;
1401 match = i;
1402 }
1403 }
1404 return match;
1405}
1406
1407static int closest_thres(const struct sge *s, int thres)
1408{
1409 int i, delta, match = 0, min_delta = INT_MAX;
1410
1411 for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
1412 delta = thres - s->counter_val[i];
1413 if (delta < 0)
1414 delta = -delta;
1415 if (delta < min_delta) {
1416 min_delta = delta;
1417 match = i;
1418 }
1419 }
1420 return match;
1421}
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432int cxgb4_set_rspq_intr_params(struct sge_rspq *q,
1433 unsigned int us, unsigned int cnt)
1434{
1435 struct adapter *adap = q->adap;
1436
1437 if ((us | cnt) == 0)
1438 cnt = 1;
1439
1440 if (cnt) {
1441 int err;
1442 u32 v, new_idx;
1443
1444 new_idx = closest_thres(&adap->sge, cnt);
1445 if (q->desc && q->pktcnt_idx != new_idx) {
1446
1447 v = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
1448 FW_PARAMS_PARAM_X_V(
1449 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
1450 FW_PARAMS_PARAM_YZ_V(q->cntxt_id);
1451 err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,
1452 &v, &new_idx);
1453 if (err)
1454 return err;
1455 }
1456 q->pktcnt_idx = new_idx;
1457 }
1458
1459 us = us == 0 ? 6 : closest_timer(&adap->sge, us);
1460 q->intr_params = QINTR_TIMER_IDX_V(us) | QINTR_CNT_EN_V(cnt > 0);
1461 return 0;
1462}
1463
1464static int cxgb_set_features(struct net_device *dev, netdev_features_t features)
1465{
1466 const struct port_info *pi = netdev_priv(dev);
1467 netdev_features_t changed = dev->features ^ features;
1468 int err;
1469
1470 if (!(changed & NETIF_F_HW_VLAN_CTAG_RX))
1471 return 0;
1472
1473 err = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, -1,
1474 -1, -1, -1,
1475 !!(features & NETIF_F_HW_VLAN_CTAG_RX), true);
1476 if (unlikely(err))
1477 dev->features = features ^ NETIF_F_HW_VLAN_CTAG_RX;
1478 return err;
1479}
1480
1481static int setup_debugfs(struct adapter *adap)
1482{
1483 if (IS_ERR_OR_NULL(adap->debugfs_root))
1484 return -1;
1485
1486#ifdef CONFIG_DEBUG_FS
1487 t4_setup_debugfs(adap);
1488#endif
1489 return 0;
1490}
1491
1492
1493
1494
1495
1496
1497
1498
1499int cxgb4_alloc_atid(struct tid_info *t, void *data)
1500{
1501 int atid = -1;
1502
1503 spin_lock_bh(&t->atid_lock);
1504 if (t->afree) {
1505 union aopen_entry *p = t->afree;
1506
1507 atid = (p - t->atid_tab) + t->atid_base;
1508 t->afree = p->next;
1509 p->data = data;
1510 t->atids_in_use++;
1511 }
1512 spin_unlock_bh(&t->atid_lock);
1513 return atid;
1514}
1515EXPORT_SYMBOL(cxgb4_alloc_atid);
1516
1517
1518
1519
1520void cxgb4_free_atid(struct tid_info *t, unsigned int atid)
1521{
1522 union aopen_entry *p = &t->atid_tab[atid - t->atid_base];
1523
1524 spin_lock_bh(&t->atid_lock);
1525 p->next = t->afree;
1526 t->afree = p;
1527 t->atids_in_use--;
1528 spin_unlock_bh(&t->atid_lock);
1529}
1530EXPORT_SYMBOL(cxgb4_free_atid);
1531
1532
1533
1534
1535int cxgb4_alloc_stid(struct tid_info *t, int family, void *data)
1536{
1537 int stid;
1538
1539 spin_lock_bh(&t->stid_lock);
1540 if (family == PF_INET) {
1541 stid = find_first_zero_bit(t->stid_bmap, t->nstids);
1542 if (stid < t->nstids)
1543 __set_bit(stid, t->stid_bmap);
1544 else
1545 stid = -1;
1546 } else {
1547 stid = bitmap_find_free_region(t->stid_bmap, t->nstids, 1);
1548 if (stid < 0)
1549 stid = -1;
1550 }
1551 if (stid >= 0) {
1552 t->stid_tab[stid].data = data;
1553 stid += t->stid_base;
1554
1555
1556
1557
1558 if (family == PF_INET)
1559 t->stids_in_use++;
1560 else
1561 t->stids_in_use += 2;
1562 }
1563 spin_unlock_bh(&t->stid_lock);
1564 return stid;
1565}
1566EXPORT_SYMBOL(cxgb4_alloc_stid);
1567
1568
1569
1570int cxgb4_alloc_sftid(struct tid_info *t, int family, void *data)
1571{
1572 int stid;
1573
1574 spin_lock_bh(&t->stid_lock);
1575 if (family == PF_INET) {
1576 stid = find_next_zero_bit(t->stid_bmap,
1577 t->nstids + t->nsftids, t->nstids);
1578 if (stid < (t->nstids + t->nsftids))
1579 __set_bit(stid, t->stid_bmap);
1580 else
1581 stid = -1;
1582 } else {
1583 stid = -1;
1584 }
1585 if (stid >= 0) {
1586 t->stid_tab[stid].data = data;
1587 stid -= t->nstids;
1588 stid += t->sftid_base;
1589 t->sftids_in_use++;
1590 }
1591 spin_unlock_bh(&t->stid_lock);
1592 return stid;
1593}
1594EXPORT_SYMBOL(cxgb4_alloc_sftid);
1595
1596
1597
1598void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family)
1599{
1600
1601 if (t->nsftids && (stid >= t->sftid_base)) {
1602 stid -= t->sftid_base;
1603 stid += t->nstids;
1604 } else {
1605 stid -= t->stid_base;
1606 }
1607
1608 spin_lock_bh(&t->stid_lock);
1609 if (family == PF_INET)
1610 __clear_bit(stid, t->stid_bmap);
1611 else
1612 bitmap_release_region(t->stid_bmap, stid, 1);
1613 t->stid_tab[stid].data = NULL;
1614 if (stid < t->nstids) {
1615 if (family == PF_INET)
1616 t->stids_in_use--;
1617 else
1618 t->stids_in_use -= 2;
1619 } else {
1620 t->sftids_in_use--;
1621 }
1622 spin_unlock_bh(&t->stid_lock);
1623}
1624EXPORT_SYMBOL(cxgb4_free_stid);
1625
1626
1627
1628
1629static void mk_tid_release(struct sk_buff *skb, unsigned int chan,
1630 unsigned int tid)
1631{
1632 struct cpl_tid_release *req;
1633
1634 set_wr_txq(skb, CPL_PRIORITY_SETUP, chan);
1635 req = (struct cpl_tid_release *)__skb_put(skb, sizeof(*req));
1636 INIT_TP_WR(req, tid);
1637 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, tid));
1638}
1639
1640
1641
1642
1643
1644static void cxgb4_queue_tid_release(struct tid_info *t, unsigned int chan,
1645 unsigned int tid)
1646{
1647 void **p = &t->tid_tab[tid];
1648 struct adapter *adap = container_of(t, struct adapter, tids);
1649
1650 spin_lock_bh(&adap->tid_release_lock);
1651 *p = adap->tid_release_head;
1652
1653 adap->tid_release_head = (void **)((uintptr_t)p | chan);
1654 if (!adap->tid_release_task_busy) {
1655 adap->tid_release_task_busy = true;
1656 queue_work(adap->workq, &adap->tid_release_task);
1657 }
1658 spin_unlock_bh(&adap->tid_release_lock);
1659}
1660
1661
1662
1663
1664static void process_tid_release_list(struct work_struct *work)
1665{
1666 struct sk_buff *skb;
1667 struct adapter *adap;
1668
1669 adap = container_of(work, struct adapter, tid_release_task);
1670
1671 spin_lock_bh(&adap->tid_release_lock);
1672 while (adap->tid_release_head) {
1673 void **p = adap->tid_release_head;
1674 unsigned int chan = (uintptr_t)p & 3;
1675 p = (void *)p - chan;
1676
1677 adap->tid_release_head = *p;
1678 *p = NULL;
1679 spin_unlock_bh(&adap->tid_release_lock);
1680
1681 while (!(skb = alloc_skb(sizeof(struct cpl_tid_release),
1682 GFP_KERNEL)))
1683 schedule_timeout_uninterruptible(1);
1684
1685 mk_tid_release(skb, chan, p - adap->tids.tid_tab);
1686 t4_ofld_send(adap, skb);
1687 spin_lock_bh(&adap->tid_release_lock);
1688 }
1689 adap->tid_release_task_busy = false;
1690 spin_unlock_bh(&adap->tid_release_lock);
1691}
1692
1693
1694
1695
1696
1697void cxgb4_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid)
1698{
1699 struct sk_buff *skb;
1700 struct adapter *adap = container_of(t, struct adapter, tids);
1701
1702 WARN_ON(tid >= t->ntids);
1703
1704 if (t->tid_tab[tid]) {
1705 t->tid_tab[tid] = NULL;
1706 if (t->hash_base && (tid >= t->hash_base))
1707 atomic_dec(&t->hash_tids_in_use);
1708 else
1709 atomic_dec(&t->tids_in_use);
1710 }
1711
1712 skb = alloc_skb(sizeof(struct cpl_tid_release), GFP_ATOMIC);
1713 if (likely(skb)) {
1714 mk_tid_release(skb, chan, tid);
1715 t4_ofld_send(adap, skb);
1716 } else
1717 cxgb4_queue_tid_release(t, chan, tid);
1718}
1719EXPORT_SYMBOL(cxgb4_remove_tid);
1720
1721
1722
1723
1724static int tid_init(struct tid_info *t)
1725{
1726 size_t size;
1727 unsigned int stid_bmap_size;
1728 unsigned int natids = t->natids;
1729 struct adapter *adap = container_of(t, struct adapter, tids);
1730
1731 stid_bmap_size = BITS_TO_LONGS(t->nstids + t->nsftids);
1732 size = t->ntids * sizeof(*t->tid_tab) +
1733 natids * sizeof(*t->atid_tab) +
1734 t->nstids * sizeof(*t->stid_tab) +
1735 t->nsftids * sizeof(*t->stid_tab) +
1736 stid_bmap_size * sizeof(long) +
1737 t->nftids * sizeof(*t->ftid_tab) +
1738 t->nsftids * sizeof(*t->ftid_tab);
1739
1740 t->tid_tab = t4_alloc_mem(size);
1741 if (!t->tid_tab)
1742 return -ENOMEM;
1743
1744 t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids];
1745 t->stid_tab = (struct serv_entry *)&t->atid_tab[natids];
1746 t->stid_bmap = (unsigned long *)&t->stid_tab[t->nstids + t->nsftids];
1747 t->ftid_tab = (struct filter_entry *)&t->stid_bmap[stid_bmap_size];
1748 spin_lock_init(&t->stid_lock);
1749 spin_lock_init(&t->atid_lock);
1750
1751 t->stids_in_use = 0;
1752 t->sftids_in_use = 0;
1753 t->afree = NULL;
1754 t->atids_in_use = 0;
1755 atomic_set(&t->tids_in_use, 0);
1756 atomic_set(&t->hash_tids_in_use, 0);
1757
1758
1759 if (natids) {
1760 while (--natids)
1761 t->atid_tab[natids - 1].next = &t->atid_tab[natids];
1762 t->afree = t->atid_tab;
1763 }
1764 bitmap_zero(t->stid_bmap, t->nstids + t->nsftids);
1765
1766 if (!t->stid_base &&
1767 (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5))
1768 __set_bit(0, t->stid_bmap);
1769
1770 return 0;
1771}
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784int cxgb4_create_server(const struct net_device *dev, unsigned int stid,
1785 __be32 sip, __be16 sport, __be16 vlan,
1786 unsigned int queue)
1787{
1788 unsigned int chan;
1789 struct sk_buff *skb;
1790 struct adapter *adap;
1791 struct cpl_pass_open_req *req;
1792 int ret;
1793
1794 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1795 if (!skb)
1796 return -ENOMEM;
1797
1798 adap = netdev2adap(dev);
1799 req = (struct cpl_pass_open_req *)__skb_put(skb, sizeof(*req));
1800 INIT_TP_WR(req, 0);
1801 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ, stid));
1802 req->local_port = sport;
1803 req->peer_port = htons(0);
1804 req->local_ip = sip;
1805 req->peer_ip = htonl(0);
1806 chan = rxq_to_chan(&adap->sge, queue);
1807 req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
1808 req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) |
1809 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue));
1810 ret = t4_mgmt_tx(adap, skb);
1811 return net_xmit_eval(ret);
1812}
1813EXPORT_SYMBOL(cxgb4_create_server);
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825int cxgb4_create_server6(const struct net_device *dev, unsigned int stid,
1826 const struct in6_addr *sip, __be16 sport,
1827 unsigned int queue)
1828{
1829 unsigned int chan;
1830 struct sk_buff *skb;
1831 struct adapter *adap;
1832 struct cpl_pass_open_req6 *req;
1833 int ret;
1834
1835 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1836 if (!skb)
1837 return -ENOMEM;
1838
1839 adap = netdev2adap(dev);
1840 req = (struct cpl_pass_open_req6 *)__skb_put(skb, sizeof(*req));
1841 INIT_TP_WR(req, 0);
1842 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ6, stid));
1843 req->local_port = sport;
1844 req->peer_port = htons(0);
1845 req->local_ip_hi = *(__be64 *)(sip->s6_addr);
1846 req->local_ip_lo = *(__be64 *)(sip->s6_addr + 8);
1847 req->peer_ip_hi = cpu_to_be64(0);
1848 req->peer_ip_lo = cpu_to_be64(0);
1849 chan = rxq_to_chan(&adap->sge, queue);
1850 req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
1851 req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) |
1852 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue));
1853 ret = t4_mgmt_tx(adap, skb);
1854 return net_xmit_eval(ret);
1855}
1856EXPORT_SYMBOL(cxgb4_create_server6);
1857
1858int cxgb4_remove_server(const struct net_device *dev, unsigned int stid,
1859 unsigned int queue, bool ipv6)
1860{
1861 struct sk_buff *skb;
1862 struct adapter *adap;
1863 struct cpl_close_listsvr_req *req;
1864 int ret;
1865
1866 adap = netdev2adap(dev);
1867
1868 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1869 if (!skb)
1870 return -ENOMEM;
1871
1872 req = (struct cpl_close_listsvr_req *)__skb_put(skb, sizeof(*req));
1873 INIT_TP_WR(req, 0);
1874 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_CLOSE_LISTSRV_REQ, stid));
1875 req->reply_ctrl = htons(NO_REPLY_V(0) | (ipv6 ? LISTSVR_IPV6_V(1) :
1876 LISTSVR_IPV6_V(0)) | QUEUENO_V(queue));
1877 ret = t4_mgmt_tx(adap, skb);
1878 return net_xmit_eval(ret);
1879}
1880EXPORT_SYMBOL(cxgb4_remove_server);
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu,
1893 unsigned int *idx)
1894{
1895 unsigned int i = 0;
1896
1897 while (i < NMTUS - 1 && mtus[i + 1] <= mtu)
1898 ++i;
1899 if (idx)
1900 *idx = i;
1901 return mtus[i];
1902}
1903EXPORT_SYMBOL(cxgb4_best_mtu);
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921unsigned int cxgb4_best_aligned_mtu(const unsigned short *mtus,
1922 unsigned short header_size,
1923 unsigned short data_size_max,
1924 unsigned short data_size_align,
1925 unsigned int *mtu_idxp)
1926{
1927 unsigned short max_mtu = header_size + data_size_max;
1928 unsigned short data_size_align_mask = data_size_align - 1;
1929 int mtu_idx, aligned_mtu_idx;
1930
1931
1932
1933
1934
1935
1936 for (mtu_idx = 0, aligned_mtu_idx = -1; mtu_idx < NMTUS; mtu_idx++) {
1937 unsigned short data_size = mtus[mtu_idx] - header_size;
1938
1939
1940
1941
1942 if ((data_size & data_size_align_mask) == 0)
1943 aligned_mtu_idx = mtu_idx;
1944
1945
1946
1947
1948
1949 if (mtu_idx+1 < NMTUS && mtus[mtu_idx+1] > max_mtu)
1950 break;
1951 }
1952
1953
1954
1955
1956 if (mtu_idx == NMTUS)
1957 mtu_idx--;
1958
1959
1960
1961
1962
1963 if (aligned_mtu_idx >= 0 &&
1964 mtu_idx - aligned_mtu_idx <= 1)
1965 mtu_idx = aligned_mtu_idx;
1966
1967
1968
1969
1970 if (mtu_idxp)
1971 *mtu_idxp = mtu_idx;
1972 return mtus[mtu_idx];
1973}
1974EXPORT_SYMBOL(cxgb4_best_aligned_mtu);
1975
1976
1977
1978
1979
1980
1981
1982
1983unsigned int cxgb4_tp_smt_idx(enum chip_type chip, unsigned int viid)
1984{
1985
1986
1987
1988
1989
1990
1991 if (CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5)
1992 return ((viid & 0x7f) << 1);
1993 else
1994 return (viid & 0x7f);
1995}
1996EXPORT_SYMBOL(cxgb4_tp_smt_idx);
1997
1998
1999
2000
2001
2002
2003
2004unsigned int cxgb4_port_chan(const struct net_device *dev)
2005{
2006 return netdev2pinfo(dev)->tx_chan;
2007}
2008EXPORT_SYMBOL(cxgb4_port_chan);
2009
2010unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo)
2011{
2012 struct adapter *adap = netdev2adap(dev);
2013 u32 v1, v2, lp_count, hp_count;
2014
2015 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
2016 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
2017 if (is_t4(adap->params.chip)) {
2018 lp_count = LP_COUNT_G(v1);
2019 hp_count = HP_COUNT_G(v1);
2020 } else {
2021 lp_count = LP_COUNT_T5_G(v1);
2022 hp_count = HP_COUNT_T5_G(v2);
2023 }
2024 return lpfifo ? lp_count : hp_count;
2025}
2026EXPORT_SYMBOL(cxgb4_dbfifo_count);
2027
2028
2029
2030
2031
2032
2033
2034unsigned int cxgb4_port_viid(const struct net_device *dev)
2035{
2036 return netdev2pinfo(dev)->viid;
2037}
2038EXPORT_SYMBOL(cxgb4_port_viid);
2039
2040
2041
2042
2043
2044
2045
2046unsigned int cxgb4_port_idx(const struct net_device *dev)
2047{
2048 return netdev2pinfo(dev)->port_id;
2049}
2050EXPORT_SYMBOL(cxgb4_port_idx);
2051
2052void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4,
2053 struct tp_tcp_stats *v6)
2054{
2055 struct adapter *adap = pci_get_drvdata(pdev);
2056
2057 spin_lock(&adap->stats_lock);
2058 t4_tp_get_tcp_stats(adap, v4, v6);
2059 spin_unlock(&adap->stats_lock);
2060}
2061EXPORT_SYMBOL(cxgb4_get_tcp_stats);
2062
2063void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask,
2064 const unsigned int *pgsz_order)
2065{
2066 struct adapter *adap = netdev2adap(dev);
2067
2068 t4_write_reg(adap, ULP_RX_ISCSI_TAGMASK_A, tag_mask);
2069 t4_write_reg(adap, ULP_RX_ISCSI_PSZ_A, HPZ0_V(pgsz_order[0]) |
2070 HPZ1_V(pgsz_order[1]) | HPZ2_V(pgsz_order[2]) |
2071 HPZ3_V(pgsz_order[3]));
2072}
2073EXPORT_SYMBOL(cxgb4_iscsi_init);
2074
2075int cxgb4_flush_eq_cache(struct net_device *dev)
2076{
2077 struct adapter *adap = netdev2adap(dev);
2078
2079 return t4_sge_ctxt_flush(adap, adap->mbox);
2080}
2081EXPORT_SYMBOL(cxgb4_flush_eq_cache);
2082
2083static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx)
2084{
2085 u32 addr = t4_read_reg(adap, SGE_DBQ_CTXT_BADDR_A) + 24 * qid + 8;
2086 __be64 indices;
2087 int ret;
2088
2089 spin_lock(&adap->win0_lock);
2090 ret = t4_memory_rw(adap, 0, MEM_EDC0, addr,
2091 sizeof(indices), (__be32 *)&indices,
2092 T4_MEMORY_READ);
2093 spin_unlock(&adap->win0_lock);
2094 if (!ret) {
2095 *cidx = (be64_to_cpu(indices) >> 25) & 0xffff;
2096 *pidx = (be64_to_cpu(indices) >> 9) & 0xffff;
2097 }
2098 return ret;
2099}
2100
2101int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx,
2102 u16 size)
2103{
2104 struct adapter *adap = netdev2adap(dev);
2105 u16 hw_pidx, hw_cidx;
2106 int ret;
2107
2108 ret = read_eq_indices(adap, qid, &hw_pidx, &hw_cidx);
2109 if (ret)
2110 goto out;
2111
2112 if (pidx != hw_pidx) {
2113 u16 delta;
2114 u32 val;
2115
2116 if (pidx >= hw_pidx)
2117 delta = pidx - hw_pidx;
2118 else
2119 delta = size - hw_pidx + pidx;
2120
2121 if (is_t4(adap->params.chip))
2122 val = PIDX_V(delta);
2123 else
2124 val = PIDX_T5_V(delta);
2125 wmb();
2126 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
2127 QID_V(qid) | val);
2128 }
2129out:
2130 return ret;
2131}
2132EXPORT_SYMBOL(cxgb4_sync_txq_pidx);
2133
2134int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte)
2135{
2136 struct adapter *adap;
2137 u32 offset, memtype, memaddr;
2138 u32 edc0_size, edc1_size, mc0_size, mc1_size, size;
2139 u32 edc0_end, edc1_end, mc0_end, mc1_end;
2140 int ret;
2141
2142 adap = netdev2adap(dev);
2143
2144 offset = ((stag >> 8) * 32) + adap->vres.stag.start;
2145
2146
2147
2148
2149
2150
2151
2152 size = t4_read_reg(adap, MA_EDRAM0_BAR_A);
2153 edc0_size = EDRAM0_SIZE_G(size) << 20;
2154 size = t4_read_reg(adap, MA_EDRAM1_BAR_A);
2155 edc1_size = EDRAM1_SIZE_G(size) << 20;
2156 size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A);
2157 mc0_size = EXT_MEM0_SIZE_G(size) << 20;
2158
2159 edc0_end = edc0_size;
2160 edc1_end = edc0_end + edc1_size;
2161 mc0_end = edc1_end + mc0_size;
2162
2163 if (offset < edc0_end) {
2164 memtype = MEM_EDC0;
2165 memaddr = offset;
2166 } else if (offset < edc1_end) {
2167 memtype = MEM_EDC1;
2168 memaddr = offset - edc0_end;
2169 } else {
2170 if (offset < mc0_end) {
2171 memtype = MEM_MC0;
2172 memaddr = offset - edc1_end;
2173 } else if (is_t5(adap->params.chip)) {
2174 size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
2175 mc1_size = EXT_MEM1_SIZE_G(size) << 20;
2176 mc1_end = mc0_end + mc1_size;
2177 if (offset < mc1_end) {
2178 memtype = MEM_MC1;
2179 memaddr = offset - mc0_end;
2180 } else {
2181
2182 goto err;
2183 }
2184 } else {
2185
2186 goto err;
2187 }
2188 }
2189
2190 spin_lock(&adap->win0_lock);
2191 ret = t4_memory_rw(adap, 0, memtype, memaddr, 32, tpte, T4_MEMORY_READ);
2192 spin_unlock(&adap->win0_lock);
2193 return ret;
2194
2195err:
2196 dev_err(adap->pdev_dev, "stag %#x, offset %#x out of range\n",
2197 stag, offset);
2198 return -EINVAL;
2199}
2200EXPORT_SYMBOL(cxgb4_read_tpte);
2201
2202u64 cxgb4_read_sge_timestamp(struct net_device *dev)
2203{
2204 u32 hi, lo;
2205 struct adapter *adap;
2206
2207 adap = netdev2adap(dev);
2208 lo = t4_read_reg(adap, SGE_TIMESTAMP_LO_A);
2209 hi = TSVAL_G(t4_read_reg(adap, SGE_TIMESTAMP_HI_A));
2210
2211 return ((u64)hi << 32) | (u64)lo;
2212}
2213EXPORT_SYMBOL(cxgb4_read_sge_timestamp);
2214
2215int cxgb4_bar2_sge_qregs(struct net_device *dev,
2216 unsigned int qid,
2217 enum cxgb4_bar2_qtype qtype,
2218 int user,
2219 u64 *pbar2_qoffset,
2220 unsigned int *pbar2_qid)
2221{
2222 return t4_bar2_sge_qregs(netdev2adap(dev),
2223 qid,
2224 (qtype == CXGB4_BAR2_QTYPE_EGRESS
2225 ? T4_BAR2_QTYPE_EGRESS
2226 : T4_BAR2_QTYPE_INGRESS),
2227 user,
2228 pbar2_qoffset,
2229 pbar2_qid);
2230}
2231EXPORT_SYMBOL(cxgb4_bar2_sge_qregs);
2232
2233static struct pci_driver cxgb4_driver;
2234
2235static void check_neigh_update(struct neighbour *neigh)
2236{
2237 const struct device *parent;
2238 const struct net_device *netdev = neigh->dev;
2239
2240 if (netdev->priv_flags & IFF_802_1Q_VLAN)
2241 netdev = vlan_dev_real_dev(netdev);
2242 parent = netdev->dev.parent;
2243 if (parent && parent->driver == &cxgb4_driver.driver)
2244 t4_l2t_update(dev_get_drvdata(parent), neigh);
2245}
2246
2247static int netevent_cb(struct notifier_block *nb, unsigned long event,
2248 void *data)
2249{
2250 switch (event) {
2251 case NETEVENT_NEIGH_UPDATE:
2252 check_neigh_update(data);
2253 break;
2254 case NETEVENT_REDIRECT:
2255 default:
2256 break;
2257 }
2258 return 0;
2259}
2260
2261static bool netevent_registered;
2262static struct notifier_block cxgb4_netevent_nb = {
2263 .notifier_call = netevent_cb
2264};
2265
2266static void drain_db_fifo(struct adapter *adap, int usecs)
2267{
2268 u32 v1, v2, lp_count, hp_count;
2269
2270 do {
2271 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
2272 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
2273 if (is_t4(adap->params.chip)) {
2274 lp_count = LP_COUNT_G(v1);
2275 hp_count = HP_COUNT_G(v1);
2276 } else {
2277 lp_count = LP_COUNT_T5_G(v1);
2278 hp_count = HP_COUNT_T5_G(v2);
2279 }
2280
2281 if (lp_count == 0 && hp_count == 0)
2282 break;
2283 set_current_state(TASK_UNINTERRUPTIBLE);
2284 schedule_timeout(usecs_to_jiffies(usecs));
2285 } while (1);
2286}
2287
2288static void disable_txq_db(struct sge_txq *q)
2289{
2290 unsigned long flags;
2291
2292 spin_lock_irqsave(&q->db_lock, flags);
2293 q->db_disabled = 1;
2294 spin_unlock_irqrestore(&q->db_lock, flags);
2295}
2296
2297static void enable_txq_db(struct adapter *adap, struct sge_txq *q)
2298{
2299 spin_lock_irq(&q->db_lock);
2300 if (q->db_pidx_inc) {
2301
2302
2303
2304 wmb();
2305 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
2306 QID_V(q->cntxt_id) | PIDX_V(q->db_pidx_inc));
2307 q->db_pidx_inc = 0;
2308 }
2309 q->db_disabled = 0;
2310 spin_unlock_irq(&q->db_lock);
2311}
2312
2313static void disable_dbs(struct adapter *adap)
2314{
2315 int i;
2316
2317 for_each_ethrxq(&adap->sge, i)
2318 disable_txq_db(&adap->sge.ethtxq[i].q);
2319 for_each_iscsirxq(&adap->sge, i)
2320 disable_txq_db(&adap->sge.ofldtxq[i].q);
2321 for_each_port(adap, i)
2322 disable_txq_db(&adap->sge.ctrlq[i].q);
2323}
2324
2325static void enable_dbs(struct adapter *adap)
2326{
2327 int i;
2328
2329 for_each_ethrxq(&adap->sge, i)
2330 enable_txq_db(adap, &adap->sge.ethtxq[i].q);
2331 for_each_iscsirxq(&adap->sge, i)
2332 enable_txq_db(adap, &adap->sge.ofldtxq[i].q);
2333 for_each_port(adap, i)
2334 enable_txq_db(adap, &adap->sge.ctrlq[i].q);
2335}
2336
2337static void notify_rdma_uld(struct adapter *adap, enum cxgb4_control cmd)
2338{
2339 if (adap->uld_handle[CXGB4_ULD_RDMA])
2340 ulds[CXGB4_ULD_RDMA].control(adap->uld_handle[CXGB4_ULD_RDMA],
2341 cmd);
2342}
2343
2344static void process_db_full(struct work_struct *work)
2345{
2346 struct adapter *adap;
2347
2348 adap = container_of(work, struct adapter, db_full_task);
2349
2350 drain_db_fifo(adap, dbfifo_drain_delay);
2351 enable_dbs(adap);
2352 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
2353 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
2354 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2355 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F,
2356 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F);
2357 else
2358 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2359 DBFIFO_LP_INT_F, DBFIFO_LP_INT_F);
2360}
2361
2362static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q)
2363{
2364 u16 hw_pidx, hw_cidx;
2365 int ret;
2366
2367 spin_lock_irq(&q->db_lock);
2368 ret = read_eq_indices(adap, (u16)q->cntxt_id, &hw_pidx, &hw_cidx);
2369 if (ret)
2370 goto out;
2371 if (q->db_pidx != hw_pidx) {
2372 u16 delta;
2373 u32 val;
2374
2375 if (q->db_pidx >= hw_pidx)
2376 delta = q->db_pidx - hw_pidx;
2377 else
2378 delta = q->size - hw_pidx + q->db_pidx;
2379
2380 if (is_t4(adap->params.chip))
2381 val = PIDX_V(delta);
2382 else
2383 val = PIDX_T5_V(delta);
2384 wmb();
2385 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
2386 QID_V(q->cntxt_id) | val);
2387 }
2388out:
2389 q->db_disabled = 0;
2390 q->db_pidx_inc = 0;
2391 spin_unlock_irq(&q->db_lock);
2392 if (ret)
2393 CH_WARN(adap, "DB drop recovery failed.\n");
2394}
2395static void recover_all_queues(struct adapter *adap)
2396{
2397 int i;
2398
2399 for_each_ethrxq(&adap->sge, i)
2400 sync_txq_pidx(adap, &adap->sge.ethtxq[i].q);
2401 for_each_iscsirxq(&adap->sge, i)
2402 sync_txq_pidx(adap, &adap->sge.ofldtxq[i].q);
2403 for_each_port(adap, i)
2404 sync_txq_pidx(adap, &adap->sge.ctrlq[i].q);
2405}
2406
2407static void process_db_drop(struct work_struct *work)
2408{
2409 struct adapter *adap;
2410
2411 adap = container_of(work, struct adapter, db_drop_task);
2412
2413 if (is_t4(adap->params.chip)) {
2414 drain_db_fifo(adap, dbfifo_drain_delay);
2415 notify_rdma_uld(adap, CXGB4_CONTROL_DB_DROP);
2416 drain_db_fifo(adap, dbfifo_drain_delay);
2417 recover_all_queues(adap);
2418 drain_db_fifo(adap, dbfifo_drain_delay);
2419 enable_dbs(adap);
2420 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
2421 } else if (is_t5(adap->params.chip)) {
2422 u32 dropped_db = t4_read_reg(adap, 0x010ac);
2423 u16 qid = (dropped_db >> 15) & 0x1ffff;
2424 u16 pidx_inc = dropped_db & 0x1fff;
2425 u64 bar2_qoffset;
2426 unsigned int bar2_qid;
2427 int ret;
2428
2429 ret = t4_bar2_sge_qregs(adap, qid, T4_BAR2_QTYPE_EGRESS,
2430 0, &bar2_qoffset, &bar2_qid);
2431 if (ret)
2432 dev_err(adap->pdev_dev, "doorbell drop recovery: "
2433 "qid=%d, pidx_inc=%d\n", qid, pidx_inc);
2434 else
2435 writel(PIDX_T5_V(pidx_inc) | QID_V(bar2_qid),
2436 adap->bar2 + bar2_qoffset + SGE_UDB_KDOORBELL);
2437
2438
2439 t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15);
2440 }
2441
2442 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
2443 t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, DROPPED_DB_F, 0);
2444}
2445
2446void t4_db_full(struct adapter *adap)
2447{
2448 if (is_t4(adap->params.chip)) {
2449 disable_dbs(adap);
2450 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
2451 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2452 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F, 0);
2453 queue_work(adap->workq, &adap->db_full_task);
2454 }
2455}
2456
2457void t4_db_dropped(struct adapter *adap)
2458{
2459 if (is_t4(adap->params.chip)) {
2460 disable_dbs(adap);
2461 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
2462 }
2463 queue_work(adap->workq, &adap->db_drop_task);
2464}
2465
2466static void uld_attach(struct adapter *adap, unsigned int uld)
2467{
2468 void *handle;
2469 struct cxgb4_lld_info lli;
2470 unsigned short i;
2471
2472 lli.pdev = adap->pdev;
2473 lli.pf = adap->pf;
2474 lli.l2t = adap->l2t;
2475 lli.tids = &adap->tids;
2476 lli.ports = adap->port;
2477 lli.vr = &adap->vres;
2478 lli.mtus = adap->params.mtus;
2479 if (uld == CXGB4_ULD_RDMA) {
2480 lli.rxq_ids = adap->sge.rdma_rxq;
2481 lli.ciq_ids = adap->sge.rdma_ciq;
2482 lli.nrxq = adap->sge.rdmaqs;
2483 lli.nciq = adap->sge.rdmaciqs;
2484 } else if (uld == CXGB4_ULD_ISCSI) {
2485 lli.rxq_ids = adap->sge.iscsi_rxq;
2486 lli.nrxq = adap->sge.iscsiqsets;
2487 } else if (uld == CXGB4_ULD_ISCSIT) {
2488 lli.rxq_ids = adap->sge.iscsit_rxq;
2489 lli.nrxq = adap->sge.niscsitq;
2490 }
2491 lli.ntxq = adap->sge.iscsiqsets;
2492 lli.nchan = adap->params.nports;
2493 lli.nports = adap->params.nports;
2494 lli.wr_cred = adap->params.ofldq_wr_cred;
2495 lli.adapter_type = adap->params.chip;
2496 lli.iscsi_iolen = MAXRXDATA_G(t4_read_reg(adap, TP_PARA_REG2_A));
2497 lli.iscsi_tagmask = t4_read_reg(adap, ULP_RX_ISCSI_TAGMASK_A);
2498 lli.iscsi_pgsz_order = t4_read_reg(adap, ULP_RX_ISCSI_PSZ_A);
2499 lli.iscsi_llimit = t4_read_reg(adap, ULP_RX_ISCSI_LLIMIT_A);
2500 lli.iscsi_ppm = &adap->iscsi_ppm;
2501 lli.cclk_ps = 1000000000 / adap->params.vpd.cclk;
2502 lli.udb_density = 1 << adap->params.sge.eq_qpp;
2503 lli.ucq_density = 1 << adap->params.sge.iq_qpp;
2504 lli.filt_mode = adap->params.tp.vlan_pri_map;
2505
2506 for (i = 0; i < NCHAN; i++)
2507 lli.tx_modq[i] = i;
2508 lli.gts_reg = adap->regs + MYPF_REG(SGE_PF_GTS_A);
2509 lli.db_reg = adap->regs + MYPF_REG(SGE_PF_KDOORBELL_A);
2510 lli.fw_vers = adap->params.fw_vers;
2511 lli.dbfifo_int_thresh = dbfifo_int_thresh;
2512 lli.sge_ingpadboundary = adap->sge.fl_align;
2513 lli.sge_egrstatuspagesize = adap->sge.stat_len;
2514 lli.sge_pktshift = adap->sge.pktshift;
2515 lli.enable_fw_ofld_conn = adap->flags & FW_OFLD_CONN;
2516 lli.max_ordird_qp = adap->params.max_ordird_qp;
2517 lli.max_ird_adapter = adap->params.max_ird_adapter;
2518 lli.ulptx_memwrite_dsgl = adap->params.ulptx_memwrite_dsgl;
2519 lli.nodeid = dev_to_node(adap->pdev_dev);
2520
2521 handle = ulds[uld].add(&lli);
2522 if (IS_ERR(handle)) {
2523 dev_warn(adap->pdev_dev,
2524 "could not attach to the %s driver, error %ld\n",
2525 uld_str[uld], PTR_ERR(handle));
2526 return;
2527 }
2528
2529 adap->uld_handle[uld] = handle;
2530
2531 if (!netevent_registered) {
2532 register_netevent_notifier(&cxgb4_netevent_nb);
2533 netevent_registered = true;
2534 }
2535
2536 if (adap->flags & FULL_INIT_DONE)
2537 ulds[uld].state_change(handle, CXGB4_STATE_UP);
2538}
2539
2540static void attach_ulds(struct adapter *adap)
2541{
2542 unsigned int i;
2543
2544 spin_lock(&adap_rcu_lock);
2545 list_add_tail_rcu(&adap->rcu_node, &adap_rcu_list);
2546 spin_unlock(&adap_rcu_lock);
2547
2548 mutex_lock(&uld_mutex);
2549 list_add_tail(&adap->list_node, &adapter_list);
2550 for (i = 0; i < CXGB4_ULD_MAX; i++)
2551 if (ulds[i].add)
2552 uld_attach(adap, i);
2553 mutex_unlock(&uld_mutex);
2554}
2555
2556static void detach_ulds(struct adapter *adap)
2557{
2558 unsigned int i;
2559
2560 mutex_lock(&uld_mutex);
2561 list_del(&adap->list_node);
2562 for (i = 0; i < CXGB4_ULD_MAX; i++)
2563 if (adap->uld_handle[i]) {
2564 ulds[i].state_change(adap->uld_handle[i],
2565 CXGB4_STATE_DETACH);
2566 adap->uld_handle[i] = NULL;
2567 }
2568 if (netevent_registered && list_empty(&adapter_list)) {
2569 unregister_netevent_notifier(&cxgb4_netevent_nb);
2570 netevent_registered = false;
2571 }
2572 mutex_unlock(&uld_mutex);
2573
2574 spin_lock(&adap_rcu_lock);
2575 list_del_rcu(&adap->rcu_node);
2576 spin_unlock(&adap_rcu_lock);
2577}
2578
2579static void notify_ulds(struct adapter *adap, enum cxgb4_state new_state)
2580{
2581 unsigned int i;
2582
2583 mutex_lock(&uld_mutex);
2584 for (i = 0; i < CXGB4_ULD_MAX; i++)
2585 if (adap->uld_handle[i])
2586 ulds[i].state_change(adap->uld_handle[i], new_state);
2587 mutex_unlock(&uld_mutex);
2588}
2589
2590
2591
2592
2593
2594
2595
2596
2597
2598
2599int cxgb4_register_uld(enum cxgb4_uld type, const struct cxgb4_uld_info *p)
2600{
2601 int ret = 0;
2602 struct adapter *adap;
2603
2604 if (type >= CXGB4_ULD_MAX)
2605 return -EINVAL;
2606 mutex_lock(&uld_mutex);
2607 if (ulds[type].add) {
2608 ret = -EBUSY;
2609 goto out;
2610 }
2611 ulds[type] = *p;
2612 list_for_each_entry(adap, &adapter_list, list_node)
2613 uld_attach(adap, type);
2614out: mutex_unlock(&uld_mutex);
2615 return ret;
2616}
2617EXPORT_SYMBOL(cxgb4_register_uld);
2618
2619
2620
2621
2622
2623
2624
2625int cxgb4_unregister_uld(enum cxgb4_uld type)
2626{
2627 struct adapter *adap;
2628
2629 if (type >= CXGB4_ULD_MAX)
2630 return -EINVAL;
2631 mutex_lock(&uld_mutex);
2632 list_for_each_entry(adap, &adapter_list, list_node)
2633 adap->uld_handle[type] = NULL;
2634 ulds[type].add = NULL;
2635 mutex_unlock(&uld_mutex);
2636 return 0;
2637}
2638EXPORT_SYMBOL(cxgb4_unregister_uld);
2639
2640#if IS_ENABLED(CONFIG_IPV6)
2641static int cxgb4_inet6addr_handler(struct notifier_block *this,
2642 unsigned long event, void *data)
2643{
2644 struct inet6_ifaddr *ifa = data;
2645 struct net_device *event_dev = ifa->idev->dev;
2646 const struct device *parent = NULL;
2647#if IS_ENABLED(CONFIG_BONDING)
2648 struct adapter *adap;
2649#endif
2650 if (event_dev->priv_flags & IFF_802_1Q_VLAN)
2651 event_dev = vlan_dev_real_dev(event_dev);
2652#if IS_ENABLED(CONFIG_BONDING)
2653 if (event_dev->flags & IFF_MASTER) {
2654 list_for_each_entry(adap, &adapter_list, list_node) {
2655 switch (event) {
2656 case NETDEV_UP:
2657 cxgb4_clip_get(adap->port[0],
2658 (const u32 *)ifa, 1);
2659 break;
2660 case NETDEV_DOWN:
2661 cxgb4_clip_release(adap->port[0],
2662 (const u32 *)ifa, 1);
2663 break;
2664 default:
2665 break;
2666 }
2667 }
2668 return NOTIFY_OK;
2669 }
2670#endif
2671
2672 if (event_dev)
2673 parent = event_dev->dev.parent;
2674
2675 if (parent && parent->driver == &cxgb4_driver.driver) {
2676 switch (event) {
2677 case NETDEV_UP:
2678 cxgb4_clip_get(event_dev, (const u32 *)ifa, 1);
2679 break;
2680 case NETDEV_DOWN:
2681 cxgb4_clip_release(event_dev, (const u32 *)ifa, 1);
2682 break;
2683 default:
2684 break;
2685 }
2686 }
2687 return NOTIFY_OK;
2688}
2689
2690static bool inet6addr_registered;
2691static struct notifier_block cxgb4_inet6addr_notifier = {
2692 .notifier_call = cxgb4_inet6addr_handler
2693};
2694
2695static void update_clip(const struct adapter *adap)
2696{
2697 int i;
2698 struct net_device *dev;
2699 int ret;
2700
2701 rcu_read_lock();
2702
2703 for (i = 0; i < MAX_NPORTS; i++) {
2704 dev = adap->port[i];
2705 ret = 0;
2706
2707 if (dev)
2708 ret = cxgb4_update_root_dev_clip(dev);
2709
2710 if (ret < 0)
2711 break;
2712 }
2713 rcu_read_unlock();
2714}
2715#endif
2716
2717
2718
2719
2720
2721
2722
2723
2724
2725
2726
2727static int cxgb_up(struct adapter *adap)
2728{
2729 int err;
2730
2731 err = setup_sge_queues(adap);
2732 if (err)
2733 goto out;
2734 err = setup_rss(adap);
2735 if (err)
2736 goto freeq;
2737
2738 if (adap->flags & USING_MSIX) {
2739 name_msix_vecs(adap);
2740 err = request_irq(adap->msix_info[0].vec, t4_nondata_intr, 0,
2741 adap->msix_info[0].desc, adap);
2742 if (err)
2743 goto irq_err;
2744
2745 err = request_msix_queue_irqs(adap);
2746 if (err) {
2747 free_irq(adap->msix_info[0].vec, adap);
2748 goto irq_err;
2749 }
2750 } else {
2751 err = request_irq(adap->pdev->irq, t4_intr_handler(adap),
2752 (adap->flags & USING_MSI) ? 0 : IRQF_SHARED,
2753 adap->port[0]->name, adap);
2754 if (err)
2755 goto irq_err;
2756 }
2757 enable_rx(adap);
2758 t4_sge_start(adap);
2759 t4_intr_enable(adap);
2760 adap->flags |= FULL_INIT_DONE;
2761 notify_ulds(adap, CXGB4_STATE_UP);
2762#if IS_ENABLED(CONFIG_IPV6)
2763 update_clip(adap);
2764#endif
2765
2766 INIT_LIST_HEAD(&adap->mac_hlist);
2767 out:
2768 return err;
2769 irq_err:
2770 dev_err(adap->pdev_dev, "request_irq failed, err %d\n", err);
2771 freeq:
2772 t4_free_sge_resources(adap);
2773 goto out;
2774}
2775
2776static void cxgb_down(struct adapter *adapter)
2777{
2778 cancel_work_sync(&adapter->tid_release_task);
2779 cancel_work_sync(&adapter->db_full_task);
2780 cancel_work_sync(&adapter->db_drop_task);
2781 adapter->tid_release_task_busy = false;
2782 adapter->tid_release_head = NULL;
2783
2784 t4_sge_stop(adapter);
2785 t4_free_sge_resources(adapter);
2786 adapter->flags &= ~FULL_INIT_DONE;
2787}
2788
2789
2790
2791
2792static int cxgb_open(struct net_device *dev)
2793{
2794 int err;
2795 struct port_info *pi = netdev_priv(dev);
2796 struct adapter *adapter = pi->adapter;
2797
2798 netif_carrier_off(dev);
2799
2800 if (!(adapter->flags & FULL_INIT_DONE)) {
2801 err = cxgb_up(adapter);
2802 if (err < 0)
2803 return err;
2804 }
2805
2806 err = link_start(dev);
2807 if (!err)
2808 netif_tx_start_all_queues(dev);
2809 return err;
2810}
2811
2812static int cxgb_close(struct net_device *dev)
2813{
2814 struct port_info *pi = netdev_priv(dev);
2815 struct adapter *adapter = pi->adapter;
2816
2817 netif_tx_stop_all_queues(dev);
2818 netif_carrier_off(dev);
2819 return t4_enable_vi(adapter, adapter->pf, pi->viid, false, false);
2820}
2821
2822
2823
2824static int writable_filter(struct filter_entry *f)
2825{
2826 if (f->locked)
2827 return -EPERM;
2828 if (f->pending)
2829 return -EBUSY;
2830
2831 return 0;
2832}
2833
2834
2835
2836
2837
2838static int delete_filter(struct adapter *adapter, unsigned int fidx)
2839{
2840 struct filter_entry *f;
2841 int ret;
2842
2843 if (fidx >= adapter->tids.nftids + adapter->tids.nsftids)
2844 return -EINVAL;
2845
2846 f = &adapter->tids.ftid_tab[fidx];
2847 ret = writable_filter(f);
2848 if (ret)
2849 return ret;
2850 if (f->valid)
2851 return del_filter_wr(adapter, fidx);
2852
2853 return 0;
2854}
2855
2856int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid,
2857 __be32 sip, __be16 sport, __be16 vlan,
2858 unsigned int queue, unsigned char port, unsigned char mask)
2859{
2860 int ret;
2861 struct filter_entry *f;
2862 struct adapter *adap;
2863 int i;
2864 u8 *val;
2865
2866 adap = netdev2adap(dev);
2867
2868
2869 stid -= adap->tids.sftid_base;
2870 stid += adap->tids.nftids;
2871
2872
2873
2874 f = &adap->tids.ftid_tab[stid];
2875 ret = writable_filter(f);
2876 if (ret)
2877 return ret;
2878
2879
2880
2881
2882 if (f->valid)
2883 clear_filter(adap, f);
2884
2885
2886 memset(&f->fs, 0, sizeof(struct ch_filter_specification));
2887 f->fs.val.lport = cpu_to_be16(sport);
2888 f->fs.mask.lport = ~0;
2889 val = (u8 *)&sip;
2890 if ((val[0] | val[1] | val[2] | val[3]) != 0) {
2891 for (i = 0; i < 4; i++) {
2892 f->fs.val.lip[i] = val[i];
2893 f->fs.mask.lip[i] = ~0;
2894 }
2895 if (adap->params.tp.vlan_pri_map & PORT_F) {
2896 f->fs.val.iport = port;
2897 f->fs.mask.iport = mask;
2898 }
2899 }
2900
2901 if (adap->params.tp.vlan_pri_map & PROTOCOL_F) {
2902 f->fs.val.proto = IPPROTO_TCP;
2903 f->fs.mask.proto = ~0;
2904 }
2905
2906 f->fs.dirsteer = 1;
2907 f->fs.iq = queue;
2908
2909 f->locked = 1;
2910 f->fs.rpttid = 1;
2911
2912 ret = set_filter_wr(adap, stid);
2913 if (ret) {
2914 clear_filter(adap, f);
2915 return ret;
2916 }
2917
2918 return 0;
2919}
2920EXPORT_SYMBOL(cxgb4_create_server_filter);
2921
2922int cxgb4_remove_server_filter(const struct net_device *dev, unsigned int stid,
2923 unsigned int queue, bool ipv6)
2924{
2925 int ret;
2926 struct filter_entry *f;
2927 struct adapter *adap;
2928
2929 adap = netdev2adap(dev);
2930
2931
2932 stid -= adap->tids.sftid_base;
2933 stid += adap->tids.nftids;
2934
2935 f = &adap->tids.ftid_tab[stid];
2936
2937 f->locked = 0;
2938
2939 ret = delete_filter(adap, stid);
2940 if (ret)
2941 return ret;
2942
2943 return 0;
2944}
2945EXPORT_SYMBOL(cxgb4_remove_server_filter);
2946
2947static struct rtnl_link_stats64 *cxgb_get_stats(struct net_device *dev,
2948 struct rtnl_link_stats64 *ns)
2949{
2950 struct port_stats stats;
2951 struct port_info *p = netdev_priv(dev);
2952 struct adapter *adapter = p->adapter;
2953
2954
2955
2956
2957
2958 spin_lock(&adapter->stats_lock);
2959 if (!netif_device_present(dev)) {
2960 spin_unlock(&adapter->stats_lock);
2961 return ns;
2962 }
2963 t4_get_port_stats_offset(adapter, p->tx_chan, &stats,
2964 &p->stats_base);
2965 spin_unlock(&adapter->stats_lock);
2966
2967 ns->tx_bytes = stats.tx_octets;
2968 ns->tx_packets = stats.tx_frames;
2969 ns->rx_bytes = stats.rx_octets;
2970 ns->rx_packets = stats.rx_frames;
2971 ns->multicast = stats.rx_mcast_frames;
2972
2973
2974 ns->rx_length_errors = stats.rx_jabber + stats.rx_too_long +
2975 stats.rx_runt;
2976 ns->rx_over_errors = 0;
2977 ns->rx_crc_errors = stats.rx_fcs_err;
2978 ns->rx_frame_errors = stats.rx_symbol_err;
2979 ns->rx_fifo_errors = stats.rx_ovflow0 + stats.rx_ovflow1 +
2980 stats.rx_ovflow2 + stats.rx_ovflow3 +
2981 stats.rx_trunc0 + stats.rx_trunc1 +
2982 stats.rx_trunc2 + stats.rx_trunc3;
2983 ns->rx_missed_errors = 0;
2984
2985
2986 ns->tx_aborted_errors = 0;
2987 ns->tx_carrier_errors = 0;
2988 ns->tx_fifo_errors = 0;
2989 ns->tx_heartbeat_errors = 0;
2990 ns->tx_window_errors = 0;
2991
2992 ns->tx_errors = stats.tx_error_frames;
2993 ns->rx_errors = stats.rx_symbol_err + stats.rx_fcs_err +
2994 ns->rx_length_errors + stats.rx_len_err + ns->rx_fifo_errors;
2995 return ns;
2996}
2997
2998static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
2999{
3000 unsigned int mbox;
3001 int ret = 0, prtad, devad;
3002 struct port_info *pi = netdev_priv(dev);
3003 struct mii_ioctl_data *data = (struct mii_ioctl_data *)&req->ifr_data;
3004
3005 switch (cmd) {
3006 case SIOCGMIIPHY:
3007 if (pi->mdio_addr < 0)
3008 return -EOPNOTSUPP;
3009 data->phy_id = pi->mdio_addr;
3010 break;
3011 case SIOCGMIIREG:
3012 case SIOCSMIIREG:
3013 if (mdio_phy_id_is_c45(data->phy_id)) {
3014 prtad = mdio_phy_id_prtad(data->phy_id);
3015 devad = mdio_phy_id_devad(data->phy_id);
3016 } else if (data->phy_id < 32) {
3017 prtad = data->phy_id;
3018 devad = 0;
3019 data->reg_num &= 0x1f;
3020 } else
3021 return -EINVAL;
3022
3023 mbox = pi->adapter->pf;
3024 if (cmd == SIOCGMIIREG)
3025 ret = t4_mdio_rd(pi->adapter, mbox, prtad, devad,
3026 data->reg_num, &data->val_out);
3027 else
3028 ret = t4_mdio_wr(pi->adapter, mbox, prtad, devad,
3029 data->reg_num, data->val_in);
3030 break;
3031 case SIOCGHWTSTAMP:
3032 return copy_to_user(req->ifr_data, &pi->tstamp_config,
3033 sizeof(pi->tstamp_config)) ?
3034 -EFAULT : 0;
3035 case SIOCSHWTSTAMP:
3036 if (copy_from_user(&pi->tstamp_config, req->ifr_data,
3037 sizeof(pi->tstamp_config)))
3038 return -EFAULT;
3039
3040 switch (pi->tstamp_config.rx_filter) {
3041 case HWTSTAMP_FILTER_NONE:
3042 pi->rxtstamp = false;
3043 break;
3044 case HWTSTAMP_FILTER_ALL:
3045 pi->rxtstamp = true;
3046 break;
3047 default:
3048 pi->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
3049 return -ERANGE;
3050 }
3051
3052 return copy_to_user(req->ifr_data, &pi->tstamp_config,
3053 sizeof(pi->tstamp_config)) ?
3054 -EFAULT : 0;
3055 default:
3056 return -EOPNOTSUPP;
3057 }
3058 return ret;
3059}
3060
3061static void cxgb_set_rxmode(struct net_device *dev)
3062{
3063
3064 set_rxmode(dev, -1, false);
3065}
3066
3067static int cxgb_change_mtu(struct net_device *dev, int new_mtu)
3068{
3069 int ret;
3070 struct port_info *pi = netdev_priv(dev);
3071
3072 if (new_mtu < 81 || new_mtu > MAX_MTU)
3073 return -EINVAL;
3074 ret = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, new_mtu, -1,
3075 -1, -1, -1, true);
3076 if (!ret)
3077 dev->mtu = new_mtu;
3078 return ret;
3079}
3080
3081static int cxgb_set_mac_addr(struct net_device *dev, void *p)
3082{
3083 int ret;
3084 struct sockaddr *addr = p;
3085 struct port_info *pi = netdev_priv(dev);
3086
3087 if (!is_valid_ether_addr(addr->sa_data))
3088 return -EADDRNOTAVAIL;
3089
3090 ret = t4_change_mac(pi->adapter, pi->adapter->pf, pi->viid,
3091 pi->xact_addr_filt, addr->sa_data, true, true);
3092 if (ret < 0)
3093 return ret;
3094
3095 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3096 pi->xact_addr_filt = ret;
3097 return 0;
3098}
3099
3100#ifdef CONFIG_NET_POLL_CONTROLLER
3101static void cxgb_netpoll(struct net_device *dev)
3102{
3103 struct port_info *pi = netdev_priv(dev);
3104 struct adapter *adap = pi->adapter;
3105
3106 if (adap->flags & USING_MSIX) {
3107 int i;
3108 struct sge_eth_rxq *rx = &adap->sge.ethrxq[pi->first_qset];
3109
3110 for (i = pi->nqsets; i; i--, rx++)
3111 t4_sge_intr_msix(0, &rx->rspq);
3112 } else
3113 t4_intr_handler(adap)(0, adap);
3114}
3115#endif
3116
3117static const struct net_device_ops cxgb4_netdev_ops = {
3118 .ndo_open = cxgb_open,
3119 .ndo_stop = cxgb_close,
3120 .ndo_start_xmit = t4_eth_xmit,
3121 .ndo_select_queue = cxgb_select_queue,
3122 .ndo_get_stats64 = cxgb_get_stats,
3123 .ndo_set_rx_mode = cxgb_set_rxmode,
3124 .ndo_set_mac_address = cxgb_set_mac_addr,
3125 .ndo_set_features = cxgb_set_features,
3126 .ndo_validate_addr = eth_validate_addr,
3127 .ndo_do_ioctl = cxgb_ioctl,
3128 .ndo_change_mtu = cxgb_change_mtu,
3129#ifdef CONFIG_NET_POLL_CONTROLLER
3130 .ndo_poll_controller = cxgb_netpoll,
3131#endif
3132#ifdef CONFIG_CHELSIO_T4_FCOE
3133 .ndo_fcoe_enable = cxgb_fcoe_enable,
3134 .ndo_fcoe_disable = cxgb_fcoe_disable,
3135#endif
3136#ifdef CONFIG_NET_RX_BUSY_POLL
3137 .ndo_busy_poll = cxgb_busy_poll,
3138#endif
3139
3140};
3141
3142void t4_fatal_err(struct adapter *adap)
3143{
3144 t4_set_reg_field(adap, SGE_CONTROL_A, GLOBALENABLE_F, 0);
3145 t4_intr_disable(adap);
3146 dev_alert(adap->pdev_dev, "encountered fatal error, adapter stopped\n");
3147}
3148
3149static void setup_memwin(struct adapter *adap)
3150{
3151 u32 nic_win_base = t4_get_util_window(adap);
3152
3153 t4_setup_memwin(adap, nic_win_base, MEMWIN_NIC);
3154}
3155
3156static void setup_memwin_rdma(struct adapter *adap)
3157{
3158 if (adap->vres.ocq.size) {
3159 u32 start;
3160 unsigned int sz_kb;
3161
3162 start = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_2);
3163 start &= PCI_BASE_ADDRESS_MEM_MASK;
3164 start += OCQ_WIN_OFFSET(adap->pdev, &adap->vres);
3165 sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10;
3166 t4_write_reg(adap,
3167 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 3),
3168 start | BIR_V(1) | WINDOW_V(ilog2(sz_kb)));
3169 t4_write_reg(adap,
3170 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3),
3171 adap->vres.ocq.start);
3172 t4_read_reg(adap,
3173 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3));
3174 }
3175}
3176
3177static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c)
3178{
3179 u32 v;
3180 int ret;
3181
3182
3183 memset(c, 0, sizeof(*c));
3184 c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3185 FW_CMD_REQUEST_F | FW_CMD_READ_F);
3186 c->cfvalid_to_len16 = htonl(FW_LEN16(*c));
3187 ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), c);
3188 if (ret < 0)
3189 return ret;
3190
3191 c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3192 FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
3193 ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), NULL);
3194 if (ret < 0)
3195 return ret;
3196
3197 ret = t4_config_glbl_rss(adap, adap->pf,
3198 FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL,
3199 FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F |
3200 FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F);
3201 if (ret < 0)
3202 return ret;
3203
3204 ret = t4_cfg_pfvf(adap, adap->mbox, adap->pf, 0, adap->sge.egr_sz, 64,
3205 MAX_INGQ, 0, 0, 4, 0xf, 0xf, 16, FW_CMD_CAP_PF,
3206 FW_CMD_CAP_PF);
3207 if (ret < 0)
3208 return ret;
3209
3210 t4_sge_init(adap);
3211
3212
3213 t4_write_reg(adap, TP_SHIFT_CNT_A, 0x64f8849);
3214 t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(PAGE_SHIFT - 12));
3215 t4_write_reg(adap, TP_PIO_ADDR_A, TP_INGRESS_CONFIG_A);
3216 v = t4_read_reg(adap, TP_PIO_DATA_A);
3217 t4_write_reg(adap, TP_PIO_DATA_A, v & ~CSUM_HAS_PSEUDO_HDR_F);
3218
3219
3220 adap->params.tp.tx_modq_map = 0xE4;
3221 t4_write_reg(adap, TP_TX_MOD_QUEUE_REQ_MAP_A,
3222 TX_MOD_QUEUE_REQ_MAP_V(adap->params.tp.tx_modq_map));
3223
3224
3225 v = 0x84218421;
3226 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
3227 &v, 1, TP_TX_SCHED_HDR_A);
3228 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
3229 &v, 1, TP_TX_SCHED_FIFO_A);
3230 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
3231 &v, 1, TP_TX_SCHED_PCMD_A);
3232
3233#define T4_TX_MODQ_10G_WEIGHT_DEFAULT 16
3234 if (is_offload(adap)) {
3235 t4_write_reg(adap, TP_TX_MOD_QUEUE_WEIGHT0_A,
3236 TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3237 TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3238 TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3239 TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
3240 t4_write_reg(adap, TP_TX_MOD_CHANNEL_WEIGHT_A,
3241 TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3242 TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3243 TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3244 TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
3245 }
3246
3247
3248 return t4_early_init(adap, adap->pf);
3249}
3250
3251
3252
3253
3254#define MAX_ATIDS 8192U
3255
3256
3257
3258
3259
3260
3261
3262
3263
3264
3265
3266
3267
3268
3269
3270
3271
3272static int adap_init0_tweaks(struct adapter *adapter)
3273{
3274
3275
3276
3277
3278
3279 t4_fixup_host_params(adapter, PAGE_SIZE, L1_CACHE_BYTES);
3280
3281
3282
3283
3284 if (rx_dma_offset != 2 && rx_dma_offset != 0) {
3285 dev_err(&adapter->pdev->dev,
3286 "Ignoring illegal rx_dma_offset=%d, using 2\n",
3287 rx_dma_offset);
3288 rx_dma_offset = 2;
3289 }
3290 t4_set_reg_field(adapter, SGE_CONTROL_A,
3291 PKTSHIFT_V(PKTSHIFT_M),
3292 PKTSHIFT_V(rx_dma_offset));
3293
3294
3295
3296
3297
3298 t4_tp_wr_bits_indirect(adapter, TP_INGRESS_CONFIG_A,
3299 CSUM_HAS_PSEUDO_HDR_F, 0);
3300
3301 return 0;
3302}
3303
3304
3305
3306
3307
3308static int phy_aq1202_version(const u8 *phy_fw_data,
3309 size_t phy_fw_size)
3310{
3311 int offset;
3312
3313
3314
3315
3316
3317
3318
3319
3320
3321
3322 #define be16(__p) (((__p)[0] << 8) | (__p)[1])
3323 #define le16(__p) ((__p)[0] | ((__p)[1] << 8))
3324 #define le24(__p) (le16(__p) | ((__p)[2] << 16))
3325
3326 offset = le24(phy_fw_data + 0x8) << 12;
3327 offset = le24(phy_fw_data + offset + 0xa);
3328 return be16(phy_fw_data + offset + 0x27e);
3329
3330 #undef be16
3331 #undef le16
3332 #undef le24
3333}
3334
3335static struct info_10gbt_phy_fw {
3336 unsigned int phy_fw_id;
3337 char *phy_fw_file;
3338 int (*phy_fw_version)(const u8 *phy_fw_data, size_t phy_fw_size);
3339 int phy_flash;
3340} phy_info_array[] = {
3341 {
3342 PHY_AQ1202_DEVICEID,
3343 PHY_AQ1202_FIRMWARE,
3344 phy_aq1202_version,
3345 1,
3346 },
3347 {
3348 PHY_BCM84834_DEVICEID,
3349 PHY_BCM84834_FIRMWARE,
3350 NULL,
3351 0,
3352 },
3353 { 0, NULL, NULL },
3354};
3355
3356static struct info_10gbt_phy_fw *find_phy_info(int devid)
3357{
3358 int i;
3359
3360 for (i = 0; i < ARRAY_SIZE(phy_info_array); i++) {
3361 if (phy_info_array[i].phy_fw_id == devid)
3362 return &phy_info_array[i];
3363 }
3364 return NULL;
3365}
3366
3367
3368
3369
3370
3371
3372static int adap_init0_phy(struct adapter *adap)
3373{
3374 const struct firmware *phyf;
3375 int ret;
3376 struct info_10gbt_phy_fw *phy_info;
3377
3378
3379
3380 phy_info = find_phy_info(adap->pdev->device);
3381 if (!phy_info) {
3382 dev_warn(adap->pdev_dev,
3383 "No PHY Firmware file found for this PHY\n");
3384 return -EOPNOTSUPP;
3385 }
3386
3387
3388
3389
3390
3391
3392 ret = request_firmware_direct(&phyf, phy_info->phy_fw_file,
3393 adap->pdev_dev);
3394 if (ret < 0) {
3395
3396
3397
3398
3399
3400
3401 dev_err(adap->pdev_dev, "unable to find PHY Firmware image "
3402 "/lib/firmware/%s, error %d\n",
3403 phy_info->phy_fw_file, -ret);
3404 if (phy_info->phy_flash) {
3405 int cur_phy_fw_ver = 0;
3406
3407 t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3408 dev_warn(adap->pdev_dev, "continuing with, on-adapter "
3409 "FLASH copy, version %#x\n", cur_phy_fw_ver);
3410 ret = 0;
3411 }
3412
3413 return ret;
3414 }
3415
3416
3417
3418 ret = t4_load_phy_fw(adap, MEMWIN_NIC, &adap->win0_lock,
3419 phy_info->phy_fw_version,
3420 (u8 *)phyf->data, phyf->size);
3421 if (ret < 0)
3422 dev_err(adap->pdev_dev, "PHY Firmware transfer error %d\n",
3423 -ret);
3424 else if (ret > 0) {
3425 int new_phy_fw_ver = 0;
3426
3427 if (phy_info->phy_fw_version)
3428 new_phy_fw_ver = phy_info->phy_fw_version(phyf->data,
3429 phyf->size);
3430 dev_info(adap->pdev_dev, "Successfully transferred PHY "
3431 "Firmware /lib/firmware/%s, version %#x\n",
3432 phy_info->phy_fw_file, new_phy_fw_ver);
3433 }
3434
3435 release_firmware(phyf);
3436
3437 return ret;
3438}
3439
3440
3441
3442
3443static int adap_init0_config(struct adapter *adapter, int reset)
3444{
3445 struct fw_caps_config_cmd caps_cmd;
3446 const struct firmware *cf;
3447 unsigned long mtype = 0, maddr = 0;
3448 u32 finiver, finicsum, cfcsum;
3449 int ret;
3450 int config_issued = 0;
3451 char *fw_config_file, fw_config_file_path[256];
3452 char *config_name = NULL;
3453
3454
3455
3456
3457 if (reset) {
3458 ret = t4_fw_reset(adapter, adapter->mbox,
3459 PIORSTMODE_F | PIORST_F);
3460 if (ret < 0)
3461 goto bye;
3462 }
3463
3464
3465
3466
3467
3468
3469 if (is_10gbt_device(adapter->pdev->device)) {
3470 ret = adap_init0_phy(adapter);
3471 if (ret < 0)
3472 goto bye;
3473 }
3474
3475
3476
3477
3478
3479 switch (CHELSIO_CHIP_VERSION(adapter->params.chip)) {
3480 case CHELSIO_T4:
3481 fw_config_file = FW4_CFNAME;
3482 break;
3483 case CHELSIO_T5:
3484 fw_config_file = FW5_CFNAME;
3485 break;
3486 case CHELSIO_T6:
3487 fw_config_file = FW6_CFNAME;
3488 break;
3489 default:
3490 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
3491 adapter->pdev->device);
3492 ret = -EINVAL;
3493 goto bye;
3494 }
3495
3496 ret = request_firmware(&cf, fw_config_file, adapter->pdev_dev);
3497 if (ret < 0) {
3498 config_name = "On FLASH";
3499 mtype = FW_MEMTYPE_CF_FLASH;
3500 maddr = t4_flash_cfg_addr(adapter);
3501 } else {
3502 u32 params[7], val[7];
3503
3504 sprintf(fw_config_file_path,
3505 "/lib/firmware/%s", fw_config_file);
3506 config_name = fw_config_file_path;
3507
3508 if (cf->size >= FLASH_CFG_MAX_SIZE)
3509 ret = -ENOMEM;
3510 else {
3511 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3512 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
3513 ret = t4_query_params(adapter, adapter->mbox,
3514 adapter->pf, 0, 1, params, val);
3515 if (ret == 0) {
3516
3517
3518
3519
3520
3521
3522
3523
3524
3525
3526 size_t resid = cf->size & 0x3;
3527 size_t size = cf->size & ~0x3;
3528 __be32 *data = (__be32 *)cf->data;
3529
3530 mtype = FW_PARAMS_PARAM_Y_G(val[0]);
3531 maddr = FW_PARAMS_PARAM_Z_G(val[0]) << 16;
3532
3533 spin_lock(&adapter->win0_lock);
3534 ret = t4_memory_rw(adapter, 0, mtype, maddr,
3535 size, data, T4_MEMORY_WRITE);
3536 if (ret == 0 && resid != 0) {
3537 union {
3538 __be32 word;
3539 char buf[4];
3540 } last;
3541 int i;
3542
3543 last.word = data[size >> 2];
3544 for (i = resid; i < 4; i++)
3545 last.buf[i] = 0;
3546 ret = t4_memory_rw(adapter, 0, mtype,
3547 maddr + size,
3548 4, &last.word,
3549 T4_MEMORY_WRITE);
3550 }
3551 spin_unlock(&adapter->win0_lock);
3552 }
3553 }
3554
3555 release_firmware(cf);
3556 if (ret)
3557 goto bye;
3558 }
3559
3560
3561
3562
3563
3564
3565
3566 memset(&caps_cmd, 0, sizeof(caps_cmd));
3567 caps_cmd.op_to_write =
3568 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3569 FW_CMD_REQUEST_F |
3570 FW_CMD_READ_F);
3571 caps_cmd.cfvalid_to_len16 =
3572 htonl(FW_CAPS_CONFIG_CMD_CFVALID_F |
3573 FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(mtype) |
3574 FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(maddr >> 16) |
3575 FW_LEN16(caps_cmd));
3576 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
3577 &caps_cmd);
3578
3579
3580
3581
3582
3583
3584
3585 if (ret == -ENOENT) {
3586 memset(&caps_cmd, 0, sizeof(caps_cmd));
3587 caps_cmd.op_to_write =
3588 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3589 FW_CMD_REQUEST_F |
3590 FW_CMD_READ_F);
3591 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
3592 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd,
3593 sizeof(caps_cmd), &caps_cmd);
3594 config_name = "Firmware Default";
3595 }
3596
3597 config_issued = 1;
3598 if (ret < 0)
3599 goto bye;
3600
3601 finiver = ntohl(caps_cmd.finiver);
3602 finicsum = ntohl(caps_cmd.finicsum);
3603 cfcsum = ntohl(caps_cmd.cfcsum);
3604 if (finicsum != cfcsum)
3605 dev_warn(adapter->pdev_dev, "Configuration File checksum "\
3606 "mismatch: [fini] csum=%#x, computed csum=%#x\n",
3607 finicsum, cfcsum);
3608
3609
3610
3611
3612 caps_cmd.op_to_write =
3613 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3614 FW_CMD_REQUEST_F |
3615 FW_CMD_WRITE_F);
3616 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
3617 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
3618 NULL);
3619 if (ret < 0)
3620 goto bye;
3621
3622
3623
3624
3625
3626 ret = adap_init0_tweaks(adapter);
3627 if (ret < 0)
3628 goto bye;
3629
3630
3631
3632
3633
3634 ret = t4_fw_initialize(adapter, adapter->mbox);
3635 if (ret < 0)
3636 goto bye;
3637
3638
3639
3640
3641 dev_info(adapter->pdev_dev, "Successfully configured using Firmware "\
3642 "Configuration File \"%s\", version %#x, computed checksum %#x\n",
3643 config_name, finiver, cfcsum);
3644 return 0;
3645
3646
3647
3648
3649
3650
3651bye:
3652 if (config_issued && ret != -ENOENT)
3653 dev_warn(adapter->pdev_dev, "\"%s\" configuration file error %d\n",
3654 config_name, -ret);
3655 return ret;
3656}
3657
3658static struct fw_info fw_info_array[] = {
3659 {
3660 .chip = CHELSIO_T4,
3661 .fs_name = FW4_CFNAME,
3662 .fw_mod_name = FW4_FNAME,
3663 .fw_hdr = {
3664 .chip = FW_HDR_CHIP_T4,
3665 .fw_ver = __cpu_to_be32(FW_VERSION(T4)),
3666 .intfver_nic = FW_INTFVER(T4, NIC),
3667 .intfver_vnic = FW_INTFVER(T4, VNIC),
3668 .intfver_ri = FW_INTFVER(T4, RI),
3669 .intfver_iscsi = FW_INTFVER(T4, ISCSI),
3670 .intfver_fcoe = FW_INTFVER(T4, FCOE),
3671 },
3672 }, {
3673 .chip = CHELSIO_T5,
3674 .fs_name = FW5_CFNAME,
3675 .fw_mod_name = FW5_FNAME,
3676 .fw_hdr = {
3677 .chip = FW_HDR_CHIP_T5,
3678 .fw_ver = __cpu_to_be32(FW_VERSION(T5)),
3679 .intfver_nic = FW_INTFVER(T5, NIC),
3680 .intfver_vnic = FW_INTFVER(T5, VNIC),
3681 .intfver_ri = FW_INTFVER(T5, RI),
3682 .intfver_iscsi = FW_INTFVER(T5, ISCSI),
3683 .intfver_fcoe = FW_INTFVER(T5, FCOE),
3684 },
3685 }, {
3686 .chip = CHELSIO_T6,
3687 .fs_name = FW6_CFNAME,
3688 .fw_mod_name = FW6_FNAME,
3689 .fw_hdr = {
3690 .chip = FW_HDR_CHIP_T6,
3691 .fw_ver = __cpu_to_be32(FW_VERSION(T6)),
3692 .intfver_nic = FW_INTFVER(T6, NIC),
3693 .intfver_vnic = FW_INTFVER(T6, VNIC),
3694 .intfver_ofld = FW_INTFVER(T6, OFLD),
3695 .intfver_ri = FW_INTFVER(T6, RI),
3696 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU),
3697 .intfver_iscsi = FW_INTFVER(T6, ISCSI),
3698 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU),
3699 .intfver_fcoe = FW_INTFVER(T6, FCOE),
3700 },
3701 }
3702
3703};
3704
3705static struct fw_info *find_fw_info(int chip)
3706{
3707 int i;
3708
3709 for (i = 0; i < ARRAY_SIZE(fw_info_array); i++) {
3710 if (fw_info_array[i].chip == chip)
3711 return &fw_info_array[i];
3712 }
3713 return NULL;
3714}
3715
3716
3717
3718
3719static int adap_init0(struct adapter *adap)
3720{
3721 int ret;
3722 u32 v, port_vec;
3723 enum dev_state state;
3724 u32 params[7], val[7];
3725 struct fw_caps_config_cmd caps_cmd;
3726 int reset = 1;
3727
3728
3729
3730
3731 ret = t4_init_devlog_params(adap);
3732 if (ret < 0)
3733 return ret;
3734
3735
3736 ret = t4_fw_hello(adap, adap->mbox, adap->mbox,
3737 is_kdump_kernel() ? MASTER_MUST : MASTER_MAY, &state);
3738 if (ret < 0) {
3739 dev_err(adap->pdev_dev, "could not connect to FW, error %d\n",
3740 ret);
3741 return ret;
3742 }
3743 if (ret == adap->mbox)
3744 adap->flags |= MASTER_PF;
3745
3746
3747
3748
3749
3750
3751
3752
3753 t4_get_fw_version(adap, &adap->params.fw_vers);
3754 t4_get_bs_version(adap, &adap->params.bs_vers);
3755 t4_get_tp_version(adap, &adap->params.tp_vers);
3756 t4_get_exprom_version(adap, &adap->params.er_vers);
3757
3758 ret = t4_check_fw_version(adap);
3759
3760 if (ret)
3761 state = DEV_STATE_UNINIT;
3762 if ((adap->flags & MASTER_PF) && state != DEV_STATE_INIT) {
3763 struct fw_info *fw_info;
3764 struct fw_hdr *card_fw;
3765 const struct firmware *fw;
3766 const u8 *fw_data = NULL;
3767 unsigned int fw_size = 0;
3768
3769
3770
3771
3772 fw_info = find_fw_info(CHELSIO_CHIP_VERSION(adap->params.chip));
3773 if (fw_info == NULL) {
3774 dev_err(adap->pdev_dev,
3775 "unable to get firmware info for chip %d.\n",
3776 CHELSIO_CHIP_VERSION(adap->params.chip));
3777 return -EINVAL;
3778 }
3779
3780
3781
3782
3783 card_fw = t4_alloc_mem(sizeof(*card_fw));
3784
3785
3786 ret = request_firmware(&fw, fw_info->fw_mod_name,
3787 adap->pdev_dev);
3788 if (ret < 0) {
3789 dev_err(adap->pdev_dev,
3790 "unable to load firmware image %s, error %d\n",
3791 fw_info->fw_mod_name, ret);
3792 } else {
3793 fw_data = fw->data;
3794 fw_size = fw->size;
3795 }
3796
3797
3798 ret = t4_prep_fw(adap, fw_info, fw_data, fw_size, card_fw,
3799 state, &reset);
3800
3801
3802 release_firmware(fw);
3803 t4_free_mem(card_fw);
3804
3805 if (ret < 0)
3806 goto bye;
3807 }
3808
3809
3810
3811
3812
3813
3814
3815
3816 ret = t4_get_vpd_params(adap, &adap->params.vpd);
3817 if (ret < 0)
3818 goto bye;
3819
3820
3821
3822
3823
3824
3825 v =
3826 FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3827 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PORTVEC);
3828 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec);
3829 if (ret < 0)
3830 goto bye;
3831
3832 adap->params.nports = hweight32(port_vec);
3833 adap->params.portvec = port_vec;
3834
3835
3836
3837
3838 if (state == DEV_STATE_INIT) {
3839 dev_info(adap->pdev_dev, "Coming up as %s: "\
3840 "Adapter already initialized\n",
3841 adap->flags & MASTER_PF ? "MASTER" : "SLAVE");
3842 } else {
3843 dev_info(adap->pdev_dev, "Coming up as MASTER: "\
3844 "Initializing adapter\n");
3845
3846
3847
3848
3849 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3850 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
3851 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
3852 params, val);
3853
3854
3855
3856
3857 if (ret < 0) {
3858 dev_err(adap->pdev_dev, "firmware doesn't support "
3859 "Firmware Configuration Files\n");
3860 goto bye;
3861 }
3862
3863
3864
3865
3866
3867 ret = adap_init0_config(adap, reset);
3868 if (ret == -ENOENT) {
3869 dev_err(adap->pdev_dev, "no Configuration File "
3870 "present on adapter.\n");
3871 goto bye;
3872 }
3873 if (ret < 0) {
3874 dev_err(adap->pdev_dev, "could not initialize "
3875 "adapter, error %d\n", -ret);
3876 goto bye;
3877 }
3878 }
3879
3880
3881
3882
3883
3884 ret = t4_sge_init(adap);
3885 if (ret < 0)
3886 goto bye;
3887
3888 if (is_bypass_device(adap->pdev->device))
3889 adap->params.bypass = 1;
3890
3891
3892
3893
3894#define FW_PARAM_DEV(param) \
3895 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | \
3896 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_##param))
3897
3898#define FW_PARAM_PFVF(param) \
3899 FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \
3900 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param)| \
3901 FW_PARAMS_PARAM_Y_V(0) | \
3902 FW_PARAMS_PARAM_Z_V(0)
3903
3904 params[0] = FW_PARAM_PFVF(EQ_START);
3905 params[1] = FW_PARAM_PFVF(L2T_START);
3906 params[2] = FW_PARAM_PFVF(L2T_END);
3907 params[3] = FW_PARAM_PFVF(FILTER_START);
3908 params[4] = FW_PARAM_PFVF(FILTER_END);
3909 params[5] = FW_PARAM_PFVF(IQFLINT_START);
3910 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params, val);
3911 if (ret < 0)
3912 goto bye;
3913 adap->sge.egr_start = val[0];
3914 adap->l2t_start = val[1];
3915 adap->l2t_end = val[2];
3916 adap->tids.ftid_base = val[3];
3917 adap->tids.nftids = val[4] - val[3] + 1;
3918 adap->sge.ingr_start = val[5];
3919
3920
3921
3922
3923
3924
3925
3926 params[0] = FW_PARAM_PFVF(EQ_END);
3927 params[1] = FW_PARAM_PFVF(IQFLINT_END);
3928 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
3929 if (ret < 0)
3930 goto bye;
3931 adap->sge.egr_sz = val[0] - adap->sge.egr_start + 1;
3932 adap->sge.ingr_sz = val[1] - adap->sge.ingr_start + 1;
3933
3934 adap->sge.egr_map = kcalloc(adap->sge.egr_sz,
3935 sizeof(*adap->sge.egr_map), GFP_KERNEL);
3936 if (!adap->sge.egr_map) {
3937 ret = -ENOMEM;
3938 goto bye;
3939 }
3940
3941 adap->sge.ingr_map = kcalloc(adap->sge.ingr_sz,
3942 sizeof(*adap->sge.ingr_map), GFP_KERNEL);
3943 if (!adap->sge.ingr_map) {
3944 ret = -ENOMEM;
3945 goto bye;
3946 }
3947
3948
3949
3950
3951 adap->sge.starving_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
3952 sizeof(long), GFP_KERNEL);
3953 if (!adap->sge.starving_fl) {
3954 ret = -ENOMEM;
3955 goto bye;
3956 }
3957
3958 adap->sge.txq_maperr = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
3959 sizeof(long), GFP_KERNEL);
3960 if (!adap->sge.txq_maperr) {
3961 ret = -ENOMEM;
3962 goto bye;
3963 }
3964
3965#ifdef CONFIG_DEBUG_FS
3966 adap->sge.blocked_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
3967 sizeof(long), GFP_KERNEL);
3968 if (!adap->sge.blocked_fl) {
3969 ret = -ENOMEM;
3970 goto bye;
3971 }
3972#endif
3973
3974 params[0] = FW_PARAM_PFVF(CLIP_START);
3975 params[1] = FW_PARAM_PFVF(CLIP_END);
3976 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
3977 if (ret < 0)
3978 goto bye;
3979 adap->clipt_start = val[0];
3980 adap->clipt_end = val[1];
3981
3982
3983 params[0] = FW_PARAM_PFVF(ACTIVE_FILTER_START);
3984 params[1] = FW_PARAM_PFVF(ACTIVE_FILTER_END);
3985 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
3986
3987
3988
3989 if ((val[0] != val[1]) && (ret >= 0)) {
3990 adap->flags |= FW_OFLD_CONN;
3991 adap->tids.aftid_base = val[0];
3992 adap->tids.aftid_end = val[1];
3993 }
3994
3995
3996
3997
3998
3999
4000 params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
4001 val[0] = 1;
4002 (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
4003
4004
4005
4006
4007
4008
4009
4010 if (is_t4(adap->params.chip)) {
4011 adap->params.ulptx_memwrite_dsgl = false;
4012 } else {
4013 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
4014 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
4015 1, params, val);
4016 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
4017 }
4018
4019
4020
4021
4022
4023 memset(&caps_cmd, 0, sizeof(caps_cmd));
4024 caps_cmd.op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
4025 FW_CMD_REQUEST_F | FW_CMD_READ_F);
4026 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
4027 ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd),
4028 &caps_cmd);
4029 if (ret < 0)
4030 goto bye;
4031
4032 if (caps_cmd.ofldcaps) {
4033
4034 params[0] = FW_PARAM_DEV(NTID);
4035 params[1] = FW_PARAM_PFVF(SERVER_START);
4036 params[2] = FW_PARAM_PFVF(SERVER_END);
4037 params[3] = FW_PARAM_PFVF(TDDP_START);
4038 params[4] = FW_PARAM_PFVF(TDDP_END);
4039 params[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
4040 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6,
4041 params, val);
4042 if (ret < 0)
4043 goto bye;
4044 adap->tids.ntids = val[0];
4045 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
4046 adap->tids.stid_base = val[1];
4047 adap->tids.nstids = val[2] - val[1] + 1;
4048
4049
4050
4051
4052
4053
4054
4055
4056
4057 if (adap->flags & FW_OFLD_CONN && !is_bypass(adap)) {
4058 adap->tids.sftid_base = adap->tids.ftid_base +
4059 DIV_ROUND_UP(adap->tids.nftids, 3);
4060 adap->tids.nsftids = adap->tids.nftids -
4061 DIV_ROUND_UP(adap->tids.nftids, 3);
4062 adap->tids.nftids = adap->tids.sftid_base -
4063 adap->tids.ftid_base;
4064 }
4065 adap->vres.ddp.start = val[3];
4066 adap->vres.ddp.size = val[4] - val[3] + 1;
4067 adap->params.ofldq_wr_cred = val[5];
4068
4069 adap->params.offload = 1;
4070 }
4071 if (caps_cmd.rdmacaps) {
4072 params[0] = FW_PARAM_PFVF(STAG_START);
4073 params[1] = FW_PARAM_PFVF(STAG_END);
4074 params[2] = FW_PARAM_PFVF(RQ_START);
4075 params[3] = FW_PARAM_PFVF(RQ_END);
4076 params[4] = FW_PARAM_PFVF(PBL_START);
4077 params[5] = FW_PARAM_PFVF(PBL_END);
4078 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6,
4079 params, val);
4080 if (ret < 0)
4081 goto bye;
4082 adap->vres.stag.start = val[0];
4083 adap->vres.stag.size = val[1] - val[0] + 1;
4084 adap->vres.rq.start = val[2];
4085 adap->vres.rq.size = val[3] - val[2] + 1;
4086 adap->vres.pbl.start = val[4];
4087 adap->vres.pbl.size = val[5] - val[4] + 1;
4088
4089 params[0] = FW_PARAM_PFVF(SQRQ_START);
4090 params[1] = FW_PARAM_PFVF(SQRQ_END);
4091 params[2] = FW_PARAM_PFVF(CQ_START);
4092 params[3] = FW_PARAM_PFVF(CQ_END);
4093 params[4] = FW_PARAM_PFVF(OCQ_START);
4094 params[5] = FW_PARAM_PFVF(OCQ_END);
4095 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params,
4096 val);
4097 if (ret < 0)
4098 goto bye;
4099 adap->vres.qp.start = val[0];
4100 adap->vres.qp.size = val[1] - val[0] + 1;
4101 adap->vres.cq.start = val[2];
4102 adap->vres.cq.size = val[3] - val[2] + 1;
4103 adap->vres.ocq.start = val[4];
4104 adap->vres.ocq.size = val[5] - val[4] + 1;
4105
4106 params[0] = FW_PARAM_DEV(MAXORDIRD_QP);
4107 params[1] = FW_PARAM_DEV(MAXIRD_ADAPTER);
4108 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params,
4109 val);
4110 if (ret < 0) {
4111 adap->params.max_ordird_qp = 8;
4112 adap->params.max_ird_adapter = 32 * adap->tids.ntids;
4113 ret = 0;
4114 } else {
4115 adap->params.max_ordird_qp = val[0];
4116 adap->params.max_ird_adapter = val[1];
4117 }
4118 dev_info(adap->pdev_dev,
4119 "max_ordird_qp %d max_ird_adapter %d\n",
4120 adap->params.max_ordird_qp,
4121 adap->params.max_ird_adapter);
4122 }
4123 if (caps_cmd.iscsicaps) {
4124 params[0] = FW_PARAM_PFVF(ISCSI_START);
4125 params[1] = FW_PARAM_PFVF(ISCSI_END);
4126 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
4127 params, val);
4128 if (ret < 0)
4129 goto bye;
4130 adap->vres.iscsi.start = val[0];
4131 adap->vres.iscsi.size = val[1] - val[0] + 1;
4132 }
4133#undef FW_PARAM_PFVF
4134#undef FW_PARAM_DEV
4135
4136
4137
4138
4139
4140
4141 t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
4142 if (state != DEV_STATE_INIT) {
4143 int i;
4144
4145
4146
4147
4148
4149
4150
4151
4152
4153
4154
4155
4156
4157
4158
4159
4160
4161
4162 for (i = 0; i < NMTUS; i++)
4163 if (adap->params.mtus[i] == 1492) {
4164 adap->params.mtus[i] = 1488;
4165 break;
4166 }
4167
4168 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
4169 adap->params.b_wnd);
4170 }
4171 t4_init_sge_params(adap);
4172 adap->flags |= FW_OK;
4173 t4_init_tp_params(adap);
4174 return 0;
4175
4176
4177
4178
4179
4180
4181bye:
4182 kfree(adap->sge.egr_map);
4183 kfree(adap->sge.ingr_map);
4184 kfree(adap->sge.starving_fl);
4185 kfree(adap->sge.txq_maperr);
4186#ifdef CONFIG_DEBUG_FS
4187 kfree(adap->sge.blocked_fl);
4188#endif
4189 if (ret != -ETIMEDOUT && ret != -EIO)
4190 t4_fw_bye(adap, adap->mbox);
4191 return ret;
4192}
4193
4194
4195
4196static pci_ers_result_t eeh_err_detected(struct pci_dev *pdev,
4197 pci_channel_state_t state)
4198{
4199 int i;
4200 struct adapter *adap = pci_get_drvdata(pdev);
4201
4202 if (!adap)
4203 goto out;
4204
4205 rtnl_lock();
4206 adap->flags &= ~FW_OK;
4207 notify_ulds(adap, CXGB4_STATE_START_RECOVERY);
4208 spin_lock(&adap->stats_lock);
4209 for_each_port(adap, i) {
4210 struct net_device *dev = adap->port[i];
4211
4212 netif_device_detach(dev);
4213 netif_carrier_off(dev);
4214 }
4215 spin_unlock(&adap->stats_lock);
4216 disable_interrupts(adap);
4217 if (adap->flags & FULL_INIT_DONE)
4218 cxgb_down(adap);
4219 rtnl_unlock();
4220 if ((adap->flags & DEV_ENABLED)) {
4221 pci_disable_device(pdev);
4222 adap->flags &= ~DEV_ENABLED;
4223 }
4224out: return state == pci_channel_io_perm_failure ?
4225 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
4226}
4227
4228static pci_ers_result_t eeh_slot_reset(struct pci_dev *pdev)
4229{
4230 int i, ret;
4231 struct fw_caps_config_cmd c;
4232 struct adapter *adap = pci_get_drvdata(pdev);
4233
4234 if (!adap) {
4235 pci_restore_state(pdev);
4236 pci_save_state(pdev);
4237 return PCI_ERS_RESULT_RECOVERED;
4238 }
4239
4240 if (!(adap->flags & DEV_ENABLED)) {
4241 if (pci_enable_device(pdev)) {
4242 dev_err(&pdev->dev, "Cannot reenable PCI "
4243 "device after reset\n");
4244 return PCI_ERS_RESULT_DISCONNECT;
4245 }
4246 adap->flags |= DEV_ENABLED;
4247 }
4248
4249 pci_set_master(pdev);
4250 pci_restore_state(pdev);
4251 pci_save_state(pdev);
4252 pci_cleanup_aer_uncorrect_error_status(pdev);
4253
4254 if (t4_wait_dev_ready(adap->regs) < 0)
4255 return PCI_ERS_RESULT_DISCONNECT;
4256 if (t4_fw_hello(adap, adap->mbox, adap->pf, MASTER_MUST, NULL) < 0)
4257 return PCI_ERS_RESULT_DISCONNECT;
4258 adap->flags |= FW_OK;
4259 if (adap_init1(adap, &c))
4260 return PCI_ERS_RESULT_DISCONNECT;
4261
4262 for_each_port(adap, i) {
4263 struct port_info *p = adap2pinfo(adap, i);
4264
4265 ret = t4_alloc_vi(adap, adap->mbox, p->tx_chan, adap->pf, 0, 1,
4266 NULL, NULL);
4267 if (ret < 0)
4268 return PCI_ERS_RESULT_DISCONNECT;
4269 p->viid = ret;
4270 p->xact_addr_filt = -1;
4271 }
4272
4273 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
4274 adap->params.b_wnd);
4275 setup_memwin(adap);
4276 if (cxgb_up(adap))
4277 return PCI_ERS_RESULT_DISCONNECT;
4278 return PCI_ERS_RESULT_RECOVERED;
4279}
4280
4281static void eeh_resume(struct pci_dev *pdev)
4282{
4283 int i;
4284 struct adapter *adap = pci_get_drvdata(pdev);
4285
4286 if (!adap)
4287 return;
4288
4289 rtnl_lock();
4290 for_each_port(adap, i) {
4291 struct net_device *dev = adap->port[i];
4292
4293 if (netif_running(dev)) {
4294 link_start(dev);
4295 cxgb_set_rxmode(dev);
4296 }
4297 netif_device_attach(dev);
4298 }
4299 rtnl_unlock();
4300}
4301
4302static const struct pci_error_handlers cxgb4_eeh = {
4303 .error_detected = eeh_err_detected,
4304 .slot_reset = eeh_slot_reset,
4305 .resume = eeh_resume,
4306};
4307
4308
4309
4310
4311static inline bool is_x_10g_port(const struct link_config *lc)
4312{
4313 unsigned int speeds, high_speeds;
4314
4315 speeds = FW_PORT_CAP_SPEED_V(FW_PORT_CAP_SPEED_G(lc->supported));
4316 high_speeds = speeds & ~(FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G);
4317
4318 return high_speeds != 0;
4319}
4320
4321static inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
4322 unsigned int us, unsigned int cnt,
4323 unsigned int size, unsigned int iqe_size)
4324{
4325 q->adap = adap;
4326 cxgb4_set_rspq_intr_params(q, us, cnt);
4327 q->iqe_len = iqe_size;
4328 q->size = size;
4329}
4330
4331
4332
4333
4334
4335
4336static void cfg_queues(struct adapter *adap)
4337{
4338 struct sge *s = &adap->sge;
4339 int i, n10g = 0, qidx = 0;
4340#ifndef CONFIG_CHELSIO_T4_DCB
4341 int q10g = 0;
4342#endif
4343 int ciq_size;
4344
4345
4346
4347 if (is_kdump_kernel())
4348 adap->params.offload = 0;
4349
4350 for_each_port(adap, i)
4351 n10g += is_x_10g_port(&adap2pinfo(adap, i)->link_cfg);
4352#ifdef CONFIG_CHELSIO_T4_DCB
4353
4354
4355
4356
4357 if (adap->params.nports * 8 > MAX_ETH_QSETS) {
4358 dev_err(adap->pdev_dev, "MAX_ETH_QSETS=%d < %d!\n",
4359 MAX_ETH_QSETS, adap->params.nports * 8);
4360 BUG_ON(1);
4361 }
4362
4363 for_each_port(adap, i) {
4364 struct port_info *pi = adap2pinfo(adap, i);
4365
4366 pi->first_qset = qidx;
4367 pi->nqsets = 8;
4368 qidx += pi->nqsets;
4369 }
4370#else
4371
4372
4373
4374
4375 if (n10g)
4376 q10g = (MAX_ETH_QSETS - (adap->params.nports - n10g)) / n10g;
4377 if (q10g > netif_get_num_default_rss_queues())
4378 q10g = netif_get_num_default_rss_queues();
4379
4380 for_each_port(adap, i) {
4381 struct port_info *pi = adap2pinfo(adap, i);
4382
4383 pi->first_qset = qidx;
4384 pi->nqsets = is_x_10g_port(&pi->link_cfg) ? q10g : 1;
4385 qidx += pi->nqsets;
4386 }
4387#endif
4388
4389 s->ethqsets = qidx;
4390 s->max_ethqsets = qidx;
4391
4392 if (is_offload(adap)) {
4393
4394
4395
4396
4397
4398 if (n10g) {
4399 i = min_t(int, ARRAY_SIZE(s->iscsirxq),
4400 num_online_cpus());
4401 s->iscsiqsets = roundup(i, adap->params.nports);
4402 } else
4403 s->iscsiqsets = adap->params.nports;
4404
4405 s->rdmaqs = adap->params.nports;
4406
4407
4408
4409
4410
4411
4412 s->rdmaciqs = min_t(int, MAX_RDMA_CIQS, num_online_cpus());
4413 s->rdmaciqs = (s->rdmaciqs / adap->params.nports) *
4414 adap->params.nports;
4415 s->rdmaciqs = max_t(int, s->rdmaciqs, adap->params.nports);
4416
4417 if (!is_t4(adap->params.chip))
4418 s->niscsitq = s->iscsiqsets;
4419 }
4420
4421 for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {
4422 struct sge_eth_rxq *r = &s->ethrxq[i];
4423
4424 init_rspq(adap, &r->rspq, 5, 10, 1024, 64);
4425 r->fl.size = 72;
4426 }
4427
4428 for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)
4429 s->ethtxq[i].q.size = 1024;
4430
4431 for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++)
4432 s->ctrlq[i].q.size = 512;
4433
4434 for (i = 0; i < ARRAY_SIZE(s->ofldtxq); i++)
4435 s->ofldtxq[i].q.size = 1024;
4436
4437 for (i = 0; i < ARRAY_SIZE(s->iscsirxq); i++) {
4438 struct sge_ofld_rxq *r = &s->iscsirxq[i];
4439
4440 init_rspq(adap, &r->rspq, 5, 1, 1024, 64);
4441 r->rspq.uld = CXGB4_ULD_ISCSI;
4442 r->fl.size = 72;
4443 }
4444
4445 if (!is_t4(adap->params.chip)) {
4446 for (i = 0; i < ARRAY_SIZE(s->iscsitrxq); i++) {
4447 struct sge_ofld_rxq *r = &s->iscsitrxq[i];
4448
4449 init_rspq(adap, &r->rspq, 5, 1, 1024, 64);
4450 r->rspq.uld = CXGB4_ULD_ISCSIT;
4451 r->fl.size = 72;
4452 }
4453 }
4454
4455 for (i = 0; i < ARRAY_SIZE(s->rdmarxq); i++) {
4456 struct sge_ofld_rxq *r = &s->rdmarxq[i];
4457
4458 init_rspq(adap, &r->rspq, 5, 1, 511, 64);
4459 r->rspq.uld = CXGB4_ULD_RDMA;
4460 r->fl.size = 72;
4461 }
4462
4463 ciq_size = 64 + adap->vres.cq.size + adap->tids.nftids;
4464 if (ciq_size > SGE_MAX_IQ_SIZE) {
4465 CH_WARN(adap, "CIQ size too small for available IQs\n");
4466 ciq_size = SGE_MAX_IQ_SIZE;
4467 }
4468
4469 for (i = 0; i < ARRAY_SIZE(s->rdmaciq); i++) {
4470 struct sge_ofld_rxq *r = &s->rdmaciq[i];
4471
4472 init_rspq(adap, &r->rspq, 5, 1, ciq_size, 64);
4473 r->rspq.uld = CXGB4_ULD_RDMA;
4474 }
4475
4476 init_rspq(adap, &s->fw_evtq, 0, 1, 1024, 64);
4477 init_rspq(adap, &s->intrq, 0, 1, 2 * MAX_INGQ, 64);
4478}
4479
4480
4481
4482
4483
4484static void reduce_ethqs(struct adapter *adap, int n)
4485{
4486 int i;
4487 struct port_info *pi;
4488
4489 while (n < adap->sge.ethqsets)
4490 for_each_port(adap, i) {
4491 pi = adap2pinfo(adap, i);
4492 if (pi->nqsets > 1) {
4493 pi->nqsets--;
4494 adap->sge.ethqsets--;
4495 if (adap->sge.ethqsets <= n)
4496 break;
4497 }
4498 }
4499
4500 n = 0;
4501 for_each_port(adap, i) {
4502 pi = adap2pinfo(adap, i);
4503 pi->first_qset = n;
4504 n += pi->nqsets;
4505 }
4506}
4507
4508
4509#define EXTRA_VECS 2
4510
4511static int enable_msix(struct adapter *adap)
4512{
4513 int ofld_need = 0;
4514 int i, want, need, allocated;
4515 struct sge *s = &adap->sge;
4516 unsigned int nchan = adap->params.nports;
4517 struct msix_entry *entries;
4518
4519 entries = kmalloc(sizeof(*entries) * (MAX_INGQ + 1),
4520 GFP_KERNEL);
4521 if (!entries)
4522 return -ENOMEM;
4523
4524 for (i = 0; i < MAX_INGQ + 1; ++i)
4525 entries[i].entry = i;
4526
4527 want = s->max_ethqsets + EXTRA_VECS;
4528 if (is_offload(adap)) {
4529 want += s->rdmaqs + s->rdmaciqs + s->iscsiqsets +
4530 s->niscsitq;
4531
4532 if (is_t4(adap->params.chip))
4533 ofld_need = 3 * nchan;
4534 else
4535 ofld_need = 4 * nchan;
4536 }
4537#ifdef CONFIG_CHELSIO_T4_DCB
4538
4539
4540
4541 need = 8 * adap->params.nports + EXTRA_VECS + ofld_need;
4542#else
4543 need = adap->params.nports + EXTRA_VECS + ofld_need;
4544#endif
4545 allocated = pci_enable_msix_range(adap->pdev, entries, need, want);
4546 if (allocated < 0) {
4547 dev_info(adap->pdev_dev, "not enough MSI-X vectors left,"
4548 " not using MSI-X\n");
4549 kfree(entries);
4550 return allocated;
4551 }
4552
4553
4554
4555
4556
4557 i = allocated - EXTRA_VECS - ofld_need;
4558 if (i < s->max_ethqsets) {
4559 s->max_ethqsets = i;
4560 if (i < s->ethqsets)
4561 reduce_ethqs(adap, i);
4562 }
4563 if (is_offload(adap)) {
4564 if (allocated < want) {
4565 s->rdmaqs = nchan;
4566 s->rdmaciqs = nchan;
4567
4568 if (!is_t4(adap->params.chip))
4569 s->niscsitq = nchan;
4570 }
4571
4572
4573 i = allocated - EXTRA_VECS - s->max_ethqsets -
4574 s->rdmaqs - s->rdmaciqs - s->niscsitq;
4575 s->iscsiqsets = (i / nchan) * nchan;
4576
4577 }
4578 for (i = 0; i < allocated; ++i)
4579 adap->msix_info[i].vec = entries[i].vector;
4580 dev_info(adap->pdev_dev, "%d MSI-X vectors allocated, "
4581 "nic %d iscsi %d rdma cpl %d rdma ciq %d\n",
4582 allocated, s->max_ethqsets, s->iscsiqsets, s->rdmaqs,
4583 s->rdmaciqs);
4584
4585 kfree(entries);
4586 return 0;
4587}
4588
4589#undef EXTRA_VECS
4590
4591static int init_rss(struct adapter *adap)
4592{
4593 unsigned int i;
4594 int err;
4595
4596 err = t4_init_rss_mode(adap, adap->mbox);
4597 if (err)
4598 return err;
4599
4600 for_each_port(adap, i) {
4601 struct port_info *pi = adap2pinfo(adap, i);
4602
4603 pi->rss = kcalloc(pi->rss_size, sizeof(u16), GFP_KERNEL);
4604 if (!pi->rss)
4605 return -ENOMEM;
4606 }
4607 return 0;
4608}
4609
4610static int cxgb4_get_pcie_dev_link_caps(struct adapter *adap,
4611 enum pci_bus_speed *speed,
4612 enum pcie_link_width *width)
4613{
4614 u32 lnkcap1, lnkcap2;
4615 int err1, err2;
4616
4617#define PCIE_MLW_CAP_SHIFT 4
4618
4619 *speed = PCI_SPEED_UNKNOWN;
4620 *width = PCIE_LNK_WIDTH_UNKNOWN;
4621
4622 err1 = pcie_capability_read_dword(adap->pdev, PCI_EXP_LNKCAP,
4623 &lnkcap1);
4624 err2 = pcie_capability_read_dword(adap->pdev, PCI_EXP_LNKCAP2,
4625 &lnkcap2);
4626 if (!err2 && lnkcap2) {
4627 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
4628 *speed = PCIE_SPEED_8_0GT;
4629 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
4630 *speed = PCIE_SPEED_5_0GT;
4631 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
4632 *speed = PCIE_SPEED_2_5GT;
4633 }
4634 if (!err1) {
4635 *width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT;
4636 if (!lnkcap2) {
4637 if (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB)
4638 *speed = PCIE_SPEED_5_0GT;
4639 else if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB)
4640 *speed = PCIE_SPEED_2_5GT;
4641 }
4642 }
4643
4644 if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN)
4645 return err1 ? err1 : err2 ? err2 : -EINVAL;
4646 return 0;
4647}
4648
4649static void cxgb4_check_pcie_caps(struct adapter *adap)
4650{
4651 enum pcie_link_width width, width_cap;
4652 enum pci_bus_speed speed, speed_cap;
4653
4654#define PCIE_SPEED_STR(speed) \
4655 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \
4656 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \
4657 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \
4658 "Unknown")
4659
4660 if (cxgb4_get_pcie_dev_link_caps(adap, &speed_cap, &width_cap)) {
4661 dev_warn(adap->pdev_dev,
4662 "Unable to determine PCIe device BW capabilities\n");
4663 return;
4664 }
4665
4666 if (pcie_get_minimum_link(adap->pdev, &speed, &width) ||
4667 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) {
4668 dev_warn(adap->pdev_dev,
4669 "Unable to determine PCI Express bandwidth.\n");
4670 return;
4671 }
4672
4673 dev_info(adap->pdev_dev, "PCIe link speed is %s, device supports %s\n",
4674 PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap));
4675 dev_info(adap->pdev_dev, "PCIe link width is x%d, device supports x%d\n",
4676 width, width_cap);
4677 if (speed < speed_cap || width < width_cap)
4678 dev_info(adap->pdev_dev,
4679 "A slot with more lanes and/or higher speed is "
4680 "suggested for optimal performance.\n");
4681}
4682
4683
4684static void print_adapter_info(struct adapter *adapter)
4685{
4686
4687 dev_info(adapter->pdev_dev, "Chelsio %s rev %d\n",
4688 adapter->params.vpd.id,
4689 CHELSIO_CHIP_RELEASE(adapter->params.chip));
4690 dev_info(adapter->pdev_dev, "S/N: %s, P/N: %s\n",
4691 adapter->params.vpd.sn, adapter->params.vpd.pn);
4692
4693
4694 if (!adapter->params.fw_vers)
4695 dev_warn(adapter->pdev_dev, "No firmware loaded\n");
4696 else
4697 dev_info(adapter->pdev_dev, "Firmware version: %u.%u.%u.%u\n",
4698 FW_HDR_FW_VER_MAJOR_G(adapter->params.fw_vers),
4699 FW_HDR_FW_VER_MINOR_G(adapter->params.fw_vers),
4700 FW_HDR_FW_VER_MICRO_G(adapter->params.fw_vers),
4701 FW_HDR_FW_VER_BUILD_G(adapter->params.fw_vers));
4702
4703
4704
4705
4706 if (!adapter->params.bs_vers)
4707 dev_info(adapter->pdev_dev, "No bootstrap loaded\n");
4708 else
4709 dev_info(adapter->pdev_dev, "Bootstrap version: %u.%u.%u.%u\n",
4710 FW_HDR_FW_VER_MAJOR_G(adapter->params.bs_vers),
4711 FW_HDR_FW_VER_MINOR_G(adapter->params.bs_vers),
4712 FW_HDR_FW_VER_MICRO_G(adapter->params.bs_vers),
4713 FW_HDR_FW_VER_BUILD_G(adapter->params.bs_vers));
4714
4715
4716 if (!adapter->params.tp_vers)
4717 dev_warn(adapter->pdev_dev, "No TP Microcode loaded\n");
4718 else
4719 dev_info(adapter->pdev_dev,
4720 "TP Microcode version: %u.%u.%u.%u\n",
4721 FW_HDR_FW_VER_MAJOR_G(adapter->params.tp_vers),
4722 FW_HDR_FW_VER_MINOR_G(adapter->params.tp_vers),
4723 FW_HDR_FW_VER_MICRO_G(adapter->params.tp_vers),
4724 FW_HDR_FW_VER_BUILD_G(adapter->params.tp_vers));
4725
4726
4727 if (!adapter->params.er_vers)
4728 dev_info(adapter->pdev_dev, "No Expansion ROM loaded\n");
4729 else
4730 dev_info(adapter->pdev_dev,
4731 "Expansion ROM version: %u.%u.%u.%u\n",
4732 FW_HDR_FW_VER_MAJOR_G(adapter->params.er_vers),
4733 FW_HDR_FW_VER_MINOR_G(adapter->params.er_vers),
4734 FW_HDR_FW_VER_MICRO_G(adapter->params.er_vers),
4735 FW_HDR_FW_VER_BUILD_G(adapter->params.er_vers));
4736
4737
4738 dev_info(adapter->pdev_dev, "Configuration: %sNIC %s, %s capable\n",
4739 is_offload(adapter) ? "R" : "",
4740 ((adapter->flags & USING_MSIX) ? "MSI-X" :
4741 (adapter->flags & USING_MSI) ? "MSI" : ""),
4742 is_offload(adapter) ? "Offload" : "non-Offload");
4743}
4744
4745static void print_port_info(const struct net_device *dev)
4746{
4747 char buf[80];
4748 char *bufp = buf;
4749 const char *spd = "";
4750 const struct port_info *pi = netdev_priv(dev);
4751 const struct adapter *adap = pi->adapter;
4752
4753 if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_2_5GB)
4754 spd = " 2.5 GT/s";
4755 else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_5_0GB)
4756 spd = " 5 GT/s";
4757 else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_8_0GB)
4758 spd = " 8 GT/s";
4759
4760 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100M)
4761 bufp += sprintf(bufp, "100/");
4762 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G)
4763 bufp += sprintf(bufp, "1000/");
4764 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G)
4765 bufp += sprintf(bufp, "10G/");
4766 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_25G)
4767 bufp += sprintf(bufp, "25G/");
4768 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G)
4769 bufp += sprintf(bufp, "40G/");
4770 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100G)
4771 bufp += sprintf(bufp, "100G/");
4772 if (bufp != buf)
4773 --bufp;
4774 sprintf(bufp, "BASE-%s", t4_get_port_type_description(pi->port_type));
4775
4776 netdev_info(dev, "%s: Chelsio %s (%s) %s\n",
4777 dev->name, adap->params.vpd.id, adap->name, buf);
4778}
4779
4780static void enable_pcie_relaxed_ordering(struct pci_dev *dev)
4781{
4782 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN);
4783}
4784
4785
4786
4787
4788
4789
4790
4791
4792static void free_some_resources(struct adapter *adapter)
4793{
4794 unsigned int i;
4795
4796 t4_free_mem(adapter->l2t);
4797 t4_free_mem(adapter->tids.tid_tab);
4798 kfree(adapter->sge.egr_map);
4799 kfree(adapter->sge.ingr_map);
4800 kfree(adapter->sge.starving_fl);
4801 kfree(adapter->sge.txq_maperr);
4802#ifdef CONFIG_DEBUG_FS
4803 kfree(adapter->sge.blocked_fl);
4804#endif
4805 disable_msi(adapter);
4806
4807 for_each_port(adapter, i)
4808 if (adapter->port[i]) {
4809 struct port_info *pi = adap2pinfo(adapter, i);
4810
4811 if (pi->viid != 0)
4812 t4_free_vi(adapter, adapter->mbox, adapter->pf,
4813 0, pi->viid);
4814 kfree(adap2pinfo(adapter, i)->rss);
4815 free_netdev(adapter->port[i]);
4816 }
4817 if (adapter->flags & FW_OK)
4818 t4_fw_bye(adapter, adapter->pf);
4819}
4820
4821#define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN)
4822#define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | TSO_FLAGS | \
4823 NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA)
4824#define SEGMENT_SIZE 128
4825
4826static int get_chip_type(struct pci_dev *pdev, u32 pl_rev)
4827{
4828 u16 device_id;
4829
4830
4831 pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id);
4832
4833 switch (device_id >> 12) {
4834 case CHELSIO_T4:
4835 return CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
4836 case CHELSIO_T5:
4837 return CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
4838 case CHELSIO_T6:
4839 return CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
4840 default:
4841 dev_err(&pdev->dev, "Device %d is not supported\n",
4842 device_id);
4843 }
4844 return -EINVAL;
4845}
4846
4847#ifdef CONFIG_PCI_IOV
4848static int cxgb4_iov_configure(struct pci_dev *pdev, int num_vfs)
4849{
4850 int err = 0;
4851 int current_vfs = pci_num_vf(pdev);
4852 u32 pcie_fw;
4853 void __iomem *regs;
4854
4855 regs = pci_ioremap_bar(pdev, 0);
4856 if (!regs) {
4857 dev_err(&pdev->dev, "cannot map device registers\n");
4858 return -ENOMEM;
4859 }
4860
4861 pcie_fw = readl(regs + PCIE_FW_A);
4862 iounmap(regs);
4863
4864 if (!(pcie_fw & PCIE_FW_INIT_F) ||
4865 !(pcie_fw & PCIE_FW_MASTER_VLD_F) ||
4866 PCIE_FW_MASTER_G(pcie_fw) != 4) {
4867 dev_warn(&pdev->dev,
4868 "cxgb4 driver needs to be MASTER to support SRIOV\n");
4869 return -EOPNOTSUPP;
4870 }
4871
4872
4873
4874
4875 if (current_vfs && pci_vfs_assigned(pdev)) {
4876 dev_err(&pdev->dev,
4877 "Cannot modify SR-IOV while VFs are assigned\n");
4878 num_vfs = current_vfs;
4879 return num_vfs;
4880 }
4881
4882
4883
4884
4885
4886
4887 if (!num_vfs) {
4888 pci_disable_sriov(pdev);
4889 return num_vfs;
4890 }
4891
4892 if (num_vfs != current_vfs) {
4893 err = pci_enable_sriov(pdev, num_vfs);
4894 if (err)
4895 return err;
4896 }
4897 return num_vfs;
4898}
4899#endif
4900
4901static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
4902{
4903 int func, i, err, s_qpp, qpp, num_seg;
4904 struct port_info *pi;
4905 bool highdma = false;
4906 struct adapter *adapter = NULL;
4907 void __iomem *regs;
4908 u32 whoami, pl_rev;
4909 enum chip_type chip;
4910
4911 printk_once(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION);
4912
4913 err = pci_request_regions(pdev, KBUILD_MODNAME);
4914 if (err) {
4915
4916 dev_info(&pdev->dev, "cannot obtain PCI resources\n");
4917 return err;
4918 }
4919
4920 err = pci_enable_device(pdev);
4921 if (err) {
4922 dev_err(&pdev->dev, "cannot enable PCI device\n");
4923 goto out_release_regions;
4924 }
4925
4926 regs = pci_ioremap_bar(pdev, 0);
4927 if (!regs) {
4928 dev_err(&pdev->dev, "cannot map device registers\n");
4929 err = -ENOMEM;
4930 goto out_disable_device;
4931 }
4932
4933 err = t4_wait_dev_ready(regs);
4934 if (err < 0)
4935 goto out_unmap_bar0;
4936
4937
4938 whoami = readl(regs + PL_WHOAMI_A);
4939 pl_rev = REV_G(readl(regs + PL_REV_A));
4940 chip = get_chip_type(pdev, pl_rev);
4941 func = CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5 ?
4942 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
4943 if (func != ent->driver_data) {
4944 iounmap(regs);
4945 pci_disable_device(pdev);
4946 pci_save_state(pdev);
4947 goto sriov;
4948 }
4949
4950 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
4951 highdma = true;
4952 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4953 if (err) {
4954 dev_err(&pdev->dev, "unable to obtain 64-bit DMA for "
4955 "coherent allocations\n");
4956 goto out_unmap_bar0;
4957 }
4958 } else {
4959 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4960 if (err) {
4961 dev_err(&pdev->dev, "no usable DMA configuration\n");
4962 goto out_unmap_bar0;
4963 }
4964 }
4965
4966 pci_enable_pcie_error_reporting(pdev);
4967 enable_pcie_relaxed_ordering(pdev);
4968 pci_set_master(pdev);
4969 pci_save_state(pdev);
4970
4971 adapter = kzalloc(sizeof(*adapter), GFP_KERNEL);
4972 if (!adapter) {
4973 err = -ENOMEM;
4974 goto out_unmap_bar0;
4975 }
4976
4977 adapter->workq = create_singlethread_workqueue("cxgb4");
4978 if (!adapter->workq) {
4979 err = -ENOMEM;
4980 goto out_free_adapter;
4981 }
4982
4983 adapter->mbox_log = kzalloc(sizeof(*adapter->mbox_log) +
4984 (sizeof(struct mbox_cmd) *
4985 T4_OS_LOG_MBOX_CMDS),
4986 GFP_KERNEL);
4987 if (!adapter->mbox_log) {
4988 err = -ENOMEM;
4989 goto out_free_adapter;
4990 }
4991 adapter->mbox_log->size = T4_OS_LOG_MBOX_CMDS;
4992
4993
4994 adapter->flags |= DEV_ENABLED;
4995
4996 adapter->regs = regs;
4997 adapter->pdev = pdev;
4998 adapter->pdev_dev = &pdev->dev;
4999 adapter->name = pci_name(pdev);
5000 adapter->mbox = func;
5001 adapter->pf = func;
5002 adapter->msg_enable = dflt_msg_enable;
5003 memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map));
5004
5005 spin_lock_init(&adapter->stats_lock);
5006 spin_lock_init(&adapter->tid_release_lock);
5007 spin_lock_init(&adapter->win0_lock);
5008
5009 INIT_WORK(&adapter->tid_release_task, process_tid_release_list);
5010 INIT_WORK(&adapter->db_full_task, process_db_full);
5011 INIT_WORK(&adapter->db_drop_task, process_db_drop);
5012
5013 err = t4_prep_adapter(adapter);
5014 if (err)
5015 goto out_free_adapter;
5016
5017
5018 if (!is_t4(adapter->params.chip)) {
5019 s_qpp = (QUEUESPERPAGEPF0_S +
5020 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) *
5021 adapter->pf);
5022 qpp = 1 << QUEUESPERPAGEPF0_G(t4_read_reg(adapter,
5023 SGE_EGRESS_QUEUES_PER_PAGE_PF_A) >> s_qpp);
5024 num_seg = PAGE_SIZE / SEGMENT_SIZE;
5025
5026
5027
5028
5029
5030
5031 if (qpp > num_seg) {
5032 dev_err(&pdev->dev,
5033 "Incorrect number of egress queues per page\n");
5034 err = -EINVAL;
5035 goto out_free_adapter;
5036 }
5037 adapter->bar2 = ioremap_wc(pci_resource_start(pdev, 2),
5038 pci_resource_len(pdev, 2));
5039 if (!adapter->bar2) {
5040 dev_err(&pdev->dev, "cannot map device bar2 region\n");
5041 err = -ENOMEM;
5042 goto out_free_adapter;
5043 }
5044 }
5045
5046 setup_memwin(adapter);
5047 err = adap_init0(adapter);
5048#ifdef CONFIG_DEBUG_FS
5049 bitmap_zero(adapter->sge.blocked_fl, adapter->sge.egr_sz);
5050#endif
5051 setup_memwin_rdma(adapter);
5052 if (err)
5053 goto out_unmap_bar;
5054
5055
5056 if (!is_t4(adapter->params.chip))
5057 t4_write_reg(adapter, SGE_STAT_CFG_A, STATSOURCE_T5_V(7) |
5058 (is_t5(adapter->params.chip) ? STATMODE_V(0) :
5059 T6_STATMODE_V(0)));
5060
5061 for_each_port(adapter, i) {
5062 struct net_device *netdev;
5063
5064 netdev = alloc_etherdev_mq(sizeof(struct port_info),
5065 MAX_ETH_QSETS);
5066 if (!netdev) {
5067 err = -ENOMEM;
5068 goto out_free_dev;
5069 }
5070
5071 SET_NETDEV_DEV(netdev, &pdev->dev);
5072
5073 adapter->port[i] = netdev;
5074 pi = netdev_priv(netdev);
5075 pi->adapter = adapter;
5076 pi->xact_addr_filt = -1;
5077 pi->port_id = i;
5078 netdev->irq = pdev->irq;
5079
5080 netdev->hw_features = NETIF_F_SG | TSO_FLAGS |
5081 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
5082 NETIF_F_RXCSUM | NETIF_F_RXHASH |
5083 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
5084 if (highdma)
5085 netdev->hw_features |= NETIF_F_HIGHDMA;
5086 netdev->features |= netdev->hw_features;
5087 netdev->vlan_features = netdev->features & VLAN_FEAT;
5088
5089 netdev->priv_flags |= IFF_UNICAST_FLT;
5090
5091 netdev->netdev_ops = &cxgb4_netdev_ops;
5092#ifdef CONFIG_CHELSIO_T4_DCB
5093 netdev->dcbnl_ops = &cxgb4_dcb_ops;
5094 cxgb4_dcb_state_init(netdev);
5095#endif
5096 cxgb4_set_ethtool_ops(netdev);
5097 }
5098
5099 pci_set_drvdata(pdev, adapter);
5100
5101 if (adapter->flags & FW_OK) {
5102 err = t4_port_init(adapter, func, func, 0);
5103 if (err)
5104 goto out_free_dev;
5105 } else if (adapter->params.nports == 1) {
5106
5107
5108
5109
5110
5111 u8 hw_addr[ETH_ALEN];
5112 u8 *na = adapter->params.vpd.na;
5113
5114 err = t4_get_raw_vpd_params(adapter, &adapter->params.vpd);
5115 if (!err) {
5116 for (i = 0; i < ETH_ALEN; i++)
5117 hw_addr[i] = (hex2val(na[2 * i + 0]) * 16 +
5118 hex2val(na[2 * i + 1]));
5119 t4_set_hw_addr(adapter, 0, hw_addr);
5120 }
5121 }
5122
5123
5124
5125
5126 cfg_queues(adapter);
5127
5128 adapter->l2t = t4_init_l2t(adapter->l2t_start, adapter->l2t_end);
5129 if (!adapter->l2t) {
5130
5131 dev_warn(&pdev->dev, "could not allocate L2T, continuing\n");
5132 adapter->params.offload = 0;
5133 }
5134
5135#if IS_ENABLED(CONFIG_IPV6)
5136 if ((CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) &&
5137 (!(t4_read_reg(adapter, LE_DB_CONFIG_A) & ASLIPCOMPEN_F))) {
5138
5139
5140
5141 dev_warn(&pdev->dev,
5142 "CLIP not enabled in hardware, continuing\n");
5143 adapter->params.offload = 0;
5144 } else {
5145 adapter->clipt = t4_init_clip_tbl(adapter->clipt_start,
5146 adapter->clipt_end);
5147 if (!adapter->clipt) {
5148
5149
5150
5151 dev_warn(&pdev->dev,
5152 "could not allocate Clip table, continuing\n");
5153 adapter->params.offload = 0;
5154 }
5155 }
5156#endif
5157 if (is_offload(adapter) && tid_init(&adapter->tids) < 0) {
5158 dev_warn(&pdev->dev, "could not allocate TID table, "
5159 "continuing\n");
5160 adapter->params.offload = 0;
5161 }
5162
5163 if (is_offload(adapter)) {
5164 if (t4_read_reg(adapter, LE_DB_CONFIG_A) & HASHEN_F) {
5165 u32 hash_base, hash_reg;
5166
5167 if (chip <= CHELSIO_T5) {
5168 hash_reg = LE_DB_TID_HASHBASE_A;
5169 hash_base = t4_read_reg(adapter, hash_reg);
5170 adapter->tids.hash_base = hash_base / 4;
5171 } else {
5172 hash_reg = T6_LE_DB_HASH_TID_BASE_A;
5173 hash_base = t4_read_reg(adapter, hash_reg);
5174 adapter->tids.hash_base = hash_base;
5175 }
5176 }
5177 }
5178
5179
5180 if (msi > 1 && enable_msix(adapter) == 0)
5181 adapter->flags |= USING_MSIX;
5182 else if (msi > 0 && pci_enable_msi(pdev) == 0)
5183 adapter->flags |= USING_MSI;
5184
5185
5186 cxgb4_check_pcie_caps(adapter);
5187
5188 err = init_rss(adapter);
5189 if (err)
5190 goto out_free_dev;
5191
5192
5193
5194
5195
5196
5197
5198 for_each_port(adapter, i) {
5199 pi = adap2pinfo(adapter, i);
5200 netif_set_real_num_tx_queues(adapter->port[i], pi->nqsets);
5201 netif_set_real_num_rx_queues(adapter->port[i], pi->nqsets);
5202
5203 err = register_netdev(adapter->port[i]);
5204 if (err)
5205 break;
5206 adapter->chan_map[pi->tx_chan] = i;
5207 print_port_info(adapter->port[i]);
5208 }
5209 if (i == 0) {
5210 dev_err(&pdev->dev, "could not register any net devices\n");
5211 goto out_free_dev;
5212 }
5213 if (err) {
5214 dev_warn(&pdev->dev, "only %d net devices registered\n", i);
5215 err = 0;
5216 }
5217
5218 if (cxgb4_debugfs_root) {
5219 adapter->debugfs_root = debugfs_create_dir(pci_name(pdev),
5220 cxgb4_debugfs_root);
5221 setup_debugfs(adapter);
5222 }
5223
5224
5225 pdev->needs_freset = 1;
5226
5227 if (is_offload(adapter))
5228 attach_ulds(adapter);
5229
5230 print_adapter_info(adapter);
5231
5232sriov:
5233#ifdef CONFIG_PCI_IOV
5234 if (func < ARRAY_SIZE(num_vf) && num_vf[func] > 0) {
5235 dev_warn(&pdev->dev,
5236 "Enabling SR-IOV VFs using the num_vf module "
5237 "parameter is deprecated - please use the pci sysfs "
5238 "interface instead.\n");
5239 if (pci_enable_sriov(pdev, num_vf[func]) == 0)
5240 dev_info(&pdev->dev,
5241 "instantiated %u virtual functions\n",
5242 num_vf[func]);
5243 }
5244#endif
5245 return 0;
5246
5247 out_free_dev:
5248 free_some_resources(adapter);
5249 out_unmap_bar:
5250 if (!is_t4(adapter->params.chip))
5251 iounmap(adapter->bar2);
5252 out_free_adapter:
5253 if (adapter->workq)
5254 destroy_workqueue(adapter->workq);
5255
5256 kfree(adapter->mbox_log);
5257 kfree(adapter);
5258 out_unmap_bar0:
5259 iounmap(regs);
5260 out_disable_device:
5261 pci_disable_pcie_error_reporting(pdev);
5262 pci_disable_device(pdev);
5263 out_release_regions:
5264 pci_release_regions(pdev);
5265 return err;
5266}
5267
5268static void remove_one(struct pci_dev *pdev)
5269{
5270 struct adapter *adapter = pci_get_drvdata(pdev);
5271
5272#ifdef CONFIG_PCI_IOV
5273 pci_disable_sriov(pdev);
5274
5275#endif
5276
5277 if (adapter) {
5278 int i;
5279
5280
5281
5282
5283 destroy_workqueue(adapter->workq);
5284
5285 if (is_offload(adapter))
5286 detach_ulds(adapter);
5287
5288 disable_interrupts(adapter);
5289
5290 for_each_port(adapter, i)
5291 if (adapter->port[i]->reg_state == NETREG_REGISTERED)
5292 unregister_netdev(adapter->port[i]);
5293
5294 debugfs_remove_recursive(adapter->debugfs_root);
5295
5296
5297
5298
5299 if (adapter->tids.ftid_tab) {
5300 struct filter_entry *f = &adapter->tids.ftid_tab[0];
5301 for (i = 0; i < (adapter->tids.nftids +
5302 adapter->tids.nsftids); i++, f++)
5303 if (f->valid)
5304 clear_filter(adapter, f);
5305 }
5306
5307 if (adapter->flags & FULL_INIT_DONE)
5308 cxgb_down(adapter);
5309
5310 free_some_resources(adapter);
5311#if IS_ENABLED(CONFIG_IPV6)
5312 t4_cleanup_clip_tbl(adapter);
5313#endif
5314 iounmap(adapter->regs);
5315 if (!is_t4(adapter->params.chip))
5316 iounmap(adapter->bar2);
5317 pci_disable_pcie_error_reporting(pdev);
5318 if ((adapter->flags & DEV_ENABLED)) {
5319 pci_disable_device(pdev);
5320 adapter->flags &= ~DEV_ENABLED;
5321 }
5322 pci_release_regions(pdev);
5323 kfree(adapter->mbox_log);
5324 synchronize_rcu();
5325 kfree(adapter);
5326 } else
5327 pci_release_regions(pdev);
5328}
5329
5330static struct pci_driver cxgb4_driver = {
5331 .name = KBUILD_MODNAME,
5332 .id_table = cxgb4_pci_tbl,
5333 .probe = init_one,
5334 .remove = remove_one,
5335 .shutdown = remove_one,
5336#ifdef CONFIG_PCI_IOV
5337 .sriov_configure = cxgb4_iov_configure,
5338#endif
5339 .err_handler = &cxgb4_eeh,
5340};
5341
5342static int __init cxgb4_init_module(void)
5343{
5344 int ret;
5345
5346
5347 cxgb4_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL);
5348 if (!cxgb4_debugfs_root)
5349 pr_warn("could not create debugfs entry, continuing\n");
5350
5351 ret = pci_register_driver(&cxgb4_driver);
5352 if (ret < 0)
5353 debugfs_remove(cxgb4_debugfs_root);
5354
5355#if IS_ENABLED(CONFIG_IPV6)
5356 if (!inet6addr_registered) {
5357 register_inet6addr_notifier(&cxgb4_inet6addr_notifier);
5358 inet6addr_registered = true;
5359 }
5360#endif
5361
5362 return ret;
5363}
5364
5365static void __exit cxgb4_cleanup_module(void)
5366{
5367#if IS_ENABLED(CONFIG_IPV6)
5368 if (inet6addr_registered) {
5369 unregister_inet6addr_notifier(&cxgb4_inet6addr_notifier);
5370 inet6addr_registered = false;
5371 }
5372#endif
5373 pci_unregister_driver(&cxgb4_driver);
5374 debugfs_remove(cxgb4_debugfs_root);
5375}
5376
5377module_init(cxgb4_init_module);
5378module_exit(cxgb4_cleanup_module);
5379