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29#include <linux/pci.h>
30#include <linux/delay.h>
31#include <linux/sched.h>
32#include <linux/netdevice.h>
33
34#include "ixgbe.h"
35#include "ixgbe_common.h"
36#include "ixgbe_phy.h"
37
38static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
39static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
40static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
41static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
42static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
43static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
44 u16 count);
45static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
46static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
47static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
48static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
49
50static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
51static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg);
52static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
53 u16 words, u16 *data);
54static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
55 u16 words, u16 *data);
56static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
57 u16 offset);
58static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw);
59
60
61const u32 ixgbe_mvals_8259X[IXGBE_MVALS_IDX_LIMIT] = {
62 IXGBE_MVALS_INIT(8259X)
63};
64
65
66
67
68
69
70
71
72
73
74bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
75{
76 bool supported = false;
77 ixgbe_link_speed speed;
78 bool link_up;
79
80 switch (hw->phy.media_type) {
81 case ixgbe_media_type_fiber:
82 hw->mac.ops.check_link(hw, &speed, &link_up, false);
83
84 if (link_up)
85 supported = speed == IXGBE_LINK_SPEED_1GB_FULL ?
86 true : false;
87 else
88 supported = true;
89 break;
90 case ixgbe_media_type_backplane:
91 supported = true;
92 break;
93 case ixgbe_media_type_copper:
94
95 switch (hw->device_id) {
96 case IXGBE_DEV_ID_82599_T3_LOM:
97 case IXGBE_DEV_ID_X540T:
98 case IXGBE_DEV_ID_X540T1:
99 case IXGBE_DEV_ID_X550T:
100 case IXGBE_DEV_ID_X550T1:
101 case IXGBE_DEV_ID_X550EM_X_10G_T:
102 supported = true;
103 break;
104 default:
105 break;
106 }
107 default:
108 break;
109 }
110
111 return supported;
112}
113
114
115
116
117
118
119
120s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw)
121{
122 s32 ret_val = 0;
123 u32 reg = 0, reg_bp = 0;
124 u16 reg_cu = 0;
125 bool locked = false;
126
127
128
129
130
131 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
132 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
133 return IXGBE_ERR_INVALID_LINK_SETTINGS;
134 }
135
136
137
138
139
140 if (hw->fc.requested_mode == ixgbe_fc_default)
141 hw->fc.requested_mode = ixgbe_fc_full;
142
143
144
145
146
147
148 switch (hw->phy.media_type) {
149 case ixgbe_media_type_backplane:
150
151 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp);
152 if (ret_val)
153 return ret_val;
154
155
156 case ixgbe_media_type_fiber:
157 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
158
159 break;
160 case ixgbe_media_type_copper:
161 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
162 MDIO_MMD_AN, ®_cu);
163 break;
164 default:
165 break;
166 }
167
168
169
170
171
172
173
174
175
176
177
178 switch (hw->fc.requested_mode) {
179 case ixgbe_fc_none:
180
181 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
182 if (hw->phy.media_type == ixgbe_media_type_backplane)
183 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
184 IXGBE_AUTOC_ASM_PAUSE);
185 else if (hw->phy.media_type == ixgbe_media_type_copper)
186 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
187 break;
188 case ixgbe_fc_tx_pause:
189
190
191
192
193 reg |= IXGBE_PCS1GANA_ASM_PAUSE;
194 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE;
195 if (hw->phy.media_type == ixgbe_media_type_backplane) {
196 reg_bp |= IXGBE_AUTOC_ASM_PAUSE;
197 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE;
198 } else if (hw->phy.media_type == ixgbe_media_type_copper) {
199 reg_cu |= IXGBE_TAF_ASM_PAUSE;
200 reg_cu &= ~IXGBE_TAF_SYM_PAUSE;
201 }
202 break;
203 case ixgbe_fc_rx_pause:
204
205
206
207
208
209
210
211
212
213 case ixgbe_fc_full:
214
215 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;
216 if (hw->phy.media_type == ixgbe_media_type_backplane)
217 reg_bp |= IXGBE_AUTOC_SYM_PAUSE |
218 IXGBE_AUTOC_ASM_PAUSE;
219 else if (hw->phy.media_type == ixgbe_media_type_copper)
220 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE;
221 break;
222 default:
223 hw_dbg(hw, "Flow control param set incorrectly\n");
224 return IXGBE_ERR_CONFIG;
225 }
226
227 if (hw->mac.type != ixgbe_mac_X540) {
228
229
230
231
232 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
233 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
234
235
236 if (hw->fc.strict_ieee)
237 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
238
239 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
240 hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg);
241 }
242
243
244
245
246
247
248 if (hw->phy.media_type == ixgbe_media_type_backplane) {
249
250
251
252
253 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked);
254 if (ret_val)
255 return ret_val;
256
257 } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
258 ixgbe_device_supports_autoneg_fc(hw)) {
259 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
260 MDIO_MMD_AN, reg_cu);
261 }
262
263 hw_dbg(hw, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg);
264 return ret_val;
265}
266
267
268
269
270
271
272
273
274
275
276s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
277{
278 s32 ret_val;
279 u32 ctrl_ext;
280 u16 device_caps;
281
282
283 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
284
285
286 hw->phy.ops.identify(hw);
287
288
289 hw->mac.ops.clear_vfta(hw);
290
291
292 hw->mac.ops.clear_hw_cntrs(hw);
293
294
295 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
296 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
297 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
298 IXGBE_WRITE_FLUSH(hw);
299
300
301 ret_val = hw->mac.ops.setup_fc(hw);
302 if (ret_val)
303 return ret_val;
304
305
306 switch (hw->mac.type) {
307 case ixgbe_mac_82599EB:
308 case ixgbe_mac_X550EM_x:
309 case ixgbe_mac_x550em_a:
310 hw->mac.ops.get_device_caps(hw, &device_caps);
311 if (device_caps & IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR)
312 hw->need_crosstalk_fix = false;
313 else
314 hw->need_crosstalk_fix = true;
315 break;
316 default:
317 hw->need_crosstalk_fix = false;
318 break;
319 }
320
321
322 hw->adapter_stopped = false;
323
324 return 0;
325}
326
327
328
329
330
331
332
333
334
335
336
337s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
338{
339 u32 i;
340
341
342 for (i = 0; i < hw->mac.max_tx_queues; i++) {
343 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
344 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
345 }
346 IXGBE_WRITE_FLUSH(hw);
347
348#ifndef CONFIG_SPARC
349
350 for (i = 0; i < hw->mac.max_tx_queues; i++) {
351 u32 regval;
352
353 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
354 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
355 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
356 }
357
358 for (i = 0; i < hw->mac.max_rx_queues; i++) {
359 u32 regval;
360
361 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
362 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
363 IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
364 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
365 }
366#endif
367 return 0;
368}
369
370
371
372
373
374
375
376
377
378
379
380s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
381{
382 s32 status;
383
384
385 status = hw->mac.ops.reset_hw(hw);
386
387 if (status == 0) {
388
389 status = hw->mac.ops.start_hw(hw);
390 }
391
392 return status;
393}
394
395
396
397
398
399
400
401
402s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
403{
404 u16 i = 0;
405
406 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
407 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
408 IXGBE_READ_REG(hw, IXGBE_ERRBC);
409 IXGBE_READ_REG(hw, IXGBE_MSPDC);
410 for (i = 0; i < 8; i++)
411 IXGBE_READ_REG(hw, IXGBE_MPC(i));
412
413 IXGBE_READ_REG(hw, IXGBE_MLFC);
414 IXGBE_READ_REG(hw, IXGBE_MRFC);
415 IXGBE_READ_REG(hw, IXGBE_RLEC);
416 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
417 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
418 if (hw->mac.type >= ixgbe_mac_82599EB) {
419 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
420 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
421 } else {
422 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
423 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
424 }
425
426 for (i = 0; i < 8; i++) {
427 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
428 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
429 if (hw->mac.type >= ixgbe_mac_82599EB) {
430 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
431 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
432 } else {
433 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
434 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
435 }
436 }
437 if (hw->mac.type >= ixgbe_mac_82599EB)
438 for (i = 0; i < 8; i++)
439 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
440 IXGBE_READ_REG(hw, IXGBE_PRC64);
441 IXGBE_READ_REG(hw, IXGBE_PRC127);
442 IXGBE_READ_REG(hw, IXGBE_PRC255);
443 IXGBE_READ_REG(hw, IXGBE_PRC511);
444 IXGBE_READ_REG(hw, IXGBE_PRC1023);
445 IXGBE_READ_REG(hw, IXGBE_PRC1522);
446 IXGBE_READ_REG(hw, IXGBE_GPRC);
447 IXGBE_READ_REG(hw, IXGBE_BPRC);
448 IXGBE_READ_REG(hw, IXGBE_MPRC);
449 IXGBE_READ_REG(hw, IXGBE_GPTC);
450 IXGBE_READ_REG(hw, IXGBE_GORCL);
451 IXGBE_READ_REG(hw, IXGBE_GORCH);
452 IXGBE_READ_REG(hw, IXGBE_GOTCL);
453 IXGBE_READ_REG(hw, IXGBE_GOTCH);
454 if (hw->mac.type == ixgbe_mac_82598EB)
455 for (i = 0; i < 8; i++)
456 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
457 IXGBE_READ_REG(hw, IXGBE_RUC);
458 IXGBE_READ_REG(hw, IXGBE_RFC);
459 IXGBE_READ_REG(hw, IXGBE_ROC);
460 IXGBE_READ_REG(hw, IXGBE_RJC);
461 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
462 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
463 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
464 IXGBE_READ_REG(hw, IXGBE_TORL);
465 IXGBE_READ_REG(hw, IXGBE_TORH);
466 IXGBE_READ_REG(hw, IXGBE_TPR);
467 IXGBE_READ_REG(hw, IXGBE_TPT);
468 IXGBE_READ_REG(hw, IXGBE_PTC64);
469 IXGBE_READ_REG(hw, IXGBE_PTC127);
470 IXGBE_READ_REG(hw, IXGBE_PTC255);
471 IXGBE_READ_REG(hw, IXGBE_PTC511);
472 IXGBE_READ_REG(hw, IXGBE_PTC1023);
473 IXGBE_READ_REG(hw, IXGBE_PTC1522);
474 IXGBE_READ_REG(hw, IXGBE_MPTC);
475 IXGBE_READ_REG(hw, IXGBE_BPTC);
476 for (i = 0; i < 16; i++) {
477 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
478 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
479 if (hw->mac.type >= ixgbe_mac_82599EB) {
480 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
481 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
482 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
483 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
484 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
485 } else {
486 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
487 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
488 }
489 }
490
491 if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) {
492 if (hw->phy.id == 0)
493 hw->phy.ops.identify(hw);
494 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL, MDIO_MMD_PCS, &i);
495 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH, MDIO_MMD_PCS, &i);
496 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL, MDIO_MMD_PCS, &i);
497 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH, MDIO_MMD_PCS, &i);
498 }
499
500 return 0;
501}
502
503
504
505
506
507
508
509
510
511s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
512 u32 pba_num_size)
513{
514 s32 ret_val;
515 u16 data;
516 u16 pba_ptr;
517 u16 offset;
518 u16 length;
519
520 if (pba_num == NULL) {
521 hw_dbg(hw, "PBA string buffer was null\n");
522 return IXGBE_ERR_INVALID_ARGUMENT;
523 }
524
525 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
526 if (ret_val) {
527 hw_dbg(hw, "NVM Read Error\n");
528 return ret_val;
529 }
530
531 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
532 if (ret_val) {
533 hw_dbg(hw, "NVM Read Error\n");
534 return ret_val;
535 }
536
537
538
539
540
541
542 if (data != IXGBE_PBANUM_PTR_GUARD) {
543 hw_dbg(hw, "NVM PBA number is not stored as string\n");
544
545
546 if (pba_num_size < 11) {
547 hw_dbg(hw, "PBA string buffer too small\n");
548 return IXGBE_ERR_NO_SPACE;
549 }
550
551
552 pba_num[0] = (data >> 12) & 0xF;
553 pba_num[1] = (data >> 8) & 0xF;
554 pba_num[2] = (data >> 4) & 0xF;
555 pba_num[3] = data & 0xF;
556 pba_num[4] = (pba_ptr >> 12) & 0xF;
557 pba_num[5] = (pba_ptr >> 8) & 0xF;
558 pba_num[6] = '-';
559 pba_num[7] = 0;
560 pba_num[8] = (pba_ptr >> 4) & 0xF;
561 pba_num[9] = pba_ptr & 0xF;
562
563
564 pba_num[10] = '\0';
565
566
567 for (offset = 0; offset < 10; offset++) {
568 if (pba_num[offset] < 0xA)
569 pba_num[offset] += '0';
570 else if (pba_num[offset] < 0x10)
571 pba_num[offset] += 'A' - 0xA;
572 }
573
574 return 0;
575 }
576
577 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
578 if (ret_val) {
579 hw_dbg(hw, "NVM Read Error\n");
580 return ret_val;
581 }
582
583 if (length == 0xFFFF || length == 0) {
584 hw_dbg(hw, "NVM PBA number section invalid length\n");
585 return IXGBE_ERR_PBA_SECTION;
586 }
587
588
589 if (pba_num_size < (((u32)length * 2) - 1)) {
590 hw_dbg(hw, "PBA string buffer too small\n");
591 return IXGBE_ERR_NO_SPACE;
592 }
593
594
595 pba_ptr++;
596 length--;
597
598 for (offset = 0; offset < length; offset++) {
599 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
600 if (ret_val) {
601 hw_dbg(hw, "NVM Read Error\n");
602 return ret_val;
603 }
604 pba_num[offset * 2] = (u8)(data >> 8);
605 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
606 }
607 pba_num[offset * 2] = '\0';
608
609 return 0;
610}
611
612
613
614
615
616
617
618
619
620
621s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
622{
623 u32 rar_high;
624 u32 rar_low;
625 u16 i;
626
627 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
628 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
629
630 for (i = 0; i < 4; i++)
631 mac_addr[i] = (u8)(rar_low >> (i*8));
632
633 for (i = 0; i < 2; i++)
634 mac_addr[i+4] = (u8)(rar_high >> (i*8));
635
636 return 0;
637}
638
639enum ixgbe_bus_width ixgbe_convert_bus_width(u16 link_status)
640{
641 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
642 case IXGBE_PCI_LINK_WIDTH_1:
643 return ixgbe_bus_width_pcie_x1;
644 case IXGBE_PCI_LINK_WIDTH_2:
645 return ixgbe_bus_width_pcie_x2;
646 case IXGBE_PCI_LINK_WIDTH_4:
647 return ixgbe_bus_width_pcie_x4;
648 case IXGBE_PCI_LINK_WIDTH_8:
649 return ixgbe_bus_width_pcie_x8;
650 default:
651 return ixgbe_bus_width_unknown;
652 }
653}
654
655enum ixgbe_bus_speed ixgbe_convert_bus_speed(u16 link_status)
656{
657 switch (link_status & IXGBE_PCI_LINK_SPEED) {
658 case IXGBE_PCI_LINK_SPEED_2500:
659 return ixgbe_bus_speed_2500;
660 case IXGBE_PCI_LINK_SPEED_5000:
661 return ixgbe_bus_speed_5000;
662 case IXGBE_PCI_LINK_SPEED_8000:
663 return ixgbe_bus_speed_8000;
664 default:
665 return ixgbe_bus_speed_unknown;
666 }
667}
668
669
670
671
672
673
674
675s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
676{
677 u16 link_status;
678
679 hw->bus.type = ixgbe_bus_type_pci_express;
680
681
682 link_status = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_LINK_STATUS);
683
684 hw->bus.width = ixgbe_convert_bus_width(link_status);
685 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
686
687 hw->mac.ops.set_lan_id(hw);
688
689 return 0;
690}
691
692
693
694
695
696
697
698
699void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
700{
701 struct ixgbe_bus_info *bus = &hw->bus;
702 u16 ee_ctrl_4;
703 u32 reg;
704
705 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
706 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
707 bus->lan_id = bus->func;
708
709
710 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS(hw));
711 if (reg & IXGBE_FACTPS_LFS)
712 bus->func ^= 0x1;
713
714
715 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP) {
716 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_4, &ee_ctrl_4);
717 bus->instance_id = (ee_ctrl_4 & IXGBE_EE_CTRL_4_INST_ID) >>
718 IXGBE_EE_CTRL_4_INST_ID_SHIFT;
719 }
720}
721
722
723
724
725
726
727
728
729
730
731s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
732{
733 u32 reg_val;
734 u16 i;
735
736
737
738
739
740 hw->adapter_stopped = true;
741
742
743 hw->mac.ops.disable_rx(hw);
744
745
746 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
747
748
749 IXGBE_READ_REG(hw, IXGBE_EICR);
750
751
752 for (i = 0; i < hw->mac.max_tx_queues; i++)
753 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH);
754
755
756 for (i = 0; i < hw->mac.max_rx_queues; i++) {
757 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
758 reg_val &= ~IXGBE_RXDCTL_ENABLE;
759 reg_val |= IXGBE_RXDCTL_SWFLSH;
760 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
761 }
762
763
764 IXGBE_WRITE_FLUSH(hw);
765 usleep_range(1000, 2000);
766
767
768
769
770
771 return ixgbe_disable_pcie_master(hw);
772}
773
774
775
776
777
778
779s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
780{
781 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
782
783 if (index > 3)
784 return IXGBE_ERR_PARAM;
785
786
787 led_reg &= ~IXGBE_LED_MODE_MASK(index);
788 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
789 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
790 IXGBE_WRITE_FLUSH(hw);
791
792 return 0;
793}
794
795
796
797
798
799
800s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
801{
802 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
803
804 if (index > 3)
805 return IXGBE_ERR_PARAM;
806
807
808 led_reg &= ~IXGBE_LED_MODE_MASK(index);
809 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
810 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
811 IXGBE_WRITE_FLUSH(hw);
812
813 return 0;
814}
815
816
817
818
819
820
821
822
823s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
824{
825 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
826 u32 eec;
827 u16 eeprom_size;
828
829 if (eeprom->type == ixgbe_eeprom_uninitialized) {
830 eeprom->type = ixgbe_eeprom_none;
831
832
833 eeprom->semaphore_delay = 10;
834
835 eeprom->word_page_size = 0;
836
837
838
839
840
841 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
842 if (eec & IXGBE_EEC_PRES) {
843 eeprom->type = ixgbe_eeprom_spi;
844
845
846
847
848
849 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
850 IXGBE_EEC_SIZE_SHIFT);
851 eeprom->word_size = BIT(eeprom_size +
852 IXGBE_EEPROM_WORD_SIZE_SHIFT);
853 }
854
855 if (eec & IXGBE_EEC_ADDR_SIZE)
856 eeprom->address_bits = 16;
857 else
858 eeprom->address_bits = 8;
859 hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: %d\n",
860 eeprom->type, eeprom->word_size, eeprom->address_bits);
861 }
862
863 return 0;
864}
865
866
867
868
869
870
871
872
873
874
875s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
876 u16 words, u16 *data)
877{
878 s32 status;
879 u16 i, count;
880
881 hw->eeprom.ops.init_params(hw);
882
883 if (words == 0)
884 return IXGBE_ERR_INVALID_ARGUMENT;
885
886 if (offset + words > hw->eeprom.word_size)
887 return IXGBE_ERR_EEPROM;
888
889
890
891
892
893 if ((hw->eeprom.word_page_size == 0) &&
894 (words > IXGBE_EEPROM_PAGE_SIZE_MAX))
895 ixgbe_detect_eeprom_page_size_generic(hw, offset);
896
897
898
899
900
901
902 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
903 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
904 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
905 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
906 count, &data[i]);
907
908 if (status != 0)
909 break;
910 }
911
912 return status;
913}
914
915
916
917
918
919
920
921
922
923
924
925static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
926 u16 words, u16 *data)
927{
928 s32 status;
929 u16 word;
930 u16 page_size;
931 u16 i;
932 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
933
934
935 status = ixgbe_acquire_eeprom(hw);
936 if (status)
937 return status;
938
939 if (ixgbe_ready_eeprom(hw) != 0) {
940 ixgbe_release_eeprom(hw);
941 return IXGBE_ERR_EEPROM;
942 }
943
944 for (i = 0; i < words; i++) {
945 ixgbe_standby_eeprom(hw);
946
947
948 ixgbe_shift_out_eeprom_bits(hw,
949 IXGBE_EEPROM_WREN_OPCODE_SPI,
950 IXGBE_EEPROM_OPCODE_BITS);
951
952 ixgbe_standby_eeprom(hw);
953
954
955
956
957 if ((hw->eeprom.address_bits == 8) &&
958 ((offset + i) >= 128))
959 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
960
961
962 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
963 IXGBE_EEPROM_OPCODE_BITS);
964 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
965 hw->eeprom.address_bits);
966
967 page_size = hw->eeprom.word_page_size;
968
969
970 do {
971 word = data[i];
972 word = (word >> 8) | (word << 8);
973 ixgbe_shift_out_eeprom_bits(hw, word, 16);
974
975 if (page_size == 0)
976 break;
977
978
979 if (((offset + i) & (page_size - 1)) ==
980 (page_size - 1))
981 break;
982 } while (++i < words);
983
984 ixgbe_standby_eeprom(hw);
985 usleep_range(10000, 20000);
986 }
987
988 ixgbe_release_eeprom(hw);
989
990 return 0;
991}
992
993
994
995
996
997
998
999
1000
1001
1002s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1003{
1004 hw->eeprom.ops.init_params(hw);
1005
1006 if (offset >= hw->eeprom.word_size)
1007 return IXGBE_ERR_EEPROM;
1008
1009 return ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
1010}
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1022 u16 words, u16 *data)
1023{
1024 s32 status;
1025 u16 i, count;
1026
1027 hw->eeprom.ops.init_params(hw);
1028
1029 if (words == 0)
1030 return IXGBE_ERR_INVALID_ARGUMENT;
1031
1032 if (offset + words > hw->eeprom.word_size)
1033 return IXGBE_ERR_EEPROM;
1034
1035
1036
1037
1038
1039
1040 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1041 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1042 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1043
1044 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
1045 count, &data[i]);
1046
1047 if (status)
1048 return status;
1049 }
1050
1051 return 0;
1052}
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1064 u16 words, u16 *data)
1065{
1066 s32 status;
1067 u16 word_in;
1068 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
1069 u16 i;
1070
1071
1072 status = ixgbe_acquire_eeprom(hw);
1073 if (status)
1074 return status;
1075
1076 if (ixgbe_ready_eeprom(hw) != 0) {
1077 ixgbe_release_eeprom(hw);
1078 return IXGBE_ERR_EEPROM;
1079 }
1080
1081 for (i = 0; i < words; i++) {
1082 ixgbe_standby_eeprom(hw);
1083
1084
1085
1086 if ((hw->eeprom.address_bits == 8) &&
1087 ((offset + i) >= 128))
1088 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1089
1090
1091 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
1092 IXGBE_EEPROM_OPCODE_BITS);
1093 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1094 hw->eeprom.address_bits);
1095
1096
1097 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
1098 data[i] = (word_in >> 8) | (word_in << 8);
1099 }
1100
1101
1102 ixgbe_release_eeprom(hw);
1103
1104 return 0;
1105}
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1116 u16 *data)
1117{
1118 hw->eeprom.ops.init_params(hw);
1119
1120 if (offset >= hw->eeprom.word_size)
1121 return IXGBE_ERR_EEPROM;
1122
1123 return ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1124}
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1136 u16 words, u16 *data)
1137{
1138 u32 eerd;
1139 s32 status;
1140 u32 i;
1141
1142 hw->eeprom.ops.init_params(hw);
1143
1144 if (words == 0)
1145 return IXGBE_ERR_INVALID_ARGUMENT;
1146
1147 if (offset >= hw->eeprom.word_size)
1148 return IXGBE_ERR_EEPROM;
1149
1150 for (i = 0; i < words; i++) {
1151 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1152 IXGBE_EEPROM_RW_REG_START;
1153
1154 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
1155 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
1156
1157 if (status == 0) {
1158 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
1159 IXGBE_EEPROM_RW_REG_DATA);
1160 } else {
1161 hw_dbg(hw, "Eeprom read timed out\n");
1162 return status;
1163 }
1164 }
1165
1166 return 0;
1167}
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
1179 u16 offset)
1180{
1181 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];
1182 s32 status;
1183 u16 i;
1184
1185 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)
1186 data[i] = i;
1187
1188 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
1189 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
1190 IXGBE_EEPROM_PAGE_SIZE_MAX, data);
1191 hw->eeprom.word_page_size = 0;
1192 if (status)
1193 return status;
1194
1195 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1196 if (status)
1197 return status;
1198
1199
1200
1201
1202
1203 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
1204
1205 hw_dbg(hw, "Detected EEPROM page size = %d words.\n",
1206 hw->eeprom.word_page_size);
1207 return 0;
1208}
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
1219{
1220 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);
1221}
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1233 u16 words, u16 *data)
1234{
1235 u32 eewr;
1236 s32 status;
1237 u16 i;
1238
1239 hw->eeprom.ops.init_params(hw);
1240
1241 if (words == 0)
1242 return IXGBE_ERR_INVALID_ARGUMENT;
1243
1244 if (offset >= hw->eeprom.word_size)
1245 return IXGBE_ERR_EEPROM;
1246
1247 for (i = 0; i < words; i++) {
1248 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1249 (data[i] << IXGBE_EEPROM_RW_REG_DATA) |
1250 IXGBE_EEPROM_RW_REG_START;
1251
1252 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1253 if (status) {
1254 hw_dbg(hw, "Eeprom write EEWR timed out\n");
1255 return status;
1256 }
1257
1258 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
1259
1260 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1261 if (status) {
1262 hw_dbg(hw, "Eeprom write EEWR timed out\n");
1263 return status;
1264 }
1265 }
1266
1267 return 0;
1268}
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1279{
1280 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);
1281}
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
1292{
1293 u32 i;
1294 u32 reg;
1295
1296 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
1297 if (ee_reg == IXGBE_NVM_POLL_READ)
1298 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
1299 else
1300 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
1301
1302 if (reg & IXGBE_EEPROM_RW_REG_DONE) {
1303 return 0;
1304 }
1305 udelay(5);
1306 }
1307 return IXGBE_ERR_EEPROM;
1308}
1309
1310
1311
1312
1313
1314
1315
1316
1317static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
1318{
1319 u32 eec;
1320 u32 i;
1321
1322 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0)
1323 return IXGBE_ERR_SWFW_SYNC;
1324
1325 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
1326
1327
1328 eec |= IXGBE_EEC_REQ;
1329 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
1330
1331 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
1332 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
1333 if (eec & IXGBE_EEC_GNT)
1334 break;
1335 udelay(5);
1336 }
1337
1338
1339 if (!(eec & IXGBE_EEC_GNT)) {
1340 eec &= ~IXGBE_EEC_REQ;
1341 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
1342 hw_dbg(hw, "Could not acquire EEPROM grant\n");
1343
1344 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1345 return IXGBE_ERR_EEPROM;
1346 }
1347
1348
1349
1350 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
1351 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
1352 IXGBE_WRITE_FLUSH(hw);
1353 udelay(1);
1354 return 0;
1355}
1356
1357
1358
1359
1360
1361
1362
1363static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
1364{
1365 u32 timeout = 2000;
1366 u32 i;
1367 u32 swsm;
1368
1369
1370 for (i = 0; i < timeout; i++) {
1371
1372
1373
1374
1375 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
1376 if (!(swsm & IXGBE_SWSM_SMBI))
1377 break;
1378 usleep_range(50, 100);
1379 }
1380
1381 if (i == timeout) {
1382 hw_dbg(hw, "Driver can't access the Eeprom - SMBI Semaphore not granted.\n");
1383
1384
1385
1386
1387
1388 ixgbe_release_eeprom_semaphore(hw);
1389
1390 usleep_range(50, 100);
1391
1392
1393
1394
1395 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
1396 if (swsm & IXGBE_SWSM_SMBI) {
1397 hw_dbg(hw, "Software semaphore SMBI between device drivers not granted.\n");
1398 return IXGBE_ERR_EEPROM;
1399 }
1400 }
1401
1402
1403 for (i = 0; i < timeout; i++) {
1404 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
1405
1406
1407 swsm |= IXGBE_SWSM_SWESMBI;
1408 IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm);
1409
1410
1411
1412
1413 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
1414 if (swsm & IXGBE_SWSM_SWESMBI)
1415 break;
1416
1417 usleep_range(50, 100);
1418 }
1419
1420
1421
1422
1423 if (i >= timeout) {
1424 hw_dbg(hw, "SWESMBI Software EEPROM semaphore not granted.\n");
1425 ixgbe_release_eeprom_semaphore(hw);
1426 return IXGBE_ERR_EEPROM;
1427 }
1428
1429 return 0;
1430}
1431
1432
1433
1434
1435
1436
1437
1438static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
1439{
1440 u32 swsm;
1441
1442 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
1443
1444
1445 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
1446 IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm);
1447 IXGBE_WRITE_FLUSH(hw);
1448}
1449
1450
1451
1452
1453
1454static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
1455{
1456 u16 i;
1457 u8 spi_stat_reg;
1458
1459
1460
1461
1462
1463
1464
1465 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
1466 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
1467 IXGBE_EEPROM_OPCODE_BITS);
1468 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
1469 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
1470 break;
1471
1472 udelay(5);
1473 ixgbe_standby_eeprom(hw);
1474 }
1475
1476
1477
1478
1479
1480 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
1481 hw_dbg(hw, "SPI EEPROM Status error\n");
1482 return IXGBE_ERR_EEPROM;
1483 }
1484
1485 return 0;
1486}
1487
1488
1489
1490
1491
1492static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
1493{
1494 u32 eec;
1495
1496 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
1497
1498
1499 eec |= IXGBE_EEC_CS;
1500 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
1501 IXGBE_WRITE_FLUSH(hw);
1502 udelay(1);
1503 eec &= ~IXGBE_EEC_CS;
1504 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
1505 IXGBE_WRITE_FLUSH(hw);
1506 udelay(1);
1507}
1508
1509
1510
1511
1512
1513
1514
1515static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
1516 u16 count)
1517{
1518 u32 eec;
1519 u32 mask;
1520 u32 i;
1521
1522 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
1523
1524
1525
1526
1527
1528 mask = BIT(count - 1);
1529
1530 for (i = 0; i < count; i++) {
1531
1532
1533
1534
1535
1536
1537
1538 if (data & mask)
1539 eec |= IXGBE_EEC_DI;
1540 else
1541 eec &= ~IXGBE_EEC_DI;
1542
1543 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
1544 IXGBE_WRITE_FLUSH(hw);
1545
1546 udelay(1);
1547
1548 ixgbe_raise_eeprom_clk(hw, &eec);
1549 ixgbe_lower_eeprom_clk(hw, &eec);
1550
1551
1552
1553
1554
1555 mask = mask >> 1;
1556 }
1557
1558
1559 eec &= ~IXGBE_EEC_DI;
1560 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
1561 IXGBE_WRITE_FLUSH(hw);
1562}
1563
1564
1565
1566
1567
1568static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
1569{
1570 u32 eec;
1571 u32 i;
1572 u16 data = 0;
1573
1574
1575
1576
1577
1578
1579
1580
1581 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
1582
1583 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
1584
1585 for (i = 0; i < count; i++) {
1586 data = data << 1;
1587 ixgbe_raise_eeprom_clk(hw, &eec);
1588
1589 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
1590
1591 eec &= ~(IXGBE_EEC_DI);
1592 if (eec & IXGBE_EEC_DO)
1593 data |= 1;
1594
1595 ixgbe_lower_eeprom_clk(hw, &eec);
1596 }
1597
1598 return data;
1599}
1600
1601
1602
1603
1604
1605
1606static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1607{
1608
1609
1610
1611
1612 *eec = *eec | IXGBE_EEC_SK;
1613 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), *eec);
1614 IXGBE_WRITE_FLUSH(hw);
1615 udelay(1);
1616}
1617
1618
1619
1620
1621
1622
1623static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1624{
1625
1626
1627
1628
1629 *eec = *eec & ~IXGBE_EEC_SK;
1630 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), *eec);
1631 IXGBE_WRITE_FLUSH(hw);
1632 udelay(1);
1633}
1634
1635
1636
1637
1638
1639static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
1640{
1641 u32 eec;
1642
1643 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
1644
1645 eec |= IXGBE_EEC_CS;
1646 eec &= ~IXGBE_EEC_SK;
1647
1648 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
1649 IXGBE_WRITE_FLUSH(hw);
1650
1651 udelay(1);
1652
1653
1654 eec &= ~IXGBE_EEC_REQ;
1655 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), eec);
1656
1657 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1658
1659
1660
1661
1662
1663 usleep_range(hw->eeprom.semaphore_delay * 1000,
1664 hw->eeprom.semaphore_delay * 2000);
1665}
1666
1667
1668
1669
1670
1671s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
1672{
1673 u16 i;
1674 u16 j;
1675 u16 checksum = 0;
1676 u16 length = 0;
1677 u16 pointer = 0;
1678 u16 word = 0;
1679
1680
1681 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
1682 if (hw->eeprom.ops.read(hw, i, &word)) {
1683 hw_dbg(hw, "EEPROM read failed\n");
1684 break;
1685 }
1686 checksum += word;
1687 }
1688
1689
1690 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
1691 if (hw->eeprom.ops.read(hw, i, &pointer)) {
1692 hw_dbg(hw, "EEPROM read failed\n");
1693 return IXGBE_ERR_EEPROM;
1694 }
1695
1696
1697 if (pointer == 0xFFFF || pointer == 0)
1698 continue;
1699
1700 if (hw->eeprom.ops.read(hw, pointer, &length)) {
1701 hw_dbg(hw, "EEPROM read failed\n");
1702 return IXGBE_ERR_EEPROM;
1703 }
1704
1705 if (length == 0xFFFF || length == 0)
1706 continue;
1707
1708 for (j = pointer + 1; j <= pointer + length; j++) {
1709 if (hw->eeprom.ops.read(hw, j, &word)) {
1710 hw_dbg(hw, "EEPROM read failed\n");
1711 return IXGBE_ERR_EEPROM;
1712 }
1713 checksum += word;
1714 }
1715 }
1716
1717 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1718
1719 return (s32)checksum;
1720}
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
1731 u16 *checksum_val)
1732{
1733 s32 status;
1734 u16 checksum;
1735 u16 read_checksum = 0;
1736
1737
1738
1739
1740
1741
1742 status = hw->eeprom.ops.read(hw, 0, &checksum);
1743 if (status) {
1744 hw_dbg(hw, "EEPROM read failed\n");
1745 return status;
1746 }
1747
1748 status = hw->eeprom.ops.calc_checksum(hw);
1749 if (status < 0)
1750 return status;
1751
1752 checksum = (u16)(status & 0xffff);
1753
1754 status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
1755 if (status) {
1756 hw_dbg(hw, "EEPROM read failed\n");
1757 return status;
1758 }
1759
1760
1761
1762
1763 if (read_checksum != checksum)
1764 status = IXGBE_ERR_EEPROM_CHECKSUM;
1765
1766
1767 if (checksum_val)
1768 *checksum_val = checksum;
1769
1770 return status;
1771}
1772
1773
1774
1775
1776
1777s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
1778{
1779 s32 status;
1780 u16 checksum;
1781
1782
1783
1784
1785
1786
1787 status = hw->eeprom.ops.read(hw, 0, &checksum);
1788 if (status) {
1789 hw_dbg(hw, "EEPROM read failed\n");
1790 return status;
1791 }
1792
1793 status = hw->eeprom.ops.calc_checksum(hw);
1794 if (status < 0)
1795 return status;
1796
1797 checksum = (u16)(status & 0xffff);
1798
1799 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum);
1800
1801 return status;
1802}
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
1815 u32 enable_addr)
1816{
1817 u32 rar_low, rar_high;
1818 u32 rar_entries = hw->mac.num_rar_entries;
1819
1820
1821 if (index >= rar_entries) {
1822 hw_dbg(hw, "RAR index %d is out of range.\n", index);
1823 return IXGBE_ERR_INVALID_ARGUMENT;
1824 }
1825
1826
1827 hw->mac.ops.set_vmdq(hw, index, vmdq);
1828
1829
1830
1831
1832
1833 rar_low = ((u32)addr[0] |
1834 ((u32)addr[1] << 8) |
1835 ((u32)addr[2] << 16) |
1836 ((u32)addr[3] << 24));
1837
1838
1839
1840
1841
1842 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1843 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1844 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
1845
1846 if (enable_addr != 0)
1847 rar_high |= IXGBE_RAH_AV;
1848
1849 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
1850 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1851
1852 return 0;
1853}
1854
1855
1856
1857
1858
1859
1860
1861
1862s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
1863{
1864 u32 rar_high;
1865 u32 rar_entries = hw->mac.num_rar_entries;
1866
1867
1868 if (index >= rar_entries) {
1869 hw_dbg(hw, "RAR index %d is out of range.\n", index);
1870 return IXGBE_ERR_INVALID_ARGUMENT;
1871 }
1872
1873
1874
1875
1876
1877
1878 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1879 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1880
1881 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
1882 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1883
1884
1885 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
1886
1887 return 0;
1888}
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
1899{
1900 u32 i;
1901 u32 rar_entries = hw->mac.num_rar_entries;
1902
1903
1904
1905
1906
1907
1908 if (!is_valid_ether_addr(hw->mac.addr)) {
1909
1910 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
1911
1912 hw_dbg(hw, " Keeping Current RAR0 Addr =%pM\n", hw->mac.addr);
1913 } else {
1914
1915 hw_dbg(hw, "Overriding MAC Address in RAR[0]\n");
1916 hw_dbg(hw, " New MAC Addr =%pM\n", hw->mac.addr);
1917
1918 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1919 }
1920
1921
1922 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
1923
1924 hw->addr_ctrl.overflow_promisc = 0;
1925
1926 hw->addr_ctrl.rar_used_count = 1;
1927
1928
1929 hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1);
1930 for (i = 1; i < rar_entries; i++) {
1931 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
1932 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
1933 }
1934
1935
1936 hw->addr_ctrl.mta_in_use = 0;
1937 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
1938
1939 hw_dbg(hw, " Clearing MTA\n");
1940 for (i = 0; i < hw->mac.mcft_size; i++)
1941 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
1942
1943 if (hw->mac.ops.init_uta_tables)
1944 hw->mac.ops.init_uta_tables(hw);
1945
1946 return 0;
1947}
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
1962{
1963 u32 vector = 0;
1964
1965 switch (hw->mac.mc_filter_type) {
1966 case 0:
1967 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
1968 break;
1969 case 1:
1970 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
1971 break;
1972 case 2:
1973 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
1974 break;
1975 case 3:
1976 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
1977 break;
1978 default:
1979 hw_dbg(hw, "MC filter type param set incorrectly\n");
1980 break;
1981 }
1982
1983
1984 vector &= 0xFFF;
1985 return vector;
1986}
1987
1988
1989
1990
1991
1992
1993
1994
1995static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
1996{
1997 u32 vector;
1998 u32 vector_bit;
1999 u32 vector_reg;
2000
2001 hw->addr_ctrl.mta_in_use++;
2002
2003 vector = ixgbe_mta_vector(hw, mc_addr);
2004 hw_dbg(hw, " bit-vector = 0x%03X\n", vector);
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015 vector_reg = (vector >> 5) & 0x7F;
2016 vector_bit = vector & 0x1F;
2017 hw->mac.mta_shadow[vector_reg] |= BIT(vector_bit);
2018}
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw,
2031 struct net_device *netdev)
2032{
2033 struct netdev_hw_addr *ha;
2034 u32 i;
2035
2036
2037
2038
2039
2040 hw->addr_ctrl.num_mc_addrs = netdev_mc_count(netdev);
2041 hw->addr_ctrl.mta_in_use = 0;
2042
2043
2044 hw_dbg(hw, " Clearing MTA\n");
2045 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
2046
2047
2048 netdev_for_each_mc_addr(ha, netdev) {
2049 hw_dbg(hw, " Adding the multicast addresses:\n");
2050 ixgbe_set_mta(hw, ha->addr);
2051 }
2052
2053
2054 for (i = 0; i < hw->mac.mcft_size; i++)
2055 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
2056 hw->mac.mta_shadow[i]);
2057
2058 if (hw->addr_ctrl.mta_in_use > 0)
2059 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
2060 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
2061
2062 hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n");
2063 return 0;
2064}
2065
2066
2067
2068
2069
2070
2071
2072s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
2073{
2074 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2075
2076 if (a->mta_in_use > 0)
2077 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
2078 hw->mac.mc_filter_type);
2079
2080 return 0;
2081}
2082
2083
2084
2085
2086
2087
2088
2089s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
2090{
2091 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2092
2093 if (a->mta_in_use > 0)
2094 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2095
2096 return 0;
2097}
2098
2099
2100
2101
2102
2103
2104
2105s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)
2106{
2107 u32 mflcn_reg, fccfg_reg;
2108 u32 reg;
2109 u32 fcrtl, fcrth;
2110 int i;
2111
2112
2113 if (!hw->fc.pause_time)
2114 return IXGBE_ERR_INVALID_LINK_SETTINGS;
2115
2116
2117 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
2118 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2119 hw->fc.high_water[i]) {
2120 if (!hw->fc.low_water[i] ||
2121 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
2122 hw_dbg(hw, "Invalid water mark configuration\n");
2123 return IXGBE_ERR_INVALID_LINK_SETTINGS;
2124 }
2125 }
2126 }
2127
2128
2129 ixgbe_fc_autoneg(hw);
2130
2131
2132 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2133 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
2134
2135 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2136 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148 switch (hw->fc.current_mode) {
2149 case ixgbe_fc_none:
2150
2151
2152
2153
2154 break;
2155 case ixgbe_fc_rx_pause:
2156
2157
2158
2159
2160
2161
2162
2163
2164 mflcn_reg |= IXGBE_MFLCN_RFCE;
2165 break;
2166 case ixgbe_fc_tx_pause:
2167
2168
2169
2170
2171 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2172 break;
2173 case ixgbe_fc_full:
2174
2175 mflcn_reg |= IXGBE_MFLCN_RFCE;
2176 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2177 break;
2178 default:
2179 hw_dbg(hw, "Flow control param set incorrectly\n");
2180 return IXGBE_ERR_CONFIG;
2181 }
2182
2183
2184 mflcn_reg |= IXGBE_MFLCN_DPF;
2185 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2186 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2187
2188
2189 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
2190 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2191 hw->fc.high_water[i]) {
2192 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
2193 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
2194 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
2195 } else {
2196 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
2197
2198
2199
2200
2201
2202
2203
2204 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;
2205 }
2206
2207 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
2208 }
2209
2210
2211 reg = hw->fc.pause_time * 0x00010001;
2212 for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++)
2213 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2214
2215 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2216
2217 return 0;
2218}
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
2234 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
2235{
2236 if ((!(adv_reg)) || (!(lp_reg)))
2237 return IXGBE_ERR_FC_NOT_NEGOTIATED;
2238
2239 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
2240
2241
2242
2243
2244
2245
2246
2247 if (hw->fc.requested_mode == ixgbe_fc_full) {
2248 hw->fc.current_mode = ixgbe_fc_full;
2249 hw_dbg(hw, "Flow Control = FULL.\n");
2250 } else {
2251 hw->fc.current_mode = ixgbe_fc_rx_pause;
2252 hw_dbg(hw, "Flow Control=RX PAUSE frames only\n");
2253 }
2254 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2255 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2256 hw->fc.current_mode = ixgbe_fc_tx_pause;
2257 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n");
2258 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2259 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2260 hw->fc.current_mode = ixgbe_fc_rx_pause;
2261 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n");
2262 } else {
2263 hw->fc.current_mode = ixgbe_fc_none;
2264 hw_dbg(hw, "Flow Control = NONE.\n");
2265 }
2266 return 0;
2267}
2268
2269
2270
2271
2272
2273
2274
2275static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
2276{
2277 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
2278 s32 ret_val;
2279
2280
2281
2282
2283
2284
2285
2286 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
2287 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
2288 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1))
2289 return IXGBE_ERR_FC_NOT_NEGOTIATED;
2290
2291 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
2292 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
2293
2294 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
2295 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
2296 IXGBE_PCS1GANA_ASM_PAUSE,
2297 IXGBE_PCS1GANA_SYM_PAUSE,
2298 IXGBE_PCS1GANA_ASM_PAUSE);
2299
2300 return ret_val;
2301}
2302
2303
2304
2305
2306
2307
2308
2309static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
2310{
2311 u32 links2, anlp1_reg, autoc_reg, links;
2312 s32 ret_val;
2313
2314
2315
2316
2317
2318
2319 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
2320 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0)
2321 return IXGBE_ERR_FC_NOT_NEGOTIATED;
2322
2323 if (hw->mac.type == ixgbe_mac_82599EB) {
2324 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
2325 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0)
2326 return IXGBE_ERR_FC_NOT_NEGOTIATED;
2327 }
2328
2329
2330
2331
2332 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2333 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2334
2335 ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
2336 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
2337 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
2338
2339 return ret_val;
2340}
2341
2342
2343
2344
2345
2346
2347
2348static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
2349{
2350 u16 technology_ability_reg = 0;
2351 u16 lp_technology_ability_reg = 0;
2352
2353 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
2354 MDIO_MMD_AN,
2355 &technology_ability_reg);
2356 hw->phy.ops.read_reg(hw, MDIO_AN_LPA,
2357 MDIO_MMD_AN,
2358 &lp_technology_ability_reg);
2359
2360 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
2361 (u32)lp_technology_ability_reg,
2362 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
2363 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
2364}
2365
2366
2367
2368
2369
2370
2371
2372
2373void ixgbe_fc_autoneg(struct ixgbe_hw *hw)
2374{
2375 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2376 ixgbe_link_speed speed;
2377 bool link_up;
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388 if (hw->fc.disable_fc_autoneg)
2389 goto out;
2390
2391 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2392 if (!link_up)
2393 goto out;
2394
2395 switch (hw->phy.media_type) {
2396
2397 case ixgbe_media_type_fiber:
2398 if (speed == IXGBE_LINK_SPEED_1GB_FULL)
2399 ret_val = ixgbe_fc_autoneg_fiber(hw);
2400 break;
2401
2402
2403 case ixgbe_media_type_backplane:
2404 ret_val = ixgbe_fc_autoneg_backplane(hw);
2405 break;
2406
2407
2408 case ixgbe_media_type_copper:
2409 if (ixgbe_device_supports_autoneg_fc(hw))
2410 ret_val = ixgbe_fc_autoneg_copper(hw);
2411 break;
2412
2413 default:
2414 break;
2415 }
2416
2417out:
2418 if (ret_val == 0) {
2419 hw->fc.fc_was_autonegged = true;
2420 } else {
2421 hw->fc.fc_was_autonegged = false;
2422 hw->fc.current_mode = hw->fc.requested_mode;
2423 }
2424}
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436static u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw)
2437{
2438 s16 devctl2;
2439 u32 pollcnt;
2440
2441 devctl2 = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_CONTROL2);
2442 devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK;
2443
2444 switch (devctl2) {
2445 case IXGBE_PCIDEVCTRL2_65_130ms:
2446 pollcnt = 1300;
2447 break;
2448 case IXGBE_PCIDEVCTRL2_260_520ms:
2449 pollcnt = 5200;
2450 break;
2451 case IXGBE_PCIDEVCTRL2_1_2s:
2452 pollcnt = 20000;
2453 break;
2454 case IXGBE_PCIDEVCTRL2_4_8s:
2455 pollcnt = 80000;
2456 break;
2457 case IXGBE_PCIDEVCTRL2_17_34s:
2458 pollcnt = 34000;
2459 break;
2460 case IXGBE_PCIDEVCTRL2_50_100us:
2461 case IXGBE_PCIDEVCTRL2_1_2ms:
2462 case IXGBE_PCIDEVCTRL2_16_32ms:
2463 case IXGBE_PCIDEVCTRL2_16_32ms_def:
2464 default:
2465 pollcnt = 800;
2466 break;
2467 }
2468
2469
2470 return (pollcnt * 11) / 10;
2471}
2472
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
2483{
2484 u32 i, poll;
2485 u16 value;
2486
2487
2488 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
2489
2490
2491 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
2492 if (IXGBE_READ_REG(hw, IXGBE_CTRL) & IXGBE_CTRL_GIO_DIS)
2493 break;
2494 usleep_range(100, 120);
2495 }
2496 if (i >= IXGBE_PCI_MASTER_DISABLE_TIMEOUT) {
2497 hw_dbg(hw, "GIO disable did not set - requesting resets\n");
2498 goto gio_disable_fail;
2499 }
2500
2501
2502 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) ||
2503 ixgbe_removed(hw->hw_addr))
2504 return 0;
2505
2506
2507 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
2508 udelay(100);
2509 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
2510 return 0;
2511 }
2512
2513
2514
2515
2516
2517
2518
2519
2520
2521 hw_dbg(hw, "GIO Master Disable bit didn't clear - requesting resets\n");
2522gio_disable_fail:
2523 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2524
2525 if (hw->mac.type >= ixgbe_mac_X550)
2526 return 0;
2527
2528
2529
2530
2531
2532 poll = ixgbe_pcie_timeout_poll(hw);
2533 for (i = 0; i < poll; i++) {
2534 udelay(100);
2535 value = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_STATUS);
2536 if (ixgbe_removed(hw->hw_addr))
2537 return 0;
2538 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
2539 return 0;
2540 }
2541
2542 hw_dbg(hw, "PCIe transaction pending bit also did not clear.\n");
2543 return IXGBE_ERR_MASTER_REQUESTS_PENDING;
2544}
2545
2546
2547
2548
2549
2550
2551
2552
2553
2554s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask)
2555{
2556 u32 gssr = 0;
2557 u32 swmask = mask;
2558 u32 fwmask = mask << 5;
2559 u32 timeout = 200;
2560 u32 i;
2561
2562 for (i = 0; i < timeout; i++) {
2563
2564
2565
2566
2567 if (ixgbe_get_eeprom_semaphore(hw))
2568 return IXGBE_ERR_SWFW_SYNC;
2569
2570 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2571 if (!(gssr & (fwmask | swmask))) {
2572 gssr |= swmask;
2573 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2574 ixgbe_release_eeprom_semaphore(hw);
2575 return 0;
2576 } else {
2577
2578 ixgbe_release_eeprom_semaphore(hw);
2579 usleep_range(5000, 10000);
2580 }
2581 }
2582
2583
2584 if (gssr & (fwmask | swmask))
2585 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask));
2586
2587 usleep_range(5000, 10000);
2588 return IXGBE_ERR_SWFW_SYNC;
2589}
2590
2591
2592
2593
2594
2595
2596
2597
2598
2599void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask)
2600{
2601 u32 gssr;
2602 u32 swmask = mask;
2603
2604 ixgbe_get_eeprom_semaphore(hw);
2605
2606 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2607 gssr &= ~swmask;
2608 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2609
2610 ixgbe_release_eeprom_semaphore(hw);
2611}
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
2623{
2624 *locked = false;
2625 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2626 return 0;
2627}
2628
2629
2630
2631
2632
2633
2634
2635
2636s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked)
2637{
2638 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val);
2639 return 0;
2640}
2641
2642
2643
2644
2645
2646
2647
2648
2649s32 ixgbe_disable_rx_buff_generic(struct ixgbe_hw *hw)
2650{
2651#define IXGBE_MAX_SECRX_POLL 40
2652 int i;
2653 int secrxreg;
2654
2655 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2656 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
2657 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2658 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
2659 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
2660 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
2661 break;
2662 else
2663
2664 udelay(1000);
2665 }
2666
2667
2668 if (i >= IXGBE_MAX_SECRX_POLL)
2669 hw_dbg(hw, "Rx unit being enabled before security path fully disabled. Continuing with init.\n");
2670
2671 return 0;
2672
2673}
2674
2675
2676
2677
2678
2679
2680
2681s32 ixgbe_enable_rx_buff_generic(struct ixgbe_hw *hw)
2682{
2683 u32 secrxreg;
2684
2685 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2686 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
2687 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2688 IXGBE_WRITE_FLUSH(hw);
2689
2690 return 0;
2691}
2692
2693
2694
2695
2696
2697
2698
2699
2700s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
2701{
2702 if (regval & IXGBE_RXCTRL_RXEN)
2703 hw->mac.ops.enable_rx(hw);
2704 else
2705 hw->mac.ops.disable_rx(hw);
2706
2707 return 0;
2708}
2709
2710
2711
2712
2713
2714
2715s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
2716{
2717 ixgbe_link_speed speed = 0;
2718 bool link_up = false;
2719 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2720 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2721 bool locked = false;
2722 s32 ret_val;
2723
2724 if (index > 3)
2725 return IXGBE_ERR_PARAM;
2726
2727
2728
2729
2730
2731 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2732
2733 if (!link_up) {
2734 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
2735 if (ret_val)
2736 return ret_val;
2737
2738 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2739 autoc_reg |= IXGBE_AUTOC_FLU;
2740
2741 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
2742 if (ret_val)
2743 return ret_val;
2744
2745 IXGBE_WRITE_FLUSH(hw);
2746
2747 usleep_range(10000, 20000);
2748 }
2749
2750 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2751 led_reg |= IXGBE_LED_BLINK(index);
2752 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2753 IXGBE_WRITE_FLUSH(hw);
2754
2755 return 0;
2756}
2757
2758
2759
2760
2761
2762
2763s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
2764{
2765 u32 autoc_reg = 0;
2766 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2767 bool locked = false;
2768 s32 ret_val;
2769
2770 if (index > 3)
2771 return IXGBE_ERR_PARAM;
2772
2773 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
2774 if (ret_val)
2775 return ret_val;
2776
2777 autoc_reg &= ~IXGBE_AUTOC_FLU;
2778 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2779
2780 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
2781 if (ret_val)
2782 return ret_val;
2783
2784 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2785 led_reg &= ~IXGBE_LED_BLINK(index);
2786 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
2787 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2788 IXGBE_WRITE_FLUSH(hw);
2789
2790 return 0;
2791}
2792
2793
2794
2795
2796
2797
2798
2799
2800
2801
2802static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
2803 u16 *san_mac_offset)
2804{
2805 s32 ret_val;
2806
2807
2808
2809
2810
2811 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR,
2812 san_mac_offset);
2813 if (ret_val)
2814 hw_err(hw, "eeprom read at offset %d failed\n",
2815 IXGBE_SAN_MAC_ADDR_PTR);
2816
2817 return ret_val;
2818}
2819
2820
2821
2822
2823
2824
2825
2826
2827
2828
2829
2830s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
2831{
2832 u16 san_mac_data, san_mac_offset;
2833 u8 i;
2834 s32 ret_val;
2835
2836
2837
2838
2839
2840 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
2841 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
2842
2843 goto san_mac_addr_clr;
2844
2845
2846 hw->mac.ops.set_lan_id(hw);
2847
2848 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
2849 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
2850 for (i = 0; i < 3; i++) {
2851 ret_val = hw->eeprom.ops.read(hw, san_mac_offset,
2852 &san_mac_data);
2853 if (ret_val) {
2854 hw_err(hw, "eeprom read at offset %d failed\n",
2855 san_mac_offset);
2856 goto san_mac_addr_clr;
2857 }
2858 san_mac_addr[i * 2] = (u8)(san_mac_data);
2859 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
2860 san_mac_offset++;
2861 }
2862 return 0;
2863
2864san_mac_addr_clr:
2865
2866
2867
2868 for (i = 0; i < 6; i++)
2869 san_mac_addr[i] = 0xFF;
2870 return ret_val;
2871}
2872
2873
2874
2875
2876
2877
2878
2879
2880u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
2881{
2882 u16 msix_count;
2883 u16 max_msix_count;
2884 u16 pcie_offset;
2885
2886 switch (hw->mac.type) {
2887 case ixgbe_mac_82598EB:
2888 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS;
2889 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598;
2890 break;
2891 case ixgbe_mac_82599EB:
2892 case ixgbe_mac_X540:
2893 case ixgbe_mac_X550:
2894 case ixgbe_mac_X550EM_x:
2895 case ixgbe_mac_x550em_a:
2896 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
2897 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
2898 break;
2899 default:
2900 return 1;
2901 }
2902
2903 msix_count = ixgbe_read_pci_cfg_word(hw, pcie_offset);
2904 if (ixgbe_removed(hw->hw_addr))
2905 msix_count = 0;
2906 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
2907
2908
2909 msix_count++;
2910
2911 if (msix_count > max_msix_count)
2912 msix_count = max_msix_count;
2913
2914 return msix_count;
2915}
2916
2917
2918
2919
2920
2921
2922
2923s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2924{
2925 u32 mpsar_lo, mpsar_hi;
2926 u32 rar_entries = hw->mac.num_rar_entries;
2927
2928
2929 if (rar >= rar_entries) {
2930 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
2931 return IXGBE_ERR_INVALID_ARGUMENT;
2932 }
2933
2934 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2935 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
2936
2937 if (ixgbe_removed(hw->hw_addr))
2938 return 0;
2939
2940 if (!mpsar_lo && !mpsar_hi)
2941 return 0;
2942
2943 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
2944 if (mpsar_lo) {
2945 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
2946 mpsar_lo = 0;
2947 }
2948 if (mpsar_hi) {
2949 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
2950 mpsar_hi = 0;
2951 }
2952 } else if (vmdq < 32) {
2953 mpsar_lo &= ~BIT(vmdq);
2954 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
2955 } else {
2956 mpsar_hi &= ~BIT(vmdq - 32);
2957 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
2958 }
2959
2960
2961 if (mpsar_lo == 0 && mpsar_hi == 0 &&
2962 rar != 0 && rar != hw->mac.san_mac_rar_index)
2963 hw->mac.ops.clear_rar(hw, rar);
2964
2965 return 0;
2966}
2967
2968
2969
2970
2971
2972
2973
2974s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2975{
2976 u32 mpsar;
2977 u32 rar_entries = hw->mac.num_rar_entries;
2978
2979
2980 if (rar >= rar_entries) {
2981 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
2982 return IXGBE_ERR_INVALID_ARGUMENT;
2983 }
2984
2985 if (vmdq < 32) {
2986 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2987 mpsar |= BIT(vmdq);
2988 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
2989 } else {
2990 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
2991 mpsar |= BIT(vmdq - 32);
2992 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
2993 }
2994 return 0;
2995}
2996
2997
2998
2999
3000
3001
3002
3003
3004
3005
3006
3007s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)
3008{
3009 u32 rar = hw->mac.san_mac_rar_index;
3010
3011 if (vmdq < 32) {
3012 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), BIT(vmdq));
3013 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3014 } else {
3015 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3016 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), BIT(vmdq - 32));
3017 }
3018
3019 return 0;
3020}
3021
3022
3023
3024
3025
3026s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
3027{
3028 int i;
3029
3030 for (i = 0; i < 128; i++)
3031 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3032
3033 return 0;
3034}
3035
3036
3037
3038
3039
3040
3041
3042
3043
3044static s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass)
3045{
3046 s32 regindex, first_empty_slot;
3047 u32 bits;
3048
3049
3050 if (vlan == 0)
3051 return 0;
3052
3053
3054
3055
3056
3057 first_empty_slot = vlvf_bypass ? IXGBE_ERR_NO_SPACE : 0;
3058
3059
3060 vlan |= IXGBE_VLVF_VIEN;
3061
3062
3063
3064
3065
3066
3067 for (regindex = IXGBE_VLVF_ENTRIES; --regindex;) {
3068 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
3069 if (bits == vlan)
3070 return regindex;
3071 if (!first_empty_slot && !bits)
3072 first_empty_slot = regindex;
3073 }
3074
3075
3076
3077
3078 if (!first_empty_slot)
3079 hw_dbg(hw, "No space in VLVF.\n");
3080
3081 return first_empty_slot ? : IXGBE_ERR_NO_SPACE;
3082}
3083
3084
3085
3086
3087
3088
3089
3090
3091
3092
3093
3094s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3095 bool vlan_on, bool vlvf_bypass)
3096{
3097 u32 regidx, vfta_delta, vfta, bits;
3098 s32 vlvf_index;
3099
3100 if ((vlan > 4095) || (vind > 63))
3101 return IXGBE_ERR_PARAM;
3102
3103
3104
3105
3106
3107
3108
3109
3110
3111
3112
3113
3114
3115 regidx = vlan / 32;
3116 vfta_delta = BIT(vlan % 32);
3117 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regidx));
3118
3119
3120
3121
3122
3123 vfta_delta &= vlan_on ? ~vfta : vfta;
3124 vfta ^= vfta_delta;
3125
3126
3127
3128
3129
3130
3131
3132
3133
3134 if (!(IXGBE_READ_REG(hw, IXGBE_VT_CTL) & IXGBE_VT_CTL_VT_ENABLE))
3135 goto vfta_update;
3136
3137 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan, vlvf_bypass);
3138 if (vlvf_index < 0) {
3139 if (vlvf_bypass)
3140 goto vfta_update;
3141 return vlvf_index;
3142 }
3143
3144 bits = IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32));
3145
3146
3147 bits |= BIT(vind % 32);
3148 if (vlan_on)
3149 goto vlvf_update;
3150
3151
3152 bits ^= BIT(vind % 32);
3153
3154 if (!bits &&
3155 !IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + 1 - vind / 32))) {
3156
3157
3158
3159
3160 if (vfta_delta)
3161 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta);
3162
3163
3164 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
3165 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), 0);
3166
3167 return 0;
3168 }
3169
3170
3171
3172
3173
3174
3175
3176
3177
3178
3179
3180
3181
3182
3183
3184 vfta_delta = 0;
3185
3186vlvf_update:
3187
3188 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), bits);
3189 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), IXGBE_VLVF_VIEN | vlan);
3190
3191vfta_update:
3192
3193 if (vfta_delta)
3194 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta);
3195
3196 return 0;
3197}
3198
3199
3200
3201
3202
3203
3204
3205s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
3206{
3207 u32 offset;
3208
3209 for (offset = 0; offset < hw->mac.vft_size; offset++)
3210 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
3211
3212 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
3213 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
3214 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
3215 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2 + 1), 0);
3216 }
3217
3218 return 0;
3219}
3220
3221
3222
3223
3224
3225
3226
3227
3228static bool ixgbe_need_crosstalk_fix(struct ixgbe_hw *hw)
3229{
3230
3231 if (!hw->need_crosstalk_fix)
3232 return false;
3233
3234
3235 switch (hw->mac.ops.get_media_type(hw)) {
3236 case ixgbe_media_type_fiber:
3237 case ixgbe_media_type_fiber_qsfp:
3238 break;
3239 default:
3240 return false;
3241 }
3242
3243 return true;
3244}
3245
3246
3247
3248
3249
3250
3251
3252
3253
3254
3255s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3256 bool *link_up, bool link_up_wait_to_complete)
3257{
3258 u32 links_reg, links_orig;
3259 u32 i;
3260
3261
3262
3263
3264 if (ixgbe_need_crosstalk_fix(hw)) {
3265 u32 sfp_cage_full;
3266
3267 switch (hw->mac.type) {
3268 case ixgbe_mac_82599EB:
3269 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) &
3270 IXGBE_ESDP_SDP2;
3271 break;
3272 case ixgbe_mac_X550EM_x:
3273 case ixgbe_mac_x550em_a:
3274 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) &
3275 IXGBE_ESDP_SDP0;
3276 break;
3277 default:
3278
3279 sfp_cage_full = false;
3280 break;
3281 }
3282
3283 if (!sfp_cage_full) {
3284 *link_up = false;
3285 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3286 return 0;
3287 }
3288 }
3289
3290
3291 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
3292
3293 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
3294
3295 if (links_orig != links_reg) {
3296 hw_dbg(hw, "LINKS changed from %08X to %08X\n",
3297 links_orig, links_reg);
3298 }
3299
3300 if (link_up_wait_to_complete) {
3301 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
3302 if (links_reg & IXGBE_LINKS_UP) {
3303 *link_up = true;
3304 break;
3305 } else {
3306 *link_up = false;
3307 }
3308 msleep(100);
3309 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
3310 }
3311 } else {
3312 if (links_reg & IXGBE_LINKS_UP)
3313 *link_up = true;
3314 else
3315 *link_up = false;
3316 }
3317
3318 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3319 case IXGBE_LINKS_SPEED_10G_82599:
3320 if ((hw->mac.type >= ixgbe_mac_X550) &&
3321 (links_reg & IXGBE_LINKS_SPEED_NON_STD))
3322 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3323 else
3324 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3325 break;
3326 case IXGBE_LINKS_SPEED_1G_82599:
3327 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3328 break;
3329 case IXGBE_LINKS_SPEED_100_82599:
3330 if ((hw->mac.type >= ixgbe_mac_X550) &&
3331 (links_reg & IXGBE_LINKS_SPEED_NON_STD))
3332 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3333 else
3334 *speed = IXGBE_LINK_SPEED_100_FULL;
3335 break;
3336 default:
3337 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3338 }
3339
3340 return 0;
3341}
3342
3343
3344
3345
3346
3347
3348
3349
3350
3351
3352
3353s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
3354 u16 *wwpn_prefix)
3355{
3356 u16 offset, caps;
3357 u16 alt_san_mac_blk_offset;
3358
3359
3360 *wwnn_prefix = 0xFFFF;
3361 *wwpn_prefix = 0xFFFF;
3362
3363
3364 offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR;
3365 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset))
3366 goto wwn_prefix_err;
3367
3368 if ((alt_san_mac_blk_offset == 0) ||
3369 (alt_san_mac_blk_offset == 0xFFFF))
3370 return 0;
3371
3372
3373 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
3374 if (hw->eeprom.ops.read(hw, offset, &caps))
3375 goto wwn_prefix_err;
3376 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
3377 return 0;
3378
3379
3380 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
3381 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix))
3382 hw_err(hw, "eeprom read at offset %d failed\n", offset);
3383
3384 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
3385 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix))
3386 goto wwn_prefix_err;
3387
3388 return 0;
3389
3390wwn_prefix_err:
3391 hw_err(hw, "eeprom read at offset %d failed\n", offset);
3392 return 0;
3393}
3394
3395
3396
3397
3398
3399
3400
3401
3402void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
3403{
3404 int vf_target_reg = vf >> 3;
3405 int vf_target_shift = vf % 8;
3406 u32 pfvfspoof;
3407
3408 if (hw->mac.type == ixgbe_mac_82598EB)
3409 return;
3410
3411 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
3412 if (enable)
3413 pfvfspoof |= BIT(vf_target_shift);
3414 else
3415 pfvfspoof &= ~BIT(vf_target_shift);
3416 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
3417}
3418
3419
3420
3421
3422
3423
3424
3425
3426void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
3427{
3428 int vf_target_reg = vf >> 3;
3429 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
3430 u32 pfvfspoof;
3431
3432 if (hw->mac.type == ixgbe_mac_82598EB)
3433 return;
3434
3435 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
3436 if (enable)
3437 pfvfspoof |= BIT(vf_target_shift);
3438 else
3439 pfvfspoof &= ~BIT(vf_target_shift);
3440 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
3441}
3442
3443
3444
3445
3446
3447
3448
3449
3450
3451s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
3452{
3453 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
3454
3455 return 0;
3456}
3457
3458
3459
3460
3461
3462
3463
3464
3465void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw,
3466 int num_pb,
3467 u32 headroom,
3468 int strategy)
3469{
3470 u32 pbsize = hw->mac.rx_pb_size;
3471 int i = 0;
3472 u32 rxpktsize, txpktsize, txpbthresh;
3473
3474
3475 pbsize -= headroom;
3476
3477 if (!num_pb)
3478 num_pb = 1;
3479
3480
3481
3482
3483 switch (strategy) {
3484 case (PBA_STRATEGY_WEIGHTED):
3485
3486
3487
3488 rxpktsize = ((pbsize * 5 * 2) / (num_pb * 8));
3489 pbsize -= rxpktsize * (num_pb / 2);
3490 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
3491 for (; i < (num_pb / 2); i++)
3492 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
3493
3494 case (PBA_STRATEGY_EQUAL):
3495
3496 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
3497 for (; i < num_pb; i++)
3498 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
3499 break;
3500 default:
3501 break;
3502 }
3503
3504
3505
3506
3507
3508
3509 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb;
3510 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
3511 for (i = 0; i < num_pb; i++) {
3512 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
3513 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
3514 }
3515
3516
3517 for (; i < IXGBE_MAX_PB; i++) {
3518 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
3519 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
3520 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
3521 }
3522}
3523
3524
3525
3526
3527
3528
3529
3530
3531
3532static u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
3533{
3534 u32 i;
3535 u8 sum = 0;
3536
3537 if (!buffer)
3538 return 0;
3539
3540 for (i = 0; i < length; i++)
3541 sum += buffer[i];
3542
3543 return (u8) (0 - sum);
3544}
3545
3546
3547
3548
3549
3550
3551
3552
3553
3554
3555
3556
3557
3558
3559
3560
3561
3562
3563s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, void *buffer,
3564 u32 length, u32 timeout,
3565 bool return_data)
3566{
3567 u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
3568 u32 hicr, i, bi, fwsts;
3569 u16 buf_len, dword_len;
3570 union {
3571 struct ixgbe_hic_hdr hdr;
3572 u32 u32arr[1];
3573 } *bp = buffer;
3574 s32 status;
3575
3576 if (!length || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
3577 hw_dbg(hw, "Buffer length failure buffersize-%d.\n", length);
3578 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
3579 }
3580
3581 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
3582 if (status)
3583 return status;
3584
3585
3586 fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS);
3587 IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI);
3588
3589
3590 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
3591 if (!(hicr & IXGBE_HICR_EN)) {
3592 hw_dbg(hw, "IXGBE_HOST_EN bit disabled.\n");
3593 status = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3594 goto rel_out;
3595 }
3596
3597
3598 if (length % sizeof(u32)) {
3599 hw_dbg(hw, "Buffer length failure, not aligned to dword");
3600 status = IXGBE_ERR_INVALID_ARGUMENT;
3601 goto rel_out;
3602 }
3603
3604 dword_len = length >> 2;
3605
3606
3607
3608
3609 for (i = 0; i < dword_len; i++)
3610 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
3611 i, cpu_to_le32(bp->u32arr[i]));
3612
3613
3614 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
3615
3616 for (i = 0; i < timeout; i++) {
3617 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
3618 if (!(hicr & IXGBE_HICR_C))
3619 break;
3620 usleep_range(1000, 2000);
3621 }
3622
3623
3624 if ((timeout && i == timeout) ||
3625 !(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV)) {
3626 hw_dbg(hw, "Command has failed with no status valid.\n");
3627 status = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3628 goto rel_out;
3629 }
3630
3631 if (!return_data)
3632 goto rel_out;
3633
3634
3635 dword_len = hdr_size >> 2;
3636
3637
3638 for (bi = 0; bi < dword_len; bi++) {
3639 bp->u32arr[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
3640 le32_to_cpus(&bp->u32arr[bi]);
3641 }
3642
3643
3644 buf_len = bp->hdr.buf_len;
3645 if (!buf_len)
3646 goto rel_out;
3647
3648 if (length < round_up(buf_len, 4) + hdr_size) {
3649 hw_dbg(hw, "Buffer not large enough for reply message.\n");
3650 status = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3651 goto rel_out;
3652 }
3653
3654
3655 dword_len = (buf_len + 3) >> 2;
3656
3657
3658 for (; bi <= dword_len; bi++) {
3659 bp->u32arr[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
3660 le32_to_cpus(&bp->u32arr[bi]);
3661 }
3662
3663rel_out:
3664 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
3665
3666 return status;
3667}
3668
3669
3670
3671
3672
3673
3674
3675
3676
3677
3678
3679
3680
3681
3682s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
3683 u8 build, u8 sub)
3684{
3685 struct ixgbe_hic_drv_info fw_cmd;
3686 int i;
3687 s32 ret_val;
3688
3689 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
3690 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
3691 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
3692 fw_cmd.port_num = hw->bus.func;
3693 fw_cmd.ver_maj = maj;
3694 fw_cmd.ver_min = min;
3695 fw_cmd.ver_build = build;
3696 fw_cmd.ver_sub = sub;
3697 fw_cmd.hdr.checksum = 0;
3698 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
3699 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
3700 fw_cmd.pad = 0;
3701 fw_cmd.pad2 = 0;
3702
3703 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
3704 ret_val = ixgbe_host_interface_command(hw, &fw_cmd,
3705 sizeof(fw_cmd),
3706 IXGBE_HI_COMMAND_TIMEOUT,
3707 true);
3708 if (ret_val != 0)
3709 continue;
3710
3711 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
3712 FW_CEM_RESP_STATUS_SUCCESS)
3713 ret_val = 0;
3714 else
3715 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3716
3717 break;
3718 }
3719
3720 return ret_val;
3721}
3722
3723
3724
3725
3726
3727
3728
3729
3730
3731void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
3732{
3733 u32 gcr_ext, hlreg0, i, poll;
3734 u16 value;
3735
3736
3737
3738
3739
3740 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
3741 return;
3742
3743
3744
3745
3746
3747
3748 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3749 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);
3750
3751
3752 IXGBE_WRITE_FLUSH(hw);
3753 usleep_range(3000, 6000);
3754
3755
3756
3757
3758 poll = ixgbe_pcie_timeout_poll(hw);
3759 for (i = 0; i < poll; i++) {
3760 usleep_range(100, 200);
3761 value = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_STATUS);
3762 if (ixgbe_removed(hw->hw_addr))
3763 break;
3764 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
3765 break;
3766 }
3767
3768
3769 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3770 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,
3771 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR);
3772
3773
3774 IXGBE_WRITE_FLUSH(hw);
3775 udelay(20);
3776
3777
3778 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3779 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3780}
3781
3782static const u8 ixgbe_emc_temp_data[4] = {
3783 IXGBE_EMC_INTERNAL_DATA,
3784 IXGBE_EMC_DIODE1_DATA,
3785 IXGBE_EMC_DIODE2_DATA,
3786 IXGBE_EMC_DIODE3_DATA
3787};
3788static const u8 ixgbe_emc_therm_limit[4] = {
3789 IXGBE_EMC_INTERNAL_THERM_LIMIT,
3790 IXGBE_EMC_DIODE1_THERM_LIMIT,
3791 IXGBE_EMC_DIODE2_THERM_LIMIT,
3792 IXGBE_EMC_DIODE3_THERM_LIMIT
3793};
3794
3795
3796
3797
3798
3799
3800
3801
3802
3803static s32 ixgbe_get_ets_data(struct ixgbe_hw *hw, u16 *ets_cfg,
3804 u16 *ets_offset)
3805{
3806 s32 status;
3807
3808 status = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, ets_offset);
3809 if (status)
3810 return status;
3811
3812 if ((*ets_offset == 0x0000) || (*ets_offset == 0xFFFF))
3813 return IXGBE_NOT_IMPLEMENTED;
3814
3815 status = hw->eeprom.ops.read(hw, *ets_offset, ets_cfg);
3816 if (status)
3817 return status;
3818
3819 if ((*ets_cfg & IXGBE_ETS_TYPE_MASK) != IXGBE_ETS_TYPE_EMC_SHIFTED)
3820 return IXGBE_NOT_IMPLEMENTED;
3821
3822 return 0;
3823}
3824
3825
3826
3827
3828
3829
3830
3831s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw)
3832{
3833 s32 status;
3834 u16 ets_offset;
3835 u16 ets_cfg;
3836 u16 ets_sensor;
3837 u8 num_sensors;
3838 u8 i;
3839 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
3840
3841
3842 if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1))
3843 return IXGBE_NOT_IMPLEMENTED;
3844
3845 status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset);
3846 if (status)
3847 return status;
3848
3849 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
3850 if (num_sensors > IXGBE_MAX_SENSORS)
3851 num_sensors = IXGBE_MAX_SENSORS;
3852
3853 for (i = 0; i < num_sensors; i++) {
3854 u8 sensor_index;
3855 u8 sensor_location;
3856
3857 status = hw->eeprom.ops.read(hw, (ets_offset + 1 + i),
3858 &ets_sensor);
3859 if (status)
3860 return status;
3861
3862 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
3863 IXGBE_ETS_DATA_INDEX_SHIFT);
3864 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
3865 IXGBE_ETS_DATA_LOC_SHIFT);
3866
3867 if (sensor_location != 0) {
3868 status = hw->phy.ops.read_i2c_byte(hw,
3869 ixgbe_emc_temp_data[sensor_index],
3870 IXGBE_I2C_THERMAL_SENSOR_ADDR,
3871 &data->sensor[i].temp);
3872 if (status)
3873 return status;
3874 }
3875 }
3876
3877 return 0;
3878}
3879
3880
3881
3882
3883
3884
3885
3886
3887s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw)
3888{
3889 s32 status;
3890 u16 ets_offset;
3891 u16 ets_cfg;
3892 u16 ets_sensor;
3893 u8 low_thresh_delta;
3894 u8 num_sensors;
3895 u8 therm_limit;
3896 u8 i;
3897 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
3898
3899 memset(data, 0, sizeof(struct ixgbe_thermal_sensor_data));
3900
3901
3902 if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1))
3903 return IXGBE_NOT_IMPLEMENTED;
3904
3905 status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset);
3906 if (status)
3907 return status;
3908
3909 low_thresh_delta = ((ets_cfg & IXGBE_ETS_LTHRES_DELTA_MASK) >>
3910 IXGBE_ETS_LTHRES_DELTA_SHIFT);
3911 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
3912 if (num_sensors > IXGBE_MAX_SENSORS)
3913 num_sensors = IXGBE_MAX_SENSORS;
3914
3915 for (i = 0; i < num_sensors; i++) {
3916 u8 sensor_index;
3917 u8 sensor_location;
3918
3919 if (hw->eeprom.ops.read(hw, ets_offset + 1 + i, &ets_sensor)) {
3920 hw_err(hw, "eeprom read at offset %d failed\n",
3921 ets_offset + 1 + i);
3922 continue;
3923 }
3924 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
3925 IXGBE_ETS_DATA_INDEX_SHIFT);
3926 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
3927 IXGBE_ETS_DATA_LOC_SHIFT);
3928 therm_limit = ets_sensor & IXGBE_ETS_DATA_HTHRESH_MASK;
3929
3930 hw->phy.ops.write_i2c_byte(hw,
3931 ixgbe_emc_therm_limit[sensor_index],
3932 IXGBE_I2C_THERMAL_SENSOR_ADDR, therm_limit);
3933
3934 if (sensor_location == 0)
3935 continue;
3936
3937 data->sensor[i].location = sensor_location;
3938 data->sensor[i].caution_thresh = therm_limit;
3939 data->sensor[i].max_op_thresh = therm_limit - low_thresh_delta;
3940 }
3941
3942 return 0;
3943}
3944
3945void ixgbe_disable_rx_generic(struct ixgbe_hw *hw)
3946{
3947 u32 rxctrl;
3948
3949 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3950 if (rxctrl & IXGBE_RXCTRL_RXEN) {
3951 if (hw->mac.type != ixgbe_mac_82598EB) {
3952 u32 pfdtxgswc;
3953
3954 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3955 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
3956 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
3957 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3958 hw->mac.set_lben = true;
3959 } else {
3960 hw->mac.set_lben = false;
3961 }
3962 }
3963 rxctrl &= ~IXGBE_RXCTRL_RXEN;
3964 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
3965 }
3966}
3967
3968void ixgbe_enable_rx_generic(struct ixgbe_hw *hw)
3969{
3970 u32 rxctrl;
3971
3972 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3973 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN));
3974
3975 if (hw->mac.type != ixgbe_mac_82598EB) {
3976 if (hw->mac.set_lben) {
3977 u32 pfdtxgswc;
3978
3979 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
3980 pfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN;
3981 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
3982 hw->mac.set_lben = false;
3983 }
3984 }
3985}
3986
3987
3988
3989
3990bool ixgbe_mng_present(struct ixgbe_hw *hw)
3991{
3992 u32 fwsm;
3993
3994 if (hw->mac.type < ixgbe_mac_82599EB)
3995 return false;
3996
3997 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw));
3998 fwsm &= IXGBE_FWSM_MODE_MASK;
3999 return fwsm == IXGBE_FWSM_FW_MODE_PT;
4000}
4001
4002
4003
4004
4005
4006
4007
4008
4009
4010s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
4011 ixgbe_link_speed speed,
4012 bool autoneg_wait_to_complete)
4013{
4014 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4015 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4016 s32 status = 0;
4017 u32 speedcnt = 0;
4018 u32 i = 0;
4019 bool autoneg, link_up = false;
4020
4021
4022 status = hw->mac.ops.get_link_capabilities(hw, &link_speed, &autoneg);
4023 if (status)
4024 return status;
4025
4026 speed &= link_speed;
4027
4028
4029
4030
4031 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
4032 speedcnt++;
4033 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
4034
4035
4036 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
4037 false);
4038 if (status)
4039 return status;
4040
4041 if (link_speed == IXGBE_LINK_SPEED_10GB_FULL && link_up)
4042 goto out;
4043
4044
4045 switch (hw->phy.media_type) {
4046 case ixgbe_media_type_fiber:
4047 hw->mac.ops.set_rate_select_speed(hw,
4048 IXGBE_LINK_SPEED_10GB_FULL);
4049 break;
4050 case ixgbe_media_type_fiber_qsfp:
4051
4052 break;
4053 default:
4054 hw_dbg(hw, "Unexpected media type\n");
4055 break;
4056 }
4057
4058
4059 msleep(40);
4060
4061 status = hw->mac.ops.setup_mac_link(hw,
4062 IXGBE_LINK_SPEED_10GB_FULL,
4063 autoneg_wait_to_complete);
4064 if (status)
4065 return status;
4066
4067
4068 if (hw->mac.ops.flap_tx_laser)
4069 hw->mac.ops.flap_tx_laser(hw);
4070
4071
4072
4073
4074
4075 for (i = 0; i < 5; i++) {
4076
4077 msleep(100);
4078
4079
4080 status = hw->mac.ops.check_link(hw, &link_speed,
4081 &link_up, false);
4082 if (status)
4083 return status;
4084
4085 if (link_up)
4086 goto out;
4087 }
4088 }
4089
4090 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
4091 speedcnt++;
4092 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
4093 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
4094
4095
4096 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
4097 false);
4098 if (status)
4099 return status;
4100
4101 if (link_speed == IXGBE_LINK_SPEED_1GB_FULL && link_up)
4102 goto out;
4103
4104
4105 switch (hw->phy.media_type) {
4106 case ixgbe_media_type_fiber:
4107 hw->mac.ops.set_rate_select_speed(hw,
4108 IXGBE_LINK_SPEED_1GB_FULL);
4109 break;
4110 case ixgbe_media_type_fiber_qsfp:
4111
4112 break;
4113 default:
4114 hw_dbg(hw, "Unexpected media type\n");
4115 break;
4116 }
4117
4118
4119 msleep(40);
4120
4121 status = hw->mac.ops.setup_mac_link(hw,
4122 IXGBE_LINK_SPEED_1GB_FULL,
4123 autoneg_wait_to_complete);
4124 if (status)
4125 return status;
4126
4127
4128 if (hw->mac.ops.flap_tx_laser)
4129 hw->mac.ops.flap_tx_laser(hw);
4130
4131
4132 msleep(100);
4133
4134
4135 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
4136 false);
4137 if (status)
4138 return status;
4139
4140 if (link_up)
4141 goto out;
4142 }
4143
4144
4145
4146
4147
4148 if (speedcnt > 1)
4149 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
4150 highest_link_speed,
4151 autoneg_wait_to_complete);
4152
4153out:
4154
4155 hw->phy.autoneg_advertised = 0;
4156
4157 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
4158 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
4159
4160 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
4161 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
4162
4163 return status;
4164}
4165
4166
4167
4168
4169
4170
4171
4172
4173void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw,
4174 ixgbe_link_speed speed)
4175{
4176 s32 status;
4177 u8 rs, eeprom_data;
4178
4179 switch (speed) {
4180 case IXGBE_LINK_SPEED_10GB_FULL:
4181
4182 rs = IXGBE_SFF_SOFT_RS_SELECT_10G;
4183 break;
4184 case IXGBE_LINK_SPEED_1GB_FULL:
4185 rs = IXGBE_SFF_SOFT_RS_SELECT_1G;
4186 break;
4187 default:
4188 hw_dbg(hw, "Invalid fixed module speed\n");
4189 return;
4190 }
4191
4192
4193 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
4194 IXGBE_I2C_EEPROM_DEV_ADDR2,
4195 &eeprom_data);
4196 if (status) {
4197 hw_dbg(hw, "Failed to read Rx Rate Select RS0\n");
4198 return;
4199 }
4200
4201 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) | rs;
4202
4203 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
4204 IXGBE_I2C_EEPROM_DEV_ADDR2,
4205 eeprom_data);
4206 if (status) {
4207 hw_dbg(hw, "Failed to write Rx Rate Select RS0\n");
4208 return;
4209 }
4210}
4211