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34static const char version[] =
35"atp.c:v1.09=ac 2002/10/01 Donald Becker <becker@scyld.com>\n";
36
37
38
39
40static int debug = 1;
41#define net_debug debug
42
43
44static int max_interrupt_work = 15;
45
46#define NUM_UNITS 2
47
48static int io[NUM_UNITS];
49static int irq[NUM_UNITS];
50static int xcvr[NUM_UNITS];
51
52
53
54
55#define TX_TIMEOUT (400*HZ/1000)
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125#include <linux/kernel.h>
126#include <linux/module.h>
127#include <linux/types.h>
128#include <linux/fcntl.h>
129#include <linux/interrupt.h>
130#include <linux/ioport.h>
131#include <linux/in.h>
132#include <linux/string.h>
133#include <linux/errno.h>
134#include <linux/init.h>
135#include <linux/crc32.h>
136#include <linux/netdevice.h>
137#include <linux/etherdevice.h>
138#include <linux/skbuff.h>
139#include <linux/spinlock.h>
140#include <linux/delay.h>
141#include <linux/bitops.h>
142
143#include <asm/io.h>
144#include <asm/dma.h>
145
146#include "atp.h"
147
148MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
149MODULE_DESCRIPTION("RealTek RTL8002/8012 parallel port Ethernet driver");
150MODULE_LICENSE("GPL");
151
152module_param(max_interrupt_work, int, 0);
153module_param(debug, int, 0);
154module_param_array(io, int, NULL, 0);
155module_param_array(irq, int, NULL, 0);
156module_param_array(xcvr, int, NULL, 0);
157MODULE_PARM_DESC(max_interrupt_work, "ATP maximum events handled per interrupt");
158MODULE_PARM_DESC(debug, "ATP debug level (0-7)");
159MODULE_PARM_DESC(io, "ATP I/O base address(es)");
160MODULE_PARM_DESC(irq, "ATP IRQ number(s)");
161MODULE_PARM_DESC(xcvr, "ATP transceiver(s) (0=internal, 1=external)");
162
163
164#define ETHERCARD_TOTAL_SIZE 3
165
166
167static char mux_8012[] = { 0xff, 0xf7, 0xff, 0xfb, 0xf3, 0xfb, 0xff, 0xf7,};
168
169struct net_local {
170 spinlock_t lock;
171 struct net_device *next_module;
172 struct timer_list timer;
173 long last_rx_time;
174 int saved_tx_size;
175 unsigned int tx_unit_busy:1;
176 unsigned char re_tx,
177 addr_mode,
178 pac_cnt_in_tx_buf;
179};
180
181
182
183
184#define TIMED_CHECKER (HZ/4)
185#ifdef TIMED_CHECKER
186#include <linux/timer.h>
187static void atp_timed_checker(unsigned long ignored);
188#endif
189
190
191
192static int atp_probe1(long ioaddr);
193static void get_node_ID(struct net_device *dev);
194static unsigned short eeprom_op(long ioaddr, unsigned int cmd);
195static int net_open(struct net_device *dev);
196static void hardware_init(struct net_device *dev);
197static void write_packet(long ioaddr, int length, unsigned char *packet, int pad, int mode);
198static void trigger_send(long ioaddr, int length);
199static netdev_tx_t atp_send_packet(struct sk_buff *skb,
200 struct net_device *dev);
201static irqreturn_t atp_interrupt(int irq, void *dev_id);
202static void net_rx(struct net_device *dev);
203static void read_block(long ioaddr, int length, unsigned char *buffer, int data_mode);
204static int net_close(struct net_device *dev);
205static void set_rx_mode(struct net_device *dev);
206static void tx_timeout(struct net_device *dev);
207
208
209
210static struct net_device *root_atp_dev;
211
212
213
214
215
216
217
218
219
220static int __init atp_init(void)
221{
222 int *port, ports[] = {0x378, 0x278, 0x3bc, 0};
223 int base_addr = io[0];
224
225 if (base_addr > 0x1ff)
226 return atp_probe1(base_addr);
227 else if (base_addr == 1)
228 return -ENXIO;
229
230 for (port = ports; *port; port++) {
231 long ioaddr = *port;
232 outb(0x57, ioaddr + PAR_DATA);
233 if (inb(ioaddr + PAR_DATA) != 0x57)
234 continue;
235 if (atp_probe1(ioaddr) == 0)
236 return 0;
237 }
238
239 return -ENODEV;
240}
241
242static const struct net_device_ops atp_netdev_ops = {
243 .ndo_open = net_open,
244 .ndo_stop = net_close,
245 .ndo_start_xmit = atp_send_packet,
246 .ndo_set_rx_mode = set_rx_mode,
247 .ndo_tx_timeout = tx_timeout,
248 .ndo_change_mtu = eth_change_mtu,
249 .ndo_set_mac_address = eth_mac_addr,
250 .ndo_validate_addr = eth_validate_addr,
251};
252
253static int __init atp_probe1(long ioaddr)
254{
255 struct net_device *dev = NULL;
256 struct net_local *lp;
257 int saved_ctrl_reg, status, i;
258 int res;
259
260 outb(0xff, ioaddr + PAR_DATA);
261
262
263 saved_ctrl_reg = inb(ioaddr + PAR_CONTROL);
264 if (net_debug > 3)
265 printk("atp: Control register was %#2.2x.\n", saved_ctrl_reg);
266
267 outb(0x04, ioaddr + PAR_CONTROL);
268#ifndef final_version
269 if (net_debug > 3) {
270
271 for (i = 0; i < 8; i++)
272 outb(mux_8012[i], ioaddr + PAR_DATA);
273 write_reg(ioaddr, MODSEL, 0x00);
274 printk("atp: Registers are ");
275 for (i = 0; i < 32; i++)
276 printk(" %2.2x", read_nibble(ioaddr, i));
277 printk(".\n");
278 }
279#endif
280
281 for (i = 0; i < 8; i++)
282 outb(mux_8012[i], ioaddr + PAR_DATA);
283 write_reg_high(ioaddr, CMR1, CMR1h_RESET);
284
285 status = read_nibble(ioaddr, CMR1);
286
287 if (net_debug > 3) {
288 printk(KERN_DEBUG "atp: Status nibble was %#2.2x..", status);
289 for (i = 0; i < 32; i++)
290 printk(" %2.2x", read_nibble(ioaddr, i));
291 printk("\n");
292 }
293
294 if ((status & 0x78) != 0x08) {
295
296 outb(saved_ctrl_reg, ioaddr + PAR_CONTROL);
297 return -ENODEV;
298 }
299 status = read_nibble(ioaddr, CMR2_h);
300 if ((status & 0x78) != 0x10) {
301 outb(saved_ctrl_reg, ioaddr + PAR_CONTROL);
302 return -ENODEV;
303 }
304
305 dev = alloc_etherdev(sizeof(struct net_local));
306 if (!dev)
307 return -ENOMEM;
308
309
310 write_reg_byte(ioaddr, CMR2, 0x01);
311 write_reg_high(ioaddr, CMR1, CMR1h_RxENABLE | CMR1h_TxENABLE);
312
313
314 if (irq[0])
315 dev->irq = irq[0];
316 else if (ioaddr == 0x378)
317 dev->irq = 7;
318 else
319 dev->irq = 5;
320 write_reg_high(ioaddr, CMR1, CMR1h_TxRxOFF);
321 write_reg(ioaddr, CMR2, CMR2_NULL);
322
323 dev->base_addr = ioaddr;
324
325
326 get_node_ID(dev);
327
328#ifndef MODULE
329 if (net_debug)
330 printk(KERN_INFO "%s", version);
331#endif
332
333 printk(KERN_NOTICE "%s: Pocket adapter found at %#3lx, IRQ %d, "
334 "SAPROM %pM.\n",
335 dev->name, dev->base_addr, dev->irq, dev->dev_addr);
336
337
338 write_reg_high(ioaddr, CMR1, CMR1h_RESET | CMR1h_MUX);
339
340 lp = netdev_priv(dev);
341 lp->addr_mode = CMR2h_Normal;
342 spin_lock_init(&lp->lock);
343
344
345 if (xcvr[0])
346 dev->if_port = xcvr[0];
347 else
348 dev->if_port = (dev->mem_start & 0xf) ? (dev->mem_start & 0x7) : 4;
349 if (dev->mem_end & 0xf)
350 net_debug = dev->mem_end & 7;
351
352 dev->netdev_ops = &atp_netdev_ops;
353 dev->watchdog_timeo = TX_TIMEOUT;
354
355 res = register_netdev(dev);
356 if (res) {
357 free_netdev(dev);
358 return res;
359 }
360
361 lp->next_module = root_atp_dev;
362 root_atp_dev = dev;
363
364 return 0;
365}
366
367
368static void __init get_node_ID(struct net_device *dev)
369{
370 long ioaddr = dev->base_addr;
371 int sa_offset = 0;
372 int i;
373
374 write_reg(ioaddr, CMR2, CMR2_EEPROM);
375
376
377
378 if (eeprom_op(ioaddr, EE_READ(0)) == 0xffff)
379 sa_offset = 15;
380
381 for (i = 0; i < 3; i++)
382 ((__be16 *)dev->dev_addr)[i] =
383 cpu_to_be16(eeprom_op(ioaddr, EE_READ(sa_offset + i)));
384
385 write_reg(ioaddr, CMR2, CMR2_NULL);
386}
387
388
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397
398
399
400static unsigned short __init eeprom_op(long ioaddr, u32 cmd)
401{
402 unsigned eedata_out = 0;
403 int num_bits = EE_CMD_SIZE;
404
405 while (--num_bits >= 0) {
406 char outval = (cmd & (1<<num_bits)) ? EE_DATA_WRITE : 0;
407 write_reg_high(ioaddr, PROM_CMD, outval | EE_CLK_LOW);
408 write_reg_high(ioaddr, PROM_CMD, outval | EE_CLK_HIGH);
409 eedata_out <<= 1;
410 if (read_nibble(ioaddr, PROM_DATA) & EE_DATA_READ)
411 eedata_out++;
412 }
413 write_reg_high(ioaddr, PROM_CMD, EE_CLK_LOW & ~EE_CS);
414 return eedata_out;
415}
416
417
418
419
420
421
422
423
424
425
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427
428static int net_open(struct net_device *dev)
429{
430 struct net_local *lp = netdev_priv(dev);
431 int ret;
432
433
434
435
436 ret = request_irq(dev->irq, atp_interrupt, 0, dev->name, dev);
437 if (ret)
438 return ret;
439
440 hardware_init(dev);
441
442 init_timer(&lp->timer);
443 lp->timer.expires = jiffies + TIMED_CHECKER;
444 lp->timer.data = (unsigned long)dev;
445 lp->timer.function = atp_timed_checker;
446 add_timer(&lp->timer);
447
448 netif_start_queue(dev);
449 return 0;
450}
451
452
453
454static void hardware_init(struct net_device *dev)
455{
456 struct net_local *lp = netdev_priv(dev);
457 long ioaddr = dev->base_addr;
458 int i;
459
460
461 for (i = 0; i < 8; i++)
462 outb(mux_8012[i], ioaddr + PAR_DATA);
463 write_reg_high(ioaddr, CMR1, CMR1h_RESET);
464
465 for (i = 0; i < 6; i++)
466 write_reg_byte(ioaddr, PAR0 + i, dev->dev_addr[i]);
467
468 write_reg_high(ioaddr, CMR2, lp->addr_mode);
469
470 if (net_debug > 2) {
471 printk(KERN_DEBUG "%s: Reset: current Rx mode %d.\n", dev->name,
472 (read_nibble(ioaddr, CMR2_h) >> 3) & 0x0f);
473 }
474
475 write_reg(ioaddr, CMR2, CMR2_IRQOUT);
476 write_reg_high(ioaddr, CMR1, CMR1h_RxENABLE | CMR1h_TxENABLE);
477
478
479 outb(Ctrl_SelData + Ctrl_IRQEN, ioaddr + PAR_CONTROL);
480
481
482 write_reg(ioaddr, IMR, ISR_RxOK | ISR_TxErr | ISR_TxOK);
483 write_reg_high(ioaddr, IMR, ISRh_RxErr);
484
485 lp->tx_unit_busy = 0;
486 lp->pac_cnt_in_tx_buf = 0;
487 lp->saved_tx_size = 0;
488}
489
490static void trigger_send(long ioaddr, int length)
491{
492 write_reg_byte(ioaddr, TxCNT0, length & 0xff);
493 write_reg(ioaddr, TxCNT1, length >> 8);
494 write_reg(ioaddr, CMR1, CMR1_Xmit);
495}
496
497static void write_packet(long ioaddr, int length, unsigned char *packet, int pad_len, int data_mode)
498{
499 if (length & 1)
500 {
501 length++;
502 pad_len++;
503 }
504
505 outb(EOC+MAR, ioaddr + PAR_DATA);
506 if ((data_mode & 1) == 0) {
507
508 outb(WrAddr+MAR, ioaddr + PAR_DATA);
509 do {
510 write_byte_mode0(ioaddr, *packet++);
511 } while (--length > pad_len) ;
512 do {
513 write_byte_mode0(ioaddr, 0);
514 } while (--length > 0) ;
515 } else {
516
517 unsigned char outbyte = *packet++;
518
519 outb(Ctrl_LNibWrite + Ctrl_IRQEN, ioaddr + PAR_CONTROL);
520 outb(WrAddr+MAR, ioaddr + PAR_DATA);
521
522 outb((outbyte & 0x0f)|0x40, ioaddr + PAR_DATA);
523 outb(outbyte & 0x0f, ioaddr + PAR_DATA);
524 outbyte >>= 4;
525 outb(outbyte & 0x0f, ioaddr + PAR_DATA);
526 outb(Ctrl_HNibWrite + Ctrl_IRQEN, ioaddr + PAR_CONTROL);
527 while (--length > pad_len)
528 write_byte_mode1(ioaddr, *packet++);
529 while (--length > 0)
530 write_byte_mode1(ioaddr, 0);
531 }
532
533 outb(0xff, ioaddr + PAR_DATA);
534 outb(Ctrl_HNibWrite | Ctrl_SelData | Ctrl_IRQEN, ioaddr + PAR_CONTROL);
535}
536
537static void tx_timeout(struct net_device *dev)
538{
539 long ioaddr = dev->base_addr;
540
541 printk(KERN_WARNING "%s: Transmit timed out, %s?\n", dev->name,
542 inb(ioaddr + PAR_CONTROL) & 0x10 ? "network cable problem"
543 : "IRQ conflict");
544 dev->stats.tx_errors++;
545
546 hardware_init(dev);
547 netif_trans_update(dev);
548 netif_wake_queue(dev);
549 dev->stats.tx_errors++;
550}
551
552static netdev_tx_t atp_send_packet(struct sk_buff *skb,
553 struct net_device *dev)
554{
555 struct net_local *lp = netdev_priv(dev);
556 long ioaddr = dev->base_addr;
557 int length;
558 unsigned long flags;
559
560 length = ETH_ZLEN < skb->len ? skb->len : ETH_ZLEN;
561
562 netif_stop_queue(dev);
563
564
565
566
567 spin_lock_irqsave(&lp->lock, flags);
568 write_reg(ioaddr, IMR, 0);
569 write_reg_high(ioaddr, IMR, 0);
570 spin_unlock_irqrestore(&lp->lock, flags);
571
572 write_packet(ioaddr, length, skb->data, length-skb->len, dev->if_port);
573
574 lp->pac_cnt_in_tx_buf++;
575 if (lp->tx_unit_busy == 0) {
576 trigger_send(ioaddr, length);
577 lp->saved_tx_size = 0;
578 lp->re_tx = 0;
579 lp->tx_unit_busy = 1;
580 } else
581 lp->saved_tx_size = length;
582
583 write_reg(ioaddr, IMR, ISR_RxOK | ISR_TxErr | ISR_TxOK);
584 write_reg_high(ioaddr, IMR, ISRh_RxErr);
585
586 dev_kfree_skb (skb);
587 return NETDEV_TX_OK;
588}
589
590
591
592
593static irqreturn_t atp_interrupt(int irq, void *dev_instance)
594{
595 struct net_device *dev = dev_instance;
596 struct net_local *lp;
597 long ioaddr;
598 static int num_tx_since_rx;
599 int boguscount = max_interrupt_work;
600 int handled = 0;
601
602 ioaddr = dev->base_addr;
603 lp = netdev_priv(dev);
604
605 spin_lock(&lp->lock);
606
607
608 outb(Ctrl_SelData, ioaddr + PAR_CONTROL);
609
610
611 write_reg(ioaddr, CMR2, CMR2_NULL);
612 write_reg(ioaddr, IMR, 0);
613
614 if (net_debug > 5) printk(KERN_DEBUG "%s: In interrupt ", dev->name);
615 while (--boguscount > 0) {
616 int status = read_nibble(ioaddr, ISR);
617 if (net_debug > 5) printk("loop status %02x..", status);
618
619 if (status & (ISR_RxOK<<3)) {
620 handled = 1;
621 write_reg(ioaddr, ISR, ISR_RxOK);
622 do {
623 int read_status = read_nibble(ioaddr, CMR1);
624 if (net_debug > 6)
625 printk("handling Rx packet %02x..", read_status);
626
627
628 if (read_status & (CMR1_IRQ << 3)) {
629 dev->stats.rx_over_errors++;
630
631 write_reg_high(ioaddr, CMR2, CMR2h_OFF);
632 net_rx(dev);
633
634 write_reg_high(ioaddr, ISR, ISRh_RxErr);
635 write_reg_high(ioaddr, CMR2, lp->addr_mode);
636 } else if ((read_status & (CMR1_BufEnb << 3)) == 0) {
637 net_rx(dev);
638 num_tx_since_rx = 0;
639 } else
640 break;
641 } while (--boguscount > 0);
642 } else if (status & ((ISR_TxErr + ISR_TxOK)<<3)) {
643 handled = 1;
644 if (net_debug > 6) printk("handling Tx done..");
645
646
647 write_reg(ioaddr, ISR, ISR_TxErr + ISR_TxOK);
648 if (status & (ISR_TxErr<<3)) {
649 dev->stats.collisions++;
650 if (++lp->re_tx > 15) {
651 dev->stats.tx_aborted_errors++;
652 hardware_init(dev);
653 break;
654 }
655
656 if (net_debug > 6) printk("attempting to ReTx");
657 write_reg(ioaddr, CMR1, CMR1_ReXmit + CMR1_Xmit);
658 } else {
659
660 dev->stats.tx_packets++;
661 lp->pac_cnt_in_tx_buf--;
662 if ( lp->saved_tx_size) {
663 trigger_send(ioaddr, lp->saved_tx_size);
664 lp->saved_tx_size = 0;
665 lp->re_tx = 0;
666 } else
667 lp->tx_unit_busy = 0;
668 netif_wake_queue(dev);
669 }
670 num_tx_since_rx++;
671 } else if (num_tx_since_rx > 8 &&
672 time_after(jiffies, dev->last_rx + HZ)) {
673 if (net_debug > 2)
674 printk(KERN_DEBUG "%s: Missed packet? No Rx after %d Tx and "
675 "%ld jiffies status %02x CMR1 %02x.\n", dev->name,
676 num_tx_since_rx, jiffies - dev->last_rx, status,
677 (read_nibble(ioaddr, CMR1) >> 3) & 15);
678 dev->stats.rx_missed_errors++;
679 hardware_init(dev);
680 num_tx_since_rx = 0;
681 break;
682 } else
683 break;
684 }
685
686
687
688 {
689 int i;
690 for (i = 0; i < 6; i++)
691 write_reg_byte(ioaddr, PAR0 + i, dev->dev_addr[i]);
692#if 0 && defined(TIMED_CHECKER)
693 mod_timer(&lp->timer, jiffies + TIMED_CHECKER);
694#endif
695 }
696
697
698 write_reg(ioaddr, CMR2, CMR2_IRQOUT);
699
700 outb(Ctrl_SelData + Ctrl_IRQEN, ioaddr + PAR_CONTROL);
701
702 write_reg(ioaddr, IMR, ISR_RxOK | ISR_TxErr | ISR_TxOK);
703 write_reg_high(ioaddr, IMR, ISRh_RxErr);
704
705 spin_unlock(&lp->lock);
706
707 if (net_debug > 5) printk("exiting interrupt.\n");
708 return IRQ_RETVAL(handled);
709}
710
711#ifdef TIMED_CHECKER
712
713
714static void atp_timed_checker(unsigned long data)
715{
716 struct net_device *dev = (struct net_device *)data;
717 long ioaddr = dev->base_addr;
718 struct net_local *lp = netdev_priv(dev);
719 int tickssofar = jiffies - lp->last_rx_time;
720 int i;
721
722 spin_lock(&lp->lock);
723 if (tickssofar > 2*HZ) {
724#if 1
725 for (i = 0; i < 6; i++)
726 write_reg_byte(ioaddr, PAR0 + i, dev->dev_addr[i]);
727 lp->last_rx_time = jiffies;
728#else
729 for (i = 0; i < 6; i++)
730 if (read_cmd_byte(ioaddr, PAR0 + i) != atp_timed_dev->dev_addr[i])
731 {
732 struct net_local *lp = netdev_priv(atp_timed_dev);
733 write_reg_byte(ioaddr, PAR0 + i, atp_timed_dev->dev_addr[i]);
734 if (i == 2)
735 dev->stats.tx_errors++;
736 else if (i == 3)
737 dev->stats.tx_dropped++;
738 else if (i == 4)
739 dev->stats.collisions++;
740 else
741 dev->stats.rx_errors++;
742 }
743#endif
744 }
745 spin_unlock(&lp->lock);
746 lp->timer.expires = jiffies + TIMED_CHECKER;
747 add_timer(&lp->timer);
748}
749#endif
750
751
752static void net_rx(struct net_device *dev)
753{
754 struct net_local *lp = netdev_priv(dev);
755 long ioaddr = dev->base_addr;
756 struct rx_header rx_head;
757
758
759 outb(EOC+MAR, ioaddr + PAR_DATA);
760 read_block(ioaddr, 8, (unsigned char*)&rx_head, dev->if_port);
761 if (net_debug > 5)
762 printk(KERN_DEBUG " rx_count %04x %04x %04x %04x..", rx_head.pad,
763 rx_head.rx_count, rx_head.rx_status, rx_head.cur_addr);
764 if ((rx_head.rx_status & 0x77) != 0x01) {
765 dev->stats.rx_errors++;
766 if (rx_head.rx_status & 0x0004) dev->stats.rx_frame_errors++;
767 else if (rx_head.rx_status & 0x0002) dev->stats.rx_crc_errors++;
768 if (net_debug > 3)
769 printk(KERN_DEBUG "%s: Unknown ATP Rx error %04x.\n",
770 dev->name, rx_head.rx_status);
771 if (rx_head.rx_status & 0x0020) {
772 dev->stats.rx_fifo_errors++;
773 write_reg_high(ioaddr, CMR1, CMR1h_TxENABLE);
774 write_reg_high(ioaddr, CMR1, CMR1h_RxENABLE | CMR1h_TxENABLE);
775 } else if (rx_head.rx_status & 0x0050)
776 hardware_init(dev);
777 return;
778 } else {
779
780 int pkt_len = (rx_head.rx_count & 0x7ff) - 4;
781 struct sk_buff *skb;
782
783 skb = netdev_alloc_skb(dev, pkt_len + 2);
784 if (skb == NULL) {
785 dev->stats.rx_dropped++;
786 goto done;
787 }
788
789 skb_reserve(skb, 2);
790 read_block(ioaddr, pkt_len, skb_put(skb,pkt_len), dev->if_port);
791 skb->protocol = eth_type_trans(skb, dev);
792 netif_rx(skb);
793 dev->last_rx = jiffies;
794 dev->stats.rx_packets++;
795 dev->stats.rx_bytes += pkt_len;
796 }
797 done:
798 write_reg(ioaddr, CMR1, CMR1_NextPkt);
799 lp->last_rx_time = jiffies;
800}
801
802static void read_block(long ioaddr, int length, unsigned char *p, int data_mode)
803{
804 if (data_mode <= 3) {
805 outb(Ctrl_LNibRead, ioaddr + PAR_CONTROL);
806 outb(length == 8 ? RdAddr | HNib | MAR : RdAddr | MAR,
807 ioaddr + PAR_DATA);
808 if (data_mode <= 1) {
809 do { *p++ = read_byte_mode0(ioaddr); } while (--length > 0);
810 } else {
811 do { *p++ = read_byte_mode2(ioaddr); } while (--length > 0);
812 }
813 } else if (data_mode <= 5) {
814 do { *p++ = read_byte_mode4(ioaddr); } while (--length > 0);
815 } else {
816 do { *p++ = read_byte_mode6(ioaddr); } while (--length > 0);
817 }
818
819 outb(EOC+HNib+MAR, ioaddr + PAR_DATA);
820 outb(Ctrl_SelData, ioaddr + PAR_CONTROL);
821}
822
823
824static int
825net_close(struct net_device *dev)
826{
827 struct net_local *lp = netdev_priv(dev);
828 long ioaddr = dev->base_addr;
829
830 netif_stop_queue(dev);
831
832 del_timer_sync(&lp->timer);
833
834
835 lp->addr_mode = CMR2h_OFF;
836 write_reg_high(ioaddr, CMR2, CMR2h_OFF);
837
838
839 outb(0x00, ioaddr + PAR_CONTROL);
840 free_irq(dev->irq, dev);
841
842
843 write_reg_high(ioaddr, CMR1, CMR1h_RESET | CMR1h_MUX);
844 return 0;
845}
846
847
848
849
850
851static void set_rx_mode(struct net_device *dev)
852{
853 struct net_local *lp = netdev_priv(dev);
854 long ioaddr = dev->base_addr;
855
856 if (!netdev_mc_empty(dev) || (dev->flags & (IFF_ALLMULTI|IFF_PROMISC)))
857 lp->addr_mode = CMR2h_PROMISC;
858 else
859 lp->addr_mode = CMR2h_Normal;
860 write_reg_high(ioaddr, CMR2, lp->addr_mode);
861}
862
863static int __init atp_init_module(void) {
864 if (debug)
865 printk(KERN_INFO "%s", version);
866 return atp_init();
867}
868
869static void __exit atp_cleanup_module(void) {
870 struct net_device *next_dev;
871
872 while (root_atp_dev) {
873 struct net_local *atp_local = netdev_priv(root_atp_dev);
874 next_dev = atp_local->next_module;
875 unregister_netdev(root_atp_dev);
876
877 free_netdev(root_atp_dev);
878 root_atp_dev = next_dev;
879 }
880}
881
882module_init(atp_init_module);
883module_exit(atp_cleanup_module);
884