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17#ifndef _HAL_H_
18#define _HAL_H_
19
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32
33
34#define WCN36XX_HAL_VER_MAJOR 1
35#define WCN36XX_HAL_VER_MINOR 4
36#define WCN36XX_HAL_VER_VERSION 1
37#define WCN36XX_HAL_VER_REVISION 2
38
39
40#define WCN36XX_HAL_MAX_ENUM_SIZE 0x7FFFFFFF
41#define WCN36XX_HAL_MSG_TYPE_MAX_ENUM_SIZE 0x7FFF
42
43
44#define STACFG_MAX_TC 8
45
46
47#define WCN36XX_HAL_MAX_AC 4
48
49#define WCN36XX_HAL_IPV4_ADDR_LEN 4
50
51#define WCN36XX_HAL_STA_INVALID_IDX 0xFF
52#define WCN36XX_HAL_BSS_INVALID_IDX 0xFF
53
54
55#define BEACON_TEMPLATE_SIZE 0x180
56
57
58#define TIM_MIN_PVM_SIZE 6
59
60
61#define PARAM_BCN_INTERVAL_CHANGED (1 << 0)
62#define PARAM_SHORT_PREAMBLE_CHANGED (1 << 1)
63#define PARAM_SHORT_SLOT_TIME_CHANGED (1 << 2)
64#define PARAM_llACOEXIST_CHANGED (1 << 3)
65#define PARAM_llBCOEXIST_CHANGED (1 << 4)
66#define PARAM_llGCOEXIST_CHANGED (1 << 5)
67#define PARAM_HT20MHZCOEXIST_CHANGED (1<<6)
68#define PARAM_NON_GF_DEVICES_PRESENT_CHANGED (1<<7)
69#define PARAM_RIFS_MODE_CHANGED (1<<8)
70#define PARAM_LSIG_TXOP_FULL_SUPPORT_CHANGED (1<<9)
71#define PARAM_OBSS_MODE_CHANGED (1<<10)
72#define PARAM_BEACON_UPDATE_MASK \
73 (PARAM_BCN_INTERVAL_CHANGED | \
74 PARAM_SHORT_PREAMBLE_CHANGED | \
75 PARAM_SHORT_SLOT_TIME_CHANGED | \
76 PARAM_llACOEXIST_CHANGED | \
77 PARAM_llBCOEXIST_CHANGED | \
78 PARAM_llGCOEXIST_CHANGED | \
79 PARAM_HT20MHZCOEXIST_CHANGED | \
80 PARAM_NON_GF_DEVICES_PRESENT_CHANGED | \
81 PARAM_RIFS_MODE_CHANGED | \
82 PARAM_LSIG_TXOP_FULL_SUPPORT_CHANGED | \
83 PARAM_OBSS_MODE_CHANGED)
84
85
86#define DUMPCMD_RSP_BUFFER 100
87
88
89#define WCN36XX_HAL_VERSION_LENGTH 64
90
91
92enum wcn36xx_hal_host_msg_type {
93
94 WCN36XX_HAL_START_REQ = 0,
95 WCN36XX_HAL_START_RSP = 1,
96 WCN36XX_HAL_STOP_REQ = 2,
97 WCN36XX_HAL_STOP_RSP = 3,
98
99
100 WCN36XX_HAL_INIT_SCAN_REQ = 4,
101 WCN36XX_HAL_INIT_SCAN_RSP = 5,
102 WCN36XX_HAL_START_SCAN_REQ = 6,
103 WCN36XX_HAL_START_SCAN_RSP = 7,
104 WCN36XX_HAL_END_SCAN_REQ = 8,
105 WCN36XX_HAL_END_SCAN_RSP = 9,
106 WCN36XX_HAL_FINISH_SCAN_REQ = 10,
107 WCN36XX_HAL_FINISH_SCAN_RSP = 11,
108
109
110 WCN36XX_HAL_CONFIG_STA_REQ = 12,
111 WCN36XX_HAL_CONFIG_STA_RSP = 13,
112 WCN36XX_HAL_DELETE_STA_REQ = 14,
113 WCN36XX_HAL_DELETE_STA_RSP = 15,
114 WCN36XX_HAL_CONFIG_BSS_REQ = 16,
115 WCN36XX_HAL_CONFIG_BSS_RSP = 17,
116 WCN36XX_HAL_DELETE_BSS_REQ = 18,
117 WCN36XX_HAL_DELETE_BSS_RSP = 19,
118
119
120 WCN36XX_HAL_JOIN_REQ = 20,
121 WCN36XX_HAL_JOIN_RSP = 21,
122 WCN36XX_HAL_POST_ASSOC_REQ = 22,
123 WCN36XX_HAL_POST_ASSOC_RSP = 23,
124
125
126 WCN36XX_HAL_SET_BSSKEY_REQ = 24,
127 WCN36XX_HAL_SET_BSSKEY_RSP = 25,
128 WCN36XX_HAL_SET_STAKEY_REQ = 26,
129 WCN36XX_HAL_SET_STAKEY_RSP = 27,
130 WCN36XX_HAL_RMV_BSSKEY_REQ = 28,
131 WCN36XX_HAL_RMV_BSSKEY_RSP = 29,
132 WCN36XX_HAL_RMV_STAKEY_REQ = 30,
133 WCN36XX_HAL_RMV_STAKEY_RSP = 31,
134
135
136 WCN36XX_HAL_ADD_TS_REQ = 32,
137 WCN36XX_HAL_ADD_TS_RSP = 33,
138 WCN36XX_HAL_DEL_TS_REQ = 34,
139 WCN36XX_HAL_DEL_TS_RSP = 35,
140 WCN36XX_HAL_UPD_EDCA_PARAMS_REQ = 36,
141 WCN36XX_HAL_UPD_EDCA_PARAMS_RSP = 37,
142 WCN36XX_HAL_ADD_BA_REQ = 38,
143 WCN36XX_HAL_ADD_BA_RSP = 39,
144 WCN36XX_HAL_DEL_BA_REQ = 40,
145 WCN36XX_HAL_DEL_BA_RSP = 41,
146
147 WCN36XX_HAL_CH_SWITCH_REQ = 42,
148 WCN36XX_HAL_CH_SWITCH_RSP = 43,
149 WCN36XX_HAL_SET_LINK_ST_REQ = 44,
150 WCN36XX_HAL_SET_LINK_ST_RSP = 45,
151 WCN36XX_HAL_GET_STATS_REQ = 46,
152 WCN36XX_HAL_GET_STATS_RSP = 47,
153 WCN36XX_HAL_UPDATE_CFG_REQ = 48,
154 WCN36XX_HAL_UPDATE_CFG_RSP = 49,
155
156 WCN36XX_HAL_MISSED_BEACON_IND = 50,
157 WCN36XX_HAL_UNKNOWN_ADDR2_FRAME_RX_IND = 51,
158 WCN36XX_HAL_MIC_FAILURE_IND = 52,
159 WCN36XX_HAL_FATAL_ERROR_IND = 53,
160 WCN36XX_HAL_SET_KEYDONE_MSG = 54,
161
162
163 WCN36XX_HAL_DOWNLOAD_NV_REQ = 55,
164 WCN36XX_HAL_DOWNLOAD_NV_RSP = 56,
165
166 WCN36XX_HAL_ADD_BA_SESSION_REQ = 57,
167 WCN36XX_HAL_ADD_BA_SESSION_RSP = 58,
168 WCN36XX_HAL_TRIGGER_BA_REQ = 59,
169 WCN36XX_HAL_TRIGGER_BA_RSP = 60,
170 WCN36XX_HAL_UPDATE_BEACON_REQ = 61,
171 WCN36XX_HAL_UPDATE_BEACON_RSP = 62,
172 WCN36XX_HAL_SEND_BEACON_REQ = 63,
173 WCN36XX_HAL_SEND_BEACON_RSP = 64,
174
175 WCN36XX_HAL_SET_BCASTKEY_REQ = 65,
176 WCN36XX_HAL_SET_BCASTKEY_RSP = 66,
177 WCN36XX_HAL_DELETE_STA_CONTEXT_IND = 67,
178 WCN36XX_HAL_UPDATE_PROBE_RSP_TEMPLATE_REQ = 68,
179 WCN36XX_HAL_UPDATE_PROBE_RSP_TEMPLATE_RSP = 69,
180
181
182 WCN36XX_HAL_PROCESS_PTT_REQ = 70,
183 WCN36XX_HAL_PROCESS_PTT_RSP = 71,
184
185
186 WCN36XX_HAL_SIGNAL_BTAMP_EVENT_REQ = 72,
187 WCN36XX_HAL_SIGNAL_BTAMP_EVENT_RSP = 73,
188 WCN36XX_HAL_TL_HAL_FLUSH_AC_REQ = 74,
189 WCN36XX_HAL_TL_HAL_FLUSH_AC_RSP = 75,
190
191 WCN36XX_HAL_ENTER_IMPS_REQ = 76,
192 WCN36XX_HAL_EXIT_IMPS_REQ = 77,
193 WCN36XX_HAL_ENTER_BMPS_REQ = 78,
194 WCN36XX_HAL_EXIT_BMPS_REQ = 79,
195 WCN36XX_HAL_ENTER_UAPSD_REQ = 80,
196 WCN36XX_HAL_EXIT_UAPSD_REQ = 81,
197 WCN36XX_HAL_UPDATE_UAPSD_PARAM_REQ = 82,
198 WCN36XX_HAL_CONFIGURE_RXP_FILTER_REQ = 83,
199 WCN36XX_HAL_ADD_BCN_FILTER_REQ = 84,
200 WCN36XX_HAL_REM_BCN_FILTER_REQ = 85,
201 WCN36XX_HAL_ADD_WOWL_BCAST_PTRN = 86,
202 WCN36XX_HAL_DEL_WOWL_BCAST_PTRN = 87,
203 WCN36XX_HAL_ENTER_WOWL_REQ = 88,
204 WCN36XX_HAL_EXIT_WOWL_REQ = 89,
205 WCN36XX_HAL_HOST_OFFLOAD_REQ = 90,
206 WCN36XX_HAL_SET_RSSI_THRESH_REQ = 91,
207 WCN36XX_HAL_GET_RSSI_REQ = 92,
208 WCN36XX_HAL_SET_UAPSD_AC_PARAMS_REQ = 93,
209 WCN36XX_HAL_CONFIGURE_APPS_CPU_WAKEUP_STATE_REQ = 94,
210
211 WCN36XX_HAL_ENTER_IMPS_RSP = 95,
212 WCN36XX_HAL_EXIT_IMPS_RSP = 96,
213 WCN36XX_HAL_ENTER_BMPS_RSP = 97,
214 WCN36XX_HAL_EXIT_BMPS_RSP = 98,
215 WCN36XX_HAL_ENTER_UAPSD_RSP = 99,
216 WCN36XX_HAL_EXIT_UAPSD_RSP = 100,
217 WCN36XX_HAL_SET_UAPSD_AC_PARAMS_RSP = 101,
218 WCN36XX_HAL_UPDATE_UAPSD_PARAM_RSP = 102,
219 WCN36XX_HAL_CONFIGURE_RXP_FILTER_RSP = 103,
220 WCN36XX_HAL_ADD_BCN_FILTER_RSP = 104,
221 WCN36XX_HAL_REM_BCN_FILTER_RSP = 105,
222 WCN36XX_HAL_SET_RSSI_THRESH_RSP = 106,
223 WCN36XX_HAL_HOST_OFFLOAD_RSP = 107,
224 WCN36XX_HAL_ADD_WOWL_BCAST_PTRN_RSP = 108,
225 WCN36XX_HAL_DEL_WOWL_BCAST_PTRN_RSP = 109,
226 WCN36XX_HAL_ENTER_WOWL_RSP = 110,
227 WCN36XX_HAL_EXIT_WOWL_RSP = 111,
228 WCN36XX_HAL_RSSI_NOTIFICATION_IND = 112,
229 WCN36XX_HAL_GET_RSSI_RSP = 113,
230 WCN36XX_HAL_CONFIGURE_APPS_CPU_WAKEUP_STATE_RSP = 114,
231
232
233 WCN36XX_HAL_SET_MAX_TX_POWER_REQ = 115,
234 WCN36XX_HAL_SET_MAX_TX_POWER_RSP = 116,
235
236
237 WCN36XX_HAL_AGGR_ADD_TS_REQ = 117,
238 WCN36XX_HAL_AGGR_ADD_TS_RSP = 118,
239
240
241 WCN36XX_HAL_SET_P2P_GONOA_REQ = 119,
242 WCN36XX_HAL_SET_P2P_GONOA_RSP = 120,
243
244
245 WCN36XX_HAL_DUMP_COMMAND_REQ = 121,
246 WCN36XX_HAL_DUMP_COMMAND_RSP = 122,
247
248
249 WCN36XX_HAL_START_OEM_DATA_REQ = 123,
250 WCN36XX_HAL_START_OEM_DATA_RSP = 124,
251
252
253 WCN36XX_HAL_ADD_STA_SELF_REQ = 125,
254 WCN36XX_HAL_ADD_STA_SELF_RSP = 126,
255
256
257 WCN36XX_HAL_DEL_STA_SELF_REQ = 127,
258 WCN36XX_HAL_DEL_STA_SELF_RSP = 128,
259
260
261 WCN36XX_HAL_COEX_IND = 129,
262
263
264 WCN36XX_HAL_OTA_TX_COMPL_IND = 130,
265
266
267 WCN36XX_HAL_HOST_SUSPEND_IND = 131,
268 WCN36XX_HAL_HOST_RESUME_REQ = 132,
269 WCN36XX_HAL_HOST_RESUME_RSP = 133,
270
271 WCN36XX_HAL_SET_TX_POWER_REQ = 134,
272 WCN36XX_HAL_SET_TX_POWER_RSP = 135,
273 WCN36XX_HAL_GET_TX_POWER_REQ = 136,
274 WCN36XX_HAL_GET_TX_POWER_RSP = 137,
275
276 WCN36XX_HAL_P2P_NOA_ATTR_IND = 138,
277
278 WCN36XX_HAL_ENABLE_RADAR_DETECT_REQ = 139,
279 WCN36XX_HAL_ENABLE_RADAR_DETECT_RSP = 140,
280 WCN36XX_HAL_GET_TPC_REPORT_REQ = 141,
281 WCN36XX_HAL_GET_TPC_REPORT_RSP = 142,
282 WCN36XX_HAL_RADAR_DETECT_IND = 143,
283 WCN36XX_HAL_RADAR_DETECT_INTR_IND = 144,
284 WCN36XX_HAL_KEEP_ALIVE_REQ = 145,
285 WCN36XX_HAL_KEEP_ALIVE_RSP = 146,
286
287
288 WCN36XX_HAL_SET_PREF_NETWORK_REQ = 147,
289 WCN36XX_HAL_SET_PREF_NETWORK_RSP = 148,
290 WCN36XX_HAL_SET_RSSI_FILTER_REQ = 149,
291 WCN36XX_HAL_SET_RSSI_FILTER_RSP = 150,
292 WCN36XX_HAL_UPDATE_SCAN_PARAM_REQ = 151,
293 WCN36XX_HAL_UPDATE_SCAN_PARAM_RSP = 152,
294 WCN36XX_HAL_PREF_NETW_FOUND_IND = 153,
295
296 WCN36XX_HAL_SET_TX_PER_TRACKING_REQ = 154,
297 WCN36XX_HAL_SET_TX_PER_TRACKING_RSP = 155,
298 WCN36XX_HAL_TX_PER_HIT_IND = 156,
299
300 WCN36XX_HAL_8023_MULTICAST_LIST_REQ = 157,
301 WCN36XX_HAL_8023_MULTICAST_LIST_RSP = 158,
302
303 WCN36XX_HAL_SET_PACKET_FILTER_REQ = 159,
304 WCN36XX_HAL_SET_PACKET_FILTER_RSP = 160,
305 WCN36XX_HAL_PACKET_FILTER_MATCH_COUNT_REQ = 161,
306 WCN36XX_HAL_PACKET_FILTER_MATCH_COUNT_RSP = 162,
307 WCN36XX_HAL_CLEAR_PACKET_FILTER_REQ = 163,
308 WCN36XX_HAL_CLEAR_PACKET_FILTER_RSP = 164,
309
310
311
312
313
314 WCN36XX_HAL_INIT_SCAN_CON_REQ = 165,
315
316 WCN36XX_HAL_SET_POWER_PARAMS_REQ = 166,
317 WCN36XX_HAL_SET_POWER_PARAMS_RSP = 167,
318
319 WCN36XX_HAL_TSM_STATS_REQ = 168,
320 WCN36XX_HAL_TSM_STATS_RSP = 169,
321
322
323 WCN36XX_HAL_WAKE_REASON_IND = 170,
324
325
326 WCN36XX_HAL_GTK_OFFLOAD_REQ = 171,
327 WCN36XX_HAL_GTK_OFFLOAD_RSP = 172,
328 WCN36XX_HAL_GTK_OFFLOAD_GETINFO_REQ = 173,
329 WCN36XX_HAL_GTK_OFFLOAD_GETINFO_RSP = 174,
330
331 WCN36XX_HAL_FEATURE_CAPS_EXCHANGE_REQ = 175,
332 WCN36XX_HAL_FEATURE_CAPS_EXCHANGE_RSP = 176,
333 WCN36XX_HAL_EXCLUDE_UNENCRYPTED_IND = 177,
334
335 WCN36XX_HAL_SET_THERMAL_MITIGATION_REQ = 178,
336 WCN36XX_HAL_SET_THERMAL_MITIGATION_RSP = 179,
337
338 WCN36XX_HAL_UPDATE_VHT_OP_MODE_REQ = 182,
339 WCN36XX_HAL_UPDATE_VHT_OP_MODE_RSP = 183,
340
341 WCN36XX_HAL_P2P_NOA_START_IND = 184,
342
343 WCN36XX_HAL_GET_ROAM_RSSI_REQ = 185,
344 WCN36XX_HAL_GET_ROAM_RSSI_RSP = 186,
345
346 WCN36XX_HAL_CLASS_B_STATS_IND = 187,
347 WCN36XX_HAL_DEL_BA_IND = 188,
348 WCN36XX_HAL_DHCP_START_IND = 189,
349 WCN36XX_HAL_DHCP_STOP_IND = 190,
350
351 WCN36XX_HAL_AVOID_FREQ_RANGE_IND = 233,
352
353 WCN36XX_HAL_MSG_MAX = WCN36XX_HAL_MSG_TYPE_MAX_ENUM_SIZE
354};
355
356
357enum wcn36xx_hal_host_msg_version {
358 WCN36XX_HAL_MSG_VERSION0 = 0,
359 WCN36XX_HAL_MSG_VERSION1 = 1,
360
361 WCN36XX_HAL_MSG_WCNSS_CTRL_VERSION = 0x7FFF,
362 WCN36XX_HAL_MSG_VERSION_MAX_FIELD = WCN36XX_HAL_MSG_WCNSS_CTRL_VERSION
363};
364
365enum driver_type {
366 DRIVER_TYPE_PRODUCTION = 0,
367 DRIVER_TYPE_MFG = 1,
368 DRIVER_TYPE_DVT = 2,
369 DRIVER_TYPE_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
370};
371
372enum wcn36xx_hal_stop_type {
373 HAL_STOP_TYPE_SYS_RESET,
374 HAL_STOP_TYPE_SYS_DEEP_SLEEP,
375 HAL_STOP_TYPE_RF_KILL,
376 HAL_STOP_TYPE_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
377};
378
379enum wcn36xx_hal_sys_mode {
380 HAL_SYS_MODE_NORMAL,
381 HAL_SYS_MODE_LEARN,
382 HAL_SYS_MODE_SCAN,
383 HAL_SYS_MODE_PROMISC,
384 HAL_SYS_MODE_SUSPEND_LINK,
385 HAL_SYS_MODE_ROAM_SCAN,
386 HAL_SYS_MODE_ROAM_SUSPEND_LINK,
387 HAL_SYS_MODE_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
388};
389
390enum phy_chan_bond_state {
391
392 PHY_SINGLE_CHANNEL_CENTERED = 0,
393
394
395 PHY_DOUBLE_CHANNEL_LOW_PRIMARY = 1,
396
397
398 PHY_DOUBLE_CHANNEL_CENTERED = 2,
399
400
401 PHY_DOUBLE_CHANNEL_HIGH_PRIMARY = 3,
402
403
404 PHY_QUADRUPLE_CHANNEL_20MHZ_LOW_40MHZ_CENTERED = 4,
405
406
407 PHY_QUADRUPLE_CHANNEL_20MHZ_CENTERED_40MHZ_CENTERED = 5,
408
409
410 PHY_QUADRUPLE_CHANNEL_20MHZ_HIGH_40MHZ_CENTERED = 6,
411
412
413 PHY_QUADRUPLE_CHANNEL_20MHZ_LOW_40MHZ_LOW = 7,
414
415
416 PHY_QUADRUPLE_CHANNEL_20MHZ_HIGH_40MHZ_LOW = 8,
417
418
419 PHY_QUADRUPLE_CHANNEL_20MHZ_LOW_40MHZ_HIGH = 9,
420
421
422 PHY_QUADRUPLE_CHANNEL_20MHZ_HIGH_40MHZ_HIGH = 10,
423
424 PHY_CHANNEL_BONDING_STATE_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
425};
426
427
428enum wcn36xx_hal_ht_mimo_state {
429
430 WCN36XX_HAL_HT_MIMO_PS_STATIC = 0,
431
432
433 WCN36XX_HAL_HT_MIMO_PS_DYNAMIC = 1,
434
435
436 WCN36XX_HAL_HT_MIMO_PS_NA = 2,
437
438
439 WCN36XX_HAL_HT_MIMO_PS_NO_LIMIT = 3,
440
441 WCN36XX_HAL_HT_MIMO_PS_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
442};
443
444
445enum sta_rate_mode {
446 STA_TAURUS = 0,
447 STA_TITAN,
448 STA_POLARIS,
449 STA_11b,
450 STA_11bg,
451 STA_11a,
452 STA_11n,
453 STA_11ac,
454 STA_INVALID_RATE_MODE = WCN36XX_HAL_MAX_ENUM_SIZE
455};
456
457
458#define WCN36XX_HAL_NUM_DSSS_RATES 4
459
460
461#define WCN36XX_HAL_NUM_OFDM_RATES 8
462
463
464#define WCN36XX_HAL_NUM_POLARIS_RATES 3
465
466#define WCN36XX_HAL_MAC_MAX_SUPPORTED_MCS_SET 16
467
468enum wcn36xx_hal_bss_type {
469 WCN36XX_HAL_INFRASTRUCTURE_MODE,
470
471
472 WCN36XX_HAL_INFRA_AP_MODE,
473
474 WCN36XX_HAL_IBSS_MODE,
475
476
477 WCN36XX_HAL_BTAMP_STA_MODE,
478
479
480 WCN36XX_HAL_BTAMP_AP_MODE,
481
482 WCN36XX_HAL_AUTO_MODE,
483
484 WCN36XX_HAL_DONOT_USE_BSS_TYPE = WCN36XX_HAL_MAX_ENUM_SIZE
485};
486
487enum wcn36xx_hal_nw_type {
488 WCN36XX_HAL_11A_NW_TYPE,
489 WCN36XX_HAL_11B_NW_TYPE,
490 WCN36XX_HAL_11G_NW_TYPE,
491 WCN36XX_HAL_11N_NW_TYPE,
492 WCN36XX_HAL_DONOT_USE_NW_TYPE = WCN36XX_HAL_MAX_ENUM_SIZE
493};
494
495#define WCN36XX_HAL_MAC_RATESET_EID_MAX 12
496
497enum wcn36xx_hal_ht_operating_mode {
498
499 WCN36XX_HAL_HT_OP_MODE_PURE,
500
501
502 WCN36XX_HAL_HT_OP_MODE_OVERLAP_LEGACY,
503
504
505 WCN36XX_HAL_HT_OP_MODE_NO_LEGACY_20MHZ_HT,
506
507
508 WCN36XX_HAL_HT_OP_MODE_MIXED,
509
510 WCN36XX_HAL_HT_OP_MODE_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
511};
512
513
514enum ani_ed_type {
515 WCN36XX_HAL_ED_NONE,
516 WCN36XX_HAL_ED_WEP40,
517 WCN36XX_HAL_ED_WEP104,
518 WCN36XX_HAL_ED_TKIP,
519 WCN36XX_HAL_ED_CCMP,
520 WCN36XX_HAL_ED_WPI,
521 WCN36XX_HAL_ED_AES_128_CMAC,
522 WCN36XX_HAL_ED_NOT_IMPLEMENTED = WCN36XX_HAL_MAX_ENUM_SIZE
523};
524
525#define WLAN_MAX_KEY_RSC_LEN 16
526#define WLAN_WAPI_KEY_RSC_LEN 16
527
528
529#define WCN36XX_HAL_MAC_MAX_KEY_LENGTH 32
530#define WCN36XX_HAL_MAC_MAX_NUM_OF_DEFAULT_KEYS 4
531
532
533
534
535enum ani_key_direction {
536 WCN36XX_HAL_TX_ONLY,
537 WCN36XX_HAL_RX_ONLY,
538 WCN36XX_HAL_TX_RX,
539 WCN36XX_HAL_TX_DEFAULT,
540 WCN36XX_HAL_DONOT_USE_KEY_DIRECTION = WCN36XX_HAL_MAX_ENUM_SIZE
541};
542
543enum ani_wep_type {
544 WCN36XX_HAL_WEP_STATIC,
545 WCN36XX_HAL_WEP_DYNAMIC,
546 WCN36XX_HAL_WEP_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
547};
548
549enum wcn36xx_hal_link_state {
550
551 WCN36XX_HAL_LINK_IDLE_STATE = 0,
552 WCN36XX_HAL_LINK_PREASSOC_STATE = 1,
553 WCN36XX_HAL_LINK_POSTASSOC_STATE = 2,
554 WCN36XX_HAL_LINK_AP_STATE = 3,
555 WCN36XX_HAL_LINK_IBSS_STATE = 4,
556
557
558 WCN36XX_HAL_LINK_BTAMP_PREASSOC_STATE = 5,
559 WCN36XX_HAL_LINK_BTAMP_POSTASSOC_STATE = 6,
560 WCN36XX_HAL_LINK_BTAMP_AP_STATE = 7,
561 WCN36XX_HAL_LINK_BTAMP_STA_STATE = 8,
562
563
564 WCN36XX_HAL_LINK_LEARN_STATE = 9,
565 WCN36XX_HAL_LINK_SCAN_STATE = 10,
566 WCN36XX_HAL_LINK_FINISH_SCAN_STATE = 11,
567 WCN36XX_HAL_LINK_INIT_CAL_STATE = 12,
568 WCN36XX_HAL_LINK_FINISH_CAL_STATE = 13,
569 WCN36XX_HAL_LINK_LISTEN_STATE = 14,
570
571 WCN36XX_HAL_LINK_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
572};
573
574enum wcn36xx_hal_stats_mask {
575 HAL_SUMMARY_STATS_INFO = 0x00000001,
576 HAL_GLOBAL_CLASS_A_STATS_INFO = 0x00000002,
577 HAL_GLOBAL_CLASS_B_STATS_INFO = 0x00000004,
578 HAL_GLOBAL_CLASS_C_STATS_INFO = 0x00000008,
579 HAL_GLOBAL_CLASS_D_STATS_INFO = 0x00000010,
580 HAL_PER_STA_STATS_INFO = 0x00000020
581};
582
583
584enum bt_amp_event_type {
585 BTAMP_EVENT_CONNECTION_START,
586 BTAMP_EVENT_CONNECTION_STOP,
587 BTAMP_EVENT_CONNECTION_TERMINATED,
588
589
590 BTAMP_EVENT_TYPE_MAX = WCN36XX_HAL_MAX_ENUM_SIZE,
591};
592
593
594enum pe_stats_mask {
595 PE_SUMMARY_STATS_INFO = 0x00000001,
596 PE_GLOBAL_CLASS_A_STATS_INFO = 0x00000002,
597 PE_GLOBAL_CLASS_B_STATS_INFO = 0x00000004,
598 PE_GLOBAL_CLASS_C_STATS_INFO = 0x00000008,
599 PE_GLOBAL_CLASS_D_STATS_INFO = 0x00000010,
600 PE_PER_STA_STATS_INFO = 0x00000020,
601
602
603 PE_STATS_TYPE_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
604};
605
606
607
608
609#define WCN36XX_HAL_CFG_STA_ID 0
610#define WCN36XX_HAL_CFG_CURRENT_TX_ANTENNA 1
611#define WCN36XX_HAL_CFG_CURRENT_RX_ANTENNA 2
612#define WCN36XX_HAL_CFG_LOW_GAIN_OVERRIDE 3
613#define WCN36XX_HAL_CFG_POWER_STATE_PER_CHAIN 4
614#define WCN36XX_HAL_CFG_CAL_PERIOD 5
615#define WCN36XX_HAL_CFG_CAL_CONTROL 6
616#define WCN36XX_HAL_CFG_PROXIMITY 7
617#define WCN36XX_HAL_CFG_NETWORK_DENSITY 8
618#define WCN36XX_HAL_CFG_MAX_MEDIUM_TIME 9
619#define WCN36XX_HAL_CFG_MAX_MPDUS_IN_AMPDU 10
620#define WCN36XX_HAL_CFG_RTS_THRESHOLD 11
621#define WCN36XX_HAL_CFG_SHORT_RETRY_LIMIT 12
622#define WCN36XX_HAL_CFG_LONG_RETRY_LIMIT 13
623#define WCN36XX_HAL_CFG_FRAGMENTATION_THRESHOLD 14
624#define WCN36XX_HAL_CFG_DYNAMIC_THRESHOLD_ZERO 15
625#define WCN36XX_HAL_CFG_DYNAMIC_THRESHOLD_ONE 16
626#define WCN36XX_HAL_CFG_DYNAMIC_THRESHOLD_TWO 17
627#define WCN36XX_HAL_CFG_FIXED_RATE 18
628#define WCN36XX_HAL_CFG_RETRYRATE_POLICY 19
629#define WCN36XX_HAL_CFG_RETRYRATE_SECONDARY 20
630#define WCN36XX_HAL_CFG_RETRYRATE_TERTIARY 21
631#define WCN36XX_HAL_CFG_FORCE_POLICY_PROTECTION 22
632#define WCN36XX_HAL_CFG_FIXED_RATE_MULTICAST_24GHZ 23
633#define WCN36XX_HAL_CFG_FIXED_RATE_MULTICAST_5GHZ 24
634#define WCN36XX_HAL_CFG_DEFAULT_RATE_INDEX_24GHZ 25
635#define WCN36XX_HAL_CFG_DEFAULT_RATE_INDEX_5GHZ 26
636#define WCN36XX_HAL_CFG_MAX_BA_SESSIONS 27
637#define WCN36XX_HAL_CFG_PS_DATA_INACTIVITY_TIMEOUT 28
638#define WCN36XX_HAL_CFG_PS_ENABLE_BCN_FILTER 29
639#define WCN36XX_HAL_CFG_PS_ENABLE_RSSI_MONITOR 30
640#define WCN36XX_HAL_CFG_NUM_BEACON_PER_RSSI_AVERAGE 31
641#define WCN36XX_HAL_CFG_STATS_PERIOD 32
642#define WCN36XX_HAL_CFG_CFP_MAX_DURATION 33
643#define WCN36XX_HAL_CFG_FRAME_TRANS_ENABLED 34
644#define WCN36XX_HAL_CFG_DTIM_PERIOD 35
645#define WCN36XX_HAL_CFG_EDCA_WMM_ACBK 36
646#define WCN36XX_HAL_CFG_EDCA_WMM_ACBE 37
647#define WCN36XX_HAL_CFG_EDCA_WMM_ACVO 38
648#define WCN36XX_HAL_CFG_EDCA_WMM_ACVI 39
649#define WCN36XX_HAL_CFG_BA_THRESHOLD_HIGH 40
650#define WCN36XX_HAL_CFG_MAX_BA_BUFFERS 41
651#define WCN36XX_HAL_CFG_RPE_POLLING_THRESHOLD 42
652#define WCN36XX_HAL_CFG_RPE_AGING_THRESHOLD_FOR_AC0_REG 43
653#define WCN36XX_HAL_CFG_RPE_AGING_THRESHOLD_FOR_AC1_REG 44
654#define WCN36XX_HAL_CFG_RPE_AGING_THRESHOLD_FOR_AC2_REG 45
655#define WCN36XX_HAL_CFG_RPE_AGING_THRESHOLD_FOR_AC3_REG 46
656#define WCN36XX_HAL_CFG_NO_OF_ONCHIP_REORDER_SESSIONS 47
657#define WCN36XX_HAL_CFG_PS_LISTEN_INTERVAL 48
658#define WCN36XX_HAL_CFG_PS_HEART_BEAT_THRESHOLD 49
659#define WCN36XX_HAL_CFG_PS_NTH_BEACON_FILTER 50
660#define WCN36XX_HAL_CFG_PS_MAX_PS_POLL 51
661#define WCN36XX_HAL_CFG_PS_MIN_RSSI_THRESHOLD 52
662#define WCN36XX_HAL_CFG_PS_RSSI_FILTER_PERIOD 53
663#define WCN36XX_HAL_CFG_PS_BROADCAST_FRAME_FILTER_ENABLE 54
664#define WCN36XX_HAL_CFG_PS_IGNORE_DTIM 55
665#define WCN36XX_HAL_CFG_PS_ENABLE_BCN_EARLY_TERM 56
666#define WCN36XX_HAL_CFG_DYNAMIC_PS_POLL_VALUE 57
667#define WCN36XX_HAL_CFG_PS_NULLDATA_AP_RESP_TIMEOUT 58
668#define WCN36XX_HAL_CFG_TELE_BCN_WAKEUP_EN 59
669#define WCN36XX_HAL_CFG_TELE_BCN_TRANS_LI 60
670#define WCN36XX_HAL_CFG_TELE_BCN_TRANS_LI_IDLE_BCNS 61
671#define WCN36XX_HAL_CFG_TELE_BCN_MAX_LI 62
672#define WCN36XX_HAL_CFG_TELE_BCN_MAX_LI_IDLE_BCNS 63
673#define WCN36XX_HAL_CFG_TX_PWR_CTRL_ENABLE 64
674#define WCN36XX_HAL_CFG_VALID_RADAR_CHANNEL_LIST 65
675#define WCN36XX_HAL_CFG_TX_POWER_24_20 66
676#define WCN36XX_HAL_CFG_TX_POWER_24_40 67
677#define WCN36XX_HAL_CFG_TX_POWER_50_20 68
678#define WCN36XX_HAL_CFG_TX_POWER_50_40 69
679#define WCN36XX_HAL_CFG_MCAST_BCAST_FILTER_SETTING 70
680#define WCN36XX_HAL_CFG_BCN_EARLY_TERM_WAKEUP_INTERVAL 71
681#define WCN36XX_HAL_CFG_MAX_TX_POWER_2_4 72
682#define WCN36XX_HAL_CFG_MAX_TX_POWER_5 73
683#define WCN36XX_HAL_CFG_INFRA_STA_KEEP_ALIVE_PERIOD 74
684#define WCN36XX_HAL_CFG_ENABLE_CLOSE_LOOP 75
685#define WCN36XX_HAL_CFG_BTC_EXECUTION_MODE 76
686#define WCN36XX_HAL_CFG_BTC_DHCP_BT_SLOTS_TO_BLOCK 77
687#define WCN36XX_HAL_CFG_BTC_A2DP_DHCP_BT_SUB_INTERVALS 78
688#define WCN36XX_HAL_CFG_PS_TX_INACTIVITY_TIMEOUT 79
689#define WCN36XX_HAL_CFG_WCNSS_API_VERSION 80
690#define WCN36XX_HAL_CFG_AP_KEEPALIVE_TIMEOUT 81
691#define WCN36XX_HAL_CFG_GO_KEEPALIVE_TIMEOUT 82
692#define WCN36XX_HAL_CFG_ENABLE_MC_ADDR_LIST 83
693#define WCN36XX_HAL_CFG_BTC_STATIC_LEN_INQ_BT 84
694#define WCN36XX_HAL_CFG_BTC_STATIC_LEN_PAGE_BT 85
695#define WCN36XX_HAL_CFG_BTC_STATIC_LEN_CONN_BT 86
696#define WCN36XX_HAL_CFG_BTC_STATIC_LEN_LE_BT 87
697#define WCN36XX_HAL_CFG_BTC_STATIC_LEN_INQ_WLAN 88
698#define WCN36XX_HAL_CFG_BTC_STATIC_LEN_PAGE_WLAN 89
699#define WCN36XX_HAL_CFG_BTC_STATIC_LEN_CONN_WLAN 90
700#define WCN36XX_HAL_CFG_BTC_STATIC_LEN_LE_WLAN 91
701#define WCN36XX_HAL_CFG_BTC_DYN_MAX_LEN_BT 92
702#define WCN36XX_HAL_CFG_BTC_DYN_MAX_LEN_WLAN 93
703#define WCN36XX_HAL_CFG_BTC_MAX_SCO_BLOCK_PERC 94
704#define WCN36XX_HAL_CFG_BTC_DHCP_PROT_ON_A2DP 95
705#define WCN36XX_HAL_CFG_BTC_DHCP_PROT_ON_SCO 96
706#define WCN36XX_HAL_CFG_ENABLE_UNICAST_FILTER 97
707#define WCN36XX_HAL_CFG_MAX_ASSOC_LIMIT 98
708#define WCN36XX_HAL_CFG_ENABLE_LPWR_IMG_TRANSITION 99
709#define WCN36XX_HAL_CFG_ENABLE_MCC_ADAPTIVE_SCHEDULER 100
710#define WCN36XX_HAL_CFG_ENABLE_DETECT_PS_SUPPORT 101
711#define WCN36XX_HAL_CFG_AP_LINK_MONITOR_TIMEOUT 102
712#define WCN36XX_HAL_CFG_BTC_DWELL_TIME_MULTIPLIER 103
713#define WCN36XX_HAL_CFG_ENABLE_TDLS_OXYGEN_MODE 104
714#define WCN36XX_HAL_CFG_MAX_PARAMS 105
715
716
717
718
719struct wcnss_wlan_version {
720 u8 revision;
721 u8 version;
722 u8 minor;
723 u8 major;
724} __packed;
725
726
727struct wcn36xx_hal_keys {
728 u8 id;
729
730
731 u8 unicast;
732
733 enum ani_key_direction direction;
734
735
736 u8 rsc[WLAN_MAX_KEY_RSC_LEN];
737
738
739 u8 pae_role;
740
741 u16 length;
742 u8 key[WCN36XX_HAL_MAC_MAX_KEY_LENGTH];
743} __packed;
744
745
746
747
748
749struct wcn36xx_hal_set_sta_key_params {
750
751 u16 sta_index;
752
753
754 enum ani_ed_type enc_type;
755
756
757 enum ani_wep_type wep_type;
758
759
760 u8 def_wep_idx;
761
762
763 struct wcn36xx_hal_keys key[WCN36XX_HAL_MAC_MAX_NUM_OF_DEFAULT_KEYS];
764
765
766
767
768
769 u8 single_tid_rc;
770
771} __packed;
772
773
774struct wcn36xx_hal_msg_header {
775 enum wcn36xx_hal_host_msg_type msg_type:16;
776 enum wcn36xx_hal_host_msg_version msg_version:16;
777 u32 len;
778} __packed;
779
780
781struct wcn36xx_hal_cfg {
782
783
784 u16 id;
785
786
787
788 u16 len;
789
790
791 u16 pad_bytes;
792
793
794 u16 reserve;
795
796
797
798} __packed;
799
800struct wcn36xx_hal_mac_start_parameters {
801
802 enum driver_type type;
803
804
805 u32 len;
806
807
808
809
810
811
812
813} __packed;
814
815struct wcn36xx_hal_mac_start_req_msg {
816
817 struct wcn36xx_hal_msg_header header;
818 struct wcn36xx_hal_mac_start_parameters params;
819} __packed;
820
821struct wcn36xx_hal_mac_start_rsp_params {
822
823 u16 status;
824
825
826 u8 stations;
827
828
829 u8 bssids;
830
831
832 struct wcnss_wlan_version version;
833
834
835 u8 crm_version[WCN36XX_HAL_VERSION_LENGTH];
836
837
838 u8 wlan_version[WCN36XX_HAL_VERSION_LENGTH];
839
840} __packed;
841
842struct wcn36xx_hal_mac_start_rsp_msg {
843 struct wcn36xx_hal_msg_header header;
844 struct wcn36xx_hal_mac_start_rsp_params start_rsp_params;
845} __packed;
846
847struct wcn36xx_hal_mac_stop_req_params {
848
849 enum wcn36xx_hal_stop_type reason;
850
851} __packed;
852
853struct wcn36xx_hal_mac_stop_req_msg {
854 struct wcn36xx_hal_msg_header header;
855 struct wcn36xx_hal_mac_stop_req_params stop_req_params;
856} __packed;
857
858struct wcn36xx_hal_mac_stop_rsp_msg {
859 struct wcn36xx_hal_msg_header header;
860
861
862 u32 status;
863} __packed;
864
865struct wcn36xx_hal_update_cfg_req_msg {
866
867
868
869
870 struct wcn36xx_hal_msg_header header;
871
872
873 u32 len;
874
875
876
877
878
879
880
881
882
883} __packed;
884
885struct wcn36xx_hal_update_cfg_rsp_msg {
886 struct wcn36xx_hal_msg_header header;
887
888
889 u32 status;
890
891} __packed;
892
893
894struct wcn36xx_hal_mac_frame_ctl {
895
896#ifndef ANI_LITTLE_BIT_ENDIAN
897
898 u8 subType:4;
899 u8 type:2;
900 u8 protVer:2;
901
902 u8 order:1;
903 u8 wep:1;
904 u8 moreData:1;
905 u8 powerMgmt:1;
906 u8 retry:1;
907 u8 moreFrag:1;
908 u8 fromDS:1;
909 u8 toDS:1;
910
911#else
912
913 u8 protVer:2;
914 u8 type:2;
915 u8 subType:4;
916
917 u8 toDS:1;
918 u8 fromDS:1;
919 u8 moreFrag:1;
920 u8 retry:1;
921 u8 powerMgmt:1;
922 u8 moreData:1;
923 u8 wep:1;
924 u8 order:1;
925
926#endif
927
928};
929
930
931struct wcn36xx_hal_mac_seq_ctl {
932 u8 fragNum:4;
933 u8 seqNumLo:4;
934 u8 seqNumHi:8;
935};
936
937
938struct wcn36xx_hal_mac_mgmt_hdr {
939 struct wcn36xx_hal_mac_frame_ctl fc;
940 u8 durationLo;
941 u8 durationHi;
942 u8 da[6];
943 u8 sa[6];
944 u8 bssId[6];
945 struct wcn36xx_hal_mac_seq_ctl seqControl;
946};
947
948
949#define WCN36XX_HAL_NUM_BSSID 2
950
951
952struct wcn36xx_hal_scan_entry {
953 u8 bss_index[WCN36XX_HAL_NUM_BSSID];
954 u8 active_bss_count;
955};
956
957struct wcn36xx_hal_init_scan_req_msg {
958 struct wcn36xx_hal_msg_header header;
959
960
961
962 enum wcn36xx_hal_sys_mode mode;
963
964
965 u8 bssid[ETH_ALEN];
966
967
968 u8 notify;
969
970
971
972 u8 frame_type;
973
974
975
976
977
978 u8 frame_len;
979
980
981
982 struct wcn36xx_hal_mac_mgmt_hdr mac_mgmt_hdr;
983
984
985 struct wcn36xx_hal_scan_entry scan_entry;
986};
987
988struct wcn36xx_hal_init_scan_con_req_msg {
989 struct wcn36xx_hal_msg_header header;
990
991
992
993 enum wcn36xx_hal_sys_mode mode;
994
995
996 u8 bssid[ETH_ALEN];
997
998
999 u8 notify;
1000
1001
1002
1003 u8 frame_type;
1004
1005
1006
1007
1008
1009 u8 frame_length;
1010
1011
1012
1013 struct wcn36xx_hal_mac_mgmt_hdr mac_mgmt_hdr;
1014
1015
1016 struct wcn36xx_hal_scan_entry scan_entry;
1017
1018
1019 u8 use_noa;
1020
1021
1022 u16 scan_duration;
1023
1024};
1025
1026struct wcn36xx_hal_init_scan_rsp_msg {
1027 struct wcn36xx_hal_msg_header header;
1028
1029
1030 u32 status;
1031
1032} __packed;
1033
1034struct wcn36xx_hal_start_scan_req_msg {
1035 struct wcn36xx_hal_msg_header header;
1036
1037
1038 u8 scan_channel;
1039} __packed;
1040
1041struct wcn36xx_hal_start_rsp_msg {
1042 struct wcn36xx_hal_msg_header header;
1043
1044
1045 u32 status;
1046
1047 u32 start_tsf[2];
1048 u8 tx_mgmt_power;
1049
1050} __packed;
1051
1052struct wcn36xx_hal_end_scan_req_msg {
1053 struct wcn36xx_hal_msg_header header;
1054
1055
1056
1057
1058 u8 scan_channel;
1059} __packed;
1060
1061struct wcn36xx_hal_end_scan_rsp_msg {
1062 struct wcn36xx_hal_msg_header header;
1063
1064
1065 u32 status;
1066} __packed;
1067
1068struct wcn36xx_hal_finish_scan_req_msg {
1069 struct wcn36xx_hal_msg_header header;
1070
1071
1072
1073 enum wcn36xx_hal_sys_mode mode;
1074
1075
1076 u8 oper_channel;
1077
1078
1079
1080
1081 enum phy_chan_bond_state cb_state;
1082
1083
1084 u8 bssid[ETH_ALEN];
1085
1086
1087 u8 notify;
1088
1089
1090
1091 u8 frame_type;
1092
1093
1094
1095
1096
1097 u8 frame_length;
1098
1099
1100
1101 struct wcn36xx_hal_mac_mgmt_hdr mac_mgmt_hdr;
1102
1103
1104 struct wcn36xx_hal_scan_entry scan_entry;
1105
1106} __packed;
1107
1108struct wcn36xx_hal_finish_scan_rsp_msg {
1109 struct wcn36xx_hal_msg_header header;
1110
1111
1112 u32 status;
1113
1114} __packed;
1115
1116enum wcn36xx_hal_rate_index {
1117 HW_RATE_INDEX_1MBPS = 0x82,
1118 HW_RATE_INDEX_2MBPS = 0x84,
1119 HW_RATE_INDEX_5_5MBPS = 0x8B,
1120 HW_RATE_INDEX_6MBPS = 0x0C,
1121 HW_RATE_INDEX_9MBPS = 0x12,
1122 HW_RATE_INDEX_11MBPS = 0x96,
1123 HW_RATE_INDEX_12MBPS = 0x18,
1124 HW_RATE_INDEX_18MBPS = 0x24,
1125 HW_RATE_INDEX_24MBPS = 0x30,
1126 HW_RATE_INDEX_36MBPS = 0x48,
1127 HW_RATE_INDEX_48MBPS = 0x60,
1128 HW_RATE_INDEX_54MBPS = 0x6C
1129};
1130
1131struct wcn36xx_hal_supported_rates {
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151 enum sta_rate_mode op_rate_mode;
1152
1153
1154
1155 u16 dsss_rates[WCN36XX_HAL_NUM_DSSS_RATES];
1156 u16 ofdm_rates[WCN36XX_HAL_NUM_OFDM_RATES];
1157 u16 legacy_rates[WCN36XX_HAL_NUM_POLARIS_RATES];
1158 u16 reserved;
1159
1160
1161
1162
1163
1164
1165 u32 enhanced_rate_bitmap;
1166
1167
1168
1169
1170
1171 u8 supported_mcs_set[WCN36XX_HAL_MAC_MAX_SUPPORTED_MCS_SET];
1172
1173
1174
1175
1176
1177
1178
1179 u16 rx_highest_data_rate;
1180
1181} __packed;
1182
1183struct wcn36xx_hal_config_sta_params {
1184
1185 u8 bssid[ETH_ALEN];
1186
1187
1188 u16 aid;
1189
1190
1191 u8 type;
1192
1193
1194 u8 short_preamble_supported;
1195
1196
1197 u8 mac[ETH_ALEN];
1198
1199
1200 u16 listen_interval;
1201
1202
1203 u8 wmm_enabled;
1204
1205
1206 u8 ht_capable;
1207
1208
1209 u8 tx_channel_width_set;
1210
1211
1212 u8 rifs_mode;
1213
1214
1215
1216
1217 u8 lsig_txop_protection;
1218
1219
1220
1221 u8 max_ampdu_size;
1222
1223
1224 u8 max_ampdu_density;
1225
1226
1227 u8 max_amsdu_size;
1228
1229
1230 u8 sgi_40mhz;
1231
1232
1233 u8 sgi_20Mhz;
1234
1235
1236
1237 struct wcn36xx_hal_supported_rates supported_rates;
1238
1239
1240 u8 rmf;
1241
1242
1243 u32 encrypt_type;
1244
1245
1246
1247
1248 u8 action;
1249
1250
1251
1252
1253 u8 uapsd;
1254
1255
1256 u8 max_sp_len;
1257
1258
1259
1260 u8 green_field_capable;
1261
1262
1263 enum wcn36xx_hal_ht_mimo_state mimo_ps;
1264
1265
1266 u8 delayed_ba_support;
1267
1268
1269 u8 max_ampdu_duration;
1270
1271
1272
1273
1274
1275 u8 dsss_cck_mode_40mhz;
1276
1277
1278
1279 u8 sta_index;
1280
1281
1282
1283
1284 u8 bssid_index;
1285
1286 u8 p2p;
1287
1288
1289
1290
1291} __packed;
1292
1293struct wcn36xx_hal_config_sta_req_msg {
1294 struct wcn36xx_hal_msg_header header;
1295 struct wcn36xx_hal_config_sta_params sta_params;
1296} __packed;
1297
1298struct wcn36xx_hal_config_sta_params_v1 {
1299
1300 u8 bssid[ETH_ALEN];
1301
1302
1303 u16 aid;
1304
1305
1306 u8 type;
1307
1308
1309 u8 short_preamble_supported;
1310
1311
1312 u8 mac[ETH_ALEN];
1313
1314
1315 u16 listen_interval;
1316
1317
1318 u8 wmm_enabled;
1319
1320
1321 u8 ht_capable;
1322
1323
1324 u8 tx_channel_width_set;
1325
1326
1327 u8 rifs_mode;
1328
1329
1330
1331
1332 u8 lsig_txop_protection;
1333
1334
1335
1336 u8 max_ampdu_size;
1337
1338
1339 u8 max_ampdu_density;
1340
1341
1342 u8 max_amsdu_size;
1343
1344
1345 u8 sgi_40mhz;
1346
1347
1348 u8 sgi_20Mhz;
1349
1350
1351 u8 rmf;
1352
1353
1354 u32 encrypt_type;
1355
1356
1357
1358
1359 u8 action;
1360
1361
1362
1363
1364 u8 uapsd;
1365
1366
1367 u8 max_sp_len;
1368
1369
1370
1371 u8 green_field_capable;
1372
1373
1374 enum wcn36xx_hal_ht_mimo_state mimo_ps;
1375
1376
1377 u8 delayed_ba_support;
1378
1379
1380 u8 max_ampdu_duration;
1381
1382
1383
1384
1385
1386 u8 dsss_cck_mode_40mhz;
1387
1388
1389
1390 u8 sta_index;
1391
1392
1393
1394
1395 u8 bssid_index;
1396
1397 u8 p2p;
1398
1399
1400 u8 reserved;
1401
1402
1403 struct wcn36xx_hal_supported_rates supported_rates;
1404} __packed;
1405
1406struct wcn36xx_hal_config_sta_req_msg_v1 {
1407 struct wcn36xx_hal_msg_header header;
1408 struct wcn36xx_hal_config_sta_params_v1 sta_params;
1409} __packed;
1410
1411struct config_sta_rsp_params {
1412
1413 u32 status;
1414
1415
1416 u8 sta_index;
1417
1418
1419 u8 bssid_index;
1420
1421
1422 u8 dpu_index;
1423
1424
1425 u8 bcast_dpu_index;
1426
1427
1428 u8 bcast_mgmt_dpu_idx;
1429
1430
1431 u8 uc_ucast_sig;
1432
1433
1434 u8 uc_bcast_sig;
1435
1436
1437 u8 uc_mgmt_sig;
1438
1439 u8 p2p;
1440
1441} __packed;
1442
1443struct wcn36xx_hal_config_sta_rsp_msg {
1444 struct wcn36xx_hal_msg_header header;
1445
1446 struct config_sta_rsp_params params;
1447} __packed;
1448
1449
1450struct wcn36xx_hal_delete_sta_req_msg {
1451 struct wcn36xx_hal_msg_header header;
1452
1453
1454 u8 sta_index;
1455
1456} __packed;
1457
1458
1459struct wcn36xx_hal_delete_sta_rsp_msg {
1460 struct wcn36xx_hal_msg_header header;
1461
1462
1463 u32 status;
1464
1465
1466 u8 sta_id;
1467} __packed;
1468
1469
1470
1471struct wcn36xx_hal_rate_set {
1472 u8 num_rates;
1473 u8 rate[WCN36XX_HAL_MAC_RATESET_EID_MAX];
1474} __packed;
1475
1476
1477struct wcn36xx_hal_aci_aifsn {
1478#ifndef ANI_LITTLE_BIT_ENDIAN
1479 u8 rsvd:1;
1480 u8 aci:2;
1481 u8 acm:1;
1482 u8 aifsn:4;
1483#else
1484 u8 aifsn:4;
1485 u8 acm:1;
1486 u8 aci:2;
1487 u8 rsvd:1;
1488#endif
1489} __packed;
1490
1491
1492struct wcn36xx_hal_mac_cw {
1493#ifndef ANI_LITTLE_BIT_ENDIAN
1494 u8 max:4;
1495 u8 min:4;
1496#else
1497 u8 min:4;
1498 u8 max:4;
1499#endif
1500} __packed;
1501
1502struct wcn36xx_hal_edca_param_record {
1503 struct wcn36xx_hal_aci_aifsn aci;
1504 struct wcn36xx_hal_mac_cw cw;
1505 u16 txop_limit;
1506} __packed;
1507
1508struct wcn36xx_hal_mac_ssid {
1509 u8 length;
1510 u8 ssid[32];
1511} __packed;
1512
1513
1514
1515enum wcn36xx_hal_con_mode {
1516 WCN36XX_HAL_STA_MODE = 0,
1517
1518
1519
1520 WCN36XX_HAL_STA_SAP_MODE = 1,
1521
1522 WCN36XX_HAL_P2P_CLIENT_MODE,
1523 WCN36XX_HAL_P2P_GO_MODE,
1524 WCN36XX_HAL_MONITOR_MODE,
1525};
1526
1527
1528
1529
1530
1531
1532enum wcn36xx_hal_concurrency_mode {
1533 HAL_STA = 1,
1534 HAL_SAP = 2,
1535
1536
1537 HAL_STA_SAP = 3,
1538
1539 HAL_P2P_CLIENT = 4,
1540 HAL_P2P_GO = 8,
1541 HAL_MAX_CONCURRENCY_PERSONA = 4
1542};
1543
1544struct wcn36xx_hal_config_bss_params {
1545
1546 u8 bssid[ETH_ALEN];
1547
1548
1549 u8 self_mac_addr[ETH_ALEN];
1550
1551
1552 enum wcn36xx_hal_bss_type bss_type;
1553
1554
1555 u8 oper_mode;
1556
1557
1558 enum wcn36xx_hal_nw_type nw_type;
1559
1560
1561 u8 short_slot_time_supported;
1562
1563
1564 u8 lla_coexist;
1565
1566
1567 u8 llb_coexist;
1568
1569
1570 u8 llg_coexist;
1571
1572
1573 u8 ht20_coexist;
1574
1575
1576 u8 lln_non_gf_coexist;
1577
1578
1579 u8 lsig_tx_op_protection_full_support;
1580
1581
1582 u8 rifs_mode;
1583
1584
1585 u16 beacon_interval;
1586
1587
1588 u8 dtim_period;
1589
1590
1591 u8 tx_channel_width_set;
1592
1593
1594 u8 oper_channel;
1595
1596
1597 u8 ext_channel;
1598
1599
1600 u8 reserved;
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611 struct wcn36xx_hal_config_sta_params sta;
1612
1613 struct wcn36xx_hal_mac_ssid ssid;
1614
1615
1616
1617
1618
1619 u8 action;
1620
1621
1622 struct wcn36xx_hal_rate_set rateset;
1623
1624
1625 u8 ht;
1626
1627
1628 u8 obss_prot_enabled;
1629
1630
1631 u8 rmf;
1632
1633
1634 enum wcn36xx_hal_ht_operating_mode ht_oper_mode;
1635
1636
1637 u8 dual_cts_protection;
1638
1639
1640 u8 max_probe_resp_retry_limit;
1641
1642
1643 u8 hidden_ssid;
1644
1645
1646 u8 proxy_probe_resp;
1647
1648
1649
1650
1651
1652 u8 edca_params_valid;
1653
1654
1655 struct wcn36xx_hal_edca_param_record acbe;
1656
1657
1658 struct wcn36xx_hal_edca_param_record acbk;
1659
1660
1661 struct wcn36xx_hal_edca_param_record acvi;
1662
1663
1664 struct wcn36xx_hal_edca_param_record acvo;
1665
1666
1667 u8 ext_set_sta_key_param_valid;
1668
1669
1670 struct wcn36xx_hal_set_sta_key_params ext_set_sta_key_param;
1671
1672
1673
1674 u8 wcn36xx_hal_persona;
1675
1676 u8 spectrum_mgt_enable;
1677
1678
1679 s8 tx_mgmt_power;
1680
1681
1682
1683 s8 max_tx_power;
1684} __packed;
1685
1686struct wcn36xx_hal_config_bss_req_msg {
1687 struct wcn36xx_hal_msg_header header;
1688 struct wcn36xx_hal_config_bss_params bss_params;
1689} __packed;
1690
1691struct wcn36xx_hal_config_bss_params_v1 {
1692
1693 u8 bssid[ETH_ALEN];
1694
1695
1696 u8 self_mac_addr[ETH_ALEN];
1697
1698
1699 enum wcn36xx_hal_bss_type bss_type;
1700
1701
1702 u8 oper_mode;
1703
1704
1705 enum wcn36xx_hal_nw_type nw_type;
1706
1707
1708 u8 short_slot_time_supported;
1709
1710
1711 u8 lla_coexist;
1712
1713
1714 u8 llb_coexist;
1715
1716
1717 u8 llg_coexist;
1718
1719
1720 u8 ht20_coexist;
1721
1722
1723 u8 lln_non_gf_coexist;
1724
1725
1726 u8 lsig_tx_op_protection_full_support;
1727
1728
1729 u8 rifs_mode;
1730
1731
1732 u16 beacon_interval;
1733
1734
1735 u8 dtim_period;
1736
1737
1738 u8 tx_channel_width_set;
1739
1740
1741 u8 oper_channel;
1742
1743
1744 u8 ext_channel;
1745
1746
1747 u8 reserved;
1748
1749
1750 struct wcn36xx_hal_mac_ssid ssid;
1751
1752
1753
1754
1755
1756 u8 action;
1757
1758
1759 struct wcn36xx_hal_rate_set rateset;
1760
1761
1762 u8 ht;
1763
1764
1765 u8 obss_prot_enabled;
1766
1767
1768 u8 rmf;
1769
1770
1771 enum wcn36xx_hal_ht_operating_mode ht_oper_mode;
1772
1773
1774 u8 dual_cts_protection;
1775
1776
1777 u8 max_probe_resp_retry_limit;
1778
1779
1780 u8 hidden_ssid;
1781
1782
1783 u8 proxy_probe_resp;
1784
1785
1786
1787
1788
1789 u8 edca_params_valid;
1790
1791
1792 struct wcn36xx_hal_edca_param_record acbe;
1793
1794
1795 struct wcn36xx_hal_edca_param_record acbk;
1796
1797
1798 struct wcn36xx_hal_edca_param_record acvi;
1799
1800
1801 struct wcn36xx_hal_edca_param_record acvo;
1802
1803
1804 u8 ext_set_sta_key_param_valid;
1805
1806
1807 struct wcn36xx_hal_set_sta_key_params ext_set_sta_key_param;
1808
1809
1810
1811 u8 wcn36xx_hal_persona;
1812
1813 u8 spectrum_mgt_enable;
1814
1815
1816 s8 tx_mgmt_power;
1817
1818
1819
1820 s8 max_tx_power;
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830 struct wcn36xx_hal_config_sta_params_v1 sta;
1831} __packed;
1832
1833struct wcn36xx_hal_config_bss_req_msg_v1 {
1834 struct wcn36xx_hal_msg_header header;
1835 struct wcn36xx_hal_config_bss_params_v1 bss_params;
1836} __packed;
1837
1838struct wcn36xx_hal_config_bss_rsp_params {
1839
1840 u32 status;
1841
1842
1843 u8 bss_index;
1844
1845
1846 u8 dpu_desc_index;
1847
1848
1849 u8 ucast_dpu_signature;
1850
1851
1852 u8 bcast_dpu_desc_indx;
1853
1854
1855 u8 bcast_dpu_signature;
1856
1857
1858 u8 mgmt_dpu_desc_index;
1859
1860
1861 u8 mgmt_dpu_signature;
1862
1863
1864 u8 bss_sta_index;
1865
1866
1867 u8 bss_self_sta_index;
1868
1869
1870 u8 bss_bcast_sta_idx;
1871
1872
1873 u8 mac[ETH_ALEN];
1874
1875
1876 s8 tx_mgmt_power;
1877
1878} __packed;
1879
1880struct wcn36xx_hal_config_bss_rsp_msg {
1881 struct wcn36xx_hal_msg_header header;
1882 struct wcn36xx_hal_config_bss_rsp_params bss_rsp_params;
1883} __packed;
1884
1885struct wcn36xx_hal_delete_bss_req_msg {
1886 struct wcn36xx_hal_msg_header header;
1887
1888
1889 u8 bss_index;
1890
1891} __packed;
1892
1893struct wcn36xx_hal_delete_bss_rsp_msg {
1894 struct wcn36xx_hal_msg_header header;
1895
1896
1897 u32 status;
1898
1899
1900 u8 bss_index;
1901
1902} __packed;
1903
1904struct wcn36xx_hal_join_req_msg {
1905 struct wcn36xx_hal_msg_header header;
1906
1907
1908 u8 bssid[ETH_ALEN];
1909
1910
1911 u8 channel;
1912
1913
1914 u8 self_sta_mac_addr[ETH_ALEN];
1915
1916
1917 u8 local_power_constraint;
1918
1919
1920 enum phy_chan_bond_state secondary_channel_offset;
1921
1922
1923 enum wcn36xx_hal_link_state link_state;
1924
1925
1926 s8 max_tx_power;
1927} __packed;
1928
1929struct wcn36xx_hal_join_rsp_msg {
1930 struct wcn36xx_hal_msg_header header;
1931
1932
1933 u32 status;
1934
1935
1936 u8 tx_mgmt_power;
1937} __packed;
1938
1939struct post_assoc_req_msg {
1940 struct wcn36xx_hal_msg_header header;
1941
1942 struct wcn36xx_hal_config_sta_params sta_params;
1943 struct wcn36xx_hal_config_bss_params bss_params;
1944};
1945
1946struct post_assoc_rsp_msg {
1947 struct wcn36xx_hal_msg_header header;
1948 struct config_sta_rsp_params sta_rsp_params;
1949 struct wcn36xx_hal_config_bss_rsp_params bss_rsp_params;
1950};
1951
1952
1953struct wcn36xx_hal_set_bss_key_req_msg {
1954 struct wcn36xx_hal_msg_header header;
1955
1956
1957 u8 bss_idx;
1958
1959
1960 enum ani_ed_type enc_type;
1961
1962
1963 u8 num_keys;
1964
1965
1966 struct wcn36xx_hal_keys keys[WCN36XX_HAL_MAC_MAX_NUM_OF_DEFAULT_KEYS];
1967
1968
1969
1970 u8 single_tid_rc;
1971} __packed;
1972
1973
1974struct wcn36xx_hal_set_bss_key_req_msg_tagged {
1975 struct wcn36xx_hal_set_bss_key_req_msg Msg;
1976 u32 tag;
1977} __packed;
1978
1979struct wcn36xx_hal_set_bss_key_rsp_msg {
1980 struct wcn36xx_hal_msg_header header;
1981
1982
1983 u32 status;
1984} __packed;
1985
1986
1987
1988
1989
1990
1991
1992struct wcn36xx_hal_set_sta_key_req_msg {
1993 struct wcn36xx_hal_msg_header header;
1994 struct wcn36xx_hal_set_sta_key_params set_sta_key_params;
1995} __packed;
1996
1997struct wcn36xx_hal_set_sta_key_rsp_msg {
1998 struct wcn36xx_hal_msg_header header;
1999
2000
2001 u32 status;
2002} __packed;
2003
2004struct wcn36xx_hal_remove_bss_key_req_msg {
2005 struct wcn36xx_hal_msg_header header;
2006
2007
2008 u8 bss_idx;
2009
2010
2011 enum ani_ed_type enc_type;
2012
2013
2014 u8 key_id;
2015
2016
2017
2018 enum ani_wep_type wep_type;
2019} __packed;
2020
2021struct wcn36xx_hal_remove_bss_key_rsp_msg {
2022 struct wcn36xx_hal_msg_header header;
2023
2024
2025 u32 status;
2026} __packed;
2027
2028
2029
2030
2031struct wcn36xx_hal_remove_sta_key_req_msg {
2032 struct wcn36xx_hal_msg_header header;
2033
2034
2035 u16 sta_idx;
2036
2037
2038 enum ani_ed_type enc_type;
2039
2040
2041 u8 key_id;
2042
2043
2044
2045 u8 unicast;
2046
2047} __packed;
2048
2049struct wcn36xx_hal_remove_sta_key_rsp_msg {
2050 struct wcn36xx_hal_msg_header header;
2051
2052
2053 u32 status;
2054
2055} __packed;
2056
2057#ifdef FEATURE_OEM_DATA_SUPPORT
2058
2059#ifndef OEM_DATA_REQ_SIZE
2060#define OEM_DATA_REQ_SIZE 134
2061#endif
2062
2063#ifndef OEM_DATA_RSP_SIZE
2064#define OEM_DATA_RSP_SIZE 1968
2065#endif
2066
2067struct start_oem_data_req_msg {
2068 struct wcn36xx_hal_msg_header header;
2069
2070 u32 status;
2071 tSirMacAddr self_mac_addr;
2072 u8 oem_data_req[OEM_DATA_REQ_SIZE];
2073
2074};
2075
2076struct start_oem_data_rsp_msg {
2077 struct wcn36xx_hal_msg_header header;
2078
2079 u8 oem_data_rsp[OEM_DATA_RSP_SIZE];
2080};
2081
2082#endif
2083
2084struct wcn36xx_hal_switch_channel_req_msg {
2085 struct wcn36xx_hal_msg_header header;
2086
2087
2088 u8 channel_number;
2089
2090
2091 u8 local_power_constraint;
2092
2093
2094 enum phy_chan_bond_state secondary_channel_offset;
2095
2096
2097 u8 tx_mgmt_power;
2098
2099
2100 u8 max_tx_power;
2101
2102
2103 u8 self_sta_mac_addr[ETH_ALEN];
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114 u8 bssid[ETH_ALEN];
2115} __packed;
2116
2117struct wcn36xx_hal_switch_channel_rsp_msg {
2118 struct wcn36xx_hal_msg_header header;
2119
2120
2121 u32 status;
2122
2123
2124 u8 channel_number;
2125
2126
2127 u8 tx_mgmt_power;
2128
2129
2130 u8 bssid[ETH_ALEN];
2131
2132} __packed;
2133
2134struct update_edca_params_req_msg {
2135 struct wcn36xx_hal_msg_header header;
2136
2137
2138 u16 bss_index;
2139
2140
2141 struct wcn36xx_hal_edca_param_record acbe;
2142
2143
2144 struct wcn36xx_hal_edca_param_record acbk;
2145
2146
2147 struct wcn36xx_hal_edca_param_record acvi;
2148
2149
2150 struct wcn36xx_hal_edca_param_record acvo;
2151};
2152
2153struct update_edca_params_rsp_msg {
2154 struct wcn36xx_hal_msg_header header;
2155
2156
2157 u32 status;
2158};
2159
2160struct dpu_stats_params {
2161
2162 u16 sta_index;
2163
2164
2165 u8 enc_mode;
2166
2167
2168 u32 status;
2169
2170
2171 u32 send_blocks;
2172 u32 recv_blocks;
2173 u32 replays;
2174 u8 mic_error_cnt;
2175 u32 prot_excl_cnt;
2176 u16 format_err_cnt;
2177 u16 un_decryptable_cnt;
2178 u32 decrypt_err_cnt;
2179 u32 decrypt_ok_cnt;
2180};
2181
2182struct wcn36xx_hal_stats_req_msg {
2183 struct wcn36xx_hal_msg_header header;
2184
2185
2186 u32 sta_id;
2187
2188
2189 u32 stats_mask;
2190};
2191
2192struct ani_summary_stats_info {
2193
2194
2195 u32 retry_cnt[4];
2196
2197
2198
2199
2200 u32 multiple_retry_cnt[4];
2201
2202
2203
2204
2205 u32 tx_frm_cnt[4];
2206
2207
2208
2209 u32 rx_frm_cnt;
2210
2211
2212 u32 frm_dup_cnt;
2213
2214
2215 u32 fail_cnt[4];
2216
2217
2218
2219 u32 rts_fail_cnt;
2220
2221
2222
2223 u32 ack_fail_cnt;
2224
2225
2226
2227 u32 rts_succ_cnt;
2228
2229
2230
2231
2232 u32 rx_discard_cnt;
2233
2234
2235
2236
2237 u32 rx_error_cnt;
2238
2239
2240
2241
2242 u32 tx_byte_cnt;
2243};
2244
2245
2246enum tx_rate_info {
2247
2248 HAL_TX_RATE_LEGACY = 0x1,
2249
2250
2251 HAL_TX_RATE_HT20 = 0x2,
2252
2253
2254 HAL_TX_RATE_HT40 = 0x4,
2255
2256
2257 HAL_TX_RATE_SGI = 0x8,
2258
2259
2260 HAL_TX_RATE_LGI = 0x10
2261};
2262
2263struct ani_global_class_a_stats_info {
2264
2265
2266 u32 rx_frag_cnt;
2267
2268
2269
2270
2271 u32 promiscuous_rx_frag_cnt;
2272
2273
2274
2275
2276
2277 u32 rx_input_sensitivity;
2278
2279
2280
2281 u32 max_pwr;
2282
2283
2284
2285
2286 u32 sync_fail_cnt;
2287
2288
2289
2290 u32 tx_rate;
2291
2292
2293 u32 mcs_index;
2294
2295
2296
2297 u32 tx_rate_flags;
2298};
2299
2300struct ani_global_security_stats {
2301
2302
2303
2304 u32 rx_wep_unencrypted_frm_cnt;
2305
2306
2307
2308 u32 rx_mic_fail_cnt;
2309
2310
2311
2312 u32 tkip_icv_err;
2313
2314
2315
2316 u32 aes_ccmp_format_err;
2317
2318
2319
2320 u32 aes_ccmp_replay_cnt;
2321
2322
2323
2324
2325 u32 aes_ccmp_decrpt_err;
2326
2327
2328
2329 u32 wep_undecryptable_cnt;
2330
2331
2332
2333 u32 wep_icv_err;
2334
2335
2336
2337 u32 rx_decrypt_succ_cnt;
2338
2339
2340
2341 u32 rx_decrypt_fail_cnt;
2342};
2343
2344struct ani_global_class_b_stats_info {
2345 struct ani_global_security_stats uc_stats;
2346 struct ani_global_security_stats mc_bc_stats;
2347};
2348
2349struct ani_global_class_c_stats_info {
2350
2351
2352
2353 u32 rx_amsdu_cnt;
2354
2355
2356
2357 u32 rx_ampdu_cnt;
2358
2359
2360
2361 u32 tx_20_frm_cnt;
2362
2363
2364
2365 u32 rx_20_frm_cnt;
2366
2367
2368
2369 u32 rx_mpdu_in_ampdu_cnt;
2370
2371
2372
2373
2374 u32 ampdu_delimiter_crc_err;
2375};
2376
2377struct ani_per_sta_stats_info {
2378
2379
2380 u32 tx_frag_cnt[4];
2381
2382
2383 u32 tx_ampdu_cnt;
2384
2385
2386
2387 u32 tx_mpdu_in_ampdu_cnt;
2388};
2389
2390struct wcn36xx_hal_stats_rsp_msg {
2391 struct wcn36xx_hal_msg_header header;
2392
2393
2394 u32 status;
2395
2396
2397 u32 sta_index;
2398
2399
2400 u32 stats_mask;
2401
2402
2403 u16 msg_type;
2404
2405
2406 u16 msg_len;
2407};
2408
2409struct wcn36xx_hal_set_link_state_req_msg {
2410 struct wcn36xx_hal_msg_header header;
2411
2412 u8 bssid[ETH_ALEN];
2413 enum wcn36xx_hal_link_state state;
2414 u8 self_mac_addr[ETH_ALEN];
2415
2416} __packed;
2417
2418struct set_link_state_rsp_msg {
2419 struct wcn36xx_hal_msg_header header;
2420
2421
2422 u32 status;
2423};
2424
2425
2426struct wcn36xx_hal_ts_info_tfc {
2427#ifndef ANI_LITTLE_BIT_ENDIAN
2428 u16 ackPolicy:2;
2429 u16 userPrio:3;
2430 u16 psb:1;
2431 u16 aggregation:1;
2432 u16 accessPolicy:2;
2433 u16 direction:2;
2434 u16 tsid:4;
2435 u16 trafficType:1;
2436#else
2437 u16 trafficType:1;
2438 u16 tsid:4;
2439 u16 direction:2;
2440 u16 accessPolicy:2;
2441 u16 aggregation:1;
2442 u16 psb:1;
2443 u16 userPrio:3;
2444 u16 ackPolicy:2;
2445#endif
2446};
2447
2448
2449struct wcn36xx_hal_ts_info_sch {
2450#ifndef ANI_LITTLE_BIT_ENDIAN
2451 u8 rsvd:7;
2452 u8 schedule:1;
2453#else
2454 u8 schedule:1;
2455 u8 rsvd:7;
2456#endif
2457};
2458
2459
2460struct wcn36xx_hal_ts_info {
2461 struct wcn36xx_hal_ts_info_tfc traffic;
2462 struct wcn36xx_hal_ts_info_sch schedule;
2463};
2464
2465
2466struct wcn36xx_hal_tspec_ie {
2467 u8 type;
2468 u8 length;
2469 struct wcn36xx_hal_ts_info ts_info;
2470 u16 nom_msdu_size;
2471 u16 max_msdu_size;
2472 u32 min_svc_interval;
2473 u32 max_svc_interval;
2474 u32 inact_interval;
2475 u32 suspend_interval;
2476 u32 svc_start_time;
2477 u32 min_data_rate;
2478 u32 mean_data_rate;
2479 u32 peak_data_rate;
2480 u32 max_burst_sz;
2481 u32 delay_bound;
2482 u32 min_phy_rate;
2483 u16 surplus_bw;
2484 u16 medium_time;
2485};
2486
2487struct add_ts_req_msg {
2488 struct wcn36xx_hal_msg_header header;
2489
2490
2491 u16 sta_index;
2492
2493
2494 u16 tspec_index;
2495
2496
2497 struct wcn36xx_hal_tspec_ie tspec;
2498
2499
2500
2501
2502 u8 uapsd;
2503
2504
2505
2506
2507 u32 service_interval[WCN36XX_HAL_MAX_AC];
2508
2509
2510 u32 suspend_interval[WCN36XX_HAL_MAX_AC];
2511
2512
2513 u32 delay_interval[WCN36XX_HAL_MAX_AC];
2514};
2515
2516struct add_rs_rsp_msg {
2517 struct wcn36xx_hal_msg_header header;
2518
2519
2520 u32 status;
2521};
2522
2523struct del_ts_req_msg {
2524 struct wcn36xx_hal_msg_header header;
2525
2526
2527 u16 sta_index;
2528
2529
2530 u16 tspec_index;
2531
2532
2533 u8 bssid[ETH_ALEN];
2534};
2535
2536struct del_ts_rsp_msg {
2537 struct wcn36xx_hal_msg_header header;
2538
2539
2540 u32 status;
2541};
2542
2543
2544
2545
2546
2547struct wcn36xx_hal_add_ba_session_req_msg {
2548 struct wcn36xx_hal_msg_header header;
2549
2550
2551 u16 sta_index;
2552
2553
2554 u8 mac_addr[ETH_ALEN];
2555
2556
2557
2558 u8 dialog_token;
2559
2560
2561
2562 u8 tid;
2563
2564
2565
2566 u8 policy;
2567
2568
2569
2570
2571
2572
2573
2574 u16 buffer_size;
2575
2576
2577 u16 timeout;
2578
2579
2580
2581
2582 u16 ssn;
2583
2584
2585
2586
2587 u8 direction;
2588} __packed;
2589
2590struct wcn36xx_hal_add_ba_session_rsp_msg {
2591 struct wcn36xx_hal_msg_header header;
2592
2593
2594 u32 status;
2595
2596
2597 u8 dialog_token;
2598
2599
2600 u8 ba_tid;
2601
2602
2603 u8 ba_buffer_size;
2604
2605 u8 ba_session_id;
2606
2607
2608 u8 win_size;
2609
2610
2611 u8 sta_index;
2612
2613
2614 u16 ssn;
2615} __packed;
2616
2617struct wcn36xx_hal_add_ba_req_msg {
2618 struct wcn36xx_hal_msg_header header;
2619
2620
2621 u8 session_id;
2622
2623
2624 u8 win_size;
2625
2626#ifdef FEATURE_ON_CHIP_REORDERING
2627 u8 reordering_done_on_chip;
2628#endif
2629} __packed;
2630
2631struct wcn36xx_hal_add_ba_rsp_msg {
2632 struct wcn36xx_hal_msg_header header;
2633
2634
2635 u32 status;
2636
2637
2638 u8 dialog_token;
2639} __packed;
2640
2641struct add_ba_info {
2642 u16 ba_enable:1;
2643 u16 starting_seq_num:12;
2644 u16 reserved:3;
2645};
2646
2647struct wcn36xx_hal_trigger_ba_rsp_candidate {
2648 u8 sta_addr[ETH_ALEN];
2649 struct add_ba_info ba_info[STACFG_MAX_TC];
2650} __packed;
2651
2652struct wcn36xx_hal_trigger_ba_req_candidate {
2653 u8 sta_index;
2654 u8 tid_bitmap;
2655} __packed;
2656
2657struct wcn36xx_hal_trigger_ba_req_msg {
2658 struct wcn36xx_hal_msg_header header;
2659
2660
2661 u8 session_id;
2662
2663
2664
2665
2666 u16 candidate_cnt;
2667
2668} __packed;
2669
2670struct wcn36xx_hal_trigger_ba_rsp_msg {
2671 struct wcn36xx_hal_msg_header header;
2672
2673
2674 u8 bssid[ETH_ALEN];
2675
2676
2677 u32 status;
2678
2679
2680
2681
2682 u16 candidate_cnt;
2683} __packed;
2684
2685struct wcn36xx_hal_del_ba_req_msg {
2686 struct wcn36xx_hal_msg_header header;
2687
2688
2689 u16 sta_index;
2690
2691
2692 u8 tid;
2693
2694
2695
2696
2697 u8 direction;
2698} __packed;
2699
2700struct wcn36xx_hal_del_ba_rsp_msg {
2701 struct wcn36xx_hal_msg_header header;
2702
2703
2704 u32 status;
2705} __packed;
2706
2707struct tsm_stats_req_msg {
2708 struct wcn36xx_hal_msg_header header;
2709
2710
2711 u8 tid;
2712
2713 u8 bssid[ETH_ALEN];
2714};
2715
2716struct tsm_stats_rsp_msg {
2717 struct wcn36xx_hal_msg_header header;
2718
2719
2720 u32 status;
2721
2722
2723 u16 uplink_pkt_queue_delay;
2724
2725
2726 u16 uplink_pkt_queue_delay_hist[4];
2727
2728
2729 u32 uplink_pkt_tx_delay;
2730
2731
2732 u16 uplink_pkt_loss;
2733
2734
2735 u16 uplink_pkt_count;
2736
2737
2738 u8 roaming_count;
2739
2740
2741 u16 roaming_delay;
2742};
2743
2744struct set_key_done_msg {
2745 struct wcn36xx_hal_msg_header header;
2746
2747
2748 u8 bssidx;
2749 u8 enc_type;
2750};
2751
2752struct wcn36xx_hal_nv_img_download_req_msg {
2753
2754
2755
2756
2757 struct wcn36xx_hal_msg_header header;
2758
2759
2760
2761
2762
2763
2764
2765
2766
2767 u16 frag_number;
2768
2769
2770
2771
2772
2773
2774 u16 last_fragment;
2775
2776
2777 u32 nv_img_buffer_size;
2778
2779
2780
2781
2782} __packed;
2783
2784struct wcn36xx_hal_nv_img_download_rsp_msg {
2785 struct wcn36xx_hal_msg_header header;
2786
2787
2788
2789 u32 status;
2790} __packed;
2791
2792struct wcn36xx_hal_nv_store_ind {
2793
2794
2795 struct wcn36xx_hal_msg_header header;
2796
2797
2798 u32 table_id;
2799
2800
2801 u32 nv_blob_size;
2802
2803
2804
2805};
2806
2807
2808
2809#define WCN36XX_HAL_CIPHER_SEQ_CTR_SIZE 6
2810
2811
2812
2813
2814struct mic_failure_ind_msg {
2815 struct wcn36xx_hal_msg_header header;
2816
2817 u8 bssid[ETH_ALEN];
2818
2819
2820 u8 src_addr[ETH_ALEN];
2821
2822
2823 u8 ta_addr[ETH_ALEN];
2824
2825 u8 dst_addr[ETH_ALEN];
2826
2827 u8 multicast;
2828
2829
2830 u8 iv1;
2831
2832
2833 u8 key_id;
2834
2835
2836 u8 tsc[WCN36XX_HAL_CIPHER_SEQ_CTR_SIZE];
2837
2838
2839 u8 rx_addr[ETH_ALEN];
2840};
2841
2842struct update_vht_op_mode_req_msg {
2843 struct wcn36xx_hal_msg_header header;
2844
2845 u16 op_mode;
2846 u16 sta_id;
2847};
2848
2849struct update_vht_op_mode_params_rsp_msg {
2850 struct wcn36xx_hal_msg_header header;
2851
2852 u32 status;
2853};
2854
2855struct update_beacon_req_msg {
2856 struct wcn36xx_hal_msg_header header;
2857
2858 u8 bss_index;
2859
2860
2861
2862 u8 short_preamble;
2863
2864
2865 u8 short_slot_time;
2866
2867
2868 u16 beacon_interval;
2869
2870
2871 u8 lla_coexist;
2872 u8 llb_coexist;
2873 u8 llg_coexist;
2874 u8 ht20_coexist;
2875 u8 lln_non_gf_coexist;
2876 u8 lsig_tx_op_protection_full_support;
2877 u8 rifs_mode;
2878
2879 u16 param_change_bitmap;
2880};
2881
2882struct update_beacon_rsp_msg {
2883 struct wcn36xx_hal_msg_header header;
2884 u32 status;
2885};
2886
2887struct wcn36xx_hal_send_beacon_req_msg {
2888 struct wcn36xx_hal_msg_header header;
2889
2890
2891 u32 beacon_length6;
2892
2893
2894 u32 beacon_length;
2895
2896
2897 u8 beacon[BEACON_TEMPLATE_SIZE - sizeof(u32)];
2898
2899 u8 bssid[ETH_ALEN];
2900
2901
2902 u32 tim_ie_offset;
2903
2904
2905 u16 p2p_ie_offset;
2906} __packed;
2907
2908struct send_beacon_rsp_msg {
2909 struct wcn36xx_hal_msg_header header;
2910 u32 status;
2911} __packed;
2912
2913struct enable_radar_req_msg {
2914 struct wcn36xx_hal_msg_header header;
2915
2916 u8 bssid[ETH_ALEN];
2917 u8 channel;
2918};
2919
2920struct enable_radar_rsp_msg {
2921 struct wcn36xx_hal_msg_header header;
2922
2923
2924 u8 bssid[ETH_ALEN];
2925
2926
2927 u32 status;
2928};
2929
2930struct radar_detect_intr_ind_msg {
2931 struct wcn36xx_hal_msg_header header;
2932
2933 u8 radar_det_channel;
2934};
2935
2936struct radar_detect_ind_msg {
2937 struct wcn36xx_hal_msg_header header;
2938
2939
2940 u8 channel_number;
2941
2942
2943 u16 radar_pulse_width;
2944
2945
2946 u16 num_radar_pulse;
2947};
2948
2949struct wcn36xx_hal_get_tpc_report_req_msg {
2950 struct wcn36xx_hal_msg_header header;
2951
2952 u8 sta[ETH_ALEN];
2953 u8 dialog_token;
2954 u8 txpower;
2955};
2956
2957struct wcn36xx_hal_get_tpc_report_rsp_msg {
2958 struct wcn36xx_hal_msg_header header;
2959
2960
2961 u32 status;
2962};
2963
2964struct wcn36xx_hal_send_probe_resp_req_msg {
2965 struct wcn36xx_hal_msg_header header;
2966
2967 u8 probe_resp_template[BEACON_TEMPLATE_SIZE];
2968 u32 probe_resp_template_len;
2969 u32 proxy_probe_req_valid_ie_bmap[8];
2970 u8 bssid[ETH_ALEN];
2971};
2972
2973struct send_probe_resp_rsp_msg {
2974 struct wcn36xx_hal_msg_header header;
2975
2976
2977 u32 status;
2978};
2979
2980struct send_unknown_frame_rx_ind_msg {
2981 struct wcn36xx_hal_msg_header header;
2982
2983
2984 u32 status;
2985};
2986
2987struct wcn36xx_hal_delete_sta_context_ind_msg {
2988 struct wcn36xx_hal_msg_header header;
2989
2990 u16 aid;
2991 u16 sta_id;
2992
2993
2994 u8 bssid[ETH_ALEN];
2995
2996
2997 u8 addr2[ETH_ALEN];
2998
2999
3000 u16 reason_code;
3001} __packed;
3002
3003struct indicate_del_sta {
3004 struct wcn36xx_hal_msg_header header;
3005 u8 aid;
3006 u8 sta_index;
3007 u8 bss_index;
3008 u8 reason_code;
3009 u32 status;
3010};
3011
3012struct bt_amp_event_msg {
3013 struct wcn36xx_hal_msg_header header;
3014
3015 enum bt_amp_event_type btAmpEventType;
3016};
3017
3018struct bt_amp_event_rsp {
3019 struct wcn36xx_hal_msg_header header;
3020
3021
3022 u32 status;
3023};
3024
3025struct tl_hal_flush_ac_req_msg {
3026 struct wcn36xx_hal_msg_header header;
3027
3028
3029 u8 sta_id;
3030
3031
3032 u8 tid;
3033};
3034
3035struct tl_hal_flush_ac_rsp_msg {
3036 struct wcn36xx_hal_msg_header header;
3037
3038
3039 u8 sta_id;
3040
3041
3042 u8 tid;
3043
3044
3045 u32 status;
3046};
3047
3048struct wcn36xx_hal_enter_imps_req_msg {
3049 struct wcn36xx_hal_msg_header header;
3050};
3051
3052struct wcn36xx_hal_exit_imps_req {
3053 struct wcn36xx_hal_msg_header header;
3054};
3055
3056struct wcn36xx_hal_enter_bmps_req_msg {
3057 struct wcn36xx_hal_msg_header header;
3058
3059 u8 bss_index;
3060
3061
3062#ifndef BUILD_QWPTTSTATIC
3063 u64 tbtt;
3064#endif
3065 u8 dtim_count;
3066
3067
3068
3069 u8 dtim_period;
3070
3071
3072 u32 rssi_filter_period;
3073
3074 u32 num_beacon_per_rssi_average;
3075 u8 rssi_filter_enable;
3076} __packed;
3077
3078struct wcn36xx_hal_exit_bmps_req_msg {
3079 struct wcn36xx_hal_msg_header header;
3080
3081 u8 send_data_null;
3082 u8 bss_index;
3083} __packed;
3084
3085struct wcn36xx_hal_missed_beacon_ind_msg {
3086 struct wcn36xx_hal_msg_header header;
3087
3088 u8 bss_index;
3089} __packed;
3090
3091
3092
3093
3094
3095
3096struct beacon_filter_ie {
3097 u8 element_id;
3098 u8 check_ie_presence;
3099 u8 offset;
3100 u8 value;
3101 u8 bitmask;
3102 u8 ref;
3103};
3104
3105struct wcn36xx_hal_add_bcn_filter_req_msg {
3106 struct wcn36xx_hal_msg_header header;
3107
3108 u16 capability_info;
3109 u16 capability_mask;
3110 u16 beacon_interval;
3111 u16 ie_num;
3112 u8 bss_index;
3113 u8 reserved;
3114};
3115
3116struct wcn36xx_hal_rem_bcn_filter_req {
3117 struct wcn36xx_hal_msg_header header;
3118
3119 u8 ie_Count;
3120 u8 rem_ie_id[1];
3121};
3122
3123#define WCN36XX_HAL_IPV4_ARP_REPLY_OFFLOAD 0
3124#define WCN36XX_HAL_IPV6_NEIGHBOR_DISCOVERY_OFFLOAD 1
3125#define WCN36XX_HAL_IPV6_NS_OFFLOAD 2
3126#define WCN36XX_HAL_IPV6_ADDR_LEN 16
3127#define WCN36XX_HAL_OFFLOAD_DISABLE 0
3128#define WCN36XX_HAL_OFFLOAD_ENABLE 1
3129#define WCN36XX_HAL_OFFLOAD_BCAST_FILTER_ENABLE 0x2
3130#define WCN36XX_HAL_OFFLOAD_ARP_AND_BCAST_FILTER_ENABLE \
3131 (HAL_OFFLOAD_ENABLE|HAL_OFFLOAD_BCAST_FILTER_ENABLE)
3132
3133struct wcn36xx_hal_ns_offload_params {
3134 u8 src_ipv6_addr[WCN36XX_HAL_IPV6_ADDR_LEN];
3135 u8 self_ipv6_addr[WCN36XX_HAL_IPV6_ADDR_LEN];
3136
3137
3138 u8 target_ipv6_addr1[WCN36XX_HAL_IPV6_ADDR_LEN];
3139 u8 target_ipv6_addr2[WCN36XX_HAL_IPV6_ADDR_LEN];
3140
3141 u8 self_addr[ETH_ALEN];
3142 u8 src_ipv6_addr_valid:1;
3143 u8 target_ipv6_addr1_valid:1;
3144 u8 target_ipv6_addr2_valid:1;
3145 u8 reserved1:5;
3146
3147
3148 u8 reserved2;
3149
3150
3151 u32 slot_index;
3152 u8 bss_index;
3153};
3154
3155struct wcn36xx_hal_host_offload_req {
3156 u8 offload_Type;
3157
3158
3159 u8 enable;
3160
3161 union {
3162 u8 host_ipv4_addr[4];
3163 u8 host_ipv6_addr[WCN36XX_HAL_IPV6_ADDR_LEN];
3164 } u;
3165};
3166
3167struct wcn36xx_hal_host_offload_req_msg {
3168 struct wcn36xx_hal_msg_header header;
3169 struct wcn36xx_hal_host_offload_req host_offload_params;
3170 struct wcn36xx_hal_ns_offload_params ns_offload_params;
3171};
3172
3173
3174#define WCN36XX_HAL_KEEP_ALIVE_NULL_PKT 1
3175#define WCN36XX_HAL_KEEP_ALIVE_UNSOLICIT_ARP_RSP 2
3176
3177
3178#define WCN36XX_HAL_KEEP_ALIVE_DISABLE 0
3179#define WCN36XX_HAL_KEEP_ALIVE_ENABLE 1
3180#define WCN36XX_KEEP_ALIVE_TIME_PERIOD 30
3181
3182
3183struct wcn36xx_hal_keep_alive_req_msg {
3184 struct wcn36xx_hal_msg_header header;
3185
3186 u8 packet_type;
3187 u32 time_period;
3188 u8 host_ipv4_addr[WCN36XX_HAL_IPV4_ADDR_LEN];
3189 u8 dest_ipv4_addr[WCN36XX_HAL_IPV4_ADDR_LEN];
3190 u8 dest_addr[ETH_ALEN];
3191 u8 bss_index;
3192} __packed;
3193
3194struct wcn36xx_hal_rssi_threshold_req_msg {
3195 struct wcn36xx_hal_msg_header header;
3196
3197 s8 threshold1:8;
3198 s8 threshold2:8;
3199 s8 threshold3:8;
3200 u8 thres1_pos_notify:1;
3201 u8 thres1_neg_notify:1;
3202 u8 thres2_pos_notify:1;
3203 u8 thres2_neg_notify:1;
3204 u8 thres3_pos_notify:1;
3205 u8 thres3_neg_notify:1;
3206 u8 reserved10:2;
3207};
3208
3209struct wcn36xx_hal_enter_uapsd_req_msg {
3210 struct wcn36xx_hal_msg_header header;
3211
3212 u8 bk_delivery:1;
3213 u8 be_delivery:1;
3214 u8 vi_delivery:1;
3215 u8 vo_delivery:1;
3216 u8 bk_trigger:1;
3217 u8 be_trigger:1;
3218 u8 vi_trigger:1;
3219 u8 vo_trigger:1;
3220 u8 bss_index;
3221};
3222
3223struct wcn36xx_hal_exit_uapsd_req_msg {
3224 struct wcn36xx_hal_msg_header header;
3225 u8 bss_index;
3226};
3227
3228#define WCN36XX_HAL_WOWL_BCAST_PATTERN_MAX_SIZE 128
3229#define WCN36XX_HAL_WOWL_BCAST_MAX_NUM_PATTERNS 16
3230
3231struct wcn36xx_hal_wowl_add_bcast_ptrn_req_msg {
3232 struct wcn36xx_hal_msg_header header;
3233
3234
3235 u8 id;
3236
3237
3238
3239 u8 byte_Offset;
3240
3241
3242 u8 size;
3243
3244
3245 u8 pattern[WCN36XX_HAL_WOWL_BCAST_PATTERN_MAX_SIZE];
3246
3247
3248 u8 mask_size;
3249
3250
3251 u8 mask[WCN36XX_HAL_WOWL_BCAST_PATTERN_MAX_SIZE];
3252
3253
3254 u8 extra[WCN36XX_HAL_WOWL_BCAST_PATTERN_MAX_SIZE];
3255
3256
3257 u8 mask_extra[WCN36XX_HAL_WOWL_BCAST_PATTERN_MAX_SIZE];
3258
3259 u8 bss_index;
3260};
3261
3262struct wcn36xx_hal_wow_del_bcast_ptrn_req_msg {
3263 struct wcn36xx_hal_msg_header header;
3264
3265
3266 u8 id;
3267 u8 bss_index;
3268};
3269
3270struct wcn36xx_hal_wowl_enter_req_msg {
3271 struct wcn36xx_hal_msg_header header;
3272
3273
3274 u8 magic_packet_enable;
3275
3276
3277 u8 magic_pattern[ETH_ALEN];
3278
3279
3280
3281
3282
3283
3284 u8 pattern_filtering_enable;
3285
3286
3287
3288
3289
3290
3291
3292 u8 ucast_pattern_filtering_enable;
3293
3294
3295
3296
3297
3298 u8 wow_channel_switch_receive;
3299
3300
3301
3302
3303
3304 u8 wow_deauth_receive;
3305
3306
3307
3308
3309
3310 u8 wow_disassoc_receive;
3311
3312
3313
3314
3315
3316
3317 u8 wow_max_missed_beacons;
3318
3319
3320
3321
3322
3323
3324 u8 wow_max_sleep;
3325
3326
3327
3328
3329
3330 u8 wow_eap_id_request_enable;
3331
3332
3333
3334
3335 u8 wow_eapol_4way_enable;
3336
3337
3338
3339
3340 u8 wow_net_scan_offload_match;
3341
3342
3343
3344
3345 u8 wow_gtk_rekey_error;
3346
3347
3348
3349 u8 wow_bss_connection_loss;
3350
3351 u8 bss_index;
3352};
3353
3354struct wcn36xx_hal_wowl_exit_req_msg {
3355 struct wcn36xx_hal_msg_header header;
3356
3357 u8 bss_index;
3358};
3359
3360struct wcn36xx_hal_get_rssi_req_msg {
3361 struct wcn36xx_hal_msg_header header;
3362};
3363
3364struct wcn36xx_hal_get_roam_rssi_req_msg {
3365 struct wcn36xx_hal_msg_header header;
3366
3367
3368 u32 sta_id;
3369};
3370
3371struct wcn36xx_hal_set_uapsd_ac_params_req_msg {
3372 struct wcn36xx_hal_msg_header header;
3373
3374
3375 u8 sta_idx;
3376
3377
3378 u8 ac;
3379
3380
3381 u8 up;
3382
3383
3384 u32 service_interval;
3385
3386
3387 u32 suspend_interval;
3388
3389
3390 u32 delay_interval;
3391};
3392
3393struct wcn36xx_hal_configure_rxp_filter_req_msg {
3394 struct wcn36xx_hal_msg_header header;
3395
3396 u8 set_mcst_bcst_filter_setting;
3397 u8 set_mcst_bcst_filter;
3398};
3399
3400struct wcn36xx_hal_enter_imps_rsp_msg {
3401 struct wcn36xx_hal_msg_header header;
3402
3403
3404 u32 status;
3405};
3406
3407struct wcn36xx_hal_exit_imps_rsp_msg {
3408 struct wcn36xx_hal_msg_header header;
3409
3410
3411 u32 status;
3412};
3413
3414struct wcn36xx_hal_enter_bmps_rsp_msg {
3415 struct wcn36xx_hal_msg_header header;
3416
3417
3418 u32 status;
3419
3420 u8 bss_index;
3421} __packed;
3422
3423struct wcn36xx_hal_exit_bmps_rsp_msg {
3424 struct wcn36xx_hal_msg_header header;
3425
3426
3427 u32 status;
3428
3429 u8 bss_index;
3430} __packed;
3431
3432struct wcn36xx_hal_enter_uapsd_rsp_msg {
3433 struct wcn36xx_hal_msg_header header;
3434
3435
3436 u32 status;
3437
3438 u8 bss_index;
3439};
3440
3441struct wcn36xx_hal_exit_uapsd_rsp_msg {
3442 struct wcn36xx_hal_msg_header header;
3443
3444
3445 u32 status;
3446
3447 u8 bss_index;
3448};
3449
3450struct wcn36xx_hal_rssi_notification_ind_msg {
3451 struct wcn36xx_hal_msg_header header;
3452
3453 u32 rssi_thres1_pos_cross:1;
3454 u32 rssi_thres1_neg_cross:1;
3455 u32 rssi_thres2_pos_cross:1;
3456 u32 rssi_thres2_neg_cross:1;
3457 u32 rssi_thres3_pos_cross:1;
3458 u32 rssi_thres3_neg_cross:1;
3459 u32 avg_rssi:8;
3460 u32 reserved:18;
3461
3462};
3463
3464struct wcn36xx_hal_get_rssio_rsp_msg {
3465 struct wcn36xx_hal_msg_header header;
3466
3467
3468 u32 status;
3469 s8 rssi;
3470
3471};
3472
3473struct wcn36xx_hal_get_roam_rssi_rsp_msg {
3474 struct wcn36xx_hal_msg_header header;
3475
3476
3477 u32 status;
3478
3479 u8 sta_id;
3480 s8 rssi;
3481};
3482
3483struct wcn36xx_hal_wowl_enter_rsp_msg {
3484 struct wcn36xx_hal_msg_header header;
3485
3486
3487 u32 status;
3488 u8 bss_index;
3489};
3490
3491struct wcn36xx_hal_wowl_exit_rsp_msg {
3492 struct wcn36xx_hal_msg_header header;
3493
3494
3495 u32 status;
3496 u8 bss_index;
3497};
3498
3499struct wcn36xx_hal_add_bcn_filter_rsp_msg {
3500 struct wcn36xx_hal_msg_header header;
3501
3502
3503 u32 status;
3504};
3505
3506struct wcn36xx_hal_rem_bcn_filter_rsp_msg {
3507 struct wcn36xx_hal_msg_header header;
3508
3509
3510 u32 status;
3511};
3512
3513struct wcn36xx_hal_add_wowl_bcast_ptrn_rsp_msg {
3514 struct wcn36xx_hal_msg_header header;
3515
3516
3517 u32 status;
3518 u8 bss_index;
3519};
3520
3521struct wcn36xx_hal_del_wowl_bcast_ptrn_rsp_msg {
3522 struct wcn36xx_hal_msg_header header;
3523
3524
3525 u32 status;
3526 u8 bss_index;
3527};
3528
3529struct wcn36xx_hal_host_offload_rsp_msg {
3530 struct wcn36xx_hal_msg_header header;
3531
3532
3533 u32 status;
3534};
3535
3536struct wcn36xx_hal_keep_alive_rsp_msg {
3537 struct wcn36xx_hal_msg_header header;
3538
3539
3540 u32 status;
3541};
3542
3543struct wcn36xx_hal_set_rssi_thresh_rsp_msg {
3544 struct wcn36xx_hal_msg_header header;
3545
3546
3547 u32 status;
3548};
3549
3550struct wcn36xx_hal_set_uapsd_ac_params_rsp_msg {
3551 struct wcn36xx_hal_msg_header header;
3552
3553
3554 u32 status;
3555};
3556
3557struct wcn36xx_hal_configure_rxp_filter_rsp_msg {
3558 struct wcn36xx_hal_msg_header header;
3559
3560
3561 u32 status;
3562};
3563
3564struct set_max_tx_pwr_req {
3565 struct wcn36xx_hal_msg_header header;
3566
3567
3568
3569
3570 u8 bssid[ETH_ALEN];
3571
3572 u8 self_addr[ETH_ALEN];
3573
3574
3575 u8 power;
3576};
3577
3578struct set_max_tx_pwr_rsp_msg {
3579 struct wcn36xx_hal_msg_header header;
3580
3581
3582 u8 power;
3583
3584
3585 u32 status;
3586};
3587
3588struct set_tx_pwr_req_msg {
3589 struct wcn36xx_hal_msg_header header;
3590
3591
3592 u32 tx_power;
3593
3594 u8 bss_index;
3595};
3596
3597struct set_tx_pwr_rsp_msg {
3598 struct wcn36xx_hal_msg_header header;
3599
3600
3601 u32 status;
3602};
3603
3604struct get_tx_pwr_req_msg {
3605 struct wcn36xx_hal_msg_header header;
3606
3607 u8 sta_id;
3608};
3609
3610struct get_tx_pwr_rsp_msg {
3611 struct wcn36xx_hal_msg_header header;
3612
3613
3614 u32 status;
3615
3616
3617 u32 tx_power;
3618};
3619
3620struct set_p2p_gonoa_req_msg {
3621 struct wcn36xx_hal_msg_header header;
3622
3623 u8 opp_ps;
3624 u32 ct_window;
3625 u8 count;
3626 u32 duration;
3627 u32 interval;
3628 u32 single_noa_duration;
3629 u8 ps_selection;
3630};
3631
3632struct set_p2p_gonoa_rsp_msg {
3633 struct wcn36xx_hal_msg_header header;
3634
3635
3636 u32 status;
3637};
3638
3639struct wcn36xx_hal_add_sta_self_req {
3640 struct wcn36xx_hal_msg_header header;
3641
3642 u8 self_addr[ETH_ALEN];
3643 u32 status;
3644} __packed;
3645
3646struct wcn36xx_hal_add_sta_self_rsp_msg {
3647 struct wcn36xx_hal_msg_header header;
3648
3649
3650 u32 status;
3651
3652
3653 u8 self_sta_index;
3654
3655
3656 u8 dpu_index;
3657
3658
3659 u8 dpu_signature;
3660} __packed;
3661
3662struct wcn36xx_hal_del_sta_self_req_msg {
3663 struct wcn36xx_hal_msg_header header;
3664
3665 u8 self_addr[ETH_ALEN];
3666} __packed;
3667
3668struct wcn36xx_hal_del_sta_self_rsp_msg {
3669 struct wcn36xx_hal_msg_header header;
3670
3671
3672 u32 status;
3673
3674 u8 self_addr[ETH_ALEN];
3675} __packed;
3676
3677struct aggr_add_ts_req {
3678 struct wcn36xx_hal_msg_header header;
3679
3680
3681 u16 sta_idx;
3682
3683
3684
3685
3686 u16 tspec_index;
3687
3688
3689 struct wcn36xx_hal_tspec_ie tspec[WCN36XX_HAL_MAX_AC];
3690
3691
3692
3693
3694 u8 uapsd;
3695
3696
3697
3698
3699 u32 service_interval[WCN36XX_HAL_MAX_AC];
3700
3701
3702 u32 suspend_interval[WCN36XX_HAL_MAX_AC];
3703
3704
3705 u32 delay_interval[WCN36XX_HAL_MAX_AC];
3706};
3707
3708struct aggr_add_ts_rsp_msg {
3709 struct wcn36xx_hal_msg_header header;
3710
3711
3712 u32 status0;
3713
3714
3715 u32 status1;
3716};
3717
3718struct wcn36xx_hal_configure_apps_cpu_wakeup_state_req_msg {
3719 struct wcn36xx_hal_msg_header header;
3720
3721 u8 is_apps_cpu_awake;
3722};
3723
3724struct wcn36xx_hal_configure_apps_cpu_wakeup_state_rsp_msg {
3725 struct wcn36xx_hal_msg_header header;
3726
3727
3728 u32 status;
3729};
3730
3731struct wcn36xx_hal_dump_cmd_req_msg {
3732 struct wcn36xx_hal_msg_header header;
3733
3734 u32 arg1;
3735 u32 arg2;
3736 u32 arg3;
3737 u32 arg4;
3738 u32 arg5;
3739} __packed;
3740
3741struct wcn36xx_hal_dump_cmd_rsp_msg {
3742 struct wcn36xx_hal_msg_header header;
3743
3744
3745 u32 status;
3746
3747
3748 u32 rsp_length;
3749
3750
3751
3752 u8 rsp_buffer[DUMPCMD_RSP_BUFFER];
3753} __packed;
3754
3755#define WLAN_COEX_IND_DATA_SIZE (4)
3756#define WLAN_COEX_IND_TYPE_DISABLE_HB_MONITOR (0)
3757#define WLAN_COEX_IND_TYPE_ENABLE_HB_MONITOR (1)
3758
3759struct coex_ind_msg {
3760 struct wcn36xx_hal_msg_header header;
3761
3762
3763 u32 type;
3764
3765
3766 u32 data[WLAN_COEX_IND_DATA_SIZE];
3767};
3768
3769struct wcn36xx_hal_tx_compl_ind_msg {
3770 struct wcn36xx_hal_msg_header header;
3771
3772
3773 u32 status;
3774};
3775
3776struct wcn36xx_hal_wlan_host_suspend_ind_msg {
3777 struct wcn36xx_hal_msg_header header;
3778
3779 u32 configured_mcst_bcst_filter_setting;
3780 u32 active_session_count;
3781};
3782
3783struct wcn36xx_hal_wlan_exclude_unencrpted_ind_msg {
3784 struct wcn36xx_hal_msg_header header;
3785
3786 u8 dot11_exclude_unencrypted;
3787 u8 bssid[ETH_ALEN];
3788};
3789
3790struct noa_attr_ind_msg {
3791 struct wcn36xx_hal_msg_header header;
3792
3793 u8 index;
3794 u8 opp_ps_flag;
3795 u16 ctwin;
3796
3797 u16 noa1_interval_count;
3798 u16 bss_index;
3799 u32 noa1_duration;
3800 u32 noa1_interval;
3801 u32 noa1_starttime;
3802
3803 u16 noa2_interval_count;
3804 u16 reserved2;
3805 u32 noa2_duration;
3806 u32 noa2_interval;
3807 u32 noa2_start_time;
3808
3809 u32 status;
3810};
3811
3812struct noa_start_ind_msg {
3813 struct wcn36xx_hal_msg_header header;
3814
3815 u32 status;
3816 u32 bss_index;
3817};
3818
3819struct wcn36xx_hal_wlan_host_resume_req_msg {
3820 struct wcn36xx_hal_msg_header header;
3821
3822 u8 configured_mcst_bcst_filter_setting;
3823};
3824
3825struct wcn36xx_hal_host_resume_rsp_msg {
3826 struct wcn36xx_hal_msg_header header;
3827
3828
3829 u32 status;
3830};
3831
3832struct wcn36xx_hal_del_ba_ind_msg {
3833 struct wcn36xx_hal_msg_header header;
3834
3835 u16 sta_idx;
3836
3837
3838 u8 peer_addr[ETH_ALEN];
3839
3840
3841 u8 ba_tid;
3842
3843
3844
3845
3846
3847 u8 direction;
3848
3849 u32 reason_code;
3850
3851
3852 u8 bssid[ETH_ALEN];
3853};
3854
3855
3856
3857
3858#define WCN36XX_HAL_PNO_MAX_NETW_CHANNELS 26
3859
3860
3861#define WCN36XX_HAL_PNO_MAX_NETW_CHANNELS_EX 60
3862
3863
3864#define WCN36XX_HAL_PNO_MAX_SUPP_NETWORKS 16
3865
3866
3867#define WCN36XX_HAL_PNO_MAX_SCAN_TIMERS 10
3868
3869
3870#define WCN36XX_HAL_PNO_MAX_PROBE_SIZE 450
3871
3872
3873
3874
3875
3876
3877
3878
3879
3880
3881enum pno_mode {
3882 PNO_MODE_IMMEDIATE,
3883 PNO_MODE_ON_SUSPEND,
3884 PNO_MODE_ON_RESUME,
3885 PNO_MODE_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
3886};
3887
3888
3889enum auth_type {
3890 AUTH_TYPE_ANY = 0,
3891 AUTH_TYPE_OPEN_SYSTEM = 1,
3892
3893
3894 AUTH_TYPE_WPA = 2,
3895 AUTH_TYPE_WPA_PSK = 3,
3896
3897 AUTH_TYPE_RSN = 4,
3898 AUTH_TYPE_RSN_PSK = 5,
3899 AUTH_TYPE_FT_RSN = 6,
3900 AUTH_TYPE_FT_RSN_PSK = 7,
3901 AUTH_TYPE_WAPI_WAI_CERTIFICATE = 8,
3902 AUTH_TYPE_WAPI_WAI_PSK = 9,
3903
3904 AUTH_TYPE_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
3905};
3906
3907
3908enum ed_type {
3909 ED_ANY = 0,
3910 ED_NONE = 1,
3911 ED_WEP = 2,
3912 ED_TKIP = 3,
3913 ED_CCMP = 4,
3914 ED_WPI = 5,
3915
3916 ED_TYPE_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
3917};
3918
3919
3920enum ssid_bcast_type {
3921 BCAST_UNKNOWN = 0,
3922 BCAST_NORMAL = 1,
3923 BCAST_HIDDEN = 2,
3924
3925 BCAST_TYPE_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
3926};
3927
3928
3929struct network_type {
3930
3931 struct wcn36xx_hal_mac_ssid ssid;
3932
3933
3934 enum auth_type authentication;
3935
3936
3937 enum ed_type encryption;
3938
3939
3940
3941 u8 channel_count;
3942 u8 channels[WCN36XX_HAL_PNO_MAX_NETW_CHANNELS];
3943
3944
3945 u8 rssi_threshold;
3946};
3947
3948struct scan_timer {
3949
3950 u32 value;
3951
3952
3953
3954 u32 repeat;
3955
3956
3957
3958
3959};
3960
3961
3962struct scan_timers_type {
3963
3964 u8 count;
3965
3966
3967
3968
3969
3970
3971
3972
3973 struct scan_timer values[WCN36XX_HAL_PNO_MAX_SCAN_TIMERS];
3974};
3975
3976
3977struct set_pref_netw_list_req {
3978 struct wcn36xx_hal_msg_header header;
3979
3980
3981 u32 enable;
3982
3983
3984 enum pno_mode mode;
3985
3986
3987 u32 networks_count;
3988
3989
3990 struct network_type networks[WCN36XX_HAL_PNO_MAX_SUPP_NETWORKS];
3991
3992
3993 struct scan_timers_type scan_timers;
3994
3995
3996 u16 band_24g_probe_size;
3997 u8 band_24g_probe_template[WCN36XX_HAL_PNO_MAX_PROBE_SIZE];
3998
3999
4000 u16 band_5g_probe_size;
4001 u8 band_5g_probe_template[WCN36XX_HAL_PNO_MAX_PROBE_SIZE];
4002};
4003
4004
4005struct network_type_new {
4006
4007 struct wcn36xx_hal_mac_ssid ssid;
4008
4009
4010 enum auth_type authentication;
4011
4012
4013 enum ed_type encryption;
4014
4015
4016 enum ssid_bcast_type bcast_network_type;
4017
4018
4019
4020 u8 channel_count;
4021 u8 channels[WCN36XX_HAL_PNO_MAX_NETW_CHANNELS];
4022
4023
4024 u8 rssi_threshold;
4025};
4026
4027
4028struct set_pref_netw_list_req_new {
4029 struct wcn36xx_hal_msg_header header;
4030
4031
4032 u32 enable;
4033
4034
4035 enum pno_mode mode;
4036
4037
4038 u32 networks_count;
4039
4040
4041 struct network_type_new networks[WCN36XX_HAL_PNO_MAX_SUPP_NETWORKS];
4042
4043
4044 struct scan_timers_type scan_timers;
4045
4046
4047 u16 band_24g_probe_size;
4048 u8 band_24g_probe_template[WCN36XX_HAL_PNO_MAX_PROBE_SIZE];
4049
4050
4051 u16 band_5g_probe_size;
4052 u8 band_5g_probe_template[WCN36XX_HAL_PNO_MAX_PROBE_SIZE];
4053};
4054
4055
4056struct set_pref_netw_list_resp {
4057 struct wcn36xx_hal_msg_header header;
4058
4059
4060
4061 u32 status;
4062};
4063
4064
4065struct pref_netw_found_ind {
4066
4067 struct wcn36xx_hal_msg_header header;
4068
4069
4070 struct wcn36xx_hal_mac_ssid ssid;
4071
4072
4073 u8 rssi;
4074};
4075
4076
4077struct set_rssi_filter_req {
4078 struct wcn36xx_hal_msg_header header;
4079
4080
4081 u8 rssi_threshold;
4082};
4083
4084
4085struct set_rssi_filter_resp {
4086 struct wcn36xx_hal_msg_header header;
4087
4088
4089 u32 status;
4090};
4091
4092
4093
4094struct wcn36xx_hal_update_scan_params_req {
4095
4096 struct wcn36xx_hal_msg_header header;
4097
4098
4099 u8 dot11d_enabled;
4100
4101
4102 u8 dot11d_resolved;
4103
4104
4105 u8 channel_count;
4106 u8 channels[WCN36XX_HAL_PNO_MAX_NETW_CHANNELS];
4107
4108
4109 u16 active_min_ch_time;
4110
4111
4112 u16 active_max_ch_time;
4113
4114
4115 u16 passive_min_ch_time;
4116
4117
4118 u16 passive_max_ch_time;
4119
4120
4121 enum phy_chan_bond_state state;
4122} __packed;
4123
4124
4125
4126struct wcn36xx_hal_update_scan_params_req_ex {
4127
4128 struct wcn36xx_hal_msg_header header;
4129
4130
4131 u8 dot11d_enabled;
4132
4133
4134 u8 dot11d_resolved;
4135
4136
4137 u8 channel_count;
4138 u8 channels[WCN36XX_HAL_PNO_MAX_NETW_CHANNELS_EX];
4139
4140
4141 u16 active_min_ch_time;
4142
4143
4144 u16 active_max_ch_time;
4145
4146
4147 u16 passive_min_ch_time;
4148
4149
4150 u16 passive_max_ch_time;
4151
4152
4153 enum phy_chan_bond_state state;
4154} __packed;
4155
4156
4157
4158struct wcn36xx_hal_update_scan_params_resp {
4159
4160 struct wcn36xx_hal_msg_header header;
4161
4162
4163 u32 status;
4164} __packed;
4165
4166struct wcn36xx_hal_set_tx_per_tracking_req_msg {
4167 struct wcn36xx_hal_msg_header header;
4168
4169
4170 u8 tx_per_tracking_enable;
4171
4172
4173 u8 tx_per_tracking_period;
4174
4175
4176 u8 tx_per_tracking_ratio;
4177
4178
4179
4180 u32 tx_per_tracking_watermark;
4181};
4182
4183struct wcn36xx_hal_set_tx_per_tracking_rsp_msg {
4184 struct wcn36xx_hal_msg_header header;
4185
4186
4187 u32 status;
4188
4189};
4190
4191struct tx_per_hit_ind_msg {
4192 struct wcn36xx_hal_msg_header header;
4193};
4194
4195
4196#define WCN36XX_HAL_PROTOCOL_DATA_LEN 8
4197#define WCN36XX_HAL_MAX_NUM_MULTICAST_ADDRESS 240
4198#define WCN36XX_HAL_MAX_NUM_FILTERS 20
4199#define WCN36XX_HAL_MAX_CMP_PER_FILTER 10
4200
4201enum wcn36xx_hal_receive_packet_filter_type {
4202 HAL_RCV_FILTER_TYPE_INVALID,
4203 HAL_RCV_FILTER_TYPE_FILTER_PKT,
4204 HAL_RCV_FILTER_TYPE_BUFFER_PKT,
4205 HAL_RCV_FILTER_TYPE_MAX_ENUM_SIZE
4206};
4207
4208enum wcn36xx_hal_rcv_pkt_flt_protocol_type {
4209 HAL_FILTER_PROTO_TYPE_INVALID,
4210 HAL_FILTER_PROTO_TYPE_MAC,
4211 HAL_FILTER_PROTO_TYPE_ARP,
4212 HAL_FILTER_PROTO_TYPE_IPV4,
4213 HAL_FILTER_PROTO_TYPE_IPV6,
4214 HAL_FILTER_PROTO_TYPE_UDP,
4215 HAL_FILTER_PROTO_TYPE_MAX
4216};
4217
4218enum wcn36xx_hal_rcv_pkt_flt_cmp_flag_type {
4219 HAL_FILTER_CMP_TYPE_INVALID,
4220 HAL_FILTER_CMP_TYPE_EQUAL,
4221 HAL_FILTER_CMP_TYPE_MASK_EQUAL,
4222 HAL_FILTER_CMP_TYPE_NOT_EQUAL,
4223 HAL_FILTER_CMP_TYPE_MAX
4224};
4225
4226struct wcn36xx_hal_rcv_pkt_filter_params {
4227 u8 protocol_layer;
4228 u8 cmp_flag;
4229
4230
4231 u16 data_length;
4232
4233
4234 u8 data_offset;
4235
4236
4237 u8 reserved;
4238
4239
4240 u8 compare_data[WCN36XX_HAL_PROTOCOL_DATA_LEN];
4241
4242
4243 u8 data_mask[WCN36XX_HAL_PROTOCOL_DATA_LEN];
4244};
4245
4246struct wcn36xx_hal_sessionized_rcv_pkt_filter_cfg_type {
4247 u8 id;
4248 u8 type;
4249 u8 params_count;
4250 u32 coleasce_time;
4251 u8 bss_index;
4252 struct wcn36xx_hal_rcv_pkt_filter_params params[1];
4253};
4254
4255struct wcn36xx_hal_set_rcv_pkt_filter_req_msg {
4256 struct wcn36xx_hal_msg_header header;
4257
4258 u8 id;
4259 u8 type;
4260 u8 params_count;
4261 u32 coalesce_time;
4262 struct wcn36xx_hal_rcv_pkt_filter_params params[1];
4263};
4264
4265struct wcn36xx_hal_rcv_flt_mc_addr_list_type {
4266
4267 u8 data_offset;
4268
4269 u32 mc_addr_count;
4270 u8 mc_addr[WCN36XX_HAL_MAX_NUM_MULTICAST_ADDRESS][ETH_ALEN];
4271 u8 bss_index;
4272} __packed;
4273
4274struct wcn36xx_hal_set_pkt_filter_rsp_msg {
4275 struct wcn36xx_hal_msg_header header;
4276
4277
4278 u32 status;
4279
4280 u8 bss_index;
4281};
4282
4283struct wcn36xx_hal_rcv_flt_pkt_match_cnt_req_msg {
4284 struct wcn36xx_hal_msg_header header;
4285
4286 u8 bss_index;
4287};
4288
4289struct wcn36xx_hal_rcv_flt_pkt_match_cnt {
4290 u8 id;
4291 u32 match_cnt;
4292};
4293
4294struct wcn36xx_hal_rcv_flt_pkt_match_cnt_rsp_msg {
4295 struct wcn36xx_hal_msg_header header;
4296
4297
4298 u32 status;
4299
4300 u32 match_count;
4301 struct wcn36xx_hal_rcv_flt_pkt_match_cnt
4302 matches[WCN36XX_HAL_MAX_NUM_FILTERS];
4303 u8 bss_index;
4304};
4305
4306struct wcn36xx_hal_rcv_flt_pkt_clear_param {
4307
4308 u32 status;
4309 u8 id;
4310 u8 bss_index;
4311};
4312
4313struct wcn36xx_hal_rcv_flt_pkt_clear_req_msg {
4314 struct wcn36xx_hal_msg_header header;
4315 struct wcn36xx_hal_rcv_flt_pkt_clear_param param;
4316};
4317
4318struct wcn36xx_hal_rcv_flt_pkt_clear_rsp_msg {
4319 struct wcn36xx_hal_msg_header header;
4320 struct wcn36xx_hal_rcv_flt_pkt_clear_param param;
4321};
4322
4323struct wcn36xx_hal_rcv_flt_pkt_set_mc_list_req_msg {
4324 struct wcn36xx_hal_msg_header header;
4325 struct wcn36xx_hal_rcv_flt_mc_addr_list_type mc_addr_list;
4326} __packed;
4327
4328struct wcn36xx_hal_rcv_flt_pkt_set_mc_list_rsp_msg {
4329 struct wcn36xx_hal_msg_header header;
4330 u32 status;
4331 u8 bss_index;
4332};
4333
4334
4335
4336struct wcn36xx_hal_set_power_params_req_msg {
4337 struct wcn36xx_hal_msg_header header;
4338
4339
4340 u32 ignore_dtim;
4341
4342
4343 u32 dtim_period;
4344
4345
4346 u32 listen_interval;
4347
4348
4349 u32 bcast_mcast_filter;
4350
4351
4352 u32 enable_bet;
4353
4354
4355 u32 bet_interval;
4356} __packed;
4357
4358struct wcn36xx_hal_set_power_params_resp {
4359
4360 struct wcn36xx_hal_msg_header header;
4361
4362
4363 u32 status;
4364} __packed;
4365
4366
4367
4368enum place_holder_in_cap_bitmap {
4369 MCC = 0,
4370 P2P = 1,
4371 DOT11AC = 2,
4372 SLM_SESSIONIZATION = 3,
4373 DOT11AC_OPMODE = 4,
4374 SAP32STA = 5,
4375 TDLS = 6,
4376 P2P_GO_NOA_DECOUPLE_INIT_SCAN = 7,
4377 WLANACTIVE_OFFLOAD = 8,
4378 BEACON_OFFLOAD = 9,
4379 SCAN_OFFLOAD = 10,
4380 ROAM_OFFLOAD = 11,
4381 BCN_MISS_OFFLOAD = 12,
4382 STA_POWERSAVE = 13,
4383 STA_ADVANCED_PWRSAVE = 14,
4384 AP_UAPSD = 15,
4385 AP_DFS = 16,
4386 BLOCKACK = 17,
4387 PHY_ERR = 18,
4388 BCN_FILTER = 19,
4389 RTT = 20,
4390 RATECTRL = 21,
4391 WOW = 22,
4392 WLAN_ROAM_SCAN_OFFLOAD = 23,
4393 SPECULATIVE_PS_POLL = 24,
4394 SCAN_SCH = 25,
4395 IBSS_HEARTBEAT_OFFLOAD = 26,
4396 WLAN_SCAN_OFFLOAD = 27,
4397 WLAN_PERIODIC_TX_PTRN = 28,
4398 ADVANCE_TDLS = 29,
4399 BATCH_SCAN = 30,
4400 FW_IN_TX_PATH = 31,
4401 EXTENDED_NSOFFLOAD_SLOT = 32,
4402 CH_SWITCH_V1 = 33,
4403 HT40_OBSS_SCAN = 34,
4404 UPDATE_CHANNEL_LIST = 35,
4405 WLAN_MCADDR_FLT = 36,
4406 WLAN_CH144 = 37,
4407 NAN = 38,
4408 TDLS_SCAN_COEXISTENCE = 39,
4409 LINK_LAYER_STATS_MEAS = 40,
4410 MU_MIMO = 41,
4411 EXTENDED_SCAN = 42,
4412 DYNAMIC_WMM_PS = 43,
4413 MAC_SPOOFED_SCAN = 44,
4414 BMU_ERROR_GENERIC_RECOVERY = 45,
4415 DISA = 46,
4416 FW_STATS = 47,
4417 WPS_PRBRSP_TMPL = 48,
4418 BCN_IE_FLT_DELTA = 49,
4419 TDLS_OFF_CHANNEL = 51,
4420 RTT3 = 52,
4421 MGMT_FRAME_LOGGING = 53,
4422 ENHANCED_TXBD_COMPLETION = 54,
4423 LOGGING_ENHANCEMENT = 55,
4424 EXT_SCAN_ENHANCED = 56,
4425 MEMORY_DUMP_SUPPORTED = 57,
4426 PER_PKT_STATS_SUPPORTED = 58,
4427 EXT_LL_STAT = 60,
4428 WIFI_CONFIG = 61,
4429 ANTENNA_DIVERSITY_SELECTION = 62,
4430
4431 MAX_FEATURE_SUPPORTED = 128,
4432};
4433
4434#define WCN36XX_HAL_CAPS_SIZE 4
4435
4436struct wcn36xx_hal_feat_caps_msg {
4437
4438 struct wcn36xx_hal_msg_header header;
4439
4440 u32 feat_caps[WCN36XX_HAL_CAPS_SIZE];
4441} __packed;
4442
4443
4444enum gtk_rekey_status {
4445 WCN36XX_HAL_GTK_REKEY_STATUS_SUCCESS = 0,
4446
4447
4448 WCN36XX_HAL_GTK_REKEY_STATUS_NOT_HANDLED = 1,
4449
4450
4451 WCN36XX_HAL_GTK_REKEY_STATUS_MIC_ERROR = 2,
4452
4453
4454 WCN36XX_HAL_GTK_REKEY_STATUS_DECRYPT_ERROR = 3,
4455
4456
4457 WCN36XX_HAL_GTK_REKEY_STATUS_REPLAY_ERROR = 4,
4458
4459
4460 WCN36XX_HAL_GTK_REKEY_STATUS_MISSING_KDE = 5,
4461
4462
4463 WCN36XX_HAL_GTK_REKEY_STATUS_MISSING_IGTK_KDE = 6,
4464
4465
4466 WCN36XX_HAL_GTK_REKEY_STATUS_INSTALL_ERROR = 7,
4467
4468
4469 WCN36XX_HAL_GTK_REKEY_STATUS_IGTK_INSTALL_ERROR = 8,
4470
4471
4472 WCN36XX_HAL_GTK_REKEY_STATUS_RESP_TX_ERROR = 9,
4473
4474
4475 WCN36XX_HAL_GTK_REKEY_STATUS_GEN_ERROR = 255
4476};
4477
4478
4479enum wake_reason_type {
4480 WCN36XX_HAL_WAKE_REASON_NONE = 0,
4481
4482
4483 WCN36XX_HAL_WAKE_REASON_MAGIC_PACKET = 1,
4484
4485
4486 WCN36XX_HAL_WAKE_REASON_PATTERN_MATCH = 2,
4487
4488
4489 WCN36XX_HAL_WAKE_REASON_EAPID_PACKET = 3,
4490
4491
4492 WCN36XX_HAL_WAKE_REASON_EAPOL4WAY_PACKET = 4,
4493
4494
4495 WCN36XX_HAL_WAKE_REASON_NETSCAN_OFFL_MATCH = 5,
4496
4497
4498 WCN36XX_HAL_WAKE_REASON_GTK_REKEY_STATUS = 6,
4499
4500
4501 WCN36XX_HAL_WAKE_REASON_BSS_CONN_LOST = 7,
4502};
4503
4504
4505
4506
4507
4508
4509
4510
4511
4512
4513
4514
4515
4516
4517
4518
4519struct wcn36xx_hal_wake_reason_ind {
4520 struct wcn36xx_hal_msg_header header;
4521
4522
4523 u32 reason;
4524
4525
4526 u32 reason_arg;
4527
4528
4529
4530
4531 u32 stored_data_len;
4532
4533
4534 u32 actual_data_len;
4535
4536
4537
4538 u8 data_start[1];
4539
4540 u32 bss_index:8;
4541 u32 reserved:24;
4542};
4543
4544#define WCN36XX_HAL_GTK_KEK_BYTES 16
4545#define WCN36XX_HAL_GTK_KCK_BYTES 16
4546
4547#define WCN36XX_HAL_GTK_OFFLOAD_FLAGS_DISABLE (1 << 0)
4548
4549#define GTK_SET_BSS_KEY_TAG 0x1234AA55
4550
4551struct wcn36xx_hal_gtk_offload_req_msg {
4552 struct wcn36xx_hal_msg_header header;
4553
4554
4555 u32 flags;
4556
4557
4558 u8 kck[WCN36XX_HAL_GTK_KCK_BYTES];
4559
4560
4561 u8 kek[WCN36XX_HAL_GTK_KEK_BYTES];
4562
4563
4564 u64 key_replay_counter;
4565
4566 u8 bss_index;
4567};
4568
4569struct wcn36xx_hal_gtk_offload_rsp_msg {
4570 struct wcn36xx_hal_msg_header header;
4571
4572
4573 u32 status;
4574
4575 u8 bss_index;
4576};
4577
4578struct wcn36xx_hal_gtk_offload_get_info_req_msg {
4579 struct wcn36xx_hal_msg_header header;
4580 u8 bss_index;
4581};
4582
4583struct wcn36xx_hal_gtk_offload_get_info_rsp_msg {
4584 struct wcn36xx_hal_msg_header header;
4585
4586
4587 u32 status;
4588
4589
4590 u32 last_rekey_status;
4591
4592
4593 u64 key_replay_counter;
4594
4595
4596 u32 total_rekey_count;
4597
4598
4599 u32 gtk_rekey_count;
4600
4601
4602 u32 igtk_rekey_count;
4603
4604 u8 bss_index;
4605};
4606
4607struct dhcp_info {
4608
4609 u8 device_mode;
4610
4611 u8 addr[ETH_ALEN];
4612};
4613
4614struct dhcp_ind_status {
4615 struct wcn36xx_hal_msg_header header;
4616
4617
4618 u32 status;
4619};
4620
4621
4622
4623
4624
4625
4626
4627
4628
4629
4630enum wcn36xx_hal_thermal_mitigation_mode_type {
4631 HAL_THERMAL_MITIGATION_MODE_INVALID = -1,
4632 HAL_THERMAL_MITIGATION_MODE_0,
4633 HAL_THERMAL_MITIGATION_MODE_1,
4634 HAL_THERMAL_MITIGATION_MODE_2,
4635 HAL_THERMAL_MITIGATION_MODE_MAX = WCN36XX_HAL_MAX_ENUM_SIZE,
4636};
4637
4638
4639
4640
4641
4642
4643
4644
4645
4646
4647
4648
4649
4650
4651
4652
4653
4654
4655
4656enum wcn36xx_hal_thermal_mitigation_level_type {
4657 HAL_THERMAL_MITIGATION_LEVEL_INVALID = -1,
4658 HAL_THERMAL_MITIGATION_LEVEL_0,
4659 HAL_THERMAL_MITIGATION_LEVEL_1,
4660 HAL_THERMAL_MITIGATION_LEVEL_2,
4661 HAL_THERMAL_MITIGATION_LEVEL_3,
4662 HAL_THERMAL_MITIGATION_LEVEL_4,
4663 HAL_THERMAL_MITIGATION_LEVEL_MAX = WCN36XX_HAL_MAX_ENUM_SIZE,
4664};
4665
4666
4667
4668struct set_thermal_mitigation_req_msg {
4669 struct wcn36xx_hal_msg_header header;
4670
4671
4672 enum wcn36xx_hal_thermal_mitigation_mode_type mode;
4673
4674
4675 enum wcn36xx_hal_thermal_mitigation_level_type level;
4676};
4677
4678struct set_thermal_mitigation_resp {
4679
4680 struct wcn36xx_hal_msg_header header;
4681
4682
4683 u32 status;
4684};
4685
4686
4687
4688struct stats_class_b_ind {
4689 struct wcn36xx_hal_msg_header header;
4690
4691
4692 u32 duration;
4693
4694
4695
4696
4697 u32 tx_bytes_pushed;
4698 u32 tx_packets_pushed;
4699
4700
4701 u32 rx_bytes_rcvd;
4702 u32 rx_packets_rcvd;
4703 u32 rx_time_total;
4704};
4705
4706#endif
4707