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17#ifndef _BRCMU_D11_H_
18#define _BRCMU_D11_H_
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21#define BRCMU_D11N_IOTYPE 1
22#define BRCMU_D11AC_IOTYPE 2
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30#define BRCMU_CHSPEC_INVALID 255
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34#define BRCMU_CHSPEC_CH_MASK 0x00ff
35#define BRCMU_CHSPEC_CH_SHIFT 0
36#define BRCMU_CHSPEC_CHL_MASK 0x000f
37#define BRCMU_CHSPEC_CHL_SHIFT 0
38#define BRCMU_CHSPEC_CHH_MASK 0x00f0
39#define BRCMU_CHSPEC_CHH_SHIFT 4
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46
47#define BRCMU_CHSPEC_D11N_SB_MASK 0x0300
48#define BRCMU_CHSPEC_D11N_SB_SHIFT 8
49#define BRCMU_CHSPEC_D11N_SB_L 0x0100
50#define BRCMU_CHSPEC_D11N_SB_U 0x0200
51#define BRCMU_CHSPEC_D11N_SB_N 0x0300
52#define BRCMU_CHSPEC_D11N_BW_MASK 0x0c00
53#define BRCMU_CHSPEC_D11N_BW_SHIFT 10
54#define BRCMU_CHSPEC_D11N_BW_10 0x0400
55#define BRCMU_CHSPEC_D11N_BW_20 0x0800
56#define BRCMU_CHSPEC_D11N_BW_40 0x0c00
57#define BRCMU_CHSPEC_D11N_BND_MASK 0x3000
58#define BRCMU_CHSPEC_D11N_BND_SHIFT 12
59#define BRCMU_CHSPEC_D11N_BND_5G 0x1000
60#define BRCMU_CHSPEC_D11N_BND_2G 0x2000
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67#define BRCMU_CHSPEC_D11AC_SB_MASK 0x0700
68#define BRCMU_CHSPEC_D11AC_SB_SHIFT 8
69#define BRCMU_CHSPEC_D11AC_SB_LLL 0x0000
70#define BRCMU_CHSPEC_D11AC_SB_LLU 0x0100
71#define BRCMU_CHSPEC_D11AC_SB_LUL 0x0200
72#define BRCMU_CHSPEC_D11AC_SB_LUU 0x0300
73#define BRCMU_CHSPEC_D11AC_SB_ULL 0x0400
74#define BRCMU_CHSPEC_D11AC_SB_ULU 0x0500
75#define BRCMU_CHSPEC_D11AC_SB_UUL 0x0600
76#define BRCMU_CHSPEC_D11AC_SB_UUU 0x0700
77#define BRCMU_CHSPEC_D11AC_SB_LL BRCMU_CHSPEC_D11AC_SB_LLL
78#define BRCMU_CHSPEC_D11AC_SB_LU BRCMU_CHSPEC_D11AC_SB_LLU
79#define BRCMU_CHSPEC_D11AC_SB_UL BRCMU_CHSPEC_D11AC_SB_LUL
80#define BRCMU_CHSPEC_D11AC_SB_UU BRCMU_CHSPEC_D11AC_SB_LUU
81#define BRCMU_CHSPEC_D11AC_SB_L BRCMU_CHSPEC_D11AC_SB_LLL
82#define BRCMU_CHSPEC_D11AC_SB_U BRCMU_CHSPEC_D11AC_SB_LLU
83#define BRCMU_CHSPEC_D11AC_BW_MASK 0x3800
84#define BRCMU_CHSPEC_D11AC_BW_SHIFT 11
85#define BRCMU_CHSPEC_D11AC_BW_5 0x0000
86#define BRCMU_CHSPEC_D11AC_BW_10 0x0800
87#define BRCMU_CHSPEC_D11AC_BW_20 0x1000
88#define BRCMU_CHSPEC_D11AC_BW_40 0x1800
89#define BRCMU_CHSPEC_D11AC_BW_80 0x2000
90#define BRCMU_CHSPEC_D11AC_BW_160 0x2800
91#define BRCMU_CHSPEC_D11AC_BW_8080 0x3000
92#define BRCMU_CHSPEC_D11AC_BND_MASK 0xc000
93#define BRCMU_CHSPEC_D11AC_BND_SHIFT 14
94#define BRCMU_CHSPEC_D11AC_BND_2G 0x0000
95#define BRCMU_CHSPEC_D11AC_BND_3G 0x4000
96#define BRCMU_CHSPEC_D11AC_BND_4G 0x8000
97#define BRCMU_CHSPEC_D11AC_BND_5G 0xc000
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99#define BRCMU_CHAN_BAND_2G 0
100#define BRCMU_CHAN_BAND_5G 1
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102enum brcmu_chan_bw {
103 BRCMU_CHAN_BW_20,
104 BRCMU_CHAN_BW_40,
105 BRCMU_CHAN_BW_80,
106 BRCMU_CHAN_BW_80P80,
107 BRCMU_CHAN_BW_160,
108};
109
110enum brcmu_chan_sb {
111 BRCMU_CHAN_SB_NONE = -1,
112 BRCMU_CHAN_SB_LLL,
113 BRCMU_CHAN_SB_LLU,
114 BRCMU_CHAN_SB_LUL,
115 BRCMU_CHAN_SB_LUU,
116 BRCMU_CHAN_SB_ULL,
117 BRCMU_CHAN_SB_ULU,
118 BRCMU_CHAN_SB_UUL,
119 BRCMU_CHAN_SB_UUU,
120 BRCMU_CHAN_SB_L = BRCMU_CHAN_SB_LLL,
121 BRCMU_CHAN_SB_U = BRCMU_CHAN_SB_LLU,
122 BRCMU_CHAN_SB_LL = BRCMU_CHAN_SB_LLL,
123 BRCMU_CHAN_SB_LU = BRCMU_CHAN_SB_LLU,
124 BRCMU_CHAN_SB_UL = BRCMU_CHAN_SB_LUL,
125 BRCMU_CHAN_SB_UU = BRCMU_CHAN_SB_LUU,
126};
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141struct brcmu_chan {
142 u16 chspec;
143 u8 chnum;
144 u8 control_ch_num;
145 u8 band;
146 enum brcmu_chan_bw bw;
147 enum brcmu_chan_sb sb;
148};
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158struct brcmu_d11inf {
159 u8 io_type;
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161 void (*encchspec)(struct brcmu_chan *ch);
162 void (*decchspec)(struct brcmu_chan *ch);
163};
164
165void brcmu_d11_attach(struct brcmu_d11inf *d11inf);
166
167#endif
168