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30#include "wifi.h"
31#include "core.h"
32#include "pci.h"
33#include "base.h"
34#include "ps.h"
35#include "efuse.h"
36#include <linux/interrupt.h>
37#include <linux/export.h>
38#include <linux/kmemleak.h>
39#include <linux/module.h>
40
41MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>");
42MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
43MODULE_AUTHOR("Larry Finger <Larry.FInger@lwfinger.net>");
44MODULE_LICENSE("GPL");
45MODULE_DESCRIPTION("PCI basic driver for rtlwifi");
46
47static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = {
48 INTEL_VENDOR_ID,
49 ATI_VENDOR_ID,
50 AMD_VENDOR_ID,
51 SIS_VENDOR_ID
52};
53
54static const u8 ac_to_hwq[] = {
55 VO_QUEUE,
56 VI_QUEUE,
57 BE_QUEUE,
58 BK_QUEUE
59};
60
61static u8 _rtl_mac_to_hwqueue(struct ieee80211_hw *hw,
62 struct sk_buff *skb)
63{
64 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
65 __le16 fc = rtl_get_fc(skb);
66 u8 queue_index = skb_get_queue_mapping(skb);
67
68 if (unlikely(ieee80211_is_beacon(fc)))
69 return BEACON_QUEUE;
70 if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc))
71 return MGNT_QUEUE;
72 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
73 if (ieee80211_is_nullfunc(fc))
74 return HIGH_QUEUE;
75
76 return ac_to_hwq[queue_index];
77}
78
79
80static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw)
81{
82 struct rtl_priv *rtlpriv = rtl_priv(hw);
83 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
84 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
85 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
86 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
87 u8 init_aspm;
88
89 ppsc->reg_rfps_level = 0;
90 ppsc->support_aspm = false;
91
92
93 ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm;
94 switch (rtlpci->const_pci_aspm) {
95 case 0:
96
97 break;
98
99 case 1:
100
101 ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM;
102 break;
103
104 case 2:
105
106 ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM |
107 RT_RF_OFF_LEVL_CLK_REQ);
108 break;
109
110 case 3:
111
112
113
114
115 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM);
116 ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM |
117 RT_RF_OFF_LEVL_CLK_REQ);
118 break;
119
120 case 4:
121
122
123
124
125 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM |
126 RT_RF_OFF_LEVL_CLK_REQ);
127 ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM;
128 break;
129 }
130
131 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
132
133
134 switch (rtlpci->const_hwsw_rfoff_d3) {
135 case 1:
136 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
137 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
138 break;
139
140 case 2:
141 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
142 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
143 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
144 break;
145
146 case 3:
147 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3;
148 break;
149 }
150
151
152 switch (rtlpci->const_support_pciaspm) {
153 case 0:{
154
155 bool support_aspm = false;
156 ppsc->support_aspm = support_aspm;
157 break;
158 }
159 case 1:{
160
161 bool support_aspm = true;
162 bool support_backdoor = true;
163 ppsc->support_aspm = support_aspm;
164
165
166
167
168
169 ppsc->support_backdoor = support_backdoor;
170
171 break;
172 }
173 case 2:
174
175 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) {
176 bool support_aspm = true;
177 ppsc->support_aspm = support_aspm;
178 }
179 break;
180 default:
181 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
182 "switch case not processed\n");
183 break;
184 }
185
186
187
188 pci_read_config_byte(rtlpci->pdev, 0x80, &init_aspm);
189 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8192SE &&
190 init_aspm == 0x43)
191 ppsc->support_aspm = false;
192}
193
194static bool _rtl_pci_platform_switch_device_pci_aspm(
195 struct ieee80211_hw *hw,
196 u8 value)
197{
198 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
199 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
200
201 if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE)
202 value |= 0x40;
203
204 pci_write_config_byte(rtlpci->pdev, 0x80, value);
205
206 return false;
207}
208
209
210static void _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u8 value)
211{
212 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
213 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
214
215 pci_write_config_byte(rtlpci->pdev, 0x81, value);
216
217 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
218 udelay(100);
219}
220
221
222static void rtl_pci_disable_aspm(struct ieee80211_hw *hw)
223{
224 struct rtl_priv *rtlpriv = rtl_priv(hw);
225 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
226 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
227 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
228 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
229 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
230
231 u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg;
232 u16 pcibridge_linkctrlreg = pcipriv->ndis_adapter.
233 pcibridge_linkctrlreg;
234 u16 aspmlevel = 0;
235 u8 tmp_u1b = 0;
236
237 if (!ppsc->support_aspm)
238 return;
239
240 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
241 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
242 "PCI(Bridge) UNKNOWN\n");
243
244 return;
245 }
246
247 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
248 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
249 _rtl_pci_switch_clk_req(hw, 0x0);
250 }
251
252
253 pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b);
254
255
256 aspmlevel |= BIT(0) | BIT(1);
257 linkctrl_reg &= ~aspmlevel;
258 pcibridge_linkctrlreg &= ~(BIT(0) | BIT(1));
259
260 _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg);
261 udelay(50);
262
263
264 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2),
265 pcibridge_linkctrlreg);
266
267 udelay(50);
268}
269
270
271
272
273
274
275
276static void rtl_pci_enable_aspm(struct ieee80211_hw *hw)
277{
278 struct rtl_priv *rtlpriv = rtl_priv(hw);
279 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
280 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
281 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
282 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
283 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
284 u16 aspmlevel;
285 u8 u_pcibridge_aspmsetting;
286 u8 u_device_aspmsetting;
287
288 if (!ppsc->support_aspm)
289 return;
290
291 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
292 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
293 "PCI(Bridge) UNKNOWN\n");
294 return;
295 }
296
297
298
299 u_pcibridge_aspmsetting =
300 pcipriv->ndis_adapter.pcibridge_linkctrlreg |
301 rtlpci->const_hostpci_aspm_setting;
302
303 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL)
304 u_pcibridge_aspmsetting &= ~BIT(0);
305
306 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2),
307 u_pcibridge_aspmsetting);
308
309 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
310 "PlatformEnableASPM(): Write reg[%x] = %x\n",
311 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10),
312 u_pcibridge_aspmsetting);
313
314 udelay(50);
315
316
317 aspmlevel = rtlpci->const_devicepci_aspm_setting;
318 u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg;
319
320
321
322
323 u_device_aspmsetting |= aspmlevel;
324
325 _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting);
326
327 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
328 _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level &
329 RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0);
330 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
331 }
332 udelay(100);
333}
334
335static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw)
336{
337 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
338
339 bool status = false;
340 u8 offset_e0;
341 unsigned offset_e4;
342
343 pci_write_config_byte(rtlpci->pdev, 0xe0, 0xa0);
344
345 pci_read_config_byte(rtlpci->pdev, 0xe0, &offset_e0);
346
347 if (offset_e0 == 0xA0) {
348 pci_read_config_dword(rtlpci->pdev, 0xe4, &offset_e4);
349 if (offset_e4 & BIT(23))
350 status = true;
351 }
352
353 return status;
354}
355
356static bool rtl_pci_check_buddy_priv(struct ieee80211_hw *hw,
357 struct rtl_priv **buddy_priv)
358{
359 struct rtl_priv *rtlpriv = rtl_priv(hw);
360 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
361 bool find_buddy_priv = false;
362 struct rtl_priv *tpriv;
363 struct rtl_pci_priv *tpcipriv = NULL;
364
365 if (!list_empty(&rtlpriv->glb_var->glb_priv_list)) {
366 list_for_each_entry(tpriv, &rtlpriv->glb_var->glb_priv_list,
367 list) {
368 tpcipriv = (struct rtl_pci_priv *)tpriv->priv;
369 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
370 "pcipriv->ndis_adapter.funcnumber %x\n",
371 pcipriv->ndis_adapter.funcnumber);
372 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
373 "tpcipriv->ndis_adapter.funcnumber %x\n",
374 tpcipriv->ndis_adapter.funcnumber);
375
376 if ((pcipriv->ndis_adapter.busnumber ==
377 tpcipriv->ndis_adapter.busnumber) &&
378 (pcipriv->ndis_adapter.devnumber ==
379 tpcipriv->ndis_adapter.devnumber) &&
380 (pcipriv->ndis_adapter.funcnumber !=
381 tpcipriv->ndis_adapter.funcnumber)) {
382 find_buddy_priv = true;
383 break;
384 }
385 }
386 }
387
388 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
389 "find_buddy_priv %d\n", find_buddy_priv);
390
391 if (find_buddy_priv)
392 *buddy_priv = tpriv;
393
394 return find_buddy_priv;
395}
396
397static void rtl_pci_get_linkcontrol_field(struct ieee80211_hw *hw)
398{
399 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
400 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
401 u8 capabilityoffset = pcipriv->ndis_adapter.pcibridge_pciehdr_offset;
402 u8 linkctrl_reg;
403 u8 num4bbytes;
404
405 num4bbytes = (capabilityoffset + 0x10) / 4;
406
407
408 pci_read_config_byte(rtlpci->pdev, (num4bbytes << 2), &linkctrl_reg);
409
410 pcipriv->ndis_adapter.pcibridge_linkctrlreg = linkctrl_reg;
411}
412
413static void rtl_pci_parse_configuration(struct pci_dev *pdev,
414 struct ieee80211_hw *hw)
415{
416 struct rtl_priv *rtlpriv = rtl_priv(hw);
417 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
418
419 u8 tmp;
420 u16 linkctrl_reg;
421
422
423 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &linkctrl_reg);
424 pcipriv->ndis_adapter.linkctrl_reg = (u8)linkctrl_reg;
425
426 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Link Control Register =%x\n",
427 pcipriv->ndis_adapter.linkctrl_reg);
428
429 pci_read_config_byte(pdev, 0x98, &tmp);
430 tmp |= BIT(4);
431 pci_write_config_byte(pdev, 0x98, tmp);
432
433 tmp = 0x17;
434 pci_write_config_byte(pdev, 0x70f, tmp);
435}
436
437static void rtl_pci_init_aspm(struct ieee80211_hw *hw)
438{
439 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
440
441 _rtl_pci_update_default_setting(hw);
442
443 if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) {
444
445 rtl_pci_enable_aspm(hw);
446 RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM);
447 }
448
449}
450
451static void _rtl_pci_io_handler_init(struct device *dev,
452 struct ieee80211_hw *hw)
453{
454 struct rtl_priv *rtlpriv = rtl_priv(hw);
455
456 rtlpriv->io.dev = dev;
457
458 rtlpriv->io.write8_async = pci_write8_async;
459 rtlpriv->io.write16_async = pci_write16_async;
460 rtlpriv->io.write32_async = pci_write32_async;
461
462 rtlpriv->io.read8_sync = pci_read8_sync;
463 rtlpriv->io.read16_sync = pci_read16_sync;
464 rtlpriv->io.read32_sync = pci_read32_sync;
465
466}
467
468static bool _rtl_update_earlymode_info(struct ieee80211_hw *hw,
469 struct sk_buff *skb, struct rtl_tcb_desc *tcb_desc, u8 tid)
470{
471 struct rtl_priv *rtlpriv = rtl_priv(hw);
472 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
473 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
474 struct sk_buff *next_skb;
475 u8 additionlen = FCS_LEN;
476
477
478 if (info->control.hw_key)
479 additionlen += info->control.hw_key->icv_len;
480
481
482 tcb_desc->empkt_num = 0;
483 spin_lock_bh(&rtlpriv->locks.waitq_lock);
484 skb_queue_walk(&rtlpriv->mac80211.skb_waitq[tid], next_skb) {
485 struct ieee80211_tx_info *next_info;
486
487 next_info = IEEE80211_SKB_CB(next_skb);
488 if (next_info->flags & IEEE80211_TX_CTL_AMPDU) {
489 tcb_desc->empkt_len[tcb_desc->empkt_num] =
490 next_skb->len + additionlen;
491 tcb_desc->empkt_num++;
492 } else {
493 break;
494 }
495
496 if (skb_queue_is_last(&rtlpriv->mac80211.skb_waitq[tid],
497 next_skb))
498 break;
499
500 if (tcb_desc->empkt_num >= rtlhal->max_earlymode_num)
501 break;
502 }
503 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
504
505 return true;
506}
507
508
509static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw)
510{
511 struct rtl_priv *rtlpriv = rtl_priv(hw);
512 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
513 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
514 struct sk_buff *skb = NULL;
515 struct ieee80211_tx_info *info = NULL;
516 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
517 int tid;
518
519 if (!rtlpriv->rtlhal.earlymode_enable)
520 return;
521
522 if (rtlpriv->dm.supp_phymode_switch &&
523 (rtlpriv->easy_concurrent_ctl.switch_in_process ||
524 (rtlpriv->buddy_priv &&
525 rtlpriv->buddy_priv->easy_concurrent_ctl.switch_in_process)))
526 return;
527
528 for (tid = 7; tid >= 0; tid--) {
529 u8 hw_queue = ac_to_hwq[rtl_tid_to_ac(tid)];
530 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
531 while (!mac->act_scanning &&
532 rtlpriv->psc.rfpwr_state == ERFON) {
533 struct rtl_tcb_desc tcb_desc;
534 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
535
536 spin_lock_bh(&rtlpriv->locks.waitq_lock);
537 if (!skb_queue_empty(&mac->skb_waitq[tid]) &&
538 (ring->entries - skb_queue_len(&ring->queue) >
539 rtlhal->max_earlymode_num)) {
540 skb = skb_dequeue(&mac->skb_waitq[tid]);
541 } else {
542 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
543 break;
544 }
545 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
546
547
548
549 info = IEEE80211_SKB_CB(skb);
550 if (info->flags & IEEE80211_TX_CTL_AMPDU)
551 _rtl_update_earlymode_info(hw, skb,
552 &tcb_desc, tid);
553
554 rtlpriv->intf_ops->adapter_tx(hw, NULL, skb, &tcb_desc);
555 }
556 }
557}
558
559
560static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio)
561{
562 struct rtl_priv *rtlpriv = rtl_priv(hw);
563 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
564
565 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
566
567 while (skb_queue_len(&ring->queue)) {
568 struct sk_buff *skb;
569 struct ieee80211_tx_info *info;
570 __le16 fc;
571 u8 tid;
572 u8 *entry;
573
574 if (rtlpriv->use_new_trx_flow)
575 entry = (u8 *)(&ring->buffer_desc[ring->idx]);
576 else
577 entry = (u8 *)(&ring->desc[ring->idx]);
578
579 if (rtlpriv->cfg->ops->get_available_desc &&
580 rtlpriv->cfg->ops->get_available_desc(hw, prio) <= 1) {
581 RT_TRACE(rtlpriv, (COMP_INTR | COMP_SEND), DBG_DMESG,
582 "no available desc!\n");
583 return;
584 }
585
586 if (!rtlpriv->cfg->ops->is_tx_desc_closed(hw, prio, ring->idx))
587 return;
588 ring->idx = (ring->idx + 1) % ring->entries;
589
590 skb = __skb_dequeue(&ring->queue);
591 pci_unmap_single(rtlpci->pdev,
592 rtlpriv->cfg->ops->
593 get_desc((u8 *)entry, true,
594 HW_DESC_TXBUFF_ADDR),
595 skb->len, PCI_DMA_TODEVICE);
596
597
598 if (rtlpriv->rtlhal.earlymode_enable)
599 skb_pull(skb, EM_HDR_LEN);
600
601 RT_TRACE(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE,
602 "new ring->idx:%d, free: skb_queue_len:%d, free: seq:%x\n",
603 ring->idx,
604 skb_queue_len(&ring->queue),
605 *(u16 *)(skb->data + 22));
606
607 if (prio == TXCMD_QUEUE) {
608 dev_kfree_skb(skb);
609 goto tx_status_ok;
610
611 }
612
613
614
615
616
617 fc = rtl_get_fc(skb);
618 if (ieee80211_is_nullfunc(fc)) {
619 if (ieee80211_has_pm(fc)) {
620 rtlpriv->mac80211.offchan_delay = true;
621 rtlpriv->psc.state_inap = true;
622 } else {
623 rtlpriv->psc.state_inap = false;
624 }
625 }
626 if (ieee80211_is_action(fc)) {
627 struct ieee80211_mgmt *action_frame =
628 (struct ieee80211_mgmt *)skb->data;
629 if (action_frame->u.action.u.ht_smps.action ==
630 WLAN_HT_ACTION_SMPS) {
631 dev_kfree_skb(skb);
632 goto tx_status_ok;
633 }
634 }
635
636
637 tid = rtl_get_tid(skb);
638 if (tid <= 7)
639 rtlpriv->link_info.tidtx_inperiod[tid]++;
640
641 info = IEEE80211_SKB_CB(skb);
642 ieee80211_tx_info_clear_status(info);
643
644 info->flags |= IEEE80211_TX_STAT_ACK;
645
646
647 ieee80211_tx_status_irqsafe(hw, skb);
648
649 if ((ring->entries - skb_queue_len(&ring->queue)) <= 4) {
650
651 RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG,
652 "more desc left, wake skb_queue@%d, ring->idx = %d, skb_queue_len = 0x%x\n",
653 prio, ring->idx,
654 skb_queue_len(&ring->queue));
655
656 ieee80211_wake_queue(hw,
657 skb_get_queue_mapping
658 (skb));
659 }
660tx_status_ok:
661 skb = NULL;
662 }
663
664 if (((rtlpriv->link_info.num_rx_inperiod +
665 rtlpriv->link_info.num_tx_inperiod) > 8) ||
666 (rtlpriv->link_info.num_rx_inperiod > 2)) {
667 rtlpriv->enter_ps = false;
668 schedule_work(&rtlpriv->works.lps_change_work);
669 }
670}
671
672static int _rtl_pci_init_one_rxdesc(struct ieee80211_hw *hw,
673 struct sk_buff *new_skb, u8 *entry,
674 int rxring_idx, int desc_idx)
675{
676 struct rtl_priv *rtlpriv = rtl_priv(hw);
677 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
678 u32 bufferaddress;
679 u8 tmp_one = 1;
680 struct sk_buff *skb;
681
682 if (likely(new_skb)) {
683 skb = new_skb;
684 goto remap;
685 }
686 skb = dev_alloc_skb(rtlpci->rxbuffersize);
687 if (!skb)
688 return 0;
689
690remap:
691
692 *((dma_addr_t *)skb->cb) =
693 pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
694 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE);
695 bufferaddress = *((dma_addr_t *)skb->cb);
696 if (pci_dma_mapping_error(rtlpci->pdev, bufferaddress))
697 return 0;
698 rtlpci->rx_ring[rxring_idx].rx_buf[desc_idx] = skb;
699 if (rtlpriv->use_new_trx_flow) {
700 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
701 HW_DESC_RX_PREPARE,
702 (u8 *)&bufferaddress);
703 } else {
704 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
705 HW_DESC_RXBUFF_ADDR,
706 (u8 *)&bufferaddress);
707 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
708 HW_DESC_RXPKT_LEN,
709 (u8 *)&rtlpci->rxbuffersize);
710 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
711 HW_DESC_RXOWN,
712 (u8 *)&tmp_one);
713 }
714 return 1;
715}
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730static void _rtl_pci_rx_to_mac80211(struct ieee80211_hw *hw,
731 struct sk_buff *skb,
732 struct ieee80211_rx_status rx_status)
733{
734 if (unlikely(!rtl_action_proc(hw, skb, false))) {
735 dev_kfree_skb_any(skb);
736 } else {
737 struct sk_buff *uskb = NULL;
738 u8 *pdata;
739
740 uskb = dev_alloc_skb(skb->len + 128);
741 if (likely(uskb)) {
742 memcpy(IEEE80211_SKB_RXCB(uskb), &rx_status,
743 sizeof(rx_status));
744 pdata = (u8 *)skb_put(uskb, skb->len);
745 memcpy(pdata, skb->data, skb->len);
746 dev_kfree_skb_any(skb);
747 ieee80211_rx_irqsafe(hw, uskb);
748 } else {
749 ieee80211_rx_irqsafe(hw, skb);
750 }
751 }
752}
753
754
755static void _rtl_pci_hs_interrupt(struct ieee80211_hw *hw)
756{
757 struct rtl_priv *rtlpriv = rtl_priv(hw);
758 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
759
760 rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR],
761 rtl_read_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR]) |
762 rtlpci->sys_irq_mask);
763}
764
765static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw)
766{
767 struct rtl_priv *rtlpriv = rtl_priv(hw);
768 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
769 int rxring_idx = RTL_PCI_RX_MPDU_QUEUE;
770 struct ieee80211_rx_status rx_status = { 0 };
771 unsigned int count = rtlpci->rxringcount;
772 u8 own;
773 u8 tmp_one;
774 bool unicast = false;
775 u8 hw_queue = 0;
776 unsigned int rx_remained_cnt;
777 struct rtl_stats stats = {
778 .signal = 0,
779 .rate = 0,
780 };
781
782
783 while (count--) {
784 struct ieee80211_hdr *hdr;
785 __le16 fc;
786 u16 len;
787
788 struct rtl_rx_buffer_desc *buffer_desc = NULL;
789
790 struct rtl_rx_desc *pdesc = NULL;
791
792 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[
793 rtlpci->rx_ring[rxring_idx].idx];
794 struct sk_buff *new_skb;
795
796 if (rtlpriv->use_new_trx_flow) {
797 rx_remained_cnt =
798 rtlpriv->cfg->ops->rx_desc_buff_remained_cnt(hw,
799 hw_queue);
800 if (rx_remained_cnt == 0)
801 return;
802 buffer_desc = &rtlpci->rx_ring[rxring_idx].buffer_desc[
803 rtlpci->rx_ring[rxring_idx].idx];
804 pdesc = (struct rtl_rx_desc *)skb->data;
805 } else {
806 pdesc = &rtlpci->rx_ring[rxring_idx].desc[
807 rtlpci->rx_ring[rxring_idx].idx];
808
809 own = (u8)rtlpriv->cfg->ops->get_desc((u8 *)pdesc,
810 false,
811 HW_DESC_OWN);
812 if (own)
813 return;
814 }
815
816
817
818
819
820 pci_unmap_single(rtlpci->pdev, *((dma_addr_t *)skb->cb),
821 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE);
822
823
824 new_skb = dev_alloc_skb(rtlpci->rxbuffersize);
825 if (unlikely(!new_skb))
826 goto no_new;
827 memset(&rx_status , 0 , sizeof(rx_status));
828 rtlpriv->cfg->ops->query_rx_desc(hw, &stats,
829 &rx_status, (u8 *)pdesc, skb);
830
831 if (rtlpriv->use_new_trx_flow)
832 rtlpriv->cfg->ops->rx_check_dma_ok(hw,
833 (u8 *)buffer_desc,
834 hw_queue);
835
836 len = rtlpriv->cfg->ops->get_desc((u8 *)pdesc, false,
837 HW_DESC_RXPKT_LEN);
838
839 if (skb->end - skb->tail > len) {
840 skb_put(skb, len);
841 if (rtlpriv->use_new_trx_flow)
842 skb_reserve(skb, stats.rx_drvinfo_size +
843 stats.rx_bufshift + 24);
844 else
845 skb_reserve(skb, stats.rx_drvinfo_size +
846 stats.rx_bufshift);
847 } else {
848 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
849 "skb->end - skb->tail = %d, len is %d\n",
850 skb->end - skb->tail, len);
851 dev_kfree_skb_any(skb);
852 goto new_trx_end;
853 }
854
855 if (rtlpriv->cfg->ops->rx_command_packet &&
856 rtlpriv->cfg->ops->rx_command_packet(hw, &stats, skb)) {
857 dev_kfree_skb_any(skb);
858 goto new_trx_end;
859 }
860
861
862
863
864
865
866
867
868 hdr = rtl_get_hdr(skb);
869 fc = rtl_get_fc(skb);
870
871 if (!stats.crc && !stats.hwerror) {
872 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status,
873 sizeof(rx_status));
874
875 if (is_broadcast_ether_addr(hdr->addr1)) {
876 ;
877 } else if (is_multicast_ether_addr(hdr->addr1)) {
878 ;
879 } else {
880 unicast = true;
881 rtlpriv->stats.rxbytesunicast += skb->len;
882 }
883 rtl_is_special_data(hw, skb, false, true);
884
885 if (ieee80211_is_data(fc)) {
886 rtlpriv->cfg->ops->led_control(hw, LED_CTL_RX);
887 if (unicast)
888 rtlpriv->link_info.num_rx_inperiod++;
889 }
890
891 rtl_beacon_statistic(hw, skb);
892 rtl_p2p_info(hw, (void *)skb->data, skb->len);
893
894 rtl_swlps_beacon(hw, (void *)skb->data, skb->len);
895 rtl_recognize_peer(hw, (void *)skb->data, skb->len);
896 if ((rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP) &&
897 (rtlpriv->rtlhal.current_bandtype ==
898 BAND_ON_2_4G) &&
899 (ieee80211_is_beacon(fc) ||
900 ieee80211_is_probe_resp(fc))) {
901 dev_kfree_skb_any(skb);
902 } else {
903 _rtl_pci_rx_to_mac80211(hw, skb, rx_status);
904 }
905 } else {
906 dev_kfree_skb_any(skb);
907 }
908new_trx_end:
909 if (rtlpriv->use_new_trx_flow) {
910 rtlpci->rx_ring[hw_queue].next_rx_rp += 1;
911 rtlpci->rx_ring[hw_queue].next_rx_rp %=
912 RTL_PCI_MAX_RX_COUNT;
913
914 rx_remained_cnt--;
915 rtl_write_word(rtlpriv, 0x3B4,
916 rtlpci->rx_ring[hw_queue].next_rx_rp);
917 }
918 if (((rtlpriv->link_info.num_rx_inperiod +
919 rtlpriv->link_info.num_tx_inperiod) > 8) ||
920 (rtlpriv->link_info.num_rx_inperiod > 2)) {
921 rtlpriv->enter_ps = false;
922 schedule_work(&rtlpriv->works.lps_change_work);
923 }
924 skb = new_skb;
925no_new:
926 if (rtlpriv->use_new_trx_flow) {
927 _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)buffer_desc,
928 rxring_idx,
929 rtlpci->rx_ring[rxring_idx].idx);
930 } else {
931 _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)pdesc,
932 rxring_idx,
933 rtlpci->rx_ring[rxring_idx].idx);
934 if (rtlpci->rx_ring[rxring_idx].idx ==
935 rtlpci->rxringcount - 1)
936 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc,
937 false,
938 HW_DESC_RXERO,
939 (u8 *)&tmp_one);
940 }
941 rtlpci->rx_ring[rxring_idx].idx =
942 (rtlpci->rx_ring[rxring_idx].idx + 1) %
943 rtlpci->rxringcount;
944 }
945}
946
947static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id)
948{
949 struct ieee80211_hw *hw = dev_id;
950 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
951 struct rtl_priv *rtlpriv = rtl_priv(hw);
952 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
953 unsigned long flags;
954 u32 inta = 0;
955 u32 intb = 0;
956 irqreturn_t ret = IRQ_HANDLED;
957
958 if (rtlpci->irq_enabled == 0)
959 return ret;
960
961 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock , flags);
962 rtlpriv->cfg->ops->disable_interrupt(hw);
963
964
965 rtlpriv->cfg->ops->interrupt_recognized(hw, &inta, &intb);
966
967
968 if (!inta || inta == 0xffff)
969 goto done;
970
971
972 if (inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK]) {
973 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
974 "beacon ok interrupt!\n");
975 }
976
977 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TBDER])) {
978 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
979 "beacon err interrupt!\n");
980 }
981
982 if (inta & rtlpriv->cfg->maps[RTL_IMR_BDOK]) {
983 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "beacon interrupt!\n");
984 }
985
986 if (inta & rtlpriv->cfg->maps[RTL_IMR_BCNINT]) {
987 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
988 "prepare beacon for interrupt!\n");
989 tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet);
990 }
991
992
993 if (unlikely(intb & rtlpriv->cfg->maps[RTL_IMR_TXFOVW]))
994 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "IMR_TXFOVW!\n");
995
996 if (inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) {
997 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
998 "Manage ok interrupt!\n");
999 _rtl_pci_tx_isr(hw, MGNT_QUEUE);
1000 }
1001
1002 if (inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) {
1003 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1004 "HIGH_QUEUE ok interrupt!\n");
1005 _rtl_pci_tx_isr(hw, HIGH_QUEUE);
1006 }
1007
1008 if (inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) {
1009 rtlpriv->link_info.num_tx_inperiod++;
1010
1011 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1012 "BK Tx OK interrupt!\n");
1013 _rtl_pci_tx_isr(hw, BK_QUEUE);
1014 }
1015
1016 if (inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) {
1017 rtlpriv->link_info.num_tx_inperiod++;
1018
1019 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1020 "BE TX OK interrupt!\n");
1021 _rtl_pci_tx_isr(hw, BE_QUEUE);
1022 }
1023
1024 if (inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) {
1025 rtlpriv->link_info.num_tx_inperiod++;
1026
1027 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1028 "VI TX OK interrupt!\n");
1029 _rtl_pci_tx_isr(hw, VI_QUEUE);
1030 }
1031
1032 if (inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) {
1033 rtlpriv->link_info.num_tx_inperiod++;
1034
1035 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1036 "Vo TX OK interrupt!\n");
1037 _rtl_pci_tx_isr(hw, VO_QUEUE);
1038 }
1039
1040 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) {
1041 if (inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) {
1042 rtlpriv->link_info.num_tx_inperiod++;
1043
1044 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1045 "CMD TX OK interrupt!\n");
1046 _rtl_pci_tx_isr(hw, TXCMD_QUEUE);
1047 }
1048 }
1049
1050
1051 if (inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) {
1052 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "Rx ok interrupt!\n");
1053 _rtl_pci_rx_interrupt(hw);
1054 }
1055
1056 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) {
1057 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1058 "rx descriptor unavailable!\n");
1059 _rtl_pci_rx_interrupt(hw);
1060 }
1061
1062 if (unlikely(intb & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) {
1063 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "rx overflow !\n");
1064 _rtl_pci_rx_interrupt(hw);
1065 }
1066
1067
1068 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723AE) {
1069 if (inta & rtlpriv->cfg->maps[RTL_IMR_C2HCMD]) {
1070 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1071 "firmware interrupt!\n");
1072 queue_delayed_work(rtlpriv->works.rtl_wq,
1073 &rtlpriv->works.fwevt_wq, 0);
1074 }
1075 }
1076
1077
1078
1079
1080
1081
1082
1083 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8188EE ||
1084 rtlhal->hw_type == HARDWARE_TYPE_RTL8723BE) {
1085 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_HSISR_IND])) {
1086 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1087 "hsisr interrupt!\n");
1088 _rtl_pci_hs_interrupt(hw);
1089 }
1090 }
1091
1092 if (rtlpriv->rtlhal.earlymode_enable)
1093 tasklet_schedule(&rtlpriv->works.irq_tasklet);
1094
1095done:
1096 rtlpriv->cfg->ops->enable_interrupt(hw);
1097 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1098 return ret;
1099}
1100
1101static void _rtl_pci_irq_tasklet(struct ieee80211_hw *hw)
1102{
1103 _rtl_pci_tx_chk_waitq(hw);
1104}
1105
1106static void _rtl_pci_prepare_bcn_tasklet(struct ieee80211_hw *hw)
1107{
1108 struct rtl_priv *rtlpriv = rtl_priv(hw);
1109 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1110 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1111 struct rtl8192_tx_ring *ring = NULL;
1112 struct ieee80211_hdr *hdr = NULL;
1113 struct ieee80211_tx_info *info = NULL;
1114 struct sk_buff *pskb = NULL;
1115 struct rtl_tx_desc *pdesc = NULL;
1116 struct rtl_tcb_desc tcb_desc;
1117
1118 struct rtl_tx_buffer_desc *pbuffer_desc = NULL;
1119 u8 temp_one = 1;
1120 u8 *entry;
1121
1122 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
1123 ring = &rtlpci->tx_ring[BEACON_QUEUE];
1124 pskb = __skb_dequeue(&ring->queue);
1125 if (rtlpriv->use_new_trx_flow)
1126 entry = (u8 *)(&ring->buffer_desc[ring->idx]);
1127 else
1128 entry = (u8 *)(&ring->desc[ring->idx]);
1129 if (pskb) {
1130 pci_unmap_single(rtlpci->pdev,
1131 rtlpriv->cfg->ops->get_desc(
1132 (u8 *)entry, true, HW_DESC_TXBUFF_ADDR),
1133 pskb->len, PCI_DMA_TODEVICE);
1134 kfree_skb(pskb);
1135 }
1136
1137
1138 pskb = ieee80211_beacon_get(hw, mac->vif);
1139 if (pskb == NULL)
1140 return;
1141 hdr = rtl_get_hdr(pskb);
1142 info = IEEE80211_SKB_CB(pskb);
1143 pdesc = &ring->desc[0];
1144 if (rtlpriv->use_new_trx_flow)
1145 pbuffer_desc = &ring->buffer_desc[0];
1146
1147 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
1148 (u8 *)pbuffer_desc, info, NULL, pskb,
1149 BEACON_QUEUE, &tcb_desc);
1150
1151 __skb_queue_tail(&ring->queue, pskb);
1152
1153 if (rtlpriv->use_new_trx_flow) {
1154 temp_one = 4;
1155 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pbuffer_desc, true,
1156 HW_DESC_OWN, (u8 *)&temp_one);
1157 } else {
1158 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, HW_DESC_OWN,
1159 &temp_one);
1160 }
1161 return;
1162}
1163
1164static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw)
1165{
1166 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1167 struct rtl_priv *rtlpriv = rtl_priv(hw);
1168 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1169 u8 i;
1170 u16 desc_num;
1171
1172 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192EE)
1173 desc_num = TX_DESC_NUM_92E;
1174 else
1175 desc_num = RT_TXDESC_NUM;
1176
1177 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1178 rtlpci->txringcount[i] = desc_num;
1179
1180
1181
1182
1183
1184 rtlpci->txringcount[BEACON_QUEUE] = 2;
1185
1186
1187
1188
1189
1190 if (!rtl_priv(hw)->use_new_trx_flow)
1191 rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE;
1192
1193 rtlpci->rxbuffersize = 9100;
1194 rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT;
1195}
1196
1197static void _rtl_pci_init_struct(struct ieee80211_hw *hw,
1198 struct pci_dev *pdev)
1199{
1200 struct rtl_priv *rtlpriv = rtl_priv(hw);
1201 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1202 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1203 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1204
1205 rtlpci->up_first_time = true;
1206 rtlpci->being_init_adapter = false;
1207
1208 rtlhal->hw = hw;
1209 rtlpci->pdev = pdev;
1210
1211
1212 _rtl_pci_init_trx_var(hw);
1213
1214
1215 mac->beacon_interval = 100;
1216
1217
1218 mac->min_space_cfg = 0;
1219 mac->max_mss_density = 0;
1220
1221 mac->current_ampdu_density = 7;
1222 mac->current_ampdu_factor = 3;
1223
1224
1225 rtlpci->acm_method = EACMWAY2_SW;
1226
1227
1228 tasklet_init(&rtlpriv->works.irq_tasklet,
1229 (void (*)(unsigned long))_rtl_pci_irq_tasklet,
1230 (unsigned long)hw);
1231 tasklet_init(&rtlpriv->works.irq_prepare_bcn_tasklet,
1232 (void (*)(unsigned long))_rtl_pci_prepare_bcn_tasklet,
1233 (unsigned long)hw);
1234 INIT_WORK(&rtlpriv->works.lps_change_work,
1235 rtl_lps_change_work_callback);
1236}
1237
1238static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw,
1239 unsigned int prio, unsigned int entries)
1240{
1241 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1242 struct rtl_priv *rtlpriv = rtl_priv(hw);
1243 struct rtl_tx_buffer_desc *buffer_desc;
1244 struct rtl_tx_desc *desc;
1245 dma_addr_t buffer_desc_dma, desc_dma;
1246 u32 nextdescaddress;
1247 int i;
1248
1249
1250 if (rtlpriv->use_new_trx_flow) {
1251 buffer_desc =
1252 pci_zalloc_consistent(rtlpci->pdev,
1253 sizeof(*buffer_desc) * entries,
1254 &buffer_desc_dma);
1255
1256 if (!buffer_desc || (unsigned long)buffer_desc & 0xFF) {
1257 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1258 "Cannot allocate TX ring (prio = %d)\n",
1259 prio);
1260 return -ENOMEM;
1261 }
1262
1263 rtlpci->tx_ring[prio].buffer_desc = buffer_desc;
1264 rtlpci->tx_ring[prio].buffer_desc_dma = buffer_desc_dma;
1265
1266 rtlpci->tx_ring[prio].cur_tx_rp = 0;
1267 rtlpci->tx_ring[prio].cur_tx_wp = 0;
1268 rtlpci->tx_ring[prio].avl_desc = entries;
1269 }
1270
1271
1272 desc = pci_zalloc_consistent(rtlpci->pdev,
1273 sizeof(*desc) * entries, &desc_dma);
1274
1275 if (!desc || (unsigned long)desc & 0xFF) {
1276 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1277 "Cannot allocate TX ring (prio = %d)\n", prio);
1278 return -ENOMEM;
1279 }
1280
1281 rtlpci->tx_ring[prio].desc = desc;
1282 rtlpci->tx_ring[prio].dma = desc_dma;
1283
1284 rtlpci->tx_ring[prio].idx = 0;
1285 rtlpci->tx_ring[prio].entries = entries;
1286 skb_queue_head_init(&rtlpci->tx_ring[prio].queue);
1287
1288 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "queue:%d, ring_addr:%p\n",
1289 prio, desc);
1290
1291
1292 if (!rtlpriv->use_new_trx_flow) {
1293 for (i = 0; i < entries; i++) {
1294 nextdescaddress = (u32)desc_dma +
1295 ((i + 1) % entries) *
1296 sizeof(*desc);
1297
1298 rtlpriv->cfg->ops->set_desc(hw, (u8 *)&desc[i],
1299 true,
1300 HW_DESC_TX_NEXTDESC_ADDR,
1301 (u8 *)&nextdescaddress);
1302 }
1303 }
1304 return 0;
1305}
1306
1307static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw, int rxring_idx)
1308{
1309 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1310 struct rtl_priv *rtlpriv = rtl_priv(hw);
1311 int i;
1312
1313 if (rtlpriv->use_new_trx_flow) {
1314 struct rtl_rx_buffer_desc *entry = NULL;
1315
1316 rtlpci->rx_ring[rxring_idx].buffer_desc =
1317 pci_zalloc_consistent(rtlpci->pdev,
1318 sizeof(*rtlpci->rx_ring[rxring_idx].
1319 buffer_desc) *
1320 rtlpci->rxringcount,
1321 &rtlpci->rx_ring[rxring_idx].dma);
1322 if (!rtlpci->rx_ring[rxring_idx].buffer_desc ||
1323 (ulong)rtlpci->rx_ring[rxring_idx].buffer_desc & 0xFF) {
1324 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1325 "Cannot allocate RX ring\n");
1326 return -ENOMEM;
1327 }
1328
1329
1330 rtlpci->rx_ring[rxring_idx].idx = 0;
1331 for (i = 0; i < rtlpci->rxringcount; i++) {
1332 entry = &rtlpci->rx_ring[rxring_idx].buffer_desc[i];
1333 if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry,
1334 rxring_idx, i))
1335 return -ENOMEM;
1336 }
1337 } else {
1338 struct rtl_rx_desc *entry = NULL;
1339 u8 tmp_one = 1;
1340
1341 rtlpci->rx_ring[rxring_idx].desc =
1342 pci_zalloc_consistent(rtlpci->pdev,
1343 sizeof(*rtlpci->rx_ring[rxring_idx].
1344 desc) * rtlpci->rxringcount,
1345 &rtlpci->rx_ring[rxring_idx].dma);
1346 if (!rtlpci->rx_ring[rxring_idx].desc ||
1347 (unsigned long)rtlpci->rx_ring[rxring_idx].desc & 0xFF) {
1348 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1349 "Cannot allocate RX ring\n");
1350 return -ENOMEM;
1351 }
1352
1353
1354 rtlpci->rx_ring[rxring_idx].idx = 0;
1355
1356 for (i = 0; i < rtlpci->rxringcount; i++) {
1357 entry = &rtlpci->rx_ring[rxring_idx].desc[i];
1358 if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry,
1359 rxring_idx, i))
1360 return -ENOMEM;
1361 }
1362
1363 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
1364 HW_DESC_RXERO, &tmp_one);
1365 }
1366 return 0;
1367}
1368
1369static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw,
1370 unsigned int prio)
1371{
1372 struct rtl_priv *rtlpriv = rtl_priv(hw);
1373 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1374 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
1375
1376
1377 while (skb_queue_len(&ring->queue)) {
1378 u8 *entry;
1379 struct sk_buff *skb = __skb_dequeue(&ring->queue);
1380
1381 if (rtlpriv->use_new_trx_flow)
1382 entry = (u8 *)(&ring->buffer_desc[ring->idx]);
1383 else
1384 entry = (u8 *)(&ring->desc[ring->idx]);
1385
1386 pci_unmap_single(rtlpci->pdev,
1387 rtlpriv->cfg->
1388 ops->get_desc((u8 *)entry, true,
1389 HW_DESC_TXBUFF_ADDR),
1390 skb->len, PCI_DMA_TODEVICE);
1391 kfree_skb(skb);
1392 ring->idx = (ring->idx + 1) % ring->entries;
1393 }
1394
1395
1396 pci_free_consistent(rtlpci->pdev,
1397 sizeof(*ring->desc) * ring->entries,
1398 ring->desc, ring->dma);
1399 ring->desc = NULL;
1400 if (rtlpriv->use_new_trx_flow) {
1401 pci_free_consistent(rtlpci->pdev,
1402 sizeof(*ring->buffer_desc) * ring->entries,
1403 ring->buffer_desc, ring->buffer_desc_dma);
1404 ring->buffer_desc = NULL;
1405 }
1406}
1407
1408static void _rtl_pci_free_rx_ring(struct ieee80211_hw *hw, int rxring_idx)
1409{
1410 struct rtl_priv *rtlpriv = rtl_priv(hw);
1411 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1412 int i;
1413
1414
1415 for (i = 0; i < rtlpci->rxringcount; i++) {
1416 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[i];
1417
1418 if (!skb)
1419 continue;
1420 pci_unmap_single(rtlpci->pdev, *((dma_addr_t *)skb->cb),
1421 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE);
1422 kfree_skb(skb);
1423 }
1424
1425
1426 if (rtlpriv->use_new_trx_flow) {
1427 pci_free_consistent(rtlpci->pdev,
1428 sizeof(*rtlpci->rx_ring[rxring_idx].
1429 buffer_desc) * rtlpci->rxringcount,
1430 rtlpci->rx_ring[rxring_idx].buffer_desc,
1431 rtlpci->rx_ring[rxring_idx].dma);
1432 rtlpci->rx_ring[rxring_idx].buffer_desc = NULL;
1433 } else {
1434 pci_free_consistent(rtlpci->pdev,
1435 sizeof(*rtlpci->rx_ring[rxring_idx].desc) *
1436 rtlpci->rxringcount,
1437 rtlpci->rx_ring[rxring_idx].desc,
1438 rtlpci->rx_ring[rxring_idx].dma);
1439 rtlpci->rx_ring[rxring_idx].desc = NULL;
1440 }
1441}
1442
1443static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw)
1444{
1445 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1446 int ret;
1447 int i, rxring_idx;
1448
1449
1450
1451
1452 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) {
1453 ret = _rtl_pci_init_rx_ring(hw, rxring_idx);
1454 if (ret)
1455 return ret;
1456 }
1457
1458 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1459 ret = _rtl_pci_init_tx_ring(hw, i,
1460 rtlpci->txringcount[i]);
1461 if (ret)
1462 goto err_free_rings;
1463 }
1464
1465 return 0;
1466
1467err_free_rings:
1468 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++)
1469 _rtl_pci_free_rx_ring(hw, rxring_idx);
1470
1471 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1472 if (rtlpci->tx_ring[i].desc ||
1473 rtlpci->tx_ring[i].buffer_desc)
1474 _rtl_pci_free_tx_ring(hw, i);
1475
1476 return 1;
1477}
1478
1479static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw)
1480{
1481 u32 i, rxring_idx;
1482
1483
1484 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++)
1485 _rtl_pci_free_rx_ring(hw, rxring_idx);
1486
1487
1488 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1489 _rtl_pci_free_tx_ring(hw, i);
1490
1491 return 0;
1492}
1493
1494int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw)
1495{
1496 struct rtl_priv *rtlpriv = rtl_priv(hw);
1497 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1498 int i, rxring_idx;
1499 unsigned long flags;
1500 u8 tmp_one = 1;
1501 u32 bufferaddress;
1502
1503
1504 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) {
1505
1506
1507
1508
1509 if (!rtlpriv->use_new_trx_flow &&
1510 rtlpci->rx_ring[rxring_idx].desc) {
1511 struct rtl_rx_desc *entry = NULL;
1512
1513 rtlpci->rx_ring[rxring_idx].idx = 0;
1514 for (i = 0; i < rtlpci->rxringcount; i++) {
1515 entry = &rtlpci->rx_ring[rxring_idx].desc[i];
1516 bufferaddress =
1517 rtlpriv->cfg->ops->get_desc((u8 *)entry,
1518 false , HW_DESC_RXBUFF_ADDR);
1519 memset((u8 *)entry , 0 ,
1520 sizeof(*rtlpci->rx_ring
1521 [rxring_idx].desc));
1522 if (rtlpriv->use_new_trx_flow) {
1523 rtlpriv->cfg->ops->set_desc(hw,
1524 (u8 *)entry, false,
1525 HW_DESC_RX_PREPARE,
1526 (u8 *)&bufferaddress);
1527 } else {
1528 rtlpriv->cfg->ops->set_desc(hw,
1529 (u8 *)entry, false,
1530 HW_DESC_RXBUFF_ADDR,
1531 (u8 *)&bufferaddress);
1532 rtlpriv->cfg->ops->set_desc(hw,
1533 (u8 *)entry, false,
1534 HW_DESC_RXPKT_LEN,
1535 (u8 *)&rtlpci->rxbuffersize);
1536 rtlpriv->cfg->ops->set_desc(hw,
1537 (u8 *)entry, false,
1538 HW_DESC_RXOWN,
1539 (u8 *)&tmp_one);
1540 }
1541 }
1542 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
1543 HW_DESC_RXERO, (u8 *)&tmp_one);
1544 }
1545 rtlpci->rx_ring[rxring_idx].idx = 0;
1546 }
1547
1548
1549
1550
1551
1552 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1553 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1554 if (rtlpci->tx_ring[i].desc ||
1555 rtlpci->tx_ring[i].buffer_desc) {
1556 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i];
1557
1558 while (skb_queue_len(&ring->queue)) {
1559 u8 *entry;
1560 struct sk_buff *skb =
1561 __skb_dequeue(&ring->queue);
1562 if (rtlpriv->use_new_trx_flow)
1563 entry = (u8 *)(&ring->buffer_desc
1564 [ring->idx]);
1565 else
1566 entry = (u8 *)(&ring->desc[ring->idx]);
1567
1568 pci_unmap_single(rtlpci->pdev,
1569 rtlpriv->cfg->ops->
1570 get_desc((u8 *)
1571 entry,
1572 true,
1573 HW_DESC_TXBUFF_ADDR),
1574 skb->len, PCI_DMA_TODEVICE);
1575 dev_kfree_skb_irq(skb);
1576 ring->idx = (ring->idx + 1) % ring->entries;
1577 }
1578 ring->idx = 0;
1579 }
1580 }
1581 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1582
1583 return 0;
1584}
1585
1586static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw,
1587 struct ieee80211_sta *sta,
1588 struct sk_buff *skb)
1589{
1590 struct rtl_priv *rtlpriv = rtl_priv(hw);
1591 struct rtl_sta_info *sta_entry = NULL;
1592 u8 tid = rtl_get_tid(skb);
1593 __le16 fc = rtl_get_fc(skb);
1594
1595 if (!sta)
1596 return false;
1597 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1598
1599 if (!rtlpriv->rtlhal.earlymode_enable)
1600 return false;
1601 if (ieee80211_is_nullfunc(fc))
1602 return false;
1603 if (ieee80211_is_qos_nullfunc(fc))
1604 return false;
1605 if (ieee80211_is_pspoll(fc))
1606 return false;
1607 if (sta_entry->tids[tid].agg.agg_state != RTL_AGG_OPERATIONAL)
1608 return false;
1609 if (_rtl_mac_to_hwqueue(hw, skb) > VO_QUEUE)
1610 return false;
1611 if (tid > 7)
1612 return false;
1613
1614
1615 if (!rtlpriv->link_info.higher_busytxtraffic[tid])
1616 return false;
1617
1618 spin_lock_bh(&rtlpriv->locks.waitq_lock);
1619 skb_queue_tail(&rtlpriv->mac80211.skb_waitq[tid], skb);
1620 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
1621
1622 return true;
1623}
1624
1625static int rtl_pci_tx(struct ieee80211_hw *hw,
1626 struct ieee80211_sta *sta,
1627 struct sk_buff *skb,
1628 struct rtl_tcb_desc *ptcb_desc)
1629{
1630 struct rtl_priv *rtlpriv = rtl_priv(hw);
1631 struct rtl_sta_info *sta_entry = NULL;
1632 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1633 struct rtl8192_tx_ring *ring;
1634 struct rtl_tx_desc *pdesc;
1635 struct rtl_tx_buffer_desc *ptx_bd_desc = NULL;
1636 u16 idx;
1637 u8 hw_queue = _rtl_mac_to_hwqueue(hw, skb);
1638 unsigned long flags;
1639 struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
1640 __le16 fc = rtl_get_fc(skb);
1641 u8 *pda_addr = hdr->addr1;
1642 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1643
1644 u8 tid = 0;
1645 u16 seq_number = 0;
1646 u8 own;
1647 u8 temp_one = 1;
1648
1649 if (ieee80211_is_mgmt(fc))
1650 rtl_tx_mgmt_proc(hw, skb);
1651
1652 if (rtlpriv->psc.sw_ps_enabled) {
1653 if (ieee80211_is_data(fc) && !ieee80211_is_nullfunc(fc) &&
1654 !ieee80211_has_pm(fc))
1655 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1656 }
1657
1658 rtl_action_proc(hw, skb, true);
1659
1660 if (is_multicast_ether_addr(pda_addr))
1661 rtlpriv->stats.txbytesmulticast += skb->len;
1662 else if (is_broadcast_ether_addr(pda_addr))
1663 rtlpriv->stats.txbytesbroadcast += skb->len;
1664 else
1665 rtlpriv->stats.txbytesunicast += skb->len;
1666
1667 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1668 ring = &rtlpci->tx_ring[hw_queue];
1669 if (hw_queue != BEACON_QUEUE) {
1670 if (rtlpriv->use_new_trx_flow)
1671 idx = ring->cur_tx_wp;
1672 else
1673 idx = (ring->idx + skb_queue_len(&ring->queue)) %
1674 ring->entries;
1675 } else {
1676 idx = 0;
1677 }
1678
1679 pdesc = &ring->desc[idx];
1680 if (rtlpriv->use_new_trx_flow) {
1681 ptx_bd_desc = &ring->buffer_desc[idx];
1682 } else {
1683 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *)pdesc,
1684 true, HW_DESC_OWN);
1685
1686 if ((own == 1) && (hw_queue != BEACON_QUEUE)) {
1687 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1688 "No more TX desc@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n",
1689 hw_queue, ring->idx, idx,
1690 skb_queue_len(&ring->queue));
1691
1692 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock,
1693 flags);
1694 return skb->len;
1695 }
1696 }
1697
1698 if (rtlpriv->cfg->ops->get_available_desc &&
1699 rtlpriv->cfg->ops->get_available_desc(hw, hw_queue) == 0) {
1700 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1701 "get_available_desc fail\n");
1702 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock,
1703 flags);
1704 return skb->len;
1705 }
1706
1707 if (ieee80211_is_data_qos(fc)) {
1708 tid = rtl_get_tid(skb);
1709 if (sta) {
1710 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1711 seq_number = (le16_to_cpu(hdr->seq_ctrl) &
1712 IEEE80211_SCTL_SEQ) >> 4;
1713 seq_number += 1;
1714
1715 if (!ieee80211_has_morefrags(hdr->frame_control))
1716 sta_entry->tids[tid].seq_number = seq_number;
1717 }
1718 }
1719
1720 if (ieee80211_is_data(fc))
1721 rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX);
1722
1723 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
1724 (u8 *)ptx_bd_desc, info, sta, skb, hw_queue, ptcb_desc);
1725
1726 __skb_queue_tail(&ring->queue, skb);
1727
1728 if (rtlpriv->use_new_trx_flow) {
1729 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true,
1730 HW_DESC_OWN, &hw_queue);
1731 } else {
1732 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true,
1733 HW_DESC_OWN, &temp_one);
1734 }
1735
1736 if ((ring->entries - skb_queue_len(&ring->queue)) < 2 &&
1737 hw_queue != BEACON_QUEUE) {
1738 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
1739 "less desc left, stop skb_queue@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n",
1740 hw_queue, ring->idx, idx,
1741 skb_queue_len(&ring->queue));
1742
1743 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
1744 }
1745
1746 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1747
1748 rtlpriv->cfg->ops->tx_polling(hw, hw_queue);
1749
1750 return 0;
1751}
1752
1753static void rtl_pci_flush(struct ieee80211_hw *hw, u32 queues, bool drop)
1754{
1755 struct rtl_priv *rtlpriv = rtl_priv(hw);
1756 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1757 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1758 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1759 u16 i = 0;
1760 int queue_id;
1761 struct rtl8192_tx_ring *ring;
1762
1763 if (mac->skip_scan)
1764 return;
1765
1766 for (queue_id = RTL_PCI_MAX_TX_QUEUE_COUNT - 1; queue_id >= 0;) {
1767 u32 queue_len;
1768
1769 if (((queues >> queue_id) & 0x1) == 0) {
1770 queue_id--;
1771 continue;
1772 }
1773 ring = &pcipriv->dev.tx_ring[queue_id];
1774 queue_len = skb_queue_len(&ring->queue);
1775 if (queue_len == 0 || queue_id == BEACON_QUEUE ||
1776 queue_id == TXCMD_QUEUE) {
1777 queue_id--;
1778 continue;
1779 } else {
1780 msleep(20);
1781 i++;
1782 }
1783
1784
1785 if (rtlpriv->psc.rfpwr_state == ERFOFF ||
1786 is_hal_stop(rtlhal) || i >= 200)
1787 return;
1788 }
1789}
1790
1791static void rtl_pci_deinit(struct ieee80211_hw *hw)
1792{
1793 struct rtl_priv *rtlpriv = rtl_priv(hw);
1794 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1795
1796 _rtl_pci_deinit_trx_ring(hw);
1797
1798 synchronize_irq(rtlpci->pdev->irq);
1799 tasklet_kill(&rtlpriv->works.irq_tasklet);
1800 cancel_work_sync(&rtlpriv->works.lps_change_work);
1801
1802 flush_workqueue(rtlpriv->works.rtl_wq);
1803 destroy_workqueue(rtlpriv->works.rtl_wq);
1804
1805}
1806
1807static int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev)
1808{
1809 struct rtl_priv *rtlpriv = rtl_priv(hw);
1810 int err;
1811
1812 _rtl_pci_init_struct(hw, pdev);
1813
1814 err = _rtl_pci_init_trx_ring(hw);
1815 if (err) {
1816 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1817 "tx ring initialization failed\n");
1818 return err;
1819 }
1820
1821 return 0;
1822}
1823
1824static int rtl_pci_start(struct ieee80211_hw *hw)
1825{
1826 struct rtl_priv *rtlpriv = rtl_priv(hw);
1827 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1828 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1829 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1830
1831 int err;
1832
1833 rtl_pci_reset_trx_ring(hw);
1834
1835 rtlpci->driver_is_goingto_unload = false;
1836 if (rtlpriv->cfg->ops->get_btc_status &&
1837 rtlpriv->cfg->ops->get_btc_status()) {
1838 rtlpriv->btcoexist.btc_ops->btc_init_variables(rtlpriv);
1839 rtlpriv->btcoexist.btc_ops->btc_init_hal_vars(rtlpriv);
1840 }
1841 err = rtlpriv->cfg->ops->hw_init(hw);
1842 if (err) {
1843 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1844 "Failed to config hardware!\n");
1845 return err;
1846 }
1847
1848 rtlpriv->cfg->ops->enable_interrupt(hw);
1849 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "enable_interrupt OK\n");
1850
1851 rtl_init_rx_config(hw);
1852
1853
1854 set_hal_start(rtlhal);
1855
1856 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1857
1858 rtlpci->up_first_time = false;
1859
1860 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "rtl_pci_start OK\n");
1861 return 0;
1862}
1863
1864static void rtl_pci_stop(struct ieee80211_hw *hw)
1865{
1866 struct rtl_priv *rtlpriv = rtl_priv(hw);
1867 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1868 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1869 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1870 unsigned long flags;
1871 u8 RFInProgressTimeOut = 0;
1872
1873 if (rtlpriv->cfg->ops->get_btc_status())
1874 rtlpriv->btcoexist.btc_ops->btc_halt_notify();
1875
1876
1877
1878
1879
1880 set_hal_stop(rtlhal);
1881
1882 rtlpci->driver_is_goingto_unload = true;
1883 rtlpriv->cfg->ops->disable_interrupt(hw);
1884 cancel_work_sync(&rtlpriv->works.lps_change_work);
1885
1886 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1887 while (ppsc->rfchange_inprogress) {
1888 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1889 if (RFInProgressTimeOut > 100) {
1890 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1891 break;
1892 }
1893 mdelay(1);
1894 RFInProgressTimeOut++;
1895 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1896 }
1897 ppsc->rfchange_inprogress = true;
1898 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1899
1900 rtlpriv->cfg->ops->hw_disable(hw);
1901
1902 if (!rtlpriv->max_fw_size)
1903 return;
1904 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1905
1906 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1907 ppsc->rfchange_inprogress = false;
1908 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1909
1910 rtl_pci_enable_aspm(hw);
1911}
1912
1913static bool _rtl_pci_find_adapter(struct pci_dev *pdev,
1914 struct ieee80211_hw *hw)
1915{
1916 struct rtl_priv *rtlpriv = rtl_priv(hw);
1917 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1918 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1919 struct pci_dev *bridge_pdev = pdev->bus->self;
1920 u16 venderid;
1921 u16 deviceid;
1922 u8 revisionid;
1923 u16 irqline;
1924 u8 tmp;
1925
1926 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
1927 venderid = pdev->vendor;
1928 deviceid = pdev->device;
1929 pci_read_config_byte(pdev, 0x8, &revisionid);
1930 pci_read_config_word(pdev, 0x3C, &irqline);
1931
1932
1933
1934
1935
1936
1937
1938 if (deviceid == RTL_PCI_8192SE_DID &&
1939 revisionid == RTL_PCI_REVISION_ID_8192PCIE)
1940 return false;
1941
1942 if (deviceid == RTL_PCI_8192_DID ||
1943 deviceid == RTL_PCI_0044_DID ||
1944 deviceid == RTL_PCI_0047_DID ||
1945 deviceid == RTL_PCI_8192SE_DID ||
1946 deviceid == RTL_PCI_8174_DID ||
1947 deviceid == RTL_PCI_8173_DID ||
1948 deviceid == RTL_PCI_8172_DID ||
1949 deviceid == RTL_PCI_8171_DID) {
1950 switch (revisionid) {
1951 case RTL_PCI_REVISION_ID_8192PCIE:
1952 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1953 "8192 PCI-E is found - vid/did=%x/%x\n",
1954 venderid, deviceid);
1955 rtlhal->hw_type = HARDWARE_TYPE_RTL8192E;
1956 return false;
1957 case RTL_PCI_REVISION_ID_8192SE:
1958 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1959 "8192SE is found - vid/did=%x/%x\n",
1960 venderid, deviceid);
1961 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1962 break;
1963 default:
1964 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1965 "Err: Unknown device - vid/did=%x/%x\n",
1966 venderid, deviceid);
1967 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1968 break;
1969
1970 }
1971 } else if (deviceid == RTL_PCI_8723AE_DID) {
1972 rtlhal->hw_type = HARDWARE_TYPE_RTL8723AE;
1973 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1974 "8723AE PCI-E is found - "
1975 "vid/did=%x/%x\n", venderid, deviceid);
1976 } else if (deviceid == RTL_PCI_8192CET_DID ||
1977 deviceid == RTL_PCI_8192CE_DID ||
1978 deviceid == RTL_PCI_8191CE_DID ||
1979 deviceid == RTL_PCI_8188CE_DID) {
1980 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE;
1981 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1982 "8192C PCI-E is found - vid/did=%x/%x\n",
1983 venderid, deviceid);
1984 } else if (deviceid == RTL_PCI_8192DE_DID ||
1985 deviceid == RTL_PCI_8192DE_DID2) {
1986 rtlhal->hw_type = HARDWARE_TYPE_RTL8192DE;
1987 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1988 "8192D PCI-E is found - vid/did=%x/%x\n",
1989 venderid, deviceid);
1990 } else if (deviceid == RTL_PCI_8188EE_DID) {
1991 rtlhal->hw_type = HARDWARE_TYPE_RTL8188EE;
1992 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1993 "Find adapter, Hardware type is 8188EE\n");
1994 } else if (deviceid == RTL_PCI_8723BE_DID) {
1995 rtlhal->hw_type = HARDWARE_TYPE_RTL8723BE;
1996 RT_TRACE(rtlpriv, COMP_INIT , DBG_LOUD,
1997 "Find adapter, Hardware type is 8723BE\n");
1998 } else if (deviceid == RTL_PCI_8192EE_DID) {
1999 rtlhal->hw_type = HARDWARE_TYPE_RTL8192EE;
2000 RT_TRACE(rtlpriv, COMP_INIT , DBG_LOUD,
2001 "Find adapter, Hardware type is 8192EE\n");
2002 } else if (deviceid == RTL_PCI_8821AE_DID) {
2003 rtlhal->hw_type = HARDWARE_TYPE_RTL8821AE;
2004 RT_TRACE(rtlpriv, COMP_INIT , DBG_LOUD,
2005 "Find adapter, Hardware type is 8821AE\n");
2006 } else if (deviceid == RTL_PCI_8812AE_DID) {
2007 rtlhal->hw_type = HARDWARE_TYPE_RTL8812AE;
2008 RT_TRACE(rtlpriv, COMP_INIT , DBG_LOUD,
2009 "Find adapter, Hardware type is 8812AE\n");
2010 } else {
2011 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2012 "Err: Unknown device - vid/did=%x/%x\n",
2013 venderid, deviceid);
2014
2015 rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE;
2016 }
2017
2018 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) {
2019 if (revisionid == 0 || revisionid == 1) {
2020 if (revisionid == 0) {
2021 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2022 "Find 92DE MAC0\n");
2023 rtlhal->interfaceindex = 0;
2024 } else if (revisionid == 1) {
2025 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2026 "Find 92DE MAC1\n");
2027 rtlhal->interfaceindex = 1;
2028 }
2029 } else {
2030 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2031 "Unknown device - VendorID/DeviceID=%x/%x, Revision=%x\n",
2032 venderid, deviceid, revisionid);
2033 rtlhal->interfaceindex = 0;
2034 }
2035 }
2036
2037
2038 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192EE)
2039 rtlpriv->use_new_trx_flow = true;
2040 else
2041 rtlpriv->use_new_trx_flow = false;
2042
2043
2044 pcipriv->ndis_adapter.busnumber = pdev->bus->number;
2045 pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn);
2046 pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn);
2047
2048
2049 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
2050
2051
2052
2053 if (bridge_pdev) {
2054
2055 pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor;
2056 for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) {
2057 if (bridge_pdev->vendor == pcibridge_vendors[tmp]) {
2058 pcipriv->ndis_adapter.pcibridge_vendor = tmp;
2059 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2060 "Pci Bridge Vendor is found index: %d\n",
2061 tmp);
2062 break;
2063 }
2064 }
2065 }
2066
2067 if (pcipriv->ndis_adapter.pcibridge_vendor !=
2068 PCI_BRIDGE_VENDOR_UNKNOWN) {
2069 pcipriv->ndis_adapter.pcibridge_busnum =
2070 bridge_pdev->bus->number;
2071 pcipriv->ndis_adapter.pcibridge_devnum =
2072 PCI_SLOT(bridge_pdev->devfn);
2073 pcipriv->ndis_adapter.pcibridge_funcnum =
2074 PCI_FUNC(bridge_pdev->devfn);
2075 pcipriv->ndis_adapter.pcibridge_pciehdr_offset =
2076 pci_pcie_cap(bridge_pdev);
2077 pcipriv->ndis_adapter.num4bytes =
2078 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10) / 4;
2079
2080 rtl_pci_get_linkcontrol_field(hw);
2081
2082 if (pcipriv->ndis_adapter.pcibridge_vendor ==
2083 PCI_BRIDGE_VENDOR_AMD) {
2084 pcipriv->ndis_adapter.amd_l1_patch =
2085 rtl_pci_get_amd_l1_patch(hw);
2086 }
2087 }
2088
2089 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2090 "pcidev busnumber:devnumber:funcnumber:vendor:link_ctl %d:%d:%d:%x:%x\n",
2091 pcipriv->ndis_adapter.busnumber,
2092 pcipriv->ndis_adapter.devnumber,
2093 pcipriv->ndis_adapter.funcnumber,
2094 pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg);
2095
2096 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2097 "pci_bridge busnumber:devnumber:funcnumber:vendor:pcie_cap:link_ctl_reg:amd %d:%d:%d:%x:%x:%x:%x\n",
2098 pcipriv->ndis_adapter.pcibridge_busnum,
2099 pcipriv->ndis_adapter.pcibridge_devnum,
2100 pcipriv->ndis_adapter.pcibridge_funcnum,
2101 pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor],
2102 pcipriv->ndis_adapter.pcibridge_pciehdr_offset,
2103 pcipriv->ndis_adapter.pcibridge_linkctrlreg,
2104 pcipriv->ndis_adapter.amd_l1_patch);
2105
2106 rtl_pci_parse_configuration(pdev, hw);
2107 list_add_tail(&rtlpriv->list, &rtlpriv->glb_var->glb_priv_list);
2108
2109 return true;
2110}
2111
2112static int rtl_pci_intr_mode_msi(struct ieee80211_hw *hw)
2113{
2114 struct rtl_priv *rtlpriv = rtl_priv(hw);
2115 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2116 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2117 int ret;
2118
2119 ret = pci_enable_msi(rtlpci->pdev);
2120 if (ret < 0)
2121 return ret;
2122
2123 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
2124 IRQF_SHARED, KBUILD_MODNAME, hw);
2125 if (ret < 0) {
2126 pci_disable_msi(rtlpci->pdev);
2127 return ret;
2128 }
2129
2130 rtlpci->using_msi = true;
2131
2132 RT_TRACE(rtlpriv, COMP_INIT|COMP_INTR, DBG_DMESG,
2133 "MSI Interrupt Mode!\n");
2134 return 0;
2135}
2136
2137static int rtl_pci_intr_mode_legacy(struct ieee80211_hw *hw)
2138{
2139 struct rtl_priv *rtlpriv = rtl_priv(hw);
2140 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2141 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2142 int ret;
2143
2144 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
2145 IRQF_SHARED, KBUILD_MODNAME, hw);
2146 if (ret < 0)
2147 return ret;
2148
2149 rtlpci->using_msi = false;
2150 RT_TRACE(rtlpriv, COMP_INIT|COMP_INTR, DBG_DMESG,
2151 "Pin-based Interrupt Mode!\n");
2152 return 0;
2153}
2154
2155static int rtl_pci_intr_mode_decide(struct ieee80211_hw *hw)
2156{
2157 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2158 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2159 int ret;
2160
2161 if (rtlpci->msi_support) {
2162 ret = rtl_pci_intr_mode_msi(hw);
2163 if (ret < 0)
2164 ret = rtl_pci_intr_mode_legacy(hw);
2165 } else {
2166 ret = rtl_pci_intr_mode_legacy(hw);
2167 }
2168 return ret;
2169}
2170
2171int rtl_pci_probe(struct pci_dev *pdev,
2172 const struct pci_device_id *id)
2173{
2174 struct ieee80211_hw *hw = NULL;
2175
2176 struct rtl_priv *rtlpriv = NULL;
2177 struct rtl_pci_priv *pcipriv = NULL;
2178 struct rtl_pci *rtlpci;
2179 unsigned long pmem_start, pmem_len, pmem_flags;
2180 int err;
2181
2182 err = pci_enable_device(pdev);
2183 if (err) {
2184 RT_ASSERT(false, "%s : Cannot enable new PCI device\n",
2185 pci_name(pdev));
2186 return err;
2187 }
2188
2189 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
2190 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
2191 RT_ASSERT(false,
2192 "Unable to obtain 32bit DMA for consistent allocations\n");
2193 err = -ENOMEM;
2194 goto fail1;
2195 }
2196 }
2197
2198 pci_set_master(pdev);
2199
2200 hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) +
2201 sizeof(struct rtl_priv), &rtl_ops);
2202 if (!hw) {
2203 RT_ASSERT(false,
2204 "%s : ieee80211 alloc failed\n", pci_name(pdev));
2205 err = -ENOMEM;
2206 goto fail1;
2207 }
2208
2209 SET_IEEE80211_DEV(hw, &pdev->dev);
2210 pci_set_drvdata(pdev, hw);
2211
2212 rtlpriv = hw->priv;
2213 rtlpriv->hw = hw;
2214 pcipriv = (void *)rtlpriv->priv;
2215 pcipriv->dev.pdev = pdev;
2216 init_completion(&rtlpriv->firmware_loading_complete);
2217
2218 rtlpriv->proximity.proxim_on = false;
2219
2220 pcipriv = (void *)rtlpriv->priv;
2221 pcipriv->dev.pdev = pdev;
2222
2223
2224 rtlpriv->rtlhal.interface = INTF_PCI;
2225 rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data);
2226 rtlpriv->intf_ops = &rtl_pci_ops;
2227 rtlpriv->glb_var = &rtl_global_var;
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237 rtl_dbgp_flag_init(hw);
2238
2239
2240 err = pci_request_regions(pdev, KBUILD_MODNAME);
2241 if (err) {
2242 RT_ASSERT(false, "Can't obtain PCI resources\n");
2243 goto fail1;
2244 }
2245
2246 pmem_start = pci_resource_start(pdev, rtlpriv->cfg->bar_id);
2247 pmem_len = pci_resource_len(pdev, rtlpriv->cfg->bar_id);
2248 pmem_flags = pci_resource_flags(pdev, rtlpriv->cfg->bar_id);
2249
2250
2251 rtlpriv->io.pci_mem_start =
2252 (unsigned long)pci_iomap(pdev,
2253 rtlpriv->cfg->bar_id, pmem_len);
2254 if (rtlpriv->io.pci_mem_start == 0) {
2255 RT_ASSERT(false, "Can't map PCI mem\n");
2256 err = -ENOMEM;
2257 goto fail2;
2258 }
2259
2260 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2261 "mem mapped space: start: 0x%08lx len:%08lx flags:%08lx, after map:0x%08lx\n",
2262 pmem_start, pmem_len, pmem_flags,
2263 rtlpriv->io.pci_mem_start);
2264
2265
2266 pci_write_config_byte(pdev, 0x81, 0);
2267
2268 pci_write_config_byte(pdev, 0x44, 0);
2269 pci_write_config_byte(pdev, 0x04, 0x06);
2270 pci_write_config_byte(pdev, 0x04, 0x07);
2271
2272
2273 if (!_rtl_pci_find_adapter(pdev, hw)) {
2274 err = -ENODEV;
2275 goto fail3;
2276 }
2277
2278
2279 _rtl_pci_io_handler_init(&pdev->dev, hw);
2280
2281
2282 rtlpriv->cfg->ops->read_eeprom_info(hw);
2283
2284 if (rtlpriv->cfg->ops->init_sw_vars(hw)) {
2285 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Can't init_sw_vars\n");
2286 err = -ENODEV;
2287 goto fail3;
2288 }
2289 rtlpriv->cfg->ops->init_sw_leds(hw);
2290
2291
2292 rtl_pci_init_aspm(hw);
2293
2294
2295 err = rtl_init_core(hw);
2296 if (err) {
2297 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2298 "Can't allocate sw for mac80211\n");
2299 goto fail3;
2300 }
2301
2302
2303 err = rtl_pci_init(hw, pdev);
2304 if (err) {
2305 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Failed to init PCI\n");
2306 goto fail3;
2307 }
2308
2309 err = ieee80211_register_hw(hw);
2310 if (err) {
2311 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2312 "Can't register mac80211 hw.\n");
2313 err = -ENODEV;
2314 goto fail3;
2315 }
2316 rtlpriv->mac80211.mac80211_registered = 1;
2317
2318 err = sysfs_create_group(&pdev->dev.kobj, &rtl_attribute_group);
2319 if (err) {
2320 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2321 "failed to create sysfs device attributes\n");
2322 goto fail3;
2323 }
2324
2325
2326 rtl_init_rfkill(hw);
2327
2328 rtlpci = rtl_pcidev(pcipriv);
2329 err = rtl_pci_intr_mode_decide(hw);
2330 if (err) {
2331 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2332 "%s: failed to register IRQ handler\n",
2333 wiphy_name(hw->wiphy));
2334 goto fail3;
2335 }
2336 rtlpci->irq_alloc = 1;
2337
2338 set_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
2339 return 0;
2340
2341fail3:
2342 pci_set_drvdata(pdev, NULL);
2343 rtl_deinit_core(hw);
2344
2345 if (rtlpriv->io.pci_mem_start != 0)
2346 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
2347
2348fail2:
2349 pci_release_regions(pdev);
2350 complete(&rtlpriv->firmware_loading_complete);
2351
2352fail1:
2353 if (hw)
2354 ieee80211_free_hw(hw);
2355 pci_disable_device(pdev);
2356
2357 return err;
2358
2359}
2360EXPORT_SYMBOL(rtl_pci_probe);
2361
2362void rtl_pci_disconnect(struct pci_dev *pdev)
2363{
2364 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2365 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2366 struct rtl_priv *rtlpriv = rtl_priv(hw);
2367 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2368 struct rtl_mac *rtlmac = rtl_mac(rtlpriv);
2369
2370
2371 wait_for_completion(&rtlpriv->firmware_loading_complete);
2372 clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
2373
2374 sysfs_remove_group(&pdev->dev.kobj, &rtl_attribute_group);
2375
2376
2377 if (rtlmac->mac80211_registered == 1) {
2378 ieee80211_unregister_hw(hw);
2379 rtlmac->mac80211_registered = 0;
2380 } else {
2381 rtl_deinit_deferred_work(hw);
2382 rtlpriv->intf_ops->adapter_stop(hw);
2383 }
2384 rtlpriv->cfg->ops->disable_interrupt(hw);
2385
2386
2387 rtl_deinit_rfkill(hw);
2388
2389 rtl_pci_deinit(hw);
2390 rtl_deinit_core(hw);
2391 rtlpriv->cfg->ops->deinit_sw_vars(hw);
2392
2393 if (rtlpci->irq_alloc) {
2394 free_irq(rtlpci->pdev->irq, hw);
2395 rtlpci->irq_alloc = 0;
2396 }
2397
2398 if (rtlpci->using_msi)
2399 pci_disable_msi(rtlpci->pdev);
2400
2401 list_del(&rtlpriv->list);
2402 if (rtlpriv->io.pci_mem_start != 0) {
2403 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
2404 pci_release_regions(pdev);
2405 }
2406
2407 pci_disable_device(pdev);
2408
2409 rtl_pci_disable_aspm(hw);
2410
2411 pci_set_drvdata(pdev, NULL);
2412
2413 ieee80211_free_hw(hw);
2414}
2415EXPORT_SYMBOL(rtl_pci_disconnect);
2416
2417#ifdef CONFIG_PM_SLEEP
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433int rtl_pci_suspend(struct device *dev)
2434{
2435 struct pci_dev *pdev = to_pci_dev(dev);
2436 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2437 struct rtl_priv *rtlpriv = rtl_priv(hw);
2438
2439 rtlpriv->cfg->ops->hw_suspend(hw);
2440 rtl_deinit_rfkill(hw);
2441
2442 return 0;
2443}
2444EXPORT_SYMBOL(rtl_pci_suspend);
2445
2446int rtl_pci_resume(struct device *dev)
2447{
2448 struct pci_dev *pdev = to_pci_dev(dev);
2449 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2450 struct rtl_priv *rtlpriv = rtl_priv(hw);
2451
2452 rtlpriv->cfg->ops->hw_resume(hw);
2453 rtl_init_rfkill(hw);
2454 return 0;
2455}
2456EXPORT_SYMBOL(rtl_pci_resume);
2457#endif
2458
2459const struct rtl_intf_ops rtl_pci_ops = {
2460 .read_efuse_byte = read_efuse_byte,
2461 .adapter_start = rtl_pci_start,
2462 .adapter_stop = rtl_pci_stop,
2463 .check_buddy_priv = rtl_pci_check_buddy_priv,
2464 .adapter_tx = rtl_pci_tx,
2465 .flush = rtl_pci_flush,
2466 .reset_trx_ring = rtl_pci_reset_trx_ring,
2467 .waitq_insert = rtl_pci_tx_chk_waitq_insert,
2468
2469 .disable_aspm = rtl_pci_disable_aspm,
2470 .enable_aspm = rtl_pci_enable_aspm,
2471};
2472
