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30#include "../wifi.h"
31#include "../efuse.h"
32#include "../base.h"
33#include "../cam.h"
34#include "../ps.h"
35#include "../usb.h"
36#include "reg.h"
37#include "def.h"
38#include "phy.h"
39#include "../rtl8192c/phy_common.h"
40#include "mac.h"
41#include "dm.h"
42#include "../rtl8192c/dm_common.h"
43#include "../rtl8192c/fw_common.h"
44#include "hw.h"
45#include "../rtl8192ce/hw.h"
46#include "trx.h"
47#include "led.h"
48#include "table.h"
49
50static void _rtl92cu_phy_param_tab_init(struct ieee80211_hw *hw)
51{
52 struct rtl_priv *rtlpriv = rtl_priv(hw);
53 struct rtl_phy *rtlphy = &(rtlpriv->phy);
54 struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv);
55
56 rtlphy->hwparam_tables[MAC_REG].length = RTL8192CUMAC_2T_ARRAYLENGTH;
57 rtlphy->hwparam_tables[MAC_REG].pdata = RTL8192CUMAC_2T_ARRAY;
58 if (IS_HIGHT_PA(rtlefuse->board_type)) {
59 rtlphy->hwparam_tables[PHY_REG_PG].length =
60 RTL8192CUPHY_REG_Array_PG_HPLength;
61 rtlphy->hwparam_tables[PHY_REG_PG].pdata =
62 RTL8192CUPHY_REG_Array_PG_HP;
63 } else {
64 rtlphy->hwparam_tables[PHY_REG_PG].length =
65 RTL8192CUPHY_REG_ARRAY_PGLENGTH;
66 rtlphy->hwparam_tables[PHY_REG_PG].pdata =
67 RTL8192CUPHY_REG_ARRAY_PG;
68 }
69
70 rtlphy->hwparam_tables[PHY_REG_2T].length =
71 RTL8192CUPHY_REG_2TARRAY_LENGTH;
72 rtlphy->hwparam_tables[PHY_REG_2T].pdata =
73 RTL8192CUPHY_REG_2TARRAY;
74 rtlphy->hwparam_tables[RADIOA_2T].length =
75 RTL8192CURADIOA_2TARRAYLENGTH;
76 rtlphy->hwparam_tables[RADIOA_2T].pdata =
77 RTL8192CURADIOA_2TARRAY;
78 rtlphy->hwparam_tables[RADIOB_2T].length =
79 RTL8192CURADIOB_2TARRAYLENGTH;
80 rtlphy->hwparam_tables[RADIOB_2T].pdata =
81 RTL8192CU_RADIOB_2TARRAY;
82 rtlphy->hwparam_tables[AGCTAB_2T].length =
83 RTL8192CUAGCTAB_2TARRAYLENGTH;
84 rtlphy->hwparam_tables[AGCTAB_2T].pdata =
85 RTL8192CUAGCTAB_2TARRAY;
86
87 if (IS_HIGHT_PA(rtlefuse->board_type)) {
88 rtlphy->hwparam_tables[PHY_REG_1T].length =
89 RTL8192CUPHY_REG_1T_HPArrayLength;
90 rtlphy->hwparam_tables[PHY_REG_1T].pdata =
91 RTL8192CUPHY_REG_1T_HPArray;
92 rtlphy->hwparam_tables[RADIOA_1T].length =
93 RTL8192CURadioA_1T_HPArrayLength;
94 rtlphy->hwparam_tables[RADIOA_1T].pdata =
95 RTL8192CURadioA_1T_HPArray;
96 rtlphy->hwparam_tables[RADIOB_1T].length =
97 RTL8192CURADIOB_1TARRAYLENGTH;
98 rtlphy->hwparam_tables[RADIOB_1T].pdata =
99 RTL8192CU_RADIOB_1TARRAY;
100 rtlphy->hwparam_tables[AGCTAB_1T].length =
101 RTL8192CUAGCTAB_1T_HPArrayLength;
102 rtlphy->hwparam_tables[AGCTAB_1T].pdata =
103 Rtl8192CUAGCTAB_1T_HPArray;
104 } else {
105 rtlphy->hwparam_tables[PHY_REG_1T].length =
106 RTL8192CUPHY_REG_1TARRAY_LENGTH;
107 rtlphy->hwparam_tables[PHY_REG_1T].pdata =
108 RTL8192CUPHY_REG_1TARRAY;
109 rtlphy->hwparam_tables[RADIOA_1T].length =
110 RTL8192CURADIOA_1TARRAYLENGTH;
111 rtlphy->hwparam_tables[RADIOA_1T].pdata =
112 RTL8192CU_RADIOA_1TARRAY;
113 rtlphy->hwparam_tables[RADIOB_1T].length =
114 RTL8192CURADIOB_1TARRAYLENGTH;
115 rtlphy->hwparam_tables[RADIOB_1T].pdata =
116 RTL8192CU_RADIOB_1TARRAY;
117 rtlphy->hwparam_tables[AGCTAB_1T].length =
118 RTL8192CUAGCTAB_1TARRAYLENGTH;
119 rtlphy->hwparam_tables[AGCTAB_1T].pdata =
120 RTL8192CUAGCTAB_1TARRAY;
121 }
122}
123
124static void _rtl92cu_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
125 bool autoload_fail,
126 u8 *hwinfo)
127{
128 struct rtl_priv *rtlpriv = rtl_priv(hw);
129 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
130 u8 rf_path, index, tempval;
131 u16 i;
132
133 for (rf_path = 0; rf_path < 2; rf_path++) {
134 for (i = 0; i < 3; i++) {
135 if (!autoload_fail) {
136 rtlefuse->
137 eeprom_chnlarea_txpwr_cck[rf_path][i] =
138 hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i];
139 rtlefuse->
140 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
141 hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 +
142 i];
143 } else {
144 rtlefuse->
145 eeprom_chnlarea_txpwr_cck[rf_path][i] =
146 EEPROM_DEFAULT_TXPOWERLEVEL;
147 rtlefuse->
148 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
149 EEPROM_DEFAULT_TXPOWERLEVEL;
150 }
151 }
152 }
153 for (i = 0; i < 3; i++) {
154 if (!autoload_fail)
155 tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i];
156 else
157 tempval = EEPROM_DEFAULT_HT40_2SDIFF;
158 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_A][i] =
159 (tempval & 0xf);
160 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_B][i] =
161 ((tempval & 0xf0) >> 4);
162 }
163 for (rf_path = 0; rf_path < 2; rf_path++)
164 for (i = 0; i < 3; i++)
165 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
166 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n",
167 rf_path, i,
168 rtlefuse->
169 eeprom_chnlarea_txpwr_cck[rf_path][i]);
170 for (rf_path = 0; rf_path < 2; rf_path++)
171 for (i = 0; i < 3; i++)
172 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
173 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
174 rf_path, i,
175 rtlefuse->
176 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i]);
177 for (rf_path = 0; rf_path < 2; rf_path++)
178 for (i = 0; i < 3; i++)
179 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
180 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
181 rf_path, i,
182 rtlefuse->
183 eprom_chnl_txpwr_ht40_2sdf[rf_path][i]);
184 for (rf_path = 0; rf_path < 2; rf_path++) {
185 for (i = 0; i < 14; i++) {
186 index = rtl92c_get_chnl_group((u8)i);
187 rtlefuse->txpwrlevel_cck[rf_path][i] =
188 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][index];
189 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
190 rtlefuse->
191 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index];
192 if ((rtlefuse->
193 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index] -
194 rtlefuse->
195 eprom_chnl_txpwr_ht40_2sdf[rf_path][index])
196 > 0) {
197 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
198 rtlefuse->
199 eeprom_chnlarea_txpwr_ht40_1s[rf_path]
200 [index] - rtlefuse->
201 eprom_chnl_txpwr_ht40_2sdf[rf_path]
202 [index];
203 } else {
204 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0;
205 }
206 }
207 for (i = 0; i < 14; i++) {
208 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
209 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n", rf_path, i,
210 rtlefuse->txpwrlevel_cck[rf_path][i],
211 rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
212 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]);
213 }
214 }
215 for (i = 0; i < 3; i++) {
216 if (!autoload_fail) {
217 rtlefuse->eeprom_pwrlimit_ht40[i] =
218 hwinfo[EEPROM_TXPWR_GROUP + i];
219 rtlefuse->eeprom_pwrlimit_ht20[i] =
220 hwinfo[EEPROM_TXPWR_GROUP + 3 + i];
221 } else {
222 rtlefuse->eeprom_pwrlimit_ht40[i] = 0;
223 rtlefuse->eeprom_pwrlimit_ht20[i] = 0;
224 }
225 }
226 for (rf_path = 0; rf_path < 2; rf_path++) {
227 for (i = 0; i < 14; i++) {
228 index = rtl92c_get_chnl_group((u8)i);
229 if (rf_path == RF90_PATH_A) {
230 rtlefuse->pwrgroup_ht20[rf_path][i] =
231 (rtlefuse->eeprom_pwrlimit_ht20[index]
232 & 0xf);
233 rtlefuse->pwrgroup_ht40[rf_path][i] =
234 (rtlefuse->eeprom_pwrlimit_ht40[index]
235 & 0xf);
236 } else if (rf_path == RF90_PATH_B) {
237 rtlefuse->pwrgroup_ht20[rf_path][i] =
238 ((rtlefuse->eeprom_pwrlimit_ht20[index]
239 & 0xf0) >> 4);
240 rtlefuse->pwrgroup_ht40[rf_path][i] =
241 ((rtlefuse->eeprom_pwrlimit_ht40[index]
242 & 0xf0) >> 4);
243 }
244 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
245 "RF-%d pwrgroup_ht20[%d] = 0x%x\n",
246 rf_path, i,
247 rtlefuse->pwrgroup_ht20[rf_path][i]);
248 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
249 "RF-%d pwrgroup_ht40[%d] = 0x%x\n",
250 rf_path, i,
251 rtlefuse->pwrgroup_ht40[rf_path][i]);
252 }
253 }
254 for (i = 0; i < 14; i++) {
255 index = rtl92c_get_chnl_group((u8)i);
256 if (!autoload_fail)
257 tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index];
258 else
259 tempval = EEPROM_DEFAULT_HT20_DIFF;
260 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
261 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
262 ((tempval >> 4) & 0xF);
263 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3))
264 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0;
265 if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3))
266 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0;
267 index = rtl92c_get_chnl_group((u8)i);
268 if (!autoload_fail)
269 tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index];
270 else
271 tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
272 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF);
273 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
274 ((tempval >> 4) & 0xF);
275 }
276 rtlefuse->legacy_ht_txpowerdiff =
277 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7];
278 for (i = 0; i < 14; i++)
279 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
280 "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n",
281 i, rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]);
282 for (i = 0; i < 14; i++)
283 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
284 "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n",
285 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]);
286 for (i = 0; i < 14; i++)
287 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
288 "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n",
289 i, rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]);
290 for (i = 0; i < 14; i++)
291 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
292 "RF-B Legacy to HT40 Diff[%d] = 0x%x\n",
293 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]);
294 if (!autoload_fail)
295 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7);
296 else
297 rtlefuse->eeprom_regulatory = 0;
298 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
299 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
300 if (!autoload_fail) {
301 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A];
302 rtlefuse->eeprom_tssi[RF90_PATH_B] = hwinfo[EEPROM_TSSI_B];
303 } else {
304 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI;
305 rtlefuse->eeprom_tssi[RF90_PATH_B] = EEPROM_DEFAULT_TSSI;
306 }
307 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
308 "TSSI_A = 0x%x, TSSI_B = 0x%x\n",
309 rtlefuse->eeprom_tssi[RF90_PATH_A],
310 rtlefuse->eeprom_tssi[RF90_PATH_B]);
311 if (!autoload_fail)
312 tempval = hwinfo[EEPROM_THERMAL_METER];
313 else
314 tempval = EEPROM_DEFAULT_THERMALMETER;
315 rtlefuse->eeprom_thermalmeter = (tempval & 0x1f);
316 if (rtlefuse->eeprom_thermalmeter < 0x06 ||
317 rtlefuse->eeprom_thermalmeter > 0x1c)
318 rtlefuse->eeprom_thermalmeter = 0x12;
319 if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail)
320 rtlefuse->apk_thermalmeterignore = true;
321 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
322 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
323 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
324}
325
326static void _rtl92cu_read_board_type(struct ieee80211_hw *hw, u8 *contents)
327{
328 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
329 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
330 u8 boardType;
331
332 if (IS_NORMAL_CHIP(rtlhal->version)) {
333 boardType = ((contents[EEPROM_RF_OPT1]) &
334 BOARD_TYPE_NORMAL_MASK) >> 5;
335 } else {
336 boardType = contents[EEPROM_RF_OPT4];
337 boardType &= BOARD_TYPE_TEST_MASK;
338 }
339 rtlefuse->board_type = boardType;
340 if (IS_HIGHT_PA(rtlefuse->board_type))
341 rtlefuse->external_pa = 1;
342 pr_info("Board Type %x\n", rtlefuse->board_type);
343}
344
345static void _rtl92cu_read_adapter_info(struct ieee80211_hw *hw)
346{
347 struct rtl_priv *rtlpriv = rtl_priv(hw);
348 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
349 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
350 int params[] = {RTL8190_EEPROM_ID, EEPROM_VID, EEPROM_DID,
351 EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR,
352 EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID,
353 0};
354 u8 *hwinfo;
355
356 hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL);
357 if (!hwinfo)
358 return;
359
360 if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params))
361 goto exit;
362
363 _rtl92cu_read_txpower_info_from_hwpg(hw,
364 rtlefuse->autoload_failflag, hwinfo);
365 _rtl92cu_read_board_type(hw, hwinfo);
366
367 rtlefuse->txpwr_fromeprom = true;
368 if (rtlhal->oem_id == RT_CID_DEFAULT) {
369 switch (rtlefuse->eeprom_oemid) {
370 case EEPROM_CID_DEFAULT:
371 if (rtlefuse->eeprom_did == 0x8176) {
372 if ((rtlefuse->eeprom_svid == 0x103C &&
373 rtlefuse->eeprom_smid == 0x1629))
374 rtlhal->oem_id = RT_CID_819X_HP;
375 else
376 rtlhal->oem_id = RT_CID_DEFAULT;
377 } else {
378 rtlhal->oem_id = RT_CID_DEFAULT;
379 }
380 break;
381 case EEPROM_CID_TOSHIBA:
382 rtlhal->oem_id = RT_CID_TOSHIBA;
383 break;
384 case EEPROM_CID_QMI:
385 rtlhal->oem_id = RT_CID_819X_QMI;
386 break;
387 case EEPROM_CID_WHQL:
388 default:
389 rtlhal->oem_id = RT_CID_DEFAULT;
390 break;
391 }
392 }
393exit:
394 kfree(hwinfo);
395}
396
397static void _rtl92cu_hal_customized_behavior(struct ieee80211_hw *hw)
398{
399 struct rtl_priv *rtlpriv = rtl_priv(hw);
400 struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw);
401 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
402
403 switch (rtlhal->oem_id) {
404 case RT_CID_819X_HP:
405 usb_priv->ledctl.led_opendrain = true;
406 break;
407 case RT_CID_819X_LENOVO:
408 case RT_CID_DEFAULT:
409 case RT_CID_TOSHIBA:
410 case RT_CID_CCX:
411 case RT_CID_819X_ACER:
412 case RT_CID_WHQL:
413 default:
414 break;
415 }
416 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "RT Customized ID: 0x%02X\n",
417 rtlhal->oem_id);
418}
419
420void rtl92cu_read_eeprom_info(struct ieee80211_hw *hw)
421{
422
423 struct rtl_priv *rtlpriv = rtl_priv(hw);
424 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
425 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
426 u8 tmp_u1b;
427
428 if (!IS_NORMAL_CHIP(rtlhal->version))
429 return;
430 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
431 rtlefuse->epromtype = (tmp_u1b & BOOT_FROM_EEPROM) ?
432 EEPROM_93C46 : EEPROM_BOOT_EFUSE;
433 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from %s\n",
434 tmp_u1b & BOOT_FROM_EEPROM ? "EERROM" : "EFUSE");
435 rtlefuse->autoload_failflag = (tmp_u1b & EEPROM_EN) ? false : true;
436 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload %s\n",
437 tmp_u1b & EEPROM_EN ? "OK!!" : "ERR!!");
438 _rtl92cu_read_adapter_info(hw);
439 _rtl92cu_hal_customized_behavior(hw);
440 return;
441}
442
443static int _rtl92cu_init_power_on(struct ieee80211_hw *hw)
444{
445 struct rtl_priv *rtlpriv = rtl_priv(hw);
446 int status = 0;
447 u16 value16;
448 u8 value8;
449
450 u32 pollingCount = 0;
451
452 do {
453 if (rtl_read_byte(rtlpriv, REG_APS_FSMCO) & PFM_ALDN) {
454 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
455 "Autoload Done!\n");
456 break;
457 }
458 if (pollingCount++ > 100) {
459 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
460 "Failed to polling REG_APS_FSMCO[PFM_ALDN] done!\n");
461 return -ENODEV;
462 }
463 } while (true);
464
465 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0);
466
467
468 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
469 udelay(100);
470 value8 = rtl_read_byte(rtlpriv, REG_LDOV12D_CTRL);
471 if (0 == (value8 & LDV12_EN)) {
472 value8 |= LDV12_EN;
473 rtl_write_byte(rtlpriv, REG_LDOV12D_CTRL, value8);
474 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
475 " power-on :REG_LDOV12D_CTRL Reg0x21:0x%02x\n",
476 value8);
477 udelay(100);
478 value8 = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL);
479 value8 &= ~ISO_MD2PP;
480 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, value8);
481 }
482
483 pollingCount = 0;
484 value16 = rtl_read_word(rtlpriv, REG_APS_FSMCO);
485 value16 |= APFM_ONMAC;
486 rtl_write_word(rtlpriv, REG_APS_FSMCO, value16);
487 do {
488 if (!(rtl_read_word(rtlpriv, REG_APS_FSMCO) & APFM_ONMAC)) {
489 pr_info("MAC auto ON okay!\n");
490 break;
491 }
492 if (pollingCount++ > 1000) {
493 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
494 "Failed to polling REG_APS_FSMCO[APFM_ONMAC] done!\n");
495 return -ENODEV;
496 }
497 } while (true);
498
499 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x0812);
500
501 value16 = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL);
502 value16 &= ~ISO_DIOR;
503 rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, value16);
504
505 pollingCount = 0;
506 rtl_write_byte(rtlpriv, REG_APSD_CTRL, (rtl_read_byte(rtlpriv,
507 REG_APSD_CTRL) & ~BIT(6)));
508 do {
509 pollingCount++;
510 } while ((pollingCount < 200) &&
511 (rtl_read_byte(rtlpriv, REG_APSD_CTRL) & BIT(7)));
512
513 value16 = rtl_read_word(rtlpriv, REG_CR);
514 value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN |
515 PROTOCOL_EN | SCHEDULE_EN | MACTXEN | MACRXEN | ENSEC);
516 rtl_write_word(rtlpriv, REG_CR, value16);
517 return status;
518}
519
520static void _rtl92cu_init_queue_reserved_page(struct ieee80211_hw *hw,
521 bool wmm_enable,
522 u8 out_ep_num,
523 u8 queue_sel)
524{
525 struct rtl_priv *rtlpriv = rtl_priv(hw);
526 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
527 bool isChipN = IS_NORMAL_CHIP(rtlhal->version);
528 u32 outEPNum = (u32)out_ep_num;
529 u32 numHQ = 0;
530 u32 numLQ = 0;
531 u32 numNQ = 0;
532 u32 numPubQ;
533 u32 value32;
534 u8 value8;
535 u32 txQPageNum, txQPageUnit, txQRemainPage;
536
537 if (!wmm_enable) {
538 numPubQ = (isChipN) ? CHIP_B_PAGE_NUM_PUBQ :
539 CHIP_A_PAGE_NUM_PUBQ;
540 txQPageNum = TX_TOTAL_PAGE_NUMBER - numPubQ;
541
542 txQPageUnit = txQPageNum/outEPNum;
543 txQRemainPage = txQPageNum % outEPNum;
544 if (queue_sel & TX_SELE_HQ)
545 numHQ = txQPageUnit;
546 if (queue_sel & TX_SELE_LQ)
547 numLQ = txQPageUnit;
548
549
550 if ((outEPNum > 1) && (txQRemainPage))
551 numHQ += txQRemainPage;
552
553 if (isChipN) {
554 if (queue_sel & TX_SELE_NQ)
555 numNQ = txQPageUnit;
556 value8 = (u8)_NPQ(numNQ);
557 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8);
558 }
559 } else {
560
561 numPubQ = isChipN ? WMM_CHIP_B_PAGE_NUM_PUBQ :
562 WMM_CHIP_A_PAGE_NUM_PUBQ;
563 if (queue_sel & TX_SELE_HQ) {
564 numHQ = isChipN ? WMM_CHIP_B_PAGE_NUM_HPQ :
565 WMM_CHIP_A_PAGE_NUM_HPQ;
566 }
567 if (queue_sel & TX_SELE_LQ) {
568 numLQ = isChipN ? WMM_CHIP_B_PAGE_NUM_LPQ :
569 WMM_CHIP_A_PAGE_NUM_LPQ;
570 }
571
572 if (isChipN) {
573 if (queue_sel & TX_SELE_NQ)
574 numNQ = WMM_CHIP_B_PAGE_NUM_NPQ;
575 value8 = (u8)_NPQ(numNQ);
576 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8);
577 }
578 }
579
580 value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
581 rtl_write_dword(rtlpriv, REG_RQPN, value32);
582}
583
584static void _rtl92c_init_trx_buffer(struct ieee80211_hw *hw, bool wmm_enable)
585{
586 struct rtl_priv *rtlpriv = rtl_priv(hw);
587 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
588 u8 txpktbuf_bndy;
589 u8 value8;
590
591 if (!wmm_enable)
592 txpktbuf_bndy = TX_PAGE_BOUNDARY;
593 else
594 txpktbuf_bndy = (IS_NORMAL_CHIP(rtlhal->version))
595 ? WMM_CHIP_B_TX_PAGE_BOUNDARY
596 : WMM_CHIP_A_TX_PAGE_BOUNDARY;
597 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
598 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
599 rtl_write_byte(rtlpriv, REG_TXPKTBUF_WMAC_LBK_BF_HD, txpktbuf_bndy);
600 rtl_write_byte(rtlpriv, REG_TRXFF_BNDY, txpktbuf_bndy);
601 rtl_write_byte(rtlpriv, REG_TDECTRL+1, txpktbuf_bndy);
602 rtl_write_word(rtlpriv, (REG_TRXFF_BNDY + 2), 0x27FF);
603 value8 = _PSRX(RX_PAGE_SIZE_REG_VALUE) | _PSTX(PBP_128);
604 rtl_write_byte(rtlpriv, REG_PBP, value8);
605}
606
607static void _rtl92c_init_chipN_reg_priority(struct ieee80211_hw *hw, u16 beQ,
608 u16 bkQ, u16 viQ, u16 voQ,
609 u16 mgtQ, u16 hiQ)
610{
611 struct rtl_priv *rtlpriv = rtl_priv(hw);
612 u16 value16 = (rtl_read_word(rtlpriv, REG_TRXDMA_CTRL) & 0x7);
613
614 value16 |= _TXDMA_BEQ_MAP(beQ) | _TXDMA_BKQ_MAP(bkQ) |
615 _TXDMA_VIQ_MAP(viQ) | _TXDMA_VOQ_MAP(voQ) |
616 _TXDMA_MGQ_MAP(mgtQ) | _TXDMA_HIQ_MAP(hiQ);
617 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, value16);
618}
619
620static void _rtl92cu_init_chipN_one_out_ep_priority(struct ieee80211_hw *hw,
621 bool wmm_enable,
622 u8 queue_sel)
623{
624 u16 uninitialized_var(value);
625
626 switch (queue_sel) {
627 case TX_SELE_HQ:
628 value = QUEUE_HIGH;
629 break;
630 case TX_SELE_LQ:
631 value = QUEUE_LOW;
632 break;
633 case TX_SELE_NQ:
634 value = QUEUE_NORMAL;
635 break;
636 default:
637 WARN_ON(1);
638 break;
639 }
640 _rtl92c_init_chipN_reg_priority(hw, value, value, value, value,
641 value, value);
642 pr_info("Tx queue select: 0x%02x\n", queue_sel);
643}
644
645static void _rtl92cu_init_chipN_two_out_ep_priority(struct ieee80211_hw *hw,
646 bool wmm_enable,
647 u8 queue_sel)
648{
649 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
650 u16 uninitialized_var(valueHi);
651 u16 uninitialized_var(valueLow);
652
653 switch (queue_sel) {
654 case (TX_SELE_HQ | TX_SELE_LQ):
655 valueHi = QUEUE_HIGH;
656 valueLow = QUEUE_LOW;
657 break;
658 case (TX_SELE_NQ | TX_SELE_LQ):
659 valueHi = QUEUE_NORMAL;
660 valueLow = QUEUE_LOW;
661 break;
662 case (TX_SELE_HQ | TX_SELE_NQ):
663 valueHi = QUEUE_HIGH;
664 valueLow = QUEUE_NORMAL;
665 break;
666 default:
667 WARN_ON(1);
668 break;
669 }
670 if (!wmm_enable) {
671 beQ = valueLow;
672 bkQ = valueLow;
673 viQ = valueHi;
674 voQ = valueHi;
675 mgtQ = valueHi;
676 hiQ = valueHi;
677 } else {
678 beQ = valueHi;
679 bkQ = valueLow;
680 viQ = valueLow;
681 voQ = valueHi;
682 mgtQ = valueHi;
683 hiQ = valueHi;
684 }
685 _rtl92c_init_chipN_reg_priority(hw, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
686 pr_info("Tx queue select: 0x%02x\n", queue_sel);
687}
688
689static void _rtl92cu_init_chipN_three_out_ep_priority(struct ieee80211_hw *hw,
690 bool wmm_enable,
691 u8 queue_sel)
692{
693 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
694 struct rtl_priv *rtlpriv = rtl_priv(hw);
695
696 if (!wmm_enable) {
697 beQ = QUEUE_LOW;
698 bkQ = QUEUE_LOW;
699 viQ = QUEUE_NORMAL;
700 voQ = QUEUE_HIGH;
701 mgtQ = QUEUE_HIGH;
702 hiQ = QUEUE_HIGH;
703 } else {
704 beQ = QUEUE_LOW;
705 bkQ = QUEUE_NORMAL;
706 viQ = QUEUE_NORMAL;
707 voQ = QUEUE_HIGH;
708 mgtQ = QUEUE_HIGH;
709 hiQ = QUEUE_HIGH;
710 }
711 _rtl92c_init_chipN_reg_priority(hw, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
712 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, "Tx queue select :0x%02x..\n",
713 queue_sel);
714}
715
716static void _rtl92cu_init_chipN_queue_priority(struct ieee80211_hw *hw,
717 bool wmm_enable,
718 u8 out_ep_num,
719 u8 queue_sel)
720{
721 switch (out_ep_num) {
722 case 1:
723 _rtl92cu_init_chipN_one_out_ep_priority(hw, wmm_enable,
724 queue_sel);
725 break;
726 case 2:
727 _rtl92cu_init_chipN_two_out_ep_priority(hw, wmm_enable,
728 queue_sel);
729 break;
730 case 3:
731 _rtl92cu_init_chipN_three_out_ep_priority(hw, wmm_enable,
732 queue_sel);
733 break;
734 default:
735 WARN_ON(1);
736 break;
737 }
738}
739
740static void _rtl92cu_init_chipT_queue_priority(struct ieee80211_hw *hw,
741 bool wmm_enable,
742 u8 out_ep_num,
743 u8 queue_sel)
744{
745 u8 hq_sele = 0;
746 struct rtl_priv *rtlpriv = rtl_priv(hw);
747
748 switch (out_ep_num) {
749 case 2:
750 if (!wmm_enable)
751 hq_sele = HQSEL_VOQ | HQSEL_VIQ | HQSEL_MGTQ |
752 HQSEL_HIQ;
753 else
754 hq_sele = HQSEL_VOQ | HQSEL_BEQ | HQSEL_MGTQ |
755 HQSEL_HIQ;
756 break;
757 case 1:
758 if (TX_SELE_LQ == queue_sel) {
759
760 hq_sele = 0;
761 } else if (TX_SELE_HQ == queue_sel) {
762
763 hq_sele = HQSEL_VOQ | HQSEL_VIQ | HQSEL_BEQ |
764 HQSEL_BKQ | HQSEL_MGTQ | HQSEL_HIQ;
765 }
766 break;
767 default:
768 WARN_ON(1);
769 break;
770 }
771 rtl_write_byte(rtlpriv, (REG_TRXDMA_CTRL+1), hq_sele);
772 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, "Tx queue select :0x%02x..\n",
773 hq_sele);
774}
775
776static void _rtl92cu_init_queue_priority(struct ieee80211_hw *hw,
777 bool wmm_enable,
778 u8 out_ep_num,
779 u8 queue_sel)
780{
781 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
782 if (IS_NORMAL_CHIP(rtlhal->version))
783 _rtl92cu_init_chipN_queue_priority(hw, wmm_enable, out_ep_num,
784 queue_sel);
785 else
786 _rtl92cu_init_chipT_queue_priority(hw, wmm_enable, out_ep_num,
787 queue_sel);
788}
789
790static void _rtl92cu_init_usb_aggregation(struct ieee80211_hw *hw)
791{
792}
793
794static void _rtl92cu_init_wmac_setting(struct ieee80211_hw *hw)
795{
796 u16 value16;
797 u32 value32;
798 struct rtl_priv *rtlpriv = rtl_priv(hw);
799
800 value32 = (RCR_APM | RCR_AM | RCR_ADF | RCR_AB | RCR_APPFCS |
801 RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL |
802 RCR_APP_MIC | RCR_APP_PHYSTS | RCR_ACRC32);
803 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(&value32));
804
805 rtl_write_dword(rtlpriv, REG_MAR, 0xFFFFFFFF);
806 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xFFFFFFFF);
807
808 value16 = 0xFFFF;
809 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_MGT_FILTER,
810 (u8 *)(&value16));
811
812 value16 = 0x0;
813 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_CTRL_FILTER,
814 (u8 *)(&value16));
815
816 value16 = 0xFFFF;
817 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_DATA_FILTER,
818 (u8 *)(&value16));
819}
820
821static void _rtl92cu_init_beacon_parameters(struct ieee80211_hw *hw)
822{
823 struct rtl_priv *rtlpriv = rtl_priv(hw);
824 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
825
826 rtl_write_word(rtlpriv, REG_BCN_CTRL, 0x1010);
827
828
829 rtl_write_word(rtlpriv, REG_TBTT_PROHIBIT, 0x6404);
830 rtl_write_byte(rtlpriv, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME);
831 rtl_write_byte(rtlpriv, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME);
832
833
834
835 if (IS_NORMAL_CHIP(rtlhal->version))
836 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660F);
837 else
838 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x66FF);
839}
840
841static int _rtl92cu_init_mac(struct ieee80211_hw *hw)
842{
843 struct rtl_priv *rtlpriv = rtl_priv(hw);
844 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
845 struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw);
846 struct rtl_usb *rtlusb = rtl_usbdev(usb_priv);
847 int err = 0;
848 u32 boundary = 0;
849 u8 wmm_enable = false;
850 u8 out_ep_nums = rtlusb->out_ep_nums;
851 u8 queue_sel = rtlusb->out_queue_sel;
852 err = _rtl92cu_init_power_on(hw);
853
854 if (err) {
855 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
856 "Failed to init power on!\n");
857 return err;
858 }
859 if (!wmm_enable) {
860 boundary = TX_PAGE_BOUNDARY;
861 } else {
862 boundary = (IS_NORMAL_CHIP(rtlhal->version))
863 ? WMM_CHIP_B_TX_PAGE_BOUNDARY
864 : WMM_CHIP_A_TX_PAGE_BOUNDARY;
865 }
866 if (false == rtl92c_init_llt_table(hw, boundary)) {
867 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
868 "Failed to init LLT Table!\n");
869 return -EINVAL;
870 }
871 _rtl92cu_init_queue_reserved_page(hw, wmm_enable, out_ep_nums,
872 queue_sel);
873 _rtl92c_init_trx_buffer(hw, wmm_enable);
874 _rtl92cu_init_queue_priority(hw, wmm_enable, out_ep_nums,
875 queue_sel);
876
877 rtl92c_init_driver_info_size(hw, RTL92C_DRIVER_INFO_SIZE);
878 rtl92c_init_interrupt(hw);
879 rtl92c_init_network_type(hw);
880 _rtl92cu_init_wmac_setting(hw);
881 rtl92c_init_adaptive_ctrl(hw);
882 rtl92c_init_edca(hw);
883 rtl92c_init_rate_fallback(hw);
884 rtl92c_init_retry_function(hw);
885 _rtl92cu_init_usb_aggregation(hw);
886 rtlpriv->cfg->ops->set_bw_mode(hw, NL80211_CHAN_HT20);
887 rtl92c_set_min_space(hw, IS_92C_SERIAL(rtlhal->version));
888 _rtl92cu_init_beacon_parameters(hw);
889 rtl92c_init_ampdu_aggregation(hw);
890 rtl92c_init_beacon_max_error(hw);
891 return err;
892}
893
894void rtl92cu_enable_hw_security_config(struct ieee80211_hw *hw)
895{
896 struct rtl_priv *rtlpriv = rtl_priv(hw);
897 u8 sec_reg_value = 0x0;
898 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
899
900 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
901 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
902 rtlpriv->sec.pairwise_enc_algorithm,
903 rtlpriv->sec.group_enc_algorithm);
904 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
905 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
906 "not open sw encryption\n");
907 return;
908 }
909 sec_reg_value = SCR_TxEncEnable | SCR_RxDecEnable;
910 if (rtlpriv->sec.use_defaultkey) {
911 sec_reg_value |= SCR_TxUseDK;
912 sec_reg_value |= SCR_RxUseDK;
913 }
914 if (IS_NORMAL_CHIP(rtlhal->version))
915 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
916 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
917 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, "The SECR-value %x\n",
918 sec_reg_value);
919 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
920}
921
922static void _rtl92cu_hw_configure(struct ieee80211_hw *hw)
923{
924 struct rtl_priv *rtlpriv = rtl_priv(hw);
925 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
926
927
928 rtl_write_byte(rtlpriv, REG_LDOHCI12_CTRL, 0x0f);
929 rtl_write_byte(rtlpriv, 0x15, 0xe9);
930
931
932 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
933
934 rtl_write_byte(rtlpriv, 0xfe40, 0xe0);
935 rtl_write_byte(rtlpriv, 0xfe41, 0x8d);
936 rtl_write_byte(rtlpriv, 0xfe42, 0x80);
937 rtlusb->reg_bcn_ctrl_val = 0x18;
938 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlusb->reg_bcn_ctrl_val);
939}
940
941static void _InitPABias(struct ieee80211_hw *hw)
942{
943 struct rtl_priv *rtlpriv = rtl_priv(hw);
944 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
945 u8 pa_setting;
946
947
948 pa_setting = efuse_read_1byte(hw, 0x1FA);
949 if (!(pa_setting & BIT(0))) {
950 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x0F406);
951 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x4F406);
952 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x8F406);
953 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0xCF406);
954 }
955 if (!(pa_setting & BIT(1)) && IS_NORMAL_CHIP(rtlhal->version) &&
956 IS_92C_SERIAL(rtlhal->version)) {
957 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x0F406);
958 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x4F406);
959 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x8F406);
960 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0xCF406);
961 }
962 if (!(pa_setting & BIT(4))) {
963 pa_setting = rtl_read_byte(rtlpriv, 0x16);
964 pa_setting &= 0x0F;
965 rtl_write_byte(rtlpriv, 0x16, pa_setting | 0x90);
966 }
967}
968
969int rtl92cu_hw_init(struct ieee80211_hw *hw)
970{
971 struct rtl_priv *rtlpriv = rtl_priv(hw);
972 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
973 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
974 struct rtl_phy *rtlphy = &(rtlpriv->phy);
975 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
976 int err = 0;
977 unsigned long flags;
978
979
980
981
982
983
984
985
986 local_save_flags(flags);
987 local_irq_enable();
988
989 rtlhal->fw_ready = false;
990 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CU;
991 err = _rtl92cu_init_mac(hw);
992 if (err) {
993 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "init mac failed!\n");
994 goto exit;
995 }
996 err = rtl92c_download_fw(hw);
997 if (err) {
998 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
999 "Failed to download FW. Init HW without FW now..\n");
1000 err = 1;
1001 goto exit;
1002 }
1003
1004 rtlhal->fw_ready = true;
1005 rtlhal->last_hmeboxnum = 0;
1006 _rtl92cu_phy_param_tab_init(hw);
1007 rtl92cu_phy_mac_config(hw);
1008 rtl92cu_phy_bb_config(hw);
1009 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
1010 rtl92c_phy_rf_config(hw);
1011 if (IS_VENDOR_UMC_A_CUT(rtlhal->version) &&
1012 !IS_92C_SERIAL(rtlhal->version)) {
1013 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255);
1014 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00);
1015 }
1016 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
1017 RF_CHNLBW, RFREG_OFFSET_MASK);
1018 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
1019 RF_CHNLBW, RFREG_OFFSET_MASK);
1020 rtl92cu_bb_block_on(hw);
1021 rtl_cam_reset_all_entry(hw);
1022 rtl92cu_enable_hw_security_config(hw);
1023 ppsc->rfpwr_state = ERFON;
1024 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1025 if (ppsc->rfpwr_state == ERFON) {
1026 rtl92c_phy_set_rfpath_switch(hw, 1);
1027 if (rtlphy->iqk_initialized) {
1028 rtl92c_phy_iq_calibrate(hw, true);
1029 } else {
1030 rtl92c_phy_iq_calibrate(hw, false);
1031 rtlphy->iqk_initialized = true;
1032 }
1033 rtl92c_dm_check_txpower_tracking(hw);
1034 rtl92c_phy_lc_calibrate(hw);
1035 }
1036 _rtl92cu_hw_configure(hw);
1037 _InitPABias(hw);
1038 rtl92c_dm_init(hw);
1039exit:
1040 local_irq_restore(flags);
1041 return err;
1042}
1043
1044static void _DisableRFAFEAndResetBB(struct ieee80211_hw *hw)
1045{
1046 struct rtl_priv *rtlpriv = rtl_priv(hw);
1047
1048
1049
1050
1051
1052
1053
1054 u8 eRFPath = 0, value8 = 0;
1055 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1056 rtl_set_rfreg(hw, (enum radio_path)eRFPath, 0x0, MASKBYTE0, 0x0);
1057
1058 value8 |= APSDOFF;
1059 rtl_write_byte(rtlpriv, REG_APSD_CTRL, value8);
1060 value8 = 0;
1061 value8 |= (FEN_USBD | FEN_USBA | FEN_BB_GLB_RSTn);
1062 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, value8);
1063 value8 &= (~FEN_BB_GLB_RSTn);
1064 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, value8);
1065}
1066
1067static void _ResetDigitalProcedure1(struct ieee80211_hw *hw, bool bWithoutHWSM)
1068{
1069 struct rtl_priv *rtlpriv = rtl_priv(hw);
1070 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1071
1072 if (rtlhal->fw_version <= 0x20) {
1073
1074
1075
1076
1077
1078
1079 u16 valu16 = 0;
1080
1081 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
1082 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1083 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 &
1084 (~FEN_CPUEN)));
1085 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN)&0x0FFF;
1086 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 |
1087 (FEN_HWPDN|FEN_ELDR)));
1088 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1089 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 |
1090 FEN_CPUEN));
1091 } else {
1092 u8 retry_cnts = 0;
1093
1094
1095 if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(1)) {
1096
1097 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
1098
1099 rtl_write_byte(rtlpriv, REG_HMETFR+3, 0x20);
1100 while ((retry_cnts++ < 100) &&
1101 (FEN_CPUEN & rtl_read_word(rtlpriv,
1102 REG_SYS_FUNC_EN))) {
1103 udelay(50);
1104 }
1105 if (retry_cnts >= 100) {
1106 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1107 "#####=> 8051 reset failed!.........................\n");
1108
1109 rtl_write_byte(rtlpriv,
1110 REG_SYS_FUNC_EN + 1,
1111 0x50);
1112 udelay(100);
1113 }
1114 }
1115
1116 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x54);
1117 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
1118 }
1119 if (bWithoutHWSM) {
1120
1121
1122
1123
1124
1125
1126
1127 rtl_write_word(rtlpriv, REG_SYS_CLKR, 0x70A3);
1128 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80);
1129 rtl_write_word(rtlpriv, REG_AFE_XTAL_CTRL, 0x880F);
1130 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xF9);
1131 }
1132}
1133
1134static void _ResetDigitalProcedure2(struct ieee80211_hw *hw)
1135{
1136 struct rtl_priv *rtlpriv = rtl_priv(hw);
1137
1138
1139
1140
1141
1142 rtl_write_word(rtlpriv, REG_SYS_CLKR, 0x70A3);
1143 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL+1, 0x82);
1144}
1145
1146static void _DisableGPIO(struct ieee80211_hw *hw)
1147{
1148 struct rtl_priv *rtlpriv = rtl_priv(hw);
1149
1150
1151
1152
1153
1154
1155
1156 u8 value8;
1157 u16 value16;
1158 u32 value32;
1159
1160
1161 rtl_write_word(rtlpriv, REG_GPIO_PIN_CTRL+2, 0x0000);
1162 value32 = rtl_read_dword(rtlpriv, REG_GPIO_PIN_CTRL) & 0xFFFF00FF;
1163 value8 = (u8)(value32&0x000000FF);
1164 value32 |= ((value8<<8) | 0x00FF0000);
1165 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, value32);
1166
1167 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG+3, 0x00);
1168 value16 = rtl_read_word(rtlpriv, REG_GPIO_MUXCFG+2) & 0xFF0F;
1169 value8 = (u8)(value16&0x000F);
1170 value16 |= ((value8<<4) | 0x0780);
1171 rtl_write_word(rtlpriv, REG_GPIO_PIN_CTRL+2, value16);
1172
1173 rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080);
1174}
1175
1176static void _DisableAnalog(struct ieee80211_hw *hw, bool bWithoutHWSM)
1177{
1178 struct rtl_priv *rtlpriv = rtl_priv(hw);
1179 u16 value16 = 0;
1180 u8 value8 = 0;
1181
1182 if (bWithoutHWSM) {
1183
1184
1185
1186
1187
1188
1189 rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x04);
1190 value8 = rtl_read_byte(rtlpriv, REG_LDOV12D_CTRL);
1191 value8 &= (~LDV12_EN);
1192 rtl_write_byte(rtlpriv, REG_LDOV12D_CTRL, value8);
1193 }
1194
1195
1196
1197
1198
1199 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23);
1200 value16 |= (APDM_HOST | AFSM_HSUS | PFM_ALDN);
1201 rtl_write_word(rtlpriv, REG_APS_FSMCO, (u16)value16);
1202 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0E);
1203}
1204
1205static void _CardDisableHWSM(struct ieee80211_hw *hw)
1206{
1207
1208 _DisableRFAFEAndResetBB(hw);
1209
1210 _ResetDigitalProcedure1(hw, false);
1211
1212 _DisableGPIO(hw);
1213
1214 _DisableAnalog(hw, false);
1215}
1216
1217static void _CardDisableWithoutHWSM(struct ieee80211_hw *hw)
1218{
1219
1220 _DisableRFAFEAndResetBB(hw);
1221
1222 _ResetDigitalProcedure1(hw, true);
1223
1224 _DisableGPIO(hw);
1225
1226 _ResetDigitalProcedure2(hw);
1227
1228 _DisableAnalog(hw, true);
1229}
1230
1231static void _rtl92cu_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
1232 u8 set_bits, u8 clear_bits)
1233{
1234 struct rtl_priv *rtlpriv = rtl_priv(hw);
1235 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1236
1237 rtlusb->reg_bcn_ctrl_val |= set_bits;
1238 rtlusb->reg_bcn_ctrl_val &= ~clear_bits;
1239 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlusb->reg_bcn_ctrl_val);
1240}
1241
1242static void _rtl92cu_stop_tx_beacon(struct ieee80211_hw *hw)
1243{
1244 struct rtl_priv *rtlpriv = rtl_priv(hw);
1245 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1246 u8 tmp1byte = 0;
1247 if (IS_NORMAL_CHIP(rtlhal->version)) {
1248 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
1249 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
1250 tmp1byte & (~BIT(6)));
1251 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
1252 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
1253 tmp1byte &= ~(BIT(0));
1254 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
1255 } else {
1256 rtl_write_byte(rtlpriv, REG_TXPAUSE,
1257 rtl_read_byte(rtlpriv, REG_TXPAUSE) | BIT(6));
1258 }
1259}
1260
1261static void _rtl92cu_resume_tx_beacon(struct ieee80211_hw *hw)
1262{
1263 struct rtl_priv *rtlpriv = rtl_priv(hw);
1264 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1265 u8 tmp1byte = 0;
1266
1267 if (IS_NORMAL_CHIP(rtlhal->version)) {
1268 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
1269 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
1270 tmp1byte | BIT(6));
1271 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
1272 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
1273 tmp1byte |= BIT(0);
1274 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
1275 } else {
1276 rtl_write_byte(rtlpriv, REG_TXPAUSE,
1277 rtl_read_byte(rtlpriv, REG_TXPAUSE) & (~BIT(6)));
1278 }
1279}
1280
1281static void _rtl92cu_enable_bcn_sub_func(struct ieee80211_hw *hw)
1282{
1283 struct rtl_priv *rtlpriv = rtl_priv(hw);
1284 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1285
1286 if (IS_NORMAL_CHIP(rtlhal->version))
1287 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(1));
1288 else
1289 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4));
1290}
1291
1292static void _rtl92cu_disable_bcn_sub_func(struct ieee80211_hw *hw)
1293{
1294 struct rtl_priv *rtlpriv = rtl_priv(hw);
1295 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1296
1297 if (IS_NORMAL_CHIP(rtlhal->version))
1298 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(1), 0);
1299 else
1300 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);
1301}
1302
1303static int _rtl92cu_set_media_status(struct ieee80211_hw *hw,
1304 enum nl80211_iftype type)
1305{
1306 struct rtl_priv *rtlpriv = rtl_priv(hw);
1307 u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1308 enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1309
1310 bt_msr &= 0xfc;
1311 if (type == NL80211_IFTYPE_UNSPECIFIED || type ==
1312 NL80211_IFTYPE_STATION) {
1313 _rtl92cu_stop_tx_beacon(hw);
1314 _rtl92cu_enable_bcn_sub_func(hw);
1315 } else if (type == NL80211_IFTYPE_ADHOC || type == NL80211_IFTYPE_AP) {
1316 _rtl92cu_resume_tx_beacon(hw);
1317 _rtl92cu_disable_bcn_sub_func(hw);
1318 } else {
1319 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1320 "Set HW_VAR_MEDIA_STATUS:No such media status(%x)\n",
1321 type);
1322 }
1323 switch (type) {
1324 case NL80211_IFTYPE_UNSPECIFIED:
1325 bt_msr |= MSR_NOLINK;
1326 ledaction = LED_CTL_LINK;
1327 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1328 "Set Network type to NO LINK!\n");
1329 break;
1330 case NL80211_IFTYPE_ADHOC:
1331 bt_msr |= MSR_ADHOC;
1332 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1333 "Set Network type to Ad Hoc!\n");
1334 break;
1335 case NL80211_IFTYPE_STATION:
1336 bt_msr |= MSR_INFRA;
1337 ledaction = LED_CTL_LINK;
1338 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1339 "Set Network type to STA!\n");
1340 break;
1341 case NL80211_IFTYPE_AP:
1342 bt_msr |= MSR_AP;
1343 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1344 "Set Network type to AP!\n");
1345 break;
1346 default:
1347 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1348 "Network type %d not supported!\n", type);
1349 goto error_out;
1350 }
1351 rtl_write_byte(rtlpriv, MSR, bt_msr);
1352 rtlpriv->cfg->ops->led_control(hw, ledaction);
1353 if ((bt_msr & MSR_MASK) == MSR_AP)
1354 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1355 else
1356 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1357 return 0;
1358error_out:
1359 return 1;
1360}
1361
1362void rtl92cu_card_disable(struct ieee80211_hw *hw)
1363{
1364 struct rtl_priv *rtlpriv = rtl_priv(hw);
1365 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1366 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1367 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1368 enum nl80211_iftype opmode;
1369
1370 mac->link_state = MAC80211_NOLINK;
1371 opmode = NL80211_IFTYPE_UNSPECIFIED;
1372 _rtl92cu_set_media_status(hw, opmode);
1373 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1374 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1375 if (rtlusb->disableHWSM)
1376 _CardDisableHWSM(hw);
1377 else
1378 _CardDisableWithoutHWSM(hw);
1379
1380
1381 rtlpriv->phy.iqk_initialized = false;
1382}
1383
1384void rtl92cu_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1385{
1386 struct rtl_priv *rtlpriv = rtl_priv(hw);
1387 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1388 u32 reg_rcr;
1389
1390 if (rtlpriv->psc.rfpwr_state != ERFON)
1391 return;
1392
1393 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr));
1394
1395 if (check_bssid) {
1396 u8 tmp;
1397 if (IS_NORMAL_CHIP(rtlhal->version)) {
1398 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1399 tmp = BIT(4);
1400 } else {
1401 reg_rcr |= RCR_CBSSID;
1402 tmp = BIT(4) | BIT(5);
1403 }
1404 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1405 (u8 *) (®_rcr));
1406 _rtl92cu_set_bcn_ctrl_reg(hw, 0, tmp);
1407 } else {
1408 u8 tmp;
1409 if (IS_NORMAL_CHIP(rtlhal->version)) {
1410 reg_rcr &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1411 tmp = BIT(4);
1412 } else {
1413 reg_rcr &= ~RCR_CBSSID;
1414 tmp = BIT(4) | BIT(5);
1415 }
1416 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1417 rtlpriv->cfg->ops->set_hw_reg(hw,
1418 HW_VAR_RCR, (u8 *) (®_rcr));
1419 _rtl92cu_set_bcn_ctrl_reg(hw, tmp, 0);
1420 }
1421}
1422
1423
1424
1425int rtl92cu_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1426{
1427 struct rtl_priv *rtlpriv = rtl_priv(hw);
1428
1429 if (_rtl92cu_set_media_status(hw, type))
1430 return -EOPNOTSUPP;
1431
1432 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1433 if (type != NL80211_IFTYPE_AP)
1434 rtl92cu_set_check_bssid(hw, true);
1435 } else {
1436 rtl92cu_set_check_bssid(hw, false);
1437 }
1438
1439 return 0;
1440}
1441
1442static void _beacon_function_enable(struct ieee80211_hw *hw)
1443{
1444 struct rtl_priv *rtlpriv = rtl_priv(hw);
1445
1446 _rtl92cu_set_bcn_ctrl_reg(hw, (BIT(4) | BIT(3) | BIT(1)), 0x00);
1447 rtl_write_byte(rtlpriv, REG_RD_CTRL+1, 0x6F);
1448}
1449
1450void rtl92cu_set_beacon_related_registers(struct ieee80211_hw *hw)
1451{
1452
1453 struct rtl_priv *rtlpriv = rtl_priv(hw);
1454 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1455 u16 bcn_interval, atim_window;
1456 u32 value32;
1457
1458 bcn_interval = mac->beacon_interval;
1459 atim_window = 2;
1460 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1461 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1462 _rtl92cu_init_beacon_parameters(hw);
1463 rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
1464
1465
1466
1467
1468
1469
1470
1471 value32 = rtl_read_dword(rtlpriv, REG_TCR);
1472 value32 &= ~TSFRST;
1473 rtl_write_dword(rtlpriv, REG_TCR, value32);
1474 value32 |= TSFRST;
1475 rtl_write_dword(rtlpriv, REG_TCR, value32);
1476 RT_TRACE(rtlpriv, COMP_INIT|COMP_BEACON, DBG_LOUD,
1477 "SetBeaconRelatedRegisters8192CUsb(): Set TCR(%x)\n",
1478 value32);
1479
1480
1481 if ((mac->opmode == NL80211_IFTYPE_ADHOC) ||
1482 (mac->opmode == NL80211_IFTYPE_MESH_POINT) ||
1483 (mac->opmode == NL80211_IFTYPE_AP)) {
1484 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x50);
1485 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x50);
1486 }
1487 _beacon_function_enable(hw);
1488}
1489
1490void rtl92cu_set_beacon_interval(struct ieee80211_hw *hw)
1491{
1492 struct rtl_priv *rtlpriv = rtl_priv(hw);
1493 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1494 u16 bcn_interval = mac->beacon_interval;
1495
1496 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG, "beacon_interval:%d\n",
1497 bcn_interval);
1498 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1499}
1500
1501void rtl92cu_update_interrupt_mask(struct ieee80211_hw *hw,
1502 u32 add_msr, u32 rm_msr)
1503{
1504}
1505
1506void rtl92cu_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
1507{
1508 struct rtl_priv *rtlpriv = rtl_priv(hw);
1509 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1510 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1511
1512 switch (variable) {
1513 case HW_VAR_RCR:
1514 *((u32 *)(val)) = mac->rx_conf;
1515 break;
1516 case HW_VAR_RF_STATE:
1517 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
1518 break;
1519 case HW_VAR_FWLPS_RF_ON:{
1520 enum rf_pwrstate rfState;
1521 u32 val_rcr;
1522
1523 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE,
1524 (u8 *)(&rfState));
1525 if (rfState == ERFOFF) {
1526 *((bool *) (val)) = true;
1527 } else {
1528 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
1529 val_rcr &= 0x00070000;
1530 if (val_rcr)
1531 *((bool *) (val)) = false;
1532 else
1533 *((bool *) (val)) = true;
1534 }
1535 break;
1536 }
1537 case HW_VAR_FW_PSMODE_STATUS:
1538 *((bool *) (val)) = ppsc->fw_current_inpsmode;
1539 break;
1540 case HW_VAR_CORRECT_TSF:{
1541 u64 tsf;
1542 u32 *ptsf_low = (u32 *)&tsf;
1543 u32 *ptsf_high = ((u32 *)&tsf) + 1;
1544
1545 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
1546 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
1547 *((u64 *)(val)) = tsf;
1548 break;
1549 }
1550 case HW_VAR_MGT_FILTER:
1551 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP0);
1552 break;
1553 case HW_VAR_CTRL_FILTER:
1554 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP1);
1555 break;
1556 case HW_VAR_DATA_FILTER:
1557 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP2);
1558 break;
1559 case HAL_DEF_WOWLAN:
1560 break;
1561 default:
1562 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1563 "switch case not processed\n");
1564 break;
1565 }
1566}
1567
1568static bool usb_cmd_send_packet(struct ieee80211_hw *hw, struct sk_buff *skb)
1569{
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579 return true;
1580}
1581
1582void rtl92cu_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
1583{
1584 struct rtl_priv *rtlpriv = rtl_priv(hw);
1585 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1586 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1587 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1588 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1589 enum wireless_mode wirelessmode = mac->mode;
1590 u8 idx = 0;
1591
1592 switch (variable) {
1593 case HW_VAR_ETHER_ADDR:{
1594 for (idx = 0; idx < ETH_ALEN; idx++) {
1595 rtl_write_byte(rtlpriv, (REG_MACID + idx),
1596 val[idx]);
1597 }
1598 break;
1599 }
1600 case HW_VAR_BASIC_RATE:{
1601 u16 rate_cfg = ((u16 *) val)[0];
1602 u8 rate_index = 0;
1603
1604 rate_cfg &= 0x15f;
1605
1606
1607
1608
1609
1610 rate_cfg |= 0x01;
1611 rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff);
1612 rtl_write_byte(rtlpriv, REG_RRSR + 1,
1613 (rate_cfg >> 8) & 0xff);
1614 while (rate_cfg > 0x1) {
1615 rate_cfg >>= 1;
1616 rate_index++;
1617 }
1618 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
1619 rate_index);
1620 break;
1621 }
1622 case HW_VAR_BSSID:{
1623 for (idx = 0; idx < ETH_ALEN; idx++) {
1624 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
1625 val[idx]);
1626 }
1627 break;
1628 }
1629 case HW_VAR_SIFS:{
1630 rtl_write_byte(rtlpriv, REG_SIFS_CCK + 1, val[0]);
1631 rtl_write_byte(rtlpriv, REG_SIFS_OFDM + 1, val[1]);
1632 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
1633 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
1634 rtl_write_byte(rtlpriv, REG_R2T_SIFS+1, val[0]);
1635 rtl_write_byte(rtlpriv, REG_T2T_SIFS+1, val[0]);
1636 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, "HW_VAR_SIFS\n");
1637 break;
1638 }
1639 case HW_VAR_SLOT_TIME:{
1640 u8 e_aci;
1641 u8 QOS_MODE = 1;
1642
1643 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
1644 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1645 "HW_VAR_SLOT_TIME %x\n", val[0]);
1646 if (QOS_MODE) {
1647 for (e_aci = 0; e_aci < AC_MAX; e_aci++)
1648 rtlpriv->cfg->ops->set_hw_reg(hw,
1649 HW_VAR_AC_PARAM,
1650 &e_aci);
1651 } else {
1652 u8 sifstime = 0;
1653 u8 u1bAIFS;
1654
1655 if (IS_WIRELESS_MODE_A(wirelessmode) ||
1656 IS_WIRELESS_MODE_N_24G(wirelessmode) ||
1657 IS_WIRELESS_MODE_N_5G(wirelessmode))
1658 sifstime = 16;
1659 else
1660 sifstime = 10;
1661 u1bAIFS = sifstime + (2 * val[0]);
1662 rtl_write_byte(rtlpriv, REG_EDCA_VO_PARAM,
1663 u1bAIFS);
1664 rtl_write_byte(rtlpriv, REG_EDCA_VI_PARAM,
1665 u1bAIFS);
1666 rtl_write_byte(rtlpriv, REG_EDCA_BE_PARAM,
1667 u1bAIFS);
1668 rtl_write_byte(rtlpriv, REG_EDCA_BK_PARAM,
1669 u1bAIFS);
1670 }
1671 break;
1672 }
1673 case HW_VAR_ACK_PREAMBLE:{
1674 u8 reg_tmp;
1675 u8 short_preamble = (bool)*val;
1676 reg_tmp = 0;
1677 if (short_preamble)
1678 reg_tmp |= 0x80;
1679 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
1680 break;
1681 }
1682 case HW_VAR_AMPDU_MIN_SPACE:{
1683 u8 min_spacing_to_set;
1684 u8 sec_min_space;
1685
1686 min_spacing_to_set = *val;
1687 if (min_spacing_to_set <= 7) {
1688 switch (rtlpriv->sec.pairwise_enc_algorithm) {
1689 case NO_ENCRYPTION:
1690 case AESCCMP_ENCRYPTION:
1691 sec_min_space = 0;
1692 break;
1693 case WEP40_ENCRYPTION:
1694 case WEP104_ENCRYPTION:
1695 case TKIP_ENCRYPTION:
1696 sec_min_space = 6;
1697 break;
1698 default:
1699 sec_min_space = 7;
1700 break;
1701 }
1702 if (min_spacing_to_set < sec_min_space)
1703 min_spacing_to_set = sec_min_space;
1704 mac->min_space_cfg = ((mac->min_space_cfg &
1705 0xf8) |
1706 min_spacing_to_set);
1707 *val = min_spacing_to_set;
1708 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1709 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
1710 mac->min_space_cfg);
1711 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
1712 mac->min_space_cfg);
1713 }
1714 break;
1715 }
1716 case HW_VAR_SHORTGI_DENSITY:{
1717 u8 density_to_set;
1718
1719 density_to_set = *val;
1720 density_to_set &= 0x1f;
1721 mac->min_space_cfg &= 0x07;
1722 mac->min_space_cfg |= (density_to_set << 3);
1723 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1724 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
1725 mac->min_space_cfg);
1726 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
1727 mac->min_space_cfg);
1728 break;
1729 }
1730 case HW_VAR_AMPDU_FACTOR:{
1731 u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9};
1732 u8 factor_toset;
1733 u8 *p_regtoset = NULL;
1734 u8 index = 0;
1735
1736 p_regtoset = regtoset_normal;
1737 factor_toset = *val;
1738 if (factor_toset <= 3) {
1739 factor_toset = (1 << (factor_toset + 2));
1740 if (factor_toset > 0xf)
1741 factor_toset = 0xf;
1742 for (index = 0; index < 4; index++) {
1743 if ((p_regtoset[index] & 0xf0) >
1744 (factor_toset << 4))
1745 p_regtoset[index] =
1746 (p_regtoset[index] & 0x0f)
1747 | (factor_toset << 4);
1748 if ((p_regtoset[index] & 0x0f) >
1749 factor_toset)
1750 p_regtoset[index] =
1751 (p_regtoset[index] & 0xf0)
1752 | (factor_toset);
1753 rtl_write_byte(rtlpriv,
1754 (REG_AGGLEN_LMT + index),
1755 p_regtoset[index]);
1756 }
1757 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1758 "Set HW_VAR_AMPDU_FACTOR: %#x\n",
1759 factor_toset);
1760 }
1761 break;
1762 }
1763 case HW_VAR_AC_PARAM:{
1764 u8 e_aci = *val;
1765 u32 u4b_ac_param;
1766 u16 cw_min = le16_to_cpu(mac->ac[e_aci].cw_min);
1767 u16 cw_max = le16_to_cpu(mac->ac[e_aci].cw_max);
1768 u16 tx_op = le16_to_cpu(mac->ac[e_aci].tx_op);
1769
1770 u4b_ac_param = (u32) mac->ac[e_aci].aifs;
1771 u4b_ac_param |= (u32) ((cw_min & 0xF) <<
1772 AC_PARAM_ECW_MIN_OFFSET);
1773 u4b_ac_param |= (u32) ((cw_max & 0xF) <<
1774 AC_PARAM_ECW_MAX_OFFSET);
1775 u4b_ac_param |= (u32) tx_op << AC_PARAM_TXOP_OFFSET;
1776 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1777 "queue:%x, ac_param:%x\n",
1778 e_aci, u4b_ac_param);
1779 switch (e_aci) {
1780 case AC1_BK:
1781 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM,
1782 u4b_ac_param);
1783 break;
1784 case AC0_BE:
1785 rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM,
1786 u4b_ac_param);
1787 break;
1788 case AC2_VI:
1789 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM,
1790 u4b_ac_param);
1791 break;
1792 case AC3_VO:
1793 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM,
1794 u4b_ac_param);
1795 break;
1796 default:
1797 RT_ASSERT(false, "invalid aci: %d !\n",
1798 e_aci);
1799 break;
1800 }
1801 break;
1802 }
1803 case HW_VAR_RCR:{
1804 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);
1805 mac->rx_conf = ((u32 *) (val))[0];
1806 RT_TRACE(rtlpriv, COMP_RECV, DBG_DMESG,
1807 "### Set RCR(0x%08x) ###\n", mac->rx_conf);
1808 break;
1809 }
1810 case HW_VAR_RETRY_LIMIT:{
1811 u8 retry_limit = val[0];
1812
1813 rtl_write_word(rtlpriv, REG_RL,
1814 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
1815 retry_limit << RETRY_LIMIT_LONG_SHIFT);
1816 RT_TRACE(rtlpriv, COMP_MLME, DBG_DMESG,
1817 "Set HW_VAR_RETRY_LIMIT(0x%08x)\n",
1818 retry_limit);
1819 break;
1820 }
1821 case HW_VAR_DUAL_TSF_RST:
1822 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
1823 break;
1824 case HW_VAR_EFUSE_BYTES:
1825 rtlefuse->efuse_usedbytes = *((u16 *) val);
1826 break;
1827 case HW_VAR_EFUSE_USAGE:
1828 rtlefuse->efuse_usedpercentage = *val;
1829 break;
1830 case HW_VAR_IO_CMD:
1831 rtl92c_phy_set_io_cmd(hw, (*(enum io_type *)val));
1832 break;
1833 case HW_VAR_WPA_CONFIG:
1834 rtl_write_byte(rtlpriv, REG_SECCFG, *val);
1835 break;
1836 case HW_VAR_SET_RPWM:{
1837 u8 rpwm_val = rtl_read_byte(rtlpriv, REG_USB_HRPWM);
1838
1839 if (rpwm_val & BIT(7))
1840 rtl_write_byte(rtlpriv, REG_USB_HRPWM, *val);
1841 else
1842 rtl_write_byte(rtlpriv, REG_USB_HRPWM,
1843 *val | BIT(7));
1844 break;
1845 }
1846 case HW_VAR_H2C_FW_PWRMODE:{
1847 u8 psmode = *val;
1848
1849 if ((psmode != FW_PS_ACTIVE_MODE) &&
1850 (!IS_92C_SERIAL(rtlhal->version)))
1851 rtl92c_dm_rf_saving(hw, true);
1852 rtl92c_set_fw_pwrmode_cmd(hw, (*val));
1853 break;
1854 }
1855 case HW_VAR_FW_PSMODE_STATUS:
1856 ppsc->fw_current_inpsmode = *((bool *) val);
1857 break;
1858 case HW_VAR_H2C_FW_JOINBSSRPT:{
1859 u8 mstatus = *val;
1860 u8 tmp_reg422;
1861 bool recover = false;
1862
1863 if (mstatus == RT_MEDIA_CONNECT) {
1864 rtlpriv->cfg->ops->set_hw_reg(hw,
1865 HW_VAR_AID, NULL);
1866 rtl_write_byte(rtlpriv, REG_CR + 1, 0x03);
1867 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(3));
1868 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);
1869 tmp_reg422 = rtl_read_byte(rtlpriv,
1870 REG_FWHW_TXQ_CTRL + 2);
1871 if (tmp_reg422 & BIT(6))
1872 recover = true;
1873 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
1874 tmp_reg422 & (~BIT(6)));
1875 rtl92c_set_fw_rsvdpagepkt(hw,
1876 &usb_cmd_send_packet);
1877 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(3), 0);
1878 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4));
1879 if (recover)
1880 rtl_write_byte(rtlpriv,
1881 REG_FWHW_TXQ_CTRL + 2,
1882 tmp_reg422 | BIT(6));
1883 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
1884 }
1885 rtl92c_set_fw_joinbss_report_cmd(hw, (*val));
1886 break;
1887 }
1888 case HW_VAR_AID:{
1889 u16 u2btmp;
1890
1891 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
1892 u2btmp &= 0xC000;
1893 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT,
1894 (u2btmp | mac->assoc_id));
1895 break;
1896 }
1897 case HW_VAR_CORRECT_TSF:{
1898 u8 btype_ibss = val[0];
1899
1900 if (btype_ibss)
1901 _rtl92cu_stop_tx_beacon(hw);
1902 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(3));
1903 rtl_write_dword(rtlpriv, REG_TSFTR, (u32)(mac->tsf &
1904 0xffffffff));
1905 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
1906 (u32)((mac->tsf >> 32) & 0xffffffff));
1907 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(3), 0);
1908 if (btype_ibss)
1909 _rtl92cu_resume_tx_beacon(hw);
1910 break;
1911 }
1912 case HW_VAR_MGT_FILTER:
1913 rtl_write_word(rtlpriv, REG_RXFLTMAP0, *(u16 *)val);
1914 mac->rx_mgt_filter = *(u16 *)val;
1915 break;
1916 case HW_VAR_CTRL_FILTER:
1917 rtl_write_word(rtlpriv, REG_RXFLTMAP1, *(u16 *)val);
1918 mac->rx_ctrl_filter = *(u16 *)val;
1919 break;
1920 case HW_VAR_DATA_FILTER:
1921 rtl_write_word(rtlpriv, REG_RXFLTMAP2, *(u16 *)val);
1922 mac->rx_data_filter = *(u16 *)val;
1923 break;
1924 case HW_VAR_KEEP_ALIVE:{
1925 u8 array[2];
1926 array[0] = 0xff;
1927 array[1] = *((u8 *)val);
1928 rtl92c_fill_h2c_cmd(hw, H2C_92C_KEEP_ALIVE_CTRL, 2,
1929 array);
1930 break;
1931 }
1932 default:
1933 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1934 "switch case not processed\n");
1935 break;
1936 }
1937}
1938
1939static void rtl92cu_update_hal_rate_table(struct ieee80211_hw *hw,
1940 struct ieee80211_sta *sta)
1941{
1942 struct rtl_priv *rtlpriv = rtl_priv(hw);
1943 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1944 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1945 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1946 u32 ratr_value;
1947 u8 ratr_index = 0;
1948 u8 nmode = mac->ht_enable;
1949 u8 mimo_ps = IEEE80211_SMPS_OFF;
1950 u16 shortgi_rate;
1951 u32 tmp_ratr_value;
1952 u8 curtxbw_40mhz = mac->bw_40;
1953 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1954 1 : 0;
1955 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1956 1 : 0;
1957 enum wireless_mode wirelessmode = mac->mode;
1958
1959 if (rtlhal->current_bandtype == BAND_ON_5G)
1960 ratr_value = sta->supp_rates[1] << 4;
1961 else
1962 ratr_value = sta->supp_rates[0];
1963 if (mac->opmode == NL80211_IFTYPE_ADHOC)
1964 ratr_value = 0xfff;
1965
1966 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1967 sta->ht_cap.mcs.rx_mask[0] << 12);
1968 switch (wirelessmode) {
1969 case WIRELESS_MODE_B:
1970 if (ratr_value & 0x0000000c)
1971 ratr_value &= 0x0000000d;
1972 else
1973 ratr_value &= 0x0000000f;
1974 break;
1975 case WIRELESS_MODE_G:
1976 ratr_value &= 0x00000FF5;
1977 break;
1978 case WIRELESS_MODE_N_24G:
1979 case WIRELESS_MODE_N_5G:
1980 nmode = 1;
1981 if (mimo_ps == IEEE80211_SMPS_STATIC) {
1982 ratr_value &= 0x0007F005;
1983 } else {
1984 u32 ratr_mask;
1985
1986 if (get_rf_type(rtlphy) == RF_1T2R ||
1987 get_rf_type(rtlphy) == RF_1T1R)
1988 ratr_mask = 0x000ff005;
1989 else
1990 ratr_mask = 0x0f0ff005;
1991
1992 ratr_value &= ratr_mask;
1993 }
1994 break;
1995 default:
1996 if (rtlphy->rf_type == RF_1T2R)
1997 ratr_value &= 0x000ff0ff;
1998 else
1999 ratr_value &= 0x0f0ff0ff;
2000
2001 break;
2002 }
2003
2004 ratr_value &= 0x0FFFFFFF;
2005
2006 if (nmode && ((curtxbw_40mhz &&
2007 curshortgi_40mhz) || (!curtxbw_40mhz &&
2008 curshortgi_20mhz))) {
2009
2010 ratr_value |= 0x10000000;
2011 tmp_ratr_value = (ratr_value >> 12);
2012
2013 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2014 if ((1 << shortgi_rate) & tmp_ratr_value)
2015 break;
2016 }
2017
2018 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2019 (shortgi_rate << 4) | (shortgi_rate);
2020 }
2021
2022 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
2023
2024 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n",
2025 rtl_read_dword(rtlpriv, REG_ARFR0));
2026}
2027
2028static void rtl92cu_update_hal_rate_mask(struct ieee80211_hw *hw,
2029 struct ieee80211_sta *sta,
2030 u8 rssi_level)
2031{
2032 struct rtl_priv *rtlpriv = rtl_priv(hw);
2033 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2034 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2035 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2036 struct rtl_sta_info *sta_entry = NULL;
2037 u32 ratr_bitmap;
2038 u8 ratr_index;
2039 u8 curtxbw_40mhz = (sta->bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0;
2040 u8 curshortgi_40mhz = curtxbw_40mhz &&
2041 (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2042 1 : 0;
2043 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2044 1 : 0;
2045 enum wireless_mode wirelessmode = 0;
2046 bool shortgi = false;
2047 u8 rate_mask[5];
2048 u8 macid = 0;
2049 u8 mimo_ps = IEEE80211_SMPS_OFF;
2050
2051 sta_entry = (struct rtl_sta_info *) sta->drv_priv;
2052 wirelessmode = sta_entry->wireless_mode;
2053 if (mac->opmode == NL80211_IFTYPE_STATION ||
2054 mac->opmode == NL80211_IFTYPE_MESH_POINT)
2055 curtxbw_40mhz = mac->bw_40;
2056 else if (mac->opmode == NL80211_IFTYPE_AP ||
2057 mac->opmode == NL80211_IFTYPE_ADHOC)
2058 macid = sta->aid + 1;
2059
2060 if (rtlhal->current_bandtype == BAND_ON_5G)
2061 ratr_bitmap = sta->supp_rates[1] << 4;
2062 else
2063 ratr_bitmap = sta->supp_rates[0];
2064 if (mac->opmode == NL80211_IFTYPE_ADHOC)
2065 ratr_bitmap = 0xfff;
2066 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2067 sta->ht_cap.mcs.rx_mask[0] << 12);
2068 switch (wirelessmode) {
2069 case WIRELESS_MODE_B:
2070 ratr_index = RATR_INX_WIRELESS_B;
2071 if (ratr_bitmap & 0x0000000c)
2072 ratr_bitmap &= 0x0000000d;
2073 else
2074 ratr_bitmap &= 0x0000000f;
2075 break;
2076 case WIRELESS_MODE_G:
2077 ratr_index = RATR_INX_WIRELESS_GB;
2078
2079 if (rssi_level == 1)
2080 ratr_bitmap &= 0x00000f00;
2081 else if (rssi_level == 2)
2082 ratr_bitmap &= 0x00000ff0;
2083 else
2084 ratr_bitmap &= 0x00000ff5;
2085 break;
2086 case WIRELESS_MODE_A:
2087 ratr_index = RATR_INX_WIRELESS_A;
2088 ratr_bitmap &= 0x00000ff0;
2089 break;
2090 case WIRELESS_MODE_N_24G:
2091 case WIRELESS_MODE_N_5G:
2092 ratr_index = RATR_INX_WIRELESS_NGB;
2093
2094 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2095 if (rssi_level == 1)
2096 ratr_bitmap &= 0x00070000;
2097 else if (rssi_level == 2)
2098 ratr_bitmap &= 0x0007f000;
2099 else
2100 ratr_bitmap &= 0x0007f005;
2101 } else {
2102 if (rtlphy->rf_type == RF_1T2R ||
2103 rtlphy->rf_type == RF_1T1R) {
2104 if (curtxbw_40mhz) {
2105 if (rssi_level == 1)
2106 ratr_bitmap &= 0x000f0000;
2107 else if (rssi_level == 2)
2108 ratr_bitmap &= 0x000ff000;
2109 else
2110 ratr_bitmap &= 0x000ff015;
2111 } else {
2112 if (rssi_level == 1)
2113 ratr_bitmap &= 0x000f0000;
2114 else if (rssi_level == 2)
2115 ratr_bitmap &= 0x000ff000;
2116 else
2117 ratr_bitmap &= 0x000ff005;
2118 }
2119 } else {
2120 if (curtxbw_40mhz) {
2121 if (rssi_level == 1)
2122 ratr_bitmap &= 0x0f0f0000;
2123 else if (rssi_level == 2)
2124 ratr_bitmap &= 0x0f0ff000;
2125 else
2126 ratr_bitmap &= 0x0f0ff015;
2127 } else {
2128 if (rssi_level == 1)
2129 ratr_bitmap &= 0x0f0f0000;
2130 else if (rssi_level == 2)
2131 ratr_bitmap &= 0x0f0ff000;
2132 else
2133 ratr_bitmap &= 0x0f0ff005;
2134 }
2135 }
2136 }
2137
2138 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2139 (!curtxbw_40mhz && curshortgi_20mhz)) {
2140
2141 if (macid == 0)
2142 shortgi = true;
2143 else if (macid == 1)
2144 shortgi = false;
2145 }
2146 break;
2147 default:
2148 ratr_index = RATR_INX_WIRELESS_NGB;
2149
2150 if (rtlphy->rf_type == RF_1T2R)
2151 ratr_bitmap &= 0x000ff0ff;
2152 else
2153 ratr_bitmap &= 0x0f0ff0ff;
2154 break;
2155 }
2156 sta_entry->ratr_index = ratr_index;
2157
2158 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2159 "ratr_bitmap :%x\n", ratr_bitmap);
2160 *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
2161 (ratr_index << 28);
2162 rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
2163 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2164 "Rate_index:%x, ratr_val:%x, %5phC\n",
2165 ratr_index, ratr_bitmap, rate_mask);
2166 memcpy(rtlpriv->rate_mask, rate_mask, 5);
2167
2168
2169 schedule_work(&rtlpriv->works.fill_h2c_cmd);
2170
2171 if (macid != 0)
2172 sta_entry->ratr_index = ratr_index;
2173}
2174
2175void rtl92cu_update_hal_rate_tbl(struct ieee80211_hw *hw,
2176 struct ieee80211_sta *sta,
2177 u8 rssi_level)
2178{
2179 struct rtl_priv *rtlpriv = rtl_priv(hw);
2180
2181 if (rtlpriv->dm.useramask)
2182 rtl92cu_update_hal_rate_mask(hw, sta, rssi_level);
2183 else
2184 rtl92cu_update_hal_rate_table(hw, sta);
2185}
2186
2187void rtl92cu_update_channel_access_setting(struct ieee80211_hw *hw)
2188{
2189 struct rtl_priv *rtlpriv = rtl_priv(hw);
2190 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2191 u16 sifs_timer;
2192
2193 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2194 &mac->slot_time);
2195 if (!mac->ht_enable)
2196 sifs_timer = 0x0a0a;
2197 else
2198 sifs_timer = 0x0e0e;
2199 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2200}
2201
2202bool rtl92cu_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 * valid)
2203{
2204 struct rtl_priv *rtlpriv = rtl_priv(hw);
2205 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2206 enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate;
2207 u8 u1tmp = 0;
2208 bool actuallyset = false;
2209 unsigned long flag = 0;
2210
2211 u8 usb_autosuspend = 0;
2212
2213 if (ppsc->swrf_processing)
2214 return false;
2215 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2216 if (ppsc->rfchange_inprogress) {
2217 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2218 return false;
2219 } else {
2220 ppsc->rfchange_inprogress = true;
2221 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2222 }
2223 cur_rfstate = ppsc->rfpwr_state;
2224 if (usb_autosuspend) {
2225
2226 } else {
2227 if (ppsc->pwrdown_mode) {
2228 u1tmp = rtl_read_byte(rtlpriv, REG_HSISR);
2229 e_rfpowerstate_toset = (u1tmp & BIT(7)) ?
2230 ERFOFF : ERFON;
2231 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
2232 "pwrdown, 0x5c(BIT7)=%02x\n", u1tmp);
2233 } else {
2234 rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG,
2235 rtl_read_byte(rtlpriv,
2236 REG_MAC_PINMUX_CFG) & ~(BIT(3)));
2237 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
2238 e_rfpowerstate_toset = (u1tmp & BIT(3)) ?
2239 ERFON : ERFOFF;
2240 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
2241 "GPIO_IN=%02x\n", u1tmp);
2242 }
2243 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "N-SS RF =%x\n",
2244 e_rfpowerstate_toset);
2245 }
2246 if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
2247 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
2248 "GPIOChangeRF - HW Radio ON, RF ON\n");
2249 ppsc->hwradiooff = false;
2250 actuallyset = true;
2251 } else if ((!ppsc->hwradiooff) && (e_rfpowerstate_toset ==
2252 ERFOFF)) {
2253 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
2254 "GPIOChangeRF - HW Radio OFF\n");
2255 ppsc->hwradiooff = true;
2256 actuallyset = true;
2257 } else {
2258 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
2259 "pHalData->bHwRadioOff and eRfPowerStateToSet do not match: pHalData->bHwRadioOff %x, eRfPowerStateToSet %x\n",
2260 ppsc->hwradiooff, e_rfpowerstate_toset);
2261 }
2262 if (actuallyset) {
2263 ppsc->hwradiooff = true;
2264 if (e_rfpowerstate_toset == ERFON) {
2265 if ((ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM) &&
2266 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM))
2267 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2268 else if ((ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3)
2269 && RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3))
2270 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);
2271 }
2272 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2273 ppsc->rfchange_inprogress = false;
2274 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2275
2276
2277
2278
2279 if (ppsc->pwrdown_mode && e_rfpowerstate_toset == ERFOFF) {
2280
2281 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0);
2282 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x8812);
2283 }
2284 if (e_rfpowerstate_toset == ERFOFF) {
2285 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM)
2286 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2287 else if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3)
2288 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);
2289 }
2290 } else if (e_rfpowerstate_toset == ERFOFF || cur_rfstate == ERFOFF) {
2291
2292 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM)
2293 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2294 else if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3)
2295 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);
2296 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2297 ppsc->rfchange_inprogress = false;
2298 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2299 } else {
2300 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2301 ppsc->rfchange_inprogress = false;
2302 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2303 }
2304 *valid = 1;
2305 return !ppsc->hwradiooff;
2306}
2307
