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26#include "../wifi.h"
27#include "../base.h"
28#include "../pci.h"
29#include "../core.h"
30#include "reg.h"
31#include "def.h"
32#include "phy.h"
33#include "dm.h"
34#include "fw.h"
35#include "trx.h"
36
37static const u32 ofdmswing_table[OFDM_TABLE_SIZE] = {
38 0x7f8001fe,
39 0x788001e2,
40 0x71c001c7,
41 0x6b8001ae,
42 0x65400195,
43 0x5fc0017f,
44 0x5a400169,
45 0x55400155,
46 0x50800142,
47 0x4c000130,
48 0x47c0011f,
49 0x43c0010f,
50 0x40000100,
51 0x3c8000f2,
52 0x390000e4,
53 0x35c000d7,
54 0x32c000cb,
55 0x300000c0,
56 0x2d4000b5,
57 0x2ac000ab,
58 0x288000a2,
59 0x26000098,
60 0x24000090,
61 0x22000088,
62 0x20000080,
63 0x1e400079,
64 0x1c800072,
65 0x1b00006c,
66 0x19800066,
67 0x18000060,
68 0x16c0005b,
69 0x15800056,
70 0x14400051,
71 0x1300004c,
72 0x12000048,
73 0x11000044,
74 0x10000040,
75 0x0f00003c,
76 0x0e400039,
77 0x0d800036,
78 0x0cc00033,
79 0x0c000030,
80 0x0b40002d,
81};
82
83static const u8 cckswing_table_ch1ch13[CCK_TABLE_SIZE][8] = {
84 {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04},
85 {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},
86 {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},
87 {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03},
88 {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},
89 {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03},
90 {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},
91 {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03},
92 {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},
93 {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02},
94 {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},
95 {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02},
96 {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02},
97 {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02},
98 {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},
99 {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02},
100 {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},
101 {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02},
102 {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},
103 {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},
104 {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},
105 {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01},
106 {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01},
107 {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01},
108 {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01},
109 {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01},
110 {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01},
111 {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01},
112 {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},
113 {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},
114 {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01},
115 {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},
116 {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}
117};
118
119static const u8 cckswing_table_ch14[CCK_TABLE_SIZE][8] = {
120 {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00},
121 {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},
122 {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},
123 {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00},
124 {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},
125 {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00},
126 {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},
127 {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00},
128 {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},
129 {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00},
130 {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},
131 {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},
132 {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00},
133 {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00},
134 {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},
135 {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00},
136 {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},
137 {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00},
138 {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},
139 {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},
140 {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},
141 {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00},
142 {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00},
143 {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},
144 {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},
145 {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00},
146 {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},
147 {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},
148 {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},
149 {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},
150 {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},
151 {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},
152 {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}
153};
154
155static void rtl92ee_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw)
156{
157 u32 ret_value;
158 struct rtl_priv *rtlpriv = rtl_priv(hw);
159 struct false_alarm_statistics *falsealm_cnt = &rtlpriv->falsealm_cnt;
160
161 rtl_set_bbreg(hw, DM_REG_OFDM_FA_HOLDC_11N, BIT(31), 1);
162 rtl_set_bbreg(hw, DM_REG_OFDM_FA_RSTD_11N, BIT(31), 1);
163
164 ret_value = rtl_get_bbreg(hw, DM_REG_OFDM_FA_TYPE1_11N, MASKDWORD);
165 falsealm_cnt->cnt_fast_fsync_fail = (ret_value & 0xffff);
166 falsealm_cnt->cnt_sb_search_fail = ((ret_value & 0xffff0000) >> 16);
167
168 ret_value = rtl_get_bbreg(hw, DM_REG_OFDM_FA_TYPE2_11N, MASKDWORD);
169 falsealm_cnt->cnt_ofdm_cca = (ret_value & 0xffff);
170 falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16);
171
172 ret_value = rtl_get_bbreg(hw, DM_REG_OFDM_FA_TYPE3_11N, MASKDWORD);
173 falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff);
174 falsealm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16);
175
176 ret_value = rtl_get_bbreg(hw, DM_REG_OFDM_FA_TYPE4_11N, MASKDWORD);
177 falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff);
178
179 falsealm_cnt->cnt_ofdm_fail = falsealm_cnt->cnt_parity_fail +
180 falsealm_cnt->cnt_rate_illegal +
181 falsealm_cnt->cnt_crc8_fail +
182 falsealm_cnt->cnt_mcs_fail +
183 falsealm_cnt->cnt_fast_fsync_fail +
184 falsealm_cnt->cnt_sb_search_fail;
185
186 ret_value = rtl_get_bbreg(hw, DM_REG_SC_CNT_11N, MASKDWORD);
187 falsealm_cnt->cnt_bw_lsc = (ret_value & 0xffff);
188 falsealm_cnt->cnt_bw_usc = ((ret_value & 0xffff0000) >> 16);
189
190 rtl_set_bbreg(hw, DM_REG_CCK_FA_RST_11N, BIT(12), 1);
191 rtl_set_bbreg(hw, DM_REG_CCK_FA_RST_11N, BIT(14), 1);
192
193 ret_value = rtl_get_bbreg(hw, DM_REG_CCK_FA_LSB_11N, MASKBYTE0);
194 falsealm_cnt->cnt_cck_fail = ret_value;
195
196 ret_value = rtl_get_bbreg(hw, DM_REG_CCK_FA_MSB_11N, MASKBYTE3);
197 falsealm_cnt->cnt_cck_fail += (ret_value & 0xff) << 8;
198
199 ret_value = rtl_get_bbreg(hw, DM_REG_CCK_CCA_CNT_11N, MASKDWORD);
200 falsealm_cnt->cnt_cck_cca = ((ret_value & 0xff) << 8) |
201 ((ret_value & 0xFF00) >> 8);
202
203 falsealm_cnt->cnt_all = falsealm_cnt->cnt_fast_fsync_fail +
204 falsealm_cnt->cnt_sb_search_fail +
205 falsealm_cnt->cnt_parity_fail +
206 falsealm_cnt->cnt_rate_illegal +
207 falsealm_cnt->cnt_crc8_fail +
208 falsealm_cnt->cnt_mcs_fail +
209 falsealm_cnt->cnt_cck_fail;
210
211 falsealm_cnt->cnt_cca_all = falsealm_cnt->cnt_ofdm_cca +
212 falsealm_cnt->cnt_cck_cca;
213
214
215 rtl_set_bbreg(hw, DM_REG_OFDM_FA_RSTC_11N, BIT(31), 1);
216 rtl_set_bbreg(hw, DM_REG_OFDM_FA_RSTC_11N, BIT(31), 0);
217 rtl_set_bbreg(hw, DM_REG_OFDM_FA_RSTD_11N, BIT(27), 1);
218 rtl_set_bbreg(hw, DM_REG_OFDM_FA_RSTD_11N, BIT(27), 0);
219
220 rtl_set_bbreg(hw, DM_REG_OFDM_FA_HOLDC_11N, BIT(31), 0);
221 rtl_set_bbreg(hw, DM_REG_OFDM_FA_RSTD_11N, BIT(31), 0);
222
223 rtl_set_bbreg(hw, DM_REG_CCK_FA_RST_11N, BIT(13) | BIT(12), 0);
224 rtl_set_bbreg(hw, DM_REG_CCK_FA_RST_11N, BIT(13) | BIT(12), 2);
225
226 rtl_set_bbreg(hw, DM_REG_CCK_FA_RST_11N, BIT(15) | BIT(14), 0);
227 rtl_set_bbreg(hw, DM_REG_CCK_FA_RST_11N, BIT(15) | BIT(14), 2);
228
229 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
230 "cnt_parity_fail = %d, cnt_rate_illegal = %d, cnt_crc8_fail = %d, cnt_mcs_fail = %d\n",
231 falsealm_cnt->cnt_parity_fail,
232 falsealm_cnt->cnt_rate_illegal,
233 falsealm_cnt->cnt_crc8_fail, falsealm_cnt->cnt_mcs_fail);
234
235 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
236 "cnt_ofdm_fail = %x, cnt_cck_fail = %x, cnt_all = %x\n",
237 falsealm_cnt->cnt_ofdm_fail,
238 falsealm_cnt->cnt_cck_fail, falsealm_cnt->cnt_all);
239}
240
241static void rtl92ee_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw)
242{
243 struct rtl_priv *rtlpriv = rtl_priv(hw);
244 struct dig_t *dm_dig = &rtlpriv->dm_digtable;
245 u8 cur_cck_cca_thresh;
246
247 if (rtlpriv->mac80211.link_state >= MAC80211_LINKED) {
248 if (dm_dig->rssi_val_min > 25) {
249 cur_cck_cca_thresh = 0xcd;
250 } else if ((dm_dig->rssi_val_min <= 25) &&
251 (dm_dig->rssi_val_min > 10)) {
252 cur_cck_cca_thresh = 0x83;
253 } else {
254 if (rtlpriv->falsealm_cnt.cnt_cck_fail > 1000)
255 cur_cck_cca_thresh = 0x83;
256 else
257 cur_cck_cca_thresh = 0x40;
258 }
259 } else {
260 if (rtlpriv->falsealm_cnt.cnt_cck_fail > 1000)
261 cur_cck_cca_thresh = 0x83;
262 else
263 cur_cck_cca_thresh = 0x40;
264 }
265 rtl92ee_dm_write_cck_cca_thres(hw, cur_cck_cca_thresh);
266}
267
268static void rtl92ee_dm_dig(struct ieee80211_hw *hw)
269{
270 struct rtl_priv *rtlpriv = rtl_priv(hw);
271 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
272 struct dig_t *dm_dig = &rtlpriv->dm_digtable;
273 u8 dig_min_0, dig_maxofmin;
274 bool bfirstconnect , bfirstdisconnect;
275 u8 dm_dig_max, dm_dig_min;
276 u8 current_igi = dm_dig->cur_igvalue;
277 u8 offset;
278
279
280 if (mac->act_scanning)
281 return;
282
283 dig_min_0 = dm_dig->dig_min_0;
284 bfirstconnect = (mac->link_state >= MAC80211_LINKED) &&
285 !dm_dig->media_connect_0;
286 bfirstdisconnect = (mac->link_state < MAC80211_LINKED) &&
287 dm_dig->media_connect_0;
288
289 dm_dig_max = 0x5a;
290 dm_dig_min = DM_DIG_MIN;
291 dig_maxofmin = DM_DIG_MAX_AP;
292
293 if (mac->link_state >= MAC80211_LINKED) {
294 if ((dm_dig->rssi_val_min + 10) > dm_dig_max)
295 dm_dig->rx_gain_max = dm_dig_max;
296 else if ((dm_dig->rssi_val_min + 10) < dm_dig_min)
297 dm_dig->rx_gain_max = dm_dig_min;
298 else
299 dm_dig->rx_gain_max = dm_dig->rssi_val_min + 10;
300
301 if (rtlpriv->dm.one_entry_only) {
302 offset = 0;
303 if (dm_dig->rssi_val_min - offset < dm_dig_min)
304 dig_min_0 = dm_dig_min;
305 else if (dm_dig->rssi_val_min - offset >
306 dig_maxofmin)
307 dig_min_0 = dig_maxofmin;
308 else
309 dig_min_0 = dm_dig->rssi_val_min - offset;
310 } else {
311 dig_min_0 = dm_dig_min;
312 }
313
314 } else {
315 dm_dig->rx_gain_max = dm_dig_max;
316 dig_min_0 = dm_dig_min;
317 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD, "no link\n");
318 }
319
320 if (rtlpriv->falsealm_cnt.cnt_all > 10000) {
321 if (dm_dig->large_fa_hit != 3)
322 dm_dig->large_fa_hit++;
323 if (dm_dig->forbidden_igi < current_igi) {
324 dm_dig->forbidden_igi = current_igi;
325 dm_dig->large_fa_hit = 1;
326 }
327
328 if (dm_dig->large_fa_hit >= 3) {
329 if (dm_dig->forbidden_igi + 1 > dm_dig->rx_gain_max)
330 dm_dig->rx_gain_min =
331 dm_dig->rx_gain_max;
332 else
333 dm_dig->rx_gain_min =
334 dm_dig->forbidden_igi + 1;
335 dm_dig->recover_cnt = 3600;
336 }
337 } else {
338 if (dm_dig->recover_cnt != 0) {
339 dm_dig->recover_cnt--;
340 } else {
341 if (dm_dig->large_fa_hit < 3) {
342 if ((dm_dig->forbidden_igi - 1) <
343 dig_min_0) {
344 dm_dig->forbidden_igi = dig_min_0;
345 dm_dig->rx_gain_min =
346 dig_min_0;
347 } else {
348 dm_dig->forbidden_igi--;
349 dm_dig->rx_gain_min =
350 dm_dig->forbidden_igi + 1;
351 }
352 } else {
353 dm_dig->large_fa_hit = 0;
354 }
355 }
356 }
357
358 if (rtlpriv->dm.dbginfo.num_qry_beacon_pkt < 5)
359 dm_dig->rx_gain_min = dm_dig_min;
360
361 if (dm_dig->rx_gain_min > dm_dig->rx_gain_max)
362 dm_dig->rx_gain_min = dm_dig->rx_gain_max;
363
364 if (mac->link_state >= MAC80211_LINKED) {
365 if (bfirstconnect) {
366 if (dm_dig->rssi_val_min <= dig_maxofmin)
367 current_igi = dm_dig->rssi_val_min;
368 else
369 current_igi = dig_maxofmin;
370
371 dm_dig->large_fa_hit = 0;
372 } else {
373 if (rtlpriv->falsealm_cnt.cnt_all > DM_DIG_FA_TH2)
374 current_igi += 4;
375 else if (rtlpriv->falsealm_cnt.cnt_all > DM_DIG_FA_TH1)
376 current_igi += 2;
377 else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH0)
378 current_igi -= 2;
379
380 if (rtlpriv->dm.dbginfo.num_qry_beacon_pkt < 5 &&
381 rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH1)
382 current_igi = dm_dig->rx_gain_min;
383 }
384 } else {
385 if (bfirstdisconnect) {
386 current_igi = dm_dig->rx_gain_min;
387 } else {
388 if (rtlpriv->falsealm_cnt.cnt_all > 10000)
389 current_igi += 4;
390 else if (rtlpriv->falsealm_cnt.cnt_all > 8000)
391 current_igi += 2;
392 else if (rtlpriv->falsealm_cnt.cnt_all < 500)
393 current_igi -= 2;
394 }
395 }
396
397 if (current_igi > dm_dig->rx_gain_max)
398 current_igi = dm_dig->rx_gain_max;
399 if (current_igi < dm_dig->rx_gain_min)
400 current_igi = dm_dig->rx_gain_min;
401
402 rtl92ee_dm_write_dig(hw , current_igi);
403 dm_dig->media_connect_0 = ((mac->link_state >= MAC80211_LINKED) ?
404 true : false);
405 dm_dig->dig_min_0 = dig_min_0;
406}
407
408void rtl92ee_dm_write_cck_cca_thres(struct ieee80211_hw *hw, u8 cur_thres)
409{
410 struct rtl_priv *rtlpriv = rtl_priv(hw);
411 struct dig_t *dm_dig = &rtlpriv->dm_digtable;
412
413 if (dm_dig->cur_cck_cca_thres != cur_thres)
414 rtl_write_byte(rtlpriv, DM_REG_CCK_CCA_11N, cur_thres);
415
416 dm_dig->pre_cck_cca_thres = dm_dig->cur_cck_cca_thres;
417 dm_dig->cur_cck_cca_thres = cur_thres;
418}
419
420void rtl92ee_dm_write_dig(struct ieee80211_hw *hw, u8 current_igi)
421{
422 struct rtl_priv *rtlpriv = rtl_priv(hw);
423 struct dig_t *dm_dig = &rtlpriv->dm_digtable;
424
425 if (dm_dig->stop_dig)
426 return;
427
428 if (dm_dig->cur_igvalue != current_igi) {
429 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f, current_igi);
430 if (rtlpriv->phy.rf_type != RF_1T1R)
431 rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, 0x7f, current_igi);
432 }
433 dm_dig->pre_igvalue = dm_dig->cur_igvalue;
434 dm_dig->cur_igvalue = current_igi;
435}
436
437static void rtl92ee_rssi_dump_to_register(struct ieee80211_hw *hw)
438{
439 struct rtl_priv *rtlpriv = rtl_priv(hw);
440
441 rtl_write_byte(rtlpriv, RA_RSSIDUMP,
442 rtlpriv->stats.rx_rssi_percentage[0]);
443 rtl_write_byte(rtlpriv, RB_RSSIDUMP,
444 rtlpriv->stats.rx_rssi_percentage[1]);
445
446
447
448
449
450 rtl_write_byte(rtlpriv, RS1_RXEVMDUMP, rtlpriv->stats.rx_evm_dbm[0]);
451 rtl_write_byte(rtlpriv, RS2_RXEVMDUMP, rtlpriv->stats.rx_evm_dbm[1]);
452
453 rtl_write_byte(rtlpriv, RA_RXSNRDUMP,
454 (u8)(rtlpriv->stats.rx_snr_db[0]));
455 rtl_write_byte(rtlpriv, RB_RXSNRDUMP,
456 (u8)(rtlpriv->stats.rx_snr_db[1]));
457
458 rtl_write_word(rtlpriv, RA_CFOSHORTDUMP,
459 rtlpriv->stats.rx_cfo_short[0]);
460 rtl_write_word(rtlpriv, RB_CFOSHORTDUMP,
461 rtlpriv->stats.rx_cfo_short[1]);
462
463 rtl_write_word(rtlpriv, RA_CFOLONGDUMP, rtlpriv->stats.rx_cfo_tail[0]);
464 rtl_write_word(rtlpriv, RB_CFOLONGDUMP, rtlpriv->stats.rx_cfo_tail[1]);
465}
466
467static void rtl92ee_dm_find_minimum_rssi(struct ieee80211_hw *hw)
468{
469 struct rtl_priv *rtlpriv = rtl_priv(hw);
470 struct dig_t *rtl_dm_dig = &rtlpriv->dm_digtable;
471 struct rtl_mac *mac = rtl_mac(rtlpriv);
472
473
474 if ((mac->link_state < MAC80211_LINKED) &&
475 (rtlpriv->dm.entry_min_undec_sm_pwdb == 0)) {
476 rtl_dm_dig->min_undec_pwdb_for_dm = 0;
477 RT_TRACE(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD,
478 "Not connected to any\n");
479 }
480 if (mac->link_state >= MAC80211_LINKED) {
481 if (mac->opmode == NL80211_IFTYPE_AP ||
482 mac->opmode == NL80211_IFTYPE_ADHOC) {
483 rtl_dm_dig->min_undec_pwdb_for_dm =
484 rtlpriv->dm.entry_min_undec_sm_pwdb;
485 RT_TRACE(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD,
486 "AP Client PWDB = 0x%lx\n",
487 rtlpriv->dm.entry_min_undec_sm_pwdb);
488 } else {
489 rtl_dm_dig->min_undec_pwdb_for_dm =
490 rtlpriv->dm.undec_sm_pwdb;
491 RT_TRACE(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD,
492 "STA Default Port PWDB = 0x%x\n",
493 rtl_dm_dig->min_undec_pwdb_for_dm);
494 }
495 } else {
496 rtl_dm_dig->min_undec_pwdb_for_dm =
497 rtlpriv->dm.entry_min_undec_sm_pwdb;
498 RT_TRACE(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD,
499 "AP Ext Port or disconnect PWDB = 0x%x\n",
500 rtl_dm_dig->min_undec_pwdb_for_dm);
501 }
502 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
503 "MinUndecoratedPWDBForDM =%d\n",
504 rtl_dm_dig->min_undec_pwdb_for_dm);
505}
506
507static void rtl92ee_dm_check_rssi_monitor(struct ieee80211_hw *hw)
508{
509 struct rtl_priv *rtlpriv = rtl_priv(hw);
510 struct dig_t *dm_dig = &rtlpriv->dm_digtable;
511 struct rtl_mac *mac = rtl_mac(rtlpriv);
512 struct rtl_dm *dm = rtl_dm(rtlpriv);
513 struct rtl_sta_info *drv_priv;
514 u8 h2c[4] = { 0 };
515 long max = 0, min = 0xff;
516 u8 i = 0;
517
518 if (mac->opmode == NL80211_IFTYPE_AP ||
519 mac->opmode == NL80211_IFTYPE_ADHOC ||
520 mac->opmode == NL80211_IFTYPE_MESH_POINT) {
521
522 spin_lock_bh(&rtlpriv->locks.entry_list_lock);
523 list_for_each_entry(drv_priv, &rtlpriv->entry_list, list) {
524 struct rssi_sta *stat = &drv_priv->rssi_stat;
525
526 if (stat->undec_sm_pwdb < min)
527 min = stat->undec_sm_pwdb;
528 if (stat->undec_sm_pwdb > max)
529 max = stat->undec_sm_pwdb;
530
531 h2c[3] = 0;
532 h2c[2] = (u8)(dm->undec_sm_pwdb & 0xFF);
533 h2c[1] = 0x20;
534 h2c[0] = ++i;
535 rtl92ee_fill_h2c_cmd(hw, H2C_92E_RSSI_REPORT, 4, h2c);
536 }
537 spin_unlock_bh(&rtlpriv->locks.entry_list_lock);
538
539
540 if (max != 0) {
541 dm->entry_max_undec_sm_pwdb = max;
542 RTPRINT(rtlpriv, FDM, DM_PWDB,
543 "EntryMaxPWDB = 0x%lx(%ld)\n", max, max);
544 } else {
545 dm->entry_max_undec_sm_pwdb = 0;
546 }
547
548 if (min != 0xff) {
549 dm->entry_min_undec_sm_pwdb = min;
550 RTPRINT(rtlpriv, FDM, DM_PWDB,
551 "EntryMinPWDB = 0x%lx(%ld)\n", min, min);
552 } else {
553 dm->entry_min_undec_sm_pwdb = 0;
554 }
555 }
556
557
558 if (dm->useramask) {
559 h2c[3] = 0;
560 h2c[2] = (u8)(dm->undec_sm_pwdb & 0xFF);
561 h2c[1] = 0x20;
562 h2c[0] = 0;
563 rtl92ee_fill_h2c_cmd(hw, H2C_92E_RSSI_REPORT, 4, h2c);
564 } else {
565 rtl_write_byte(rtlpriv, 0x4fe, dm->undec_sm_pwdb);
566 }
567 rtl92ee_rssi_dump_to_register(hw);
568 rtl92ee_dm_find_minimum_rssi(hw);
569 dm_dig->rssi_val_min = rtlpriv->dm_digtable.min_undec_pwdb_for_dm;
570}
571
572static void rtl92ee_dm_init_primary_cca_check(struct ieee80211_hw *hw)
573{
574 struct rtl_priv *rtlpriv = rtl_priv(hw);
575 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
576 struct dynamic_primary_cca *primarycca = &rtlpriv->primarycca;
577
578 rtlhal->rts_en = 0;
579 primarycca->dup_rts_flag = 0;
580 primarycca->intf_flag = 0;
581 primarycca->intf_type = 0;
582 primarycca->monitor_flag = 0;
583 primarycca->ch_offset = 0;
584 primarycca->mf_state = 0;
585}
586
587static bool rtl92ee_dm_is_edca_turbo_disable(struct ieee80211_hw *hw)
588{
589 struct rtl_priv *rtlpriv = rtl_priv(hw);
590
591 if (rtlpriv->mac80211.mode == WIRELESS_MODE_B)
592 return true;
593
594 return false;
595}
596
597void rtl92ee_dm_init_edca_turbo(struct ieee80211_hw *hw)
598{
599 struct rtl_priv *rtlpriv = rtl_priv(hw);
600
601 rtlpriv->dm.current_turbo_edca = false;
602 rtlpriv->dm.is_cur_rdlstate = false;
603 rtlpriv->dm.is_any_nonbepkts = false;
604}
605
606static void rtl92ee_dm_check_edca_turbo(struct ieee80211_hw *hw)
607{
608 struct rtl_priv *rtlpriv = rtl_priv(hw);
609
610 static u64 last_txok_cnt;
611 static u64 last_rxok_cnt;
612 u64 cur_txok_cnt = 0;
613 u64 cur_rxok_cnt = 0;
614 u32 edca_be_ul = 0x5ea42b;
615 u32 edca_be_dl = 0x5ea42b;
616 u32 edca_be = 0x5ea42b;
617 bool is_cur_rdlstate;
618 bool b_edca_turbo_on = false;
619
620 if (rtlpriv->dm.dbginfo.num_non_be_pkt > 0x100)
621 rtlpriv->dm.is_any_nonbepkts = true;
622 rtlpriv->dm.dbginfo.num_non_be_pkt = 0;
623
624 cur_txok_cnt = rtlpriv->stats.txbytesunicast - last_txok_cnt;
625 cur_rxok_cnt = rtlpriv->stats.rxbytesunicast - last_rxok_cnt;
626
627
628 b_edca_turbo_on = ((!rtlpriv->dm.is_any_nonbepkts) &&
629 (!rtlpriv->dm.disable_framebursting)) ?
630 true : false;
631
632 if (rtl92ee_dm_is_edca_turbo_disable(hw))
633 goto check_exit;
634
635 if (b_edca_turbo_on) {
636 is_cur_rdlstate = (cur_rxok_cnt > cur_txok_cnt * 4) ?
637 true : false;
638
639 edca_be = is_cur_rdlstate ? edca_be_dl : edca_be_ul;
640 rtl_write_dword(rtlpriv , REG_EDCA_BE_PARAM , edca_be);
641 rtlpriv->dm.is_cur_rdlstate = is_cur_rdlstate;
642 rtlpriv->dm.current_turbo_edca = true;
643 } else {
644 if (rtlpriv->dm.current_turbo_edca) {
645 u8 tmp = AC0_BE;
646
647 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
648 (u8 *)(&tmp));
649 }
650 rtlpriv->dm.current_turbo_edca = false;
651 }
652
653check_exit:
654 rtlpriv->dm.is_any_nonbepkts = false;
655 last_txok_cnt = rtlpriv->stats.txbytesunicast;
656 last_rxok_cnt = rtlpriv->stats.rxbytesunicast;
657}
658
659static void rtl92ee_dm_dynamic_edcca(struct ieee80211_hw *hw)
660{
661 struct rtl_priv *rtlpriv = rtl_priv(hw);
662 u8 reg_c50 , reg_c58;
663 bool fw_current_in_ps_mode = false;
664
665 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
666 (u8 *)(&fw_current_in_ps_mode));
667 if (fw_current_in_ps_mode)
668 return;
669
670 reg_c50 = rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0);
671 reg_c58 = rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0);
672
673 if (reg_c50 > 0x28 && reg_c58 > 0x28) {
674 if (!rtlpriv->rtlhal.pre_edcca_enable) {
675 rtl_write_byte(rtlpriv, ROFDM0_ECCATHRESHOLD, 0x03);
676 rtl_write_byte(rtlpriv, ROFDM0_ECCATHRESHOLD + 2, 0x00);
677 rtlpriv->rtlhal.pre_edcca_enable = true;
678 }
679 } else if (reg_c50 < 0x25 && reg_c58 < 0x25) {
680 if (rtlpriv->rtlhal.pre_edcca_enable) {
681 rtl_write_byte(rtlpriv, ROFDM0_ECCATHRESHOLD, 0x7f);
682 rtl_write_byte(rtlpriv, ROFDM0_ECCATHRESHOLD + 2, 0x7f);
683 rtlpriv->rtlhal.pre_edcca_enable = false;
684 }
685 }
686}
687
688static void rtl92ee_dm_adaptivity(struct ieee80211_hw *hw)
689{
690 rtl92ee_dm_dynamic_edcca(hw);
691}
692
693static void rtl92ee_dm_write_dynamic_cca(struct ieee80211_hw *hw,
694 u8 cur_mf_state)
695{
696 struct dynamic_primary_cca *primarycca = &rtl_priv(hw)->primarycca;
697
698 if (primarycca->mf_state != cur_mf_state)
699 rtl_set_bbreg(hw, DM_REG_L1SBD_PD_CH_11N, BIT(8) | BIT(7),
700 cur_mf_state);
701
702 primarycca->mf_state = cur_mf_state;
703}
704
705static void rtl92ee_dm_dynamic_primary_cca_ckeck(struct ieee80211_hw *hw)
706{
707 struct rtl_priv *rtlpriv = rtl_priv(hw);
708 struct false_alarm_statistics *falsealm_cnt = &rtlpriv->falsealm_cnt;
709 struct dynamic_primary_cca *primarycca = &rtlpriv->primarycca;
710 bool is40mhz = false;
711 u64 ofdm_cca, ofdm_fa, bw_usc_cnt, bw_lsc_cnt;
712 u8 sec_ch_offset;
713 u8 cur_mf_state;
714 static u8 count_down = MONITOR_TIME;
715
716 ofdm_cca = falsealm_cnt->cnt_ofdm_cca;
717 ofdm_fa = falsealm_cnt->cnt_ofdm_fail;
718 bw_usc_cnt = falsealm_cnt->cnt_bw_usc;
719 bw_lsc_cnt = falsealm_cnt->cnt_bw_lsc;
720 is40mhz = rtlpriv->mac80211.bw_40;
721 sec_ch_offset = rtlpriv->mac80211.cur_40_prime_sc;
722
723
724 if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP) {
725 cur_mf_state = MF_USC_LSC;
726 rtl92ee_dm_write_dynamic_cca(hw, cur_mf_state);
727 return;
728 }
729
730 if (rtlpriv->mac80211.link_state < MAC80211_LINKED)
731 return;
732
733 if (is40mhz)
734 return;
735
736 if (primarycca->pricca_flag == 0) {
737
738
739
740 if (sec_ch_offset == 2) {
741 if ((ofdm_cca > OFDMCCA_TH) &&
742 (bw_lsc_cnt > (bw_usc_cnt + BW_IND_BIAS)) &&
743 (ofdm_fa > (ofdm_cca >> 1))) {
744 primarycca->intf_type = 1;
745 primarycca->intf_flag = 1;
746 cur_mf_state = MF_USC;
747 rtl92ee_dm_write_dynamic_cca(hw, cur_mf_state);
748 primarycca->pricca_flag = 1;
749 } else if ((ofdm_cca > OFDMCCA_TH) &&
750 (bw_lsc_cnt > (bw_usc_cnt + BW_IND_BIAS)) &&
751 (ofdm_fa < (ofdm_cca >> 1))) {
752 primarycca->intf_type = 2;
753 primarycca->intf_flag = 1;
754 cur_mf_state = MF_USC;
755 rtl92ee_dm_write_dynamic_cca(hw, cur_mf_state);
756 primarycca->pricca_flag = 1;
757 primarycca->dup_rts_flag = 1;
758 rtlpriv->rtlhal.rts_en = 1;
759 } else {
760 primarycca->intf_type = 0;
761 primarycca->intf_flag = 0;
762 cur_mf_state = MF_USC_LSC;
763 rtl92ee_dm_write_dynamic_cca(hw, cur_mf_state);
764 rtlpriv->rtlhal.rts_en = 0;
765 primarycca->dup_rts_flag = 0;
766 }
767 } else if (sec_ch_offset == 1) {
768 if ((ofdm_cca > OFDMCCA_TH) &&
769 (bw_usc_cnt > (bw_lsc_cnt + BW_IND_BIAS)) &&
770 (ofdm_fa > (ofdm_cca >> 1))) {
771 primarycca->intf_type = 1;
772 primarycca->intf_flag = 1;
773 cur_mf_state = MF_LSC;
774 rtl92ee_dm_write_dynamic_cca(hw, cur_mf_state);
775 primarycca->pricca_flag = 1;
776 } else if ((ofdm_cca > OFDMCCA_TH) &&
777 (bw_usc_cnt > (bw_lsc_cnt + BW_IND_BIAS)) &&
778 (ofdm_fa < (ofdm_cca >> 1))) {
779 primarycca->intf_type = 2;
780 primarycca->intf_flag = 1;
781 cur_mf_state = MF_LSC;
782 rtl92ee_dm_write_dynamic_cca(hw, cur_mf_state);
783 primarycca->pricca_flag = 1;
784 primarycca->dup_rts_flag = 1;
785 rtlpriv->rtlhal.rts_en = 1;
786 } else {
787 primarycca->intf_type = 0;
788 primarycca->intf_flag = 0;
789 cur_mf_state = MF_USC_LSC;
790 rtl92ee_dm_write_dynamic_cca(hw, cur_mf_state);
791 rtlpriv->rtlhal.rts_en = 0;
792 primarycca->dup_rts_flag = 0;
793 }
794 }
795 } else {
796 count_down--;
797 if (count_down == 0) {
798 count_down = MONITOR_TIME;
799 primarycca->pricca_flag = 0;
800 cur_mf_state = MF_USC_LSC;
801
802 rtl92ee_dm_write_dynamic_cca(hw, cur_mf_state);
803 rtlpriv->rtlhal.rts_en = 0;
804 primarycca->dup_rts_flag = 0;
805 primarycca->intf_type = 0;
806 primarycca->intf_flag = 0;
807 }
808 }
809}
810
811static void rtl92ee_dm_dynamic_atc_switch(struct ieee80211_hw *hw)
812{
813 struct rtl_priv *rtlpriv = rtl_priv(hw);
814 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
815 u8 crystal_cap;
816 u32 packet_count;
817 int cfo_khz_a , cfo_khz_b , cfo_ave = 0, adjust_xtal = 0;
818 int cfo_ave_diff;
819
820 if (rtlpriv->mac80211.link_state < MAC80211_LINKED) {
821 if (rtldm->atc_status == ATC_STATUS_OFF) {
822 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(11),
823 ATC_STATUS_ON);
824 rtldm->atc_status = ATC_STATUS_ON;
825 }
826
827 if (rtlpriv->cfg->ops->get_btc_status()) {
828 if (!rtlpriv->btcoexist.btc_ops->
829 btc_is_bt_disabled(rtlpriv)) {
830 RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
831 "odm_DynamicATCSwitch(): Disable CFO tracking for BT!!\n");
832 return;
833 }
834 }
835
836 if (rtldm->crystal_cap != rtlpriv->efuse.crystalcap) {
837 rtldm->crystal_cap = rtlpriv->efuse.crystalcap;
838 crystal_cap = rtldm->crystal_cap & 0x3f;
839 rtl_set_bbreg(hw, REG_MAC_PHY_CTRL, 0xFFF000,
840 (crystal_cap | (crystal_cap << 6)));
841 }
842 } else {
843 cfo_khz_a = (int)(rtldm->cfo_tail[0] * 3125) / 1280;
844 cfo_khz_b = (int)(rtldm->cfo_tail[1] * 3125) / 1280;
845 packet_count = rtldm->packet_count;
846
847 if (packet_count == rtldm->packet_count_pre)
848 return;
849
850 rtldm->packet_count_pre = packet_count;
851
852 if (rtlpriv->phy.rf_type == RF_1T1R)
853 cfo_ave = cfo_khz_a;
854 else
855 cfo_ave = (int)(cfo_khz_a + cfo_khz_b) >> 1;
856
857 cfo_ave_diff = (rtldm->cfo_ave_pre >= cfo_ave) ?
858 (rtldm->cfo_ave_pre - cfo_ave) :
859 (cfo_ave - rtldm->cfo_ave_pre);
860
861 if (cfo_ave_diff > 20 && rtldm->large_cfo_hit == 0) {
862 rtldm->large_cfo_hit = 1;
863 return;
864 }
865 rtldm->large_cfo_hit = 0;
866
867 rtldm->cfo_ave_pre = cfo_ave;
868
869 if (cfo_ave >= -rtldm->cfo_threshold &&
870 cfo_ave <= rtldm->cfo_threshold && rtldm->is_freeze == 0) {
871 if (rtldm->cfo_threshold == CFO_THRESHOLD_XTAL) {
872 rtldm->cfo_threshold = CFO_THRESHOLD_XTAL + 10;
873 rtldm->is_freeze = 1;
874 } else {
875 rtldm->cfo_threshold = CFO_THRESHOLD_XTAL;
876 }
877 }
878
879 if (cfo_ave > rtldm->cfo_threshold && rtldm->crystal_cap < 0x3f)
880 adjust_xtal = ((cfo_ave - CFO_THRESHOLD_XTAL) >> 2) + 1;
881 else if ((cfo_ave < -rtlpriv->dm.cfo_threshold) &&
882 rtlpriv->dm.crystal_cap > 0)
883 adjust_xtal = ((cfo_ave + CFO_THRESHOLD_XTAL) >> 2) - 1;
884
885 if (adjust_xtal != 0) {
886 rtldm->is_freeze = 0;
887 rtldm->crystal_cap += adjust_xtal;
888
889 if (rtldm->crystal_cap > 0x3f)
890 rtldm->crystal_cap = 0x3f;
891 else if (rtldm->crystal_cap < 0)
892 rtldm->crystal_cap = 0;
893
894 crystal_cap = rtldm->crystal_cap & 0x3f;
895 rtl_set_bbreg(hw, REG_MAC_PHY_CTRL, 0xFFF000,
896 (crystal_cap | (crystal_cap << 6)));
897 }
898
899 if (cfo_ave < CFO_THRESHOLD_ATC &&
900 cfo_ave > -CFO_THRESHOLD_ATC) {
901 if (rtldm->atc_status == ATC_STATUS_ON) {
902 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(11),
903 ATC_STATUS_OFF);
904 rtldm->atc_status = ATC_STATUS_OFF;
905 }
906 } else {
907 if (rtldm->atc_status == ATC_STATUS_OFF) {
908 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(11),
909 ATC_STATUS_ON);
910 rtldm->atc_status = ATC_STATUS_ON;
911 }
912 }
913 }
914}
915
916static void rtl92ee_dm_init_txpower_tracking(struct ieee80211_hw *hw)
917{
918 struct rtl_priv *rtlpriv = rtl_priv(hw);
919 struct rtl_dm *dm = rtl_dm(rtlpriv);
920 u8 path;
921
922 dm->txpower_tracking = true;
923 dm->default_ofdm_index = 30;
924 dm->default_cck_index = 20;
925
926 dm->swing_idx_cck_base = dm->default_cck_index;
927 dm->cck_index = dm->default_cck_index;
928
929 for (path = RF90_PATH_A; path < MAX_RF_PATH; path++) {
930 dm->swing_idx_ofdm_base[path] = dm->default_ofdm_index;
931 dm->ofdm_index[path] = dm->default_ofdm_index;
932 dm->delta_power_index[path] = 0;
933 dm->delta_power_index_last[path] = 0;
934 dm->power_index_offset[path] = 0;
935 }
936}
937
938void rtl92ee_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw)
939{
940 struct rtl_priv *rtlpriv = rtl_priv(hw);
941 struct rate_adaptive *p_ra = &rtlpriv->ra;
942
943 p_ra->ratr_state = DM_RATR_STA_INIT;
944 p_ra->pre_ratr_state = DM_RATR_STA_INIT;
945
946 if (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER)
947 rtlpriv->dm.useramask = true;
948 else
949 rtlpriv->dm.useramask = false;
950
951 p_ra->ldpc_thres = 35;
952 p_ra->use_ldpc = false;
953 p_ra->high_rssi_thresh_for_ra = 50;
954 p_ra->low_rssi_thresh_for_ra40m = 20;
955}
956
957static bool _rtl92ee_dm_ra_state_check(struct ieee80211_hw *hw,
958 s32 rssi, u8 *ratr_state)
959{
960 struct rtl_priv *rtlpriv = rtl_priv(hw);
961 struct rate_adaptive *p_ra = &rtlpriv->ra;
962 const u8 go_up_gap = 5;
963 u32 high_rssithresh_for_ra = p_ra->high_rssi_thresh_for_ra;
964 u32 low_rssithresh_for_ra = p_ra->low_rssi_thresh_for_ra40m;
965 u8 state;
966
967
968
969
970
971
972
973 switch (*ratr_state) {
974 case DM_RATR_STA_INIT:
975 case DM_RATR_STA_HIGH:
976 break;
977 case DM_RATR_STA_MIDDLE:
978 high_rssithresh_for_ra += go_up_gap;
979 break;
980 case DM_RATR_STA_LOW:
981 high_rssithresh_for_ra += go_up_gap;
982 low_rssithresh_for_ra += go_up_gap;
983 break;
984 default:
985 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
986 "wrong rssi level setting %d !\n", *ratr_state);
987 break;
988 }
989
990
991 if (rssi > high_rssithresh_for_ra)
992 state = DM_RATR_STA_HIGH;
993 else if (rssi > low_rssithresh_for_ra)
994 state = DM_RATR_STA_MIDDLE;
995 else
996 state = DM_RATR_STA_LOW;
997
998 if (*ratr_state != state) {
999 *ratr_state = state;
1000 return true;
1001 }
1002
1003 return false;
1004}
1005
1006static void rtl92ee_dm_refresh_rate_adaptive_mask(struct ieee80211_hw *hw)
1007{
1008 struct rtl_priv *rtlpriv = rtl_priv(hw);
1009 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1010 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1011 struct rate_adaptive *p_ra = &rtlpriv->ra;
1012 struct ieee80211_sta *sta = NULL;
1013
1014 if (is_hal_stop(rtlhal)) {
1015 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
1016 "driver is going to unload\n");
1017 return;
1018 }
1019
1020 if (!rtlpriv->dm.useramask) {
1021 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
1022 "driver does not control rate adaptive mask\n");
1023 return;
1024 }
1025
1026 if (mac->link_state == MAC80211_LINKED &&
1027 mac->opmode == NL80211_IFTYPE_STATION) {
1028 if (rtlpriv->dm.undec_sm_pwdb < p_ra->ldpc_thres) {
1029 p_ra->use_ldpc = true;
1030 p_ra->lower_rts_rate = true;
1031 } else if (rtlpriv->dm.undec_sm_pwdb >
1032 (p_ra->ldpc_thres - 5)) {
1033 p_ra->use_ldpc = false;
1034 p_ra->lower_rts_rate = false;
1035 }
1036 if (_rtl92ee_dm_ra_state_check(hw, rtlpriv->dm.undec_sm_pwdb,
1037 &p_ra->ratr_state)) {
1038 rcu_read_lock();
1039 sta = rtl_find_sta(hw, mac->bssid);
1040 if (sta)
1041 rtlpriv->cfg->ops->update_rate_tbl(hw, sta,
1042 p_ra->ratr_state);
1043 rcu_read_unlock();
1044
1045 p_ra->pre_ratr_state = p_ra->ratr_state;
1046 }
1047 }
1048}
1049
1050static void rtl92ee_dm_init_dynamic_atc_switch(struct ieee80211_hw *hw)
1051{
1052 struct rtl_priv *rtlpriv = rtl_priv(hw);
1053
1054 rtlpriv->dm.crystal_cap = rtlpriv->efuse.crystalcap;
1055
1056 rtlpriv->dm.atc_status = rtl_get_bbreg(hw, ROFDM1_CFOTRACKING, BIT(11));
1057 rtlpriv->dm.cfo_threshold = CFO_THRESHOLD_XTAL;
1058}
1059
1060void rtl92ee_dm_init(struct ieee80211_hw *hw)
1061{
1062 struct rtl_priv *rtlpriv = rtl_priv(hw);
1063 u32 cur_igvalue = rtl_get_bbreg(hw, DM_REG_IGI_A_11N, DM_BIT_IGI_11N);
1064
1065 rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER;
1066
1067 rtl_dm_diginit(hw, cur_igvalue);
1068 rtl92ee_dm_init_rate_adaptive_mask(hw);
1069 rtl92ee_dm_init_primary_cca_check(hw);
1070 rtl92ee_dm_init_edca_turbo(hw);
1071 rtl92ee_dm_init_txpower_tracking(hw);
1072 rtl92ee_dm_init_dynamic_atc_switch(hw);
1073}
1074
1075static void rtl92ee_dm_common_info_self_update(struct ieee80211_hw *hw)
1076{
1077 struct rtl_priv *rtlpriv = rtl_priv(hw);
1078 struct rtl_sta_info *drv_priv;
1079 u8 cnt = 0;
1080
1081 rtlpriv->dm.one_entry_only = false;
1082
1083 if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_STATION &&
1084 rtlpriv->mac80211.link_state >= MAC80211_LINKED) {
1085 rtlpriv->dm.one_entry_only = true;
1086 return;
1087 }
1088
1089 if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP ||
1090 rtlpriv->mac80211.opmode == NL80211_IFTYPE_ADHOC ||
1091 rtlpriv->mac80211.opmode == NL80211_IFTYPE_MESH_POINT) {
1092 spin_lock_bh(&rtlpriv->locks.entry_list_lock);
1093 list_for_each_entry(drv_priv, &rtlpriv->entry_list, list) {
1094 cnt++;
1095 }
1096 spin_unlock_bh(&rtlpriv->locks.entry_list_lock);
1097
1098 if (cnt == 1)
1099 rtlpriv->dm.one_entry_only = true;
1100 }
1101}
1102
1103void rtl92ee_dm_dynamic_arfb_select(struct ieee80211_hw *hw,
1104 u8 rate, bool collision_state)
1105{
1106 struct rtl_priv *rtlpriv = rtl_priv(hw);
1107
1108 if (rate >= DESC92C_RATEMCS8 && rate <= DESC92C_RATEMCS12) {
1109 if (collision_state == 1) {
1110 if (rate == DESC92C_RATEMCS12) {
1111 rtl_write_dword(rtlpriv, REG_DARFRC, 0x0);
1112 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1113 0x07060501);
1114 } else if (rate == DESC92C_RATEMCS11) {
1115 rtl_write_dword(rtlpriv, REG_DARFRC, 0x0);
1116 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1117 0x07070605);
1118 } else if (rate == DESC92C_RATEMCS10) {
1119 rtl_write_dword(rtlpriv, REG_DARFRC, 0x0);
1120 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1121 0x08080706);
1122 } else if (rate == DESC92C_RATEMCS9) {
1123 rtl_write_dword(rtlpriv, REG_DARFRC, 0x0);
1124 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1125 0x08080707);
1126 } else {
1127 rtl_write_dword(rtlpriv, REG_DARFRC, 0x0);
1128 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1129 0x09090808);
1130 }
1131 } else {
1132 if (rate == DESC92C_RATEMCS12) {
1133 rtl_write_dword(rtlpriv, REG_DARFRC,
1134 0x05010000);
1135 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1136 0x09080706);
1137 } else if (rate == DESC92C_RATEMCS11) {
1138 rtl_write_dword(rtlpriv, REG_DARFRC,
1139 0x06050000);
1140 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1141 0x09080807);
1142 } else if (rate == DESC92C_RATEMCS10) {
1143 rtl_write_dword(rtlpriv, REG_DARFRC,
1144 0x07060000);
1145 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1146 0x0a090908);
1147 } else if (rate == DESC92C_RATEMCS9) {
1148 rtl_write_dword(rtlpriv, REG_DARFRC,
1149 0x07070000);
1150 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1151 0x0a090808);
1152 } else {
1153 rtl_write_dword(rtlpriv, REG_DARFRC,
1154 0x08080000);
1155 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1156 0x0b0a0909);
1157 }
1158 }
1159 } else {
1160 if (collision_state == 1) {
1161 if (rate == DESC92C_RATEMCS15) {
1162 rtl_write_dword(rtlpriv, REG_DARFRC,
1163 0x00000000);
1164 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1165 0x05040302);
1166 } else if (rate == DESC92C_RATEMCS14) {
1167 rtl_write_dword(rtlpriv, REG_DARFRC,
1168 0x00000000);
1169 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1170 0x06050302);
1171 } else if (rate == DESC92C_RATEMCS13) {
1172 rtl_write_dword(rtlpriv, REG_DARFRC,
1173 0x00000000);
1174 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1175 0x07060502);
1176 } else {
1177 rtl_write_dword(rtlpriv, REG_DARFRC,
1178 0x00000000);
1179 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1180 0x06050402);
1181 }
1182 } else{
1183 if (rate == DESC92C_RATEMCS15) {
1184 rtl_write_dword(rtlpriv, REG_DARFRC,
1185 0x03020000);
1186 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1187 0x07060504);
1188 } else if (rate == DESC92C_RATEMCS14) {
1189 rtl_write_dword(rtlpriv, REG_DARFRC,
1190 0x03020000);
1191 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1192 0x08070605);
1193 } else if (rate == DESC92C_RATEMCS13) {
1194 rtl_write_dword(rtlpriv, REG_DARFRC,
1195 0x05020000);
1196 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1197 0x09080706);
1198 } else {
1199 rtl_write_dword(rtlpriv, REG_DARFRC,
1200 0x04020000);
1201 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1202 0x08070605);
1203 }
1204 }
1205 }
1206}
1207
1208void rtl92ee_dm_watchdog(struct ieee80211_hw *hw)
1209{
1210 struct rtl_priv *rtlpriv = rtl_priv(hw);
1211 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1212 bool fw_current_inpsmode = false;
1213 bool fw_ps_awake = true;
1214
1215 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
1216 (u8 *)(&fw_current_inpsmode));
1217 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FWLPS_RF_ON,
1218 (u8 *)(&fw_ps_awake));
1219 if (ppsc->p2p_ps_info.p2p_ps_mode)
1220 fw_ps_awake = false;
1221
1222 spin_lock(&rtlpriv->locks.rf_ps_lock);
1223 if ((ppsc->rfpwr_state == ERFON) &&
1224 ((!fw_current_inpsmode) && fw_ps_awake) &&
1225 (!ppsc->rfchange_inprogress)) {
1226 rtl92ee_dm_common_info_self_update(hw);
1227 rtl92ee_dm_false_alarm_counter_statistics(hw);
1228 rtl92ee_dm_check_rssi_monitor(hw);
1229 rtl92ee_dm_dig(hw);
1230 rtl92ee_dm_adaptivity(hw);
1231 rtl92ee_dm_cck_packet_detection_thresh(hw);
1232 rtl92ee_dm_refresh_rate_adaptive_mask(hw);
1233 rtl92ee_dm_check_edca_turbo(hw);
1234 rtl92ee_dm_dynamic_atc_switch(hw);
1235 rtl92ee_dm_dynamic_primary_cca_ckeck(hw);
1236 }
1237 spin_unlock(&rtlpriv->locks.rf_ps_lock);
1238}
1239
