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9#include <linux/bitops.h>
10#include <linux/clk.h>
11#include <linux/err.h>
12#include <linux/io.h>
13#include <linux/module.h>
14#include <linux/of.h>
15#include <linux/of_device.h>
16#include <linux/platform_device.h>
17#include <linux/pwm.h>
18#include <linux/slab.h>
19#include <linux/spinlock.h>
20#include <linux/time.h>
21
22#define PWM_CTRL_REG 0x0
23
24#define PWM_CH_PRD_BASE 0x4
25#define PWM_CH_PRD_OFFSET 0x4
26#define PWM_CH_PRD(ch) (PWM_CH_PRD_BASE + PWM_CH_PRD_OFFSET * (ch))
27
28#define PWMCH_OFFSET 15
29#define PWM_PRESCAL_MASK GENMASK(3, 0)
30#define PWM_PRESCAL_OFF 0
31#define PWM_EN BIT(4)
32#define PWM_ACT_STATE BIT(5)
33#define PWM_CLK_GATING BIT(6)
34#define PWM_MODE BIT(7)
35#define PWM_PULSE BIT(8)
36#define PWM_BYPASS BIT(9)
37
38#define PWM_RDY_BASE 28
39#define PWM_RDY_OFFSET 1
40#define PWM_RDY(ch) BIT(PWM_RDY_BASE + PWM_RDY_OFFSET * (ch))
41
42#define PWM_PRD(prd) (((prd) - 1) << 16)
43#define PWM_PRD_MASK GENMASK(15, 0)
44
45#define PWM_DTY_MASK GENMASK(15, 0)
46
47#define BIT_CH(bit, chan) ((bit) << ((chan) * PWMCH_OFFSET))
48
49static const u32 prescaler_table[] = {
50 120,
51 180,
52 240,
53 360,
54 480,
55 0,
56 0,
57 0,
58 12000,
59 24000,
60 36000,
61 48000,
62 72000,
63 0,
64 0,
65 0,
66};
67
68struct sun4i_pwm_data {
69 bool has_prescaler_bypass;
70 bool has_rdy;
71 unsigned int npwm;
72};
73
74struct sun4i_pwm_chip {
75 struct pwm_chip chip;
76 struct clk *clk;
77 void __iomem *base;
78 spinlock_t ctrl_lock;
79 const struct sun4i_pwm_data *data;
80};
81
82static inline struct sun4i_pwm_chip *to_sun4i_pwm_chip(struct pwm_chip *chip)
83{
84 return container_of(chip, struct sun4i_pwm_chip, chip);
85}
86
87static inline u32 sun4i_pwm_readl(struct sun4i_pwm_chip *chip,
88 unsigned long offset)
89{
90 return readl(chip->base + offset);
91}
92
93static inline void sun4i_pwm_writel(struct sun4i_pwm_chip *chip,
94 u32 val, unsigned long offset)
95{
96 writel(val, chip->base + offset);
97}
98
99static int sun4i_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
100 int duty_ns, int period_ns)
101{
102 struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
103 u32 prd, dty, val, clk_gate;
104 u64 clk_rate, div = 0;
105 unsigned int prescaler = 0;
106 int err;
107
108 clk_rate = clk_get_rate(sun4i_pwm->clk);
109
110 if (sun4i_pwm->data->has_prescaler_bypass) {
111
112 prescaler = PWM_PRESCAL_MASK;
113
114
115
116
117
118 div = clk_rate * period_ns + NSEC_PER_SEC / 2;
119 do_div(div, NSEC_PER_SEC);
120 if (div - 1 > PWM_PRD_MASK)
121 prescaler = 0;
122 }
123
124 if (prescaler == 0) {
125
126 for (prescaler = 0; prescaler < PWM_PRESCAL_MASK; prescaler++) {
127 if (!prescaler_table[prescaler])
128 continue;
129 div = clk_rate;
130 do_div(div, prescaler_table[prescaler]);
131 div = div * period_ns;
132 do_div(div, NSEC_PER_SEC);
133 if (div - 1 <= PWM_PRD_MASK)
134 break;
135 }
136
137 if (div - 1 > PWM_PRD_MASK) {
138 dev_err(chip->dev, "period exceeds the maximum value\n");
139 return -EINVAL;
140 }
141 }
142
143 prd = div;
144 div *= duty_ns;
145 do_div(div, period_ns);
146 dty = div;
147
148 err = clk_prepare_enable(sun4i_pwm->clk);
149 if (err) {
150 dev_err(chip->dev, "failed to enable PWM clock\n");
151 return err;
152 }
153
154 spin_lock(&sun4i_pwm->ctrl_lock);
155 val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
156
157 if (sun4i_pwm->data->has_rdy && (val & PWM_RDY(pwm->hwpwm))) {
158 spin_unlock(&sun4i_pwm->ctrl_lock);
159 clk_disable_unprepare(sun4i_pwm->clk);
160 return -EBUSY;
161 }
162
163 clk_gate = val & BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
164 if (clk_gate) {
165 val &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
166 sun4i_pwm_writel(sun4i_pwm, val, PWM_CTRL_REG);
167 }
168
169 val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
170 val &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm);
171 val |= BIT_CH(prescaler, pwm->hwpwm);
172 sun4i_pwm_writel(sun4i_pwm, val, PWM_CTRL_REG);
173
174 val = (dty & PWM_DTY_MASK) | PWM_PRD(prd);
175 sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm));
176
177 if (clk_gate) {
178 val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
179 val |= clk_gate;
180 sun4i_pwm_writel(sun4i_pwm, val, PWM_CTRL_REG);
181 }
182
183 spin_unlock(&sun4i_pwm->ctrl_lock);
184 clk_disable_unprepare(sun4i_pwm->clk);
185
186 return 0;
187}
188
189static int sun4i_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
190 enum pwm_polarity polarity)
191{
192 struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
193 u32 val;
194 int ret;
195
196 ret = clk_prepare_enable(sun4i_pwm->clk);
197 if (ret) {
198 dev_err(chip->dev, "failed to enable PWM clock\n");
199 return ret;
200 }
201
202 spin_lock(&sun4i_pwm->ctrl_lock);
203 val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
204
205 if (polarity != PWM_POLARITY_NORMAL)
206 val &= ~BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
207 else
208 val |= BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
209
210 sun4i_pwm_writel(sun4i_pwm, val, PWM_CTRL_REG);
211
212 spin_unlock(&sun4i_pwm->ctrl_lock);
213 clk_disable_unprepare(sun4i_pwm->clk);
214
215 return 0;
216}
217
218static int sun4i_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
219{
220 struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
221 u32 val;
222 int ret;
223
224 ret = clk_prepare_enable(sun4i_pwm->clk);
225 if (ret) {
226 dev_err(chip->dev, "failed to enable PWM clock\n");
227 return ret;
228 }
229
230 spin_lock(&sun4i_pwm->ctrl_lock);
231 val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
232 val |= BIT_CH(PWM_EN, pwm->hwpwm);
233 val |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
234 sun4i_pwm_writel(sun4i_pwm, val, PWM_CTRL_REG);
235 spin_unlock(&sun4i_pwm->ctrl_lock);
236
237 return 0;
238}
239
240static void sun4i_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
241{
242 struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
243 u32 val;
244
245 spin_lock(&sun4i_pwm->ctrl_lock);
246 val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
247 val &= ~BIT_CH(PWM_EN, pwm->hwpwm);
248 val &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
249 sun4i_pwm_writel(sun4i_pwm, val, PWM_CTRL_REG);
250 spin_unlock(&sun4i_pwm->ctrl_lock);
251
252 clk_disable_unprepare(sun4i_pwm->clk);
253}
254
255static const struct pwm_ops sun4i_pwm_ops = {
256 .config = sun4i_pwm_config,
257 .set_polarity = sun4i_pwm_set_polarity,
258 .enable = sun4i_pwm_enable,
259 .disable = sun4i_pwm_disable,
260 .owner = THIS_MODULE,
261};
262
263static const struct sun4i_pwm_data sun4i_pwm_data_a10 = {
264 .has_prescaler_bypass = false,
265 .has_rdy = false,
266 .npwm = 2,
267};
268
269static const struct sun4i_pwm_data sun4i_pwm_data_a10s = {
270 .has_prescaler_bypass = true,
271 .has_rdy = true,
272 .npwm = 2,
273};
274
275static const struct sun4i_pwm_data sun4i_pwm_data_a13 = {
276 .has_prescaler_bypass = true,
277 .has_rdy = true,
278 .npwm = 1,
279};
280
281static const struct sun4i_pwm_data sun4i_pwm_data_a20 = {
282 .has_prescaler_bypass = true,
283 .has_rdy = true,
284 .npwm = 2,
285};
286
287static const struct of_device_id sun4i_pwm_dt_ids[] = {
288 {
289 .compatible = "allwinner,sun4i-a10-pwm",
290 .data = &sun4i_pwm_data_a10,
291 }, {
292 .compatible = "allwinner,sun5i-a10s-pwm",
293 .data = &sun4i_pwm_data_a10s,
294 }, {
295 .compatible = "allwinner,sun5i-a13-pwm",
296 .data = &sun4i_pwm_data_a13,
297 }, {
298 .compatible = "allwinner,sun7i-a20-pwm",
299 .data = &sun4i_pwm_data_a20,
300 }, {
301
302 },
303};
304MODULE_DEVICE_TABLE(of, sun4i_pwm_dt_ids);
305
306static int sun4i_pwm_probe(struct platform_device *pdev)
307{
308 struct sun4i_pwm_chip *pwm;
309 struct resource *res;
310 u32 val;
311 int i, ret;
312 const struct of_device_id *match;
313
314 match = of_match_device(sun4i_pwm_dt_ids, &pdev->dev);
315
316 pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
317 if (!pwm)
318 return -ENOMEM;
319
320 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
321 pwm->base = devm_ioremap_resource(&pdev->dev, res);
322 if (IS_ERR(pwm->base))
323 return PTR_ERR(pwm->base);
324
325 pwm->clk = devm_clk_get(&pdev->dev, NULL);
326 if (IS_ERR(pwm->clk))
327 return PTR_ERR(pwm->clk);
328
329 pwm->data = match->data;
330 pwm->chip.dev = &pdev->dev;
331 pwm->chip.ops = &sun4i_pwm_ops;
332 pwm->chip.base = -1;
333 pwm->chip.npwm = pwm->data->npwm;
334 pwm->chip.can_sleep = true;
335 pwm->chip.of_xlate = of_pwm_xlate_with_flags;
336 pwm->chip.of_pwm_n_cells = 3;
337
338 spin_lock_init(&pwm->ctrl_lock);
339
340 ret = pwmchip_add(&pwm->chip);
341 if (ret < 0) {
342 dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
343 return ret;
344 }
345
346 platform_set_drvdata(pdev, pwm);
347
348 ret = clk_prepare_enable(pwm->clk);
349 if (ret) {
350 dev_err(&pdev->dev, "failed to enable PWM clock\n");
351 goto clk_error;
352 }
353
354 val = sun4i_pwm_readl(pwm, PWM_CTRL_REG);
355 for (i = 0; i < pwm->chip.npwm; i++)
356 if (!(val & BIT_CH(PWM_ACT_STATE, i)))
357 pwm_set_polarity(&pwm->chip.pwms[i],
358 PWM_POLARITY_INVERSED);
359 clk_disable_unprepare(pwm->clk);
360
361 return 0;
362
363clk_error:
364 pwmchip_remove(&pwm->chip);
365 return ret;
366}
367
368static int sun4i_pwm_remove(struct platform_device *pdev)
369{
370 struct sun4i_pwm_chip *pwm = platform_get_drvdata(pdev);
371
372 return pwmchip_remove(&pwm->chip);
373}
374
375static struct platform_driver sun4i_pwm_driver = {
376 .driver = {
377 .name = "sun4i-pwm",
378 .of_match_table = sun4i_pwm_dt_ids,
379 },
380 .probe = sun4i_pwm_probe,
381 .remove = sun4i_pwm_remove,
382};
383module_platform_driver(sun4i_pwm_driver);
384
385MODULE_ALIAS("platform:sun4i-pwm");
386MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@free-electrons.com>");
387MODULE_DESCRIPTION("Allwinner sun4i PWM driver");
388MODULE_LICENSE("GPL v2");
389
