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57#include <linux/fs.h>
58#include <linux/init.h>
59#include <linux/types.h>
60#include <linux/errno.h>
61#include <linux/kernel.h>
62#include <linux/slab.h>
63#include <linux/vmalloc.h>
64#include <linux/ioport.h>
65#include <linux/delay.h>
66#include <linux/pci.h>
67#include <linux/wait.h>
68#include <linux/spinlock.h>
69#include <linux/sched.h>
70#include <linux/interrupt.h>
71#include <linux/blkdev.h>
72#include <linux/firmware.h>
73#include <linux/module.h>
74#include <linux/moduleparam.h>
75#include <linux/libata.h>
76#include <linux/hdreg.h>
77#include <linux/reboot.h>
78#include <linux/stringify.h>
79#include <asm/io.h>
80#include <asm/irq.h>
81#include <asm/processor.h>
82#include <scsi/scsi.h>
83#include <scsi/scsi_host.h>
84#include <scsi/scsi_tcq.h>
85#include <scsi/scsi_eh.h>
86#include <scsi/scsi_cmnd.h>
87#include "ipr.h"
88
89
90
91
92static LIST_HEAD(ipr_ioa_head);
93static unsigned int ipr_log_level = IPR_DEFAULT_LOG_LEVEL;
94static unsigned int ipr_max_speed = 1;
95static int ipr_testmode = 0;
96static unsigned int ipr_fastfail = 0;
97static unsigned int ipr_transop_timeout = 0;
98static unsigned int ipr_debug = 0;
99static unsigned int ipr_max_devs = IPR_DEFAULT_SIS64_DEVS;
100static unsigned int ipr_dual_ioa_raid = 1;
101static unsigned int ipr_number_of_msix = 16;
102static unsigned int ipr_fast_reboot;
103static DEFINE_SPINLOCK(ipr_driver_lock);
104
105
106static const struct ipr_chip_cfg_t ipr_chip_cfg[] = {
107 {
108 .mailbox = 0x0042C,
109 .max_cmds = 100,
110 .cache_line_size = 0x20,
111 .clear_isr = 1,
112 .iopoll_weight = 0,
113 {
114 .set_interrupt_mask_reg = 0x0022C,
115 .clr_interrupt_mask_reg = 0x00230,
116 .clr_interrupt_mask_reg32 = 0x00230,
117 .sense_interrupt_mask_reg = 0x0022C,
118 .sense_interrupt_mask_reg32 = 0x0022C,
119 .clr_interrupt_reg = 0x00228,
120 .clr_interrupt_reg32 = 0x00228,
121 .sense_interrupt_reg = 0x00224,
122 .sense_interrupt_reg32 = 0x00224,
123 .ioarrin_reg = 0x00404,
124 .sense_uproc_interrupt_reg = 0x00214,
125 .sense_uproc_interrupt_reg32 = 0x00214,
126 .set_uproc_interrupt_reg = 0x00214,
127 .set_uproc_interrupt_reg32 = 0x00214,
128 .clr_uproc_interrupt_reg = 0x00218,
129 .clr_uproc_interrupt_reg32 = 0x00218
130 }
131 },
132 {
133 .mailbox = 0x0052C,
134 .max_cmds = 100,
135 .cache_line_size = 0x20,
136 .clear_isr = 1,
137 .iopoll_weight = 0,
138 {
139 .set_interrupt_mask_reg = 0x00288,
140 .clr_interrupt_mask_reg = 0x0028C,
141 .clr_interrupt_mask_reg32 = 0x0028C,
142 .sense_interrupt_mask_reg = 0x00288,
143 .sense_interrupt_mask_reg32 = 0x00288,
144 .clr_interrupt_reg = 0x00284,
145 .clr_interrupt_reg32 = 0x00284,
146 .sense_interrupt_reg = 0x00280,
147 .sense_interrupt_reg32 = 0x00280,
148 .ioarrin_reg = 0x00504,
149 .sense_uproc_interrupt_reg = 0x00290,
150 .sense_uproc_interrupt_reg32 = 0x00290,
151 .set_uproc_interrupt_reg = 0x00290,
152 .set_uproc_interrupt_reg32 = 0x00290,
153 .clr_uproc_interrupt_reg = 0x00294,
154 .clr_uproc_interrupt_reg32 = 0x00294
155 }
156 },
157 {
158 .mailbox = 0x00044,
159 .max_cmds = 1000,
160 .cache_line_size = 0x20,
161 .clear_isr = 0,
162 .iopoll_weight = 64,
163 {
164 .set_interrupt_mask_reg = 0x00010,
165 .clr_interrupt_mask_reg = 0x00018,
166 .clr_interrupt_mask_reg32 = 0x0001C,
167 .sense_interrupt_mask_reg = 0x00010,
168 .sense_interrupt_mask_reg32 = 0x00014,
169 .clr_interrupt_reg = 0x00008,
170 .clr_interrupt_reg32 = 0x0000C,
171 .sense_interrupt_reg = 0x00000,
172 .sense_interrupt_reg32 = 0x00004,
173 .ioarrin_reg = 0x00070,
174 .sense_uproc_interrupt_reg = 0x00020,
175 .sense_uproc_interrupt_reg32 = 0x00024,
176 .set_uproc_interrupt_reg = 0x00020,
177 .set_uproc_interrupt_reg32 = 0x00024,
178 .clr_uproc_interrupt_reg = 0x00028,
179 .clr_uproc_interrupt_reg32 = 0x0002C,
180 .init_feedback_reg = 0x0005C,
181 .dump_addr_reg = 0x00064,
182 .dump_data_reg = 0x00068,
183 .endian_swap_reg = 0x00084
184 }
185 },
186};
187
188static const struct ipr_chip_t ipr_chip[] = {
189 { PCI_VENDOR_ID_MYLEX, PCI_DEVICE_ID_IBM_GEMSTONE, IPR_USE_LSI, IPR_SIS32, IPR_PCI_CFG, &ipr_chip_cfg[0] },
190 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, IPR_USE_LSI, IPR_SIS32, IPR_PCI_CFG, &ipr_chip_cfg[0] },
191 { PCI_VENDOR_ID_ADAPTEC2, PCI_DEVICE_ID_ADAPTEC2_OBSIDIAN, IPR_USE_LSI, IPR_SIS32, IPR_PCI_CFG, &ipr_chip_cfg[0] },
192 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN, IPR_USE_LSI, IPR_SIS32, IPR_PCI_CFG, &ipr_chip_cfg[0] },
193 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN_E, IPR_USE_MSI, IPR_SIS32, IPR_PCI_CFG, &ipr_chip_cfg[0] },
194 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_SNIPE, IPR_USE_LSI, IPR_SIS32, IPR_PCI_CFG, &ipr_chip_cfg[1] },
195 { PCI_VENDOR_ID_ADAPTEC2, PCI_DEVICE_ID_ADAPTEC2_SCAMP, IPR_USE_LSI, IPR_SIS32, IPR_PCI_CFG, &ipr_chip_cfg[1] },
196 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_FPGA_E2, IPR_USE_MSI, IPR_SIS64, IPR_MMIO, &ipr_chip_cfg[2] },
197 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE, IPR_USE_MSI, IPR_SIS64, IPR_MMIO, &ipr_chip_cfg[2] },
198 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_RATTLESNAKE, IPR_USE_MSI, IPR_SIS64, IPR_MMIO, &ipr_chip_cfg[2] }
199};
200
201static int ipr_max_bus_speeds[] = {
202 IPR_80MBs_SCSI_RATE, IPR_U160_SCSI_RATE, IPR_U320_SCSI_RATE
203};
204
205MODULE_AUTHOR("Brian King <brking@us.ibm.com>");
206MODULE_DESCRIPTION("IBM Power RAID SCSI Adapter Driver");
207module_param_named(max_speed, ipr_max_speed, uint, 0);
208MODULE_PARM_DESC(max_speed, "Maximum bus speed (0-2). Default: 1=U160. Speeds: 0=80 MB/s, 1=U160, 2=U320");
209module_param_named(log_level, ipr_log_level, uint, 0);
210MODULE_PARM_DESC(log_level, "Set to 0 - 4 for increasing verbosity of device driver");
211module_param_named(testmode, ipr_testmode, int, 0);
212MODULE_PARM_DESC(testmode, "DANGEROUS!!! Allows unsupported configurations");
213module_param_named(fastfail, ipr_fastfail, int, S_IRUGO | S_IWUSR);
214MODULE_PARM_DESC(fastfail, "Reduce timeouts and retries");
215module_param_named(transop_timeout, ipr_transop_timeout, int, 0);
216MODULE_PARM_DESC(transop_timeout, "Time in seconds to wait for adapter to come operational (default: 300)");
217module_param_named(debug, ipr_debug, int, S_IRUGO | S_IWUSR);
218MODULE_PARM_DESC(debug, "Enable device driver debugging logging. Set to 1 to enable. (default: 0)");
219module_param_named(dual_ioa_raid, ipr_dual_ioa_raid, int, 0);
220MODULE_PARM_DESC(dual_ioa_raid, "Enable dual adapter RAID support. Set to 1 to enable. (default: 1)");
221module_param_named(max_devs, ipr_max_devs, int, 0);
222MODULE_PARM_DESC(max_devs, "Specify the maximum number of physical devices. "
223 "[Default=" __stringify(IPR_DEFAULT_SIS64_DEVS) "]");
224module_param_named(number_of_msix, ipr_number_of_msix, int, 0);
225MODULE_PARM_DESC(number_of_msix, "Specify the number of MSIX interrupts to use on capable adapters (1 - 16). (default:16)");
226module_param_named(fast_reboot, ipr_fast_reboot, int, S_IRUGO | S_IWUSR);
227MODULE_PARM_DESC(fast_reboot, "Skip adapter shutdown during reboot. Set to 1 to enable. (default: 0)");
228MODULE_LICENSE("GPL");
229MODULE_VERSION(IPR_DRIVER_VERSION);
230
231
232static const
233struct ipr_error_table_t ipr_error_table[] = {
234 {0x00000000, 1, IPR_DEFAULT_LOG_LEVEL,
235 "8155: An unknown error was received"},
236 {0x00330000, 0, 0,
237 "Soft underlength error"},
238 {0x005A0000, 0, 0,
239 "Command to be cancelled not found"},
240 {0x00808000, 0, 0,
241 "Qualified success"},
242 {0x01080000, 1, IPR_DEFAULT_LOG_LEVEL,
243 "FFFE: Soft device bus error recovered by the IOA"},
244 {0x01088100, 0, IPR_DEFAULT_LOG_LEVEL,
245 "4101: Soft device bus fabric error"},
246 {0x01100100, 0, IPR_DEFAULT_LOG_LEVEL,
247 "FFFC: Logical block guard error recovered by the device"},
248 {0x01100300, 0, IPR_DEFAULT_LOG_LEVEL,
249 "FFFC: Logical block reference tag error recovered by the device"},
250 {0x01108300, 0, IPR_DEFAULT_LOG_LEVEL,
251 "4171: Recovered scatter list tag / sequence number error"},
252 {0x01109000, 0, IPR_DEFAULT_LOG_LEVEL,
253 "FF3D: Recovered logical block CRC error on IOA to Host transfer"},
254 {0x01109200, 0, IPR_DEFAULT_LOG_LEVEL,
255 "4171: Recovered logical block sequence number error on IOA to Host transfer"},
256 {0x0110A000, 0, IPR_DEFAULT_LOG_LEVEL,
257 "FFFD: Recovered logical block reference tag error detected by the IOA"},
258 {0x0110A100, 0, IPR_DEFAULT_LOG_LEVEL,
259 "FFFD: Logical block guard error recovered by the IOA"},
260 {0x01170600, 0, IPR_DEFAULT_LOG_LEVEL,
261 "FFF9: Device sector reassign successful"},
262 {0x01170900, 0, IPR_DEFAULT_LOG_LEVEL,
263 "FFF7: Media error recovered by device rewrite procedures"},
264 {0x01180200, 0, IPR_DEFAULT_LOG_LEVEL,
265 "7001: IOA sector reassignment successful"},
266 {0x01180500, 0, IPR_DEFAULT_LOG_LEVEL,
267 "FFF9: Soft media error. Sector reassignment recommended"},
268 {0x01180600, 0, IPR_DEFAULT_LOG_LEVEL,
269 "FFF7: Media error recovered by IOA rewrite procedures"},
270 {0x01418000, 0, IPR_DEFAULT_LOG_LEVEL,
271 "FF3D: Soft PCI bus error recovered by the IOA"},
272 {0x01440000, 1, IPR_DEFAULT_LOG_LEVEL,
273 "FFF6: Device hardware error recovered by the IOA"},
274 {0x01448100, 0, IPR_DEFAULT_LOG_LEVEL,
275 "FFF6: Device hardware error recovered by the device"},
276 {0x01448200, 1, IPR_DEFAULT_LOG_LEVEL,
277 "FF3D: Soft IOA error recovered by the IOA"},
278 {0x01448300, 0, IPR_DEFAULT_LOG_LEVEL,
279 "FFFA: Undefined device response recovered by the IOA"},
280 {0x014A0000, 1, IPR_DEFAULT_LOG_LEVEL,
281 "FFF6: Device bus error, message or command phase"},
282 {0x014A8000, 0, IPR_DEFAULT_LOG_LEVEL,
283 "FFFE: Task Management Function failed"},
284 {0x015D0000, 0, IPR_DEFAULT_LOG_LEVEL,
285 "FFF6: Failure prediction threshold exceeded"},
286 {0x015D9200, 0, IPR_DEFAULT_LOG_LEVEL,
287 "8009: Impending cache battery pack failure"},
288 {0x02040100, 0, 0,
289 "Logical Unit in process of becoming ready"},
290 {0x02040200, 0, 0,
291 "Initializing command required"},
292 {0x02040400, 0, 0,
293 "34FF: Disk device format in progress"},
294 {0x02040C00, 0, 0,
295 "Logical unit not accessible, target port in unavailable state"},
296 {0x02048000, 0, IPR_DEFAULT_LOG_LEVEL,
297 "9070: IOA requested reset"},
298 {0x023F0000, 0, 0,
299 "Synchronization required"},
300 {0x02408500, 0, 0,
301 "IOA microcode download required"},
302 {0x02408600, 0, 0,
303 "Device bus connection is prohibited by host"},
304 {0x024E0000, 0, 0,
305 "No ready, IOA shutdown"},
306 {0x025A0000, 0, 0,
307 "Not ready, IOA has been shutdown"},
308 {0x02670100, 0, IPR_DEFAULT_LOG_LEVEL,
309 "3020: Storage subsystem configuration error"},
310 {0x03110B00, 0, 0,
311 "FFF5: Medium error, data unreadable, recommend reassign"},
312 {0x03110C00, 0, 0,
313 "7000: Medium error, data unreadable, do not reassign"},
314 {0x03310000, 0, IPR_DEFAULT_LOG_LEVEL,
315 "FFF3: Disk media format bad"},
316 {0x04050000, 0, IPR_DEFAULT_LOG_LEVEL,
317 "3002: Addressed device failed to respond to selection"},
318 {0x04080000, 1, IPR_DEFAULT_LOG_LEVEL,
319 "3100: Device bus error"},
320 {0x04080100, 0, IPR_DEFAULT_LOG_LEVEL,
321 "3109: IOA timed out a device command"},
322 {0x04088000, 0, 0,
323 "3120: SCSI bus is not operational"},
324 {0x04088100, 0, IPR_DEFAULT_LOG_LEVEL,
325 "4100: Hard device bus fabric error"},
326 {0x04100100, 0, IPR_DEFAULT_LOG_LEVEL,
327 "310C: Logical block guard error detected by the device"},
328 {0x04100300, 0, IPR_DEFAULT_LOG_LEVEL,
329 "310C: Logical block reference tag error detected by the device"},
330 {0x04108300, 1, IPR_DEFAULT_LOG_LEVEL,
331 "4170: Scatter list tag / sequence number error"},
332 {0x04109000, 1, IPR_DEFAULT_LOG_LEVEL,
333 "8150: Logical block CRC error on IOA to Host transfer"},
334 {0x04109200, 1, IPR_DEFAULT_LOG_LEVEL,
335 "4170: Logical block sequence number error on IOA to Host transfer"},
336 {0x0410A000, 0, IPR_DEFAULT_LOG_LEVEL,
337 "310D: Logical block reference tag error detected by the IOA"},
338 {0x0410A100, 0, IPR_DEFAULT_LOG_LEVEL,
339 "310D: Logical block guard error detected by the IOA"},
340 {0x04118000, 0, IPR_DEFAULT_LOG_LEVEL,
341 "9000: IOA reserved area data check"},
342 {0x04118100, 0, IPR_DEFAULT_LOG_LEVEL,
343 "9001: IOA reserved area invalid data pattern"},
344 {0x04118200, 0, IPR_DEFAULT_LOG_LEVEL,
345 "9002: IOA reserved area LRC error"},
346 {0x04118300, 1, IPR_DEFAULT_LOG_LEVEL,
347 "Hardware Error, IOA metadata access error"},
348 {0x04320000, 0, IPR_DEFAULT_LOG_LEVEL,
349 "102E: Out of alternate sectors for disk storage"},
350 {0x04330000, 1, IPR_DEFAULT_LOG_LEVEL,
351 "FFF4: Data transfer underlength error"},
352 {0x04338000, 1, IPR_DEFAULT_LOG_LEVEL,
353 "FFF4: Data transfer overlength error"},
354 {0x043E0100, 0, IPR_DEFAULT_LOG_LEVEL,
355 "3400: Logical unit failure"},
356 {0x04408500, 0, IPR_DEFAULT_LOG_LEVEL,
357 "FFF4: Device microcode is corrupt"},
358 {0x04418000, 1, IPR_DEFAULT_LOG_LEVEL,
359 "8150: PCI bus error"},
360 {0x04430000, 1, 0,
361 "Unsupported device bus message received"},
362 {0x04440000, 1, IPR_DEFAULT_LOG_LEVEL,
363 "FFF4: Disk device problem"},
364 {0x04448200, 1, IPR_DEFAULT_LOG_LEVEL,
365 "8150: Permanent IOA failure"},
366 {0x04448300, 0, IPR_DEFAULT_LOG_LEVEL,
367 "3010: Disk device returned wrong response to IOA"},
368 {0x04448400, 0, IPR_DEFAULT_LOG_LEVEL,
369 "8151: IOA microcode error"},
370 {0x04448500, 0, 0,
371 "Device bus status error"},
372 {0x04448600, 0, IPR_DEFAULT_LOG_LEVEL,
373 "8157: IOA error requiring IOA reset to recover"},
374 {0x04448700, 0, 0,
375 "ATA device status error"},
376 {0x04490000, 0, 0,
377 "Message reject received from the device"},
378 {0x04449200, 0, IPR_DEFAULT_LOG_LEVEL,
379 "8008: A permanent cache battery pack failure occurred"},
380 {0x0444A000, 0, IPR_DEFAULT_LOG_LEVEL,
381 "9090: Disk unit has been modified after the last known status"},
382 {0x0444A200, 0, IPR_DEFAULT_LOG_LEVEL,
383 "9081: IOA detected device error"},
384 {0x0444A300, 0, IPR_DEFAULT_LOG_LEVEL,
385 "9082: IOA detected device error"},
386 {0x044A0000, 1, IPR_DEFAULT_LOG_LEVEL,
387 "3110: Device bus error, message or command phase"},
388 {0x044A8000, 1, IPR_DEFAULT_LOG_LEVEL,
389 "3110: SAS Command / Task Management Function failed"},
390 {0x04670400, 0, IPR_DEFAULT_LOG_LEVEL,
391 "9091: Incorrect hardware configuration change has been detected"},
392 {0x04678000, 0, IPR_DEFAULT_LOG_LEVEL,
393 "9073: Invalid multi-adapter configuration"},
394 {0x04678100, 0, IPR_DEFAULT_LOG_LEVEL,
395 "4010: Incorrect connection between cascaded expanders"},
396 {0x04678200, 0, IPR_DEFAULT_LOG_LEVEL,
397 "4020: Connections exceed IOA design limits"},
398 {0x04678300, 0, IPR_DEFAULT_LOG_LEVEL,
399 "4030: Incorrect multipath connection"},
400 {0x04679000, 0, IPR_DEFAULT_LOG_LEVEL,
401 "4110: Unsupported enclosure function"},
402 {0x04679800, 0, IPR_DEFAULT_LOG_LEVEL,
403 "4120: SAS cable VPD cannot be read"},
404 {0x046E0000, 0, IPR_DEFAULT_LOG_LEVEL,
405 "FFF4: Command to logical unit failed"},
406 {0x05240000, 1, 0,
407 "Illegal request, invalid request type or request packet"},
408 {0x05250000, 0, 0,
409 "Illegal request, invalid resource handle"},
410 {0x05258000, 0, 0,
411 "Illegal request, commands not allowed to this device"},
412 {0x05258100, 0, 0,
413 "Illegal request, command not allowed to a secondary adapter"},
414 {0x05258200, 0, 0,
415 "Illegal request, command not allowed to a non-optimized resource"},
416 {0x05260000, 0, 0,
417 "Illegal request, invalid field in parameter list"},
418 {0x05260100, 0, 0,
419 "Illegal request, parameter not supported"},
420 {0x05260200, 0, 0,
421 "Illegal request, parameter value invalid"},
422 {0x052C0000, 0, 0,
423 "Illegal request, command sequence error"},
424 {0x052C8000, 1, 0,
425 "Illegal request, dual adapter support not enabled"},
426 {0x052C8100, 1, 0,
427 "Illegal request, another cable connector was physically disabled"},
428 {0x054E8000, 1, 0,
429 "Illegal request, inconsistent group id/group count"},
430 {0x06040500, 0, IPR_DEFAULT_LOG_LEVEL,
431 "9031: Array protection temporarily suspended, protection resuming"},
432 {0x06040600, 0, IPR_DEFAULT_LOG_LEVEL,
433 "9040: Array protection temporarily suspended, protection resuming"},
434 {0x060B0100, 0, IPR_DEFAULT_LOG_LEVEL,
435 "4080: IOA exceeded maximum operating temperature"},
436 {0x060B8000, 0, IPR_DEFAULT_LOG_LEVEL,
437 "4085: Service required"},
438 {0x06288000, 0, IPR_DEFAULT_LOG_LEVEL,
439 "3140: Device bus not ready to ready transition"},
440 {0x06290000, 0, IPR_DEFAULT_LOG_LEVEL,
441 "FFFB: SCSI bus was reset"},
442 {0x06290500, 0, 0,
443 "FFFE: SCSI bus transition to single ended"},
444 {0x06290600, 0, 0,
445 "FFFE: SCSI bus transition to LVD"},
446 {0x06298000, 0, IPR_DEFAULT_LOG_LEVEL,
447 "FFFB: SCSI bus was reset by another initiator"},
448 {0x063F0300, 0, IPR_DEFAULT_LOG_LEVEL,
449 "3029: A device replacement has occurred"},
450 {0x063F8300, 0, IPR_DEFAULT_LOG_LEVEL,
451 "4102: Device bus fabric performance degradation"},
452 {0x064C8000, 0, IPR_DEFAULT_LOG_LEVEL,
453 "9051: IOA cache data exists for a missing or failed device"},
454 {0x064C8100, 0, IPR_DEFAULT_LOG_LEVEL,
455 "9055: Auxiliary cache IOA contains cache data needed by the primary IOA"},
456 {0x06670100, 0, IPR_DEFAULT_LOG_LEVEL,
457 "9025: Disk unit is not supported at its physical location"},
458 {0x06670600, 0, IPR_DEFAULT_LOG_LEVEL,
459 "3020: IOA detected a SCSI bus configuration error"},
460 {0x06678000, 0, IPR_DEFAULT_LOG_LEVEL,
461 "3150: SCSI bus configuration error"},
462 {0x06678100, 0, IPR_DEFAULT_LOG_LEVEL,
463 "9074: Asymmetric advanced function disk configuration"},
464 {0x06678300, 0, IPR_DEFAULT_LOG_LEVEL,
465 "4040: Incomplete multipath connection between IOA and enclosure"},
466 {0x06678400, 0, IPR_DEFAULT_LOG_LEVEL,
467 "4041: Incomplete multipath connection between enclosure and device"},
468 {0x06678500, 0, IPR_DEFAULT_LOG_LEVEL,
469 "9075: Incomplete multipath connection between IOA and remote IOA"},
470 {0x06678600, 0, IPR_DEFAULT_LOG_LEVEL,
471 "9076: Configuration error, missing remote IOA"},
472 {0x06679100, 0, IPR_DEFAULT_LOG_LEVEL,
473 "4050: Enclosure does not support a required multipath function"},
474 {0x06679800, 0, IPR_DEFAULT_LOG_LEVEL,
475 "4121: Configuration error, required cable is missing"},
476 {0x06679900, 0, IPR_DEFAULT_LOG_LEVEL,
477 "4122: Cable is not plugged into the correct location on remote IOA"},
478 {0x06679A00, 0, IPR_DEFAULT_LOG_LEVEL,
479 "4123: Configuration error, invalid cable vital product data"},
480 {0x06679B00, 0, IPR_DEFAULT_LOG_LEVEL,
481 "4124: Configuration error, both cable ends are plugged into the same IOA"},
482 {0x06690000, 0, IPR_DEFAULT_LOG_LEVEL,
483 "4070: Logically bad block written on device"},
484 {0x06690200, 0, IPR_DEFAULT_LOG_LEVEL,
485 "9041: Array protection temporarily suspended"},
486 {0x06698200, 0, IPR_DEFAULT_LOG_LEVEL,
487 "9042: Corrupt array parity detected on specified device"},
488 {0x066B0200, 0, IPR_DEFAULT_LOG_LEVEL,
489 "9030: Array no longer protected due to missing or failed disk unit"},
490 {0x066B8000, 0, IPR_DEFAULT_LOG_LEVEL,
491 "9071: Link operational transition"},
492 {0x066B8100, 0, IPR_DEFAULT_LOG_LEVEL,
493 "9072: Link not operational transition"},
494 {0x066B8200, 0, IPR_DEFAULT_LOG_LEVEL,
495 "9032: Array exposed but still protected"},
496 {0x066B8300, 0, IPR_DEFAULT_LOG_LEVEL + 1,
497 "70DD: Device forced failed by disrupt device command"},
498 {0x066B9100, 0, IPR_DEFAULT_LOG_LEVEL,
499 "4061: Multipath redundancy level got better"},
500 {0x066B9200, 0, IPR_DEFAULT_LOG_LEVEL,
501 "4060: Multipath redundancy level got worse"},
502 {0x06808100, 0, IPR_DEFAULT_LOG_LEVEL,
503 "9083: Device raw mode enabled"},
504 {0x06808200, 0, IPR_DEFAULT_LOG_LEVEL,
505 "9084: Device raw mode disabled"},
506 {0x07270000, 0, 0,
507 "Failure due to other device"},
508 {0x07278000, 0, IPR_DEFAULT_LOG_LEVEL,
509 "9008: IOA does not support functions expected by devices"},
510 {0x07278100, 0, IPR_DEFAULT_LOG_LEVEL,
511 "9010: Cache data associated with attached devices cannot be found"},
512 {0x07278200, 0, IPR_DEFAULT_LOG_LEVEL,
513 "9011: Cache data belongs to devices other than those attached"},
514 {0x07278400, 0, IPR_DEFAULT_LOG_LEVEL,
515 "9020: Array missing 2 or more devices with only 1 device present"},
516 {0x07278500, 0, IPR_DEFAULT_LOG_LEVEL,
517 "9021: Array missing 2 or more devices with 2 or more devices present"},
518 {0x07278600, 0, IPR_DEFAULT_LOG_LEVEL,
519 "9022: Exposed array is missing a required device"},
520 {0x07278700, 0, IPR_DEFAULT_LOG_LEVEL,
521 "9023: Array member(s) not at required physical locations"},
522 {0x07278800, 0, IPR_DEFAULT_LOG_LEVEL,
523 "9024: Array not functional due to present hardware configuration"},
524 {0x07278900, 0, IPR_DEFAULT_LOG_LEVEL,
525 "9026: Array not functional due to present hardware configuration"},
526 {0x07278A00, 0, IPR_DEFAULT_LOG_LEVEL,
527 "9027: Array is missing a device and parity is out of sync"},
528 {0x07278B00, 0, IPR_DEFAULT_LOG_LEVEL,
529 "9028: Maximum number of arrays already exist"},
530 {0x07278C00, 0, IPR_DEFAULT_LOG_LEVEL,
531 "9050: Required cache data cannot be located for a disk unit"},
532 {0x07278D00, 0, IPR_DEFAULT_LOG_LEVEL,
533 "9052: Cache data exists for a device that has been modified"},
534 {0x07278F00, 0, IPR_DEFAULT_LOG_LEVEL,
535 "9054: IOA resources not available due to previous problems"},
536 {0x07279100, 0, IPR_DEFAULT_LOG_LEVEL,
537 "9092: Disk unit requires initialization before use"},
538 {0x07279200, 0, IPR_DEFAULT_LOG_LEVEL,
539 "9029: Incorrect hardware configuration change has been detected"},
540 {0x07279600, 0, IPR_DEFAULT_LOG_LEVEL,
541 "9060: One or more disk pairs are missing from an array"},
542 {0x07279700, 0, IPR_DEFAULT_LOG_LEVEL,
543 "9061: One or more disks are missing from an array"},
544 {0x07279800, 0, IPR_DEFAULT_LOG_LEVEL,
545 "9062: One or more disks are missing from an array"},
546 {0x07279900, 0, IPR_DEFAULT_LOG_LEVEL,
547 "9063: Maximum number of functional arrays has been exceeded"},
548 {0x07279A00, 0, 0,
549 "Data protect, other volume set problem"},
550 {0x0B260000, 0, 0,
551 "Aborted command, invalid descriptor"},
552 {0x0B3F9000, 0, 0,
553 "Target operating conditions have changed, dual adapter takeover"},
554 {0x0B530200, 0, 0,
555 "Aborted command, medium removal prevented"},
556 {0x0B5A0000, 0, 0,
557 "Command terminated by host"},
558 {0x0B5B8000, 0, 0,
559 "Aborted command, command terminated by host"}
560};
561
562static const struct ipr_ses_table_entry ipr_ses_table[] = {
563 { "2104-DL1 ", "XXXXXXXXXXXXXXXX", 80 },
564 { "2104-TL1 ", "XXXXXXXXXXXXXXXX", 80 },
565 { "HSBP07M P U2SCSI", "XXXXXXXXXXXXXXXX", 80 },
566 { "HSBP05M P U2SCSI", "XXXXXXXXXXXXXXXX", 80 },
567 { "HSBP05M S U2SCSI", "XXXXXXXXXXXXXXXX", 80 },
568 { "HSBP06E ASU2SCSI", "XXXXXXXXXXXXXXXX", 80 },
569 { "2104-DU3 ", "XXXXXXXXXXXXXXXX", 160 },
570 { "2104-TU3 ", "XXXXXXXXXXXXXXXX", 160 },
571 { "HSBP04C RSU2SCSI", "XXXXXXX*XXXXXXXX", 160 },
572 { "HSBP06E RSU2SCSI", "XXXXXXX*XXXXXXXX", 160 },
573 { "St V1S2 ", "XXXXXXXXXXXXXXXX", 160 },
574 { "HSBPD4M PU3SCSI", "XXXXXXX*XXXXXXXX", 160 },
575 { "VSBPD1H U3SCSI", "XXXXXXX*XXXXXXXX", 160 }
576};
577
578
579
580
581static int ipr_reset_alert(struct ipr_cmnd *);
582static void ipr_process_ccn(struct ipr_cmnd *);
583static void ipr_process_error(struct ipr_cmnd *);
584static void ipr_reset_ioa_job(struct ipr_cmnd *);
585static void ipr_initiate_ioa_reset(struct ipr_ioa_cfg *,
586 enum ipr_shutdown_type);
587
588#ifdef CONFIG_SCSI_IPR_TRACE
589
590
591
592
593
594
595
596
597
598static void ipr_trc_hook(struct ipr_cmnd *ipr_cmd,
599 u8 type, u32 add_data)
600{
601 struct ipr_trace_entry *trace_entry;
602 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
603 unsigned int trace_index;
604
605 trace_index = atomic_add_return(1, &ioa_cfg->trace_index) & IPR_TRACE_INDEX_MASK;
606 trace_entry = &ioa_cfg->trace[trace_index];
607 trace_entry->time = jiffies;
608 trace_entry->op_code = ipr_cmd->ioarcb.cmd_pkt.cdb[0];
609 trace_entry->type = type;
610 if (ipr_cmd->ioa_cfg->sis64)
611 trace_entry->ata_op_code = ipr_cmd->i.ata_ioadl.regs.command;
612 else
613 trace_entry->ata_op_code = ipr_cmd->ioarcb.u.add_data.u.regs.command;
614 trace_entry->cmd_index = ipr_cmd->cmd_index & 0xff;
615 trace_entry->res_handle = ipr_cmd->ioarcb.res_handle;
616 trace_entry->u.add_data = add_data;
617 wmb();
618}
619#else
620#define ipr_trc_hook(ipr_cmd, type, add_data) do { } while (0)
621#endif
622
623
624
625
626
627
628
629
630static void ipr_lock_and_done(struct ipr_cmnd *ipr_cmd)
631{
632 unsigned long lock_flags;
633 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
634
635 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
636 ipr_cmd->done(ipr_cmd);
637 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
638}
639
640
641
642
643
644
645
646
647static void ipr_reinit_ipr_cmnd(struct ipr_cmnd *ipr_cmd)
648{
649 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
650 struct ipr_ioasa *ioasa = &ipr_cmd->s.ioasa;
651 struct ipr_ioasa64 *ioasa64 = &ipr_cmd->s.ioasa64;
652 dma_addr_t dma_addr = ipr_cmd->dma_addr;
653 int hrrq_id;
654
655 hrrq_id = ioarcb->cmd_pkt.hrrq_id;
656 memset(&ioarcb->cmd_pkt, 0, sizeof(struct ipr_cmd_pkt));
657 ioarcb->cmd_pkt.hrrq_id = hrrq_id;
658 ioarcb->data_transfer_length = 0;
659 ioarcb->read_data_transfer_length = 0;
660 ioarcb->ioadl_len = 0;
661 ioarcb->read_ioadl_len = 0;
662
663 if (ipr_cmd->ioa_cfg->sis64) {
664 ioarcb->u.sis64_addr_data.data_ioadl_addr =
665 cpu_to_be64(dma_addr + offsetof(struct ipr_cmnd, i.ioadl64));
666 ioasa64->u.gata.status = 0;
667 } else {
668 ioarcb->write_ioadl_addr =
669 cpu_to_be32(dma_addr + offsetof(struct ipr_cmnd, i.ioadl));
670 ioarcb->read_ioadl_addr = ioarcb->write_ioadl_addr;
671 ioasa->u.gata.status = 0;
672 }
673
674 ioasa->hdr.ioasc = 0;
675 ioasa->hdr.residual_data_len = 0;
676 ipr_cmd->scsi_cmd = NULL;
677 ipr_cmd->qc = NULL;
678 ipr_cmd->sense_buffer[0] = 0;
679 ipr_cmd->dma_use_sg = 0;
680}
681
682
683
684
685
686
687
688
689static void ipr_init_ipr_cmnd(struct ipr_cmnd *ipr_cmd,
690 void (*fast_done) (struct ipr_cmnd *))
691{
692 ipr_reinit_ipr_cmnd(ipr_cmd);
693 ipr_cmd->u.scratch = 0;
694 ipr_cmd->sibling = NULL;
695 ipr_cmd->eh_comp = NULL;
696 ipr_cmd->fast_done = fast_done;
697 init_timer(&ipr_cmd->timer);
698}
699
700
701
702
703
704
705
706
707static
708struct ipr_cmnd *__ipr_get_free_ipr_cmnd(struct ipr_hrr_queue *hrrq)
709{
710 struct ipr_cmnd *ipr_cmd = NULL;
711
712 if (likely(!list_empty(&hrrq->hrrq_free_q))) {
713 ipr_cmd = list_entry(hrrq->hrrq_free_q.next,
714 struct ipr_cmnd, queue);
715 list_del(&ipr_cmd->queue);
716 }
717
718
719 return ipr_cmd;
720}
721
722
723
724
725
726
727
728
729static
730struct ipr_cmnd *ipr_get_free_ipr_cmnd(struct ipr_ioa_cfg *ioa_cfg)
731{
732 struct ipr_cmnd *ipr_cmd =
733 __ipr_get_free_ipr_cmnd(&ioa_cfg->hrrq[IPR_INIT_HRRQ]);
734 ipr_init_ipr_cmnd(ipr_cmd, ipr_lock_and_done);
735 return ipr_cmd;
736}
737
738
739
740
741
742
743
744
745
746
747
748
749static void ipr_mask_and_clear_interrupts(struct ipr_ioa_cfg *ioa_cfg,
750 u32 clr_ints)
751{
752 volatile u32 int_reg;
753 int i;
754
755
756 for (i = 0; i < ioa_cfg->hrrq_num; i++) {
757 spin_lock(&ioa_cfg->hrrq[i]._lock);
758 ioa_cfg->hrrq[i].allow_interrupts = 0;
759 spin_unlock(&ioa_cfg->hrrq[i]._lock);
760 }
761 wmb();
762
763
764 if (ioa_cfg->sis64)
765 writeq(~0, ioa_cfg->regs.set_interrupt_mask_reg);
766 else
767 writel(~0, ioa_cfg->regs.set_interrupt_mask_reg);
768
769
770 if (ioa_cfg->sis64)
771 writel(~0, ioa_cfg->regs.clr_interrupt_reg);
772 writel(clr_ints, ioa_cfg->regs.clr_interrupt_reg32);
773 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg);
774}
775
776
777
778
779
780
781
782
783static int ipr_save_pcix_cmd_reg(struct ipr_ioa_cfg *ioa_cfg)
784{
785 int pcix_cmd_reg = pci_find_capability(ioa_cfg->pdev, PCI_CAP_ID_PCIX);
786
787 if (pcix_cmd_reg == 0)
788 return 0;
789
790 if (pci_read_config_word(ioa_cfg->pdev, pcix_cmd_reg + PCI_X_CMD,
791 &ioa_cfg->saved_pcix_cmd_reg) != PCIBIOS_SUCCESSFUL) {
792 dev_err(&ioa_cfg->pdev->dev, "Failed to save PCI-X command register\n");
793 return -EIO;
794 }
795
796 ioa_cfg->saved_pcix_cmd_reg |= PCI_X_CMD_DPERR_E | PCI_X_CMD_ERO;
797 return 0;
798}
799
800
801
802
803
804
805
806
807static int ipr_set_pcix_cmd_reg(struct ipr_ioa_cfg *ioa_cfg)
808{
809 int pcix_cmd_reg = pci_find_capability(ioa_cfg->pdev, PCI_CAP_ID_PCIX);
810
811 if (pcix_cmd_reg) {
812 if (pci_write_config_word(ioa_cfg->pdev, pcix_cmd_reg + PCI_X_CMD,
813 ioa_cfg->saved_pcix_cmd_reg) != PCIBIOS_SUCCESSFUL) {
814 dev_err(&ioa_cfg->pdev->dev, "Failed to setup PCI-X command register\n");
815 return -EIO;
816 }
817 }
818
819 return 0;
820}
821
822
823
824
825
826
827
828
829
830
831
832static void ipr_sata_eh_done(struct ipr_cmnd *ipr_cmd)
833{
834 struct ata_queued_cmd *qc = ipr_cmd->qc;
835 struct ipr_sata_port *sata_port = qc->ap->private_data;
836
837 qc->err_mask |= AC_ERR_OTHER;
838 sata_port->ioasa.status |= ATA_BUSY;
839 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
840 ata_qc_complete(qc);
841}
842
843
844
845
846
847
848
849
850
851
852
853static void ipr_scsi_eh_done(struct ipr_cmnd *ipr_cmd)
854{
855 struct scsi_cmnd *scsi_cmd = ipr_cmd->scsi_cmd;
856
857 scsi_cmd->result |= (DID_ERROR << 16);
858
859 scsi_dma_unmap(ipr_cmd->scsi_cmd);
860 scsi_cmd->scsi_done(scsi_cmd);
861 if (ipr_cmd->eh_comp)
862 complete(ipr_cmd->eh_comp);
863 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
864}
865
866
867
868
869
870
871
872
873
874
875static void ipr_fail_all_ops(struct ipr_ioa_cfg *ioa_cfg)
876{
877 struct ipr_cmnd *ipr_cmd, *temp;
878 struct ipr_hrr_queue *hrrq;
879
880 ENTER;
881 for_each_hrrq(hrrq, ioa_cfg) {
882 spin_lock(&hrrq->_lock);
883 list_for_each_entry_safe(ipr_cmd,
884 temp, &hrrq->hrrq_pending_q, queue) {
885 list_del(&ipr_cmd->queue);
886
887 ipr_cmd->s.ioasa.hdr.ioasc =
888 cpu_to_be32(IPR_IOASC_IOA_WAS_RESET);
889 ipr_cmd->s.ioasa.hdr.ilid =
890 cpu_to_be32(IPR_DRIVER_ILID);
891
892 if (ipr_cmd->scsi_cmd)
893 ipr_cmd->done = ipr_scsi_eh_done;
894 else if (ipr_cmd->qc)
895 ipr_cmd->done = ipr_sata_eh_done;
896
897 ipr_trc_hook(ipr_cmd, IPR_TRACE_FINISH,
898 IPR_IOASC_IOA_WAS_RESET);
899 del_timer(&ipr_cmd->timer);
900 ipr_cmd->done(ipr_cmd);
901 }
902 spin_unlock(&hrrq->_lock);
903 }
904 LEAVE;
905}
906
907
908
909
910
911
912
913
914
915
916
917
918static void ipr_send_command(struct ipr_cmnd *ipr_cmd)
919{
920 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
921 dma_addr_t send_dma_addr = ipr_cmd->dma_addr;
922
923 if (ioa_cfg->sis64) {
924
925 send_dma_addr |= 0x1;
926
927
928
929 if (ipr_cmd->dma_use_sg * sizeof(struct ipr_ioadl64_desc) > 128 )
930 send_dma_addr |= 0x4;
931 writeq(send_dma_addr, ioa_cfg->regs.ioarrin_reg);
932 } else
933 writel(send_dma_addr, ioa_cfg->regs.ioarrin_reg);
934}
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949static void ipr_do_req(struct ipr_cmnd *ipr_cmd,
950 void (*done) (struct ipr_cmnd *),
951 void (*timeout_func) (struct ipr_cmnd *), u32 timeout)
952{
953 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_pending_q);
954
955 ipr_cmd->done = done;
956
957 ipr_cmd->timer.data = (unsigned long) ipr_cmd;
958 ipr_cmd->timer.expires = jiffies + timeout;
959 ipr_cmd->timer.function = (void (*)(unsigned long))timeout_func;
960
961 add_timer(&ipr_cmd->timer);
962
963 ipr_trc_hook(ipr_cmd, IPR_TRACE_START, 0);
964
965 ipr_send_command(ipr_cmd);
966}
967
968
969
970
971
972
973
974
975
976
977
978static void ipr_internal_cmd_done(struct ipr_cmnd *ipr_cmd)
979{
980 if (ipr_cmd->sibling)
981 ipr_cmd->sibling = NULL;
982 else
983 complete(&ipr_cmd->completion);
984}
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999static void ipr_init_ioadl(struct ipr_cmnd *ipr_cmd, dma_addr_t dma_addr,
1000 u32 len, int flags)
1001{
1002 struct ipr_ioadl_desc *ioadl = ipr_cmd->i.ioadl;
1003 struct ipr_ioadl64_desc *ioadl64 = ipr_cmd->i.ioadl64;
1004
1005 ipr_cmd->dma_use_sg = 1;
1006
1007 if (ipr_cmd->ioa_cfg->sis64) {
1008 ioadl64->flags = cpu_to_be32(flags);
1009 ioadl64->data_len = cpu_to_be32(len);
1010 ioadl64->address = cpu_to_be64(dma_addr);
1011
1012 ipr_cmd->ioarcb.ioadl_len =
1013 cpu_to_be32(sizeof(struct ipr_ioadl64_desc));
1014 ipr_cmd->ioarcb.data_transfer_length = cpu_to_be32(len);
1015 } else {
1016 ioadl->flags_and_data_len = cpu_to_be32(flags | len);
1017 ioadl->address = cpu_to_be32(dma_addr);
1018
1019 if (flags == IPR_IOADL_FLAGS_READ_LAST) {
1020 ipr_cmd->ioarcb.read_ioadl_len =
1021 cpu_to_be32(sizeof(struct ipr_ioadl_desc));
1022 ipr_cmd->ioarcb.read_data_transfer_length = cpu_to_be32(len);
1023 } else {
1024 ipr_cmd->ioarcb.ioadl_len =
1025 cpu_to_be32(sizeof(struct ipr_ioadl_desc));
1026 ipr_cmd->ioarcb.data_transfer_length = cpu_to_be32(len);
1027 }
1028 }
1029}
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040static void ipr_send_blocking_cmd(struct ipr_cmnd *ipr_cmd,
1041 void (*timeout_func) (struct ipr_cmnd *ipr_cmd),
1042 u32 timeout)
1043{
1044 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
1045
1046 init_completion(&ipr_cmd->completion);
1047 ipr_do_req(ipr_cmd, ipr_internal_cmd_done, timeout_func, timeout);
1048
1049 spin_unlock_irq(ioa_cfg->host->host_lock);
1050 wait_for_completion(&ipr_cmd->completion);
1051 spin_lock_irq(ioa_cfg->host->host_lock);
1052}
1053
1054static int ipr_get_hrrq_index(struct ipr_ioa_cfg *ioa_cfg)
1055{
1056 unsigned int hrrq;
1057
1058 if (ioa_cfg->hrrq_num == 1)
1059 hrrq = 0;
1060 else {
1061 hrrq = atomic_add_return(1, &ioa_cfg->hrrq_index);
1062 hrrq = (hrrq % (ioa_cfg->hrrq_num - 1)) + 1;
1063 }
1064 return hrrq;
1065}
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080static void ipr_send_hcam(struct ipr_ioa_cfg *ioa_cfg, u8 type,
1081 struct ipr_hostrcb *hostrcb)
1082{
1083 struct ipr_cmnd *ipr_cmd;
1084 struct ipr_ioarcb *ioarcb;
1085
1086 if (ioa_cfg->hrrq[IPR_INIT_HRRQ].allow_cmds) {
1087 ipr_cmd = ipr_get_free_ipr_cmnd(ioa_cfg);
1088 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_pending_q);
1089 list_add_tail(&hostrcb->queue, &ioa_cfg->hostrcb_pending_q);
1090
1091 ipr_cmd->u.hostrcb = hostrcb;
1092 ioarcb = &ipr_cmd->ioarcb;
1093
1094 ioarcb->res_handle = cpu_to_be32(IPR_IOA_RES_HANDLE);
1095 ioarcb->cmd_pkt.request_type = IPR_RQTYPE_HCAM;
1096 ioarcb->cmd_pkt.cdb[0] = IPR_HOST_CONTROLLED_ASYNC;
1097 ioarcb->cmd_pkt.cdb[1] = type;
1098 ioarcb->cmd_pkt.cdb[7] = (sizeof(hostrcb->hcam) >> 8) & 0xff;
1099 ioarcb->cmd_pkt.cdb[8] = sizeof(hostrcb->hcam) & 0xff;
1100
1101 ipr_init_ioadl(ipr_cmd, hostrcb->hostrcb_dma,
1102 sizeof(hostrcb->hcam), IPR_IOADL_FLAGS_READ_LAST);
1103
1104 if (type == IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE)
1105 ipr_cmd->done = ipr_process_ccn;
1106 else
1107 ipr_cmd->done = ipr_process_error;
1108
1109 ipr_trc_hook(ipr_cmd, IPR_TRACE_START, IPR_IOA_RES_ADDR);
1110
1111 ipr_send_command(ipr_cmd);
1112 } else {
1113 list_add_tail(&hostrcb->queue, &ioa_cfg->hostrcb_free_q);
1114 }
1115}
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125static void ipr_update_ata_class(struct ipr_resource_entry *res, unsigned int proto)
1126{
1127 switch (proto) {
1128 case IPR_PROTO_SATA:
1129 case IPR_PROTO_SAS_STP:
1130 res->ata_class = ATA_DEV_ATA;
1131 break;
1132 case IPR_PROTO_SATA_ATAPI:
1133 case IPR_PROTO_SAS_STP_ATAPI:
1134 res->ata_class = ATA_DEV_ATAPI;
1135 break;
1136 default:
1137 res->ata_class = ATA_DEV_UNKNOWN;
1138 break;
1139 };
1140}
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150static void ipr_init_res_entry(struct ipr_resource_entry *res,
1151 struct ipr_config_table_entry_wrapper *cfgtew)
1152{
1153 int found = 0;
1154 unsigned int proto;
1155 struct ipr_ioa_cfg *ioa_cfg = res->ioa_cfg;
1156 struct ipr_resource_entry *gscsi_res = NULL;
1157
1158 res->needs_sync_complete = 0;
1159 res->in_erp = 0;
1160 res->add_to_ml = 0;
1161 res->del_from_ml = 0;
1162 res->resetting_device = 0;
1163 res->reset_occurred = 0;
1164 res->sdev = NULL;
1165 res->sata_port = NULL;
1166
1167 if (ioa_cfg->sis64) {
1168 proto = cfgtew->u.cfgte64->proto;
1169 res->flags = be16_to_cpu(cfgtew->u.cfgte64->flags);
1170 res->res_flags = be16_to_cpu(cfgtew->u.cfgte64->res_flags);
1171 res->qmodel = IPR_QUEUEING_MODEL64(res);
1172 res->type = cfgtew->u.cfgte64->res_type;
1173
1174 memcpy(res->res_path, &cfgtew->u.cfgte64->res_path,
1175 sizeof(res->res_path));
1176
1177 res->bus = 0;
1178 memcpy(&res->dev_lun.scsi_lun, &cfgtew->u.cfgte64->lun,
1179 sizeof(res->dev_lun.scsi_lun));
1180 res->lun = scsilun_to_int(&res->dev_lun);
1181
1182 if (res->type == IPR_RES_TYPE_GENERIC_SCSI) {
1183 list_for_each_entry(gscsi_res, &ioa_cfg->used_res_q, queue) {
1184 if (gscsi_res->dev_id == cfgtew->u.cfgte64->dev_id) {
1185 found = 1;
1186 res->target = gscsi_res->target;
1187 break;
1188 }
1189 }
1190 if (!found) {
1191 res->target = find_first_zero_bit(ioa_cfg->target_ids,
1192 ioa_cfg->max_devs_supported);
1193 set_bit(res->target, ioa_cfg->target_ids);
1194 }
1195 } else if (res->type == IPR_RES_TYPE_IOAFP) {
1196 res->bus = IPR_IOAFP_VIRTUAL_BUS;
1197 res->target = 0;
1198 } else if (res->type == IPR_RES_TYPE_ARRAY) {
1199 res->bus = IPR_ARRAY_VIRTUAL_BUS;
1200 res->target = find_first_zero_bit(ioa_cfg->array_ids,
1201 ioa_cfg->max_devs_supported);
1202 set_bit(res->target, ioa_cfg->array_ids);
1203 } else if (res->type == IPR_RES_TYPE_VOLUME_SET) {
1204 res->bus = IPR_VSET_VIRTUAL_BUS;
1205 res->target = find_first_zero_bit(ioa_cfg->vset_ids,
1206 ioa_cfg->max_devs_supported);
1207 set_bit(res->target, ioa_cfg->vset_ids);
1208 } else {
1209 res->target = find_first_zero_bit(ioa_cfg->target_ids,
1210 ioa_cfg->max_devs_supported);
1211 set_bit(res->target, ioa_cfg->target_ids);
1212 }
1213 } else {
1214 proto = cfgtew->u.cfgte->proto;
1215 res->qmodel = IPR_QUEUEING_MODEL(res);
1216 res->flags = cfgtew->u.cfgte->flags;
1217 if (res->flags & IPR_IS_IOA_RESOURCE)
1218 res->type = IPR_RES_TYPE_IOAFP;
1219 else
1220 res->type = cfgtew->u.cfgte->rsvd_subtype & 0x0f;
1221
1222 res->bus = cfgtew->u.cfgte->res_addr.bus;
1223 res->target = cfgtew->u.cfgte->res_addr.target;
1224 res->lun = cfgtew->u.cfgte->res_addr.lun;
1225 res->lun_wwn = get_unaligned_be64(cfgtew->u.cfgte->lun_wwn);
1226 }
1227
1228 ipr_update_ata_class(res, proto);
1229}
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239static int ipr_is_same_device(struct ipr_resource_entry *res,
1240 struct ipr_config_table_entry_wrapper *cfgtew)
1241{
1242 if (res->ioa_cfg->sis64) {
1243 if (!memcmp(&res->dev_id, &cfgtew->u.cfgte64->dev_id,
1244 sizeof(cfgtew->u.cfgte64->dev_id)) &&
1245 !memcmp(&res->dev_lun.scsi_lun, &cfgtew->u.cfgte64->lun,
1246 sizeof(cfgtew->u.cfgte64->lun))) {
1247 return 1;
1248 }
1249 } else {
1250 if (res->bus == cfgtew->u.cfgte->res_addr.bus &&
1251 res->target == cfgtew->u.cfgte->res_addr.target &&
1252 res->lun == cfgtew->u.cfgte->res_addr.lun)
1253 return 1;
1254 }
1255
1256 return 0;
1257}
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268static char *__ipr_format_res_path(u8 *res_path, char *buffer, int len)
1269{
1270 int i;
1271 char *p = buffer;
1272
1273 *p = '\0';
1274 p += snprintf(p, buffer + len - p, "%02X", res_path[0]);
1275 for (i = 1; res_path[i] != 0xff && ((i * 3) < len); i++)
1276 p += snprintf(p, buffer + len - p, "-%02X", res_path[i]);
1277
1278 return buffer;
1279}
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291static char *ipr_format_res_path(struct ipr_ioa_cfg *ioa_cfg,
1292 u8 *res_path, char *buffer, int len)
1293{
1294 char *p = buffer;
1295
1296 *p = '\0';
1297 p += snprintf(p, buffer + len - p, "%d/", ioa_cfg->host->host_no);
1298 __ipr_format_res_path(res_path, p, len - (buffer - p));
1299 return buffer;
1300}
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310static void ipr_update_res_entry(struct ipr_resource_entry *res,
1311 struct ipr_config_table_entry_wrapper *cfgtew)
1312{
1313 char buffer[IPR_MAX_RES_PATH_LENGTH];
1314 unsigned int proto;
1315 int new_path = 0;
1316
1317 if (res->ioa_cfg->sis64) {
1318 res->flags = be16_to_cpu(cfgtew->u.cfgte64->flags);
1319 res->res_flags = be16_to_cpu(cfgtew->u.cfgte64->res_flags);
1320 res->type = cfgtew->u.cfgte64->res_type;
1321
1322 memcpy(&res->std_inq_data, &cfgtew->u.cfgte64->std_inq_data,
1323 sizeof(struct ipr_std_inq_data));
1324
1325 res->qmodel = IPR_QUEUEING_MODEL64(res);
1326 proto = cfgtew->u.cfgte64->proto;
1327 res->res_handle = cfgtew->u.cfgte64->res_handle;
1328 res->dev_id = cfgtew->u.cfgte64->dev_id;
1329
1330 memcpy(&res->dev_lun.scsi_lun, &cfgtew->u.cfgte64->lun,
1331 sizeof(res->dev_lun.scsi_lun));
1332
1333 if (memcmp(res->res_path, &cfgtew->u.cfgte64->res_path,
1334 sizeof(res->res_path))) {
1335 memcpy(res->res_path, &cfgtew->u.cfgte64->res_path,
1336 sizeof(res->res_path));
1337 new_path = 1;
1338 }
1339
1340 if (res->sdev && new_path)
1341 sdev_printk(KERN_INFO, res->sdev, "Resource path: %s\n",
1342 ipr_format_res_path(res->ioa_cfg,
1343 res->res_path, buffer, sizeof(buffer)));
1344 } else {
1345 res->flags = cfgtew->u.cfgte->flags;
1346 if (res->flags & IPR_IS_IOA_RESOURCE)
1347 res->type = IPR_RES_TYPE_IOAFP;
1348 else
1349 res->type = cfgtew->u.cfgte->rsvd_subtype & 0x0f;
1350
1351 memcpy(&res->std_inq_data, &cfgtew->u.cfgte->std_inq_data,
1352 sizeof(struct ipr_std_inq_data));
1353
1354 res->qmodel = IPR_QUEUEING_MODEL(res);
1355 proto = cfgtew->u.cfgte->proto;
1356 res->res_handle = cfgtew->u.cfgte->res_handle;
1357 }
1358
1359 ipr_update_ata_class(res, proto);
1360}
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371static void ipr_clear_res_target(struct ipr_resource_entry *res)
1372{
1373 struct ipr_resource_entry *gscsi_res = NULL;
1374 struct ipr_ioa_cfg *ioa_cfg = res->ioa_cfg;
1375
1376 if (!ioa_cfg->sis64)
1377 return;
1378
1379 if (res->bus == IPR_ARRAY_VIRTUAL_BUS)
1380 clear_bit(res->target, ioa_cfg->array_ids);
1381 else if (res->bus == IPR_VSET_VIRTUAL_BUS)
1382 clear_bit(res->target, ioa_cfg->vset_ids);
1383 else if (res->bus == 0 && res->type == IPR_RES_TYPE_GENERIC_SCSI) {
1384 list_for_each_entry(gscsi_res, &ioa_cfg->used_res_q, queue)
1385 if (gscsi_res->dev_id == res->dev_id && gscsi_res != res)
1386 return;
1387 clear_bit(res->target, ioa_cfg->target_ids);
1388
1389 } else if (res->bus == 0)
1390 clear_bit(res->target, ioa_cfg->target_ids);
1391}
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401static void ipr_handle_config_change(struct ipr_ioa_cfg *ioa_cfg,
1402 struct ipr_hostrcb *hostrcb)
1403{
1404 struct ipr_resource_entry *res = NULL;
1405 struct ipr_config_table_entry_wrapper cfgtew;
1406 __be32 cc_res_handle;
1407
1408 u32 is_ndn = 1;
1409
1410 if (ioa_cfg->sis64) {
1411 cfgtew.u.cfgte64 = &hostrcb->hcam.u.ccn.u.cfgte64;
1412 cc_res_handle = cfgtew.u.cfgte64->res_handle;
1413 } else {
1414 cfgtew.u.cfgte = &hostrcb->hcam.u.ccn.u.cfgte;
1415 cc_res_handle = cfgtew.u.cfgte->res_handle;
1416 }
1417
1418 list_for_each_entry(res, &ioa_cfg->used_res_q, queue) {
1419 if (res->res_handle == cc_res_handle) {
1420 is_ndn = 0;
1421 break;
1422 }
1423 }
1424
1425 if (is_ndn) {
1426 if (list_empty(&ioa_cfg->free_res_q)) {
1427 ipr_send_hcam(ioa_cfg,
1428 IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE,
1429 hostrcb);
1430 return;
1431 }
1432
1433 res = list_entry(ioa_cfg->free_res_q.next,
1434 struct ipr_resource_entry, queue);
1435
1436 list_del(&res->queue);
1437 ipr_init_res_entry(res, &cfgtew);
1438 list_add_tail(&res->queue, &ioa_cfg->used_res_q);
1439 }
1440
1441 ipr_update_res_entry(res, &cfgtew);
1442
1443 if (hostrcb->hcam.notify_type == IPR_HOST_RCB_NOTIF_TYPE_REM_ENTRY) {
1444 if (res->sdev) {
1445 res->del_from_ml = 1;
1446 res->res_handle = IPR_INVALID_RES_HANDLE;
1447 schedule_work(&ioa_cfg->work_q);
1448 } else {
1449 ipr_clear_res_target(res);
1450 list_move_tail(&res->queue, &ioa_cfg->free_res_q);
1451 }
1452 } else if (!res->sdev || res->del_from_ml) {
1453 res->add_to_ml = 1;
1454 schedule_work(&ioa_cfg->work_q);
1455 }
1456
1457 ipr_send_hcam(ioa_cfg, IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE, hostrcb);
1458}
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470static void ipr_process_ccn(struct ipr_cmnd *ipr_cmd)
1471{
1472 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
1473 struct ipr_hostrcb *hostrcb = ipr_cmd->u.hostrcb;
1474 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
1475
1476 list_del(&hostrcb->queue);
1477 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
1478
1479 if (ioasc) {
1480 if (ioasc != IPR_IOASC_IOA_WAS_RESET &&
1481 ioasc != IPR_IOASC_ABORTED_CMD_TERM_BY_HOST)
1482 dev_err(&ioa_cfg->pdev->dev,
1483 "Host RCB failed with IOASC: 0x%08X\n", ioasc);
1484
1485 ipr_send_hcam(ioa_cfg, IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE, hostrcb);
1486 } else {
1487 ipr_handle_config_change(ioa_cfg, hostrcb);
1488 }
1489}
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502static int strip_and_pad_whitespace(int i, char *buf)
1503{
1504 while (i && buf[i] == ' ')
1505 i--;
1506 buf[i+1] = ' ';
1507 buf[i+2] = '\0';
1508 return i + 2;
1509}
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520static void ipr_log_vpd_compact(char *prefix, struct ipr_hostrcb *hostrcb,
1521 struct ipr_vpd *vpd)
1522{
1523 char buffer[IPR_VENDOR_ID_LEN + IPR_PROD_ID_LEN + IPR_SERIAL_NUM_LEN + 3];
1524 int i = 0;
1525
1526 memcpy(buffer, vpd->vpids.vendor_id, IPR_VENDOR_ID_LEN);
1527 i = strip_and_pad_whitespace(IPR_VENDOR_ID_LEN - 1, buffer);
1528
1529 memcpy(&buffer[i], vpd->vpids.product_id, IPR_PROD_ID_LEN);
1530 i = strip_and_pad_whitespace(i + IPR_PROD_ID_LEN - 1, buffer);
1531
1532 memcpy(&buffer[i], vpd->sn, IPR_SERIAL_NUM_LEN);
1533 buffer[IPR_SERIAL_NUM_LEN + i] = '\0';
1534
1535 ipr_hcam_err(hostrcb, "%s VPID/SN: %s\n", prefix, buffer);
1536}
1537
1538
1539
1540
1541
1542
1543
1544
1545static void ipr_log_vpd(struct ipr_vpd *vpd)
1546{
1547 char buffer[IPR_VENDOR_ID_LEN + IPR_PROD_ID_LEN
1548 + IPR_SERIAL_NUM_LEN];
1549
1550 memcpy(buffer, vpd->vpids.vendor_id, IPR_VENDOR_ID_LEN);
1551 memcpy(buffer + IPR_VENDOR_ID_LEN, vpd->vpids.product_id,
1552 IPR_PROD_ID_LEN);
1553 buffer[IPR_VENDOR_ID_LEN + IPR_PROD_ID_LEN] = '\0';
1554 ipr_err("Vendor/Product ID: %s\n", buffer);
1555
1556 memcpy(buffer, vpd->sn, IPR_SERIAL_NUM_LEN);
1557 buffer[IPR_SERIAL_NUM_LEN] = '\0';
1558 ipr_err(" Serial Number: %s\n", buffer);
1559}
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570static void ipr_log_ext_vpd_compact(char *prefix, struct ipr_hostrcb *hostrcb,
1571 struct ipr_ext_vpd *vpd)
1572{
1573 ipr_log_vpd_compact(prefix, hostrcb, &vpd->vpd);
1574 ipr_hcam_err(hostrcb, "%s WWN: %08X%08X\n", prefix,
1575 be32_to_cpu(vpd->wwid[0]), be32_to_cpu(vpd->wwid[1]));
1576}
1577
1578
1579
1580
1581
1582
1583
1584
1585static void ipr_log_ext_vpd(struct ipr_ext_vpd *vpd)
1586{
1587 ipr_log_vpd(&vpd->vpd);
1588 ipr_err(" WWN: %08X%08X\n", be32_to_cpu(vpd->wwid[0]),
1589 be32_to_cpu(vpd->wwid[1]));
1590}
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600static void ipr_log_enhanced_cache_error(struct ipr_ioa_cfg *ioa_cfg,
1601 struct ipr_hostrcb *hostrcb)
1602{
1603 struct ipr_hostrcb_type_12_error *error;
1604
1605 if (ioa_cfg->sis64)
1606 error = &hostrcb->hcam.u.error64.u.type_12_error;
1607 else
1608 error = &hostrcb->hcam.u.error.u.type_12_error;
1609
1610 ipr_err("-----Current Configuration-----\n");
1611 ipr_err("Cache Directory Card Information:\n");
1612 ipr_log_ext_vpd(&error->ioa_vpd);
1613 ipr_err("Adapter Card Information:\n");
1614 ipr_log_ext_vpd(&error->cfc_vpd);
1615
1616 ipr_err("-----Expected Configuration-----\n");
1617 ipr_err("Cache Directory Card Information:\n");
1618 ipr_log_ext_vpd(&error->ioa_last_attached_to_cfc_vpd);
1619 ipr_err("Adapter Card Information:\n");
1620 ipr_log_ext_vpd(&error->cfc_last_attached_to_ioa_vpd);
1621
1622 ipr_err("Additional IOA Data: %08X %08X %08X\n",
1623 be32_to_cpu(error->ioa_data[0]),
1624 be32_to_cpu(error->ioa_data[1]),
1625 be32_to_cpu(error->ioa_data[2]));
1626}
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636static void ipr_log_cache_error(struct ipr_ioa_cfg *ioa_cfg,
1637 struct ipr_hostrcb *hostrcb)
1638{
1639 struct ipr_hostrcb_type_02_error *error =
1640 &hostrcb->hcam.u.error.u.type_02_error;
1641
1642 ipr_err("-----Current Configuration-----\n");
1643 ipr_err("Cache Directory Card Information:\n");
1644 ipr_log_vpd(&error->ioa_vpd);
1645 ipr_err("Adapter Card Information:\n");
1646 ipr_log_vpd(&error->cfc_vpd);
1647
1648 ipr_err("-----Expected Configuration-----\n");
1649 ipr_err("Cache Directory Card Information:\n");
1650 ipr_log_vpd(&error->ioa_last_attached_to_cfc_vpd);
1651 ipr_err("Adapter Card Information:\n");
1652 ipr_log_vpd(&error->cfc_last_attached_to_ioa_vpd);
1653
1654 ipr_err("Additional IOA Data: %08X %08X %08X\n",
1655 be32_to_cpu(error->ioa_data[0]),
1656 be32_to_cpu(error->ioa_data[1]),
1657 be32_to_cpu(error->ioa_data[2]));
1658}
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668static void ipr_log_enhanced_config_error(struct ipr_ioa_cfg *ioa_cfg,
1669 struct ipr_hostrcb *hostrcb)
1670{
1671 int errors_logged, i;
1672 struct ipr_hostrcb_device_data_entry_enhanced *dev_entry;
1673 struct ipr_hostrcb_type_13_error *error;
1674
1675 error = &hostrcb->hcam.u.error.u.type_13_error;
1676 errors_logged = be32_to_cpu(error->errors_logged);
1677
1678 ipr_err("Device Errors Detected/Logged: %d/%d\n",
1679 be32_to_cpu(error->errors_detected), errors_logged);
1680
1681 dev_entry = error->dev;
1682
1683 for (i = 0; i < errors_logged; i++, dev_entry++) {
1684 ipr_err_separator;
1685
1686 ipr_phys_res_err(ioa_cfg, dev_entry->dev_res_addr, "Device %d", i + 1);
1687 ipr_log_ext_vpd(&dev_entry->vpd);
1688
1689 ipr_err("-----New Device Information-----\n");
1690 ipr_log_ext_vpd(&dev_entry->new_vpd);
1691
1692 ipr_err("Cache Directory Card Information:\n");
1693 ipr_log_ext_vpd(&dev_entry->ioa_last_with_dev_vpd);
1694
1695 ipr_err("Adapter Card Information:\n");
1696 ipr_log_ext_vpd(&dev_entry->cfc_last_with_dev_vpd);
1697 }
1698}
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708static void ipr_log_sis64_config_error(struct ipr_ioa_cfg *ioa_cfg,
1709 struct ipr_hostrcb *hostrcb)
1710{
1711 int errors_logged, i;
1712 struct ipr_hostrcb64_device_data_entry_enhanced *dev_entry;
1713 struct ipr_hostrcb_type_23_error *error;
1714 char buffer[IPR_MAX_RES_PATH_LENGTH];
1715
1716 error = &hostrcb->hcam.u.error64.u.type_23_error;
1717 errors_logged = be32_to_cpu(error->errors_logged);
1718
1719 ipr_err("Device Errors Detected/Logged: %d/%d\n",
1720 be32_to_cpu(error->errors_detected), errors_logged);
1721
1722 dev_entry = error->dev;
1723
1724 for (i = 0; i < errors_logged; i++, dev_entry++) {
1725 ipr_err_separator;
1726
1727 ipr_err("Device %d : %s", i + 1,
1728 __ipr_format_res_path(dev_entry->res_path,
1729 buffer, sizeof(buffer)));
1730 ipr_log_ext_vpd(&dev_entry->vpd);
1731
1732 ipr_err("-----New Device Information-----\n");
1733 ipr_log_ext_vpd(&dev_entry->new_vpd);
1734
1735 ipr_err("Cache Directory Card Information:\n");
1736 ipr_log_ext_vpd(&dev_entry->ioa_last_with_dev_vpd);
1737
1738 ipr_err("Adapter Card Information:\n");
1739 ipr_log_ext_vpd(&dev_entry->cfc_last_with_dev_vpd);
1740 }
1741}
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751static void ipr_log_config_error(struct ipr_ioa_cfg *ioa_cfg,
1752 struct ipr_hostrcb *hostrcb)
1753{
1754 int errors_logged, i;
1755 struct ipr_hostrcb_device_data_entry *dev_entry;
1756 struct ipr_hostrcb_type_03_error *error;
1757
1758 error = &hostrcb->hcam.u.error.u.type_03_error;
1759 errors_logged = be32_to_cpu(error->errors_logged);
1760
1761 ipr_err("Device Errors Detected/Logged: %d/%d\n",
1762 be32_to_cpu(error->errors_detected), errors_logged);
1763
1764 dev_entry = error->dev;
1765
1766 for (i = 0; i < errors_logged; i++, dev_entry++) {
1767 ipr_err_separator;
1768
1769 ipr_phys_res_err(ioa_cfg, dev_entry->dev_res_addr, "Device %d", i + 1);
1770 ipr_log_vpd(&dev_entry->vpd);
1771
1772 ipr_err("-----New Device Information-----\n");
1773 ipr_log_vpd(&dev_entry->new_vpd);
1774
1775 ipr_err("Cache Directory Card Information:\n");
1776 ipr_log_vpd(&dev_entry->ioa_last_with_dev_vpd);
1777
1778 ipr_err("Adapter Card Information:\n");
1779 ipr_log_vpd(&dev_entry->cfc_last_with_dev_vpd);
1780
1781 ipr_err("Additional IOA Data: %08X %08X %08X %08X %08X\n",
1782 be32_to_cpu(dev_entry->ioa_data[0]),
1783 be32_to_cpu(dev_entry->ioa_data[1]),
1784 be32_to_cpu(dev_entry->ioa_data[2]),
1785 be32_to_cpu(dev_entry->ioa_data[3]),
1786 be32_to_cpu(dev_entry->ioa_data[4]));
1787 }
1788}
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798static void ipr_log_enhanced_array_error(struct ipr_ioa_cfg *ioa_cfg,
1799 struct ipr_hostrcb *hostrcb)
1800{
1801 int i, num_entries;
1802 struct ipr_hostrcb_type_14_error *error;
1803 struct ipr_hostrcb_array_data_entry_enhanced *array_entry;
1804 const u8 zero_sn[IPR_SERIAL_NUM_LEN] = { [0 ... IPR_SERIAL_NUM_LEN-1] = '0' };
1805
1806 error = &hostrcb->hcam.u.error.u.type_14_error;
1807
1808 ipr_err_separator;
1809
1810 ipr_err("RAID %s Array Configuration: %d:%d:%d:%d\n",
1811 error->protection_level,
1812 ioa_cfg->host->host_no,
1813 error->last_func_vset_res_addr.bus,
1814 error->last_func_vset_res_addr.target,
1815 error->last_func_vset_res_addr.lun);
1816
1817 ipr_err_separator;
1818
1819 array_entry = error->array_member;
1820 num_entries = min_t(u32, be32_to_cpu(error->num_entries),
1821 ARRAY_SIZE(error->array_member));
1822
1823 for (i = 0; i < num_entries; i++, array_entry++) {
1824 if (!memcmp(array_entry->vpd.vpd.sn, zero_sn, IPR_SERIAL_NUM_LEN))
1825 continue;
1826
1827 if (be32_to_cpu(error->exposed_mode_adn) == i)
1828 ipr_err("Exposed Array Member %d:\n", i);
1829 else
1830 ipr_err("Array Member %d:\n", i);
1831
1832 ipr_log_ext_vpd(&array_entry->vpd);
1833 ipr_phys_res_err(ioa_cfg, array_entry->dev_res_addr, "Current Location");
1834 ipr_phys_res_err(ioa_cfg, array_entry->expected_dev_res_addr,
1835 "Expected Location");
1836
1837 ipr_err_separator;
1838 }
1839}
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849static void ipr_log_array_error(struct ipr_ioa_cfg *ioa_cfg,
1850 struct ipr_hostrcb *hostrcb)
1851{
1852 int i;
1853 struct ipr_hostrcb_type_04_error *error;
1854 struct ipr_hostrcb_array_data_entry *array_entry;
1855 const u8 zero_sn[IPR_SERIAL_NUM_LEN] = { [0 ... IPR_SERIAL_NUM_LEN-1] = '0' };
1856
1857 error = &hostrcb->hcam.u.error.u.type_04_error;
1858
1859 ipr_err_separator;
1860
1861 ipr_err("RAID %s Array Configuration: %d:%d:%d:%d\n",
1862 error->protection_level,
1863 ioa_cfg->host->host_no,
1864 error->last_func_vset_res_addr.bus,
1865 error->last_func_vset_res_addr.target,
1866 error->last_func_vset_res_addr.lun);
1867
1868 ipr_err_separator;
1869
1870 array_entry = error->array_member;
1871
1872 for (i = 0; i < 18; i++) {
1873 if (!memcmp(array_entry->vpd.sn, zero_sn, IPR_SERIAL_NUM_LEN))
1874 continue;
1875
1876 if (be32_to_cpu(error->exposed_mode_adn) == i)
1877 ipr_err("Exposed Array Member %d:\n", i);
1878 else
1879 ipr_err("Array Member %d:\n", i);
1880
1881 ipr_log_vpd(&array_entry->vpd);
1882
1883 ipr_phys_res_err(ioa_cfg, array_entry->dev_res_addr, "Current Location");
1884 ipr_phys_res_err(ioa_cfg, array_entry->expected_dev_res_addr,
1885 "Expected Location");
1886
1887 ipr_err_separator;
1888
1889 if (i == 9)
1890 array_entry = error->array_member2;
1891 else
1892 array_entry++;
1893 }
1894}
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905static void ipr_log_hex_data(struct ipr_ioa_cfg *ioa_cfg, __be32 *data, int len)
1906{
1907 int i;
1908
1909 if (len == 0)
1910 return;
1911
1912 if (ioa_cfg->log_level <= IPR_DEFAULT_LOG_LEVEL)
1913 len = min_t(int, len, IPR_DEFAULT_MAX_ERROR_DUMP);
1914
1915 for (i = 0; i < len / 4; i += 4) {
1916 ipr_err("%08X: %08X %08X %08X %08X\n", i*4,
1917 be32_to_cpu(data[i]),
1918 be32_to_cpu(data[i+1]),
1919 be32_to_cpu(data[i+2]),
1920 be32_to_cpu(data[i+3]));
1921 }
1922}
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932static void ipr_log_enhanced_dual_ioa_error(struct ipr_ioa_cfg *ioa_cfg,
1933 struct ipr_hostrcb *hostrcb)
1934{
1935 struct ipr_hostrcb_type_17_error *error;
1936
1937 if (ioa_cfg->sis64)
1938 error = &hostrcb->hcam.u.error64.u.type_17_error;
1939 else
1940 error = &hostrcb->hcam.u.error.u.type_17_error;
1941
1942 error->failure_reason[sizeof(error->failure_reason) - 1] = '\0';
1943 strim(error->failure_reason);
1944
1945 ipr_hcam_err(hostrcb, "%s [PRC: %08X]\n", error->failure_reason,
1946 be32_to_cpu(hostrcb->hcam.u.error.prc));
1947 ipr_log_ext_vpd_compact("Remote IOA", hostrcb, &error->vpd);
1948 ipr_log_hex_data(ioa_cfg, error->data,
1949 be32_to_cpu(hostrcb->hcam.length) -
1950 (offsetof(struct ipr_hostrcb_error, u) +
1951 offsetof(struct ipr_hostrcb_type_17_error, data)));
1952}
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962static void ipr_log_dual_ioa_error(struct ipr_ioa_cfg *ioa_cfg,
1963 struct ipr_hostrcb *hostrcb)
1964{
1965 struct ipr_hostrcb_type_07_error *error;
1966
1967 error = &hostrcb->hcam.u.error.u.type_07_error;
1968 error->failure_reason[sizeof(error->failure_reason) - 1] = '\0';
1969 strim(error->failure_reason);
1970
1971 ipr_hcam_err(hostrcb, "%s [PRC: %08X]\n", error->failure_reason,
1972 be32_to_cpu(hostrcb->hcam.u.error.prc));
1973 ipr_log_vpd_compact("Remote IOA", hostrcb, &error->vpd);
1974 ipr_log_hex_data(ioa_cfg, error->data,
1975 be32_to_cpu(hostrcb->hcam.length) -
1976 (offsetof(struct ipr_hostrcb_error, u) +
1977 offsetof(struct ipr_hostrcb_type_07_error, data)));
1978}
1979
1980static const struct {
1981 u8 active;
1982 char *desc;
1983} path_active_desc[] = {
1984 { IPR_PATH_NO_INFO, "Path" },
1985 { IPR_PATH_ACTIVE, "Active path" },
1986 { IPR_PATH_NOT_ACTIVE, "Inactive path" }
1987};
1988
1989static const struct {
1990 u8 state;
1991 char *desc;
1992} path_state_desc[] = {
1993 { IPR_PATH_STATE_NO_INFO, "has no path state information available" },
1994 { IPR_PATH_HEALTHY, "is healthy" },
1995 { IPR_PATH_DEGRADED, "is degraded" },
1996 { IPR_PATH_FAILED, "is failed" }
1997};
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007static void ipr_log_fabric_path(struct ipr_hostrcb *hostrcb,
2008 struct ipr_hostrcb_fabric_desc *fabric)
2009{
2010 int i, j;
2011 u8 path_state = fabric->path_state;
2012 u8 active = path_state & IPR_PATH_ACTIVE_MASK;
2013 u8 state = path_state & IPR_PATH_STATE_MASK;
2014
2015 for (i = 0; i < ARRAY_SIZE(path_active_desc); i++) {
2016 if (path_active_desc[i].active != active)
2017 continue;
2018
2019 for (j = 0; j < ARRAY_SIZE(path_state_desc); j++) {
2020 if (path_state_desc[j].state != state)
2021 continue;
2022
2023 if (fabric->cascaded_expander == 0xff && fabric->phy == 0xff) {
2024 ipr_hcam_err(hostrcb, "%s %s: IOA Port=%d\n",
2025 path_active_desc[i].desc, path_state_desc[j].desc,
2026 fabric->ioa_port);
2027 } else if (fabric->cascaded_expander == 0xff) {
2028 ipr_hcam_err(hostrcb, "%s %s: IOA Port=%d, Phy=%d\n",
2029 path_active_desc[i].desc, path_state_desc[j].desc,
2030 fabric->ioa_port, fabric->phy);
2031 } else if (fabric->phy == 0xff) {
2032 ipr_hcam_err(hostrcb, "%s %s: IOA Port=%d, Cascade=%d\n",
2033 path_active_desc[i].desc, path_state_desc[j].desc,
2034 fabric->ioa_port, fabric->cascaded_expander);
2035 } else {
2036 ipr_hcam_err(hostrcb, "%s %s: IOA Port=%d, Cascade=%d, Phy=%d\n",
2037 path_active_desc[i].desc, path_state_desc[j].desc,
2038 fabric->ioa_port, fabric->cascaded_expander, fabric->phy);
2039 }
2040 return;
2041 }
2042 }
2043
2044 ipr_err("Path state=%02X IOA Port=%d Cascade=%d Phy=%d\n", path_state,
2045 fabric->ioa_port, fabric->cascaded_expander, fabric->phy);
2046}
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056static void ipr_log64_fabric_path(struct ipr_hostrcb *hostrcb,
2057 struct ipr_hostrcb64_fabric_desc *fabric)
2058{
2059 int i, j;
2060 u8 path_state = fabric->path_state;
2061 u8 active = path_state & IPR_PATH_ACTIVE_MASK;
2062 u8 state = path_state & IPR_PATH_STATE_MASK;
2063 char buffer[IPR_MAX_RES_PATH_LENGTH];
2064
2065 for (i = 0; i < ARRAY_SIZE(path_active_desc); i++) {
2066 if (path_active_desc[i].active != active)
2067 continue;
2068
2069 for (j = 0; j < ARRAY_SIZE(path_state_desc); j++) {
2070 if (path_state_desc[j].state != state)
2071 continue;
2072
2073 ipr_hcam_err(hostrcb, "%s %s: Resource Path=%s\n",
2074 path_active_desc[i].desc, path_state_desc[j].desc,
2075 ipr_format_res_path(hostrcb->ioa_cfg,
2076 fabric->res_path,
2077 buffer, sizeof(buffer)));
2078 return;
2079 }
2080 }
2081
2082 ipr_err("Path state=%02X Resource Path=%s\n", path_state,
2083 ipr_format_res_path(hostrcb->ioa_cfg, fabric->res_path,
2084 buffer, sizeof(buffer)));
2085}
2086
2087static const struct {
2088 u8 type;
2089 char *desc;
2090} path_type_desc[] = {
2091 { IPR_PATH_CFG_IOA_PORT, "IOA port" },
2092 { IPR_PATH_CFG_EXP_PORT, "Expander port" },
2093 { IPR_PATH_CFG_DEVICE_PORT, "Device port" },
2094 { IPR_PATH_CFG_DEVICE_LUN, "Device LUN" }
2095};
2096
2097static const struct {
2098 u8 status;
2099 char *desc;
2100} path_status_desc[] = {
2101 { IPR_PATH_CFG_NO_PROB, "Functional" },
2102 { IPR_PATH_CFG_DEGRADED, "Degraded" },
2103 { IPR_PATH_CFG_FAILED, "Failed" },
2104 { IPR_PATH_CFG_SUSPECT, "Suspect" },
2105 { IPR_PATH_NOT_DETECTED, "Missing" },
2106 { IPR_PATH_INCORRECT_CONN, "Incorrectly connected" }
2107};
2108
2109static const char *link_rate[] = {
2110 "unknown",
2111 "disabled",
2112 "phy reset problem",
2113 "spinup hold",
2114 "port selector",
2115 "unknown",
2116 "unknown",
2117 "unknown",
2118 "1.5Gbps",
2119 "3.0Gbps",
2120 "unknown",
2121 "unknown",
2122 "unknown",
2123 "unknown",
2124 "unknown",
2125 "unknown"
2126};
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136static void ipr_log_path_elem(struct ipr_hostrcb *hostrcb,
2137 struct ipr_hostrcb_config_element *cfg)
2138{
2139 int i, j;
2140 u8 type = cfg->type_status & IPR_PATH_CFG_TYPE_MASK;
2141 u8 status = cfg->type_status & IPR_PATH_CFG_STATUS_MASK;
2142
2143 if (type == IPR_PATH_CFG_NOT_EXIST)
2144 return;
2145
2146 for (i = 0; i < ARRAY_SIZE(path_type_desc); i++) {
2147 if (path_type_desc[i].type != type)
2148 continue;
2149
2150 for (j = 0; j < ARRAY_SIZE(path_status_desc); j++) {
2151 if (path_status_desc[j].status != status)
2152 continue;
2153
2154 if (type == IPR_PATH_CFG_IOA_PORT) {
2155 ipr_hcam_err(hostrcb, "%s %s: Phy=%d, Link rate=%s, WWN=%08X%08X\n",
2156 path_status_desc[j].desc, path_type_desc[i].desc,
2157 cfg->phy, link_rate[cfg->link_rate & IPR_PHY_LINK_RATE_MASK],
2158 be32_to_cpu(cfg->wwid[0]), be32_to_cpu(cfg->wwid[1]));
2159 } else {
2160 if (cfg->cascaded_expander == 0xff && cfg->phy == 0xff) {
2161 ipr_hcam_err(hostrcb, "%s %s: Link rate=%s, WWN=%08X%08X\n",
2162 path_status_desc[j].desc, path_type_desc[i].desc,
2163 link_rate[cfg->link_rate & IPR_PHY_LINK_RATE_MASK],
2164 be32_to_cpu(cfg->wwid[0]), be32_to_cpu(cfg->wwid[1]));
2165 } else if (cfg->cascaded_expander == 0xff) {
2166 ipr_hcam_err(hostrcb, "%s %s: Phy=%d, Link rate=%s, "
2167 "WWN=%08X%08X\n", path_status_desc[j].desc,
2168 path_type_desc[i].desc, cfg->phy,
2169 link_rate[cfg->link_rate & IPR_PHY_LINK_RATE_MASK],
2170 be32_to_cpu(cfg->wwid[0]), be32_to_cpu(cfg->wwid[1]));
2171 } else if (cfg->phy == 0xff) {
2172 ipr_hcam_err(hostrcb, "%s %s: Cascade=%d, Link rate=%s, "
2173 "WWN=%08X%08X\n", path_status_desc[j].desc,
2174 path_type_desc[i].desc, cfg->cascaded_expander,
2175 link_rate[cfg->link_rate & IPR_PHY_LINK_RATE_MASK],
2176 be32_to_cpu(cfg->wwid[0]), be32_to_cpu(cfg->wwid[1]));
2177 } else {
2178 ipr_hcam_err(hostrcb, "%s %s: Cascade=%d, Phy=%d, Link rate=%s "
2179 "WWN=%08X%08X\n", path_status_desc[j].desc,
2180 path_type_desc[i].desc, cfg->cascaded_expander, cfg->phy,
2181 link_rate[cfg->link_rate & IPR_PHY_LINK_RATE_MASK],
2182 be32_to_cpu(cfg->wwid[0]), be32_to_cpu(cfg->wwid[1]));
2183 }
2184 }
2185 return;
2186 }
2187 }
2188
2189 ipr_hcam_err(hostrcb, "Path element=%02X: Cascade=%d Phy=%d Link rate=%s "
2190 "WWN=%08X%08X\n", cfg->type_status, cfg->cascaded_expander, cfg->phy,
2191 link_rate[cfg->link_rate & IPR_PHY_LINK_RATE_MASK],
2192 be32_to_cpu(cfg->wwid[0]), be32_to_cpu(cfg->wwid[1]));
2193}
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203static void ipr_log64_path_elem(struct ipr_hostrcb *hostrcb,
2204 struct ipr_hostrcb64_config_element *cfg)
2205{
2206 int i, j;
2207 u8 desc_id = cfg->descriptor_id & IPR_DESCRIPTOR_MASK;
2208 u8 type = cfg->type_status & IPR_PATH_CFG_TYPE_MASK;
2209 u8 status = cfg->type_status & IPR_PATH_CFG_STATUS_MASK;
2210 char buffer[IPR_MAX_RES_PATH_LENGTH];
2211
2212 if (type == IPR_PATH_CFG_NOT_EXIST || desc_id != IPR_DESCRIPTOR_SIS64)
2213 return;
2214
2215 for (i = 0; i < ARRAY_SIZE(path_type_desc); i++) {
2216 if (path_type_desc[i].type != type)
2217 continue;
2218
2219 for (j = 0; j < ARRAY_SIZE(path_status_desc); j++) {
2220 if (path_status_desc[j].status != status)
2221 continue;
2222
2223 ipr_hcam_err(hostrcb, "%s %s: Resource Path=%s, Link rate=%s, WWN=%08X%08X\n",
2224 path_status_desc[j].desc, path_type_desc[i].desc,
2225 ipr_format_res_path(hostrcb->ioa_cfg,
2226 cfg->res_path, buffer, sizeof(buffer)),
2227 link_rate[cfg->link_rate & IPR_PHY_LINK_RATE_MASK],
2228 be32_to_cpu(cfg->wwid[0]),
2229 be32_to_cpu(cfg->wwid[1]));
2230 return;
2231 }
2232 }
2233 ipr_hcam_err(hostrcb, "Path element=%02X: Resource Path=%s, Link rate=%s "
2234 "WWN=%08X%08X\n", cfg->type_status,
2235 ipr_format_res_path(hostrcb->ioa_cfg,
2236 cfg->res_path, buffer, sizeof(buffer)),
2237 link_rate[cfg->link_rate & IPR_PHY_LINK_RATE_MASK],
2238 be32_to_cpu(cfg->wwid[0]), be32_to_cpu(cfg->wwid[1]));
2239}
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249static void ipr_log_fabric_error(struct ipr_ioa_cfg *ioa_cfg,
2250 struct ipr_hostrcb *hostrcb)
2251{
2252 struct ipr_hostrcb_type_20_error *error;
2253 struct ipr_hostrcb_fabric_desc *fabric;
2254 struct ipr_hostrcb_config_element *cfg;
2255 int i, add_len;
2256
2257 error = &hostrcb->hcam.u.error.u.type_20_error;
2258 error->failure_reason[sizeof(error->failure_reason) - 1] = '\0';
2259 ipr_hcam_err(hostrcb, "%s\n", error->failure_reason);
2260
2261 add_len = be32_to_cpu(hostrcb->hcam.length) -
2262 (offsetof(struct ipr_hostrcb_error, u) +
2263 offsetof(struct ipr_hostrcb_type_20_error, desc));
2264
2265 for (i = 0, fabric = error->desc; i < error->num_entries; i++) {
2266 ipr_log_fabric_path(hostrcb, fabric);
2267 for_each_fabric_cfg(fabric, cfg)
2268 ipr_log_path_elem(hostrcb, cfg);
2269
2270 add_len -= be16_to_cpu(fabric->length);
2271 fabric = (struct ipr_hostrcb_fabric_desc *)
2272 ((unsigned long)fabric + be16_to_cpu(fabric->length));
2273 }
2274
2275 ipr_log_hex_data(ioa_cfg, (__be32 *)fabric, add_len);
2276}
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286static void ipr_log_sis64_array_error(struct ipr_ioa_cfg *ioa_cfg,
2287 struct ipr_hostrcb *hostrcb)
2288{
2289 int i, num_entries;
2290 struct ipr_hostrcb_type_24_error *error;
2291 struct ipr_hostrcb64_array_data_entry *array_entry;
2292 char buffer[IPR_MAX_RES_PATH_LENGTH];
2293 const u8 zero_sn[IPR_SERIAL_NUM_LEN] = { [0 ... IPR_SERIAL_NUM_LEN-1] = '0' };
2294
2295 error = &hostrcb->hcam.u.error64.u.type_24_error;
2296
2297 ipr_err_separator;
2298
2299 ipr_err("RAID %s Array Configuration: %s\n",
2300 error->protection_level,
2301 ipr_format_res_path(ioa_cfg, error->last_res_path,
2302 buffer, sizeof(buffer)));
2303
2304 ipr_err_separator;
2305
2306 array_entry = error->array_member;
2307 num_entries = min_t(u32, error->num_entries,
2308 ARRAY_SIZE(error->array_member));
2309
2310 for (i = 0; i < num_entries; i++, array_entry++) {
2311
2312 if (!memcmp(array_entry->vpd.vpd.sn, zero_sn, IPR_SERIAL_NUM_LEN))
2313 continue;
2314
2315 if (error->exposed_mode_adn == i)
2316 ipr_err("Exposed Array Member %d:\n", i);
2317 else
2318 ipr_err("Array Member %d:\n", i);
2319
2320 ipr_err("Array Member %d:\n", i);
2321 ipr_log_ext_vpd(&array_entry->vpd);
2322 ipr_err("Current Location: %s\n",
2323 ipr_format_res_path(ioa_cfg, array_entry->res_path,
2324 buffer, sizeof(buffer)));
2325 ipr_err("Expected Location: %s\n",
2326 ipr_format_res_path(ioa_cfg,
2327 array_entry->expected_res_path,
2328 buffer, sizeof(buffer)));
2329
2330 ipr_err_separator;
2331 }
2332}
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342static void ipr_log_sis64_fabric_error(struct ipr_ioa_cfg *ioa_cfg,
2343 struct ipr_hostrcb *hostrcb)
2344{
2345 struct ipr_hostrcb_type_30_error *error;
2346 struct ipr_hostrcb64_fabric_desc *fabric;
2347 struct ipr_hostrcb64_config_element *cfg;
2348 int i, add_len;
2349
2350 error = &hostrcb->hcam.u.error64.u.type_30_error;
2351
2352 error->failure_reason[sizeof(error->failure_reason) - 1] = '\0';
2353 ipr_hcam_err(hostrcb, "%s\n", error->failure_reason);
2354
2355 add_len = be32_to_cpu(hostrcb->hcam.length) -
2356 (offsetof(struct ipr_hostrcb64_error, u) +
2357 offsetof(struct ipr_hostrcb_type_30_error, desc));
2358
2359 for (i = 0, fabric = error->desc; i < error->num_entries; i++) {
2360 ipr_log64_fabric_path(hostrcb, fabric);
2361 for_each_fabric_cfg(fabric, cfg)
2362 ipr_log64_path_elem(hostrcb, cfg);
2363
2364 add_len -= be16_to_cpu(fabric->length);
2365 fabric = (struct ipr_hostrcb64_fabric_desc *)
2366 ((unsigned long)fabric + be16_to_cpu(fabric->length));
2367 }
2368
2369 ipr_log_hex_data(ioa_cfg, (__be32 *)fabric, add_len);
2370}
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380static void ipr_log_generic_error(struct ipr_ioa_cfg *ioa_cfg,
2381 struct ipr_hostrcb *hostrcb)
2382{
2383 ipr_log_hex_data(ioa_cfg, hostrcb->hcam.u.raw.data,
2384 be32_to_cpu(hostrcb->hcam.length));
2385}
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395static void ipr_log_sis64_device_error(struct ipr_ioa_cfg *ioa_cfg,
2396 struct ipr_hostrcb *hostrcb)
2397{
2398 struct ipr_hostrcb_type_21_error *error;
2399 char buffer[IPR_MAX_RES_PATH_LENGTH];
2400
2401 error = &hostrcb->hcam.u.error64.u.type_21_error;
2402
2403 ipr_err("-----Failing Device Information-----\n");
2404 ipr_err("World Wide Unique ID: %08X%08X%08X%08X\n",
2405 be32_to_cpu(error->wwn[0]), be32_to_cpu(error->wwn[1]),
2406 be32_to_cpu(error->wwn[2]), be32_to_cpu(error->wwn[3]));
2407 ipr_err("Device Resource Path: %s\n",
2408 __ipr_format_res_path(error->res_path,
2409 buffer, sizeof(buffer)));
2410 error->primary_problem_desc[sizeof(error->primary_problem_desc) - 1] = '\0';
2411 error->second_problem_desc[sizeof(error->second_problem_desc) - 1] = '\0';
2412 ipr_err("Primary Problem Description: %s\n", error->primary_problem_desc);
2413 ipr_err("Secondary Problem Description: %s\n", error->second_problem_desc);
2414 ipr_err("SCSI Sense Data:\n");
2415 ipr_log_hex_data(ioa_cfg, error->sense_data, sizeof(error->sense_data));
2416 ipr_err("SCSI Command Descriptor Block: \n");
2417 ipr_log_hex_data(ioa_cfg, error->cdb, sizeof(error->cdb));
2418
2419 ipr_err("Additional IOA Data:\n");
2420 ipr_log_hex_data(ioa_cfg, error->ioa_data, be32_to_cpu(error->length_of_error));
2421}
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434static u32 ipr_get_error(u32 ioasc)
2435{
2436 int i;
2437
2438 for (i = 0; i < ARRAY_SIZE(ipr_error_table); i++)
2439 if (ipr_error_table[i].ioasc == (ioasc & IPR_IOASC_IOASC_MASK))
2440 return i;
2441
2442 return 0;
2443}
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455static void ipr_handle_log_data(struct ipr_ioa_cfg *ioa_cfg,
2456 struct ipr_hostrcb *hostrcb)
2457{
2458 u32 ioasc;
2459 int error_index;
2460 struct ipr_hostrcb_type_21_error *error;
2461
2462 if (hostrcb->hcam.notify_type != IPR_HOST_RCB_NOTIF_TYPE_ERROR_LOG_ENTRY)
2463 return;
2464
2465 if (hostrcb->hcam.notifications_lost == IPR_HOST_RCB_NOTIFICATIONS_LOST)
2466 dev_err(&ioa_cfg->pdev->dev, "Error notifications lost\n");
2467
2468 if (ioa_cfg->sis64)
2469 ioasc = be32_to_cpu(hostrcb->hcam.u.error64.fd_ioasc);
2470 else
2471 ioasc = be32_to_cpu(hostrcb->hcam.u.error.fd_ioasc);
2472
2473 if (!ioa_cfg->sis64 && (ioasc == IPR_IOASC_BUS_WAS_RESET ||
2474 ioasc == IPR_IOASC_BUS_WAS_RESET_BY_OTHER)) {
2475
2476 scsi_report_bus_reset(ioa_cfg->host,
2477 hostrcb->hcam.u.error.fd_res_addr.bus);
2478 }
2479
2480 error_index = ipr_get_error(ioasc);
2481
2482 if (!ipr_error_table[error_index].log_hcam)
2483 return;
2484
2485 if (ioasc == IPR_IOASC_HW_CMD_FAILED &&
2486 hostrcb->hcam.overlay_id == IPR_HOST_RCB_OVERLAY_ID_21) {
2487 error = &hostrcb->hcam.u.error64.u.type_21_error;
2488
2489 if (((be32_to_cpu(error->sense_data[0]) & 0x0000ff00) >> 8) == ILLEGAL_REQUEST &&
2490 ioa_cfg->log_level <= IPR_DEFAULT_LOG_LEVEL)
2491 return;
2492 }
2493
2494 ipr_hcam_err(hostrcb, "%s\n", ipr_error_table[error_index].error);
2495
2496
2497 ioa_cfg->errors_logged++;
2498
2499 if (ioa_cfg->log_level < ipr_error_table[error_index].log_hcam)
2500 return;
2501 if (be32_to_cpu(hostrcb->hcam.length) > sizeof(hostrcb->hcam.u.raw))
2502 hostrcb->hcam.length = cpu_to_be32(sizeof(hostrcb->hcam.u.raw));
2503
2504 switch (hostrcb->hcam.overlay_id) {
2505 case IPR_HOST_RCB_OVERLAY_ID_2:
2506 ipr_log_cache_error(ioa_cfg, hostrcb);
2507 break;
2508 case IPR_HOST_RCB_OVERLAY_ID_3:
2509 ipr_log_config_error(ioa_cfg, hostrcb);
2510 break;
2511 case IPR_HOST_RCB_OVERLAY_ID_4:
2512 case IPR_HOST_RCB_OVERLAY_ID_6:
2513 ipr_log_array_error(ioa_cfg, hostrcb);
2514 break;
2515 case IPR_HOST_RCB_OVERLAY_ID_7:
2516 ipr_log_dual_ioa_error(ioa_cfg, hostrcb);
2517 break;
2518 case IPR_HOST_RCB_OVERLAY_ID_12:
2519 ipr_log_enhanced_cache_error(ioa_cfg, hostrcb);
2520 break;
2521 case IPR_HOST_RCB_OVERLAY_ID_13:
2522 ipr_log_enhanced_config_error(ioa_cfg, hostrcb);
2523 break;
2524 case IPR_HOST_RCB_OVERLAY_ID_14:
2525 case IPR_HOST_RCB_OVERLAY_ID_16:
2526 ipr_log_enhanced_array_error(ioa_cfg, hostrcb);
2527 break;
2528 case IPR_HOST_RCB_OVERLAY_ID_17:
2529 ipr_log_enhanced_dual_ioa_error(ioa_cfg, hostrcb);
2530 break;
2531 case IPR_HOST_RCB_OVERLAY_ID_20:
2532 ipr_log_fabric_error(ioa_cfg, hostrcb);
2533 break;
2534 case IPR_HOST_RCB_OVERLAY_ID_21:
2535 ipr_log_sis64_device_error(ioa_cfg, hostrcb);
2536 break;
2537 case IPR_HOST_RCB_OVERLAY_ID_23:
2538 ipr_log_sis64_config_error(ioa_cfg, hostrcb);
2539 break;
2540 case IPR_HOST_RCB_OVERLAY_ID_24:
2541 case IPR_HOST_RCB_OVERLAY_ID_26:
2542 ipr_log_sis64_array_error(ioa_cfg, hostrcb);
2543 break;
2544 case IPR_HOST_RCB_OVERLAY_ID_30:
2545 ipr_log_sis64_fabric_error(ioa_cfg, hostrcb);
2546 break;
2547 case IPR_HOST_RCB_OVERLAY_ID_1:
2548 case IPR_HOST_RCB_OVERLAY_ID_DEFAULT:
2549 default:
2550 ipr_log_generic_error(ioa_cfg, hostrcb);
2551 break;
2552 }
2553}
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563
2564
2565
2566static void ipr_process_error(struct ipr_cmnd *ipr_cmd)
2567{
2568 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
2569 struct ipr_hostrcb *hostrcb = ipr_cmd->u.hostrcb;
2570 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
2571 u32 fd_ioasc;
2572
2573 if (ioa_cfg->sis64)
2574 fd_ioasc = be32_to_cpu(hostrcb->hcam.u.error64.fd_ioasc);
2575 else
2576 fd_ioasc = be32_to_cpu(hostrcb->hcam.u.error.fd_ioasc);
2577
2578 list_del(&hostrcb->queue);
2579 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
2580
2581 if (!ioasc) {
2582 ipr_handle_log_data(ioa_cfg, hostrcb);
2583 if (fd_ioasc == IPR_IOASC_NR_IOA_RESET_REQUIRED)
2584 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_ABBREV);
2585 } else if (ioasc != IPR_IOASC_IOA_WAS_RESET &&
2586 ioasc != IPR_IOASC_ABORTED_CMD_TERM_BY_HOST) {
2587 dev_err(&ioa_cfg->pdev->dev,
2588 "Host RCB failed with IOASC: 0x%08X\n", ioasc);
2589 }
2590
2591 ipr_send_hcam(ioa_cfg, IPR_HCAM_CDB_OP_CODE_LOG_DATA, hostrcb);
2592}
2593
2594
2595
2596
2597
2598
2599
2600
2601
2602
2603
2604static void ipr_timeout(struct ipr_cmnd *ipr_cmd)
2605{
2606 unsigned long lock_flags = 0;
2607 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
2608
2609 ENTER;
2610 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
2611
2612 ioa_cfg->errors_logged++;
2613 dev_err(&ioa_cfg->pdev->dev,
2614 "Adapter being reset due to command timeout.\n");
2615
2616 if (WAIT_FOR_DUMP == ioa_cfg->sdt_state)
2617 ioa_cfg->sdt_state = GET_DUMP;
2618
2619 if (!ioa_cfg->in_reset_reload || ioa_cfg->reset_cmd == ipr_cmd)
2620 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
2621
2622 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
2623 LEAVE;
2624}
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634
2635
2636static void ipr_oper_timeout(struct ipr_cmnd *ipr_cmd)
2637{
2638 unsigned long lock_flags = 0;
2639 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
2640
2641 ENTER;
2642 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
2643
2644 ioa_cfg->errors_logged++;
2645 dev_err(&ioa_cfg->pdev->dev,
2646 "Adapter timed out transitioning to operational.\n");
2647
2648 if (WAIT_FOR_DUMP == ioa_cfg->sdt_state)
2649 ioa_cfg->sdt_state = GET_DUMP;
2650
2651 if (!ioa_cfg->in_reset_reload || ioa_cfg->reset_cmd == ipr_cmd) {
2652 if (ipr_fastfail)
2653 ioa_cfg->reset_retries += IPR_NUM_RESET_RELOAD_RETRIES;
2654 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
2655 }
2656
2657 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
2658 LEAVE;
2659}
2660
2661
2662
2663
2664
2665
2666
2667
2668static const struct ipr_ses_table_entry *
2669ipr_find_ses_entry(struct ipr_resource_entry *res)
2670{
2671 int i, j, matches;
2672 struct ipr_std_inq_vpids *vpids;
2673 const struct ipr_ses_table_entry *ste = ipr_ses_table;
2674
2675 for (i = 0; i < ARRAY_SIZE(ipr_ses_table); i++, ste++) {
2676 for (j = 0, matches = 0; j < IPR_PROD_ID_LEN; j++) {
2677 if (ste->compare_product_id_byte[j] == 'X') {
2678 vpids = &res->std_inq_data.vpids;
2679 if (vpids->product_id[j] == ste->product_id[j])
2680 matches++;
2681 else
2682 break;
2683 } else
2684 matches++;
2685 }
2686
2687 if (matches == IPR_PROD_ID_LEN)
2688 return ste;
2689 }
2690
2691 return NULL;
2692}
2693
2694
2695
2696
2697
2698
2699
2700
2701
2702
2703
2704
2705
2706static u32 ipr_get_max_scsi_speed(struct ipr_ioa_cfg *ioa_cfg, u8 bus, u8 bus_width)
2707{
2708 struct ipr_resource_entry *res;
2709 const struct ipr_ses_table_entry *ste;
2710 u32 max_xfer_rate = IPR_MAX_SCSI_RATE(bus_width);
2711
2712
2713 list_for_each_entry(res, &ioa_cfg->used_res_q, queue) {
2714 if (!(IPR_IS_SES_DEVICE(res->std_inq_data)))
2715 continue;
2716
2717 if (bus != res->bus)
2718 continue;
2719
2720 if (!(ste = ipr_find_ses_entry(res)))
2721 continue;
2722
2723 max_xfer_rate = (ste->max_bus_speed_limit * 10) / (bus_width / 8);
2724 }
2725
2726 return max_xfer_rate;
2727}
2728
2729
2730
2731
2732
2733
2734
2735
2736
2737
2738
2739static int ipr_wait_iodbg_ack(struct ipr_ioa_cfg *ioa_cfg, int max_delay)
2740{
2741 volatile u32 pcii_reg;
2742 int delay = 1;
2743
2744
2745 while (delay < max_delay) {
2746 pcii_reg = readl(ioa_cfg->regs.sense_interrupt_reg);
2747
2748 if (pcii_reg & IPR_PCII_IO_DEBUG_ACKNOWLEDGE)
2749 return 0;
2750
2751
2752 if ((delay / 1000) > MAX_UDELAY_MS)
2753 mdelay(delay / 1000);
2754 else
2755 udelay(delay);
2756
2757 delay += delay;
2758 }
2759 return -EIO;
2760}
2761
2762
2763
2764
2765
2766
2767
2768
2769
2770
2771
2772static int ipr_get_sis64_dump_data_section(struct ipr_ioa_cfg *ioa_cfg,
2773 u32 start_addr,
2774 __be32 *dest, u32 length_in_words)
2775{
2776 int i;
2777
2778 for (i = 0; i < length_in_words; i++) {
2779 writel(start_addr+(i*4), ioa_cfg->regs.dump_addr_reg);
2780 *dest = cpu_to_be32(readl(ioa_cfg->regs.dump_data_reg));
2781 dest++;
2782 }
2783
2784 return 0;
2785}
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795
2796
2797static int ipr_get_ldump_data_section(struct ipr_ioa_cfg *ioa_cfg,
2798 u32 start_addr,
2799 __be32 *dest, u32 length_in_words)
2800{
2801 volatile u32 temp_pcii_reg;
2802 int i, delay = 0;
2803
2804 if (ioa_cfg->sis64)
2805 return ipr_get_sis64_dump_data_section(ioa_cfg, start_addr,
2806 dest, length_in_words);
2807
2808
2809 writel((IPR_UPROCI_RESET_ALERT | IPR_UPROCI_IO_DEBUG_ALERT),
2810 ioa_cfg->regs.set_uproc_interrupt_reg32);
2811
2812
2813 if (ipr_wait_iodbg_ack(ioa_cfg,
2814 IPR_LDUMP_MAX_LONG_ACK_DELAY_IN_USEC)) {
2815 dev_err(&ioa_cfg->pdev->dev,
2816 "IOA dump long data transfer timeout\n");
2817 return -EIO;
2818 }
2819
2820
2821 writel(IPR_PCII_IO_DEBUG_ACKNOWLEDGE,
2822 ioa_cfg->regs.clr_interrupt_reg);
2823
2824
2825 writel(start_addr, ioa_cfg->ioa_mailbox);
2826
2827
2828 writel(IPR_UPROCI_RESET_ALERT,
2829 ioa_cfg->regs.clr_uproc_interrupt_reg32);
2830
2831 for (i = 0; i < length_in_words; i++) {
2832
2833 if (ipr_wait_iodbg_ack(ioa_cfg,
2834 IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC)) {
2835 dev_err(&ioa_cfg->pdev->dev,
2836 "IOA dump short data transfer timeout\n");
2837 return -EIO;
2838 }
2839
2840
2841 *dest = cpu_to_be32(readl(ioa_cfg->ioa_mailbox));
2842 dest++;
2843
2844
2845 if (i < (length_in_words - 1)) {
2846
2847 writel(IPR_PCII_IO_DEBUG_ACKNOWLEDGE,
2848 ioa_cfg->regs.clr_interrupt_reg);
2849 }
2850 }
2851
2852
2853 writel(IPR_UPROCI_RESET_ALERT,
2854 ioa_cfg->regs.set_uproc_interrupt_reg32);
2855
2856 writel(IPR_UPROCI_IO_DEBUG_ALERT,
2857 ioa_cfg->regs.clr_uproc_interrupt_reg32);
2858
2859
2860 writel(IPR_PCII_IO_DEBUG_ACKNOWLEDGE,
2861 ioa_cfg->regs.clr_interrupt_reg);
2862
2863
2864 while (delay < IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC) {
2865 temp_pcii_reg =
2866 readl(ioa_cfg->regs.sense_uproc_interrupt_reg32);
2867
2868 if (!(temp_pcii_reg & IPR_UPROCI_RESET_ALERT))
2869 return 0;
2870
2871 udelay(10);
2872 delay += 10;
2873 }
2874
2875 return 0;
2876}
2877
2878#ifdef CONFIG_SCSI_IPR_DUMP
2879
2880
2881
2882
2883
2884
2885
2886
2887
2888
2889
2890static int ipr_sdt_copy(struct ipr_ioa_cfg *ioa_cfg,
2891 unsigned long pci_address, u32 length)
2892{
2893 int bytes_copied = 0;
2894 int cur_len, rc, rem_len, rem_page_len, max_dump_size;
2895 __be32 *page;
2896 unsigned long lock_flags = 0;
2897 struct ipr_ioa_dump *ioa_dump = &ioa_cfg->dump->ioa_dump;
2898
2899 if (ioa_cfg->sis64)
2900 max_dump_size = IPR_FMT3_MAX_IOA_DUMP_SIZE;
2901 else
2902 max_dump_size = IPR_FMT2_MAX_IOA_DUMP_SIZE;
2903
2904 while (bytes_copied < length &&
2905 (ioa_dump->hdr.len + bytes_copied) < max_dump_size) {
2906 if (ioa_dump->page_offset >= PAGE_SIZE ||
2907 ioa_dump->page_offset == 0) {
2908 page = (__be32 *)__get_free_page(GFP_ATOMIC);
2909
2910 if (!page) {
2911 ipr_trace;
2912 return bytes_copied;
2913 }
2914
2915 ioa_dump->page_offset = 0;
2916 ioa_dump->ioa_data[ioa_dump->next_page_index] = page;
2917 ioa_dump->next_page_index++;
2918 } else
2919 page = ioa_dump->ioa_data[ioa_dump->next_page_index - 1];
2920
2921 rem_len = length - bytes_copied;
2922 rem_page_len = PAGE_SIZE - ioa_dump->page_offset;
2923 cur_len = min(rem_len, rem_page_len);
2924
2925 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
2926 if (ioa_cfg->sdt_state == ABORT_DUMP) {
2927 rc = -EIO;
2928 } else {
2929 rc = ipr_get_ldump_data_section(ioa_cfg,
2930 pci_address + bytes_copied,
2931 &page[ioa_dump->page_offset / 4],
2932 (cur_len / sizeof(u32)));
2933 }
2934 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
2935
2936 if (!rc) {
2937 ioa_dump->page_offset += cur_len;
2938 bytes_copied += cur_len;
2939 } else {
2940 ipr_trace;
2941 break;
2942 }
2943 schedule();
2944 }
2945
2946 return bytes_copied;
2947}
2948
2949
2950
2951
2952
2953
2954
2955
2956static void ipr_init_dump_entry_hdr(struct ipr_dump_entry_header *hdr)
2957{
2958 hdr->eye_catcher = IPR_DUMP_EYE_CATCHER;
2959 hdr->num_elems = 1;
2960 hdr->offset = sizeof(*hdr);
2961 hdr->status = IPR_DUMP_STATUS_SUCCESS;
2962}
2963
2964
2965
2966
2967
2968
2969
2970
2971
2972static void ipr_dump_ioa_type_data(struct ipr_ioa_cfg *ioa_cfg,
2973 struct ipr_driver_dump *driver_dump)
2974{
2975 struct ipr_inquiry_page3 *ucode_vpd = &ioa_cfg->vpd_cbs->page3_data;
2976
2977 ipr_init_dump_entry_hdr(&driver_dump->ioa_type_entry.hdr);
2978 driver_dump->ioa_type_entry.hdr.len =
2979 sizeof(struct ipr_dump_ioa_type_entry) -
2980 sizeof(struct ipr_dump_entry_header);
2981 driver_dump->ioa_type_entry.hdr.data_type = IPR_DUMP_DATA_TYPE_BINARY;
2982 driver_dump->ioa_type_entry.hdr.id = IPR_DUMP_DRIVER_TYPE_ID;
2983 driver_dump->ioa_type_entry.type = ioa_cfg->type;
2984 driver_dump->ioa_type_entry.fw_version = (ucode_vpd->major_release << 24) |
2985 (ucode_vpd->card_type << 16) | (ucode_vpd->minor_release[0] << 8) |
2986 ucode_vpd->minor_release[1];
2987 driver_dump->hdr.num_entries++;
2988}
2989
2990
2991
2992
2993
2994
2995
2996
2997
2998static void ipr_dump_version_data(struct ipr_ioa_cfg *ioa_cfg,
2999 struct ipr_driver_dump *driver_dump)
3000{
3001 ipr_init_dump_entry_hdr(&driver_dump->version_entry.hdr);
3002 driver_dump->version_entry.hdr.len =
3003 sizeof(struct ipr_dump_version_entry) -
3004 sizeof(struct ipr_dump_entry_header);
3005 driver_dump->version_entry.hdr.data_type = IPR_DUMP_DATA_TYPE_ASCII;
3006 driver_dump->version_entry.hdr.id = IPR_DUMP_DRIVER_VERSION_ID;
3007 strcpy(driver_dump->version_entry.version, IPR_DRIVER_VERSION);
3008 driver_dump->hdr.num_entries++;
3009}
3010
3011
3012
3013
3014
3015
3016
3017
3018
3019static void ipr_dump_trace_data(struct ipr_ioa_cfg *ioa_cfg,
3020 struct ipr_driver_dump *driver_dump)
3021{
3022 ipr_init_dump_entry_hdr(&driver_dump->trace_entry.hdr);
3023 driver_dump->trace_entry.hdr.len =
3024 sizeof(struct ipr_dump_trace_entry) -
3025 sizeof(struct ipr_dump_entry_header);
3026 driver_dump->trace_entry.hdr.data_type = IPR_DUMP_DATA_TYPE_BINARY;
3027 driver_dump->trace_entry.hdr.id = IPR_DUMP_TRACE_ID;
3028 memcpy(driver_dump->trace_entry.trace, ioa_cfg->trace, IPR_TRACE_SIZE);
3029 driver_dump->hdr.num_entries++;
3030}
3031
3032
3033
3034
3035
3036
3037
3038
3039
3040static void ipr_dump_location_data(struct ipr_ioa_cfg *ioa_cfg,
3041 struct ipr_driver_dump *driver_dump)
3042{
3043 ipr_init_dump_entry_hdr(&driver_dump->location_entry.hdr);
3044 driver_dump->location_entry.hdr.len =
3045 sizeof(struct ipr_dump_location_entry) -
3046 sizeof(struct ipr_dump_entry_header);
3047 driver_dump->location_entry.hdr.data_type = IPR_DUMP_DATA_TYPE_ASCII;
3048 driver_dump->location_entry.hdr.id = IPR_DUMP_LOCATION_ID;
3049 strcpy(driver_dump->location_entry.location, dev_name(&ioa_cfg->pdev->dev));
3050 driver_dump->hdr.num_entries++;
3051}
3052
3053
3054
3055
3056
3057
3058
3059
3060
3061static void ipr_get_ioa_dump(struct ipr_ioa_cfg *ioa_cfg, struct ipr_dump *dump)
3062{
3063 unsigned long start_addr, sdt_word;
3064 unsigned long lock_flags = 0;
3065 struct ipr_driver_dump *driver_dump = &dump->driver_dump;
3066 struct ipr_ioa_dump *ioa_dump = &dump->ioa_dump;
3067 u32 num_entries, max_num_entries, start_off, end_off;
3068 u32 max_dump_size, bytes_to_copy, bytes_copied, rc;
3069 struct ipr_sdt *sdt;
3070 int valid = 1;
3071 int i;
3072
3073 ENTER;
3074
3075 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3076
3077 if (ioa_cfg->sdt_state != READ_DUMP) {
3078 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3079 return;
3080 }
3081
3082 if (ioa_cfg->sis64) {
3083 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3084 ssleep(IPR_DUMP_DELAY_SECONDS);
3085 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3086 }
3087
3088 start_addr = readl(ioa_cfg->ioa_mailbox);
3089
3090 if (!ioa_cfg->sis64 && !ipr_sdt_is_fmt2(start_addr)) {
3091 dev_err(&ioa_cfg->pdev->dev,
3092 "Invalid dump table format: %lx\n", start_addr);
3093 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3094 return;
3095 }
3096
3097 dev_err(&ioa_cfg->pdev->dev, "Dump of IOA initiated\n");
3098
3099 driver_dump->hdr.eye_catcher = IPR_DUMP_EYE_CATCHER;
3100
3101
3102 driver_dump->hdr.len = sizeof(struct ipr_driver_dump);
3103 driver_dump->hdr.num_entries = 1;
3104 driver_dump->hdr.first_entry_offset = sizeof(struct ipr_dump_header);
3105 driver_dump->hdr.status = IPR_DUMP_STATUS_SUCCESS;
3106 driver_dump->hdr.os = IPR_DUMP_OS_LINUX;
3107 driver_dump->hdr.driver_name = IPR_DUMP_DRIVER_NAME;
3108
3109 ipr_dump_version_data(ioa_cfg, driver_dump);
3110 ipr_dump_location_data(ioa_cfg, driver_dump);
3111 ipr_dump_ioa_type_data(ioa_cfg, driver_dump);
3112 ipr_dump_trace_data(ioa_cfg, driver_dump);
3113
3114
3115 driver_dump->hdr.len += sizeof(struct ipr_dump_entry_header);
3116
3117
3118 ipr_init_dump_entry_hdr(&ioa_dump->hdr);
3119 ioa_dump->hdr.len = 0;
3120 ioa_dump->hdr.data_type = IPR_DUMP_DATA_TYPE_BINARY;
3121 ioa_dump->hdr.id = IPR_DUMP_IOA_DUMP_ID;
3122
3123
3124
3125
3126
3127 sdt = &ioa_dump->sdt;
3128
3129 if (ioa_cfg->sis64) {
3130 max_num_entries = IPR_FMT3_NUM_SDT_ENTRIES;
3131 max_dump_size = IPR_FMT3_MAX_IOA_DUMP_SIZE;
3132 } else {
3133 max_num_entries = IPR_FMT2_NUM_SDT_ENTRIES;
3134 max_dump_size = IPR_FMT2_MAX_IOA_DUMP_SIZE;
3135 }
3136
3137 bytes_to_copy = offsetof(struct ipr_sdt, entry) +
3138 (max_num_entries * sizeof(struct ipr_sdt_entry));
3139 rc = ipr_get_ldump_data_section(ioa_cfg, start_addr, (__be32 *)sdt,
3140 bytes_to_copy / sizeof(__be32));
3141
3142
3143 if (rc || ((be32_to_cpu(sdt->hdr.state) != IPR_FMT3_SDT_READY_TO_USE) &&
3144 (be32_to_cpu(sdt->hdr.state) != IPR_FMT2_SDT_READY_TO_USE))) {
3145 dev_err(&ioa_cfg->pdev->dev,
3146 "Dump of IOA failed. Dump table not valid: %d, %X.\n",
3147 rc, be32_to_cpu(sdt->hdr.state));
3148 driver_dump->hdr.status = IPR_DUMP_STATUS_FAILED;
3149 ioa_cfg->sdt_state = DUMP_OBTAINED;
3150 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3151 return;
3152 }
3153
3154 num_entries = be32_to_cpu(sdt->hdr.num_entries_used);
3155
3156 if (num_entries > max_num_entries)
3157 num_entries = max_num_entries;
3158
3159
3160 dump->driver_dump.hdr.len += sizeof(struct ipr_sdt_header);
3161 if (ioa_cfg->sis64)
3162 dump->driver_dump.hdr.len += num_entries * sizeof(struct ipr_sdt_entry);
3163 else
3164 dump->driver_dump.hdr.len += max_num_entries * sizeof(struct ipr_sdt_entry);
3165
3166 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3167
3168 for (i = 0; i < num_entries; i++) {
3169 if (ioa_dump->hdr.len > max_dump_size) {
3170 driver_dump->hdr.status = IPR_DUMP_STATUS_QUAL_SUCCESS;
3171 break;
3172 }
3173
3174 if (sdt->entry[i].flags & IPR_SDT_VALID_ENTRY) {
3175 sdt_word = be32_to_cpu(sdt->entry[i].start_token);
3176 if (ioa_cfg->sis64)
3177 bytes_to_copy = be32_to_cpu(sdt->entry[i].end_token);
3178 else {
3179 start_off = sdt_word & IPR_FMT2_MBX_ADDR_MASK;
3180 end_off = be32_to_cpu(sdt->entry[i].end_token);
3181
3182 if (ipr_sdt_is_fmt2(sdt_word) && sdt_word)
3183 bytes_to_copy = end_off - start_off;
3184 else
3185 valid = 0;
3186 }
3187 if (valid) {
3188 if (bytes_to_copy > max_dump_size) {
3189 sdt->entry[i].flags &= ~IPR_SDT_VALID_ENTRY;
3190 continue;
3191 }
3192
3193
3194 bytes_copied = ipr_sdt_copy(ioa_cfg, sdt_word,
3195 bytes_to_copy);
3196
3197 ioa_dump->hdr.len += bytes_copied;
3198
3199 if (bytes_copied != bytes_to_copy) {
3200 driver_dump->hdr.status = IPR_DUMP_STATUS_QUAL_SUCCESS;
3201 break;
3202 }
3203 }
3204 }
3205 }
3206
3207 dev_err(&ioa_cfg->pdev->dev, "Dump of IOA completed.\n");
3208
3209
3210 driver_dump->hdr.len += ioa_dump->hdr.len;
3211 wmb();
3212 ioa_cfg->sdt_state = DUMP_OBTAINED;
3213 LEAVE;
3214}
3215
3216#else
3217#define ipr_get_ioa_dump(ioa_cfg, dump) do { } while (0)
3218#endif
3219
3220
3221
3222
3223
3224
3225
3226
3227static void ipr_release_dump(struct kref *kref)
3228{
3229 struct ipr_dump *dump = container_of(kref, struct ipr_dump, kref);
3230 struct ipr_ioa_cfg *ioa_cfg = dump->ioa_cfg;
3231 unsigned long lock_flags = 0;
3232 int i;
3233
3234 ENTER;
3235 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3236 ioa_cfg->dump = NULL;
3237 ioa_cfg->sdt_state = INACTIVE;
3238 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3239
3240 for (i = 0; i < dump->ioa_dump.next_page_index; i++)
3241 free_page((unsigned long) dump->ioa_dump.ioa_data[i]);
3242
3243 vfree(dump->ioa_dump.ioa_data);
3244 kfree(dump);
3245 LEAVE;
3246}
3247
3248
3249
3250
3251
3252
3253
3254
3255
3256
3257
3258
3259static void ipr_worker_thread(struct work_struct *work)
3260{
3261 unsigned long lock_flags;
3262 struct ipr_resource_entry *res;
3263 struct scsi_device *sdev;
3264 struct ipr_dump *dump;
3265 struct ipr_ioa_cfg *ioa_cfg =
3266 container_of(work, struct ipr_ioa_cfg, work_q);
3267 u8 bus, target, lun;
3268 int did_work;
3269
3270 ENTER;
3271 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3272
3273 if (ioa_cfg->sdt_state == READ_DUMP) {
3274 dump = ioa_cfg->dump;
3275 if (!dump) {
3276 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3277 return;
3278 }
3279 kref_get(&dump->kref);
3280 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3281 ipr_get_ioa_dump(ioa_cfg, dump);
3282 kref_put(&dump->kref, ipr_release_dump);
3283
3284 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3285 if (ioa_cfg->sdt_state == DUMP_OBTAINED && !ioa_cfg->dump_timeout)
3286 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
3287 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3288 return;
3289 }
3290
3291 if (!ioa_cfg->scan_enabled) {
3292 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3293 return;
3294 }
3295
3296restart:
3297 do {
3298 did_work = 0;
3299 if (!ioa_cfg->hrrq[IPR_INIT_HRRQ].allow_cmds) {
3300 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3301 return;
3302 }
3303
3304 list_for_each_entry(res, &ioa_cfg->used_res_q, queue) {
3305 if (res->del_from_ml && res->sdev) {
3306 did_work = 1;
3307 sdev = res->sdev;
3308 if (!scsi_device_get(sdev)) {
3309 if (!res->add_to_ml)
3310 list_move_tail(&res->queue, &ioa_cfg->free_res_q);
3311 else
3312 res->del_from_ml = 0;
3313 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3314 scsi_remove_device(sdev);
3315 scsi_device_put(sdev);
3316 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3317 }
3318 break;
3319 }
3320 }
3321 } while (did_work);
3322
3323 list_for_each_entry(res, &ioa_cfg->used_res_q, queue) {
3324 if (res->add_to_ml) {
3325 bus = res->bus;
3326 target = res->target;
3327 lun = res->lun;
3328 res->add_to_ml = 0;
3329 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3330 scsi_add_device(ioa_cfg->host, bus, target, lun);
3331 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3332 goto restart;
3333 }
3334 }
3335
3336 ioa_cfg->scan_done = 1;
3337 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3338 kobject_uevent(&ioa_cfg->host->shost_dev.kobj, KOBJ_CHANGE);
3339 LEAVE;
3340}
3341
3342#ifdef CONFIG_SCSI_IPR_TRACE
3343
3344
3345
3346
3347
3348
3349
3350
3351
3352
3353
3354
3355static ssize_t ipr_read_trace(struct file *filp, struct kobject *kobj,
3356 struct bin_attribute *bin_attr,
3357 char *buf, loff_t off, size_t count)
3358{
3359 struct device *dev = container_of(kobj, struct device, kobj);
3360 struct Scsi_Host *shost = class_to_shost(dev);
3361 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3362 unsigned long lock_flags = 0;
3363 ssize_t ret;
3364
3365 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3366 ret = memory_read_from_buffer(buf, count, &off, ioa_cfg->trace,
3367 IPR_TRACE_SIZE);
3368 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3369
3370 return ret;
3371}
3372
3373static struct bin_attribute ipr_trace_attr = {
3374 .attr = {
3375 .name = "trace",
3376 .mode = S_IRUGO,
3377 },
3378 .size = 0,
3379 .read = ipr_read_trace,
3380};
3381#endif
3382
3383
3384
3385
3386
3387
3388
3389
3390
3391static ssize_t ipr_show_fw_version(struct device *dev,
3392 struct device_attribute *attr, char *buf)
3393{
3394 struct Scsi_Host *shost = class_to_shost(dev);
3395 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3396 struct ipr_inquiry_page3 *ucode_vpd = &ioa_cfg->vpd_cbs->page3_data;
3397 unsigned long lock_flags = 0;
3398 int len;
3399
3400 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3401 len = snprintf(buf, PAGE_SIZE, "%02X%02X%02X%02X\n",
3402 ucode_vpd->major_release, ucode_vpd->card_type,
3403 ucode_vpd->minor_release[0],
3404 ucode_vpd->minor_release[1]);
3405 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3406 return len;
3407}
3408
3409static struct device_attribute ipr_fw_version_attr = {
3410 .attr = {
3411 .name = "fw_version",
3412 .mode = S_IRUGO,
3413 },
3414 .show = ipr_show_fw_version,
3415};
3416
3417
3418
3419
3420
3421
3422
3423
3424
3425static ssize_t ipr_show_log_level(struct device *dev,
3426 struct device_attribute *attr, char *buf)
3427{
3428 struct Scsi_Host *shost = class_to_shost(dev);
3429 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3430 unsigned long lock_flags = 0;
3431 int len;
3432
3433 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3434 len = snprintf(buf, PAGE_SIZE, "%d\n", ioa_cfg->log_level);
3435 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3436 return len;
3437}
3438
3439
3440
3441
3442
3443
3444
3445
3446
3447static ssize_t ipr_store_log_level(struct device *dev,
3448 struct device_attribute *attr,
3449 const char *buf, size_t count)
3450{
3451 struct Scsi_Host *shost = class_to_shost(dev);
3452 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3453 unsigned long lock_flags = 0;
3454
3455 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3456 ioa_cfg->log_level = simple_strtoul(buf, NULL, 10);
3457 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3458 return strlen(buf);
3459}
3460
3461static struct device_attribute ipr_log_level_attr = {
3462 .attr = {
3463 .name = "log_level",
3464 .mode = S_IRUGO | S_IWUSR,
3465 },
3466 .show = ipr_show_log_level,
3467 .store = ipr_store_log_level
3468};
3469
3470
3471
3472
3473
3474
3475
3476
3477
3478
3479
3480
3481
3482static ssize_t ipr_store_diagnostics(struct device *dev,
3483 struct device_attribute *attr,
3484 const char *buf, size_t count)
3485{
3486 struct Scsi_Host *shost = class_to_shost(dev);
3487 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3488 unsigned long lock_flags = 0;
3489 int rc = count;
3490
3491 if (!capable(CAP_SYS_ADMIN))
3492 return -EACCES;
3493
3494 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3495 while (ioa_cfg->in_reset_reload) {
3496 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3497 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
3498 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3499 }
3500
3501 ioa_cfg->errors_logged = 0;
3502 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NORMAL);
3503
3504 if (ioa_cfg->in_reset_reload) {
3505 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3506 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
3507
3508
3509 msleep(1000);
3510 } else {
3511 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3512 return -EIO;
3513 }
3514
3515 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3516 if (ioa_cfg->in_reset_reload || ioa_cfg->errors_logged)
3517 rc = -EIO;
3518 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3519
3520 return rc;
3521}
3522
3523static struct device_attribute ipr_diagnostics_attr = {
3524 .attr = {
3525 .name = "run_diagnostics",
3526 .mode = S_IWUSR,
3527 },
3528 .store = ipr_store_diagnostics
3529};
3530
3531
3532
3533
3534
3535
3536
3537
3538
3539static ssize_t ipr_show_adapter_state(struct device *dev,
3540 struct device_attribute *attr, char *buf)
3541{
3542 struct Scsi_Host *shost = class_to_shost(dev);
3543 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3544 unsigned long lock_flags = 0;
3545 int len;
3546
3547 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3548 if (ioa_cfg->hrrq[IPR_INIT_HRRQ].ioa_is_dead)
3549 len = snprintf(buf, PAGE_SIZE, "offline\n");
3550 else
3551 len = snprintf(buf, PAGE_SIZE, "online\n");
3552 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3553 return len;
3554}
3555
3556
3557
3558
3559
3560
3561
3562
3563
3564
3565
3566
3567static ssize_t ipr_store_adapter_state(struct device *dev,
3568 struct device_attribute *attr,
3569 const char *buf, size_t count)
3570{
3571 struct Scsi_Host *shost = class_to_shost(dev);
3572 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3573 unsigned long lock_flags;
3574 int result = count, i;
3575
3576 if (!capable(CAP_SYS_ADMIN))
3577 return -EACCES;
3578
3579 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3580 if (ioa_cfg->hrrq[IPR_INIT_HRRQ].ioa_is_dead &&
3581 !strncmp(buf, "online", 6)) {
3582 for (i = 0; i < ioa_cfg->hrrq_num; i++) {
3583 spin_lock(&ioa_cfg->hrrq[i]._lock);
3584 ioa_cfg->hrrq[i].ioa_is_dead = 0;
3585 spin_unlock(&ioa_cfg->hrrq[i]._lock);
3586 }
3587 wmb();
3588 ioa_cfg->reset_retries = 0;
3589 ioa_cfg->in_ioa_bringdown = 0;
3590 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
3591 }
3592 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3593 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
3594
3595 return result;
3596}
3597
3598static struct device_attribute ipr_ioa_state_attr = {
3599 .attr = {
3600 .name = "online_state",
3601 .mode = S_IRUGO | S_IWUSR,
3602 },
3603 .show = ipr_show_adapter_state,
3604 .store = ipr_store_adapter_state
3605};
3606
3607
3608
3609
3610
3611
3612
3613
3614
3615
3616
3617
3618static ssize_t ipr_store_reset_adapter(struct device *dev,
3619 struct device_attribute *attr,
3620 const char *buf, size_t count)
3621{
3622 struct Scsi_Host *shost = class_to_shost(dev);
3623 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3624 unsigned long lock_flags;
3625 int result = count;
3626
3627 if (!capable(CAP_SYS_ADMIN))
3628 return -EACCES;
3629
3630 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3631 if (!ioa_cfg->in_reset_reload)
3632 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NORMAL);
3633 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3634 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
3635
3636 return result;
3637}
3638
3639static struct device_attribute ipr_ioa_reset_attr = {
3640 .attr = {
3641 .name = "reset_host",
3642 .mode = S_IWUSR,
3643 },
3644 .store = ipr_store_reset_adapter
3645};
3646
3647static int ipr_iopoll(struct irq_poll *iop, int budget);
3648
3649
3650
3651
3652
3653
3654
3655
3656static ssize_t ipr_show_iopoll_weight(struct device *dev,
3657 struct device_attribute *attr, char *buf)
3658{
3659 struct Scsi_Host *shost = class_to_shost(dev);
3660 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3661 unsigned long lock_flags = 0;
3662 int len;
3663
3664 spin_lock_irqsave(shost->host_lock, lock_flags);
3665 len = snprintf(buf, PAGE_SIZE, "%d\n", ioa_cfg->iopoll_weight);
3666 spin_unlock_irqrestore(shost->host_lock, lock_flags);
3667
3668 return len;
3669}
3670
3671
3672
3673
3674
3675
3676
3677
3678
3679static ssize_t ipr_store_iopoll_weight(struct device *dev,
3680 struct device_attribute *attr,
3681 const char *buf, size_t count)
3682{
3683 struct Scsi_Host *shost = class_to_shost(dev);
3684 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3685 unsigned long user_iopoll_weight;
3686 unsigned long lock_flags = 0;
3687 int i;
3688
3689 if (!ioa_cfg->sis64) {
3690 dev_info(&ioa_cfg->pdev->dev, "irq_poll not supported on this adapter\n");
3691 return -EINVAL;
3692 }
3693 if (kstrtoul(buf, 10, &user_iopoll_weight))
3694 return -EINVAL;
3695
3696 if (user_iopoll_weight > 256) {
3697 dev_info(&ioa_cfg->pdev->dev, "Invalid irq_poll weight. It must be less than 256\n");
3698 return -EINVAL;
3699 }
3700
3701 if (user_iopoll_weight == ioa_cfg->iopoll_weight) {
3702 dev_info(&ioa_cfg->pdev->dev, "Current irq_poll weight has the same weight\n");
3703 return strlen(buf);
3704 }
3705
3706 if (ioa_cfg->iopoll_weight && ioa_cfg->sis64 && ioa_cfg->nvectors > 1) {
3707 for (i = 1; i < ioa_cfg->hrrq_num; i++)
3708 irq_poll_disable(&ioa_cfg->hrrq[i].iopoll);
3709 }
3710
3711 spin_lock_irqsave(shost->host_lock, lock_flags);
3712 ioa_cfg->iopoll_weight = user_iopoll_weight;
3713 if (ioa_cfg->iopoll_weight && ioa_cfg->sis64 && ioa_cfg->nvectors > 1) {
3714 for (i = 1; i < ioa_cfg->hrrq_num; i++) {
3715 irq_poll_init(&ioa_cfg->hrrq[i].iopoll,
3716 ioa_cfg->iopoll_weight, ipr_iopoll);
3717 }
3718 }
3719 spin_unlock_irqrestore(shost->host_lock, lock_flags);
3720
3721 return strlen(buf);
3722}
3723
3724static struct device_attribute ipr_iopoll_weight_attr = {
3725 .attr = {
3726 .name = "iopoll_weight",
3727 .mode = S_IRUGO | S_IWUSR,
3728 },
3729 .show = ipr_show_iopoll_weight,
3730 .store = ipr_store_iopoll_weight
3731};
3732
3733
3734
3735
3736
3737
3738
3739
3740
3741
3742
3743static struct ipr_sglist *ipr_alloc_ucode_buffer(int buf_len)
3744{
3745 int sg_size, order, bsize_elem, num_elem, i, j;
3746 struct ipr_sglist *sglist;
3747 struct scatterlist *scatterlist;
3748 struct page *page;
3749
3750
3751 sg_size = buf_len / (IPR_MAX_SGLIST - 1);
3752
3753
3754 order = get_order(sg_size);
3755
3756
3757 bsize_elem = PAGE_SIZE * (1 << order);
3758
3759
3760 if (buf_len % bsize_elem)
3761 num_elem = (buf_len / bsize_elem) + 1;
3762 else
3763 num_elem = buf_len / bsize_elem;
3764
3765
3766 sglist = kzalloc(sizeof(struct ipr_sglist) +
3767 (sizeof(struct scatterlist) * (num_elem - 1)),
3768 GFP_KERNEL);
3769
3770 if (sglist == NULL) {
3771 ipr_trace;
3772 return NULL;
3773 }
3774
3775 scatterlist = sglist->scatterlist;
3776 sg_init_table(scatterlist, num_elem);
3777
3778 sglist->order = order;
3779 sglist->num_sg = num_elem;
3780
3781
3782 for (i = 0; i < num_elem; i++) {
3783 page = alloc_pages(GFP_KERNEL, order);
3784 if (!page) {
3785 ipr_trace;
3786
3787
3788 for (j = i - 1; j >= 0; j--)
3789 __free_pages(sg_page(&scatterlist[j]), order);
3790 kfree(sglist);
3791 return NULL;
3792 }
3793
3794 sg_set_page(&scatterlist[i], page, 0, 0);
3795 }
3796
3797 return sglist;
3798}
3799
3800
3801
3802
3803
3804
3805
3806
3807
3808
3809
3810static void ipr_free_ucode_buffer(struct ipr_sglist *sglist)
3811{
3812 int i;
3813
3814 for (i = 0; i < sglist->num_sg; i++)
3815 __free_pages(sg_page(&sglist->scatterlist[i]), sglist->order);
3816
3817 kfree(sglist);
3818}
3819
3820
3821
3822
3823
3824
3825
3826
3827
3828
3829
3830
3831
3832static int ipr_copy_ucode_buffer(struct ipr_sglist *sglist,
3833 u8 *buffer, u32 len)
3834{
3835 int bsize_elem, i, result = 0;
3836 struct scatterlist *scatterlist;
3837 void *kaddr;
3838
3839
3840 bsize_elem = PAGE_SIZE * (1 << sglist->order);
3841
3842 scatterlist = sglist->scatterlist;
3843
3844 for (i = 0; i < (len / bsize_elem); i++, buffer += bsize_elem) {
3845 struct page *page = sg_page(&scatterlist[i]);
3846
3847 kaddr = kmap(page);
3848 memcpy(kaddr, buffer, bsize_elem);
3849 kunmap(page);
3850
3851 scatterlist[i].length = bsize_elem;
3852
3853 if (result != 0) {
3854 ipr_trace;
3855 return result;
3856 }
3857 }
3858
3859 if (len % bsize_elem) {
3860 struct page *page = sg_page(&scatterlist[i]);
3861
3862 kaddr = kmap(page);
3863 memcpy(kaddr, buffer, len % bsize_elem);
3864 kunmap(page);
3865
3866 scatterlist[i].length = len % bsize_elem;
3867 }
3868
3869 sglist->buffer_len = len;
3870 return result;
3871}
3872
3873
3874
3875
3876
3877
3878
3879
3880
3881static void ipr_build_ucode_ioadl64(struct ipr_cmnd *ipr_cmd,
3882 struct ipr_sglist *sglist)
3883{
3884 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
3885 struct ipr_ioadl64_desc *ioadl64 = ipr_cmd->i.ioadl64;
3886 struct scatterlist *scatterlist = sglist->scatterlist;
3887 int i;
3888
3889 ipr_cmd->dma_use_sg = sglist->num_dma_sg;
3890 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_WRITE_NOT_READ;
3891 ioarcb->data_transfer_length = cpu_to_be32(sglist->buffer_len);
3892
3893 ioarcb->ioadl_len =
3894 cpu_to_be32(sizeof(struct ipr_ioadl64_desc) * ipr_cmd->dma_use_sg);
3895 for (i = 0; i < ipr_cmd->dma_use_sg; i++) {
3896 ioadl64[i].flags = cpu_to_be32(IPR_IOADL_FLAGS_WRITE);
3897 ioadl64[i].data_len = cpu_to_be32(sg_dma_len(&scatterlist[i]));
3898 ioadl64[i].address = cpu_to_be64(sg_dma_address(&scatterlist[i]));
3899 }
3900
3901 ioadl64[i-1].flags |= cpu_to_be32(IPR_IOADL_FLAGS_LAST);
3902}
3903
3904
3905
3906
3907
3908
3909
3910
3911
3912static void ipr_build_ucode_ioadl(struct ipr_cmnd *ipr_cmd,
3913 struct ipr_sglist *sglist)
3914{
3915 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
3916 struct ipr_ioadl_desc *ioadl = ipr_cmd->i.ioadl;
3917 struct scatterlist *scatterlist = sglist->scatterlist;
3918 int i;
3919
3920 ipr_cmd->dma_use_sg = sglist->num_dma_sg;
3921 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_WRITE_NOT_READ;
3922 ioarcb->data_transfer_length = cpu_to_be32(sglist->buffer_len);
3923
3924 ioarcb->ioadl_len =
3925 cpu_to_be32(sizeof(struct ipr_ioadl_desc) * ipr_cmd->dma_use_sg);
3926
3927 for (i = 0; i < ipr_cmd->dma_use_sg; i++) {
3928 ioadl[i].flags_and_data_len =
3929 cpu_to_be32(IPR_IOADL_FLAGS_WRITE | sg_dma_len(&scatterlist[i]));
3930 ioadl[i].address =
3931 cpu_to_be32(sg_dma_address(&scatterlist[i]));
3932 }
3933
3934 ioadl[i-1].flags_and_data_len |=
3935 cpu_to_be32(IPR_IOADL_FLAGS_LAST);
3936}
3937
3938
3939
3940
3941
3942
3943
3944
3945
3946
3947
3948static int ipr_update_ioa_ucode(struct ipr_ioa_cfg *ioa_cfg,
3949 struct ipr_sglist *sglist)
3950{
3951 unsigned long lock_flags;
3952
3953 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3954 while (ioa_cfg->in_reset_reload) {
3955 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3956 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
3957 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3958 }
3959
3960 if (ioa_cfg->ucode_sglist) {
3961 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3962 dev_err(&ioa_cfg->pdev->dev,
3963 "Microcode download already in progress\n");
3964 return -EIO;
3965 }
3966
3967 sglist->num_dma_sg = dma_map_sg(&ioa_cfg->pdev->dev,
3968 sglist->scatterlist, sglist->num_sg,
3969 DMA_TO_DEVICE);
3970
3971 if (!sglist->num_dma_sg) {
3972 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3973 dev_err(&ioa_cfg->pdev->dev,
3974 "Failed to map microcode download buffer!\n");
3975 return -EIO;
3976 }
3977
3978 ioa_cfg->ucode_sglist = sglist;
3979 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NORMAL);
3980 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3981 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
3982
3983 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3984 ioa_cfg->ucode_sglist = NULL;
3985 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3986 return 0;
3987}
3988
3989
3990
3991
3992
3993
3994
3995
3996
3997
3998
3999
4000static ssize_t ipr_store_update_fw(struct device *dev,
4001 struct device_attribute *attr,
4002 const char *buf, size_t count)
4003{
4004 struct Scsi_Host *shost = class_to_shost(dev);
4005 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
4006 struct ipr_ucode_image_header *image_hdr;
4007 const struct firmware *fw_entry;
4008 struct ipr_sglist *sglist;
4009 char fname[100];
4010 char *src;
4011 char *endline;
4012 int result, dnld_size;
4013
4014 if (!capable(CAP_SYS_ADMIN))
4015 return -EACCES;
4016
4017 snprintf(fname, sizeof(fname), "%s", buf);
4018
4019 endline = strchr(fname, '\n');
4020 if (endline)
4021 *endline = '\0';
4022
4023 if (request_firmware(&fw_entry, fname, &ioa_cfg->pdev->dev)) {
4024 dev_err(&ioa_cfg->pdev->dev, "Firmware file %s not found\n", fname);
4025 return -EIO;
4026 }
4027
4028 image_hdr = (struct ipr_ucode_image_header *)fw_entry->data;
4029
4030 src = (u8 *)image_hdr + be32_to_cpu(image_hdr->header_length);
4031 dnld_size = fw_entry->size - be32_to_cpu(image_hdr->header_length);
4032 sglist = ipr_alloc_ucode_buffer(dnld_size);
4033
4034 if (!sglist) {
4035 dev_err(&ioa_cfg->pdev->dev, "Microcode buffer allocation failed\n");
4036 release_firmware(fw_entry);
4037 return -ENOMEM;
4038 }
4039
4040 result = ipr_copy_ucode_buffer(sglist, src, dnld_size);
4041
4042 if (result) {
4043 dev_err(&ioa_cfg->pdev->dev,
4044 "Microcode buffer copy to DMA buffer failed\n");
4045 goto out;
4046 }
4047
4048 ipr_info("Updating microcode, please be patient. This may take up to 30 minutes.\n");
4049
4050 result = ipr_update_ioa_ucode(ioa_cfg, sglist);
4051
4052 if (!result)
4053 result = count;
4054out:
4055 ipr_free_ucode_buffer(sglist);
4056 release_firmware(fw_entry);
4057 return result;
4058}
4059
4060static struct device_attribute ipr_update_fw_attr = {
4061 .attr = {
4062 .name = "update_fw",
4063 .mode = S_IWUSR,
4064 },
4065 .store = ipr_store_update_fw
4066};
4067
4068
4069
4070
4071
4072
4073
4074
4075
4076static ssize_t ipr_show_fw_type(struct device *dev,
4077 struct device_attribute *attr, char *buf)
4078{
4079 struct Scsi_Host *shost = class_to_shost(dev);
4080 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
4081 unsigned long lock_flags = 0;
4082 int len;
4083
4084 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4085 len = snprintf(buf, PAGE_SIZE, "%d\n", ioa_cfg->sis64);
4086 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4087 return len;
4088}
4089
4090static struct device_attribute ipr_ioa_fw_type_attr = {
4091 .attr = {
4092 .name = "fw_type",
4093 .mode = S_IRUGO,
4094 },
4095 .show = ipr_show_fw_type
4096};
4097
4098static struct device_attribute *ipr_ioa_attrs[] = {
4099 &ipr_fw_version_attr,
4100 &ipr_log_level_attr,
4101 &ipr_diagnostics_attr,
4102 &ipr_ioa_state_attr,
4103 &ipr_ioa_reset_attr,
4104 &ipr_update_fw_attr,
4105 &ipr_ioa_fw_type_attr,
4106 &ipr_iopoll_weight_attr,
4107 NULL,
4108};
4109
4110#ifdef CONFIG_SCSI_IPR_DUMP
4111
4112
4113
4114
4115
4116
4117
4118
4119
4120
4121
4122
4123static ssize_t ipr_read_dump(struct file *filp, struct kobject *kobj,
4124 struct bin_attribute *bin_attr,
4125 char *buf, loff_t off, size_t count)
4126{
4127 struct device *cdev = container_of(kobj, struct device, kobj);
4128 struct Scsi_Host *shost = class_to_shost(cdev);
4129 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
4130 struct ipr_dump *dump;
4131 unsigned long lock_flags = 0;
4132 char *src;
4133 int len, sdt_end;
4134 size_t rc = count;
4135
4136 if (!capable(CAP_SYS_ADMIN))
4137 return -EACCES;
4138
4139 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4140 dump = ioa_cfg->dump;
4141
4142 if (ioa_cfg->sdt_state != DUMP_OBTAINED || !dump) {
4143 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4144 return 0;
4145 }
4146 kref_get(&dump->kref);
4147 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4148
4149 if (off > dump->driver_dump.hdr.len) {
4150 kref_put(&dump->kref, ipr_release_dump);
4151 return 0;
4152 }
4153
4154 if (off + count > dump->driver_dump.hdr.len) {
4155 count = dump->driver_dump.hdr.len - off;
4156 rc = count;
4157 }
4158
4159 if (count && off < sizeof(dump->driver_dump)) {
4160 if (off + count > sizeof(dump->driver_dump))
4161 len = sizeof(dump->driver_dump) - off;
4162 else
4163 len = count;
4164 src = (u8 *)&dump->driver_dump + off;
4165 memcpy(buf, src, len);
4166 buf += len;
4167 off += len;
4168 count -= len;
4169 }
4170
4171 off -= sizeof(dump->driver_dump);
4172
4173 if (ioa_cfg->sis64)
4174 sdt_end = offsetof(struct ipr_ioa_dump, sdt.entry) +
4175 (be32_to_cpu(dump->ioa_dump.sdt.hdr.num_entries_used) *
4176 sizeof(struct ipr_sdt_entry));
4177 else
4178 sdt_end = offsetof(struct ipr_ioa_dump, sdt.entry) +
4179 (IPR_FMT2_NUM_SDT_ENTRIES * sizeof(struct ipr_sdt_entry));
4180
4181 if (count && off < sdt_end) {
4182 if (off + count > sdt_end)
4183 len = sdt_end - off;
4184 else
4185 len = count;
4186 src = (u8 *)&dump->ioa_dump + off;
4187 memcpy(buf, src, len);
4188 buf += len;
4189 off += len;
4190 count -= len;
4191 }
4192
4193 off -= sdt_end;
4194
4195 while (count) {
4196 if ((off & PAGE_MASK) != ((off + count) & PAGE_MASK))
4197 len = PAGE_ALIGN(off) - off;
4198 else
4199 len = count;
4200 src = (u8 *)dump->ioa_dump.ioa_data[(off & PAGE_MASK) >> PAGE_SHIFT];
4201 src += off & ~PAGE_MASK;
4202 memcpy(buf, src, len);
4203 buf += len;
4204 off += len;
4205 count -= len;
4206 }
4207
4208 kref_put(&dump->kref, ipr_release_dump);
4209 return rc;
4210}
4211
4212
4213
4214
4215
4216
4217
4218
4219static int ipr_alloc_dump(struct ipr_ioa_cfg *ioa_cfg)
4220{
4221 struct ipr_dump *dump;
4222 __be32 **ioa_data;
4223 unsigned long lock_flags = 0;
4224
4225 dump = kzalloc(sizeof(struct ipr_dump), GFP_KERNEL);
4226
4227 if (!dump) {
4228 ipr_err("Dump memory allocation failed\n");
4229 return -ENOMEM;
4230 }
4231
4232 if (ioa_cfg->sis64)
4233 ioa_data = vmalloc(IPR_FMT3_MAX_NUM_DUMP_PAGES * sizeof(__be32 *));
4234 else
4235 ioa_data = vmalloc(IPR_FMT2_MAX_NUM_DUMP_PAGES * sizeof(__be32 *));
4236
4237 if (!ioa_data) {
4238 ipr_err("Dump memory allocation failed\n");
4239 kfree(dump);
4240 return -ENOMEM;
4241 }
4242
4243 dump->ioa_dump.ioa_data = ioa_data;
4244
4245 kref_init(&dump->kref);
4246 dump->ioa_cfg = ioa_cfg;
4247
4248 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4249
4250 if (INACTIVE != ioa_cfg->sdt_state) {
4251 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4252 vfree(dump->ioa_dump.ioa_data);
4253 kfree(dump);
4254 return 0;
4255 }
4256
4257 ioa_cfg->dump = dump;
4258 ioa_cfg->sdt_state = WAIT_FOR_DUMP;
4259 if (ioa_cfg->hrrq[IPR_INIT_HRRQ].ioa_is_dead && !ioa_cfg->dump_taken) {
4260 ioa_cfg->dump_taken = 1;
4261 schedule_work(&ioa_cfg->work_q);
4262 }
4263 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4264
4265 return 0;
4266}
4267
4268
4269
4270
4271
4272
4273
4274
4275static int ipr_free_dump(struct ipr_ioa_cfg *ioa_cfg)
4276{
4277 struct ipr_dump *dump;
4278 unsigned long lock_flags = 0;
4279
4280 ENTER;
4281
4282 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4283 dump = ioa_cfg->dump;
4284 if (!dump) {
4285 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4286 return 0;
4287 }
4288
4289 ioa_cfg->dump = NULL;
4290 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4291
4292 kref_put(&dump->kref, ipr_release_dump);
4293
4294 LEAVE;
4295 return 0;
4296}
4297
4298
4299
4300
4301
4302
4303
4304
4305
4306
4307
4308
4309
4310static ssize_t ipr_write_dump(struct file *filp, struct kobject *kobj,
4311 struct bin_attribute *bin_attr,
4312 char *buf, loff_t off, size_t count)
4313{
4314 struct device *cdev = container_of(kobj, struct device, kobj);
4315 struct Scsi_Host *shost = class_to_shost(cdev);
4316 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
4317 int rc;
4318
4319 if (!capable(CAP_SYS_ADMIN))
4320 return -EACCES;
4321
4322 if (buf[0] == '1')
4323 rc = ipr_alloc_dump(ioa_cfg);
4324 else if (buf[0] == '0')
4325 rc = ipr_free_dump(ioa_cfg);
4326 else
4327 return -EINVAL;
4328
4329 if (rc)
4330 return rc;
4331 else
4332 return count;
4333}
4334
4335static struct bin_attribute ipr_dump_attr = {
4336 .attr = {
4337 .name = "dump",
4338 .mode = S_IRUSR | S_IWUSR,
4339 },
4340 .size = 0,
4341 .read = ipr_read_dump,
4342 .write = ipr_write_dump
4343};
4344#else
4345static int ipr_free_dump(struct ipr_ioa_cfg *ioa_cfg) { return 0; };
4346#endif
4347
4348
4349
4350
4351
4352
4353
4354
4355
4356
4357static int ipr_change_queue_depth(struct scsi_device *sdev, int qdepth)
4358{
4359 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)sdev->host->hostdata;
4360 struct ipr_resource_entry *res;
4361 unsigned long lock_flags = 0;
4362
4363 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4364 res = (struct ipr_resource_entry *)sdev->hostdata;
4365
4366 if (res && ipr_is_gata(res) && qdepth > IPR_MAX_CMD_PER_ATA_LUN)
4367 qdepth = IPR_MAX_CMD_PER_ATA_LUN;
4368 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4369
4370 scsi_change_queue_depth(sdev, qdepth);
4371 return sdev->queue_depth;
4372}
4373
4374
4375
4376
4377
4378
4379
4380
4381
4382
4383static ssize_t ipr_show_adapter_handle(struct device *dev, struct device_attribute *attr, char *buf)
4384{
4385 struct scsi_device *sdev = to_scsi_device(dev);
4386 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)sdev->host->hostdata;
4387 struct ipr_resource_entry *res;
4388 unsigned long lock_flags = 0;
4389 ssize_t len = -ENXIO;
4390
4391 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4392 res = (struct ipr_resource_entry *)sdev->hostdata;
4393 if (res)
4394 len = snprintf(buf, PAGE_SIZE, "%08X\n", res->res_handle);
4395 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4396 return len;
4397}
4398
4399static struct device_attribute ipr_adapter_handle_attr = {
4400 .attr = {
4401 .name = "adapter_handle",
4402 .mode = S_IRUSR,
4403 },
4404 .show = ipr_show_adapter_handle
4405};
4406
4407
4408
4409
4410
4411
4412
4413
4414
4415
4416
4417static ssize_t ipr_show_resource_path(struct device *dev, struct device_attribute *attr, char *buf)
4418{
4419 struct scsi_device *sdev = to_scsi_device(dev);
4420 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)sdev->host->hostdata;
4421 struct ipr_resource_entry *res;
4422 unsigned long lock_flags = 0;
4423 ssize_t len = -ENXIO;
4424 char buffer[IPR_MAX_RES_PATH_LENGTH];
4425
4426 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4427 res = (struct ipr_resource_entry *)sdev->hostdata;
4428 if (res && ioa_cfg->sis64)
4429 len = snprintf(buf, PAGE_SIZE, "%s\n",
4430 __ipr_format_res_path(res->res_path, buffer,
4431 sizeof(buffer)));
4432 else if (res)
4433 len = snprintf(buf, PAGE_SIZE, "%d:%d:%d:%d\n", ioa_cfg->host->host_no,
4434 res->bus, res->target, res->lun);
4435
4436 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4437 return len;
4438}
4439
4440static struct device_attribute ipr_resource_path_attr = {
4441 .attr = {
4442 .name = "resource_path",
4443 .mode = S_IRUGO,
4444 },
4445 .show = ipr_show_resource_path
4446};
4447
4448
4449
4450
4451
4452
4453
4454
4455
4456
4457static ssize_t ipr_show_device_id(struct device *dev, struct device_attribute *attr, char *buf)
4458{
4459 struct scsi_device *sdev = to_scsi_device(dev);
4460 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)sdev->host->hostdata;
4461 struct ipr_resource_entry *res;
4462 unsigned long lock_flags = 0;
4463 ssize_t len = -ENXIO;
4464
4465 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4466 res = (struct ipr_resource_entry *)sdev->hostdata;
4467 if (res && ioa_cfg->sis64)
4468 len = snprintf(buf, PAGE_SIZE, "0x%llx\n", be64_to_cpu(res->dev_id));
4469 else if (res)
4470 len = snprintf(buf, PAGE_SIZE, "0x%llx\n", res->lun_wwn);
4471
4472 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4473 return len;
4474}
4475
4476static struct device_attribute ipr_device_id_attr = {
4477 .attr = {
4478 .name = "device_id",
4479 .mode = S_IRUGO,
4480 },
4481 .show = ipr_show_device_id
4482};
4483
4484
4485
4486
4487
4488
4489
4490
4491
4492
4493static ssize_t ipr_show_resource_type(struct device *dev, struct device_attribute *attr, char *buf)
4494{
4495 struct scsi_device *sdev = to_scsi_device(dev);
4496 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)sdev->host->hostdata;
4497 struct ipr_resource_entry *res;
4498 unsigned long lock_flags = 0;
4499 ssize_t len = -ENXIO;
4500
4501 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4502 res = (struct ipr_resource_entry *)sdev->hostdata;
4503
4504 if (res)
4505 len = snprintf(buf, PAGE_SIZE, "%x\n", res->type);
4506
4507 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4508 return len;
4509}
4510
4511static struct device_attribute ipr_resource_type_attr = {
4512 .attr = {
4513 .name = "resource_type",
4514 .mode = S_IRUGO,
4515 },
4516 .show = ipr_show_resource_type
4517};
4518
4519
4520
4521
4522
4523
4524
4525
4526
4527static ssize_t ipr_show_raw_mode(struct device *dev,
4528 struct device_attribute *attr, char *buf)
4529{
4530 struct scsi_device *sdev = to_scsi_device(dev);
4531 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)sdev->host->hostdata;
4532 struct ipr_resource_entry *res;
4533 unsigned long lock_flags = 0;
4534 ssize_t len;
4535
4536 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4537 res = (struct ipr_resource_entry *)sdev->hostdata;
4538 if (res)
4539 len = snprintf(buf, PAGE_SIZE, "%d\n", res->raw_mode);
4540 else
4541 len = -ENXIO;
4542 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4543 return len;
4544}
4545
4546
4547
4548
4549
4550
4551
4552
4553
4554static ssize_t ipr_store_raw_mode(struct device *dev,
4555 struct device_attribute *attr,
4556 const char *buf, size_t count)
4557{
4558 struct scsi_device *sdev = to_scsi_device(dev);
4559 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)sdev->host->hostdata;
4560 struct ipr_resource_entry *res;
4561 unsigned long lock_flags = 0;
4562 ssize_t len;
4563
4564 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4565 res = (struct ipr_resource_entry *)sdev->hostdata;
4566 if (res) {
4567 if (ipr_is_af_dasd_device(res)) {
4568 res->raw_mode = simple_strtoul(buf, NULL, 10);
4569 len = strlen(buf);
4570 if (res->sdev)
4571 sdev_printk(KERN_INFO, res->sdev, "raw mode is %s\n",
4572 res->raw_mode ? "enabled" : "disabled");
4573 } else
4574 len = -EINVAL;
4575 } else
4576 len = -ENXIO;
4577 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4578 return len;
4579}
4580
4581static struct device_attribute ipr_raw_mode_attr = {
4582 .attr = {
4583 .name = "raw_mode",
4584 .mode = S_IRUGO | S_IWUSR,
4585 },
4586 .show = ipr_show_raw_mode,
4587 .store = ipr_store_raw_mode
4588};
4589
4590static struct device_attribute *ipr_dev_attrs[] = {
4591 &ipr_adapter_handle_attr,
4592 &ipr_resource_path_attr,
4593 &ipr_device_id_attr,
4594 &ipr_resource_type_attr,
4595 &ipr_raw_mode_attr,
4596 NULL,
4597};
4598
4599
4600
4601
4602
4603
4604
4605
4606
4607
4608
4609
4610
4611
4612
4613static int ipr_biosparam(struct scsi_device *sdev,
4614 struct block_device *block_device,
4615 sector_t capacity, int *parm)
4616{
4617 int heads, sectors;
4618 sector_t cylinders;
4619
4620 heads = 128;
4621 sectors = 32;
4622
4623 cylinders = capacity;
4624 sector_div(cylinders, (128 * 32));
4625
4626
4627 parm[0] = heads;
4628 parm[1] = sectors;
4629 parm[2] = cylinders;
4630
4631 return 0;
4632}
4633
4634
4635
4636
4637
4638
4639
4640
4641static struct ipr_resource_entry *ipr_find_starget(struct scsi_target *starget)
4642{
4643 struct Scsi_Host *shost = dev_to_shost(&starget->dev);
4644 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *) shost->hostdata;
4645 struct ipr_resource_entry *res;
4646
4647 list_for_each_entry(res, &ioa_cfg->used_res_q, queue) {
4648 if ((res->bus == starget->channel) &&
4649 (res->target == starget->id)) {
4650 return res;
4651 }
4652 }
4653
4654 return NULL;
4655}
4656
4657static struct ata_port_info sata_port_info;
4658
4659
4660
4661
4662
4663
4664
4665
4666
4667
4668
4669static int ipr_target_alloc(struct scsi_target *starget)
4670{
4671 struct Scsi_Host *shost = dev_to_shost(&starget->dev);
4672 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *) shost->hostdata;
4673 struct ipr_sata_port *sata_port;
4674 struct ata_port *ap;
4675 struct ipr_resource_entry *res;
4676 unsigned long lock_flags;
4677
4678 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4679 res = ipr_find_starget(starget);
4680 starget->hostdata = NULL;
4681
4682 if (res && ipr_is_gata(res)) {
4683 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4684 sata_port = kzalloc(sizeof(*sata_port), GFP_KERNEL);
4685 if (!sata_port)
4686 return -ENOMEM;
4687
4688 ap = ata_sas_port_alloc(&ioa_cfg->ata_host, &sata_port_info, shost);
4689 if (ap) {
4690 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4691 sata_port->ioa_cfg = ioa_cfg;
4692 sata_port->ap = ap;
4693 sata_port->res = res;
4694
4695 res->sata_port = sata_port;
4696 ap->private_data = sata_port;
4697 starget->hostdata = sata_port;
4698 } else {
4699 kfree(sata_port);
4700 return -ENOMEM;
4701 }
4702 }
4703 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4704
4705 return 0;
4706}
4707
4708
4709
4710
4711
4712
4713
4714
4715
4716static void ipr_target_destroy(struct scsi_target *starget)
4717{
4718 struct ipr_sata_port *sata_port = starget->hostdata;
4719 struct Scsi_Host *shost = dev_to_shost(&starget->dev);
4720 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *) shost->hostdata;
4721
4722 if (ioa_cfg->sis64) {
4723 if (!ipr_find_starget(starget)) {
4724 if (starget->channel == IPR_ARRAY_VIRTUAL_BUS)
4725 clear_bit(starget->id, ioa_cfg->array_ids);
4726 else if (starget->channel == IPR_VSET_VIRTUAL_BUS)
4727 clear_bit(starget->id, ioa_cfg->vset_ids);
4728 else if (starget->channel == 0)
4729 clear_bit(starget->id, ioa_cfg->target_ids);
4730 }
4731 }
4732
4733 if (sata_port) {
4734 starget->hostdata = NULL;
4735 ata_sas_port_destroy(sata_port->ap);
4736 kfree(sata_port);
4737 }
4738}
4739
4740
4741
4742
4743
4744
4745
4746
4747static struct ipr_resource_entry *ipr_find_sdev(struct scsi_device *sdev)
4748{
4749 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *) sdev->host->hostdata;
4750 struct ipr_resource_entry *res;
4751
4752 list_for_each_entry(res, &ioa_cfg->used_res_q, queue) {
4753 if ((res->bus == sdev->channel) &&
4754 (res->target == sdev->id) &&
4755 (res->lun == sdev->lun))
4756 return res;
4757 }
4758
4759 return NULL;
4760}
4761
4762
4763
4764
4765
4766
4767
4768
4769static void ipr_slave_destroy(struct scsi_device *sdev)
4770{
4771 struct ipr_resource_entry *res;
4772 struct ipr_ioa_cfg *ioa_cfg;
4773 unsigned long lock_flags = 0;
4774
4775 ioa_cfg = (struct ipr_ioa_cfg *) sdev->host->hostdata;
4776
4777 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4778 res = (struct ipr_resource_entry *) sdev->hostdata;
4779 if (res) {
4780 if (res->sata_port)
4781 res->sata_port->ap->link.device[0].class = ATA_DEV_NONE;
4782 sdev->hostdata = NULL;
4783 res->sdev = NULL;
4784 res->sata_port = NULL;
4785 }
4786 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4787}
4788
4789
4790
4791
4792
4793
4794
4795
4796
4797
4798static int ipr_slave_configure(struct scsi_device *sdev)
4799{
4800 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *) sdev->host->hostdata;
4801 struct ipr_resource_entry *res;
4802 struct ata_port *ap = NULL;
4803 unsigned long lock_flags = 0;
4804 char buffer[IPR_MAX_RES_PATH_LENGTH];
4805
4806 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4807 res = sdev->hostdata;
4808 if (res) {
4809 if (ipr_is_af_dasd_device(res))
4810 sdev->type = TYPE_RAID;
4811 if (ipr_is_af_dasd_device(res) || ipr_is_ioa_resource(res)) {
4812 sdev->scsi_level = 4;
4813 sdev->no_uld_attach = 1;
4814 }
4815 if (ipr_is_vset_device(res)) {
4816 sdev->scsi_level = SCSI_SPC_3;
4817 blk_queue_rq_timeout(sdev->request_queue,
4818 IPR_VSET_RW_TIMEOUT);
4819 blk_queue_max_hw_sectors(sdev->request_queue, IPR_VSET_MAX_SECTORS);
4820 }
4821 if (ipr_is_gata(res) && res->sata_port)
4822 ap = res->sata_port->ap;
4823 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4824
4825 if (ap) {
4826 scsi_change_queue_depth(sdev, IPR_MAX_CMD_PER_ATA_LUN);
4827 ata_sas_slave_configure(sdev, ap);
4828 }
4829
4830 if (ioa_cfg->sis64)
4831 sdev_printk(KERN_INFO, sdev, "Resource path: %s\n",
4832 ipr_format_res_path(ioa_cfg,
4833 res->res_path, buffer, sizeof(buffer)));
4834 return 0;
4835 }
4836 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4837 return 0;
4838}
4839
4840
4841
4842
4843
4844
4845
4846
4847
4848
4849
4850static int ipr_ata_slave_alloc(struct scsi_device *sdev)
4851{
4852 struct ipr_sata_port *sata_port = NULL;
4853 int rc = -ENXIO;
4854
4855 ENTER;
4856 if (sdev->sdev_target)
4857 sata_port = sdev->sdev_target->hostdata;
4858 if (sata_port) {
4859 rc = ata_sas_port_init(sata_port->ap);
4860 if (rc == 0)
4861 rc = ata_sas_sync_probe(sata_port->ap);
4862 }
4863
4864 if (rc)
4865 ipr_slave_destroy(sdev);
4866
4867 LEAVE;
4868 return rc;
4869}
4870
4871
4872
4873
4874
4875
4876
4877
4878
4879
4880
4881
4882
4883static int ipr_slave_alloc(struct scsi_device *sdev)
4884{
4885 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *) sdev->host->hostdata;
4886 struct ipr_resource_entry *res;
4887 unsigned long lock_flags;
4888 int rc = -ENXIO;
4889
4890 sdev->hostdata = NULL;
4891
4892 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4893
4894 res = ipr_find_sdev(sdev);
4895 if (res) {
4896 res->sdev = sdev;
4897 res->add_to_ml = 0;
4898 res->in_erp = 0;
4899 sdev->hostdata = res;
4900 if (!ipr_is_naca_model(res))
4901 res->needs_sync_complete = 1;
4902 rc = 0;
4903 if (ipr_is_gata(res)) {
4904 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4905 return ipr_ata_slave_alloc(sdev);
4906 }
4907 }
4908
4909 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4910
4911 return rc;
4912}
4913
4914
4915
4916
4917
4918
4919
4920
4921
4922static int ipr_match_lun(struct ipr_cmnd *ipr_cmd, void *device)
4923{
4924 if (ipr_cmd->scsi_cmd && ipr_cmd->scsi_cmd->device == device)
4925 return 1;
4926 return 0;
4927}
4928
4929
4930
4931
4932
4933
4934
4935
4936
4937
4938static int ipr_wait_for_ops(struct ipr_ioa_cfg *ioa_cfg, void *device,
4939 int (*match)(struct ipr_cmnd *, void *))
4940{
4941 struct ipr_cmnd *ipr_cmd;
4942 int wait;
4943 unsigned long flags;
4944 struct ipr_hrr_queue *hrrq;
4945 signed long timeout = IPR_ABORT_TASK_TIMEOUT;
4946 DECLARE_COMPLETION_ONSTACK(comp);
4947
4948 ENTER;
4949 do {
4950 wait = 0;
4951
4952 for_each_hrrq(hrrq, ioa_cfg) {
4953 spin_lock_irqsave(hrrq->lock, flags);
4954 list_for_each_entry(ipr_cmd, &hrrq->hrrq_pending_q, queue) {
4955 if (match(ipr_cmd, device)) {
4956 ipr_cmd->eh_comp = ∁
4957 wait++;
4958 }
4959 }
4960 spin_unlock_irqrestore(hrrq->lock, flags);
4961 }
4962
4963 if (wait) {
4964 timeout = wait_for_completion_timeout(&comp, timeout);
4965
4966 if (!timeout) {
4967 wait = 0;
4968
4969 for_each_hrrq(hrrq, ioa_cfg) {
4970 spin_lock_irqsave(hrrq->lock, flags);
4971 list_for_each_entry(ipr_cmd, &hrrq->hrrq_pending_q, queue) {
4972 if (match(ipr_cmd, device)) {
4973 ipr_cmd->eh_comp = NULL;
4974 wait++;
4975 }
4976 }
4977 spin_unlock_irqrestore(hrrq->lock, flags);
4978 }
4979
4980 if (wait)
4981 dev_err(&ioa_cfg->pdev->dev, "Timed out waiting for aborted commands\n");
4982 LEAVE;
4983 return wait ? FAILED : SUCCESS;
4984 }
4985 }
4986 } while (wait);
4987
4988 LEAVE;
4989 return SUCCESS;
4990}
4991
4992static int ipr_eh_host_reset(struct scsi_cmnd *cmd)
4993{
4994 struct ipr_ioa_cfg *ioa_cfg;
4995 unsigned long lock_flags = 0;
4996 int rc = SUCCESS;
4997
4998 ENTER;
4999 ioa_cfg = (struct ipr_ioa_cfg *) cmd->device->host->hostdata;
5000 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
5001
5002 if (!ioa_cfg->in_reset_reload && !ioa_cfg->hrrq[IPR_INIT_HRRQ].ioa_is_dead) {
5003 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_ABBREV);
5004 dev_err(&ioa_cfg->pdev->dev,
5005 "Adapter being reset as a result of error recovery.\n");
5006
5007 if (WAIT_FOR_DUMP == ioa_cfg->sdt_state)
5008 ioa_cfg->sdt_state = GET_DUMP;
5009 }
5010
5011 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
5012 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
5013 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
5014
5015
5016
5017 if (ioa_cfg->hrrq[IPR_INIT_HRRQ].ioa_is_dead) {
5018 ipr_trace;
5019 rc = FAILED;
5020 }
5021
5022 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
5023 LEAVE;
5024 return rc;
5025}
5026
5027
5028
5029
5030
5031
5032
5033
5034
5035
5036
5037
5038
5039
5040
5041static int ipr_device_reset(struct ipr_ioa_cfg *ioa_cfg,
5042 struct ipr_resource_entry *res)
5043{
5044 struct ipr_cmnd *ipr_cmd;
5045 struct ipr_ioarcb *ioarcb;
5046 struct ipr_cmd_pkt *cmd_pkt;
5047 struct ipr_ioarcb_ata_regs *regs;
5048 u32 ioasc;
5049
5050 ENTER;
5051 ipr_cmd = ipr_get_free_ipr_cmnd(ioa_cfg);
5052 ioarcb = &ipr_cmd->ioarcb;
5053 cmd_pkt = &ioarcb->cmd_pkt;
5054
5055 if (ipr_cmd->ioa_cfg->sis64) {
5056 regs = &ipr_cmd->i.ata_ioadl.regs;
5057 ioarcb->add_cmd_parms_offset = cpu_to_be16(sizeof(*ioarcb));
5058 } else
5059 regs = &ioarcb->u.add_data.u.regs;
5060
5061 ioarcb->res_handle = res->res_handle;
5062 cmd_pkt->request_type = IPR_RQTYPE_IOACMD;
5063 cmd_pkt->cdb[0] = IPR_RESET_DEVICE;
5064 if (ipr_is_gata(res)) {
5065 cmd_pkt->cdb[2] = IPR_ATA_PHY_RESET;
5066 ioarcb->add_cmd_parms_len = cpu_to_be16(sizeof(regs->flags));
5067 regs->flags |= IPR_ATA_FLAG_STATUS_ON_GOOD_COMPLETION;
5068 }
5069
5070 ipr_send_blocking_cmd(ipr_cmd, ipr_timeout, IPR_DEVICE_RESET_TIMEOUT);
5071 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
5072 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
5073 if (ipr_is_gata(res) && res->sata_port && ioasc != IPR_IOASC_IOA_WAS_RESET) {
5074 if (ipr_cmd->ioa_cfg->sis64)
5075 memcpy(&res->sata_port->ioasa, &ipr_cmd->s.ioasa64.u.gata,
5076 sizeof(struct ipr_ioasa_gata));
5077 else
5078 memcpy(&res->sata_port->ioasa, &ipr_cmd->s.ioasa.u.gata,
5079 sizeof(struct ipr_ioasa_gata));
5080 }
5081
5082 LEAVE;
5083 return IPR_IOASC_SENSE_KEY(ioasc) ? -EIO : 0;
5084}
5085
5086
5087
5088
5089
5090
5091
5092
5093
5094
5095
5096static int ipr_sata_reset(struct ata_link *link, unsigned int *classes,
5097 unsigned long deadline)
5098{
5099 struct ipr_sata_port *sata_port = link->ap->private_data;
5100 struct ipr_ioa_cfg *ioa_cfg = sata_port->ioa_cfg;
5101 struct ipr_resource_entry *res;
5102 unsigned long lock_flags = 0;
5103 int rc = -ENXIO;
5104
5105 ENTER;
5106 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
5107 while (ioa_cfg->in_reset_reload) {
5108 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
5109 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
5110 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
5111 }
5112
5113 res = sata_port->res;
5114 if (res) {
5115 rc = ipr_device_reset(ioa_cfg, res);
5116 *classes = res->ata_class;
5117 }
5118
5119 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
5120 LEAVE;
5121 return rc;
5122}
5123
5124
5125
5126
5127
5128
5129
5130
5131
5132
5133
5134
5135static int __ipr_eh_dev_reset(struct scsi_cmnd *scsi_cmd)
5136{
5137 struct ipr_cmnd *ipr_cmd;
5138 struct ipr_ioa_cfg *ioa_cfg;
5139 struct ipr_resource_entry *res;
5140 struct ata_port *ap;
5141 int rc = 0;
5142 struct ipr_hrr_queue *hrrq;
5143
5144 ENTER;
5145 ioa_cfg = (struct ipr_ioa_cfg *) scsi_cmd->device->host->hostdata;
5146 res = scsi_cmd->device->hostdata;
5147
5148 if (!res)
5149 return FAILED;
5150
5151
5152
5153
5154
5155
5156 if (ioa_cfg->in_reset_reload)
5157 return FAILED;
5158 if (ioa_cfg->hrrq[IPR_INIT_HRRQ].ioa_is_dead)
5159 return FAILED;
5160
5161 for_each_hrrq(hrrq, ioa_cfg) {
5162 spin_lock(&hrrq->_lock);
5163 list_for_each_entry(ipr_cmd, &hrrq->hrrq_pending_q, queue) {
5164 if (ipr_cmd->ioarcb.res_handle == res->res_handle) {
5165 if (ipr_cmd->scsi_cmd)
5166 ipr_cmd->done = ipr_scsi_eh_done;
5167 if (ipr_cmd->qc)
5168 ipr_cmd->done = ipr_sata_eh_done;
5169 if (ipr_cmd->qc &&
5170 !(ipr_cmd->qc->flags & ATA_QCFLAG_FAILED)) {
5171 ipr_cmd->qc->err_mask |= AC_ERR_TIMEOUT;
5172 ipr_cmd->qc->flags |= ATA_QCFLAG_FAILED;
5173 }
5174 }
5175 }
5176 spin_unlock(&hrrq->_lock);
5177 }
5178 res->resetting_device = 1;
5179 scmd_printk(KERN_ERR, scsi_cmd, "Resetting device\n");
5180
5181 if (ipr_is_gata(res) && res->sata_port) {
5182 ap = res->sata_port->ap;
5183 spin_unlock_irq(scsi_cmd->device->host->host_lock);
5184 ata_std_error_handler(ap);
5185 spin_lock_irq(scsi_cmd->device->host->host_lock);
5186
5187 for_each_hrrq(hrrq, ioa_cfg) {
5188 spin_lock(&hrrq->_lock);
5189 list_for_each_entry(ipr_cmd,
5190 &hrrq->hrrq_pending_q, queue) {
5191 if (ipr_cmd->ioarcb.res_handle ==
5192 res->res_handle) {
5193 rc = -EIO;
5194 break;
5195 }
5196 }
5197 spin_unlock(&hrrq->_lock);
5198 }
5199 } else
5200 rc = ipr_device_reset(ioa_cfg, res);
5201 res->resetting_device = 0;
5202 res->reset_occurred = 1;
5203
5204 LEAVE;
5205 return rc ? FAILED : SUCCESS;
5206}
5207
5208static int ipr_eh_dev_reset(struct scsi_cmnd *cmd)
5209{
5210 int rc;
5211 struct ipr_ioa_cfg *ioa_cfg;
5212
5213 ioa_cfg = (struct ipr_ioa_cfg *) cmd->device->host->hostdata;
5214
5215 spin_lock_irq(cmd->device->host->host_lock);
5216 rc = __ipr_eh_dev_reset(cmd);
5217 spin_unlock_irq(cmd->device->host->host_lock);
5218
5219 if (rc == SUCCESS)
5220 rc = ipr_wait_for_ops(ioa_cfg, cmd->device, ipr_match_lun);
5221
5222 return rc;
5223}
5224
5225
5226
5227
5228
5229
5230
5231
5232
5233
5234static void ipr_bus_reset_done(struct ipr_cmnd *ipr_cmd)
5235{
5236 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
5237 struct ipr_resource_entry *res;
5238
5239 ENTER;
5240 if (!ioa_cfg->sis64)
5241 list_for_each_entry(res, &ioa_cfg->used_res_q, queue) {
5242 if (res->res_handle == ipr_cmd->ioarcb.res_handle) {
5243 scsi_report_bus_reset(ioa_cfg->host, res->bus);
5244 break;
5245 }
5246 }
5247
5248
5249
5250
5251
5252 if (ipr_cmd->sibling->sibling)
5253 ipr_cmd->sibling->sibling = NULL;
5254 else
5255 ipr_cmd->sibling->done(ipr_cmd->sibling);
5256
5257 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
5258 LEAVE;
5259}
5260
5261
5262
5263
5264
5265
5266
5267
5268
5269
5270
5271
5272static void ipr_abort_timeout(struct ipr_cmnd *ipr_cmd)
5273{
5274 struct ipr_cmnd *reset_cmd;
5275 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
5276 struct ipr_cmd_pkt *cmd_pkt;
5277 unsigned long lock_flags = 0;
5278
5279 ENTER;
5280 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
5281 if (ipr_cmd->completion.done || ioa_cfg->in_reset_reload) {
5282 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
5283 return;
5284 }
5285
5286 sdev_printk(KERN_ERR, ipr_cmd->u.sdev, "Abort timed out. Resetting bus.\n");
5287 reset_cmd = ipr_get_free_ipr_cmnd(ioa_cfg);
5288 ipr_cmd->sibling = reset_cmd;
5289 reset_cmd->sibling = ipr_cmd;
5290 reset_cmd->ioarcb.res_handle = ipr_cmd->ioarcb.res_handle;
5291 cmd_pkt = &reset_cmd->ioarcb.cmd_pkt;
5292 cmd_pkt->request_type = IPR_RQTYPE_IOACMD;
5293 cmd_pkt->cdb[0] = IPR_RESET_DEVICE;
5294 cmd_pkt->cdb[2] = IPR_RESET_TYPE_SELECT | IPR_BUS_RESET;
5295
5296 ipr_do_req(reset_cmd, ipr_bus_reset_done, ipr_timeout, IPR_DEVICE_RESET_TIMEOUT);
5297 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
5298 LEAVE;
5299}
5300
5301
5302
5303
5304
5305
5306
5307
5308
5309
5310static int ipr_cancel_op(struct scsi_cmnd *scsi_cmd)
5311{
5312 struct ipr_cmnd *ipr_cmd;
5313 struct ipr_ioa_cfg *ioa_cfg;
5314 struct ipr_resource_entry *res;
5315 struct ipr_cmd_pkt *cmd_pkt;
5316 u32 ioasc, int_reg;
5317 int op_found = 0;
5318 struct ipr_hrr_queue *hrrq;
5319
5320 ENTER;
5321 ioa_cfg = (struct ipr_ioa_cfg *)scsi_cmd->device->host->hostdata;
5322 res = scsi_cmd->device->hostdata;
5323
5324
5325
5326
5327
5328 if (ioa_cfg->in_reset_reload ||
5329 ioa_cfg->hrrq[IPR_INIT_HRRQ].ioa_is_dead)
5330 return FAILED;
5331 if (!res)
5332 return FAILED;
5333
5334
5335
5336
5337
5338
5339 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg);
5340
5341 if (!ipr_is_gscsi(res))
5342 return FAILED;
5343
5344 for_each_hrrq(hrrq, ioa_cfg) {
5345 spin_lock(&hrrq->_lock);
5346 list_for_each_entry(ipr_cmd, &hrrq->hrrq_pending_q, queue) {
5347 if (ipr_cmd->scsi_cmd == scsi_cmd) {
5348 ipr_cmd->done = ipr_scsi_eh_done;
5349 op_found = 1;
5350 break;
5351 }
5352 }
5353 spin_unlock(&hrrq->_lock);
5354 }
5355
5356 if (!op_found)
5357 return SUCCESS;
5358
5359 ipr_cmd = ipr_get_free_ipr_cmnd(ioa_cfg);
5360 ipr_cmd->ioarcb.res_handle = res->res_handle;
5361 cmd_pkt = &ipr_cmd->ioarcb.cmd_pkt;
5362 cmd_pkt->request_type = IPR_RQTYPE_IOACMD;
5363 cmd_pkt->cdb[0] = IPR_CANCEL_ALL_REQUESTS;
5364 ipr_cmd->u.sdev = scsi_cmd->device;
5365
5366 scmd_printk(KERN_ERR, scsi_cmd, "Aborting command: %02X\n",
5367 scsi_cmd->cmnd[0]);
5368 ipr_send_blocking_cmd(ipr_cmd, ipr_abort_timeout, IPR_CANCEL_ALL_TIMEOUT);
5369 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
5370
5371
5372
5373
5374
5375 if (ioasc == IPR_IOASC_BUS_WAS_RESET || ioasc == IPR_IOASC_SYNC_REQUIRED) {
5376 ioasc = 0;
5377 ipr_trace;
5378 }
5379
5380 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
5381 if (!ipr_is_naca_model(res))
5382 res->needs_sync_complete = 1;
5383
5384 LEAVE;
5385 return IPR_IOASC_SENSE_KEY(ioasc) ? FAILED : SUCCESS;
5386}
5387
5388
5389
5390
5391
5392
5393
5394
5395static int ipr_scan_finished(struct Scsi_Host *shost, unsigned long elapsed_time)
5396{
5397 unsigned long lock_flags;
5398 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *) shost->hostdata;
5399 int rc = 0;
5400
5401 spin_lock_irqsave(shost->host_lock, lock_flags);
5402 if (ioa_cfg->hrrq[IPR_INIT_HRRQ].ioa_is_dead || ioa_cfg->scan_done)
5403 rc = 1;
5404 if ((elapsed_time/HZ) > (ioa_cfg->transop_timeout * 2))
5405 rc = 1;
5406 spin_unlock_irqrestore(shost->host_lock, lock_flags);
5407 return rc;
5408}
5409
5410
5411
5412
5413
5414
5415
5416
5417static int ipr_eh_abort(struct scsi_cmnd *scsi_cmd)
5418{
5419 unsigned long flags;
5420 int rc;
5421 struct ipr_ioa_cfg *ioa_cfg;
5422
5423 ENTER;
5424
5425 ioa_cfg = (struct ipr_ioa_cfg *) scsi_cmd->device->host->hostdata;
5426
5427 spin_lock_irqsave(scsi_cmd->device->host->host_lock, flags);
5428 rc = ipr_cancel_op(scsi_cmd);
5429 spin_unlock_irqrestore(scsi_cmd->device->host->host_lock, flags);
5430
5431 if (rc == SUCCESS)
5432 rc = ipr_wait_for_ops(ioa_cfg, scsi_cmd->device, ipr_match_lun);
5433 LEAVE;
5434 return rc;
5435}
5436
5437
5438
5439
5440
5441
5442
5443
5444
5445static irqreturn_t ipr_handle_other_interrupt(struct ipr_ioa_cfg *ioa_cfg,
5446 u32 int_reg)
5447{
5448 irqreturn_t rc = IRQ_HANDLED;
5449 u32 int_mask_reg;
5450
5451 int_mask_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg32);
5452 int_reg &= ~int_mask_reg;
5453
5454
5455
5456
5457 if ((int_reg & IPR_PCII_OPER_INTERRUPTS) == 0) {
5458 if (ioa_cfg->sis64) {
5459 int_mask_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg);
5460 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg) & ~int_mask_reg;
5461 if (int_reg & IPR_PCII_IPL_STAGE_CHANGE) {
5462
5463
5464 writel(IPR_PCII_IPL_STAGE_CHANGE, ioa_cfg->regs.clr_interrupt_reg);
5465 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg) & ~int_mask_reg;
5466 list_del(&ioa_cfg->reset_cmd->queue);
5467 del_timer(&ioa_cfg->reset_cmd->timer);
5468 ipr_reset_ioa_job(ioa_cfg->reset_cmd);
5469 return IRQ_HANDLED;
5470 }
5471 }
5472
5473 return IRQ_NONE;
5474 }
5475
5476 if (int_reg & IPR_PCII_IOA_TRANS_TO_OPER) {
5477
5478 writel(IPR_PCII_IOA_TRANS_TO_OPER, ioa_cfg->regs.set_interrupt_mask_reg);
5479 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg);
5480
5481 list_del(&ioa_cfg->reset_cmd->queue);
5482 del_timer(&ioa_cfg->reset_cmd->timer);
5483 ipr_reset_ioa_job(ioa_cfg->reset_cmd);
5484 } else if ((int_reg & IPR_PCII_HRRQ_UPDATED) == int_reg) {
5485 if (ioa_cfg->clear_isr) {
5486 if (ipr_debug && printk_ratelimit())
5487 dev_err(&ioa_cfg->pdev->dev,
5488 "Spurious interrupt detected. 0x%08X\n", int_reg);
5489 writel(IPR_PCII_HRRQ_UPDATED, ioa_cfg->regs.clr_interrupt_reg32);
5490 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg32);
5491 return IRQ_NONE;
5492 }
5493 } else {
5494 if (int_reg & IPR_PCII_IOA_UNIT_CHECKED)
5495 ioa_cfg->ioa_unit_checked = 1;
5496 else if (int_reg & IPR_PCII_NO_HOST_RRQ)
5497 dev_err(&ioa_cfg->pdev->dev,
5498 "No Host RRQ. 0x%08X\n", int_reg);
5499 else
5500 dev_err(&ioa_cfg->pdev->dev,
5501 "Permanent IOA failure. 0x%08X\n", int_reg);
5502
5503 if (WAIT_FOR_DUMP == ioa_cfg->sdt_state)
5504 ioa_cfg->sdt_state = GET_DUMP;
5505
5506 ipr_mask_and_clear_interrupts(ioa_cfg, ~0);
5507 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
5508 }
5509
5510 return rc;
5511}
5512
5513
5514
5515
5516
5517
5518
5519
5520
5521static void ipr_isr_eh(struct ipr_ioa_cfg *ioa_cfg, char *msg, u16 number)
5522{
5523 ioa_cfg->errors_logged++;
5524 dev_err(&ioa_cfg->pdev->dev, "%s %d\n", msg, number);
5525
5526 if (WAIT_FOR_DUMP == ioa_cfg->sdt_state)
5527 ioa_cfg->sdt_state = GET_DUMP;
5528
5529 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
5530}
5531
5532static int ipr_process_hrrq(struct ipr_hrr_queue *hrr_queue, int budget,
5533 struct list_head *doneq)
5534{
5535 u32 ioasc;
5536 u16 cmd_index;
5537 struct ipr_cmnd *ipr_cmd;
5538 struct ipr_ioa_cfg *ioa_cfg = hrr_queue->ioa_cfg;
5539 int num_hrrq = 0;
5540
5541
5542 if (!hrr_queue->allow_interrupts)
5543 return 0;
5544
5545 while ((be32_to_cpu(*hrr_queue->hrrq_curr) & IPR_HRRQ_TOGGLE_BIT) ==
5546 hrr_queue->toggle_bit) {
5547
5548 cmd_index = (be32_to_cpu(*hrr_queue->hrrq_curr) &
5549 IPR_HRRQ_REQ_RESP_HANDLE_MASK) >>
5550 IPR_HRRQ_REQ_RESP_HANDLE_SHIFT;
5551
5552 if (unlikely(cmd_index > hrr_queue->max_cmd_id ||
5553 cmd_index < hrr_queue->min_cmd_id)) {
5554 ipr_isr_eh(ioa_cfg,
5555 "Invalid response handle from IOA: ",
5556 cmd_index);
5557 break;
5558 }
5559
5560 ipr_cmd = ioa_cfg->ipr_cmnd_list[cmd_index];
5561 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
5562
5563 ipr_trc_hook(ipr_cmd, IPR_TRACE_FINISH, ioasc);
5564
5565 list_move_tail(&ipr_cmd->queue, doneq);
5566
5567 if (hrr_queue->hrrq_curr < hrr_queue->hrrq_end) {
5568 hrr_queue->hrrq_curr++;
5569 } else {
5570 hrr_queue->hrrq_curr = hrr_queue->hrrq_start;
5571 hrr_queue->toggle_bit ^= 1u;
5572 }
5573 num_hrrq++;
5574 if (budget > 0 && num_hrrq >= budget)
5575 break;
5576 }
5577
5578 return num_hrrq;
5579}
5580
5581static int ipr_iopoll(struct irq_poll *iop, int budget)
5582{
5583 struct ipr_ioa_cfg *ioa_cfg;
5584 struct ipr_hrr_queue *hrrq;
5585 struct ipr_cmnd *ipr_cmd, *temp;
5586 unsigned long hrrq_flags;
5587 int completed_ops;
5588 LIST_HEAD(doneq);
5589
5590 hrrq = container_of(iop, struct ipr_hrr_queue, iopoll);
5591 ioa_cfg = hrrq->ioa_cfg;
5592
5593 spin_lock_irqsave(hrrq->lock, hrrq_flags);
5594 completed_ops = ipr_process_hrrq(hrrq, budget, &doneq);
5595
5596 if (completed_ops < budget)
5597 irq_poll_complete(iop);
5598 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
5599
5600 list_for_each_entry_safe(ipr_cmd, temp, &doneq, queue) {
5601 list_del(&ipr_cmd->queue);
5602 del_timer(&ipr_cmd->timer);
5603 ipr_cmd->fast_done(ipr_cmd);
5604 }
5605
5606 return completed_ops;
5607}
5608
5609
5610
5611
5612
5613
5614
5615
5616
5617static irqreturn_t ipr_isr(int irq, void *devp)
5618{
5619 struct ipr_hrr_queue *hrrq = (struct ipr_hrr_queue *)devp;
5620 struct ipr_ioa_cfg *ioa_cfg = hrrq->ioa_cfg;
5621 unsigned long hrrq_flags = 0;
5622 u32 int_reg = 0;
5623 int num_hrrq = 0;
5624 int irq_none = 0;
5625 struct ipr_cmnd *ipr_cmd, *temp;
5626 irqreturn_t rc = IRQ_NONE;
5627 LIST_HEAD(doneq);
5628
5629 spin_lock_irqsave(hrrq->lock, hrrq_flags);
5630
5631 if (!hrrq->allow_interrupts) {
5632 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
5633 return IRQ_NONE;
5634 }
5635
5636 while (1) {
5637 if (ipr_process_hrrq(hrrq, -1, &doneq)) {
5638 rc = IRQ_HANDLED;
5639
5640 if (!ioa_cfg->clear_isr)
5641 break;
5642
5643
5644 num_hrrq = 0;
5645 do {
5646 writel(IPR_PCII_HRRQ_UPDATED,
5647 ioa_cfg->regs.clr_interrupt_reg32);
5648 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg32);
5649 } while (int_reg & IPR_PCII_HRRQ_UPDATED &&
5650 num_hrrq++ < IPR_MAX_HRRQ_RETRIES);
5651
5652 } else if (rc == IRQ_NONE && irq_none == 0) {
5653 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg32);
5654 irq_none++;
5655 } else if (num_hrrq == IPR_MAX_HRRQ_RETRIES &&
5656 int_reg & IPR_PCII_HRRQ_UPDATED) {
5657 ipr_isr_eh(ioa_cfg,
5658 "Error clearing HRRQ: ", num_hrrq);
5659 rc = IRQ_HANDLED;
5660 break;
5661 } else
5662 break;
5663 }
5664
5665 if (unlikely(rc == IRQ_NONE))
5666 rc = ipr_handle_other_interrupt(ioa_cfg, int_reg);
5667
5668 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
5669 list_for_each_entry_safe(ipr_cmd, temp, &doneq, queue) {
5670 list_del(&ipr_cmd->queue);
5671 del_timer(&ipr_cmd->timer);
5672 ipr_cmd->fast_done(ipr_cmd);
5673 }
5674 return rc;
5675}
5676
5677
5678
5679
5680
5681
5682
5683
5684
5685static irqreturn_t ipr_isr_mhrrq(int irq, void *devp)
5686{
5687 struct ipr_hrr_queue *hrrq = (struct ipr_hrr_queue *)devp;
5688 struct ipr_ioa_cfg *ioa_cfg = hrrq->ioa_cfg;
5689 unsigned long hrrq_flags = 0;
5690 struct ipr_cmnd *ipr_cmd, *temp;
5691 irqreturn_t rc = IRQ_NONE;
5692 LIST_HEAD(doneq);
5693
5694 spin_lock_irqsave(hrrq->lock, hrrq_flags);
5695
5696
5697 if (!hrrq->allow_interrupts) {
5698 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
5699 return IRQ_NONE;
5700 }
5701
5702 if (ioa_cfg->iopoll_weight && ioa_cfg->sis64 && ioa_cfg->nvectors > 1) {
5703 if ((be32_to_cpu(*hrrq->hrrq_curr) & IPR_HRRQ_TOGGLE_BIT) ==
5704 hrrq->toggle_bit) {
5705 irq_poll_sched(&hrrq->iopoll);
5706 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
5707 return IRQ_HANDLED;
5708 }
5709 } else {
5710 if ((be32_to_cpu(*hrrq->hrrq_curr) & IPR_HRRQ_TOGGLE_BIT) ==
5711 hrrq->toggle_bit)
5712
5713 if (ipr_process_hrrq(hrrq, -1, &doneq))
5714 rc = IRQ_HANDLED;
5715 }
5716
5717 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
5718
5719 list_for_each_entry_safe(ipr_cmd, temp, &doneq, queue) {
5720 list_del(&ipr_cmd->queue);
5721 del_timer(&ipr_cmd->timer);
5722 ipr_cmd->fast_done(ipr_cmd);
5723 }
5724 return rc;
5725}
5726
5727
5728
5729
5730
5731
5732
5733
5734
5735static int ipr_build_ioadl64(struct ipr_ioa_cfg *ioa_cfg,
5736 struct ipr_cmnd *ipr_cmd)
5737{
5738 int i, nseg;
5739 struct scatterlist *sg;
5740 u32 length;
5741 u32 ioadl_flags = 0;
5742 struct scsi_cmnd *scsi_cmd = ipr_cmd->scsi_cmd;
5743 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
5744 struct ipr_ioadl64_desc *ioadl64 = ipr_cmd->i.ioadl64;
5745
5746 length = scsi_bufflen(scsi_cmd);
5747 if (!length)
5748 return 0;
5749
5750 nseg = scsi_dma_map(scsi_cmd);
5751 if (nseg < 0) {
5752 if (printk_ratelimit())
5753 dev_err(&ioa_cfg->pdev->dev, "scsi_dma_map failed!\n");
5754 return -1;
5755 }
5756
5757 ipr_cmd->dma_use_sg = nseg;
5758
5759 ioarcb->data_transfer_length = cpu_to_be32(length);
5760 ioarcb->ioadl_len =
5761 cpu_to_be32(sizeof(struct ipr_ioadl64_desc) * ipr_cmd->dma_use_sg);
5762
5763 if (scsi_cmd->sc_data_direction == DMA_TO_DEVICE) {
5764 ioadl_flags = IPR_IOADL_FLAGS_WRITE;
5765 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_WRITE_NOT_READ;
5766 } else if (scsi_cmd->sc_data_direction == DMA_FROM_DEVICE)
5767 ioadl_flags = IPR_IOADL_FLAGS_READ;
5768
5769 scsi_for_each_sg(scsi_cmd, sg, ipr_cmd->dma_use_sg, i) {
5770 ioadl64[i].flags = cpu_to_be32(ioadl_flags);
5771 ioadl64[i].data_len = cpu_to_be32(sg_dma_len(sg));
5772 ioadl64[i].address = cpu_to_be64(sg_dma_address(sg));
5773 }
5774
5775 ioadl64[i-1].flags |= cpu_to_be32(IPR_IOADL_FLAGS_LAST);
5776 return 0;
5777}
5778
5779
5780
5781
5782
5783
5784
5785
5786
5787static int ipr_build_ioadl(struct ipr_ioa_cfg *ioa_cfg,
5788 struct ipr_cmnd *ipr_cmd)
5789{
5790 int i, nseg;
5791 struct scatterlist *sg;
5792 u32 length;
5793 u32 ioadl_flags = 0;
5794 struct scsi_cmnd *scsi_cmd = ipr_cmd->scsi_cmd;
5795 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
5796 struct ipr_ioadl_desc *ioadl = ipr_cmd->i.ioadl;
5797
5798 length = scsi_bufflen(scsi_cmd);
5799 if (!length)
5800 return 0;
5801
5802 nseg = scsi_dma_map(scsi_cmd);
5803 if (nseg < 0) {
5804 dev_err(&ioa_cfg->pdev->dev, "scsi_dma_map failed!\n");
5805 return -1;
5806 }
5807
5808 ipr_cmd->dma_use_sg = nseg;
5809
5810 if (scsi_cmd->sc_data_direction == DMA_TO_DEVICE) {
5811 ioadl_flags = IPR_IOADL_FLAGS_WRITE;
5812 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_WRITE_NOT_READ;
5813 ioarcb->data_transfer_length = cpu_to_be32(length);
5814 ioarcb->ioadl_len =
5815 cpu_to_be32(sizeof(struct ipr_ioadl_desc) * ipr_cmd->dma_use_sg);
5816 } else if (scsi_cmd->sc_data_direction == DMA_FROM_DEVICE) {
5817 ioadl_flags = IPR_IOADL_FLAGS_READ;
5818 ioarcb->read_data_transfer_length = cpu_to_be32(length);
5819 ioarcb->read_ioadl_len =
5820 cpu_to_be32(sizeof(struct ipr_ioadl_desc) * ipr_cmd->dma_use_sg);
5821 }
5822
5823 if (ipr_cmd->dma_use_sg <= ARRAY_SIZE(ioarcb->u.add_data.u.ioadl)) {
5824 ioadl = ioarcb->u.add_data.u.ioadl;
5825 ioarcb->write_ioadl_addr = cpu_to_be32((ipr_cmd->dma_addr) +
5826 offsetof(struct ipr_ioarcb, u.add_data));
5827 ioarcb->read_ioadl_addr = ioarcb->write_ioadl_addr;
5828 }
5829
5830 scsi_for_each_sg(scsi_cmd, sg, ipr_cmd->dma_use_sg, i) {
5831 ioadl[i].flags_and_data_len =
5832 cpu_to_be32(ioadl_flags | sg_dma_len(sg));
5833 ioadl[i].address = cpu_to_be32(sg_dma_address(sg));
5834 }
5835
5836 ioadl[i-1].flags_and_data_len |= cpu_to_be32(IPR_IOADL_FLAGS_LAST);
5837 return 0;
5838}
5839
5840
5841
5842
5843
5844
5845
5846
5847
5848
5849
5850static void ipr_erp_done(struct ipr_cmnd *ipr_cmd)
5851{
5852 struct scsi_cmnd *scsi_cmd = ipr_cmd->scsi_cmd;
5853 struct ipr_resource_entry *res = scsi_cmd->device->hostdata;
5854 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
5855
5856 if (IPR_IOASC_SENSE_KEY(ioasc) > 0) {
5857 scsi_cmd->result |= (DID_ERROR << 16);
5858 scmd_printk(KERN_ERR, scsi_cmd,
5859 "Request Sense failed with IOASC: 0x%08X\n", ioasc);
5860 } else {
5861 memcpy(scsi_cmd->sense_buffer, ipr_cmd->sense_buffer,
5862 SCSI_SENSE_BUFFERSIZE);
5863 }
5864
5865 if (res) {
5866 if (!ipr_is_naca_model(res))
5867 res->needs_sync_complete = 1;
5868 res->in_erp = 0;
5869 }
5870 scsi_dma_unmap(ipr_cmd->scsi_cmd);
5871 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
5872 scsi_cmd->scsi_done(scsi_cmd);
5873}
5874
5875
5876
5877
5878
5879
5880
5881
5882static void ipr_reinit_ipr_cmnd_for_erp(struct ipr_cmnd *ipr_cmd)
5883{
5884 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
5885 struct ipr_ioasa *ioasa = &ipr_cmd->s.ioasa;
5886 dma_addr_t dma_addr = ipr_cmd->dma_addr;
5887
5888 memset(&ioarcb->cmd_pkt, 0, sizeof(struct ipr_cmd_pkt));
5889 ioarcb->data_transfer_length = 0;
5890 ioarcb->read_data_transfer_length = 0;
5891 ioarcb->ioadl_len = 0;
5892 ioarcb->read_ioadl_len = 0;
5893 ioasa->hdr.ioasc = 0;
5894 ioasa->hdr.residual_data_len = 0;
5895
5896 if (ipr_cmd->ioa_cfg->sis64)
5897 ioarcb->u.sis64_addr_data.data_ioadl_addr =
5898 cpu_to_be64(dma_addr + offsetof(struct ipr_cmnd, i.ioadl64));
5899 else {
5900 ioarcb->write_ioadl_addr =
5901 cpu_to_be32(dma_addr + offsetof(struct ipr_cmnd, i.ioadl));
5902 ioarcb->read_ioadl_addr = ioarcb->write_ioadl_addr;
5903 }
5904}
5905
5906
5907
5908
5909
5910
5911
5912
5913
5914
5915
5916static void ipr_erp_request_sense(struct ipr_cmnd *ipr_cmd)
5917{
5918 struct ipr_cmd_pkt *cmd_pkt = &ipr_cmd->ioarcb.cmd_pkt;
5919 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
5920
5921 if (IPR_IOASC_SENSE_KEY(ioasc) > 0) {
5922 ipr_erp_done(ipr_cmd);
5923 return;
5924 }
5925
5926 ipr_reinit_ipr_cmnd_for_erp(ipr_cmd);
5927
5928 cmd_pkt->request_type = IPR_RQTYPE_SCSICDB;
5929 cmd_pkt->cdb[0] = REQUEST_SENSE;
5930 cmd_pkt->cdb[4] = SCSI_SENSE_BUFFERSIZE;
5931 cmd_pkt->flags_hi |= IPR_FLAGS_HI_SYNC_OVERRIDE;
5932 cmd_pkt->flags_hi |= IPR_FLAGS_HI_NO_ULEN_CHK;
5933 cmd_pkt->timeout = cpu_to_be16(IPR_REQUEST_SENSE_TIMEOUT / HZ);
5934
5935 ipr_init_ioadl(ipr_cmd, ipr_cmd->sense_buffer_dma,
5936 SCSI_SENSE_BUFFERSIZE, IPR_IOADL_FLAGS_READ_LAST);
5937
5938 ipr_do_req(ipr_cmd, ipr_erp_done, ipr_timeout,
5939 IPR_REQUEST_SENSE_TIMEOUT * 2);
5940}
5941
5942
5943
5944
5945
5946
5947
5948
5949
5950
5951
5952
5953
5954static void ipr_erp_cancel_all(struct ipr_cmnd *ipr_cmd)
5955{
5956 struct scsi_cmnd *scsi_cmd = ipr_cmd->scsi_cmd;
5957 struct ipr_resource_entry *res = scsi_cmd->device->hostdata;
5958 struct ipr_cmd_pkt *cmd_pkt;
5959
5960 res->in_erp = 1;
5961
5962 ipr_reinit_ipr_cmnd_for_erp(ipr_cmd);
5963
5964 if (!scsi_cmd->device->simple_tags) {
5965 ipr_erp_request_sense(ipr_cmd);
5966 return;
5967 }
5968
5969 cmd_pkt = &ipr_cmd->ioarcb.cmd_pkt;
5970 cmd_pkt->request_type = IPR_RQTYPE_IOACMD;
5971 cmd_pkt->cdb[0] = IPR_CANCEL_ALL_REQUESTS;
5972
5973 ipr_do_req(ipr_cmd, ipr_erp_request_sense, ipr_timeout,
5974 IPR_CANCEL_ALL_TIMEOUT);
5975}
5976
5977
5978
5979
5980
5981
5982
5983
5984
5985
5986
5987
5988
5989
5990static void ipr_dump_ioasa(struct ipr_ioa_cfg *ioa_cfg,
5991 struct ipr_cmnd *ipr_cmd, struct ipr_resource_entry *res)
5992{
5993 int i;
5994 u16 data_len;
5995 u32 ioasc, fd_ioasc;
5996 struct ipr_ioasa *ioasa = &ipr_cmd->s.ioasa;
5997 __be32 *ioasa_data = (__be32 *)ioasa;
5998 int error_index;
5999
6000 ioasc = be32_to_cpu(ioasa->hdr.ioasc) & IPR_IOASC_IOASC_MASK;
6001 fd_ioasc = be32_to_cpu(ioasa->hdr.fd_ioasc) & IPR_IOASC_IOASC_MASK;
6002
6003 if (0 == ioasc)
6004 return;
6005
6006 if (ioa_cfg->log_level < IPR_DEFAULT_LOG_LEVEL)
6007 return;
6008
6009 if (ioasc == IPR_IOASC_BUS_WAS_RESET && fd_ioasc)
6010 error_index = ipr_get_error(fd_ioasc);
6011 else
6012 error_index = ipr_get_error(ioasc);
6013
6014 if (ioa_cfg->log_level < IPR_MAX_LOG_LEVEL) {
6015
6016 if (ioasa->hdr.ilid != 0)
6017 return;
6018
6019 if (!ipr_is_gscsi(res))
6020 return;
6021
6022 if (ipr_error_table[error_index].log_ioasa == 0)
6023 return;
6024 }
6025
6026 ipr_res_err(ioa_cfg, res, "%s\n", ipr_error_table[error_index].error);
6027
6028 data_len = be16_to_cpu(ioasa->hdr.ret_stat_len);
6029 if (ioa_cfg->sis64 && sizeof(struct ipr_ioasa64) < data_len)
6030 data_len = sizeof(struct ipr_ioasa64);
6031 else if (!ioa_cfg->sis64 && sizeof(struct ipr_ioasa) < data_len)
6032 data_len = sizeof(struct ipr_ioasa);
6033
6034 ipr_err("IOASA Dump:\n");
6035
6036 for (i = 0; i < data_len / 4; i += 4) {
6037 ipr_err("%08X: %08X %08X %08X %08X\n", i*4,
6038 be32_to_cpu(ioasa_data[i]),
6039 be32_to_cpu(ioasa_data[i+1]),
6040 be32_to_cpu(ioasa_data[i+2]),
6041 be32_to_cpu(ioasa_data[i+3]));
6042 }
6043}
6044
6045
6046
6047
6048
6049
6050
6051
6052
6053static void ipr_gen_sense(struct ipr_cmnd *ipr_cmd)
6054{
6055 u32 failing_lba;
6056 u8 *sense_buf = ipr_cmd->scsi_cmd->sense_buffer;
6057 struct ipr_resource_entry *res = ipr_cmd->scsi_cmd->device->hostdata;
6058 struct ipr_ioasa *ioasa = &ipr_cmd->s.ioasa;
6059 u32 ioasc = be32_to_cpu(ioasa->hdr.ioasc);
6060
6061 memset(sense_buf, 0, SCSI_SENSE_BUFFERSIZE);
6062
6063 if (ioasc >= IPR_FIRST_DRIVER_IOASC)
6064 return;
6065
6066 ipr_cmd->scsi_cmd->result = SAM_STAT_CHECK_CONDITION;
6067
6068 if (ipr_is_vset_device(res) &&
6069 ioasc == IPR_IOASC_MED_DO_NOT_REALLOC &&
6070 ioasa->u.vset.failing_lba_hi != 0) {
6071 sense_buf[0] = 0x72;
6072 sense_buf[1] = IPR_IOASC_SENSE_KEY(ioasc);
6073 sense_buf[2] = IPR_IOASC_SENSE_CODE(ioasc);
6074 sense_buf[3] = IPR_IOASC_SENSE_QUAL(ioasc);
6075
6076 sense_buf[7] = 12;
6077 sense_buf[8] = 0;
6078 sense_buf[9] = 0x0A;
6079 sense_buf[10] = 0x80;
6080
6081 failing_lba = be32_to_cpu(ioasa->u.vset.failing_lba_hi);
6082
6083 sense_buf[12] = (failing_lba & 0xff000000) >> 24;
6084 sense_buf[13] = (failing_lba & 0x00ff0000) >> 16;
6085 sense_buf[14] = (failing_lba & 0x0000ff00) >> 8;
6086 sense_buf[15] = failing_lba & 0x000000ff;
6087
6088 failing_lba = be32_to_cpu(ioasa->u.vset.failing_lba_lo);
6089
6090 sense_buf[16] = (failing_lba & 0xff000000) >> 24;
6091 sense_buf[17] = (failing_lba & 0x00ff0000) >> 16;
6092 sense_buf[18] = (failing_lba & 0x0000ff00) >> 8;
6093 sense_buf[19] = failing_lba & 0x000000ff;
6094 } else {
6095 sense_buf[0] = 0x70;
6096 sense_buf[2] = IPR_IOASC_SENSE_KEY(ioasc);
6097 sense_buf[12] = IPR_IOASC_SENSE_CODE(ioasc);
6098 sense_buf[13] = IPR_IOASC_SENSE_QUAL(ioasc);
6099
6100
6101 if ((IPR_IOASC_SENSE_KEY(ioasc) == 0x05) &&
6102 (be32_to_cpu(ioasa->hdr.ioasc_specific) & IPR_FIELD_POINTER_VALID)) {
6103 sense_buf[7] = 10;
6104
6105
6106 if (IPR_IOASC_SENSE_CODE(ioasc) == 0x24)
6107 sense_buf[15] = 0xC0;
6108 else
6109 sense_buf[15] = 0x80;
6110
6111 sense_buf[16] =
6112 ((IPR_FIELD_POINTER_MASK &
6113 be32_to_cpu(ioasa->hdr.ioasc_specific)) >> 8) & 0xff;
6114 sense_buf[17] =
6115 (IPR_FIELD_POINTER_MASK &
6116 be32_to_cpu(ioasa->hdr.ioasc_specific)) & 0xff;
6117 } else {
6118 if (ioasc == IPR_IOASC_MED_DO_NOT_REALLOC) {
6119 if (ipr_is_vset_device(res))
6120 failing_lba = be32_to_cpu(ioasa->u.vset.failing_lba_lo);
6121 else
6122 failing_lba = be32_to_cpu(ioasa->u.dasd.failing_lba);
6123
6124 sense_buf[0] |= 0x80;
6125 sense_buf[3] = (failing_lba & 0xff000000) >> 24;
6126 sense_buf[4] = (failing_lba & 0x00ff0000) >> 16;
6127 sense_buf[5] = (failing_lba & 0x0000ff00) >> 8;
6128 sense_buf[6] = failing_lba & 0x000000ff;
6129 }
6130
6131 sense_buf[7] = 6;
6132 }
6133 }
6134}
6135
6136
6137
6138
6139
6140
6141
6142
6143
6144
6145
6146static int ipr_get_autosense(struct ipr_cmnd *ipr_cmd)
6147{
6148 struct ipr_ioasa *ioasa = &ipr_cmd->s.ioasa;
6149 struct ipr_ioasa64 *ioasa64 = &ipr_cmd->s.ioasa64;
6150
6151 if ((be32_to_cpu(ioasa->hdr.ioasc_specific) & IPR_AUTOSENSE_VALID) == 0)
6152 return 0;
6153
6154 if (ipr_cmd->ioa_cfg->sis64)
6155 memcpy(ipr_cmd->scsi_cmd->sense_buffer, ioasa64->auto_sense.data,
6156 min_t(u16, be16_to_cpu(ioasa64->auto_sense.auto_sense_len),
6157 SCSI_SENSE_BUFFERSIZE));
6158 else
6159 memcpy(ipr_cmd->scsi_cmd->sense_buffer, ioasa->auto_sense.data,
6160 min_t(u16, be16_to_cpu(ioasa->auto_sense.auto_sense_len),
6161 SCSI_SENSE_BUFFERSIZE));
6162 return 1;
6163}
6164
6165
6166
6167
6168
6169
6170
6171
6172
6173
6174
6175
6176static void ipr_erp_start(struct ipr_ioa_cfg *ioa_cfg,
6177 struct ipr_cmnd *ipr_cmd)
6178{
6179 struct scsi_cmnd *scsi_cmd = ipr_cmd->scsi_cmd;
6180 struct ipr_resource_entry *res = scsi_cmd->device->hostdata;
6181 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
6182 u32 masked_ioasc = ioasc & IPR_IOASC_IOASC_MASK;
6183
6184 if (!res) {
6185 ipr_scsi_eh_done(ipr_cmd);
6186 return;
6187 }
6188
6189 if (!ipr_is_gscsi(res) && masked_ioasc != IPR_IOASC_HW_DEV_BUS_STATUS)
6190 ipr_gen_sense(ipr_cmd);
6191
6192 ipr_dump_ioasa(ioa_cfg, ipr_cmd, res);
6193
6194 switch (masked_ioasc) {
6195 case IPR_IOASC_ABORTED_CMD_TERM_BY_HOST:
6196 if (ipr_is_naca_model(res))
6197 scsi_cmd->result |= (DID_ABORT << 16);
6198 else
6199 scsi_cmd->result |= (DID_IMM_RETRY << 16);
6200 break;
6201 case IPR_IOASC_IR_RESOURCE_HANDLE:
6202 case IPR_IOASC_IR_NO_CMDS_TO_2ND_IOA:
6203 scsi_cmd->result |= (DID_NO_CONNECT << 16);
6204 break;
6205 case IPR_IOASC_HW_SEL_TIMEOUT:
6206 scsi_cmd->result |= (DID_NO_CONNECT << 16);
6207 if (!ipr_is_naca_model(res))
6208 res->needs_sync_complete = 1;
6209 break;
6210 case IPR_IOASC_SYNC_REQUIRED:
6211 if (!res->in_erp)
6212 res->needs_sync_complete = 1;
6213 scsi_cmd->result |= (DID_IMM_RETRY << 16);
6214 break;
6215 case IPR_IOASC_MED_DO_NOT_REALLOC:
6216 case IPR_IOASA_IR_DUAL_IOA_DISABLED:
6217 scsi_cmd->result |= (DID_PASSTHROUGH << 16);
6218 break;
6219 case IPR_IOASC_BUS_WAS_RESET:
6220 case IPR_IOASC_BUS_WAS_RESET_BY_OTHER:
6221
6222
6223
6224
6225 if (!res->resetting_device)
6226 scsi_report_bus_reset(ioa_cfg->host, scsi_cmd->device->channel);
6227 scsi_cmd->result |= (DID_ERROR << 16);
6228 if (!ipr_is_naca_model(res))
6229 res->needs_sync_complete = 1;
6230 break;
6231 case IPR_IOASC_HW_DEV_BUS_STATUS:
6232 scsi_cmd->result |= IPR_IOASC_SENSE_STATUS(ioasc);
6233 if (IPR_IOASC_SENSE_STATUS(ioasc) == SAM_STAT_CHECK_CONDITION) {
6234 if (!ipr_get_autosense(ipr_cmd)) {
6235 if (!ipr_is_naca_model(res)) {
6236 ipr_erp_cancel_all(ipr_cmd);
6237 return;
6238 }
6239 }
6240 }
6241 if (!ipr_is_naca_model(res))
6242 res->needs_sync_complete = 1;
6243 break;
6244 case IPR_IOASC_NR_INIT_CMD_REQUIRED:
6245 break;
6246 case IPR_IOASC_IR_NON_OPTIMIZED:
6247 if (res->raw_mode) {
6248 res->raw_mode = 0;
6249 scsi_cmd->result |= (DID_IMM_RETRY << 16);
6250 } else
6251 scsi_cmd->result |= (DID_ERROR << 16);
6252 break;
6253 default:
6254 if (IPR_IOASC_SENSE_KEY(ioasc) > RECOVERED_ERROR)
6255 scsi_cmd->result |= (DID_ERROR << 16);
6256 if (!ipr_is_vset_device(res) && !ipr_is_naca_model(res))
6257 res->needs_sync_complete = 1;
6258 break;
6259 }
6260
6261 scsi_dma_unmap(ipr_cmd->scsi_cmd);
6262 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
6263 scsi_cmd->scsi_done(scsi_cmd);
6264}
6265
6266
6267
6268
6269
6270
6271
6272
6273
6274
6275
6276static void ipr_scsi_done(struct ipr_cmnd *ipr_cmd)
6277{
6278 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
6279 struct scsi_cmnd *scsi_cmd = ipr_cmd->scsi_cmd;
6280 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
6281 unsigned long lock_flags;
6282
6283 scsi_set_resid(scsi_cmd, be32_to_cpu(ipr_cmd->s.ioasa.hdr.residual_data_len));
6284
6285 if (likely(IPR_IOASC_SENSE_KEY(ioasc) == 0)) {
6286 scsi_dma_unmap(scsi_cmd);
6287
6288 spin_lock_irqsave(ipr_cmd->hrrq->lock, lock_flags);
6289 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
6290 scsi_cmd->scsi_done(scsi_cmd);
6291 spin_unlock_irqrestore(ipr_cmd->hrrq->lock, lock_flags);
6292 } else {
6293 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
6294 spin_lock(&ipr_cmd->hrrq->_lock);
6295 ipr_erp_start(ioa_cfg, ipr_cmd);
6296 spin_unlock(&ipr_cmd->hrrq->_lock);
6297 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
6298 }
6299}
6300
6301
6302
6303
6304
6305
6306
6307
6308
6309
6310
6311
6312
6313static int ipr_queuecommand(struct Scsi_Host *shost,
6314 struct scsi_cmnd *scsi_cmd)
6315{
6316 struct ipr_ioa_cfg *ioa_cfg;
6317 struct ipr_resource_entry *res;
6318 struct ipr_ioarcb *ioarcb;
6319 struct ipr_cmnd *ipr_cmd;
6320 unsigned long hrrq_flags, lock_flags;
6321 int rc;
6322 struct ipr_hrr_queue *hrrq;
6323 int hrrq_id;
6324
6325 ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
6326
6327 scsi_cmd->result = (DID_OK << 16);
6328 res = scsi_cmd->device->hostdata;
6329
6330 if (ipr_is_gata(res) && res->sata_port) {
6331 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
6332 rc = ata_sas_queuecmd(scsi_cmd, res->sata_port->ap);
6333 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
6334 return rc;
6335 }
6336
6337 hrrq_id = ipr_get_hrrq_index(ioa_cfg);
6338 hrrq = &ioa_cfg->hrrq[hrrq_id];
6339
6340 spin_lock_irqsave(hrrq->lock, hrrq_flags);
6341
6342
6343
6344
6345
6346 if (unlikely(!hrrq->allow_cmds && !hrrq->ioa_is_dead && !hrrq->removing_ioa)) {
6347 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
6348 return SCSI_MLQUEUE_HOST_BUSY;
6349 }
6350
6351
6352
6353
6354
6355 if (unlikely(hrrq->ioa_is_dead || hrrq->removing_ioa || !res)) {
6356 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
6357 goto err_nodev;
6358 }
6359
6360 ipr_cmd = __ipr_get_free_ipr_cmnd(hrrq);
6361 if (ipr_cmd == NULL) {
6362 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
6363 return SCSI_MLQUEUE_HOST_BUSY;
6364 }
6365 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
6366
6367 ipr_init_ipr_cmnd(ipr_cmd, ipr_scsi_done);
6368 ioarcb = &ipr_cmd->ioarcb;
6369
6370 memcpy(ioarcb->cmd_pkt.cdb, scsi_cmd->cmnd, scsi_cmd->cmd_len);
6371 ipr_cmd->scsi_cmd = scsi_cmd;
6372 ipr_cmd->done = ipr_scsi_eh_done;
6373
6374 if (ipr_is_gscsi(res)) {
6375 if (scsi_cmd->underflow == 0)
6376 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_NO_ULEN_CHK;
6377
6378 if (res->reset_occurred) {
6379 res->reset_occurred = 0;
6380 ioarcb->cmd_pkt.flags_lo |= IPR_FLAGS_LO_DELAY_AFTER_RST;
6381 }
6382 }
6383
6384 if (ipr_is_gscsi(res) || ipr_is_vset_device(res)) {
6385 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_NO_LINK_DESC;
6386
6387 ioarcb->cmd_pkt.flags_lo |= IPR_FLAGS_LO_ALIGNED_BFR;
6388 if (scsi_cmd->flags & SCMD_TAGGED)
6389 ioarcb->cmd_pkt.flags_lo |= IPR_FLAGS_LO_SIMPLE_TASK;
6390 else
6391 ioarcb->cmd_pkt.flags_lo |= IPR_FLAGS_LO_UNTAGGED_TASK;
6392 }
6393
6394 if (scsi_cmd->cmnd[0] >= 0xC0 &&
6395 (!ipr_is_gscsi(res) || scsi_cmd->cmnd[0] == IPR_QUERY_RSRC_STATE)) {
6396 ioarcb->cmd_pkt.request_type = IPR_RQTYPE_IOACMD;
6397 }
6398 if (res->raw_mode && ipr_is_af_dasd_device(res)) {
6399 ioarcb->cmd_pkt.request_type = IPR_RQTYPE_PIPE;
6400
6401 if (scsi_cmd->underflow == 0)
6402 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_NO_ULEN_CHK;
6403 }
6404
6405 if (ioa_cfg->sis64)
6406 rc = ipr_build_ioadl64(ioa_cfg, ipr_cmd);
6407 else
6408 rc = ipr_build_ioadl(ioa_cfg, ipr_cmd);
6409
6410 spin_lock_irqsave(hrrq->lock, hrrq_flags);
6411 if (unlikely(rc || (!hrrq->allow_cmds && !hrrq->ioa_is_dead))) {
6412 list_add_tail(&ipr_cmd->queue, &hrrq->hrrq_free_q);
6413 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
6414 if (!rc)
6415 scsi_dma_unmap(scsi_cmd);
6416 return SCSI_MLQUEUE_HOST_BUSY;
6417 }
6418
6419 if (unlikely(hrrq->ioa_is_dead)) {
6420 list_add_tail(&ipr_cmd->queue, &hrrq->hrrq_free_q);
6421 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
6422 scsi_dma_unmap(scsi_cmd);
6423 goto err_nodev;
6424 }
6425
6426 ioarcb->res_handle = res->res_handle;
6427 if (res->needs_sync_complete) {
6428 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_SYNC_COMPLETE;
6429 res->needs_sync_complete = 0;
6430 }
6431 list_add_tail(&ipr_cmd->queue, &hrrq->hrrq_pending_q);
6432 ipr_trc_hook(ipr_cmd, IPR_TRACE_START, IPR_GET_RES_PHYS_LOC(res));
6433 ipr_send_command(ipr_cmd);
6434 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
6435 return 0;
6436
6437err_nodev:
6438 spin_lock_irqsave(hrrq->lock, hrrq_flags);
6439 memset(scsi_cmd->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
6440 scsi_cmd->result = (DID_NO_CONNECT << 16);
6441 scsi_cmd->scsi_done(scsi_cmd);
6442 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
6443 return 0;
6444}
6445
6446
6447
6448
6449
6450
6451
6452
6453
6454
6455static int ipr_ioctl(struct scsi_device *sdev, int cmd, void __user *arg)
6456{
6457 struct ipr_resource_entry *res;
6458
6459 res = (struct ipr_resource_entry *)sdev->hostdata;
6460 if (res && ipr_is_gata(res)) {
6461 if (cmd == HDIO_GET_IDENTITY)
6462 return -ENOTTY;
6463 return ata_sas_scsi_ioctl(res->sata_port->ap, sdev, cmd, arg);
6464 }
6465
6466 return -EINVAL;
6467}
6468
6469
6470
6471
6472
6473
6474
6475
6476static const char *ipr_ioa_info(struct Scsi_Host *host)
6477{
6478 static char buffer[512];
6479 struct ipr_ioa_cfg *ioa_cfg;
6480 unsigned long lock_flags = 0;
6481
6482 ioa_cfg = (struct ipr_ioa_cfg *) host->hostdata;
6483
6484 spin_lock_irqsave(host->host_lock, lock_flags);
6485 sprintf(buffer, "IBM %X Storage Adapter", ioa_cfg->type);
6486 spin_unlock_irqrestore(host->host_lock, lock_flags);
6487
6488 return buffer;
6489}
6490
6491static struct scsi_host_template driver_template = {
6492 .module = THIS_MODULE,
6493 .name = "IPR",
6494 .info = ipr_ioa_info,
6495 .ioctl = ipr_ioctl,
6496 .queuecommand = ipr_queuecommand,
6497 .eh_abort_handler = ipr_eh_abort,
6498 .eh_device_reset_handler = ipr_eh_dev_reset,
6499 .eh_host_reset_handler = ipr_eh_host_reset,
6500 .slave_alloc = ipr_slave_alloc,
6501 .slave_configure = ipr_slave_configure,
6502 .slave_destroy = ipr_slave_destroy,
6503 .scan_finished = ipr_scan_finished,
6504 .target_alloc = ipr_target_alloc,
6505 .target_destroy = ipr_target_destroy,
6506 .change_queue_depth = ipr_change_queue_depth,
6507 .bios_param = ipr_biosparam,
6508 .can_queue = IPR_MAX_COMMANDS,
6509 .this_id = -1,
6510 .sg_tablesize = IPR_MAX_SGLIST,
6511 .max_sectors = IPR_IOA_MAX_SECTORS,
6512 .cmd_per_lun = IPR_MAX_CMD_PER_LUN,
6513 .use_clustering = ENABLE_CLUSTERING,
6514 .shost_attrs = ipr_ioa_attrs,
6515 .sdev_attrs = ipr_dev_attrs,
6516 .proc_name = IPR_NAME,
6517};
6518
6519
6520
6521
6522
6523
6524static void ipr_ata_phy_reset(struct ata_port *ap)
6525{
6526 unsigned long flags;
6527 struct ipr_sata_port *sata_port = ap->private_data;
6528 struct ipr_resource_entry *res = sata_port->res;
6529 struct ipr_ioa_cfg *ioa_cfg = sata_port->ioa_cfg;
6530 int rc;
6531
6532 ENTER;
6533 spin_lock_irqsave(ioa_cfg->host->host_lock, flags);
6534 while (ioa_cfg->in_reset_reload) {
6535 spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags);
6536 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
6537 spin_lock_irqsave(ioa_cfg->host->host_lock, flags);
6538 }
6539
6540 if (!ioa_cfg->hrrq[IPR_INIT_HRRQ].allow_cmds)
6541 goto out_unlock;
6542
6543 rc = ipr_device_reset(ioa_cfg, res);
6544
6545 if (rc) {
6546 ap->link.device[0].class = ATA_DEV_NONE;
6547 goto out_unlock;
6548 }
6549
6550 ap->link.device[0].class = res->ata_class;
6551 if (ap->link.device[0].class == ATA_DEV_UNKNOWN)
6552 ap->link.device[0].class = ATA_DEV_NONE;
6553
6554out_unlock:
6555 spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags);
6556 LEAVE;
6557}
6558
6559
6560
6561
6562
6563
6564
6565
6566static void ipr_ata_post_internal(struct ata_queued_cmd *qc)
6567{
6568 struct ipr_sata_port *sata_port = qc->ap->private_data;
6569 struct ipr_ioa_cfg *ioa_cfg = sata_port->ioa_cfg;
6570 struct ipr_cmnd *ipr_cmd;
6571 struct ipr_hrr_queue *hrrq;
6572 unsigned long flags;
6573
6574 spin_lock_irqsave(ioa_cfg->host->host_lock, flags);
6575 while (ioa_cfg->in_reset_reload) {
6576 spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags);
6577 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
6578 spin_lock_irqsave(ioa_cfg->host->host_lock, flags);
6579 }
6580
6581 for_each_hrrq(hrrq, ioa_cfg) {
6582 spin_lock(&hrrq->_lock);
6583 list_for_each_entry(ipr_cmd, &hrrq->hrrq_pending_q, queue) {
6584 if (ipr_cmd->qc == qc) {
6585 ipr_device_reset(ioa_cfg, sata_port->res);
6586 break;
6587 }
6588 }
6589 spin_unlock(&hrrq->_lock);
6590 }
6591 spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags);
6592}
6593
6594
6595
6596
6597
6598
6599
6600
6601
6602static void ipr_copy_sata_tf(struct ipr_ioarcb_ata_regs *regs,
6603 struct ata_taskfile *tf)
6604{
6605 regs->feature = tf->feature;
6606 regs->nsect = tf->nsect;
6607 regs->lbal = tf->lbal;
6608 regs->lbam = tf->lbam;
6609 regs->lbah = tf->lbah;
6610 regs->device = tf->device;
6611 regs->command = tf->command;
6612 regs->hob_feature = tf->hob_feature;
6613 regs->hob_nsect = tf->hob_nsect;
6614 regs->hob_lbal = tf->hob_lbal;
6615 regs->hob_lbam = tf->hob_lbam;
6616 regs->hob_lbah = tf->hob_lbah;
6617 regs->ctl = tf->ctl;
6618}
6619
6620
6621
6622
6623
6624
6625
6626
6627
6628
6629
6630static void ipr_sata_done(struct ipr_cmnd *ipr_cmd)
6631{
6632 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
6633 struct ata_queued_cmd *qc = ipr_cmd->qc;
6634 struct ipr_sata_port *sata_port = qc->ap->private_data;
6635 struct ipr_resource_entry *res = sata_port->res;
6636 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
6637
6638 spin_lock(&ipr_cmd->hrrq->_lock);
6639 if (ipr_cmd->ioa_cfg->sis64)
6640 memcpy(&sata_port->ioasa, &ipr_cmd->s.ioasa64.u.gata,
6641 sizeof(struct ipr_ioasa_gata));
6642 else
6643 memcpy(&sata_port->ioasa, &ipr_cmd->s.ioasa.u.gata,
6644 sizeof(struct ipr_ioasa_gata));
6645 ipr_dump_ioasa(ioa_cfg, ipr_cmd, res);
6646
6647 if (be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc_specific) & IPR_ATA_DEVICE_WAS_RESET)
6648 scsi_report_device_reset(ioa_cfg->host, res->bus, res->target);
6649
6650 if (IPR_IOASC_SENSE_KEY(ioasc) > RECOVERED_ERROR)
6651 qc->err_mask |= __ac_err_mask(sata_port->ioasa.status);
6652 else
6653 qc->err_mask |= ac_err_mask(sata_port->ioasa.status);
6654 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
6655 spin_unlock(&ipr_cmd->hrrq->_lock);
6656 ata_qc_complete(qc);
6657}
6658
6659
6660
6661
6662
6663
6664
6665static void ipr_build_ata_ioadl64(struct ipr_cmnd *ipr_cmd,
6666 struct ata_queued_cmd *qc)
6667{
6668 u32 ioadl_flags = 0;
6669 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
6670 struct ipr_ioadl64_desc *ioadl64 = ipr_cmd->i.ata_ioadl.ioadl64;
6671 struct ipr_ioadl64_desc *last_ioadl64 = NULL;
6672 int len = qc->nbytes;
6673 struct scatterlist *sg;
6674 unsigned int si;
6675 dma_addr_t dma_addr = ipr_cmd->dma_addr;
6676
6677 if (len == 0)
6678 return;
6679
6680 if (qc->dma_dir == DMA_TO_DEVICE) {
6681 ioadl_flags = IPR_IOADL_FLAGS_WRITE;
6682 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_WRITE_NOT_READ;
6683 } else if (qc->dma_dir == DMA_FROM_DEVICE)
6684 ioadl_flags = IPR_IOADL_FLAGS_READ;
6685
6686 ioarcb->data_transfer_length = cpu_to_be32(len);
6687 ioarcb->ioadl_len =
6688 cpu_to_be32(sizeof(struct ipr_ioadl64_desc) * ipr_cmd->dma_use_sg);
6689 ioarcb->u.sis64_addr_data.data_ioadl_addr =
6690 cpu_to_be64(dma_addr + offsetof(struct ipr_cmnd, i.ata_ioadl.ioadl64));
6691
6692 for_each_sg(qc->sg, sg, qc->n_elem, si) {
6693 ioadl64->flags = cpu_to_be32(ioadl_flags);
6694 ioadl64->data_len = cpu_to_be32(sg_dma_len(sg));
6695 ioadl64->address = cpu_to_be64(sg_dma_address(sg));
6696
6697 last_ioadl64 = ioadl64;
6698 ioadl64++;
6699 }
6700
6701 if (likely(last_ioadl64))
6702 last_ioadl64->flags |= cpu_to_be32(IPR_IOADL_FLAGS_LAST);
6703}
6704
6705
6706
6707
6708
6709
6710
6711static void ipr_build_ata_ioadl(struct ipr_cmnd *ipr_cmd,
6712 struct ata_queued_cmd *qc)
6713{
6714 u32 ioadl_flags = 0;
6715 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
6716 struct ipr_ioadl_desc *ioadl = ipr_cmd->i.ioadl;
6717 struct ipr_ioadl_desc *last_ioadl = NULL;
6718 int len = qc->nbytes;
6719 struct scatterlist *sg;
6720 unsigned int si;
6721
6722 if (len == 0)
6723 return;
6724
6725 if (qc->dma_dir == DMA_TO_DEVICE) {
6726 ioadl_flags = IPR_IOADL_FLAGS_WRITE;
6727 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_WRITE_NOT_READ;
6728 ioarcb->data_transfer_length = cpu_to_be32(len);
6729 ioarcb->ioadl_len =
6730 cpu_to_be32(sizeof(struct ipr_ioadl_desc) * ipr_cmd->dma_use_sg);
6731 } else if (qc->dma_dir == DMA_FROM_DEVICE) {
6732 ioadl_flags = IPR_IOADL_FLAGS_READ;
6733 ioarcb->read_data_transfer_length = cpu_to_be32(len);
6734 ioarcb->read_ioadl_len =
6735 cpu_to_be32(sizeof(struct ipr_ioadl_desc) * ipr_cmd->dma_use_sg);
6736 }
6737
6738 for_each_sg(qc->sg, sg, qc->n_elem, si) {
6739 ioadl->flags_and_data_len = cpu_to_be32(ioadl_flags | sg_dma_len(sg));
6740 ioadl->address = cpu_to_be32(sg_dma_address(sg));
6741
6742 last_ioadl = ioadl;
6743 ioadl++;
6744 }
6745
6746 if (likely(last_ioadl))
6747 last_ioadl->flags_and_data_len |= cpu_to_be32(IPR_IOADL_FLAGS_LAST);
6748}
6749
6750
6751
6752
6753
6754
6755
6756
6757static int ipr_qc_defer(struct ata_queued_cmd *qc)
6758{
6759 struct ata_port *ap = qc->ap;
6760 struct ipr_sata_port *sata_port = ap->private_data;
6761 struct ipr_ioa_cfg *ioa_cfg = sata_port->ioa_cfg;
6762 struct ipr_cmnd *ipr_cmd;
6763 struct ipr_hrr_queue *hrrq;
6764 int hrrq_id;
6765
6766 hrrq_id = ipr_get_hrrq_index(ioa_cfg);
6767 hrrq = &ioa_cfg->hrrq[hrrq_id];
6768
6769 qc->lldd_task = NULL;
6770 spin_lock(&hrrq->_lock);
6771 if (unlikely(hrrq->ioa_is_dead)) {
6772 spin_unlock(&hrrq->_lock);
6773 return 0;
6774 }
6775
6776 if (unlikely(!hrrq->allow_cmds)) {
6777 spin_unlock(&hrrq->_lock);
6778 return ATA_DEFER_LINK;
6779 }
6780
6781 ipr_cmd = __ipr_get_free_ipr_cmnd(hrrq);
6782 if (ipr_cmd == NULL) {
6783 spin_unlock(&hrrq->_lock);
6784 return ATA_DEFER_LINK;
6785 }
6786
6787 qc->lldd_task = ipr_cmd;
6788 spin_unlock(&hrrq->_lock);
6789 return 0;
6790}
6791
6792
6793
6794
6795
6796
6797
6798
6799static unsigned int ipr_qc_issue(struct ata_queued_cmd *qc)
6800{
6801 struct ata_port *ap = qc->ap;
6802 struct ipr_sata_port *sata_port = ap->private_data;
6803 struct ipr_resource_entry *res = sata_port->res;
6804 struct ipr_ioa_cfg *ioa_cfg = sata_port->ioa_cfg;
6805 struct ipr_cmnd *ipr_cmd;
6806 struct ipr_ioarcb *ioarcb;
6807 struct ipr_ioarcb_ata_regs *regs;
6808
6809 if (qc->lldd_task == NULL)
6810 ipr_qc_defer(qc);
6811
6812 ipr_cmd = qc->lldd_task;
6813 if (ipr_cmd == NULL)
6814 return AC_ERR_SYSTEM;
6815
6816 qc->lldd_task = NULL;
6817 spin_lock(&ipr_cmd->hrrq->_lock);
6818 if (unlikely(!ipr_cmd->hrrq->allow_cmds ||
6819 ipr_cmd->hrrq->ioa_is_dead)) {
6820 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
6821 spin_unlock(&ipr_cmd->hrrq->_lock);
6822 return AC_ERR_SYSTEM;
6823 }
6824
6825 ipr_init_ipr_cmnd(ipr_cmd, ipr_lock_and_done);
6826 ioarcb = &ipr_cmd->ioarcb;
6827
6828 if (ioa_cfg->sis64) {
6829 regs = &ipr_cmd->i.ata_ioadl.regs;
6830 ioarcb->add_cmd_parms_offset = cpu_to_be16(sizeof(*ioarcb));
6831 } else
6832 regs = &ioarcb->u.add_data.u.regs;
6833
6834 memset(regs, 0, sizeof(*regs));
6835 ioarcb->add_cmd_parms_len = cpu_to_be16(sizeof(*regs));
6836
6837 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_pending_q);
6838 ipr_cmd->qc = qc;
6839 ipr_cmd->done = ipr_sata_done;
6840 ipr_cmd->ioarcb.res_handle = res->res_handle;
6841 ioarcb->cmd_pkt.request_type = IPR_RQTYPE_ATA_PASSTHRU;
6842 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_NO_LINK_DESC;
6843 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_NO_ULEN_CHK;
6844 ipr_cmd->dma_use_sg = qc->n_elem;
6845
6846 if (ioa_cfg->sis64)
6847 ipr_build_ata_ioadl64(ipr_cmd, qc);
6848 else
6849 ipr_build_ata_ioadl(ipr_cmd, qc);
6850
6851 regs->flags |= IPR_ATA_FLAG_STATUS_ON_GOOD_COMPLETION;
6852 ipr_copy_sata_tf(regs, &qc->tf);
6853 memcpy(ioarcb->cmd_pkt.cdb, qc->cdb, IPR_MAX_CDB_LEN);
6854 ipr_trc_hook(ipr_cmd, IPR_TRACE_START, IPR_GET_RES_PHYS_LOC(res));
6855
6856 switch (qc->tf.protocol) {
6857 case ATA_PROT_NODATA:
6858 case ATA_PROT_PIO:
6859 break;
6860
6861 case ATA_PROT_DMA:
6862 regs->flags |= IPR_ATA_FLAG_XFER_TYPE_DMA;
6863 break;
6864
6865 case ATAPI_PROT_PIO:
6866 case ATAPI_PROT_NODATA:
6867 regs->flags |= IPR_ATA_FLAG_PACKET_CMD;
6868 break;
6869
6870 case ATAPI_PROT_DMA:
6871 regs->flags |= IPR_ATA_FLAG_PACKET_CMD;
6872 regs->flags |= IPR_ATA_FLAG_XFER_TYPE_DMA;
6873 break;
6874
6875 default:
6876 WARN_ON(1);
6877 spin_unlock(&ipr_cmd->hrrq->_lock);
6878 return AC_ERR_INVALID;
6879 }
6880
6881 ipr_send_command(ipr_cmd);
6882 spin_unlock(&ipr_cmd->hrrq->_lock);
6883
6884 return 0;
6885}
6886
6887
6888
6889
6890
6891
6892
6893
6894static bool ipr_qc_fill_rtf(struct ata_queued_cmd *qc)
6895{
6896 struct ipr_sata_port *sata_port = qc->ap->private_data;
6897 struct ipr_ioasa_gata *g = &sata_port->ioasa;
6898 struct ata_taskfile *tf = &qc->result_tf;
6899
6900 tf->feature = g->error;
6901 tf->nsect = g->nsect;
6902 tf->lbal = g->lbal;
6903 tf->lbam = g->lbam;
6904 tf->lbah = g->lbah;
6905 tf->device = g->device;
6906 tf->command = g->status;
6907 tf->hob_nsect = g->hob_nsect;
6908 tf->hob_lbal = g->hob_lbal;
6909 tf->hob_lbam = g->hob_lbam;
6910 tf->hob_lbah = g->hob_lbah;
6911
6912 return true;
6913}
6914
6915static struct ata_port_operations ipr_sata_ops = {
6916 .phy_reset = ipr_ata_phy_reset,
6917 .hardreset = ipr_sata_reset,
6918 .post_internal_cmd = ipr_ata_post_internal,
6919 .qc_prep = ata_noop_qc_prep,
6920 .qc_defer = ipr_qc_defer,
6921 .qc_issue = ipr_qc_issue,
6922 .qc_fill_rtf = ipr_qc_fill_rtf,
6923 .port_start = ata_sas_port_start,
6924 .port_stop = ata_sas_port_stop
6925};
6926
6927static struct ata_port_info sata_port_info = {
6928 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA |
6929 ATA_FLAG_SAS_HOST,
6930 .pio_mask = ATA_PIO4_ONLY,
6931 .mwdma_mask = ATA_MWDMA2,
6932 .udma_mask = ATA_UDMA6,
6933 .port_ops = &ipr_sata_ops
6934};
6935
6936#ifdef CONFIG_PPC_PSERIES
6937static const u16 ipr_blocked_processors[] = {
6938 PVR_NORTHSTAR,
6939 PVR_PULSAR,
6940 PVR_POWER4,
6941 PVR_ICESTAR,
6942 PVR_SSTAR,
6943 PVR_POWER4p,
6944 PVR_630,
6945 PVR_630p
6946};
6947
6948
6949
6950
6951
6952
6953
6954
6955
6956
6957
6958
6959static int ipr_invalid_adapter(struct ipr_ioa_cfg *ioa_cfg)
6960{
6961 int i;
6962
6963 if ((ioa_cfg->type == 0x5702) && (ioa_cfg->pdev->revision < 4)) {
6964 for (i = 0; i < ARRAY_SIZE(ipr_blocked_processors); i++) {
6965 if (pvr_version_is(ipr_blocked_processors[i]))
6966 return 1;
6967 }
6968 }
6969 return 0;
6970}
6971#else
6972#define ipr_invalid_adapter(ioa_cfg) 0
6973#endif
6974
6975
6976
6977
6978
6979
6980
6981
6982
6983
6984
6985static int ipr_ioa_bringdown_done(struct ipr_cmnd *ipr_cmd)
6986{
6987 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
6988 int i;
6989
6990 ENTER;
6991 if (!ioa_cfg->hrrq[IPR_INIT_HRRQ].removing_ioa) {
6992 ipr_trace;
6993 spin_unlock_irq(ioa_cfg->host->host_lock);
6994 scsi_unblock_requests(ioa_cfg->host);
6995 spin_lock_irq(ioa_cfg->host->host_lock);
6996 }
6997
6998 ioa_cfg->in_reset_reload = 0;
6999 ioa_cfg->reset_retries = 0;
7000 for (i = 0; i < ioa_cfg->hrrq_num; i++) {
7001 spin_lock(&ioa_cfg->hrrq[i]._lock);
7002 ioa_cfg->hrrq[i].ioa_is_dead = 1;
7003 spin_unlock(&ioa_cfg->hrrq[i]._lock);
7004 }
7005 wmb();
7006
7007 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
7008 wake_up_all(&ioa_cfg->reset_wait_q);
7009 LEAVE;
7010
7011 return IPR_RC_JOB_RETURN;
7012}
7013
7014
7015
7016
7017
7018
7019
7020
7021
7022
7023
7024
7025static int ipr_ioa_reset_done(struct ipr_cmnd *ipr_cmd)
7026{
7027 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7028 struct ipr_resource_entry *res;
7029 struct ipr_hostrcb *hostrcb, *temp;
7030 int i = 0, j;
7031
7032 ENTER;
7033 ioa_cfg->in_reset_reload = 0;
7034 for (j = 0; j < ioa_cfg->hrrq_num; j++) {
7035 spin_lock(&ioa_cfg->hrrq[j]._lock);
7036 ioa_cfg->hrrq[j].allow_cmds = 1;
7037 spin_unlock(&ioa_cfg->hrrq[j]._lock);
7038 }
7039 wmb();
7040 ioa_cfg->reset_cmd = NULL;
7041 ioa_cfg->doorbell |= IPR_RUNTIME_RESET;
7042
7043 list_for_each_entry(res, &ioa_cfg->used_res_q, queue) {
7044 if (res->add_to_ml || res->del_from_ml) {
7045 ipr_trace;
7046 break;
7047 }
7048 }
7049 schedule_work(&ioa_cfg->work_q);
7050
7051 list_for_each_entry_safe(hostrcb, temp, &ioa_cfg->hostrcb_free_q, queue) {
7052 list_del(&hostrcb->queue);
7053 if (i++ < IPR_NUM_LOG_HCAMS)
7054 ipr_send_hcam(ioa_cfg, IPR_HCAM_CDB_OP_CODE_LOG_DATA, hostrcb);
7055 else
7056 ipr_send_hcam(ioa_cfg, IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE, hostrcb);
7057 }
7058
7059 scsi_report_bus_reset(ioa_cfg->host, IPR_VSET_BUS);
7060 dev_info(&ioa_cfg->pdev->dev, "IOA initialized.\n");
7061
7062 ioa_cfg->reset_retries = 0;
7063 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
7064 wake_up_all(&ioa_cfg->reset_wait_q);
7065
7066 spin_unlock(ioa_cfg->host->host_lock);
7067 scsi_unblock_requests(ioa_cfg->host);
7068 spin_lock(ioa_cfg->host->host_lock);
7069
7070 if (!ioa_cfg->hrrq[IPR_INIT_HRRQ].allow_cmds)
7071 scsi_block_requests(ioa_cfg->host);
7072
7073 schedule_work(&ioa_cfg->work_q);
7074 LEAVE;
7075 return IPR_RC_JOB_RETURN;
7076}
7077
7078
7079
7080
7081
7082
7083
7084
7085
7086static void ipr_set_sup_dev_dflt(struct ipr_supported_device *supported_dev,
7087 struct ipr_std_inq_vpids *vpids)
7088{
7089 memset(supported_dev, 0, sizeof(struct ipr_supported_device));
7090 memcpy(&supported_dev->vpids, vpids, sizeof(struct ipr_std_inq_vpids));
7091 supported_dev->num_records = 1;
7092 supported_dev->data_length =
7093 cpu_to_be16(sizeof(struct ipr_supported_device));
7094 supported_dev->reserved = 0;
7095}
7096
7097
7098
7099
7100
7101
7102
7103
7104
7105
7106static int ipr_set_supported_devs(struct ipr_cmnd *ipr_cmd)
7107{
7108 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7109 struct ipr_supported_device *supp_dev = &ioa_cfg->vpd_cbs->supp_dev;
7110 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
7111 struct ipr_resource_entry *res = ipr_cmd->u.res;
7112
7113 ipr_cmd->job_step = ipr_ioa_reset_done;
7114
7115 list_for_each_entry_continue(res, &ioa_cfg->used_res_q, queue) {
7116 if (!ipr_is_scsi_disk(res))
7117 continue;
7118
7119 ipr_cmd->u.res = res;
7120 ipr_set_sup_dev_dflt(supp_dev, &res->std_inq_data.vpids);
7121
7122 ioarcb->res_handle = cpu_to_be32(IPR_IOA_RES_HANDLE);
7123 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_WRITE_NOT_READ;
7124 ioarcb->cmd_pkt.request_type = IPR_RQTYPE_IOACMD;
7125
7126 ioarcb->cmd_pkt.cdb[0] = IPR_SET_SUPPORTED_DEVICES;
7127 ioarcb->cmd_pkt.cdb[1] = IPR_SET_ALL_SUPPORTED_DEVICES;
7128 ioarcb->cmd_pkt.cdb[7] = (sizeof(struct ipr_supported_device) >> 8) & 0xff;
7129 ioarcb->cmd_pkt.cdb[8] = sizeof(struct ipr_supported_device) & 0xff;
7130
7131 ipr_init_ioadl(ipr_cmd,
7132 ioa_cfg->vpd_cbs_dma +
7133 offsetof(struct ipr_misc_cbs, supp_dev),
7134 sizeof(struct ipr_supported_device),
7135 IPR_IOADL_FLAGS_WRITE_LAST);
7136
7137 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout,
7138 IPR_SET_SUP_DEVICE_TIMEOUT);
7139
7140 if (!ioa_cfg->sis64)
7141 ipr_cmd->job_step = ipr_set_supported_devs;
7142 LEAVE;
7143 return IPR_RC_JOB_RETURN;
7144 }
7145
7146 LEAVE;
7147 return IPR_RC_JOB_CONTINUE;
7148}
7149
7150
7151
7152
7153
7154
7155
7156
7157
7158
7159static void *ipr_get_mode_page(struct ipr_mode_pages *mode_pages,
7160 u32 page_code, u32 len)
7161{
7162 struct ipr_mode_page_hdr *mode_hdr;
7163 u32 page_length;
7164 u32 length;
7165
7166 if (!mode_pages || (mode_pages->hdr.length == 0))
7167 return NULL;
7168
7169 length = (mode_pages->hdr.length + 1) - 4 - mode_pages->hdr.block_desc_len;
7170 mode_hdr = (struct ipr_mode_page_hdr *)
7171 (mode_pages->data + mode_pages->hdr.block_desc_len);
7172
7173 while (length) {
7174 if (IPR_GET_MODE_PAGE_CODE(mode_hdr) == page_code) {
7175 if (mode_hdr->page_length >= (len - sizeof(struct ipr_mode_page_hdr)))
7176 return mode_hdr;
7177 break;
7178 } else {
7179 page_length = (sizeof(struct ipr_mode_page_hdr) +
7180 mode_hdr->page_length);
7181 length -= page_length;
7182 mode_hdr = (struct ipr_mode_page_hdr *)
7183 ((unsigned long)mode_hdr + page_length);
7184 }
7185 }
7186 return NULL;
7187}
7188
7189
7190
7191
7192
7193
7194
7195
7196
7197
7198
7199static void ipr_check_term_power(struct ipr_ioa_cfg *ioa_cfg,
7200 struct ipr_mode_pages *mode_pages)
7201{
7202 int i;
7203 int entry_length;
7204 struct ipr_dev_bus_entry *bus;
7205 struct ipr_mode_page28 *mode_page;
7206
7207 mode_page = ipr_get_mode_page(mode_pages, 0x28,
7208 sizeof(struct ipr_mode_page28));
7209
7210 entry_length = mode_page->entry_length;
7211
7212 bus = mode_page->bus;
7213
7214 for (i = 0; i < mode_page->num_entries; i++) {
7215 if (bus->flags & IPR_SCSI_ATTR_NO_TERM_PWR) {
7216 dev_err(&ioa_cfg->pdev->dev,
7217 "Term power is absent on scsi bus %d\n",
7218 bus->res_addr.bus);
7219 }
7220
7221 bus = (struct ipr_dev_bus_entry *)((char *)bus + entry_length);
7222 }
7223}
7224
7225
7226
7227
7228
7229
7230
7231
7232
7233
7234
7235
7236static void ipr_scsi_bus_speed_limit(struct ipr_ioa_cfg *ioa_cfg)
7237{
7238 u32 max_xfer_rate;
7239 int i;
7240
7241 for (i = 0; i < IPR_MAX_NUM_BUSES; i++) {
7242 max_xfer_rate = ipr_get_max_scsi_speed(ioa_cfg, i,
7243 ioa_cfg->bus_attr[i].bus_width);
7244
7245 if (max_xfer_rate < ioa_cfg->bus_attr[i].max_xfer_rate)
7246 ioa_cfg->bus_attr[i].max_xfer_rate = max_xfer_rate;
7247 }
7248}
7249
7250
7251
7252
7253
7254
7255
7256
7257
7258
7259
7260static void ipr_modify_ioafp_mode_page_28(struct ipr_ioa_cfg *ioa_cfg,
7261 struct ipr_mode_pages *mode_pages)
7262{
7263 int i, entry_length;
7264 struct ipr_dev_bus_entry *bus;
7265 struct ipr_bus_attributes *bus_attr;
7266 struct ipr_mode_page28 *mode_page;
7267
7268 mode_page = ipr_get_mode_page(mode_pages, 0x28,
7269 sizeof(struct ipr_mode_page28));
7270
7271 entry_length = mode_page->entry_length;
7272
7273
7274 for (i = 0, bus = mode_page->bus;
7275 i < mode_page->num_entries;
7276 i++, bus = (struct ipr_dev_bus_entry *)((u8 *)bus + entry_length)) {
7277 if (bus->res_addr.bus > IPR_MAX_NUM_BUSES) {
7278 dev_err(&ioa_cfg->pdev->dev,
7279 "Invalid resource address reported: 0x%08X\n",
7280 IPR_GET_PHYS_LOC(bus->res_addr));
7281 continue;
7282 }
7283
7284 bus_attr = &ioa_cfg->bus_attr[i];
7285 bus->extended_reset_delay = IPR_EXTENDED_RESET_DELAY;
7286 bus->bus_width = bus_attr->bus_width;
7287 bus->max_xfer_rate = cpu_to_be32(bus_attr->max_xfer_rate);
7288 bus->flags &= ~IPR_SCSI_ATTR_QAS_MASK;
7289 if (bus_attr->qas_enabled)
7290 bus->flags |= IPR_SCSI_ATTR_ENABLE_QAS;
7291 else
7292 bus->flags |= IPR_SCSI_ATTR_DISABLE_QAS;
7293 }
7294}
7295
7296
7297
7298
7299
7300
7301
7302
7303
7304
7305
7306
7307static void ipr_build_mode_select(struct ipr_cmnd *ipr_cmd,
7308 __be32 res_handle, u8 parm,
7309 dma_addr_t dma_addr, u8 xfer_len)
7310{
7311 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
7312
7313 ioarcb->res_handle = res_handle;
7314 ioarcb->cmd_pkt.request_type = IPR_RQTYPE_SCSICDB;
7315 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_WRITE_NOT_READ;
7316 ioarcb->cmd_pkt.cdb[0] = MODE_SELECT;
7317 ioarcb->cmd_pkt.cdb[1] = parm;
7318 ioarcb->cmd_pkt.cdb[4] = xfer_len;
7319
7320 ipr_init_ioadl(ipr_cmd, dma_addr, xfer_len, IPR_IOADL_FLAGS_WRITE_LAST);
7321}
7322
7323
7324
7325
7326
7327
7328
7329
7330
7331
7332
7333static int ipr_ioafp_mode_select_page28(struct ipr_cmnd *ipr_cmd)
7334{
7335 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7336 struct ipr_mode_pages *mode_pages = &ioa_cfg->vpd_cbs->mode_pages;
7337 int length;
7338
7339 ENTER;
7340 ipr_scsi_bus_speed_limit(ioa_cfg);
7341 ipr_check_term_power(ioa_cfg, mode_pages);
7342 ipr_modify_ioafp_mode_page_28(ioa_cfg, mode_pages);
7343 length = mode_pages->hdr.length + 1;
7344 mode_pages->hdr.length = 0;
7345
7346 ipr_build_mode_select(ipr_cmd, cpu_to_be32(IPR_IOA_RES_HANDLE), 0x11,
7347 ioa_cfg->vpd_cbs_dma + offsetof(struct ipr_misc_cbs, mode_pages),
7348 length);
7349
7350 ipr_cmd->job_step = ipr_set_supported_devs;
7351 ipr_cmd->u.res = list_entry(ioa_cfg->used_res_q.next,
7352 struct ipr_resource_entry, queue);
7353 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout, IPR_INTERNAL_TIMEOUT);
7354
7355 LEAVE;
7356 return IPR_RC_JOB_RETURN;
7357}
7358
7359
7360
7361
7362
7363
7364
7365
7366
7367
7368
7369
7370static void ipr_build_mode_sense(struct ipr_cmnd *ipr_cmd,
7371 __be32 res_handle,
7372 u8 parm, dma_addr_t dma_addr, u8 xfer_len)
7373{
7374 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
7375
7376 ioarcb->res_handle = res_handle;
7377 ioarcb->cmd_pkt.cdb[0] = MODE_SENSE;
7378 ioarcb->cmd_pkt.cdb[2] = parm;
7379 ioarcb->cmd_pkt.cdb[4] = xfer_len;
7380 ioarcb->cmd_pkt.request_type = IPR_RQTYPE_SCSICDB;
7381
7382 ipr_init_ioadl(ipr_cmd, dma_addr, xfer_len, IPR_IOADL_FLAGS_READ_LAST);
7383}
7384
7385
7386
7387
7388
7389
7390
7391
7392
7393
7394static int ipr_reset_cmd_failed(struct ipr_cmnd *ipr_cmd)
7395{
7396 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7397 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
7398
7399 dev_err(&ioa_cfg->pdev->dev,
7400 "0x%02X failed with IOASC: 0x%08X\n",
7401 ipr_cmd->ioarcb.cmd_pkt.cdb[0], ioasc);
7402
7403 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
7404 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
7405 return IPR_RC_JOB_RETURN;
7406}
7407
7408
7409
7410
7411
7412
7413
7414
7415
7416
7417
7418static int ipr_reset_mode_sense_failed(struct ipr_cmnd *ipr_cmd)
7419{
7420 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7421 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
7422
7423 if (ioasc == IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT) {
7424 ipr_cmd->job_step = ipr_set_supported_devs;
7425 ipr_cmd->u.res = list_entry(ioa_cfg->used_res_q.next,
7426 struct ipr_resource_entry, queue);
7427 return IPR_RC_JOB_CONTINUE;
7428 }
7429
7430 return ipr_reset_cmd_failed(ipr_cmd);
7431}
7432
7433
7434
7435
7436
7437
7438
7439
7440
7441
7442
7443static int ipr_ioafp_mode_sense_page28(struct ipr_cmnd *ipr_cmd)
7444{
7445 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7446
7447 ENTER;
7448 ipr_build_mode_sense(ipr_cmd, cpu_to_be32(IPR_IOA_RES_HANDLE),
7449 0x28, ioa_cfg->vpd_cbs_dma +
7450 offsetof(struct ipr_misc_cbs, mode_pages),
7451 sizeof(struct ipr_mode_pages));
7452
7453 ipr_cmd->job_step = ipr_ioafp_mode_select_page28;
7454 ipr_cmd->job_step_failed = ipr_reset_mode_sense_failed;
7455
7456 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout, IPR_INTERNAL_TIMEOUT);
7457
7458 LEAVE;
7459 return IPR_RC_JOB_RETURN;
7460}
7461
7462
7463
7464
7465
7466
7467
7468
7469
7470
7471static int ipr_ioafp_mode_select_page24(struct ipr_cmnd *ipr_cmd)
7472{
7473 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7474 struct ipr_mode_pages *mode_pages = &ioa_cfg->vpd_cbs->mode_pages;
7475 struct ipr_mode_page24 *mode_page;
7476 int length;
7477
7478 ENTER;
7479 mode_page = ipr_get_mode_page(mode_pages, 0x24,
7480 sizeof(struct ipr_mode_page24));
7481
7482 if (mode_page)
7483 mode_page->flags |= IPR_ENABLE_DUAL_IOA_AF;
7484
7485 length = mode_pages->hdr.length + 1;
7486 mode_pages->hdr.length = 0;
7487
7488 ipr_build_mode_select(ipr_cmd, cpu_to_be32(IPR_IOA_RES_HANDLE), 0x11,
7489 ioa_cfg->vpd_cbs_dma + offsetof(struct ipr_misc_cbs, mode_pages),
7490 length);
7491
7492 ipr_cmd->job_step = ipr_ioafp_mode_sense_page28;
7493 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout, IPR_INTERNAL_TIMEOUT);
7494
7495 LEAVE;
7496 return IPR_RC_JOB_RETURN;
7497}
7498
7499
7500
7501
7502
7503
7504
7505
7506
7507
7508
7509static int ipr_reset_mode_sense_page24_failed(struct ipr_cmnd *ipr_cmd)
7510{
7511 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
7512
7513 if (ioasc == IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT) {
7514 ipr_cmd->job_step = ipr_ioafp_mode_sense_page28;
7515 return IPR_RC_JOB_CONTINUE;
7516 }
7517
7518 return ipr_reset_cmd_failed(ipr_cmd);
7519}
7520
7521
7522
7523
7524
7525
7526
7527
7528
7529
7530
7531static int ipr_ioafp_mode_sense_page24(struct ipr_cmnd *ipr_cmd)
7532{
7533 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7534
7535 ENTER;
7536 ipr_build_mode_sense(ipr_cmd, cpu_to_be32(IPR_IOA_RES_HANDLE),
7537 0x24, ioa_cfg->vpd_cbs_dma +
7538 offsetof(struct ipr_misc_cbs, mode_pages),
7539 sizeof(struct ipr_mode_pages));
7540
7541 ipr_cmd->job_step = ipr_ioafp_mode_select_page24;
7542 ipr_cmd->job_step_failed = ipr_reset_mode_sense_page24_failed;
7543
7544 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout, IPR_INTERNAL_TIMEOUT);
7545
7546 LEAVE;
7547 return IPR_RC_JOB_RETURN;
7548}
7549
7550
7551
7552
7553
7554
7555
7556
7557
7558
7559
7560
7561
7562static int ipr_init_res_table(struct ipr_cmnd *ipr_cmd)
7563{
7564 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7565 struct ipr_resource_entry *res, *temp;
7566 struct ipr_config_table_entry_wrapper cfgtew;
7567 int entries, found, flag, i;
7568 LIST_HEAD(old_res);
7569
7570 ENTER;
7571 if (ioa_cfg->sis64)
7572 flag = ioa_cfg->u.cfg_table64->hdr64.flags;
7573 else
7574 flag = ioa_cfg->u.cfg_table->hdr.flags;
7575
7576 if (flag & IPR_UCODE_DOWNLOAD_REQ)
7577 dev_err(&ioa_cfg->pdev->dev, "Microcode download required\n");
7578
7579 list_for_each_entry_safe(res, temp, &ioa_cfg->used_res_q, queue)
7580 list_move_tail(&res->queue, &old_res);
7581
7582 if (ioa_cfg->sis64)
7583 entries = be16_to_cpu(ioa_cfg->u.cfg_table64->hdr64.num_entries);
7584 else
7585 entries = ioa_cfg->u.cfg_table->hdr.num_entries;
7586
7587 for (i = 0; i < entries; i++) {
7588 if (ioa_cfg->sis64)
7589 cfgtew.u.cfgte64 = &ioa_cfg->u.cfg_table64->dev[i];
7590 else
7591 cfgtew.u.cfgte = &ioa_cfg->u.cfg_table->dev[i];
7592 found = 0;
7593
7594 list_for_each_entry_safe(res, temp, &old_res, queue) {
7595 if (ipr_is_same_device(res, &cfgtew)) {
7596 list_move_tail(&res->queue, &ioa_cfg->used_res_q);
7597 found = 1;
7598 break;
7599 }
7600 }
7601
7602 if (!found) {
7603 if (list_empty(&ioa_cfg->free_res_q)) {
7604 dev_err(&ioa_cfg->pdev->dev, "Too many devices attached\n");
7605 break;
7606 }
7607
7608 found = 1;
7609 res = list_entry(ioa_cfg->free_res_q.next,
7610 struct ipr_resource_entry, queue);
7611 list_move_tail(&res->queue, &ioa_cfg->used_res_q);
7612 ipr_init_res_entry(res, &cfgtew);
7613 res->add_to_ml = 1;
7614 } else if (res->sdev && (ipr_is_vset_device(res) || ipr_is_scsi_disk(res)))
7615 res->sdev->allow_restart = 1;
7616
7617 if (found)
7618 ipr_update_res_entry(res, &cfgtew);
7619 }
7620
7621 list_for_each_entry_safe(res, temp, &old_res, queue) {
7622 if (res->sdev) {
7623 res->del_from_ml = 1;
7624 res->res_handle = IPR_INVALID_RES_HANDLE;
7625 list_move_tail(&res->queue, &ioa_cfg->used_res_q);
7626 }
7627 }
7628
7629 list_for_each_entry_safe(res, temp, &old_res, queue) {
7630 ipr_clear_res_target(res);
7631 list_move_tail(&res->queue, &ioa_cfg->free_res_q);
7632 }
7633
7634 if (ioa_cfg->dual_raid && ipr_dual_ioa_raid)
7635 ipr_cmd->job_step = ipr_ioafp_mode_sense_page24;
7636 else
7637 ipr_cmd->job_step = ipr_ioafp_mode_sense_page28;
7638
7639 LEAVE;
7640 return IPR_RC_JOB_CONTINUE;
7641}
7642
7643
7644
7645
7646
7647
7648
7649
7650
7651
7652
7653static int ipr_ioafp_query_ioa_cfg(struct ipr_cmnd *ipr_cmd)
7654{
7655 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7656 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
7657 struct ipr_inquiry_page3 *ucode_vpd = &ioa_cfg->vpd_cbs->page3_data;
7658 struct ipr_inquiry_cap *cap = &ioa_cfg->vpd_cbs->cap;
7659
7660 ENTER;
7661 if (cap->cap & IPR_CAP_DUAL_IOA_RAID)
7662 ioa_cfg->dual_raid = 1;
7663 dev_info(&ioa_cfg->pdev->dev, "Adapter firmware version: %02X%02X%02X%02X\n",
7664 ucode_vpd->major_release, ucode_vpd->card_type,
7665 ucode_vpd->minor_release[0], ucode_vpd->minor_release[1]);
7666 ioarcb->cmd_pkt.request_type = IPR_RQTYPE_IOACMD;
7667 ioarcb->res_handle = cpu_to_be32(IPR_IOA_RES_HANDLE);
7668
7669 ioarcb->cmd_pkt.cdb[0] = IPR_QUERY_IOA_CONFIG;
7670 ioarcb->cmd_pkt.cdb[6] = (ioa_cfg->cfg_table_size >> 16) & 0xff;
7671 ioarcb->cmd_pkt.cdb[7] = (ioa_cfg->cfg_table_size >> 8) & 0xff;
7672 ioarcb->cmd_pkt.cdb[8] = ioa_cfg->cfg_table_size & 0xff;
7673
7674 ipr_init_ioadl(ipr_cmd, ioa_cfg->cfg_table_dma, ioa_cfg->cfg_table_size,
7675 IPR_IOADL_FLAGS_READ_LAST);
7676
7677 ipr_cmd->job_step = ipr_init_res_table;
7678
7679 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout, IPR_INTERNAL_TIMEOUT);
7680
7681 LEAVE;
7682 return IPR_RC_JOB_RETURN;
7683}
7684
7685static int ipr_ioa_service_action_failed(struct ipr_cmnd *ipr_cmd)
7686{
7687 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
7688
7689 if (ioasc == IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT)
7690 return IPR_RC_JOB_CONTINUE;
7691
7692 return ipr_reset_cmd_failed(ipr_cmd);
7693}
7694
7695static void ipr_build_ioa_service_action(struct ipr_cmnd *ipr_cmd,
7696 __be32 res_handle, u8 sa_code)
7697{
7698 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
7699
7700 ioarcb->res_handle = res_handle;
7701 ioarcb->cmd_pkt.cdb[0] = IPR_IOA_SERVICE_ACTION;
7702 ioarcb->cmd_pkt.cdb[1] = sa_code;
7703 ioarcb->cmd_pkt.request_type = IPR_RQTYPE_IOACMD;
7704}
7705
7706
7707
7708
7709
7710
7711
7712
7713static int ipr_ioafp_set_caching_parameters(struct ipr_cmnd *ipr_cmd)
7714{
7715 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
7716 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7717 struct ipr_inquiry_pageC4 *pageC4 = &ioa_cfg->vpd_cbs->pageC4_data;
7718
7719 ENTER;
7720
7721 ipr_cmd->job_step = ipr_ioafp_query_ioa_cfg;
7722
7723 if (pageC4->cache_cap[0] & IPR_CAP_SYNC_CACHE) {
7724 ipr_build_ioa_service_action(ipr_cmd,
7725 cpu_to_be32(IPR_IOA_RES_HANDLE),
7726 IPR_IOA_SA_CHANGE_CACHE_PARAMS);
7727
7728 ioarcb->cmd_pkt.cdb[2] = 0x40;
7729
7730 ipr_cmd->job_step_failed = ipr_ioa_service_action_failed;
7731 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout,
7732 IPR_SET_SUP_DEVICE_TIMEOUT);
7733
7734 LEAVE;
7735 return IPR_RC_JOB_RETURN;
7736 }
7737
7738 LEAVE;
7739 return IPR_RC_JOB_CONTINUE;
7740}
7741
7742
7743
7744
7745
7746
7747
7748
7749
7750
7751static void ipr_ioafp_inquiry(struct ipr_cmnd *ipr_cmd, u8 flags, u8 page,
7752 dma_addr_t dma_addr, u8 xfer_len)
7753{
7754 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
7755
7756 ENTER;
7757 ioarcb->cmd_pkt.request_type = IPR_RQTYPE_SCSICDB;
7758 ioarcb->res_handle = cpu_to_be32(IPR_IOA_RES_HANDLE);
7759
7760 ioarcb->cmd_pkt.cdb[0] = INQUIRY;
7761 ioarcb->cmd_pkt.cdb[1] = flags;
7762 ioarcb->cmd_pkt.cdb[2] = page;
7763 ioarcb->cmd_pkt.cdb[4] = xfer_len;
7764
7765 ipr_init_ioadl(ipr_cmd, dma_addr, xfer_len, IPR_IOADL_FLAGS_READ_LAST);
7766
7767 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout, IPR_INTERNAL_TIMEOUT);
7768 LEAVE;
7769}
7770
7771
7772
7773
7774
7775
7776
7777
7778
7779
7780
7781static int ipr_inquiry_page_supported(struct ipr_inquiry_page0 *page0, u8 page)
7782{
7783 int i;
7784
7785 for (i = 0; i < min_t(u8, page0->len, IPR_INQUIRY_PAGE0_ENTRIES); i++)
7786 if (page0->page[i] == page)
7787 return 1;
7788
7789 return 0;
7790}
7791
7792
7793
7794
7795
7796
7797
7798
7799
7800
7801
7802static int ipr_ioafp_pageC4_inquiry(struct ipr_cmnd *ipr_cmd)
7803{
7804 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7805 struct ipr_inquiry_page0 *page0 = &ioa_cfg->vpd_cbs->page0_data;
7806 struct ipr_inquiry_pageC4 *pageC4 = &ioa_cfg->vpd_cbs->pageC4_data;
7807
7808 ENTER;
7809 ipr_cmd->job_step = ipr_ioafp_set_caching_parameters;
7810 memset(pageC4, 0, sizeof(*pageC4));
7811
7812 if (ipr_inquiry_page_supported(page0, 0xC4)) {
7813 ipr_ioafp_inquiry(ipr_cmd, 1, 0xC4,
7814 (ioa_cfg->vpd_cbs_dma
7815 + offsetof(struct ipr_misc_cbs,
7816 pageC4_data)),
7817 sizeof(struct ipr_inquiry_pageC4));
7818 return IPR_RC_JOB_RETURN;
7819 }
7820
7821 LEAVE;
7822 return IPR_RC_JOB_CONTINUE;
7823}
7824
7825
7826
7827
7828
7829
7830
7831
7832
7833
7834
7835static int ipr_ioafp_cap_inquiry(struct ipr_cmnd *ipr_cmd)
7836{
7837 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7838 struct ipr_inquiry_page0 *page0 = &ioa_cfg->vpd_cbs->page0_data;
7839 struct ipr_inquiry_cap *cap = &ioa_cfg->vpd_cbs->cap;
7840
7841 ENTER;
7842 ipr_cmd->job_step = ipr_ioafp_pageC4_inquiry;
7843 memset(cap, 0, sizeof(*cap));
7844
7845 if (ipr_inquiry_page_supported(page0, 0xD0)) {
7846 ipr_ioafp_inquiry(ipr_cmd, 1, 0xD0,
7847 ioa_cfg->vpd_cbs_dma + offsetof(struct ipr_misc_cbs, cap),
7848 sizeof(struct ipr_inquiry_cap));
7849 return IPR_RC_JOB_RETURN;
7850 }
7851
7852 LEAVE;
7853 return IPR_RC_JOB_CONTINUE;
7854}
7855
7856
7857
7858
7859
7860
7861
7862
7863
7864
7865
7866static int ipr_ioafp_page3_inquiry(struct ipr_cmnd *ipr_cmd)
7867{
7868 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7869
7870 ENTER;
7871
7872 ipr_cmd->job_step = ipr_ioafp_cap_inquiry;
7873
7874 ipr_ioafp_inquiry(ipr_cmd, 1, 3,
7875 ioa_cfg->vpd_cbs_dma + offsetof(struct ipr_misc_cbs, page3_data),
7876 sizeof(struct ipr_inquiry_page3));
7877
7878 LEAVE;
7879 return IPR_RC_JOB_RETURN;
7880}
7881
7882
7883
7884
7885
7886
7887
7888
7889
7890
7891
7892static int ipr_ioafp_page0_inquiry(struct ipr_cmnd *ipr_cmd)
7893{
7894 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7895 char type[5];
7896
7897 ENTER;
7898
7899
7900 memcpy(type, ioa_cfg->vpd_cbs->ioa_vpd.std_inq_data.vpids.product_id, 4);
7901 type[4] = '\0';
7902 ioa_cfg->type = simple_strtoul((char *)type, NULL, 16);
7903
7904 if (ipr_invalid_adapter(ioa_cfg)) {
7905 dev_err(&ioa_cfg->pdev->dev,
7906 "Adapter not supported in this hardware configuration.\n");
7907
7908 if (!ipr_testmode) {
7909 ioa_cfg->reset_retries += IPR_NUM_RESET_RELOAD_RETRIES;
7910 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
7911 list_add_tail(&ipr_cmd->queue,
7912 &ioa_cfg->hrrq->hrrq_free_q);
7913 return IPR_RC_JOB_RETURN;
7914 }
7915 }
7916
7917 ipr_cmd->job_step = ipr_ioafp_page3_inquiry;
7918
7919 ipr_ioafp_inquiry(ipr_cmd, 1, 0,
7920 ioa_cfg->vpd_cbs_dma + offsetof(struct ipr_misc_cbs, page0_data),
7921 sizeof(struct ipr_inquiry_page0));
7922
7923 LEAVE;
7924 return IPR_RC_JOB_RETURN;
7925}
7926
7927
7928
7929
7930
7931
7932
7933
7934
7935
7936static int ipr_ioafp_std_inquiry(struct ipr_cmnd *ipr_cmd)
7937{
7938 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7939
7940 ENTER;
7941 ipr_cmd->job_step = ipr_ioafp_page0_inquiry;
7942
7943 ipr_ioafp_inquiry(ipr_cmd, 0, 0,
7944 ioa_cfg->vpd_cbs_dma + offsetof(struct ipr_misc_cbs, ioa_vpd),
7945 sizeof(struct ipr_ioa_vpd));
7946
7947 LEAVE;
7948 return IPR_RC_JOB_RETURN;
7949}
7950
7951
7952
7953
7954
7955
7956
7957
7958
7959
7960
7961static int ipr_ioafp_identify_hrrq(struct ipr_cmnd *ipr_cmd)
7962{
7963 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7964 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
7965 struct ipr_hrr_queue *hrrq;
7966
7967 ENTER;
7968 ipr_cmd->job_step = ipr_ioafp_std_inquiry;
7969 dev_info(&ioa_cfg->pdev->dev, "Starting IOA initialization sequence.\n");
7970
7971 if (ioa_cfg->identify_hrrq_index < ioa_cfg->hrrq_num) {
7972 hrrq = &ioa_cfg->hrrq[ioa_cfg->identify_hrrq_index];
7973
7974 ioarcb->cmd_pkt.cdb[0] = IPR_ID_HOST_RR_Q;
7975 ioarcb->res_handle = cpu_to_be32(IPR_IOA_RES_HANDLE);
7976
7977 ioarcb->cmd_pkt.request_type = IPR_RQTYPE_IOACMD;
7978 if (ioa_cfg->sis64)
7979 ioarcb->cmd_pkt.cdb[1] = 0x1;
7980
7981 if (ioa_cfg->nvectors == 1)
7982 ioarcb->cmd_pkt.cdb[1] &= ~IPR_ID_HRRQ_SELE_ENABLE;
7983 else
7984 ioarcb->cmd_pkt.cdb[1] |= IPR_ID_HRRQ_SELE_ENABLE;
7985
7986 ioarcb->cmd_pkt.cdb[2] =
7987 ((u64) hrrq->host_rrq_dma >> 24) & 0xff;
7988 ioarcb->cmd_pkt.cdb[3] =
7989 ((u64) hrrq->host_rrq_dma >> 16) & 0xff;
7990 ioarcb->cmd_pkt.cdb[4] =
7991 ((u64) hrrq->host_rrq_dma >> 8) & 0xff;
7992 ioarcb->cmd_pkt.cdb[5] =
7993 ((u64) hrrq->host_rrq_dma) & 0xff;
7994 ioarcb->cmd_pkt.cdb[7] =
7995 ((sizeof(u32) * hrrq->size) >> 8) & 0xff;
7996 ioarcb->cmd_pkt.cdb[8] =
7997 (sizeof(u32) * hrrq->size) & 0xff;
7998
7999 if (ioarcb->cmd_pkt.cdb[1] & IPR_ID_HRRQ_SELE_ENABLE)
8000 ioarcb->cmd_pkt.cdb[9] =
8001 ioa_cfg->identify_hrrq_index;
8002
8003 if (ioa_cfg->sis64) {
8004 ioarcb->cmd_pkt.cdb[10] =
8005 ((u64) hrrq->host_rrq_dma >> 56) & 0xff;
8006 ioarcb->cmd_pkt.cdb[11] =
8007 ((u64) hrrq->host_rrq_dma >> 48) & 0xff;
8008 ioarcb->cmd_pkt.cdb[12] =
8009 ((u64) hrrq->host_rrq_dma >> 40) & 0xff;
8010 ioarcb->cmd_pkt.cdb[13] =
8011 ((u64) hrrq->host_rrq_dma >> 32) & 0xff;
8012 }
8013
8014 if (ioarcb->cmd_pkt.cdb[1] & IPR_ID_HRRQ_SELE_ENABLE)
8015 ioarcb->cmd_pkt.cdb[14] =
8016 ioa_cfg->identify_hrrq_index;
8017
8018 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout,
8019 IPR_INTERNAL_TIMEOUT);
8020
8021 if (++ioa_cfg->identify_hrrq_index < ioa_cfg->hrrq_num)
8022 ipr_cmd->job_step = ipr_ioafp_identify_hrrq;
8023
8024 LEAVE;
8025 return IPR_RC_JOB_RETURN;
8026 }
8027
8028 LEAVE;
8029 return IPR_RC_JOB_CONTINUE;
8030}
8031
8032
8033
8034
8035
8036
8037
8038
8039
8040
8041
8042
8043
8044
8045static void ipr_reset_timer_done(struct ipr_cmnd *ipr_cmd)
8046{
8047 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8048 unsigned long lock_flags = 0;
8049
8050 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
8051
8052 if (ioa_cfg->reset_cmd == ipr_cmd) {
8053 list_del(&ipr_cmd->queue);
8054 ipr_cmd->done(ipr_cmd);
8055 }
8056
8057 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
8058}
8059
8060
8061
8062
8063
8064
8065
8066
8067
8068
8069
8070
8071
8072
8073
8074static void ipr_reset_start_timer(struct ipr_cmnd *ipr_cmd,
8075 unsigned long timeout)
8076{
8077
8078 ENTER;
8079 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_pending_q);
8080 ipr_cmd->done = ipr_reset_ioa_job;
8081
8082 ipr_cmd->timer.data = (unsigned long) ipr_cmd;
8083 ipr_cmd->timer.expires = jiffies + timeout;
8084 ipr_cmd->timer.function = (void (*)(unsigned long))ipr_reset_timer_done;
8085 add_timer(&ipr_cmd->timer);
8086}
8087
8088
8089
8090
8091
8092
8093
8094
8095static void ipr_init_ioa_mem(struct ipr_ioa_cfg *ioa_cfg)
8096{
8097 struct ipr_hrr_queue *hrrq;
8098
8099 for_each_hrrq(hrrq, ioa_cfg) {
8100 spin_lock(&hrrq->_lock);
8101 memset(hrrq->host_rrq, 0, sizeof(u32) * hrrq->size);
8102
8103
8104 hrrq->hrrq_start = hrrq->host_rrq;
8105 hrrq->hrrq_end = &hrrq->host_rrq[hrrq->size - 1];
8106 hrrq->hrrq_curr = hrrq->hrrq_start;
8107 hrrq->toggle_bit = 1;
8108 spin_unlock(&hrrq->_lock);
8109 }
8110 wmb();
8111
8112 ioa_cfg->identify_hrrq_index = 0;
8113 if (ioa_cfg->hrrq_num == 1)
8114 atomic_set(&ioa_cfg->hrrq_index, 0);
8115 else
8116 atomic_set(&ioa_cfg->hrrq_index, 1);
8117
8118
8119 memset(ioa_cfg->u.cfg_table, 0, ioa_cfg->cfg_table_size);
8120}
8121
8122
8123
8124
8125
8126
8127
8128
8129static int ipr_reset_next_stage(struct ipr_cmnd *ipr_cmd)
8130{
8131 unsigned long stage, stage_time;
8132 u32 feedback;
8133 volatile u32 int_reg;
8134 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8135 u64 maskval = 0;
8136
8137 feedback = readl(ioa_cfg->regs.init_feedback_reg);
8138 stage = feedback & IPR_IPL_INIT_STAGE_MASK;
8139 stage_time = feedback & IPR_IPL_INIT_STAGE_TIME_MASK;
8140
8141 ipr_dbg("IPL stage = 0x%lx, IPL stage time = %ld\n", stage, stage_time);
8142
8143
8144 if (stage_time == 0)
8145 stage_time = IPR_IPL_INIT_DEFAULT_STAGE_TIME;
8146 else if (stage_time < IPR_IPL_INIT_MIN_STAGE_TIME)
8147 stage_time = IPR_IPL_INIT_MIN_STAGE_TIME;
8148 else if (stage_time > IPR_LONG_OPERATIONAL_TIMEOUT)
8149 stage_time = IPR_LONG_OPERATIONAL_TIMEOUT;
8150
8151 if (stage == IPR_IPL_INIT_STAGE_UNKNOWN) {
8152 writel(IPR_PCII_IPL_STAGE_CHANGE, ioa_cfg->regs.set_interrupt_mask_reg);
8153 int_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg);
8154 stage_time = ioa_cfg->transop_timeout;
8155 ipr_cmd->job_step = ipr_ioafp_identify_hrrq;
8156 } else if (stage == IPR_IPL_INIT_STAGE_TRANSOP) {
8157 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg32);
8158 if (int_reg & IPR_PCII_IOA_TRANS_TO_OPER) {
8159 ipr_cmd->job_step = ipr_ioafp_identify_hrrq;
8160 maskval = IPR_PCII_IPL_STAGE_CHANGE;
8161 maskval = (maskval << 32) | IPR_PCII_IOA_TRANS_TO_OPER;
8162 writeq(maskval, ioa_cfg->regs.set_interrupt_mask_reg);
8163 int_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg);
8164 return IPR_RC_JOB_CONTINUE;
8165 }
8166 }
8167
8168 ipr_cmd->timer.data = (unsigned long) ipr_cmd;
8169 ipr_cmd->timer.expires = jiffies + stage_time * HZ;
8170 ipr_cmd->timer.function = (void (*)(unsigned long))ipr_oper_timeout;
8171 ipr_cmd->done = ipr_reset_ioa_job;
8172 add_timer(&ipr_cmd->timer);
8173
8174 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_pending_q);
8175
8176 return IPR_RC_JOB_RETURN;
8177}
8178
8179
8180
8181
8182
8183
8184
8185
8186
8187
8188
8189static int ipr_reset_enable_ioa(struct ipr_cmnd *ipr_cmd)
8190{
8191 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8192 volatile u32 int_reg;
8193 volatile u64 maskval;
8194 int i;
8195
8196 ENTER;
8197 ipr_cmd->job_step = ipr_ioafp_identify_hrrq;
8198 ipr_init_ioa_mem(ioa_cfg);
8199
8200 for (i = 0; i < ioa_cfg->hrrq_num; i++) {
8201 spin_lock(&ioa_cfg->hrrq[i]._lock);
8202 ioa_cfg->hrrq[i].allow_interrupts = 1;
8203 spin_unlock(&ioa_cfg->hrrq[i]._lock);
8204 }
8205 wmb();
8206 if (ioa_cfg->sis64) {
8207
8208 writel(IPR_ENDIAN_SWAP_KEY, ioa_cfg->regs.endian_swap_reg);
8209 int_reg = readl(ioa_cfg->regs.endian_swap_reg);
8210 }
8211
8212 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg32);
8213
8214 if (int_reg & IPR_PCII_IOA_TRANS_TO_OPER) {
8215 writel((IPR_PCII_ERROR_INTERRUPTS | IPR_PCII_HRRQ_UPDATED),
8216 ioa_cfg->regs.clr_interrupt_mask_reg32);
8217 int_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg);
8218 return IPR_RC_JOB_CONTINUE;
8219 }
8220
8221
8222 writel(ioa_cfg->doorbell, ioa_cfg->regs.set_uproc_interrupt_reg32);
8223
8224 if (ioa_cfg->sis64) {
8225 maskval = IPR_PCII_IPL_STAGE_CHANGE;
8226 maskval = (maskval << 32) | IPR_PCII_OPER_INTERRUPTS;
8227 writeq(maskval, ioa_cfg->regs.clr_interrupt_mask_reg);
8228 } else
8229 writel(IPR_PCII_OPER_INTERRUPTS, ioa_cfg->regs.clr_interrupt_mask_reg32);
8230
8231 int_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg);
8232
8233 dev_info(&ioa_cfg->pdev->dev, "Initializing IOA.\n");
8234
8235 if (ioa_cfg->sis64) {
8236 ipr_cmd->job_step = ipr_reset_next_stage;
8237 return IPR_RC_JOB_CONTINUE;
8238 }
8239
8240 ipr_cmd->timer.data = (unsigned long) ipr_cmd;
8241 ipr_cmd->timer.expires = jiffies + (ioa_cfg->transop_timeout * HZ);
8242 ipr_cmd->timer.function = (void (*)(unsigned long))ipr_oper_timeout;
8243 ipr_cmd->done = ipr_reset_ioa_job;
8244 add_timer(&ipr_cmd->timer);
8245 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_pending_q);
8246
8247 LEAVE;
8248 return IPR_RC_JOB_RETURN;
8249}
8250
8251
8252
8253
8254
8255
8256
8257
8258
8259
8260
8261static int ipr_reset_wait_for_dump(struct ipr_cmnd *ipr_cmd)
8262{
8263 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8264
8265 if (ioa_cfg->sdt_state == GET_DUMP)
8266 ioa_cfg->sdt_state = WAIT_FOR_DUMP;
8267 else if (ioa_cfg->sdt_state == READ_DUMP)
8268 ioa_cfg->sdt_state = ABORT_DUMP;
8269
8270 ioa_cfg->dump_timeout = 1;
8271 ipr_cmd->job_step = ipr_reset_alert;
8272
8273 return IPR_RC_JOB_CONTINUE;
8274}
8275
8276
8277
8278
8279
8280
8281
8282
8283
8284
8285
8286static void ipr_unit_check_no_data(struct ipr_ioa_cfg *ioa_cfg)
8287{
8288 ioa_cfg->errors_logged++;
8289 dev_err(&ioa_cfg->pdev->dev, "IOA unit check with no data\n");
8290}
8291
8292
8293
8294
8295
8296
8297
8298
8299
8300
8301
8302static void ipr_get_unit_check_buffer(struct ipr_ioa_cfg *ioa_cfg)
8303{
8304 unsigned long mailbox;
8305 struct ipr_hostrcb *hostrcb;
8306 struct ipr_uc_sdt sdt;
8307 int rc, length;
8308 u32 ioasc;
8309
8310 mailbox = readl(ioa_cfg->ioa_mailbox);
8311
8312 if (!ioa_cfg->sis64 && !ipr_sdt_is_fmt2(mailbox)) {
8313 ipr_unit_check_no_data(ioa_cfg);
8314 return;
8315 }
8316
8317 memset(&sdt, 0, sizeof(struct ipr_uc_sdt));
8318 rc = ipr_get_ldump_data_section(ioa_cfg, mailbox, (__be32 *) &sdt,
8319 (sizeof(struct ipr_uc_sdt)) / sizeof(__be32));
8320
8321 if (rc || !(sdt.entry[0].flags & IPR_SDT_VALID_ENTRY) ||
8322 ((be32_to_cpu(sdt.hdr.state) != IPR_FMT3_SDT_READY_TO_USE) &&
8323 (be32_to_cpu(sdt.hdr.state) != IPR_FMT2_SDT_READY_TO_USE))) {
8324 ipr_unit_check_no_data(ioa_cfg);
8325 return;
8326 }
8327
8328
8329 if (be32_to_cpu(sdt.hdr.state) == IPR_FMT3_SDT_READY_TO_USE)
8330 length = be32_to_cpu(sdt.entry[0].end_token);
8331 else
8332 length = (be32_to_cpu(sdt.entry[0].end_token) -
8333 be32_to_cpu(sdt.entry[0].start_token)) &
8334 IPR_FMT2_MBX_ADDR_MASK;
8335
8336 hostrcb = list_entry(ioa_cfg->hostrcb_free_q.next,
8337 struct ipr_hostrcb, queue);
8338 list_del(&hostrcb->queue);
8339 memset(&hostrcb->hcam, 0, sizeof(hostrcb->hcam));
8340
8341 rc = ipr_get_ldump_data_section(ioa_cfg,
8342 be32_to_cpu(sdt.entry[0].start_token),
8343 (__be32 *)&hostrcb->hcam,
8344 min(length, (int)sizeof(hostrcb->hcam)) / sizeof(__be32));
8345
8346 if (!rc) {
8347 ipr_handle_log_data(ioa_cfg, hostrcb);
8348 ioasc = be32_to_cpu(hostrcb->hcam.u.error.fd_ioasc);
8349 if (ioasc == IPR_IOASC_NR_IOA_RESET_REQUIRED &&
8350 ioa_cfg->sdt_state == GET_DUMP)
8351 ioa_cfg->sdt_state = WAIT_FOR_DUMP;
8352 } else
8353 ipr_unit_check_no_data(ioa_cfg);
8354
8355 list_add_tail(&hostrcb->queue, &ioa_cfg->hostrcb_free_q);
8356}
8357
8358
8359
8360
8361
8362
8363
8364
8365
8366
8367static int ipr_reset_get_unit_check_job(struct ipr_cmnd *ipr_cmd)
8368{
8369 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8370
8371 ENTER;
8372 ioa_cfg->ioa_unit_checked = 0;
8373 ipr_get_unit_check_buffer(ioa_cfg);
8374 ipr_cmd->job_step = ipr_reset_alert;
8375 ipr_reset_start_timer(ipr_cmd, 0);
8376
8377 LEAVE;
8378 return IPR_RC_JOB_RETURN;
8379}
8380
8381static int ipr_dump_mailbox_wait(struct ipr_cmnd *ipr_cmd)
8382{
8383 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8384
8385 ENTER;
8386
8387 if (ioa_cfg->sdt_state != GET_DUMP)
8388 return IPR_RC_JOB_RETURN;
8389
8390 if (!ioa_cfg->sis64 || !ipr_cmd->u.time_left ||
8391 (readl(ioa_cfg->regs.sense_interrupt_reg) &
8392 IPR_PCII_MAILBOX_STABLE)) {
8393
8394 if (!ipr_cmd->u.time_left)
8395 dev_err(&ioa_cfg->pdev->dev,
8396 "Timed out waiting for Mailbox register.\n");
8397
8398 ioa_cfg->sdt_state = READ_DUMP;
8399 ioa_cfg->dump_timeout = 0;
8400 if (ioa_cfg->sis64)
8401 ipr_reset_start_timer(ipr_cmd, IPR_SIS64_DUMP_TIMEOUT);
8402 else
8403 ipr_reset_start_timer(ipr_cmd, IPR_SIS32_DUMP_TIMEOUT);
8404 ipr_cmd->job_step = ipr_reset_wait_for_dump;
8405 schedule_work(&ioa_cfg->work_q);
8406
8407 } else {
8408 ipr_cmd->u.time_left -= IPR_CHECK_FOR_RESET_TIMEOUT;
8409 ipr_reset_start_timer(ipr_cmd,
8410 IPR_CHECK_FOR_RESET_TIMEOUT);
8411 }
8412
8413 LEAVE;
8414 return IPR_RC_JOB_RETURN;
8415}
8416
8417
8418
8419
8420
8421
8422
8423
8424
8425
8426
8427
8428static int ipr_reset_restore_cfg_space(struct ipr_cmnd *ipr_cmd)
8429{
8430 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8431 u32 int_reg;
8432
8433 ENTER;
8434 ioa_cfg->pdev->state_saved = true;
8435 pci_restore_state(ioa_cfg->pdev);
8436
8437 if (ipr_set_pcix_cmd_reg(ioa_cfg)) {
8438 ipr_cmd->s.ioasa.hdr.ioasc = cpu_to_be32(IPR_IOASC_PCI_ACCESS_ERROR);
8439 return IPR_RC_JOB_CONTINUE;
8440 }
8441
8442 ipr_fail_all_ops(ioa_cfg);
8443
8444 if (ioa_cfg->sis64) {
8445
8446 writel(IPR_ENDIAN_SWAP_KEY, ioa_cfg->regs.endian_swap_reg);
8447 int_reg = readl(ioa_cfg->regs.endian_swap_reg);
8448 }
8449
8450 if (ioa_cfg->ioa_unit_checked) {
8451 if (ioa_cfg->sis64) {
8452 ipr_cmd->job_step = ipr_reset_get_unit_check_job;
8453 ipr_reset_start_timer(ipr_cmd, IPR_DUMP_DELAY_TIMEOUT);
8454 return IPR_RC_JOB_RETURN;
8455 } else {
8456 ioa_cfg->ioa_unit_checked = 0;
8457 ipr_get_unit_check_buffer(ioa_cfg);
8458 ipr_cmd->job_step = ipr_reset_alert;
8459 ipr_reset_start_timer(ipr_cmd, 0);
8460 return IPR_RC_JOB_RETURN;
8461 }
8462 }
8463
8464 if (ioa_cfg->in_ioa_bringdown) {
8465 ipr_cmd->job_step = ipr_ioa_bringdown_done;
8466 } else if (ioa_cfg->sdt_state == GET_DUMP) {
8467 ipr_cmd->job_step = ipr_dump_mailbox_wait;
8468 ipr_cmd->u.time_left = IPR_WAIT_FOR_MAILBOX;
8469 } else {
8470 ipr_cmd->job_step = ipr_reset_enable_ioa;
8471 }
8472
8473 LEAVE;
8474 return IPR_RC_JOB_CONTINUE;
8475}
8476
8477
8478
8479
8480
8481
8482
8483
8484
8485
8486static int ipr_reset_bist_done(struct ipr_cmnd *ipr_cmd)
8487{
8488 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8489
8490 ENTER;
8491 if (ioa_cfg->cfg_locked)
8492 pci_cfg_access_unlock(ioa_cfg->pdev);
8493 ioa_cfg->cfg_locked = 0;
8494 ipr_cmd->job_step = ipr_reset_restore_cfg_space;
8495 LEAVE;
8496 return IPR_RC_JOB_CONTINUE;
8497}
8498
8499
8500
8501
8502
8503
8504
8505
8506
8507
8508static int ipr_reset_start_bist(struct ipr_cmnd *ipr_cmd)
8509{
8510 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8511 int rc = PCIBIOS_SUCCESSFUL;
8512
8513 ENTER;
8514 if (ioa_cfg->ipr_chip->bist_method == IPR_MMIO)
8515 writel(IPR_UPROCI_SIS64_START_BIST,
8516 ioa_cfg->regs.set_uproc_interrupt_reg32);
8517 else
8518 rc = pci_write_config_byte(ioa_cfg->pdev, PCI_BIST, PCI_BIST_START);
8519
8520 if (rc == PCIBIOS_SUCCESSFUL) {
8521 ipr_cmd->job_step = ipr_reset_bist_done;
8522 ipr_reset_start_timer(ipr_cmd, IPR_WAIT_FOR_BIST_TIMEOUT);
8523 rc = IPR_RC_JOB_RETURN;
8524 } else {
8525 if (ioa_cfg->cfg_locked)
8526 pci_cfg_access_unlock(ipr_cmd->ioa_cfg->pdev);
8527 ioa_cfg->cfg_locked = 0;
8528 ipr_cmd->s.ioasa.hdr.ioasc = cpu_to_be32(IPR_IOASC_PCI_ACCESS_ERROR);
8529 rc = IPR_RC_JOB_CONTINUE;
8530 }
8531
8532 LEAVE;
8533 return rc;
8534}
8535
8536
8537
8538
8539
8540
8541
8542
8543
8544
8545static int ipr_reset_slot_reset_done(struct ipr_cmnd *ipr_cmd)
8546{
8547 ENTER;
8548 ipr_cmd->job_step = ipr_reset_bist_done;
8549 ipr_reset_start_timer(ipr_cmd, IPR_WAIT_FOR_BIST_TIMEOUT);
8550 LEAVE;
8551 return IPR_RC_JOB_RETURN;
8552}
8553
8554
8555
8556
8557
8558
8559
8560
8561static void ipr_reset_reset_work(struct work_struct *work)
8562{
8563 struct ipr_cmnd *ipr_cmd = container_of(work, struct ipr_cmnd, work);
8564 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8565 struct pci_dev *pdev = ioa_cfg->pdev;
8566 unsigned long lock_flags = 0;
8567
8568 ENTER;
8569 pci_set_pcie_reset_state(pdev, pcie_warm_reset);
8570 msleep(jiffies_to_msecs(IPR_PCI_RESET_TIMEOUT));
8571 pci_set_pcie_reset_state(pdev, pcie_deassert_reset);
8572
8573 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
8574 if (ioa_cfg->reset_cmd == ipr_cmd)
8575 ipr_reset_ioa_job(ipr_cmd);
8576 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
8577 LEAVE;
8578}
8579
8580
8581
8582
8583
8584
8585
8586
8587
8588
8589static int ipr_reset_slot_reset(struct ipr_cmnd *ipr_cmd)
8590{
8591 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8592
8593 ENTER;
8594 INIT_WORK(&ipr_cmd->work, ipr_reset_reset_work);
8595 queue_work(ioa_cfg->reset_work_q, &ipr_cmd->work);
8596 ipr_cmd->job_step = ipr_reset_slot_reset_done;
8597 LEAVE;
8598 return IPR_RC_JOB_RETURN;
8599}
8600
8601
8602
8603
8604
8605
8606
8607
8608
8609
8610static int ipr_reset_block_config_access_wait(struct ipr_cmnd *ipr_cmd)
8611{
8612 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8613 int rc = IPR_RC_JOB_CONTINUE;
8614
8615 if (pci_cfg_access_trylock(ioa_cfg->pdev)) {
8616 ioa_cfg->cfg_locked = 1;
8617 ipr_cmd->job_step = ioa_cfg->reset;
8618 } else {
8619 if (ipr_cmd->u.time_left) {
8620 rc = IPR_RC_JOB_RETURN;
8621 ipr_cmd->u.time_left -= IPR_CHECK_FOR_RESET_TIMEOUT;
8622 ipr_reset_start_timer(ipr_cmd,
8623 IPR_CHECK_FOR_RESET_TIMEOUT);
8624 } else {
8625 ipr_cmd->job_step = ioa_cfg->reset;
8626 dev_err(&ioa_cfg->pdev->dev,
8627 "Timed out waiting to lock config access. Resetting anyway.\n");
8628 }
8629 }
8630
8631 return rc;
8632}
8633
8634
8635
8636
8637
8638
8639
8640
8641
8642
8643static int ipr_reset_block_config_access(struct ipr_cmnd *ipr_cmd)
8644{
8645 ipr_cmd->ioa_cfg->cfg_locked = 0;
8646 ipr_cmd->job_step = ipr_reset_block_config_access_wait;
8647 ipr_cmd->u.time_left = IPR_WAIT_FOR_RESET_TIMEOUT;
8648 return IPR_RC_JOB_CONTINUE;
8649}
8650
8651
8652
8653
8654
8655
8656
8657
8658static int ipr_reset_allowed(struct ipr_ioa_cfg *ioa_cfg)
8659{
8660 volatile u32 temp_reg;
8661
8662 temp_reg = readl(ioa_cfg->regs.sense_interrupt_reg);
8663 return ((temp_reg & IPR_PCII_CRITICAL_OPERATION) == 0);
8664}
8665
8666
8667
8668
8669
8670
8671
8672
8673
8674
8675
8676
8677
8678
8679
8680
8681static int ipr_reset_wait_to_start_bist(struct ipr_cmnd *ipr_cmd)
8682{
8683 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8684 int rc = IPR_RC_JOB_RETURN;
8685
8686 if (!ipr_reset_allowed(ioa_cfg) && ipr_cmd->u.time_left) {
8687 ipr_cmd->u.time_left -= IPR_CHECK_FOR_RESET_TIMEOUT;
8688 ipr_reset_start_timer(ipr_cmd, IPR_CHECK_FOR_RESET_TIMEOUT);
8689 } else {
8690 ipr_cmd->job_step = ipr_reset_block_config_access;
8691 rc = IPR_RC_JOB_CONTINUE;
8692 }
8693
8694 return rc;
8695}
8696
8697
8698
8699
8700
8701
8702
8703
8704
8705
8706
8707
8708
8709static int ipr_reset_alert(struct ipr_cmnd *ipr_cmd)
8710{
8711 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8712 u16 cmd_reg;
8713 int rc;
8714
8715 ENTER;
8716 rc = pci_read_config_word(ioa_cfg->pdev, PCI_COMMAND, &cmd_reg);
8717
8718 if ((rc == PCIBIOS_SUCCESSFUL) && (cmd_reg & PCI_COMMAND_MEMORY)) {
8719 ipr_mask_and_clear_interrupts(ioa_cfg, ~0);
8720 writel(IPR_UPROCI_RESET_ALERT, ioa_cfg->regs.set_uproc_interrupt_reg32);
8721 ipr_cmd->job_step = ipr_reset_wait_to_start_bist;
8722 } else {
8723 ipr_cmd->job_step = ipr_reset_block_config_access;
8724 }
8725
8726 ipr_cmd->u.time_left = IPR_WAIT_FOR_RESET_TIMEOUT;
8727 ipr_reset_start_timer(ipr_cmd, IPR_CHECK_FOR_RESET_TIMEOUT);
8728
8729 LEAVE;
8730 return IPR_RC_JOB_RETURN;
8731}
8732
8733
8734
8735
8736
8737
8738
8739
8740
8741
8742static int ipr_reset_quiesce_done(struct ipr_cmnd *ipr_cmd)
8743{
8744 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8745
8746 ENTER;
8747 ipr_cmd->job_step = ipr_ioa_bringdown_done;
8748 ipr_mask_and_clear_interrupts(ioa_cfg, ~IPR_PCII_IOA_TRANS_TO_OPER);
8749 LEAVE;
8750 return IPR_RC_JOB_CONTINUE;
8751}
8752
8753
8754
8755
8756
8757
8758
8759
8760
8761
8762
8763static int ipr_reset_cancel_hcam_done(struct ipr_cmnd *ipr_cmd)
8764{
8765 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8766 struct ipr_cmnd *loop_cmd;
8767 struct ipr_hrr_queue *hrrq;
8768 int rc = IPR_RC_JOB_CONTINUE;
8769 int count = 0;
8770
8771 ENTER;
8772 ipr_cmd->job_step = ipr_reset_quiesce_done;
8773
8774 for_each_hrrq(hrrq, ioa_cfg) {
8775 spin_lock(&hrrq->_lock);
8776 list_for_each_entry(loop_cmd, &hrrq->hrrq_pending_q, queue) {
8777 count++;
8778 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
8779 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
8780 rc = IPR_RC_JOB_RETURN;
8781 break;
8782 }
8783 spin_unlock(&hrrq->_lock);
8784
8785 if (count)
8786 break;
8787 }
8788
8789 LEAVE;
8790 return rc;
8791}
8792
8793
8794
8795
8796
8797
8798
8799
8800
8801
8802static int ipr_reset_cancel_hcam(struct ipr_cmnd *ipr_cmd)
8803{
8804 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8805 int rc = IPR_RC_JOB_CONTINUE;
8806 struct ipr_cmd_pkt *cmd_pkt;
8807 struct ipr_cmnd *hcam_cmd;
8808 struct ipr_hrr_queue *hrrq = &ioa_cfg->hrrq[IPR_INIT_HRRQ];
8809
8810 ENTER;
8811 ipr_cmd->job_step = ipr_reset_cancel_hcam_done;
8812
8813 if (!hrrq->ioa_is_dead) {
8814 if (!list_empty(&ioa_cfg->hostrcb_pending_q)) {
8815 list_for_each_entry(hcam_cmd, &hrrq->hrrq_pending_q, queue) {
8816 if (hcam_cmd->ioarcb.cmd_pkt.cdb[0] != IPR_HOST_CONTROLLED_ASYNC)
8817 continue;
8818
8819 ipr_cmd->ioarcb.res_handle = cpu_to_be32(IPR_IOA_RES_HANDLE);
8820 ipr_cmd->ioarcb.cmd_pkt.request_type = IPR_RQTYPE_IOACMD;
8821 cmd_pkt = &ipr_cmd->ioarcb.cmd_pkt;
8822 cmd_pkt->request_type = IPR_RQTYPE_IOACMD;
8823 cmd_pkt->cdb[0] = IPR_CANCEL_REQUEST;
8824 cmd_pkt->cdb[1] = IPR_CANCEL_64BIT_IOARCB;
8825 cmd_pkt->cdb[10] = ((u64) hcam_cmd->dma_addr >> 56) & 0xff;
8826 cmd_pkt->cdb[11] = ((u64) hcam_cmd->dma_addr >> 48) & 0xff;
8827 cmd_pkt->cdb[12] = ((u64) hcam_cmd->dma_addr >> 40) & 0xff;
8828 cmd_pkt->cdb[13] = ((u64) hcam_cmd->dma_addr >> 32) & 0xff;
8829 cmd_pkt->cdb[2] = ((u64) hcam_cmd->dma_addr >> 24) & 0xff;
8830 cmd_pkt->cdb[3] = ((u64) hcam_cmd->dma_addr >> 16) & 0xff;
8831 cmd_pkt->cdb[4] = ((u64) hcam_cmd->dma_addr >> 8) & 0xff;
8832 cmd_pkt->cdb[5] = ((u64) hcam_cmd->dma_addr) & 0xff;
8833
8834 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout,
8835 IPR_CANCEL_TIMEOUT);
8836
8837 rc = IPR_RC_JOB_RETURN;
8838 ipr_cmd->job_step = ipr_reset_cancel_hcam;
8839 break;
8840 }
8841 }
8842 } else
8843 ipr_cmd->job_step = ipr_reset_alert;
8844
8845 LEAVE;
8846 return rc;
8847}
8848
8849
8850
8851
8852
8853
8854
8855
8856
8857
8858static int ipr_reset_ucode_download_done(struct ipr_cmnd *ipr_cmd)
8859{
8860 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8861 struct ipr_sglist *sglist = ioa_cfg->ucode_sglist;
8862
8863 dma_unmap_sg(&ioa_cfg->pdev->dev, sglist->scatterlist,
8864 sglist->num_sg, DMA_TO_DEVICE);
8865
8866 ipr_cmd->job_step = ipr_reset_alert;
8867 return IPR_RC_JOB_CONTINUE;
8868}
8869
8870
8871
8872
8873
8874
8875
8876
8877
8878
8879
8880static int ipr_reset_ucode_download(struct ipr_cmnd *ipr_cmd)
8881{
8882 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8883 struct ipr_sglist *sglist = ioa_cfg->ucode_sglist;
8884
8885 ENTER;
8886 ipr_cmd->job_step = ipr_reset_alert;
8887
8888 if (!sglist)
8889 return IPR_RC_JOB_CONTINUE;
8890
8891 ipr_cmd->ioarcb.res_handle = cpu_to_be32(IPR_IOA_RES_HANDLE);
8892 ipr_cmd->ioarcb.cmd_pkt.request_type = IPR_RQTYPE_SCSICDB;
8893 ipr_cmd->ioarcb.cmd_pkt.cdb[0] = WRITE_BUFFER;
8894 ipr_cmd->ioarcb.cmd_pkt.cdb[1] = IPR_WR_BUF_DOWNLOAD_AND_SAVE;
8895 ipr_cmd->ioarcb.cmd_pkt.cdb[6] = (sglist->buffer_len & 0xff0000) >> 16;
8896 ipr_cmd->ioarcb.cmd_pkt.cdb[7] = (sglist->buffer_len & 0x00ff00) >> 8;
8897 ipr_cmd->ioarcb.cmd_pkt.cdb[8] = sglist->buffer_len & 0x0000ff;
8898
8899 if (ioa_cfg->sis64)
8900 ipr_build_ucode_ioadl64(ipr_cmd, sglist);
8901 else
8902 ipr_build_ucode_ioadl(ipr_cmd, sglist);
8903 ipr_cmd->job_step = ipr_reset_ucode_download_done;
8904
8905 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout,
8906 IPR_WRITE_BUFFER_TIMEOUT);
8907
8908 LEAVE;
8909 return IPR_RC_JOB_RETURN;
8910}
8911
8912
8913
8914
8915
8916
8917
8918
8919
8920
8921
8922
8923static int ipr_reset_shutdown_ioa(struct ipr_cmnd *ipr_cmd)
8924{
8925 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8926 enum ipr_shutdown_type shutdown_type = ipr_cmd->u.shutdown_type;
8927 unsigned long timeout;
8928 int rc = IPR_RC_JOB_CONTINUE;
8929
8930 ENTER;
8931 if (shutdown_type == IPR_SHUTDOWN_QUIESCE)
8932 ipr_cmd->job_step = ipr_reset_cancel_hcam;
8933 else if (shutdown_type != IPR_SHUTDOWN_NONE &&
8934 !ioa_cfg->hrrq[IPR_INIT_HRRQ].ioa_is_dead) {
8935 ipr_cmd->ioarcb.res_handle = cpu_to_be32(IPR_IOA_RES_HANDLE);
8936 ipr_cmd->ioarcb.cmd_pkt.request_type = IPR_RQTYPE_IOACMD;
8937 ipr_cmd->ioarcb.cmd_pkt.cdb[0] = IPR_IOA_SHUTDOWN;
8938 ipr_cmd->ioarcb.cmd_pkt.cdb[1] = shutdown_type;
8939
8940 if (shutdown_type == IPR_SHUTDOWN_NORMAL)
8941 timeout = IPR_SHUTDOWN_TIMEOUT;
8942 else if (shutdown_type == IPR_SHUTDOWN_PREPARE_FOR_NORMAL)
8943 timeout = IPR_INTERNAL_TIMEOUT;
8944 else if (ioa_cfg->dual_raid && ipr_dual_ioa_raid)
8945 timeout = IPR_DUAL_IOA_ABBR_SHUTDOWN_TO;
8946 else
8947 timeout = IPR_ABBREV_SHUTDOWN_TIMEOUT;
8948
8949 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout, timeout);
8950
8951 rc = IPR_RC_JOB_RETURN;
8952 ipr_cmd->job_step = ipr_reset_ucode_download;
8953 } else
8954 ipr_cmd->job_step = ipr_reset_alert;
8955
8956 LEAVE;
8957 return rc;
8958}
8959
8960
8961
8962
8963
8964
8965
8966
8967
8968
8969static void ipr_reset_ioa_job(struct ipr_cmnd *ipr_cmd)
8970{
8971 u32 rc, ioasc;
8972 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8973
8974 do {
8975 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
8976
8977 if (ioa_cfg->reset_cmd != ipr_cmd) {
8978
8979
8980
8981
8982 list_add_tail(&ipr_cmd->queue,
8983 &ipr_cmd->hrrq->hrrq_free_q);
8984 return;
8985 }
8986
8987 if (IPR_IOASC_SENSE_KEY(ioasc)) {
8988 rc = ipr_cmd->job_step_failed(ipr_cmd);
8989 if (rc == IPR_RC_JOB_RETURN)
8990 return;
8991 }
8992
8993 ipr_reinit_ipr_cmnd(ipr_cmd);
8994 ipr_cmd->job_step_failed = ipr_reset_cmd_failed;
8995 rc = ipr_cmd->job_step(ipr_cmd);
8996 } while (rc == IPR_RC_JOB_CONTINUE);
8997}
8998
8999
9000
9001
9002
9003
9004
9005
9006
9007
9008
9009
9010
9011
9012
9013static void _ipr_initiate_ioa_reset(struct ipr_ioa_cfg *ioa_cfg,
9014 int (*job_step) (struct ipr_cmnd *),
9015 enum ipr_shutdown_type shutdown_type)
9016{
9017 struct ipr_cmnd *ipr_cmd;
9018 int i;
9019
9020 ioa_cfg->in_reset_reload = 1;
9021 for (i = 0; i < ioa_cfg->hrrq_num; i++) {
9022 spin_lock(&ioa_cfg->hrrq[i]._lock);
9023 ioa_cfg->hrrq[i].allow_cmds = 0;
9024 spin_unlock(&ioa_cfg->hrrq[i]._lock);
9025 }
9026 wmb();
9027 if (!ioa_cfg->hrrq[IPR_INIT_HRRQ].removing_ioa)
9028 scsi_block_requests(ioa_cfg->host);
9029
9030 ipr_cmd = ipr_get_free_ipr_cmnd(ioa_cfg);
9031 ioa_cfg->reset_cmd = ipr_cmd;
9032 ipr_cmd->job_step = job_step;
9033 ipr_cmd->u.shutdown_type = shutdown_type;
9034
9035 ipr_reset_ioa_job(ipr_cmd);
9036}
9037
9038
9039
9040
9041
9042
9043
9044
9045
9046
9047
9048
9049
9050static void ipr_initiate_ioa_reset(struct ipr_ioa_cfg *ioa_cfg,
9051 enum ipr_shutdown_type shutdown_type)
9052{
9053 int i;
9054
9055 if (ioa_cfg->hrrq[IPR_INIT_HRRQ].ioa_is_dead)
9056 return;
9057
9058 if (ioa_cfg->in_reset_reload) {
9059 if (ioa_cfg->sdt_state == GET_DUMP)
9060 ioa_cfg->sdt_state = WAIT_FOR_DUMP;
9061 else if (ioa_cfg->sdt_state == READ_DUMP)
9062 ioa_cfg->sdt_state = ABORT_DUMP;
9063 }
9064
9065 if (ioa_cfg->reset_retries++ >= IPR_NUM_RESET_RELOAD_RETRIES) {
9066 dev_err(&ioa_cfg->pdev->dev,
9067 "IOA taken offline - error recovery failed\n");
9068
9069 ioa_cfg->reset_retries = 0;
9070 for (i = 0; i < ioa_cfg->hrrq_num; i++) {
9071 spin_lock(&ioa_cfg->hrrq[i]._lock);
9072 ioa_cfg->hrrq[i].ioa_is_dead = 1;
9073 spin_unlock(&ioa_cfg->hrrq[i]._lock);
9074 }
9075 wmb();
9076
9077 if (ioa_cfg->in_ioa_bringdown) {
9078 ioa_cfg->reset_cmd = NULL;
9079 ioa_cfg->in_reset_reload = 0;
9080 ipr_fail_all_ops(ioa_cfg);
9081 wake_up_all(&ioa_cfg->reset_wait_q);
9082
9083 if (!ioa_cfg->hrrq[IPR_INIT_HRRQ].removing_ioa) {
9084 spin_unlock_irq(ioa_cfg->host->host_lock);
9085 scsi_unblock_requests(ioa_cfg->host);
9086 spin_lock_irq(ioa_cfg->host->host_lock);
9087 }
9088 return;
9089 } else {
9090 ioa_cfg->in_ioa_bringdown = 1;
9091 shutdown_type = IPR_SHUTDOWN_NONE;
9092 }
9093 }
9094
9095 _ipr_initiate_ioa_reset(ioa_cfg, ipr_reset_shutdown_ioa,
9096 shutdown_type);
9097}
9098
9099
9100
9101
9102
9103
9104
9105
9106
9107static int ipr_reset_freeze(struct ipr_cmnd *ipr_cmd)
9108{
9109 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
9110 int i;
9111
9112
9113 for (i = 0; i < ioa_cfg->hrrq_num; i++) {
9114 spin_lock(&ioa_cfg->hrrq[i]._lock);
9115 ioa_cfg->hrrq[i].allow_interrupts = 0;
9116 spin_unlock(&ioa_cfg->hrrq[i]._lock);
9117 }
9118 wmb();
9119 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_pending_q);
9120 ipr_cmd->done = ipr_reset_ioa_job;
9121 return IPR_RC_JOB_RETURN;
9122}
9123
9124
9125
9126
9127
9128
9129
9130
9131static pci_ers_result_t ipr_pci_mmio_enabled(struct pci_dev *pdev)
9132{
9133 unsigned long flags = 0;
9134 struct ipr_ioa_cfg *ioa_cfg = pci_get_drvdata(pdev);
9135
9136 spin_lock_irqsave(ioa_cfg->host->host_lock, flags);
9137 if (!ioa_cfg->probe_done)
9138 pci_save_state(pdev);
9139 spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags);
9140 return PCI_ERS_RESULT_NEED_RESET;
9141}
9142
9143
9144
9145
9146
9147
9148
9149
9150
9151static void ipr_pci_frozen(struct pci_dev *pdev)
9152{
9153 unsigned long flags = 0;
9154 struct ipr_ioa_cfg *ioa_cfg = pci_get_drvdata(pdev);
9155
9156 spin_lock_irqsave(ioa_cfg->host->host_lock, flags);
9157 if (ioa_cfg->probe_done)
9158 _ipr_initiate_ioa_reset(ioa_cfg, ipr_reset_freeze, IPR_SHUTDOWN_NONE);
9159 spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags);
9160}
9161
9162
9163
9164
9165
9166
9167
9168
9169
9170static pci_ers_result_t ipr_pci_slot_reset(struct pci_dev *pdev)
9171{
9172 unsigned long flags = 0;
9173 struct ipr_ioa_cfg *ioa_cfg = pci_get_drvdata(pdev);
9174
9175 spin_lock_irqsave(ioa_cfg->host->host_lock, flags);
9176 if (ioa_cfg->probe_done) {
9177 if (ioa_cfg->needs_warm_reset)
9178 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
9179 else
9180 _ipr_initiate_ioa_reset(ioa_cfg, ipr_reset_restore_cfg_space,
9181 IPR_SHUTDOWN_NONE);
9182 } else
9183 wake_up_all(&ioa_cfg->eeh_wait_q);
9184 spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags);
9185 return PCI_ERS_RESULT_RECOVERED;
9186}
9187
9188
9189
9190
9191
9192
9193
9194
9195static void ipr_pci_perm_failure(struct pci_dev *pdev)
9196{
9197 unsigned long flags = 0;
9198 struct ipr_ioa_cfg *ioa_cfg = pci_get_drvdata(pdev);
9199 int i;
9200
9201 spin_lock_irqsave(ioa_cfg->host->host_lock, flags);
9202 if (ioa_cfg->probe_done) {
9203 if (ioa_cfg->sdt_state == WAIT_FOR_DUMP)
9204 ioa_cfg->sdt_state = ABORT_DUMP;
9205 ioa_cfg->reset_retries = IPR_NUM_RESET_RELOAD_RETRIES - 1;
9206 ioa_cfg->in_ioa_bringdown = 1;
9207 for (i = 0; i < ioa_cfg->hrrq_num; i++) {
9208 spin_lock(&ioa_cfg->hrrq[i]._lock);
9209 ioa_cfg->hrrq[i].allow_cmds = 0;
9210 spin_unlock(&ioa_cfg->hrrq[i]._lock);
9211 }
9212 wmb();
9213 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
9214 } else
9215 wake_up_all(&ioa_cfg->eeh_wait_q);
9216 spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags);
9217}
9218
9219
9220
9221
9222
9223
9224
9225
9226
9227
9228
9229static pci_ers_result_t ipr_pci_error_detected(struct pci_dev *pdev,
9230 pci_channel_state_t state)
9231{
9232 switch (state) {
9233 case pci_channel_io_frozen:
9234 ipr_pci_frozen(pdev);
9235 return PCI_ERS_RESULT_CAN_RECOVER;
9236 case pci_channel_io_perm_failure:
9237 ipr_pci_perm_failure(pdev);
9238 return PCI_ERS_RESULT_DISCONNECT;
9239 break;
9240 default:
9241 break;
9242 }
9243 return PCI_ERS_RESULT_NEED_RESET;
9244}
9245
9246
9247
9248
9249
9250
9251
9252
9253
9254
9255
9256
9257static int ipr_probe_ioa_part2(struct ipr_ioa_cfg *ioa_cfg)
9258{
9259 int rc = 0;
9260 unsigned long host_lock_flags = 0;
9261
9262 ENTER;
9263 spin_lock_irqsave(ioa_cfg->host->host_lock, host_lock_flags);
9264 dev_dbg(&ioa_cfg->pdev->dev, "ioa_cfg adx: 0x%p\n", ioa_cfg);
9265 ioa_cfg->probe_done = 1;
9266 if (ioa_cfg->needs_hard_reset) {
9267 ioa_cfg->needs_hard_reset = 0;
9268 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
9269 } else
9270 _ipr_initiate_ioa_reset(ioa_cfg, ipr_reset_enable_ioa,
9271 IPR_SHUTDOWN_NONE);
9272 spin_unlock_irqrestore(ioa_cfg->host->host_lock, host_lock_flags);
9273
9274 LEAVE;
9275 return rc;
9276}
9277
9278
9279
9280
9281
9282
9283
9284
9285static void ipr_free_cmd_blks(struct ipr_ioa_cfg *ioa_cfg)
9286{
9287 int i;
9288
9289 if (ioa_cfg->ipr_cmnd_list) {
9290 for (i = 0; i < IPR_NUM_CMD_BLKS; i++) {
9291 if (ioa_cfg->ipr_cmnd_list[i])
9292 dma_pool_free(ioa_cfg->ipr_cmd_pool,
9293 ioa_cfg->ipr_cmnd_list[i],
9294 ioa_cfg->ipr_cmnd_list_dma[i]);
9295
9296 ioa_cfg->ipr_cmnd_list[i] = NULL;
9297 }
9298 }
9299
9300 if (ioa_cfg->ipr_cmd_pool)
9301 dma_pool_destroy(ioa_cfg->ipr_cmd_pool);
9302
9303 kfree(ioa_cfg->ipr_cmnd_list);
9304 kfree(ioa_cfg->ipr_cmnd_list_dma);
9305 ioa_cfg->ipr_cmnd_list = NULL;
9306 ioa_cfg->ipr_cmnd_list_dma = NULL;
9307 ioa_cfg->ipr_cmd_pool = NULL;
9308}
9309
9310
9311
9312
9313
9314
9315
9316
9317static void ipr_free_mem(struct ipr_ioa_cfg *ioa_cfg)
9318{
9319 int i;
9320
9321 kfree(ioa_cfg->res_entries);
9322 dma_free_coherent(&ioa_cfg->pdev->dev, sizeof(struct ipr_misc_cbs),
9323 ioa_cfg->vpd_cbs, ioa_cfg->vpd_cbs_dma);
9324 ipr_free_cmd_blks(ioa_cfg);
9325
9326 for (i = 0; i < ioa_cfg->hrrq_num; i++)
9327 dma_free_coherent(&ioa_cfg->pdev->dev,
9328 sizeof(u32) * ioa_cfg->hrrq[i].size,
9329 ioa_cfg->hrrq[i].host_rrq,
9330 ioa_cfg->hrrq[i].host_rrq_dma);
9331
9332 dma_free_coherent(&ioa_cfg->pdev->dev, ioa_cfg->cfg_table_size,
9333 ioa_cfg->u.cfg_table, ioa_cfg->cfg_table_dma);
9334
9335 for (i = 0; i < IPR_NUM_HCAMS; i++) {
9336 dma_free_coherent(&ioa_cfg->pdev->dev,
9337 sizeof(struct ipr_hostrcb),
9338 ioa_cfg->hostrcb[i],
9339 ioa_cfg->hostrcb_dma[i]);
9340 }
9341
9342 ipr_free_dump(ioa_cfg);
9343 kfree(ioa_cfg->trace);
9344}
9345
9346
9347
9348
9349
9350
9351
9352
9353
9354
9355
9356static void ipr_free_irqs(struct ipr_ioa_cfg *ioa_cfg)
9357{
9358 struct pci_dev *pdev = ioa_cfg->pdev;
9359
9360 if (ioa_cfg->intr_flag == IPR_USE_MSI ||
9361 ioa_cfg->intr_flag == IPR_USE_MSIX) {
9362 int i;
9363 for (i = 0; i < ioa_cfg->nvectors; i++)
9364 free_irq(ioa_cfg->vectors_info[i].vec,
9365 &ioa_cfg->hrrq[i]);
9366 } else
9367 free_irq(pdev->irq, &ioa_cfg->hrrq[0]);
9368
9369 if (ioa_cfg->intr_flag == IPR_USE_MSI) {
9370 pci_disable_msi(pdev);
9371 ioa_cfg->intr_flag &= ~IPR_USE_MSI;
9372 } else if (ioa_cfg->intr_flag == IPR_USE_MSIX) {
9373 pci_disable_msix(pdev);
9374 ioa_cfg->intr_flag &= ~IPR_USE_MSIX;
9375 }
9376}
9377
9378
9379
9380
9381
9382
9383
9384
9385
9386
9387
9388static void ipr_free_all_resources(struct ipr_ioa_cfg *ioa_cfg)
9389{
9390 struct pci_dev *pdev = ioa_cfg->pdev;
9391
9392 ENTER;
9393 ipr_free_irqs(ioa_cfg);
9394 if (ioa_cfg->reset_work_q)
9395 destroy_workqueue(ioa_cfg->reset_work_q);
9396 iounmap(ioa_cfg->hdw_dma_regs);
9397 pci_release_regions(pdev);
9398 ipr_free_mem(ioa_cfg);
9399 scsi_host_put(ioa_cfg->host);
9400 pci_disable_device(pdev);
9401 LEAVE;
9402}
9403
9404
9405
9406
9407
9408
9409
9410
9411static int ipr_alloc_cmd_blks(struct ipr_ioa_cfg *ioa_cfg)
9412{
9413 struct ipr_cmnd *ipr_cmd;
9414 struct ipr_ioarcb *ioarcb;
9415 dma_addr_t dma_addr;
9416 int i, entries_each_hrrq, hrrq_id = 0;
9417
9418 ioa_cfg->ipr_cmd_pool = dma_pool_create(IPR_NAME, &ioa_cfg->pdev->dev,
9419 sizeof(struct ipr_cmnd), 512, 0);
9420
9421 if (!ioa_cfg->ipr_cmd_pool)
9422 return -ENOMEM;
9423
9424 ioa_cfg->ipr_cmnd_list = kcalloc(IPR_NUM_CMD_BLKS, sizeof(struct ipr_cmnd *), GFP_KERNEL);
9425 ioa_cfg->ipr_cmnd_list_dma = kcalloc(IPR_NUM_CMD_BLKS, sizeof(dma_addr_t), GFP_KERNEL);
9426
9427 if (!ioa_cfg->ipr_cmnd_list || !ioa_cfg->ipr_cmnd_list_dma) {
9428 ipr_free_cmd_blks(ioa_cfg);
9429 return -ENOMEM;
9430 }
9431
9432 for (i = 0; i < ioa_cfg->hrrq_num; i++) {
9433 if (ioa_cfg->hrrq_num > 1) {
9434 if (i == 0) {
9435 entries_each_hrrq = IPR_NUM_INTERNAL_CMD_BLKS;
9436 ioa_cfg->hrrq[i].min_cmd_id = 0;
9437 ioa_cfg->hrrq[i].max_cmd_id =
9438 (entries_each_hrrq - 1);
9439 } else {
9440 entries_each_hrrq =
9441 IPR_NUM_BASE_CMD_BLKS/
9442 (ioa_cfg->hrrq_num - 1);
9443 ioa_cfg->hrrq[i].min_cmd_id =
9444 IPR_NUM_INTERNAL_CMD_BLKS +
9445 (i - 1) * entries_each_hrrq;
9446 ioa_cfg->hrrq[i].max_cmd_id =
9447 (IPR_NUM_INTERNAL_CMD_BLKS +
9448 i * entries_each_hrrq - 1);
9449 }
9450 } else {
9451 entries_each_hrrq = IPR_NUM_CMD_BLKS;
9452 ioa_cfg->hrrq[i].min_cmd_id = 0;
9453 ioa_cfg->hrrq[i].max_cmd_id = (entries_each_hrrq - 1);
9454 }
9455 ioa_cfg->hrrq[i].size = entries_each_hrrq;
9456 }
9457
9458 BUG_ON(ioa_cfg->hrrq_num == 0);
9459
9460 i = IPR_NUM_CMD_BLKS -
9461 ioa_cfg->hrrq[ioa_cfg->hrrq_num - 1].max_cmd_id - 1;
9462 if (i > 0) {
9463 ioa_cfg->hrrq[ioa_cfg->hrrq_num - 1].size += i;
9464 ioa_cfg->hrrq[ioa_cfg->hrrq_num - 1].max_cmd_id += i;
9465 }
9466
9467 for (i = 0; i < IPR_NUM_CMD_BLKS; i++) {
9468 ipr_cmd = dma_pool_alloc(ioa_cfg->ipr_cmd_pool, GFP_KERNEL, &dma_addr);
9469
9470 if (!ipr_cmd) {
9471 ipr_free_cmd_blks(ioa_cfg);
9472 return -ENOMEM;
9473 }
9474
9475 memset(ipr_cmd, 0, sizeof(*ipr_cmd));
9476 ioa_cfg->ipr_cmnd_list[i] = ipr_cmd;
9477 ioa_cfg->ipr_cmnd_list_dma[i] = dma_addr;
9478
9479 ioarcb = &ipr_cmd->ioarcb;
9480 ipr_cmd->dma_addr = dma_addr;
9481 if (ioa_cfg->sis64)
9482 ioarcb->a.ioarcb_host_pci_addr64 = cpu_to_be64(dma_addr);
9483 else
9484 ioarcb->a.ioarcb_host_pci_addr = cpu_to_be32(dma_addr);
9485
9486 ioarcb->host_response_handle = cpu_to_be32(i << 2);
9487 if (ioa_cfg->sis64) {
9488 ioarcb->u.sis64_addr_data.data_ioadl_addr =
9489 cpu_to_be64(dma_addr + offsetof(struct ipr_cmnd, i.ioadl64));
9490 ioarcb->u.sis64_addr_data.ioasa_host_pci_addr =
9491 cpu_to_be64(dma_addr + offsetof(struct ipr_cmnd, s.ioasa64));
9492 } else {
9493 ioarcb->write_ioadl_addr =
9494 cpu_to_be32(dma_addr + offsetof(struct ipr_cmnd, i.ioadl));
9495 ioarcb->read_ioadl_addr = ioarcb->write_ioadl_addr;
9496 ioarcb->ioasa_host_pci_addr =
9497 cpu_to_be32(dma_addr + offsetof(struct ipr_cmnd, s.ioasa));
9498 }
9499 ioarcb->ioasa_len = cpu_to_be16(sizeof(struct ipr_ioasa));
9500 ipr_cmd->cmd_index = i;
9501 ipr_cmd->ioa_cfg = ioa_cfg;
9502 ipr_cmd->sense_buffer_dma = dma_addr +
9503 offsetof(struct ipr_cmnd, sense_buffer);
9504
9505 ipr_cmd->ioarcb.cmd_pkt.hrrq_id = hrrq_id;
9506 ipr_cmd->hrrq = &ioa_cfg->hrrq[hrrq_id];
9507 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
9508 if (i >= ioa_cfg->hrrq[hrrq_id].max_cmd_id)
9509 hrrq_id++;
9510 }
9511
9512 return 0;
9513}
9514
9515
9516
9517
9518
9519
9520
9521
9522static int ipr_alloc_mem(struct ipr_ioa_cfg *ioa_cfg)
9523{
9524 struct pci_dev *pdev = ioa_cfg->pdev;
9525 int i, rc = -ENOMEM;
9526
9527 ENTER;
9528 ioa_cfg->res_entries = kzalloc(sizeof(struct ipr_resource_entry) *
9529 ioa_cfg->max_devs_supported, GFP_KERNEL);
9530
9531 if (!ioa_cfg->res_entries)
9532 goto out;
9533
9534 for (i = 0; i < ioa_cfg->max_devs_supported; i++) {
9535 list_add_tail(&ioa_cfg->res_entries[i].queue, &ioa_cfg->free_res_q);
9536 ioa_cfg->res_entries[i].ioa_cfg = ioa_cfg;
9537 }
9538
9539 ioa_cfg->vpd_cbs = dma_alloc_coherent(&pdev->dev,
9540 sizeof(struct ipr_misc_cbs),
9541 &ioa_cfg->vpd_cbs_dma,
9542 GFP_KERNEL);
9543
9544 if (!ioa_cfg->vpd_cbs)
9545 goto out_free_res_entries;
9546
9547 if (ipr_alloc_cmd_blks(ioa_cfg))
9548 goto out_free_vpd_cbs;
9549
9550 for (i = 0; i < ioa_cfg->hrrq_num; i++) {
9551 ioa_cfg->hrrq[i].host_rrq = dma_alloc_coherent(&pdev->dev,
9552 sizeof(u32) * ioa_cfg->hrrq[i].size,
9553 &ioa_cfg->hrrq[i].host_rrq_dma,
9554 GFP_KERNEL);
9555
9556 if (!ioa_cfg->hrrq[i].host_rrq) {
9557 while (--i > 0)
9558 dma_free_coherent(&pdev->dev,
9559 sizeof(u32) * ioa_cfg->hrrq[i].size,
9560 ioa_cfg->hrrq[i].host_rrq,
9561 ioa_cfg->hrrq[i].host_rrq_dma);
9562 goto out_ipr_free_cmd_blocks;
9563 }
9564 ioa_cfg->hrrq[i].ioa_cfg = ioa_cfg;
9565 }
9566
9567 ioa_cfg->u.cfg_table = dma_alloc_coherent(&pdev->dev,
9568 ioa_cfg->cfg_table_size,
9569 &ioa_cfg->cfg_table_dma,
9570 GFP_KERNEL);
9571
9572 if (!ioa_cfg->u.cfg_table)
9573 goto out_free_host_rrq;
9574
9575 for (i = 0; i < IPR_NUM_HCAMS; i++) {
9576 ioa_cfg->hostrcb[i] = dma_alloc_coherent(&pdev->dev,
9577 sizeof(struct ipr_hostrcb),
9578 &ioa_cfg->hostrcb_dma[i],
9579 GFP_KERNEL);
9580
9581 if (!ioa_cfg->hostrcb[i])
9582 goto out_free_hostrcb_dma;
9583
9584 ioa_cfg->hostrcb[i]->hostrcb_dma =
9585 ioa_cfg->hostrcb_dma[i] + offsetof(struct ipr_hostrcb, hcam);
9586 ioa_cfg->hostrcb[i]->ioa_cfg = ioa_cfg;
9587 list_add_tail(&ioa_cfg->hostrcb[i]->queue, &ioa_cfg->hostrcb_free_q);
9588 }
9589
9590 ioa_cfg->trace = kzalloc(sizeof(struct ipr_trace_entry) *
9591 IPR_NUM_TRACE_ENTRIES, GFP_KERNEL);
9592
9593 if (!ioa_cfg->trace)
9594 goto out_free_hostrcb_dma;
9595
9596 rc = 0;
9597out:
9598 LEAVE;
9599 return rc;
9600
9601out_free_hostrcb_dma:
9602 while (i-- > 0) {
9603 dma_free_coherent(&pdev->dev, sizeof(struct ipr_hostrcb),
9604 ioa_cfg->hostrcb[i],
9605 ioa_cfg->hostrcb_dma[i]);
9606 }
9607 dma_free_coherent(&pdev->dev, ioa_cfg->cfg_table_size,
9608 ioa_cfg->u.cfg_table, ioa_cfg->cfg_table_dma);
9609out_free_host_rrq:
9610 for (i = 0; i < ioa_cfg->hrrq_num; i++) {
9611 dma_free_coherent(&pdev->dev,
9612 sizeof(u32) * ioa_cfg->hrrq[i].size,
9613 ioa_cfg->hrrq[i].host_rrq,
9614 ioa_cfg->hrrq[i].host_rrq_dma);
9615 }
9616out_ipr_free_cmd_blocks:
9617 ipr_free_cmd_blks(ioa_cfg);
9618out_free_vpd_cbs:
9619 dma_free_coherent(&pdev->dev, sizeof(struct ipr_misc_cbs),
9620 ioa_cfg->vpd_cbs, ioa_cfg->vpd_cbs_dma);
9621out_free_res_entries:
9622 kfree(ioa_cfg->res_entries);
9623 goto out;
9624}
9625
9626
9627
9628
9629
9630
9631
9632
9633static void ipr_initialize_bus_attr(struct ipr_ioa_cfg *ioa_cfg)
9634{
9635 int i;
9636
9637 for (i = 0; i < IPR_MAX_NUM_BUSES; i++) {
9638 ioa_cfg->bus_attr[i].bus = i;
9639 ioa_cfg->bus_attr[i].qas_enabled = 0;
9640 ioa_cfg->bus_attr[i].bus_width = IPR_DEFAULT_BUS_WIDTH;
9641 if (ipr_max_speed < ARRAY_SIZE(ipr_max_bus_speeds))
9642 ioa_cfg->bus_attr[i].max_xfer_rate = ipr_max_bus_speeds[ipr_max_speed];
9643 else
9644 ioa_cfg->bus_attr[i].max_xfer_rate = IPR_U160_SCSI_RATE;
9645 }
9646}
9647
9648
9649
9650
9651
9652
9653
9654
9655static void ipr_init_regs(struct ipr_ioa_cfg *ioa_cfg)
9656{
9657 const struct ipr_interrupt_offsets *p;
9658 struct ipr_interrupts *t;
9659 void __iomem *base;
9660
9661 p = &ioa_cfg->chip_cfg->regs;
9662 t = &ioa_cfg->regs;
9663 base = ioa_cfg->hdw_dma_regs;
9664
9665 t->set_interrupt_mask_reg = base + p->set_interrupt_mask_reg;
9666 t->clr_interrupt_mask_reg = base + p->clr_interrupt_mask_reg;
9667 t->clr_interrupt_mask_reg32 = base + p->clr_interrupt_mask_reg32;
9668 t->sense_interrupt_mask_reg = base + p->sense_interrupt_mask_reg;
9669 t->sense_interrupt_mask_reg32 = base + p->sense_interrupt_mask_reg32;
9670 t->clr_interrupt_reg = base + p->clr_interrupt_reg;
9671 t->clr_interrupt_reg32 = base + p->clr_interrupt_reg32;
9672 t->sense_interrupt_reg = base + p->sense_interrupt_reg;
9673 t->sense_interrupt_reg32 = base + p->sense_interrupt_reg32;
9674 t->ioarrin_reg = base + p->ioarrin_reg;
9675 t->sense_uproc_interrupt_reg = base + p->sense_uproc_interrupt_reg;
9676 t->sense_uproc_interrupt_reg32 = base + p->sense_uproc_interrupt_reg32;
9677 t->set_uproc_interrupt_reg = base + p->set_uproc_interrupt_reg;
9678 t->set_uproc_interrupt_reg32 = base + p->set_uproc_interrupt_reg32;
9679 t->clr_uproc_interrupt_reg = base + p->clr_uproc_interrupt_reg;
9680 t->clr_uproc_interrupt_reg32 = base + p->clr_uproc_interrupt_reg32;
9681
9682 if (ioa_cfg->sis64) {
9683 t->init_feedback_reg = base + p->init_feedback_reg;
9684 t->dump_addr_reg = base + p->dump_addr_reg;
9685 t->dump_data_reg = base + p->dump_data_reg;
9686 t->endian_swap_reg = base + p->endian_swap_reg;
9687 }
9688}
9689
9690
9691
9692
9693
9694
9695
9696
9697
9698
9699static void ipr_init_ioa_cfg(struct ipr_ioa_cfg *ioa_cfg,
9700 struct Scsi_Host *host, struct pci_dev *pdev)
9701{
9702 int i;
9703
9704 ioa_cfg->host = host;
9705 ioa_cfg->pdev = pdev;
9706 ioa_cfg->log_level = ipr_log_level;
9707 ioa_cfg->doorbell = IPR_DOORBELL;
9708 sprintf(ioa_cfg->eye_catcher, IPR_EYECATCHER);
9709 sprintf(ioa_cfg->trace_start, IPR_TRACE_START_LABEL);
9710 sprintf(ioa_cfg->cfg_table_start, IPR_CFG_TBL_START);
9711 sprintf(ioa_cfg->resource_table_label, IPR_RES_TABLE_LABEL);
9712 sprintf(ioa_cfg->ipr_hcam_label, IPR_HCAM_LABEL);
9713 sprintf(ioa_cfg->ipr_cmd_label, IPR_CMD_LABEL);
9714
9715 INIT_LIST_HEAD(&ioa_cfg->hostrcb_free_q);
9716 INIT_LIST_HEAD(&ioa_cfg->hostrcb_pending_q);
9717 INIT_LIST_HEAD(&ioa_cfg->free_res_q);
9718 INIT_LIST_HEAD(&ioa_cfg->used_res_q);
9719 INIT_WORK(&ioa_cfg->work_q, ipr_worker_thread);
9720 init_waitqueue_head(&ioa_cfg->reset_wait_q);
9721 init_waitqueue_head(&ioa_cfg->msi_wait_q);
9722 init_waitqueue_head(&ioa_cfg->eeh_wait_q);
9723 ioa_cfg->sdt_state = INACTIVE;
9724
9725 ipr_initialize_bus_attr(ioa_cfg);
9726 ioa_cfg->max_devs_supported = ipr_max_devs;
9727
9728 if (ioa_cfg->sis64) {
9729 host->max_id = IPR_MAX_SIS64_TARGETS_PER_BUS;
9730 host->max_lun = IPR_MAX_SIS64_LUNS_PER_TARGET;
9731 if (ipr_max_devs > IPR_MAX_SIS64_DEVS)
9732 ioa_cfg->max_devs_supported = IPR_MAX_SIS64_DEVS;
9733 ioa_cfg->cfg_table_size = (sizeof(struct ipr_config_table_hdr64)
9734 + ((sizeof(struct ipr_config_table_entry64)
9735 * ioa_cfg->max_devs_supported)));
9736 } else {
9737 host->max_id = IPR_MAX_NUM_TARGETS_PER_BUS;
9738 host->max_lun = IPR_MAX_NUM_LUNS_PER_TARGET;
9739 if (ipr_max_devs > IPR_MAX_PHYSICAL_DEVS)
9740 ioa_cfg->max_devs_supported = IPR_MAX_PHYSICAL_DEVS;
9741 ioa_cfg->cfg_table_size = (sizeof(struct ipr_config_table_hdr)
9742 + ((sizeof(struct ipr_config_table_entry)
9743 * ioa_cfg->max_devs_supported)));
9744 }
9745
9746 host->max_channel = IPR_VSET_BUS;
9747 host->unique_id = host->host_no;
9748 host->max_cmd_len = IPR_MAX_CDB_LEN;
9749 host->can_queue = ioa_cfg->max_cmds;
9750 pci_set_drvdata(pdev, ioa_cfg);
9751
9752 for (i = 0; i < ARRAY_SIZE(ioa_cfg->hrrq); i++) {
9753 INIT_LIST_HEAD(&ioa_cfg->hrrq[i].hrrq_free_q);
9754 INIT_LIST_HEAD(&ioa_cfg->hrrq[i].hrrq_pending_q);
9755 spin_lock_init(&ioa_cfg->hrrq[i]._lock);
9756 if (i == 0)
9757 ioa_cfg->hrrq[i].lock = ioa_cfg->host->host_lock;
9758 else
9759 ioa_cfg->hrrq[i].lock = &ioa_cfg->hrrq[i]._lock;
9760 }
9761}
9762
9763
9764
9765
9766
9767
9768
9769
9770static const struct ipr_chip_t *
9771ipr_get_chip_info(const struct pci_device_id *dev_id)
9772{
9773 int i;
9774
9775 for (i = 0; i < ARRAY_SIZE(ipr_chip); i++)
9776 if (ipr_chip[i].vendor == dev_id->vendor &&
9777 ipr_chip[i].device == dev_id->device)
9778 return &ipr_chip[i];
9779 return NULL;
9780}
9781
9782
9783
9784
9785
9786
9787
9788
9789
9790static void ipr_wait_for_pci_err_recovery(struct ipr_ioa_cfg *ioa_cfg)
9791{
9792 struct pci_dev *pdev = ioa_cfg->pdev;
9793
9794 if (pci_channel_offline(pdev)) {
9795 wait_event_timeout(ioa_cfg->eeh_wait_q,
9796 !pci_channel_offline(pdev),
9797 IPR_PCI_ERROR_RECOVERY_TIMEOUT);
9798 pci_restore_state(pdev);
9799 }
9800}
9801
9802static int ipr_enable_msix(struct ipr_ioa_cfg *ioa_cfg)
9803{
9804 struct msix_entry entries[IPR_MAX_MSIX_VECTORS];
9805 int i, vectors;
9806
9807 for (i = 0; i < ARRAY_SIZE(entries); ++i)
9808 entries[i].entry = i;
9809
9810 vectors = pci_enable_msix_range(ioa_cfg->pdev,
9811 entries, 1, ipr_number_of_msix);
9812 if (vectors < 0) {
9813 ipr_wait_for_pci_err_recovery(ioa_cfg);
9814 return vectors;
9815 }
9816
9817 for (i = 0; i < vectors; i++)
9818 ioa_cfg->vectors_info[i].vec = entries[i].vector;
9819 ioa_cfg->nvectors = vectors;
9820
9821 return 0;
9822}
9823
9824static int ipr_enable_msi(struct ipr_ioa_cfg *ioa_cfg)
9825{
9826 int i, vectors;
9827
9828 vectors = pci_enable_msi_range(ioa_cfg->pdev, 1, ipr_number_of_msix);
9829 if (vectors < 0) {
9830 ipr_wait_for_pci_err_recovery(ioa_cfg);
9831 return vectors;
9832 }
9833
9834 for (i = 0; i < vectors; i++)
9835 ioa_cfg->vectors_info[i].vec = ioa_cfg->pdev->irq + i;
9836 ioa_cfg->nvectors = vectors;
9837
9838 return 0;
9839}
9840
9841static void name_msi_vectors(struct ipr_ioa_cfg *ioa_cfg)
9842{
9843 int vec_idx, n = sizeof(ioa_cfg->vectors_info[0].desc) - 1;
9844
9845 for (vec_idx = 0; vec_idx < ioa_cfg->nvectors; vec_idx++) {
9846 snprintf(ioa_cfg->vectors_info[vec_idx].desc, n,
9847 "host%d-%d", ioa_cfg->host->host_no, vec_idx);
9848 ioa_cfg->vectors_info[vec_idx].
9849 desc[strlen(ioa_cfg->vectors_info[vec_idx].desc)] = 0;
9850 }
9851}
9852
9853static int ipr_request_other_msi_irqs(struct ipr_ioa_cfg *ioa_cfg)
9854{
9855 int i, rc;
9856
9857 for (i = 1; i < ioa_cfg->nvectors; i++) {
9858 rc = request_irq(ioa_cfg->vectors_info[i].vec,
9859 ipr_isr_mhrrq,
9860 0,
9861 ioa_cfg->vectors_info[i].desc,
9862 &ioa_cfg->hrrq[i]);
9863 if (rc) {
9864 while (--i >= 0)
9865 free_irq(ioa_cfg->vectors_info[i].vec,
9866 &ioa_cfg->hrrq[i]);
9867 return rc;
9868 }
9869 }
9870 return 0;
9871}
9872
9873
9874
9875
9876
9877
9878
9879
9880
9881
9882
9883static irqreturn_t ipr_test_intr(int irq, void *devp)
9884{
9885 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)devp;
9886 unsigned long lock_flags = 0;
9887 irqreturn_t rc = IRQ_HANDLED;
9888
9889 dev_info(&ioa_cfg->pdev->dev, "Received IRQ : %d\n", irq);
9890 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
9891
9892 ioa_cfg->msi_received = 1;
9893 wake_up(&ioa_cfg->msi_wait_q);
9894
9895 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
9896 return rc;
9897}
9898
9899
9900
9901
9902
9903
9904
9905
9906
9907
9908
9909
9910
9911static int ipr_test_msi(struct ipr_ioa_cfg *ioa_cfg, struct pci_dev *pdev)
9912{
9913 int rc;
9914 volatile u32 int_reg;
9915 unsigned long lock_flags = 0;
9916
9917 ENTER;
9918
9919 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
9920 init_waitqueue_head(&ioa_cfg->msi_wait_q);
9921 ioa_cfg->msi_received = 0;
9922 ipr_mask_and_clear_interrupts(ioa_cfg, ~IPR_PCII_IOA_TRANS_TO_OPER);
9923 writel(IPR_PCII_IO_DEBUG_ACKNOWLEDGE, ioa_cfg->regs.clr_interrupt_mask_reg32);
9924 int_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg);
9925 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
9926
9927 if (ioa_cfg->intr_flag == IPR_USE_MSIX)
9928 rc = request_irq(ioa_cfg->vectors_info[0].vec, ipr_test_intr, 0, IPR_NAME, ioa_cfg);
9929 else
9930 rc = request_irq(pdev->irq, ipr_test_intr, 0, IPR_NAME, ioa_cfg);
9931 if (rc) {
9932 dev_err(&pdev->dev, "Can not assign irq %d\n", pdev->irq);
9933 return rc;
9934 } else if (ipr_debug)
9935 dev_info(&pdev->dev, "IRQ assigned: %d\n", pdev->irq);
9936
9937 writel(IPR_PCII_IO_DEBUG_ACKNOWLEDGE, ioa_cfg->regs.sense_interrupt_reg32);
9938 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg);
9939 wait_event_timeout(ioa_cfg->msi_wait_q, ioa_cfg->msi_received, HZ);
9940 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
9941 ipr_mask_and_clear_interrupts(ioa_cfg, ~IPR_PCII_IOA_TRANS_TO_OPER);
9942
9943 if (!ioa_cfg->msi_received) {
9944
9945 dev_info(&pdev->dev, "MSI test failed. Falling back to LSI.\n");
9946 rc = -EOPNOTSUPP;
9947 } else if (ipr_debug)
9948 dev_info(&pdev->dev, "MSI test succeeded.\n");
9949
9950 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
9951
9952 if (ioa_cfg->intr_flag == IPR_USE_MSIX)
9953 free_irq(ioa_cfg->vectors_info[0].vec, ioa_cfg);
9954 else
9955 free_irq(pdev->irq, ioa_cfg);
9956
9957 LEAVE;
9958
9959 return rc;
9960}
9961
9962
9963
9964
9965
9966
9967
9968
9969static int ipr_probe_ioa(struct pci_dev *pdev,
9970 const struct pci_device_id *dev_id)
9971{
9972 struct ipr_ioa_cfg *ioa_cfg;
9973 struct Scsi_Host *host;
9974 unsigned long ipr_regs_pci;
9975 void __iomem *ipr_regs;
9976 int rc = PCIBIOS_SUCCESSFUL;
9977 volatile u32 mask, uproc, interrupts;
9978 unsigned long lock_flags, driver_lock_flags;
9979
9980 ENTER;
9981
9982 dev_info(&pdev->dev, "Found IOA with IRQ: %d\n", pdev->irq);
9983 host = scsi_host_alloc(&driver_template, sizeof(*ioa_cfg));
9984
9985 if (!host) {
9986 dev_err(&pdev->dev, "call to scsi_host_alloc failed!\n");
9987 rc = -ENOMEM;
9988 goto out;
9989 }
9990
9991 ioa_cfg = (struct ipr_ioa_cfg *)host->hostdata;
9992 memset(ioa_cfg, 0, sizeof(struct ipr_ioa_cfg));
9993 ata_host_init(&ioa_cfg->ata_host, &pdev->dev, &ipr_sata_ops);
9994
9995 ioa_cfg->ipr_chip = ipr_get_chip_info(dev_id);
9996
9997 if (!ioa_cfg->ipr_chip) {
9998 dev_err(&pdev->dev, "Unknown adapter chipset 0x%04X 0x%04X\n",
9999 dev_id->vendor, dev_id->device);
10000 goto out_scsi_host_put;
10001 }
10002
10003
10004 ioa_cfg->sis64 = ioa_cfg->ipr_chip->sis_type == IPR_SIS64 ? 1 : 0;
10005 ioa_cfg->chip_cfg = ioa_cfg->ipr_chip->cfg;
10006 ioa_cfg->clear_isr = ioa_cfg->chip_cfg->clear_isr;
10007 ioa_cfg->max_cmds = ioa_cfg->chip_cfg->max_cmds;
10008
10009 if (ipr_transop_timeout)
10010 ioa_cfg->transop_timeout = ipr_transop_timeout;
10011 else if (dev_id->driver_data & IPR_USE_LONG_TRANSOP_TIMEOUT)
10012 ioa_cfg->transop_timeout = IPR_LONG_OPERATIONAL_TIMEOUT;
10013 else
10014 ioa_cfg->transop_timeout = IPR_OPERATIONAL_TIMEOUT;
10015
10016 ioa_cfg->revid = pdev->revision;
10017
10018 ipr_init_ioa_cfg(ioa_cfg, host, pdev);
10019
10020 ipr_regs_pci = pci_resource_start(pdev, 0);
10021
10022 rc = pci_request_regions(pdev, IPR_NAME);
10023 if (rc < 0) {
10024 dev_err(&pdev->dev,
10025 "Couldn't register memory range of registers\n");
10026 goto out_scsi_host_put;
10027 }
10028
10029 rc = pci_enable_device(pdev);
10030
10031 if (rc || pci_channel_offline(pdev)) {
10032 if (pci_channel_offline(pdev)) {
10033 ipr_wait_for_pci_err_recovery(ioa_cfg);
10034 rc = pci_enable_device(pdev);
10035 }
10036
10037 if (rc) {
10038 dev_err(&pdev->dev, "Cannot enable adapter\n");
10039 ipr_wait_for_pci_err_recovery(ioa_cfg);
10040 goto out_release_regions;
10041 }
10042 }
10043
10044 ipr_regs = pci_ioremap_bar(pdev, 0);
10045
10046 if (!ipr_regs) {
10047 dev_err(&pdev->dev,
10048 "Couldn't map memory range of registers\n");
10049 rc = -ENOMEM;
10050 goto out_disable;
10051 }
10052
10053 ioa_cfg->hdw_dma_regs = ipr_regs;
10054 ioa_cfg->hdw_dma_regs_pci = ipr_regs_pci;
10055 ioa_cfg->ioa_mailbox = ioa_cfg->chip_cfg->mailbox + ipr_regs;
10056
10057 ipr_init_regs(ioa_cfg);
10058
10059 if (ioa_cfg->sis64) {
10060 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
10061 if (rc < 0) {
10062 dev_dbg(&pdev->dev, "Failed to set 64 bit DMA mask\n");
10063 rc = dma_set_mask_and_coherent(&pdev->dev,
10064 DMA_BIT_MASK(32));
10065 }
10066 } else
10067 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
10068
10069 if (rc < 0) {
10070 dev_err(&pdev->dev, "Failed to set DMA mask\n");
10071 goto cleanup_nomem;
10072 }
10073
10074 rc = pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
10075 ioa_cfg->chip_cfg->cache_line_size);
10076
10077 if (rc != PCIBIOS_SUCCESSFUL) {
10078 dev_err(&pdev->dev, "Write of cache line size failed\n");
10079 ipr_wait_for_pci_err_recovery(ioa_cfg);
10080 rc = -EIO;
10081 goto cleanup_nomem;
10082 }
10083
10084
10085 interrupts = readl(ioa_cfg->regs.sense_interrupt_reg);
10086 ipr_wait_for_pci_err_recovery(ioa_cfg);
10087
10088 if (ipr_number_of_msix > IPR_MAX_MSIX_VECTORS) {
10089 dev_err(&pdev->dev, "The max number of MSIX is %d\n",
10090 IPR_MAX_MSIX_VECTORS);
10091 ipr_number_of_msix = IPR_MAX_MSIX_VECTORS;
10092 }
10093
10094 if (ioa_cfg->ipr_chip->intr_type == IPR_USE_MSI &&
10095 ipr_enable_msix(ioa_cfg) == 0)
10096 ioa_cfg->intr_flag = IPR_USE_MSIX;
10097 else if (ioa_cfg->ipr_chip->intr_type == IPR_USE_MSI &&
10098 ipr_enable_msi(ioa_cfg) == 0)
10099 ioa_cfg->intr_flag = IPR_USE_MSI;
10100 else {
10101 ioa_cfg->intr_flag = IPR_USE_LSI;
10102 ioa_cfg->clear_isr = 1;
10103 ioa_cfg->nvectors = 1;
10104 dev_info(&pdev->dev, "Cannot enable MSI.\n");
10105 }
10106
10107 pci_set_master(pdev);
10108
10109 if (pci_channel_offline(pdev)) {
10110 ipr_wait_for_pci_err_recovery(ioa_cfg);
10111 pci_set_master(pdev);
10112 if (pci_channel_offline(pdev)) {
10113 rc = -EIO;
10114 goto out_msi_disable;
10115 }
10116 }
10117
10118 if (ioa_cfg->intr_flag == IPR_USE_MSI ||
10119 ioa_cfg->intr_flag == IPR_USE_MSIX) {
10120 rc = ipr_test_msi(ioa_cfg, pdev);
10121 if (rc == -EOPNOTSUPP) {
10122 ipr_wait_for_pci_err_recovery(ioa_cfg);
10123 if (ioa_cfg->intr_flag == IPR_USE_MSI) {
10124 ioa_cfg->intr_flag &= ~IPR_USE_MSI;
10125 pci_disable_msi(pdev);
10126 } else if (ioa_cfg->intr_flag == IPR_USE_MSIX) {
10127 ioa_cfg->intr_flag &= ~IPR_USE_MSIX;
10128 pci_disable_msix(pdev);
10129 }
10130
10131 ioa_cfg->intr_flag = IPR_USE_LSI;
10132 ioa_cfg->nvectors = 1;
10133 }
10134 else if (rc)
10135 goto out_msi_disable;
10136 else {
10137 if (ioa_cfg->intr_flag == IPR_USE_MSI)
10138 dev_info(&pdev->dev,
10139 "Request for %d MSIs succeeded with starting IRQ: %d\n",
10140 ioa_cfg->nvectors, pdev->irq);
10141 else if (ioa_cfg->intr_flag == IPR_USE_MSIX)
10142 dev_info(&pdev->dev,
10143 "Request for %d MSIXs succeeded.",
10144 ioa_cfg->nvectors);
10145 }
10146 }
10147
10148 ioa_cfg->hrrq_num = min3(ioa_cfg->nvectors,
10149 (unsigned int)num_online_cpus(),
10150 (unsigned int)IPR_MAX_HRRQ_NUM);
10151
10152 if ((rc = ipr_save_pcix_cmd_reg(ioa_cfg)))
10153 goto out_msi_disable;
10154
10155 if ((rc = ipr_set_pcix_cmd_reg(ioa_cfg)))
10156 goto out_msi_disable;
10157
10158 rc = ipr_alloc_mem(ioa_cfg);
10159 if (rc < 0) {
10160 dev_err(&pdev->dev,
10161 "Couldn't allocate enough memory for device driver!\n");
10162 goto out_msi_disable;
10163 }
10164
10165
10166 rc = pci_save_state(pdev);
10167
10168 if (rc != PCIBIOS_SUCCESSFUL) {
10169 dev_err(&pdev->dev, "Failed to save PCI config space\n");
10170 rc = -EIO;
10171 goto cleanup_nolog;
10172 }
10173
10174
10175
10176
10177
10178 mask = readl(ioa_cfg->regs.sense_interrupt_mask_reg32);
10179 interrupts = readl(ioa_cfg->regs.sense_interrupt_reg32);
10180 uproc = readl(ioa_cfg->regs.sense_uproc_interrupt_reg32);
10181 if ((mask & IPR_PCII_HRRQ_UPDATED) == 0 || (uproc & IPR_UPROCI_RESET_ALERT))
10182 ioa_cfg->needs_hard_reset = 1;
10183 if ((interrupts & IPR_PCII_ERROR_INTERRUPTS) || reset_devices)
10184 ioa_cfg->needs_hard_reset = 1;
10185 if (interrupts & IPR_PCII_IOA_UNIT_CHECKED)
10186 ioa_cfg->ioa_unit_checked = 1;
10187
10188 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
10189 ipr_mask_and_clear_interrupts(ioa_cfg, ~IPR_PCII_IOA_TRANS_TO_OPER);
10190 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
10191
10192 if (ioa_cfg->intr_flag == IPR_USE_MSI
10193 || ioa_cfg->intr_flag == IPR_USE_MSIX) {
10194 name_msi_vectors(ioa_cfg);
10195 rc = request_irq(ioa_cfg->vectors_info[0].vec, ipr_isr,
10196 0,
10197 ioa_cfg->vectors_info[0].desc,
10198 &ioa_cfg->hrrq[0]);
10199 if (!rc)
10200 rc = ipr_request_other_msi_irqs(ioa_cfg);
10201 } else {
10202 rc = request_irq(pdev->irq, ipr_isr,
10203 IRQF_SHARED,
10204 IPR_NAME, &ioa_cfg->hrrq[0]);
10205 }
10206 if (rc) {
10207 dev_err(&pdev->dev, "Couldn't register IRQ %d! rc=%d\n",
10208 pdev->irq, rc);
10209 goto cleanup_nolog;
10210 }
10211
10212 if ((dev_id->driver_data & IPR_USE_PCI_WARM_RESET) ||
10213 (dev_id->device == PCI_DEVICE_ID_IBM_OBSIDIAN_E && !ioa_cfg->revid)) {
10214 ioa_cfg->needs_warm_reset = 1;
10215 ioa_cfg->reset = ipr_reset_slot_reset;
10216
10217 ioa_cfg->reset_work_q = alloc_ordered_workqueue("ipr_reset_%d",
10218 WQ_MEM_RECLAIM, host->host_no);
10219
10220 if (!ioa_cfg->reset_work_q) {
10221 dev_err(&pdev->dev, "Couldn't register reset workqueue\n");
10222 rc = -ENOMEM;
10223 goto out_free_irq;
10224 }
10225 } else
10226 ioa_cfg->reset = ipr_reset_start_bist;
10227
10228 spin_lock_irqsave(&ipr_driver_lock, driver_lock_flags);
10229 list_add_tail(&ioa_cfg->queue, &ipr_ioa_head);
10230 spin_unlock_irqrestore(&ipr_driver_lock, driver_lock_flags);
10231
10232 LEAVE;
10233out:
10234 return rc;
10235
10236out_free_irq:
10237 ipr_free_irqs(ioa_cfg);
10238cleanup_nolog:
10239 ipr_free_mem(ioa_cfg);
10240out_msi_disable:
10241 ipr_wait_for_pci_err_recovery(ioa_cfg);
10242 if (ioa_cfg->intr_flag == IPR_USE_MSI)
10243 pci_disable_msi(pdev);
10244 else if (ioa_cfg->intr_flag == IPR_USE_MSIX)
10245 pci_disable_msix(pdev);
10246cleanup_nomem:
10247 iounmap(ipr_regs);
10248out_disable:
10249 pci_disable_device(pdev);
10250out_release_regions:
10251 pci_release_regions(pdev);
10252out_scsi_host_put:
10253 scsi_host_put(host);
10254 goto out;
10255}
10256
10257
10258
10259
10260
10261
10262
10263
10264
10265
10266
10267
10268
10269
10270
10271static void ipr_initiate_ioa_bringdown(struct ipr_ioa_cfg *ioa_cfg,
10272 enum ipr_shutdown_type shutdown_type)
10273{
10274 ENTER;
10275 if (ioa_cfg->sdt_state == WAIT_FOR_DUMP)
10276 ioa_cfg->sdt_state = ABORT_DUMP;
10277 ioa_cfg->reset_retries = 0;
10278 ioa_cfg->in_ioa_bringdown = 1;
10279 ipr_initiate_ioa_reset(ioa_cfg, shutdown_type);
10280 LEAVE;
10281}
10282
10283
10284
10285
10286
10287
10288
10289
10290
10291
10292static void __ipr_remove(struct pci_dev *pdev)
10293{
10294 unsigned long host_lock_flags = 0;
10295 struct ipr_ioa_cfg *ioa_cfg = pci_get_drvdata(pdev);
10296 int i;
10297 unsigned long driver_lock_flags;
10298 ENTER;
10299
10300 spin_lock_irqsave(ioa_cfg->host->host_lock, host_lock_flags);
10301 while (ioa_cfg->in_reset_reload) {
10302 spin_unlock_irqrestore(ioa_cfg->host->host_lock, host_lock_flags);
10303 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
10304 spin_lock_irqsave(ioa_cfg->host->host_lock, host_lock_flags);
10305 }
10306
10307 for (i = 0; i < ioa_cfg->hrrq_num; i++) {
10308 spin_lock(&ioa_cfg->hrrq[i]._lock);
10309 ioa_cfg->hrrq[i].removing_ioa = 1;
10310 spin_unlock(&ioa_cfg->hrrq[i]._lock);
10311 }
10312 wmb();
10313 ipr_initiate_ioa_bringdown(ioa_cfg, IPR_SHUTDOWN_NORMAL);
10314
10315 spin_unlock_irqrestore(ioa_cfg->host->host_lock, host_lock_flags);
10316 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
10317 flush_work(&ioa_cfg->work_q);
10318 if (ioa_cfg->reset_work_q)
10319 flush_workqueue(ioa_cfg->reset_work_q);
10320 INIT_LIST_HEAD(&ioa_cfg->used_res_q);
10321 spin_lock_irqsave(ioa_cfg->host->host_lock, host_lock_flags);
10322
10323 spin_lock_irqsave(&ipr_driver_lock, driver_lock_flags);
10324 list_del(&ioa_cfg->queue);
10325 spin_unlock_irqrestore(&ipr_driver_lock, driver_lock_flags);
10326
10327 if (ioa_cfg->sdt_state == ABORT_DUMP)
10328 ioa_cfg->sdt_state = WAIT_FOR_DUMP;
10329 spin_unlock_irqrestore(ioa_cfg->host->host_lock, host_lock_flags);
10330
10331 ipr_free_all_resources(ioa_cfg);
10332
10333 LEAVE;
10334}
10335
10336
10337
10338
10339
10340
10341
10342
10343
10344
10345static void ipr_remove(struct pci_dev *pdev)
10346{
10347 struct ipr_ioa_cfg *ioa_cfg = pci_get_drvdata(pdev);
10348
10349 ENTER;
10350
10351 ipr_remove_trace_file(&ioa_cfg->host->shost_dev.kobj,
10352 &ipr_trace_attr);
10353 ipr_remove_dump_file(&ioa_cfg->host->shost_dev.kobj,
10354 &ipr_dump_attr);
10355 scsi_remove_host(ioa_cfg->host);
10356
10357 __ipr_remove(pdev);
10358
10359 LEAVE;
10360}
10361
10362
10363
10364
10365
10366
10367
10368static int ipr_probe(struct pci_dev *pdev, const struct pci_device_id *dev_id)
10369{
10370 struct ipr_ioa_cfg *ioa_cfg;
10371 unsigned long flags;
10372 int rc, i;
10373
10374 rc = ipr_probe_ioa(pdev, dev_id);
10375
10376 if (rc)
10377 return rc;
10378
10379 ioa_cfg = pci_get_drvdata(pdev);
10380 rc = ipr_probe_ioa_part2(ioa_cfg);
10381
10382 if (rc) {
10383 __ipr_remove(pdev);
10384 return rc;
10385 }
10386
10387 rc = scsi_add_host(ioa_cfg->host, &pdev->dev);
10388
10389 if (rc) {
10390 __ipr_remove(pdev);
10391 return rc;
10392 }
10393
10394 rc = ipr_create_trace_file(&ioa_cfg->host->shost_dev.kobj,
10395 &ipr_trace_attr);
10396
10397 if (rc) {
10398 scsi_remove_host(ioa_cfg->host);
10399 __ipr_remove(pdev);
10400 return rc;
10401 }
10402
10403 rc = ipr_create_dump_file(&ioa_cfg->host->shost_dev.kobj,
10404 &ipr_dump_attr);
10405
10406 if (rc) {
10407 ipr_remove_trace_file(&ioa_cfg->host->shost_dev.kobj,
10408 &ipr_trace_attr);
10409 scsi_remove_host(ioa_cfg->host);
10410 __ipr_remove(pdev);
10411 return rc;
10412 }
10413 spin_lock_irqsave(ioa_cfg->host->host_lock, flags);
10414 ioa_cfg->scan_enabled = 1;
10415 schedule_work(&ioa_cfg->work_q);
10416 spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags);
10417
10418 ioa_cfg->iopoll_weight = ioa_cfg->chip_cfg->iopoll_weight;
10419
10420 if (ioa_cfg->iopoll_weight && ioa_cfg->sis64 && ioa_cfg->nvectors > 1) {
10421 for (i = 1; i < ioa_cfg->hrrq_num; i++) {
10422 irq_poll_init(&ioa_cfg->hrrq[i].iopoll,
10423 ioa_cfg->iopoll_weight, ipr_iopoll);
10424 }
10425 }
10426
10427 scsi_scan_host(ioa_cfg->host);
10428
10429 return 0;
10430}
10431
10432
10433
10434
10435
10436
10437
10438
10439
10440
10441
10442static void ipr_shutdown(struct pci_dev *pdev)
10443{
10444 struct ipr_ioa_cfg *ioa_cfg = pci_get_drvdata(pdev);
10445 unsigned long lock_flags = 0;
10446 enum ipr_shutdown_type shutdown_type = IPR_SHUTDOWN_NORMAL;
10447 int i;
10448
10449 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
10450 if (ioa_cfg->iopoll_weight && ioa_cfg->sis64 && ioa_cfg->nvectors > 1) {
10451 ioa_cfg->iopoll_weight = 0;
10452 for (i = 1; i < ioa_cfg->hrrq_num; i++)
10453 irq_poll_disable(&ioa_cfg->hrrq[i].iopoll);
10454 }
10455
10456 while (ioa_cfg->in_reset_reload) {
10457 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
10458 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
10459 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
10460 }
10461
10462 if (ipr_fast_reboot && system_state == SYSTEM_RESTART && ioa_cfg->sis64)
10463 shutdown_type = IPR_SHUTDOWN_QUIESCE;
10464
10465 ipr_initiate_ioa_bringdown(ioa_cfg, shutdown_type);
10466 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
10467 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
10468 if (ipr_fast_reboot && system_state == SYSTEM_RESTART && ioa_cfg->sis64) {
10469 ipr_free_irqs(ioa_cfg);
10470 pci_disable_device(ioa_cfg->pdev);
10471 }
10472}
10473
10474static struct pci_device_id ipr_pci_table[] = {
10475 { PCI_VENDOR_ID_MYLEX, PCI_DEVICE_ID_IBM_GEMSTONE,
10476 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_5702, 0, 0, 0 },
10477 { PCI_VENDOR_ID_MYLEX, PCI_DEVICE_ID_IBM_GEMSTONE,
10478 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_5703, 0, 0, 0 },
10479 { PCI_VENDOR_ID_MYLEX, PCI_DEVICE_ID_IBM_GEMSTONE,
10480 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_573D, 0, 0, 0 },
10481 { PCI_VENDOR_ID_MYLEX, PCI_DEVICE_ID_IBM_GEMSTONE,
10482 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_573E, 0, 0, 0 },
10483 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE,
10484 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_571B, 0, 0, 0 },
10485 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE,
10486 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_572E, 0, 0, 0 },
10487 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE,
10488 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_571A, 0, 0, 0 },
10489 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE,
10490 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_575B, 0, 0,
10491 IPR_USE_LONG_TRANSOP_TIMEOUT },
10492 { PCI_VENDOR_ID_ADAPTEC2, PCI_DEVICE_ID_ADAPTEC2_OBSIDIAN,
10493 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_572A, 0, 0, 0 },
10494 { PCI_VENDOR_ID_ADAPTEC2, PCI_DEVICE_ID_ADAPTEC2_OBSIDIAN,
10495 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_572B, 0, 0,
10496 IPR_USE_LONG_TRANSOP_TIMEOUT },
10497 { PCI_VENDOR_ID_ADAPTEC2, PCI_DEVICE_ID_ADAPTEC2_OBSIDIAN,
10498 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_575C, 0, 0,
10499 IPR_USE_LONG_TRANSOP_TIMEOUT },
10500 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN,
10501 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_572A, 0, 0, 0 },
10502 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN,
10503 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_572B, 0, 0,
10504 IPR_USE_LONG_TRANSOP_TIMEOUT},
10505 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN,
10506 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_575C, 0, 0,
10507 IPR_USE_LONG_TRANSOP_TIMEOUT },
10508 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN_E,
10509 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_574E, 0, 0,
10510 IPR_USE_LONG_TRANSOP_TIMEOUT },
10511 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN_E,
10512 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57B3, 0, 0, 0 },
10513 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN_E,
10514 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57CC, 0, 0, 0 },
10515 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN_E,
10516 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57B7, 0, 0,
10517 IPR_USE_LONG_TRANSOP_TIMEOUT | IPR_USE_PCI_WARM_RESET },
10518 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_SNIPE,
10519 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_2780, 0, 0, 0 },
10520 { PCI_VENDOR_ID_ADAPTEC2, PCI_DEVICE_ID_ADAPTEC2_SCAMP,
10521 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_571E, 0, 0, 0 },
10522 { PCI_VENDOR_ID_ADAPTEC2, PCI_DEVICE_ID_ADAPTEC2_SCAMP,
10523 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_571F, 0, 0,
10524 IPR_USE_LONG_TRANSOP_TIMEOUT },
10525 { PCI_VENDOR_ID_ADAPTEC2, PCI_DEVICE_ID_ADAPTEC2_SCAMP,
10526 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_572F, 0, 0,
10527 IPR_USE_LONG_TRANSOP_TIMEOUT },
10528 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_FPGA_E2,
10529 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57B5, 0, 0, 0 },
10530 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_FPGA_E2,
10531 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_574D, 0, 0, 0 },
10532 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_FPGA_E2,
10533 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57B2, 0, 0, 0 },
10534 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_FPGA_E2,
10535 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57C0, 0, 0, 0 },
10536 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_FPGA_E2,
10537 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57C3, 0, 0, 0 },
10538 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_FPGA_E2,
10539 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57C4, 0, 0, 0 },
10540 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
10541 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57B4, 0, 0, 0 },
10542 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
10543 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57B1, 0, 0, 0 },
10544 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
10545 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57C6, 0, 0, 0 },
10546 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
10547 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57C8, 0, 0, 0 },
10548 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
10549 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57CE, 0, 0, 0 },
10550 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
10551 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57D5, 0, 0, 0 },
10552 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
10553 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57D6, 0, 0, 0 },
10554 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
10555 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57D7, 0, 0, 0 },
10556 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
10557 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57D8, 0, 0, 0 },
10558 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
10559 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57D9, 0, 0, 0 },
10560 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
10561 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57DA, 0, 0, 0 },
10562 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
10563 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57EB, 0, 0, 0 },
10564 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
10565 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57EC, 0, 0, 0 },
10566 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
10567 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57ED, 0, 0, 0 },
10568 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
10569 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57EE, 0, 0, 0 },
10570 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
10571 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57EF, 0, 0, 0 },
10572 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
10573 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57F0, 0, 0, 0 },
10574 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
10575 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_2CCA, 0, 0, 0 },
10576 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
10577 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_2CD2, 0, 0, 0 },
10578 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
10579 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_2CCD, 0, 0, 0 },
10580 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_RATTLESNAKE,
10581 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_580A, 0, 0, 0 },
10582 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_RATTLESNAKE,
10583 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_580B, 0, 0, 0 },
10584 { }
10585};
10586MODULE_DEVICE_TABLE(pci, ipr_pci_table);
10587
10588static const struct pci_error_handlers ipr_err_handler = {
10589 .error_detected = ipr_pci_error_detected,
10590 .mmio_enabled = ipr_pci_mmio_enabled,
10591 .slot_reset = ipr_pci_slot_reset,
10592};
10593
10594static struct pci_driver ipr_driver = {
10595 .name = IPR_NAME,
10596 .id_table = ipr_pci_table,
10597 .probe = ipr_probe,
10598 .remove = ipr_remove,
10599 .shutdown = ipr_shutdown,
10600 .err_handler = &ipr_err_handler,
10601};
10602
10603
10604
10605
10606
10607
10608
10609static void ipr_halt_done(struct ipr_cmnd *ipr_cmd)
10610{
10611 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
10612}
10613
10614
10615
10616
10617
10618
10619
10620static int ipr_halt(struct notifier_block *nb, ulong event, void *buf)
10621{
10622 struct ipr_cmnd *ipr_cmd;
10623 struct ipr_ioa_cfg *ioa_cfg;
10624 unsigned long flags = 0, driver_lock_flags;
10625
10626 if (event != SYS_RESTART && event != SYS_HALT && event != SYS_POWER_OFF)
10627 return NOTIFY_DONE;
10628
10629 spin_lock_irqsave(&ipr_driver_lock, driver_lock_flags);
10630
10631 list_for_each_entry(ioa_cfg, &ipr_ioa_head, queue) {
10632 spin_lock_irqsave(ioa_cfg->host->host_lock, flags);
10633 if (!ioa_cfg->hrrq[IPR_INIT_HRRQ].allow_cmds ||
10634 (ipr_fast_reboot && event == SYS_RESTART && ioa_cfg->sis64)) {
10635 spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags);
10636 continue;
10637 }
10638
10639 ipr_cmd = ipr_get_free_ipr_cmnd(ioa_cfg);
10640 ipr_cmd->ioarcb.res_handle = cpu_to_be32(IPR_IOA_RES_HANDLE);
10641 ipr_cmd->ioarcb.cmd_pkt.request_type = IPR_RQTYPE_IOACMD;
10642 ipr_cmd->ioarcb.cmd_pkt.cdb[0] = IPR_IOA_SHUTDOWN;
10643 ipr_cmd->ioarcb.cmd_pkt.cdb[1] = IPR_SHUTDOWN_PREPARE_FOR_NORMAL;
10644
10645 ipr_do_req(ipr_cmd, ipr_halt_done, ipr_timeout, IPR_DEVICE_RESET_TIMEOUT);
10646 spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags);
10647 }
10648 spin_unlock_irqrestore(&ipr_driver_lock, driver_lock_flags);
10649
10650 return NOTIFY_OK;
10651}
10652
10653static struct notifier_block ipr_notifier = {
10654 ipr_halt, NULL, 0
10655};
10656
10657
10658
10659
10660
10661
10662
10663static int __init ipr_init(void)
10664{
10665 ipr_info("IBM Power RAID SCSI Device Driver version: %s %s\n",
10666 IPR_DRIVER_VERSION, IPR_DRIVER_DATE);
10667
10668 register_reboot_notifier(&ipr_notifier);
10669 return pci_register_driver(&ipr_driver);
10670}
10671
10672
10673
10674
10675
10676
10677
10678
10679
10680static void __exit ipr_exit(void)
10681{
10682 unregister_reboot_notifier(&ipr_notifier);
10683 pci_unregister_driver(&ipr_driver);
10684}
10685
10686module_init(ipr_init);
10687module_exit(ipr_exit);
10688
