linux/drivers/spi/spi-dw.h
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   1#ifndef DW_SPI_HEADER_H
   2#define DW_SPI_HEADER_H
   3
   4#include <linux/io.h>
   5#include <linux/scatterlist.h>
   6#include <linux/gpio.h>
   7
   8/* Register offsets */
   9#define DW_SPI_CTRL0                    0x00
  10#define DW_SPI_CTRL1                    0x04
  11#define DW_SPI_SSIENR                   0x08
  12#define DW_SPI_MWCR                     0x0c
  13#define DW_SPI_SER                      0x10
  14#define DW_SPI_BAUDR                    0x14
  15#define DW_SPI_TXFLTR                   0x18
  16#define DW_SPI_RXFLTR                   0x1c
  17#define DW_SPI_TXFLR                    0x20
  18#define DW_SPI_RXFLR                    0x24
  19#define DW_SPI_SR                       0x28
  20#define DW_SPI_IMR                      0x2c
  21#define DW_SPI_ISR                      0x30
  22#define DW_SPI_RISR                     0x34
  23#define DW_SPI_TXOICR                   0x38
  24#define DW_SPI_RXOICR                   0x3c
  25#define DW_SPI_RXUICR                   0x40
  26#define DW_SPI_MSTICR                   0x44
  27#define DW_SPI_ICR                      0x48
  28#define DW_SPI_DMACR                    0x4c
  29#define DW_SPI_DMATDLR                  0x50
  30#define DW_SPI_DMARDLR                  0x54
  31#define DW_SPI_IDR                      0x58
  32#define DW_SPI_VERSION                  0x5c
  33#define DW_SPI_DR                       0x60
  34
  35/* Bit fields in CTRLR0 */
  36#define SPI_DFS_OFFSET                  0
  37
  38#define SPI_FRF_OFFSET                  4
  39#define SPI_FRF_SPI                     0x0
  40#define SPI_FRF_SSP                     0x1
  41#define SPI_FRF_MICROWIRE               0x2
  42#define SPI_FRF_RESV                    0x3
  43
  44#define SPI_MODE_OFFSET                 6
  45#define SPI_SCPH_OFFSET                 6
  46#define SPI_SCOL_OFFSET                 7
  47
  48#define SPI_TMOD_OFFSET                 8
  49#define SPI_TMOD_MASK                   (0x3 << SPI_TMOD_OFFSET)
  50#define SPI_TMOD_TR                     0x0             /* xmit & recv */
  51#define SPI_TMOD_TO                     0x1             /* xmit only */
  52#define SPI_TMOD_RO                     0x2             /* recv only */
  53#define SPI_TMOD_EPROMREAD              0x3             /* eeprom read mode */
  54
  55#define SPI_SLVOE_OFFSET                10
  56#define SPI_SRL_OFFSET                  11
  57#define SPI_CFS_OFFSET                  12
  58
  59/* Bit fields in SR, 7 bits */
  60#define SR_MASK                         0x7f            /* cover 7 bits */
  61#define SR_BUSY                         (1 << 0)
  62#define SR_TF_NOT_FULL                  (1 << 1)
  63#define SR_TF_EMPT                      (1 << 2)
  64#define SR_RF_NOT_EMPT                  (1 << 3)
  65#define SR_RF_FULL                      (1 << 4)
  66#define SR_TX_ERR                       (1 << 5)
  67#define SR_DCOL                         (1 << 6)
  68
  69/* Bit fields in ISR, IMR, RISR, 7 bits */
  70#define SPI_INT_TXEI                    (1 << 0)
  71#define SPI_INT_TXOI                    (1 << 1)
  72#define SPI_INT_RXUI                    (1 << 2)
  73#define SPI_INT_RXOI                    (1 << 3)
  74#define SPI_INT_RXFI                    (1 << 4)
  75#define SPI_INT_MSTI                    (1 << 5)
  76
  77/* Bit fields in DMACR */
  78#define SPI_DMA_RDMAE                   (1 << 0)
  79#define SPI_DMA_TDMAE                   (1 << 1)
  80
  81/* TX RX interrupt level threshold, max can be 256 */
  82#define SPI_INT_THRESHOLD               32
  83
  84enum dw_ssi_type {
  85        SSI_MOTO_SPI = 0,
  86        SSI_TI_SSP,
  87        SSI_NS_MICROWIRE,
  88};
  89
  90struct dw_spi;
  91struct dw_spi_dma_ops {
  92        int (*dma_init)(struct dw_spi *dws);
  93        void (*dma_exit)(struct dw_spi *dws);
  94        int (*dma_setup)(struct dw_spi *dws, struct spi_transfer *xfer);
  95        bool (*can_dma)(struct spi_master *master, struct spi_device *spi,
  96                        struct spi_transfer *xfer);
  97        int (*dma_transfer)(struct dw_spi *dws, struct spi_transfer *xfer);
  98        void (*dma_stop)(struct dw_spi *dws);
  99};
 100
 101struct dw_spi {
 102        struct spi_master       *master;
 103        enum dw_ssi_type        type;
 104        char                    name[16];
 105
 106        void __iomem            *regs;
 107        unsigned long           paddr;
 108        int                     irq;
 109        u32                     fifo_len;       /* depth of the FIFO buffer */
 110        u32                     max_freq;       /* max bus freq supported */
 111
 112        u32                     reg_io_width;   /* DR I/O width in bytes */
 113        u16                     bus_num;
 114        u16                     num_cs;         /* supported slave numbers */
 115
 116        /* Current message transfer state info */
 117        size_t                  len;
 118        void                    *tx;
 119        void                    *tx_end;
 120        void                    *rx;
 121        void                    *rx_end;
 122        int                     dma_mapped;
 123        u8                      n_bytes;        /* current is a 1/2 bytes op */
 124        u32                     dma_width;
 125        irqreturn_t             (*transfer_handler)(struct dw_spi *dws);
 126
 127        /* DMA info */
 128        int                     dma_inited;
 129        struct dma_chan         *txchan;
 130        struct dma_chan         *rxchan;
 131        unsigned long           dma_chan_busy;
 132        dma_addr_t              dma_addr; /* phy address of the Data register */
 133        const struct dw_spi_dma_ops *dma_ops;
 134        void                    *dma_tx;
 135        void                    *dma_rx;
 136
 137        /* Bus interface info */
 138        void                    *priv;
 139#ifdef CONFIG_DEBUG_FS
 140        struct dentry *debugfs;
 141#endif
 142};
 143
 144static inline u32 dw_readl(struct dw_spi *dws, u32 offset)
 145{
 146        return __raw_readl(dws->regs + offset);
 147}
 148
 149static inline u16 dw_readw(struct dw_spi *dws, u32 offset)
 150{
 151        return __raw_readw(dws->regs + offset);
 152}
 153
 154static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val)
 155{
 156        __raw_writel(val, dws->regs + offset);
 157}
 158
 159static inline void dw_writew(struct dw_spi *dws, u32 offset, u16 val)
 160{
 161        __raw_writew(val, dws->regs + offset);
 162}
 163
 164static inline u32 dw_read_io_reg(struct dw_spi *dws, u32 offset)
 165{
 166        switch (dws->reg_io_width) {
 167        case 2:
 168                return dw_readw(dws, offset);
 169        case 4:
 170        default:
 171                return dw_readl(dws, offset);
 172        }
 173}
 174
 175static inline void dw_write_io_reg(struct dw_spi *dws, u32 offset, u32 val)
 176{
 177        switch (dws->reg_io_width) {
 178        case 2:
 179                dw_writew(dws, offset, val);
 180                break;
 181        case 4:
 182        default:
 183                dw_writel(dws, offset, val);
 184                break;
 185        }
 186}
 187
 188static inline void spi_enable_chip(struct dw_spi *dws, int enable)
 189{
 190        dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0));
 191}
 192
 193static inline void spi_set_clk(struct dw_spi *dws, u16 div)
 194{
 195        dw_writel(dws, DW_SPI_BAUDR, div);
 196}
 197
 198/* Disable IRQ bits */
 199static inline void spi_mask_intr(struct dw_spi *dws, u32 mask)
 200{
 201        u32 new_mask;
 202
 203        new_mask = dw_readl(dws, DW_SPI_IMR) & ~mask;
 204        dw_writel(dws, DW_SPI_IMR, new_mask);
 205}
 206
 207/* Enable IRQ bits */
 208static inline void spi_umask_intr(struct dw_spi *dws, u32 mask)
 209{
 210        u32 new_mask;
 211
 212        new_mask = dw_readl(dws, DW_SPI_IMR) | mask;
 213        dw_writel(dws, DW_SPI_IMR, new_mask);
 214}
 215
 216/*
 217 * This does disable the SPI controller, interrupts, and re-enable the
 218 * controller back. Transmit and receive FIFO buffers are cleared when the
 219 * device is disabled.
 220 */
 221static inline void spi_reset_chip(struct dw_spi *dws)
 222{
 223        spi_enable_chip(dws, 0);
 224        spi_mask_intr(dws, 0xff);
 225        spi_enable_chip(dws, 1);
 226}
 227
 228static inline void spi_shutdown_chip(struct dw_spi *dws)
 229{
 230        spi_enable_chip(dws, 0);
 231        spi_set_clk(dws, 0);
 232}
 233
 234/*
 235 * Each SPI slave device to work with dw_api controller should
 236 * has such a structure claiming its working mode (poll or PIO/DMA),
 237 * which can be save in the "controller_data" member of the
 238 * struct spi_device.
 239 */
 240struct dw_spi_chip {
 241        u8 poll_mode;   /* 1 for controller polling mode */
 242        u8 type;        /* SPI/SSP/MicroWire */
 243        void (*cs_control)(u32 command);
 244};
 245
 246extern int dw_spi_add_host(struct device *dev, struct dw_spi *dws);
 247extern void dw_spi_remove_host(struct dw_spi *dws);
 248extern int dw_spi_suspend_host(struct dw_spi *dws);
 249extern int dw_spi_resume_host(struct dw_spi *dws);
 250
 251/* platform related setup */
 252extern int dw_spi_mid_init(struct dw_spi *dws); /* Intel MID platforms */
 253#endif /* DW_SPI_HEADER_H */
 254
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