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110#include <linux/module.h>
111#include <linux/delay.h>
112
113#include "../comedi_pci.h"
114
115#include <asm/byteorder.h>
116
117#include "ni_stc.h"
118#include "mite.h"
119
120#define PCIDMA
121
122
123
124
125
126
127
128
129static const struct comedi_lrange range_ni_M_628x_ao = {
130 8, {
131 BIP_RANGE(10),
132 BIP_RANGE(5),
133 BIP_RANGE(2),
134 BIP_RANGE(1),
135 RANGE(-5, 15),
136 UNI_RANGE(10),
137 RANGE(3, 7),
138 RANGE(4, 6),
139 RANGE_ext(-1, 1)
140 }
141};
142
143static const struct comedi_lrange range_ni_M_625x_ao = {
144 3, {
145 BIP_RANGE(10),
146 BIP_RANGE(5),
147 RANGE_ext(-1, 1)
148 }
149};
150
151enum ni_pcimio_boardid {
152 BOARD_PCIMIO_16XE_50,
153 BOARD_PCIMIO_16XE_10,
154 BOARD_PCI6014,
155 BOARD_PXI6030E,
156 BOARD_PCIMIO_16E_1,
157 BOARD_PCIMIO_16E_4,
158 BOARD_PXI6040E,
159 BOARD_PCI6031E,
160 BOARD_PCI6032E,
161 BOARD_PCI6033E,
162 BOARD_PCI6071E,
163 BOARD_PCI6023E,
164 BOARD_PCI6024E,
165 BOARD_PCI6025E,
166 BOARD_PXI6025E,
167 BOARD_PCI6034E,
168 BOARD_PCI6035E,
169 BOARD_PCI6052E,
170 BOARD_PCI6110,
171 BOARD_PCI6111,
172
173
174 BOARD_PCI6711,
175 BOARD_PXI6711,
176 BOARD_PCI6713,
177 BOARD_PXI6713,
178 BOARD_PCI6731,
179
180 BOARD_PCI6733,
181 BOARD_PXI6733,
182 BOARD_PXI6071E,
183 BOARD_PXI6070E,
184 BOARD_PXI6052E,
185 BOARD_PXI6031E,
186 BOARD_PCI6036E,
187 BOARD_PCI6220,
188 BOARD_PCI6221,
189 BOARD_PCI6221_37PIN,
190 BOARD_PCI6224,
191 BOARD_PXI6224,
192 BOARD_PCI6225,
193 BOARD_PXI6225,
194 BOARD_PCI6229,
195 BOARD_PCI6250,
196 BOARD_PCI6251,
197 BOARD_PXI6251,
198 BOARD_PCIE6251,
199 BOARD_PXIE6251,
200 BOARD_PCI6254,
201 BOARD_PCI6259,
202 BOARD_PCIE6259,
203 BOARD_PCI6280,
204 BOARD_PCI6281,
205 BOARD_PXI6281,
206 BOARD_PCI6284,
207 BOARD_PCI6289,
208 BOARD_PCI6143,
209 BOARD_PXI6143,
210};
211
212static const struct ni_board_struct ni_boards[] = {
213 [BOARD_PCIMIO_16XE_50] = {
214 .name = "pci-mio-16xe-50",
215 .n_adchan = 16,
216 .ai_maxdata = 0xffff,
217 .ai_fifo_depth = 2048,
218 .alwaysdither = 1,
219 .gainlkup = ai_gain_8,
220 .ai_speed = 50000,
221 .n_aochan = 2,
222 .ao_maxdata = 0x0fff,
223 .ao_range_table = &range_bipolar10,
224 .ao_speed = 50000,
225 .caldac = { dac8800, dac8043 },
226 },
227 [BOARD_PCIMIO_16XE_10] = {
228 .name = "pci-mio-16xe-10",
229 .n_adchan = 16,
230 .ai_maxdata = 0xffff,
231 .ai_fifo_depth = 512,
232 .alwaysdither = 1,
233 .gainlkup = ai_gain_14,
234 .ai_speed = 10000,
235 .n_aochan = 2,
236 .ao_maxdata = 0xffff,
237 .ao_fifo_depth = 2048,
238 .ao_range_table = &range_ni_E_ao_ext,
239 .ao_speed = 10000,
240 .caldac = { dac8800, dac8043, ad8522 },
241 },
242 [BOARD_PCI6014] = {
243 .name = "pci-6014",
244 .n_adchan = 16,
245 .ai_maxdata = 0xffff,
246 .ai_fifo_depth = 512,
247 .alwaysdither = 1,
248 .gainlkup = ai_gain_4,
249 .ai_speed = 5000,
250 .n_aochan = 2,
251 .ao_maxdata = 0xffff,
252 .ao_range_table = &range_bipolar10,
253 .ao_speed = 100000,
254 .caldac = { ad8804_debug },
255 },
256 [BOARD_PXI6030E] = {
257 .name = "pxi-6030e",
258 .n_adchan = 16,
259 .ai_maxdata = 0xffff,
260 .ai_fifo_depth = 512,
261 .alwaysdither = 1,
262 .gainlkup = ai_gain_14,
263 .ai_speed = 10000,
264 .n_aochan = 2,
265 .ao_maxdata = 0xffff,
266 .ao_fifo_depth = 2048,
267 .ao_range_table = &range_ni_E_ao_ext,
268 .ao_speed = 10000,
269 .caldac = { dac8800, dac8043, ad8522 },
270 },
271 [BOARD_PCIMIO_16E_1] = {
272 .name = "pci-mio-16e-1",
273 .n_adchan = 16,
274 .ai_maxdata = 0x0fff,
275 .ai_fifo_depth = 512,
276 .gainlkup = ai_gain_16,
277 .ai_speed = 800,
278 .n_aochan = 2,
279 .ao_maxdata = 0x0fff,
280 .ao_fifo_depth = 2048,
281 .ao_range_table = &range_ni_E_ao_ext,
282 .ao_speed = 1000,
283 .caldac = { mb88341 },
284 },
285 [BOARD_PCIMIO_16E_4] = {
286 .name = "pci-mio-16e-4",
287 .n_adchan = 16,
288 .ai_maxdata = 0x0fff,
289 .ai_fifo_depth = 512,
290 .gainlkup = ai_gain_16,
291
292
293
294
295 .ai_speed = 2000,
296 .n_aochan = 2,
297 .ao_maxdata = 0x0fff,
298 .ao_fifo_depth = 512,
299 .ao_range_table = &range_ni_E_ao_ext,
300 .ao_speed = 1000,
301 .caldac = { ad8804_debug },
302 },
303 [BOARD_PXI6040E] = {
304 .name = "pxi-6040e",
305 .n_adchan = 16,
306 .ai_maxdata = 0x0fff,
307 .ai_fifo_depth = 512,
308 .gainlkup = ai_gain_16,
309 .ai_speed = 2000,
310 .n_aochan = 2,
311 .ao_maxdata = 0x0fff,
312 .ao_fifo_depth = 512,
313 .ao_range_table = &range_ni_E_ao_ext,
314 .ao_speed = 1000,
315 .caldac = { mb88341 },
316 },
317 [BOARD_PCI6031E] = {
318 .name = "pci-6031e",
319 .n_adchan = 64,
320 .ai_maxdata = 0xffff,
321 .ai_fifo_depth = 512,
322 .alwaysdither = 1,
323 .gainlkup = ai_gain_14,
324 .ai_speed = 10000,
325 .n_aochan = 2,
326 .ao_maxdata = 0xffff,
327 .ao_fifo_depth = 2048,
328 .ao_range_table = &range_ni_E_ao_ext,
329 .ao_speed = 10000,
330 .caldac = { dac8800, dac8043, ad8522 },
331 },
332 [BOARD_PCI6032E] = {
333 .name = "pci-6032e",
334 .n_adchan = 16,
335 .ai_maxdata = 0xffff,
336 .ai_fifo_depth = 512,
337 .alwaysdither = 1,
338 .gainlkup = ai_gain_14,
339 .ai_speed = 10000,
340 .caldac = { dac8800, dac8043, ad8522 },
341 },
342 [BOARD_PCI6033E] = {
343 .name = "pci-6033e",
344 .n_adchan = 64,
345 .ai_maxdata = 0xffff,
346 .ai_fifo_depth = 512,
347 .alwaysdither = 1,
348 .gainlkup = ai_gain_14,
349 .ai_speed = 10000,
350 .caldac = { dac8800, dac8043, ad8522 },
351 },
352 [BOARD_PCI6071E] = {
353 .name = "pci-6071e",
354 .n_adchan = 64,
355 .ai_maxdata = 0x0fff,
356 .ai_fifo_depth = 512,
357 .alwaysdither = 1,
358 .gainlkup = ai_gain_16,
359 .ai_speed = 800,
360 .n_aochan = 2,
361 .ao_maxdata = 0x0fff,
362 .ao_fifo_depth = 2048,
363 .ao_range_table = &range_ni_E_ao_ext,
364 .ao_speed = 1000,
365 .caldac = { ad8804_debug },
366 },
367 [BOARD_PCI6023E] = {
368 .name = "pci-6023e",
369 .n_adchan = 16,
370 .ai_maxdata = 0x0fff,
371 .ai_fifo_depth = 512,
372 .gainlkup = ai_gain_4,
373 .ai_speed = 5000,
374 .caldac = { ad8804_debug },
375 },
376 [BOARD_PCI6024E] = {
377 .name = "pci-6024e",
378 .n_adchan = 16,
379 .ai_maxdata = 0x0fff,
380 .ai_fifo_depth = 512,
381 .gainlkup = ai_gain_4,
382 .ai_speed = 5000,
383 .n_aochan = 2,
384 .ao_maxdata = 0x0fff,
385 .ao_range_table = &range_bipolar10,
386 .ao_speed = 100000,
387 .caldac = { ad8804_debug },
388 },
389 [BOARD_PCI6025E] = {
390 .name = "pci-6025e",
391 .n_adchan = 16,
392 .ai_maxdata = 0x0fff,
393 .ai_fifo_depth = 512,
394 .gainlkup = ai_gain_4,
395 .ai_speed = 5000,
396 .n_aochan = 2,
397 .ao_maxdata = 0x0fff,
398 .ao_range_table = &range_bipolar10,
399 .ao_speed = 100000,
400 .caldac = { ad8804_debug },
401 .has_8255 = 1,
402 },
403 [BOARD_PXI6025E] = {
404 .name = "pxi-6025e",
405 .n_adchan = 16,
406 .ai_maxdata = 0x0fff,
407 .ai_fifo_depth = 512,
408 .gainlkup = ai_gain_4,
409 .ai_speed = 5000,
410 .n_aochan = 2,
411 .ao_maxdata = 0x0fff,
412 .ao_range_table = &range_ni_E_ao_ext,
413 .ao_speed = 100000,
414 .caldac = { ad8804_debug },
415 .has_8255 = 1,
416 },
417 [BOARD_PCI6034E] = {
418 .name = "pci-6034e",
419 .n_adchan = 16,
420 .ai_maxdata = 0xffff,
421 .ai_fifo_depth = 512,
422 .alwaysdither = 1,
423 .gainlkup = ai_gain_4,
424 .ai_speed = 5000,
425 .caldac = { ad8804_debug },
426 },
427 [BOARD_PCI6035E] = {
428 .name = "pci-6035e",
429 .n_adchan = 16,
430 .ai_maxdata = 0xffff,
431 .ai_fifo_depth = 512,
432 .alwaysdither = 1,
433 .gainlkup = ai_gain_4,
434 .ai_speed = 5000,
435 .n_aochan = 2,
436 .ao_maxdata = 0x0fff,
437 .ao_range_table = &range_bipolar10,
438 .ao_speed = 100000,
439 .caldac = { ad8804_debug },
440 },
441 [BOARD_PCI6052E] = {
442 .name = "pci-6052e",
443 .n_adchan = 16,
444 .ai_maxdata = 0xffff,
445 .ai_fifo_depth = 512,
446 .alwaysdither = 1,
447 .gainlkup = ai_gain_16,
448 .ai_speed = 3000,
449 .n_aochan = 2,
450 .ao_maxdata = 0xffff,
451 .ao_fifo_depth = 2048,
452 .ao_range_table = &range_ni_E_ao_ext,
453 .ao_speed = 3000,
454
455 .caldac = { ad8804_debug, ad8804_debug, ad8522 },
456 },
457 [BOARD_PCI6110] = {
458 .name = "pci-6110",
459 .n_adchan = 4,
460 .ai_maxdata = 0x0fff,
461 .ai_fifo_depth = 8192,
462 .alwaysdither = 0,
463 .gainlkup = ai_gain_611x,
464 .ai_speed = 200,
465 .n_aochan = 2,
466 .ao_maxdata = 0xffff,
467 .reg_type = ni_reg_611x,
468 .ao_range_table = &range_bipolar10,
469 .ao_fifo_depth = 2048,
470 .ao_speed = 250,
471 .caldac = { ad8804, ad8804 },
472 },
473 [BOARD_PCI6111] = {
474 .name = "pci-6111",
475 .n_adchan = 2,
476 .ai_maxdata = 0x0fff,
477 .ai_fifo_depth = 8192,
478 .gainlkup = ai_gain_611x,
479 .ai_speed = 200,
480 .n_aochan = 2,
481 .ao_maxdata = 0xffff,
482 .reg_type = ni_reg_611x,
483 .ao_range_table = &range_bipolar10,
484 .ao_fifo_depth = 2048,
485 .ao_speed = 250,
486 .caldac = { ad8804, ad8804 },
487 },
488#if 0
489
490 [BOARD_PCI6115] = {
491 .name = "pci-6115",
492 .n_adchan = 4,
493 .ai_maxdata = 0x0fff,
494 .ai_fifo_depth = 8192,
495 .gainlkup = ai_gain_611x,
496 .ai_speed = 100,
497 .n_aochan = 2,
498 .ao_maxdata = 0xffff,
499 .ao_671x = 1,
500 .ao_fifo_depth = 2048,
501 .ao_speed = 250,
502 .reg_611x = 1,
503
504 .caldac = { ad8804_debug, ad8804_debug, ad8804_debug },
505 },
506#endif
507#if 0
508 [BOARD_PXI6115] = {
509 .name = "pxi-6115",
510 .n_adchan = 4,
511 .ai_maxdata = 0x0fff,
512 .ai_fifo_depth = 8192,
513 .gainlkup = ai_gain_611x,
514 .ai_speed = 100,
515 .n_aochan = 2,
516 .ao_maxdata = 0xffff,
517 .ao_671x = 1,
518 .ao_fifo_depth = 2048,
519 .ao_speed = 250,
520 .reg_611x = 1,
521
522 .caldac = { ad8804_debug, ad8804_debug, ad8804_debug },
523 },
524#endif
525 [BOARD_PCI6711] = {
526 .name = "pci-6711",
527 .n_aochan = 4,
528 .ao_maxdata = 0x0fff,
529
530 .ao_fifo_depth = 16384,
531 .ao_range_table = &range_bipolar10,
532 .ao_speed = 1000,
533 .reg_type = ni_reg_6711,
534 .caldac = { ad8804_debug },
535 },
536 [BOARD_PXI6711] = {
537 .name = "pxi-6711",
538 .n_aochan = 4,
539 .ao_maxdata = 0x0fff,
540 .ao_fifo_depth = 16384,
541 .ao_range_table = &range_bipolar10,
542 .ao_speed = 1000,
543 .reg_type = ni_reg_6711,
544 .caldac = { ad8804_debug },
545 },
546 [BOARD_PCI6713] = {
547 .name = "pci-6713",
548 .n_aochan = 8,
549 .ao_maxdata = 0x0fff,
550 .ao_fifo_depth = 16384,
551 .ao_range_table = &range_bipolar10,
552 .ao_speed = 1000,
553 .reg_type = ni_reg_6713,
554 .caldac = { ad8804_debug, ad8804_debug },
555 },
556 [BOARD_PXI6713] = {
557 .name = "pxi-6713",
558 .n_aochan = 8,
559 .ao_maxdata = 0x0fff,
560 .ao_fifo_depth = 16384,
561 .ao_range_table = &range_bipolar10,
562 .ao_speed = 1000,
563 .reg_type = ni_reg_6713,
564 .caldac = { ad8804_debug, ad8804_debug },
565 },
566 [BOARD_PCI6731] = {
567 .name = "pci-6731",
568 .n_aochan = 4,
569 .ao_maxdata = 0xffff,
570 .ao_fifo_depth = 8192,
571 .ao_range_table = &range_bipolar10,
572 .ao_speed = 1000,
573 .reg_type = ni_reg_6711,
574 .caldac = { ad8804_debug },
575 },
576#if 0
577 [BOARD_PXI6731] = {
578 .name = "pxi-6731",
579 .n_aochan = 4,
580 .ao_maxdata = 0xffff,
581 .ao_fifo_depth = 8192,
582 .ao_range_table = &range_bipolar10,
583 .reg_type = ni_reg_6711,
584 .caldac = { ad8804_debug },
585 },
586#endif
587 [BOARD_PCI6733] = {
588 .name = "pci-6733",
589 .n_aochan = 8,
590 .ao_maxdata = 0xffff,
591 .ao_fifo_depth = 16384,
592 .ao_range_table = &range_bipolar10,
593 .ao_speed = 1000,
594 .reg_type = ni_reg_6713,
595 .caldac = { ad8804_debug, ad8804_debug },
596 },
597 [BOARD_PXI6733] = {
598 .name = "pxi-6733",
599 .n_aochan = 8,
600 .ao_maxdata = 0xffff,
601 .ao_fifo_depth = 16384,
602 .ao_range_table = &range_bipolar10,
603 .ao_speed = 1000,
604 .reg_type = ni_reg_6713,
605 .caldac = { ad8804_debug, ad8804_debug },
606 },
607 [BOARD_PXI6071E] = {
608 .name = "pxi-6071e",
609 .n_adchan = 64,
610 .ai_maxdata = 0x0fff,
611 .ai_fifo_depth = 512,
612 .alwaysdither = 1,
613 .gainlkup = ai_gain_16,
614 .ai_speed = 800,
615 .n_aochan = 2,
616 .ao_maxdata = 0x0fff,
617 .ao_fifo_depth = 2048,
618 .ao_range_table = &range_ni_E_ao_ext,
619 .ao_speed = 1000,
620 .caldac = { ad8804_debug },
621 },
622 [BOARD_PXI6070E] = {
623 .name = "pxi-6070e",
624 .n_adchan = 16,
625 .ai_maxdata = 0x0fff,
626 .ai_fifo_depth = 512,
627 .alwaysdither = 1,
628 .gainlkup = ai_gain_16,
629 .ai_speed = 800,
630 .n_aochan = 2,
631 .ao_maxdata = 0x0fff,
632 .ao_fifo_depth = 2048,
633 .ao_range_table = &range_ni_E_ao_ext,
634 .ao_speed = 1000,
635 .caldac = { ad8804_debug },
636 },
637 [BOARD_PXI6052E] = {
638 .name = "pxi-6052e",
639 .n_adchan = 16,
640 .ai_maxdata = 0xffff,
641 .ai_fifo_depth = 512,
642 .alwaysdither = 1,
643 .gainlkup = ai_gain_16,
644 .ai_speed = 3000,
645 .n_aochan = 2,
646 .ao_maxdata = 0xffff,
647 .ao_fifo_depth = 2048,
648 .ao_range_table = &range_ni_E_ao_ext,
649 .ao_speed = 3000,
650 .caldac = { mb88341, mb88341, ad8522 },
651 },
652 [BOARD_PXI6031E] = {
653 .name = "pxi-6031e",
654 .n_adchan = 64,
655 .ai_maxdata = 0xffff,
656 .ai_fifo_depth = 512,
657 .alwaysdither = 1,
658 .gainlkup = ai_gain_14,
659 .ai_speed = 10000,
660 .n_aochan = 2,
661 .ao_maxdata = 0xffff,
662 .ao_fifo_depth = 2048,
663 .ao_range_table = &range_ni_E_ao_ext,
664 .ao_speed = 10000,
665 .caldac = { dac8800, dac8043, ad8522 },
666 },
667 [BOARD_PCI6036E] = {
668 .name = "pci-6036e",
669 .n_adchan = 16,
670 .ai_maxdata = 0xffff,
671 .ai_fifo_depth = 512,
672 .alwaysdither = 1,
673 .gainlkup = ai_gain_4,
674 .ai_speed = 5000,
675 .n_aochan = 2,
676 .ao_maxdata = 0xffff,
677 .ao_range_table = &range_bipolar10,
678 .ao_speed = 100000,
679 .caldac = { ad8804_debug },
680 },
681 [BOARD_PCI6220] = {
682 .name = "pci-6220",
683 .n_adchan = 16,
684 .ai_maxdata = 0xffff,
685 .ai_fifo_depth = 512,
686 .gainlkup = ai_gain_622x,
687 .ai_speed = 4000,
688 .reg_type = ni_reg_622x,
689 .caldac = { caldac_none },
690 },
691 [BOARD_PCI6221] = {
692 .name = "pci-6221",
693 .n_adchan = 16,
694 .ai_maxdata = 0xffff,
695 .ai_fifo_depth = 4095,
696 .gainlkup = ai_gain_622x,
697 .ai_speed = 4000,
698 .n_aochan = 2,
699 .ao_maxdata = 0xffff,
700 .ao_fifo_depth = 8191,
701 .ao_range_table = &range_bipolar10,
702 .reg_type = ni_reg_622x,
703 .ao_speed = 1200,
704 .caldac = { caldac_none },
705 },
706 [BOARD_PCI6221_37PIN] = {
707 .name = "pci-6221_37pin",
708 .n_adchan = 16,
709 .ai_maxdata = 0xffff,
710 .ai_fifo_depth = 4095,
711 .gainlkup = ai_gain_622x,
712 .ai_speed = 4000,
713 .n_aochan = 2,
714 .ao_maxdata = 0xffff,
715 .ao_fifo_depth = 8191,
716 .ao_range_table = &range_bipolar10,
717 .reg_type = ni_reg_622x,
718 .ao_speed = 1200,
719 .caldac = { caldac_none },
720 },
721 [BOARD_PCI6224] = {
722 .name = "pci-6224",
723 .n_adchan = 32,
724 .ai_maxdata = 0xffff,
725 .ai_fifo_depth = 4095,
726 .gainlkup = ai_gain_622x,
727 .ai_speed = 4000,
728 .reg_type = ni_reg_622x,
729 .has_32dio_chan = 1,
730 .caldac = { caldac_none },
731 },
732 [BOARD_PXI6224] = {
733 .name = "pxi-6224",
734 .n_adchan = 32,
735 .ai_maxdata = 0xffff,
736 .ai_fifo_depth = 4095,
737 .gainlkup = ai_gain_622x,
738 .ai_speed = 4000,
739 .reg_type = ni_reg_622x,
740 .has_32dio_chan = 1,
741 .caldac = { caldac_none },
742 },
743 [BOARD_PCI6225] = {
744 .name = "pci-6225",
745 .n_adchan = 80,
746 .ai_maxdata = 0xffff,
747 .ai_fifo_depth = 4095,
748 .gainlkup = ai_gain_622x,
749 .ai_speed = 4000,
750 .n_aochan = 2,
751 .ao_maxdata = 0xffff,
752 .ao_fifo_depth = 8191,
753 .ao_range_table = &range_bipolar10,
754 .reg_type = ni_reg_622x,
755 .ao_speed = 1200,
756 .has_32dio_chan = 1,
757 .caldac = { caldac_none },
758 },
759 [BOARD_PXI6225] = {
760 .name = "pxi-6225",
761 .n_adchan = 80,
762 .ai_maxdata = 0xffff,
763 .ai_fifo_depth = 4095,
764 .gainlkup = ai_gain_622x,
765 .ai_speed = 4000,
766 .n_aochan = 2,
767 .ao_maxdata = 0xffff,
768 .ao_fifo_depth = 8191,
769 .ao_range_table = &range_bipolar10,
770 .reg_type = ni_reg_622x,
771 .ao_speed = 1200,
772 .has_32dio_chan = 1,
773 .caldac = { caldac_none },
774 },
775 [BOARD_PCI6229] = {
776 .name = "pci-6229",
777 .n_adchan = 32,
778 .ai_maxdata = 0xffff,
779 .ai_fifo_depth = 4095,
780 .gainlkup = ai_gain_622x,
781 .ai_speed = 4000,
782 .n_aochan = 4,
783 .ao_maxdata = 0xffff,
784 .ao_fifo_depth = 8191,
785 .ao_range_table = &range_bipolar10,
786 .reg_type = ni_reg_622x,
787 .ao_speed = 1200,
788 .has_32dio_chan = 1,
789 .caldac = { caldac_none },
790 },
791 [BOARD_PCI6250] = {
792 .name = "pci-6250",
793 .n_adchan = 16,
794 .ai_maxdata = 0xffff,
795 .ai_fifo_depth = 4095,
796 .gainlkup = ai_gain_628x,
797 .ai_speed = 800,
798 .reg_type = ni_reg_625x,
799 .caldac = { caldac_none },
800 },
801 [BOARD_PCI6251] = {
802 .name = "pci-6251",
803 .n_adchan = 16,
804 .ai_maxdata = 0xffff,
805 .ai_fifo_depth = 4095,
806 .gainlkup = ai_gain_628x,
807 .ai_speed = 800,
808 .n_aochan = 2,
809 .ao_maxdata = 0xffff,
810 .ao_fifo_depth = 8191,
811 .ao_range_table = &range_ni_M_625x_ao,
812 .reg_type = ni_reg_625x,
813 .ao_speed = 350,
814 .caldac = { caldac_none },
815 },
816 [BOARD_PXI6251] = {
817 .name = "pxi-6251",
818 .n_adchan = 16,
819 .ai_maxdata = 0xffff,
820 .ai_fifo_depth = 4095,
821 .gainlkup = ai_gain_628x,
822 .ai_speed = 800,
823 .n_aochan = 2,
824 .ao_maxdata = 0xffff,
825 .ao_fifo_depth = 8191,
826 .ao_range_table = &range_ni_M_625x_ao,
827 .reg_type = ni_reg_625x,
828 .ao_speed = 350,
829 .caldac = { caldac_none },
830 },
831 [BOARD_PCIE6251] = {
832 .name = "pcie-6251",
833 .n_adchan = 16,
834 .ai_maxdata = 0xffff,
835 .ai_fifo_depth = 4095,
836 .gainlkup = ai_gain_628x,
837 .ai_speed = 800,
838 .n_aochan = 2,
839 .ao_maxdata = 0xffff,
840 .ao_fifo_depth = 8191,
841 .ao_range_table = &range_ni_M_625x_ao,
842 .reg_type = ni_reg_625x,
843 .ao_speed = 350,
844 .caldac = { caldac_none },
845 },
846 [BOARD_PXIE6251] = {
847 .name = "pxie-6251",
848 .n_adchan = 16,
849 .ai_maxdata = 0xffff,
850 .ai_fifo_depth = 4095,
851 .gainlkup = ai_gain_628x,
852 .ai_speed = 800,
853 .n_aochan = 2,
854 .ao_maxdata = 0xffff,
855 .ao_fifo_depth = 8191,
856 .ao_range_table = &range_ni_M_625x_ao,
857 .reg_type = ni_reg_625x,
858 .ao_speed = 350,
859 .caldac = { caldac_none },
860 },
861 [BOARD_PCI6254] = {
862 .name = "pci-6254",
863 .n_adchan = 32,
864 .ai_maxdata = 0xffff,
865 .ai_fifo_depth = 4095,
866 .gainlkup = ai_gain_628x,
867 .ai_speed = 800,
868 .reg_type = ni_reg_625x,
869 .has_32dio_chan = 1,
870 .caldac = { caldac_none },
871 },
872 [BOARD_PCI6259] = {
873 .name = "pci-6259",
874 .n_adchan = 32,
875 .ai_maxdata = 0xffff,
876 .ai_fifo_depth = 4095,
877 .gainlkup = ai_gain_628x,
878 .ai_speed = 800,
879 .n_aochan = 4,
880 .ao_maxdata = 0xffff,
881 .ao_fifo_depth = 8191,
882 .ao_range_table = &range_ni_M_625x_ao,
883 .reg_type = ni_reg_625x,
884 .ao_speed = 350,
885 .has_32dio_chan = 1,
886 .caldac = { caldac_none },
887 },
888 [BOARD_PCIE6259] = {
889 .name = "pcie-6259",
890 .n_adchan = 32,
891 .ai_maxdata = 0xffff,
892 .ai_fifo_depth = 4095,
893 .gainlkup = ai_gain_628x,
894 .ai_speed = 800,
895 .n_aochan = 4,
896 .ao_maxdata = 0xffff,
897 .ao_fifo_depth = 8191,
898 .ao_range_table = &range_ni_M_625x_ao,
899 .reg_type = ni_reg_625x,
900 .ao_speed = 350,
901 .has_32dio_chan = 1,
902 .caldac = { caldac_none },
903 },
904 [BOARD_PCI6280] = {
905 .name = "pci-6280",
906 .n_adchan = 16,
907 .ai_maxdata = 0x3ffff,
908 .ai_fifo_depth = 2047,
909 .gainlkup = ai_gain_628x,
910 .ai_speed = 1600,
911 .ao_fifo_depth = 8191,
912 .reg_type = ni_reg_628x,
913 .caldac = { caldac_none },
914 },
915 [BOARD_PCI6281] = {
916 .name = "pci-6281",
917 .n_adchan = 16,
918 .ai_maxdata = 0x3ffff,
919 .ai_fifo_depth = 2047,
920 .gainlkup = ai_gain_628x,
921 .ai_speed = 1600,
922 .n_aochan = 2,
923 .ao_maxdata = 0xffff,
924 .ao_fifo_depth = 8191,
925 .ao_range_table = &range_ni_M_628x_ao,
926 .reg_type = ni_reg_628x,
927 .ao_speed = 350,
928 .caldac = { caldac_none },
929 },
930 [BOARD_PXI6281] = {
931 .name = "pxi-6281",
932 .n_adchan = 16,
933 .ai_maxdata = 0x3ffff,
934 .ai_fifo_depth = 2047,
935 .gainlkup = ai_gain_628x,
936 .ai_speed = 1600,
937 .n_aochan = 2,
938 .ao_maxdata = 0xffff,
939 .ao_fifo_depth = 8191,
940 .ao_range_table = &range_ni_M_628x_ao,
941 .reg_type = ni_reg_628x,
942 .ao_speed = 350,
943 .caldac = { caldac_none },
944 },
945 [BOARD_PCI6284] = {
946 .name = "pci-6284",
947 .n_adchan = 32,
948 .ai_maxdata = 0x3ffff,
949 .ai_fifo_depth = 2047,
950 .gainlkup = ai_gain_628x,
951 .ai_speed = 1600,
952 .reg_type = ni_reg_628x,
953 .has_32dio_chan = 1,
954 .caldac = { caldac_none },
955 },
956 [BOARD_PCI6289] = {
957 .name = "pci-6289",
958 .n_adchan = 32,
959 .ai_maxdata = 0x3ffff,
960 .ai_fifo_depth = 2047,
961 .gainlkup = ai_gain_628x,
962 .ai_speed = 1600,
963 .n_aochan = 4,
964 .ao_maxdata = 0xffff,
965 .ao_fifo_depth = 8191,
966 .ao_range_table = &range_ni_M_628x_ao,
967 .reg_type = ni_reg_628x,
968 .ao_speed = 350,
969 .has_32dio_chan = 1,
970 .caldac = { caldac_none },
971 },
972 [BOARD_PCI6143] = {
973 .name = "pci-6143",
974 .n_adchan = 8,
975 .ai_maxdata = 0xffff,
976 .ai_fifo_depth = 1024,
977 .gainlkup = ai_gain_6143,
978 .ai_speed = 4000,
979 .reg_type = ni_reg_6143,
980 .caldac = { ad8804_debug, ad8804_debug },
981 },
982 [BOARD_PXI6143] = {
983 .name = "pxi-6143",
984 .n_adchan = 8,
985 .ai_maxdata = 0xffff,
986 .ai_fifo_depth = 1024,
987 .gainlkup = ai_gain_6143,
988 .ai_speed = 4000,
989 .reg_type = ni_reg_6143,
990 .caldac = { ad8804_debug, ad8804_debug },
991 },
992};
993
994#include "ni_mio_common.c"
995
996static int pcimio_ai_change(struct comedi_device *dev,
997 struct comedi_subdevice *s)
998{
999 struct ni_private *devpriv = dev->private;
1000 int ret;
1001
1002 ret = mite_buf_change(devpriv->ai_mite_ring, s);
1003 if (ret < 0)
1004 return ret;
1005
1006 return 0;
1007}
1008
1009static int pcimio_ao_change(struct comedi_device *dev,
1010 struct comedi_subdevice *s)
1011{
1012 struct ni_private *devpriv = dev->private;
1013 int ret;
1014
1015 ret = mite_buf_change(devpriv->ao_mite_ring, s);
1016 if (ret < 0)
1017 return ret;
1018
1019 return 0;
1020}
1021
1022static int pcimio_gpct0_change(struct comedi_device *dev,
1023 struct comedi_subdevice *s)
1024{
1025 struct ni_private *devpriv = dev->private;
1026 int ret;
1027
1028 ret = mite_buf_change(devpriv->gpct_mite_ring[0], s);
1029 if (ret < 0)
1030 return ret;
1031
1032 return 0;
1033}
1034
1035static int pcimio_gpct1_change(struct comedi_device *dev,
1036 struct comedi_subdevice *s)
1037{
1038 struct ni_private *devpriv = dev->private;
1039 int ret;
1040
1041 ret = mite_buf_change(devpriv->gpct_mite_ring[1], s);
1042 if (ret < 0)
1043 return ret;
1044
1045 return 0;
1046}
1047
1048static int pcimio_dio_change(struct comedi_device *dev,
1049 struct comedi_subdevice *s)
1050{
1051 struct ni_private *devpriv = dev->private;
1052 int ret;
1053
1054 ret = mite_buf_change(devpriv->cdo_mite_ring, s);
1055 if (ret < 0)
1056 return ret;
1057
1058 return 0;
1059}
1060
1061static void m_series_init_eeprom_buffer(struct comedi_device *dev)
1062{
1063 struct ni_private *devpriv = dev->private;
1064 struct mite *mite = devpriv->mite;
1065 resource_size_t daq_phys_addr;
1066 static const int Start_Cal_EEPROM = 0x400;
1067 static const unsigned int window_size = 10;
1068 static const int serial_number_eeprom_offset = 0x4;
1069 static const int serial_number_eeprom_length = 0x4;
1070 unsigned int old_iodwbsr_bits;
1071 unsigned int old_iodwbsr1_bits;
1072 unsigned int old_iodwcr1_bits;
1073 int i;
1074
1075
1076 daq_phys_addr = pci_resource_start(mite->pcidev, 1);
1077
1078 old_iodwbsr_bits = readl(mite->mmio + MITE_IODWBSR);
1079 old_iodwbsr1_bits = readl(mite->mmio + MITE_IODWBSR_1);
1080 old_iodwcr1_bits = readl(mite->mmio + MITE_IODWCR_1);
1081 writel(0x0, mite->mmio + MITE_IODWBSR);
1082 writel(((0x80 | window_size) | daq_phys_addr),
1083 mite->mmio + MITE_IODWBSR_1);
1084 writel(0x1 | old_iodwcr1_bits, mite->mmio + MITE_IODWCR_1);
1085 writel(0xf, mite->mmio + 0x30);
1086
1087 BUG_ON(serial_number_eeprom_length > sizeof(devpriv->serial_number));
1088 for (i = 0; i < serial_number_eeprom_length; ++i) {
1089 char *byte_ptr = (char *)&devpriv->serial_number + i;
1090 *byte_ptr = ni_readb(dev, serial_number_eeprom_offset + i);
1091 }
1092 devpriv->serial_number = be32_to_cpu(devpriv->serial_number);
1093
1094 for (i = 0; i < M_SERIES_EEPROM_SIZE; ++i)
1095 devpriv->eeprom_buffer[i] = ni_readb(dev, Start_Cal_EEPROM + i);
1096
1097 writel(old_iodwbsr1_bits, mite->mmio + MITE_IODWBSR_1);
1098 writel(old_iodwbsr_bits, mite->mmio + MITE_IODWBSR);
1099 writel(old_iodwcr1_bits, mite->mmio + MITE_IODWCR_1);
1100 writel(0x0, mite->mmio + 0x30);
1101}
1102
1103static void init_6143(struct comedi_device *dev)
1104{
1105 const struct ni_board_struct *board = dev->board_ptr;
1106 struct ni_private *devpriv = dev->private;
1107
1108
1109 ni_stc_writew(dev, 0, NISTC_INT_CTRL_REG);
1110
1111
1112
1113
1114 ni_writeb(dev, 0x00, NI6143_MAGIC_REG);
1115
1116 ni_writeb(dev, 0x80, NI6143_PIPELINE_DELAY_REG);
1117
1118 ni_writeb(dev, 0x00, NI6143_EOC_SET_REG);
1119
1120
1121 ni_writel(dev, board->ai_fifo_depth / 2, NI6143_AI_FIFO_FLAG_REG);
1122
1123
1124 devpriv->ai_calib_source_enabled = 0;
1125 ni_writew(dev, devpriv->ai_calib_source | NI6143_CALIB_CHAN_RELAY_OFF,
1126 NI6143_CALIB_CHAN_REG);
1127 ni_writew(dev, devpriv->ai_calib_source, NI6143_CALIB_CHAN_REG);
1128}
1129
1130static void pcimio_detach(struct comedi_device *dev)
1131{
1132 struct ni_private *devpriv = dev->private;
1133
1134 mio_common_detach(dev);
1135 if (dev->irq)
1136 free_irq(dev->irq, dev);
1137 if (devpriv) {
1138 mite_free_ring(devpriv->ai_mite_ring);
1139 mite_free_ring(devpriv->ao_mite_ring);
1140 mite_free_ring(devpriv->cdo_mite_ring);
1141 mite_free_ring(devpriv->gpct_mite_ring[0]);
1142 mite_free_ring(devpriv->gpct_mite_ring[1]);
1143 mite_detach(devpriv->mite);
1144 }
1145 if (dev->mmio)
1146 iounmap(dev->mmio);
1147 comedi_pci_disable(dev);
1148}
1149
1150static int pcimio_auto_attach(struct comedi_device *dev,
1151 unsigned long context)
1152{
1153 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1154 const struct ni_board_struct *board = NULL;
1155 struct ni_private *devpriv;
1156 unsigned int irq;
1157 int ret;
1158
1159 if (context < ARRAY_SIZE(ni_boards))
1160 board = &ni_boards[context];
1161 if (!board)
1162 return -ENODEV;
1163 dev->board_ptr = board;
1164 dev->board_name = board->name;
1165
1166 ret = comedi_pci_enable(dev);
1167 if (ret)
1168 return ret;
1169
1170 ret = ni_alloc_private(dev);
1171 if (ret)
1172 return ret;
1173 devpriv = dev->private;
1174
1175 devpriv->mite = mite_attach(dev, false);
1176 if (!devpriv->mite)
1177 return -ENOMEM;
1178
1179 if (board->reg_type & ni_reg_m_series_mask)
1180 devpriv->is_m_series = 1;
1181 if (board->reg_type & ni_reg_6xxx_mask)
1182 devpriv->is_6xxx = 1;
1183 if (board->reg_type == ni_reg_611x)
1184 devpriv->is_611x = 1;
1185 if (board->reg_type == ni_reg_6143)
1186 devpriv->is_6143 = 1;
1187 if (board->reg_type == ni_reg_622x)
1188 devpriv->is_622x = 1;
1189 if (board->reg_type == ni_reg_625x)
1190 devpriv->is_625x = 1;
1191 if (board->reg_type == ni_reg_628x)
1192 devpriv->is_628x = 1;
1193 if (board->reg_type & ni_reg_67xx_mask)
1194 devpriv->is_67xx = 1;
1195 if (board->reg_type == ni_reg_6711)
1196 devpriv->is_6711 = 1;
1197 if (board->reg_type == ni_reg_6713)
1198 devpriv->is_6713 = 1;
1199
1200 devpriv->ai_mite_ring = mite_alloc_ring(devpriv->mite);
1201 if (!devpriv->ai_mite_ring)
1202 return -ENOMEM;
1203 devpriv->ao_mite_ring = mite_alloc_ring(devpriv->mite);
1204 if (!devpriv->ao_mite_ring)
1205 return -ENOMEM;
1206 devpriv->cdo_mite_ring = mite_alloc_ring(devpriv->mite);
1207 if (!devpriv->cdo_mite_ring)
1208 return -ENOMEM;
1209 devpriv->gpct_mite_ring[0] = mite_alloc_ring(devpriv->mite);
1210 if (!devpriv->gpct_mite_ring[0])
1211 return -ENOMEM;
1212 devpriv->gpct_mite_ring[1] = mite_alloc_ring(devpriv->mite);
1213 if (!devpriv->gpct_mite_ring[1])
1214 return -ENOMEM;
1215
1216 if (devpriv->is_m_series)
1217 m_series_init_eeprom_buffer(dev);
1218 if (devpriv->is_6143)
1219 init_6143(dev);
1220
1221 irq = pcidev->irq;
1222 if (irq) {
1223 ret = request_irq(irq, ni_E_interrupt, IRQF_SHARED,
1224 dev->board_name, dev);
1225 if (ret == 0)
1226 dev->irq = irq;
1227 }
1228
1229 ret = ni_E_init(dev, 0, 1);
1230 if (ret < 0)
1231 return ret;
1232
1233 dev->subdevices[NI_AI_SUBDEV].buf_change = &pcimio_ai_change;
1234 dev->subdevices[NI_AO_SUBDEV].buf_change = &pcimio_ao_change;
1235 dev->subdevices[NI_GPCT_SUBDEV(0)].buf_change = &pcimio_gpct0_change;
1236 dev->subdevices[NI_GPCT_SUBDEV(1)].buf_change = &pcimio_gpct1_change;
1237 dev->subdevices[NI_DIO_SUBDEV].buf_change = &pcimio_dio_change;
1238
1239 return 0;
1240}
1241
1242static struct comedi_driver ni_pcimio_driver = {
1243 .driver_name = "ni_pcimio",
1244 .module = THIS_MODULE,
1245 .auto_attach = pcimio_auto_attach,
1246 .detach = pcimio_detach,
1247};
1248
1249static int ni_pcimio_pci_probe(struct pci_dev *dev,
1250 const struct pci_device_id *id)
1251{
1252 return comedi_pci_auto_config(dev, &ni_pcimio_driver, id->driver_data);
1253}
1254
1255static const struct pci_device_id ni_pcimio_pci_table[] = {
1256 { PCI_VDEVICE(NI, 0x0162), BOARD_PCIMIO_16XE_50 },
1257 { PCI_VDEVICE(NI, 0x1170), BOARD_PCIMIO_16XE_10 },
1258 { PCI_VDEVICE(NI, 0x1180), BOARD_PCIMIO_16E_1 },
1259 { PCI_VDEVICE(NI, 0x1190), BOARD_PCIMIO_16E_4 },
1260 { PCI_VDEVICE(NI, 0x11b0), BOARD_PXI6070E },
1261 { PCI_VDEVICE(NI, 0x11c0), BOARD_PXI6040E },
1262 { PCI_VDEVICE(NI, 0x11d0), BOARD_PXI6030E },
1263 { PCI_VDEVICE(NI, 0x1270), BOARD_PCI6032E },
1264 { PCI_VDEVICE(NI, 0x1330), BOARD_PCI6031E },
1265 { PCI_VDEVICE(NI, 0x1340), BOARD_PCI6033E },
1266 { PCI_VDEVICE(NI, 0x1350), BOARD_PCI6071E },
1267 { PCI_VDEVICE(NI, 0x14e0), BOARD_PCI6110 },
1268 { PCI_VDEVICE(NI, 0x14f0), BOARD_PCI6111 },
1269 { PCI_VDEVICE(NI, 0x1580), BOARD_PXI6031E },
1270 { PCI_VDEVICE(NI, 0x15b0), BOARD_PXI6071E },
1271 { PCI_VDEVICE(NI, 0x1880), BOARD_PCI6711 },
1272 { PCI_VDEVICE(NI, 0x1870), BOARD_PCI6713 },
1273 { PCI_VDEVICE(NI, 0x18b0), BOARD_PCI6052E },
1274 { PCI_VDEVICE(NI, 0x18c0), BOARD_PXI6052E },
1275 { PCI_VDEVICE(NI, 0x2410), BOARD_PCI6733 },
1276 { PCI_VDEVICE(NI, 0x2420), BOARD_PXI6733 },
1277 { PCI_VDEVICE(NI, 0x2430), BOARD_PCI6731 },
1278 { PCI_VDEVICE(NI, 0x2890), BOARD_PCI6036E },
1279 { PCI_VDEVICE(NI, 0x28c0), BOARD_PCI6014 },
1280 { PCI_VDEVICE(NI, 0x2a60), BOARD_PCI6023E },
1281 { PCI_VDEVICE(NI, 0x2a70), BOARD_PCI6024E },
1282 { PCI_VDEVICE(NI, 0x2a80), BOARD_PCI6025E },
1283 { PCI_VDEVICE(NI, 0x2ab0), BOARD_PXI6025E },
1284 { PCI_VDEVICE(NI, 0x2b80), BOARD_PXI6713 },
1285 { PCI_VDEVICE(NI, 0x2b90), BOARD_PXI6711 },
1286 { PCI_VDEVICE(NI, 0x2c80), BOARD_PCI6035E },
1287 { PCI_VDEVICE(NI, 0x2ca0), BOARD_PCI6034E },
1288 { PCI_VDEVICE(NI, 0x70aa), BOARD_PCI6229 },
1289 { PCI_VDEVICE(NI, 0x70ab), BOARD_PCI6259 },
1290 { PCI_VDEVICE(NI, 0x70ac), BOARD_PCI6289 },
1291 { PCI_VDEVICE(NI, 0x70af), BOARD_PCI6221 },
1292 { PCI_VDEVICE(NI, 0x70b0), BOARD_PCI6220 },
1293 { PCI_VDEVICE(NI, 0x70b4), BOARD_PCI6250 },
1294 { PCI_VDEVICE(NI, 0x70b6), BOARD_PCI6280 },
1295 { PCI_VDEVICE(NI, 0x70b7), BOARD_PCI6254 },
1296 { PCI_VDEVICE(NI, 0x70b8), BOARD_PCI6251 },
1297 { PCI_VDEVICE(NI, 0x70bc), BOARD_PCI6284 },
1298 { PCI_VDEVICE(NI, 0x70bd), BOARD_PCI6281 },
1299 { PCI_VDEVICE(NI, 0x70bf), BOARD_PXI6281 },
1300 { PCI_VDEVICE(NI, 0x70c0), BOARD_PCI6143 },
1301 { PCI_VDEVICE(NI, 0x70f2), BOARD_PCI6224 },
1302 { PCI_VDEVICE(NI, 0x70f3), BOARD_PXI6224 },
1303 { PCI_VDEVICE(NI, 0x710d), BOARD_PXI6143 },
1304 { PCI_VDEVICE(NI, 0x716c), BOARD_PCI6225 },
1305 { PCI_VDEVICE(NI, 0x716d), BOARD_PXI6225 },
1306 { PCI_VDEVICE(NI, 0x717f), BOARD_PCIE6259 },
1307 { PCI_VDEVICE(NI, 0x71bc), BOARD_PCI6221_37PIN },
1308 { PCI_VDEVICE(NI, 0x717d), BOARD_PCIE6251 },
1309 { PCI_VDEVICE(NI, 0x72e8), BOARD_PXIE6251 },
1310 { PCI_VDEVICE(NI, 0x70ad), BOARD_PXI6251 },
1311 { 0 }
1312};
1313MODULE_DEVICE_TABLE(pci, ni_pcimio_pci_table);
1314
1315static struct pci_driver ni_pcimio_pci_driver = {
1316 .name = "ni_pcimio",
1317 .id_table = ni_pcimio_pci_table,
1318 .probe = ni_pcimio_pci_probe,
1319 .remove = comedi_pci_auto_unconfig,
1320};
1321module_comedi_pci_driver(ni_pcimio_driver, ni_pcimio_pci_driver);
1322
1323MODULE_AUTHOR("Comedi http://www.comedi.org");
1324MODULE_DESCRIPTION("Comedi low-level driver");
1325MODULE_LICENSE("GPL");
1326
