1/* 2 * core.h - DesignWare HS OTG Controller common declarations 3 * 4 * Copyright (C) 2004-2013 Synopsys, Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer, 11 * without modification. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The names of the above-listed copyright holders may not be used 16 * to endorse or promote products derived from this software without 17 * specific prior written permission. 18 * 19 * ALTERNATIVELY, this software may be distributed under the terms of the 20 * GNU General Public License ("GPL") as published by the Free Software 21 * Foundation; either version 2 of the License, or (at your option) any 22 * later version. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37#ifndef __DWC2_CORE_H__ 38#define __DWC2_CORE_H__ 39 40#include <linux/phy/phy.h> 41#include <linux/regulator/consumer.h> 42#include <linux/usb/gadget.h> 43#include <linux/usb/otg.h> 44#include <linux/usb/phy.h> 45#include "hw.h" 46 47/* 48 * Suggested defines for tracers: 49 * - no_printk: Disable tracing 50 * - pr_info: Print this info to the console 51 * - trace_printk: Print this info to trace buffer (good for verbose logging) 52 */ 53 54#define DWC2_TRACE_SCHEDULER no_printk 55#define DWC2_TRACE_SCHEDULER_VB no_printk 56 57/* Detailed scheduler tracing, but won't overwhelm console */ 58#define dwc2_sch_dbg(hsotg, fmt, ...) \ 59 DWC2_TRACE_SCHEDULER(pr_fmt("%s: SCH: " fmt), \ 60 dev_name(hsotg->dev), ##__VA_ARGS__) 61 62/* Verbose scheduler tracing */ 63#define dwc2_sch_vdbg(hsotg, fmt, ...) \ 64 DWC2_TRACE_SCHEDULER_VB(pr_fmt("%s: SCH: " fmt), \ 65 dev_name(hsotg->dev), ##__VA_ARGS__) 66 67#ifdef CONFIG_MIPS 68/* 69 * There are some MIPS machines that can run in either big-endian 70 * or little-endian mode and that use the dwc2 register without 71 * a byteswap in both ways. 72 * Unlike other architectures, MIPS apparently does not require a 73 * barrier before the __raw_writel() to synchronize with DMA but does 74 * require the barrier after the __raw_writel() to serialize a set of 75 * writes. This set of operations was added specifically for MIPS and 76 * should only be used there. 77 */ 78static inline u32 dwc2_readl(const void __iomem *addr) 79{ 80 u32 value = __raw_readl(addr); 81 82 /* In order to preserve endianness __raw_* operation is used. Therefore 83 * a barrier is needed to ensure IO access is not re-ordered across 84 * reads or writes 85 */ 86 mb(); 87 return value; 88} 89 90static inline void dwc2_writel(u32 value, void __iomem *addr) 91{ 92 __raw_writel(value, addr); 93 94 /* 95 * In order to preserve endianness __raw_* operation is used. Therefore 96 * a barrier is needed to ensure IO access is not re-ordered across 97 * reads or writes 98 */ 99 mb(); 100#ifdef DWC2_LOG_WRITES 101 pr_info("INFO:: wrote %08x to %p\n", value, addr); 102#endif 103} 104#else 105/* Normal architectures just use readl/write */ 106static inline u32 dwc2_readl(const void __iomem *addr) 107{ 108 return readl(addr); 109} 110 111static inline void dwc2_writel(u32 value, void __iomem *addr) 112{ 113 writel(value, addr); 114 115#ifdef DWC2_LOG_WRITES 116 pr_info("info:: wrote %08x to %p\n", value, addr); 117#endif 118} 119#endif 120 121/* Maximum number of Endpoints/HostChannels */ 122#define MAX_EPS_CHANNELS 16 123 124/* dwc2-hsotg declarations */ 125static const char * const dwc2_hsotg_supply_names[] = { 126 "vusb_d", /* digital USB supply, 1.2V */ 127 "vusb_a", /* analog USB supply, 1.1V */ 128}; 129 130/* 131 * EP0_MPS_LIMIT 132 * 133 * Unfortunately there seems to be a limit of the amount of data that can 134 * be transferred by IN transactions on EP0. This is either 127 bytes or 3 135 * packets (which practically means 1 packet and 63 bytes of data) when the 136 * MPS is set to 64. 137 * 138 * This means if we are wanting to move >127 bytes of data, we need to 139 * split the transactions up, but just doing one packet at a time does 140 * not work (this may be an implicit DATA0 PID on first packet of the 141 * transaction) and doing 2 packets is outside the controller's limits. 142 * 143 * If we try to lower the MPS size for EP0, then no transfers work properly 144 * for EP0, and the system will fail basic enumeration. As no cause for this 145 * has currently been found, we cannot support any large IN transfers for 146 * EP0. 147 */ 148#define EP0_MPS_LIMIT 64 149 150struct dwc2_hsotg; 151struct dwc2_hsotg_req; 152 153/** 154 * struct dwc2_hsotg_ep - driver endpoint definition. 155 * @ep: The gadget layer representation of the endpoint. 156 * @name: The driver generated name for the endpoint. 157 * @queue: Queue of requests for this endpoint. 158 * @parent: Reference back to the parent device structure. 159 * @req: The current request that the endpoint is processing. This is 160 * used to indicate an request has been loaded onto the endpoint 161 * and has yet to be completed (maybe due to data move, or simply 162 * awaiting an ack from the core all the data has been completed). 163 * @debugfs: File entry for debugfs file for this endpoint. 164 * @lock: State lock to protect contents of endpoint. 165 * @dir_in: Set to true if this endpoint is of the IN direction, which 166 * means that it is sending data to the Host. 167 * @index: The index for the endpoint registers. 168 * @mc: Multi Count - number of transactions per microframe 169 * @interval - Interval for periodic endpoints, in frames or microframes. 170 * @name: The name array passed to the USB core. 171 * @halted: Set if the endpoint has been halted. 172 * @periodic: Set if this is a periodic ep, such as Interrupt 173 * @isochronous: Set if this is a isochronous ep 174 * @send_zlp: Set if we need to send a zero-length packet. 175 * @total_data: The total number of data bytes done. 176 * @fifo_size: The size of the FIFO (for periodic IN endpoints) 177 * @fifo_load: The amount of data loaded into the FIFO (periodic IN) 178 * @last_load: The offset of data for the last start of request. 179 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN 180 * @target_frame: Targeted frame num to setup next ISOC transfer 181 * @frame_overrun: Indicates SOF number overrun in DSTS 182 * 183 * This is the driver's state for each registered enpoint, allowing it 184 * to keep track of transactions that need doing. Each endpoint has a 185 * lock to protect the state, to try and avoid using an overall lock 186 * for the host controller as much as possible. 187 * 188 * For periodic IN endpoints, we have fifo_size and fifo_load to try 189 * and keep track of the amount of data in the periodic FIFO for each 190 * of these as we don't have a status register that tells us how much 191 * is in each of them. (note, this may actually be useless information 192 * as in shared-fifo mode periodic in acts like a single-frame packet 193 * buffer than a fifo) 194 */ 195struct dwc2_hsotg_ep { 196 struct usb_ep ep; 197 struct list_head queue; 198 struct dwc2_hsotg *parent; 199 struct dwc2_hsotg_req *req; 200 struct dentry *debugfs; 201 202 unsigned long total_data; 203 unsigned int size_loaded; 204 unsigned int last_load; 205 unsigned int fifo_load; 206 unsigned short fifo_size; 207 unsigned short fifo_index; 208 209 unsigned char dir_in; 210 unsigned char index; 211 unsigned char mc; 212 unsigned char interval; 213 214 unsigned int halted:1; 215 unsigned int periodic:1; 216 unsigned int isochronous:1; 217 unsigned int send_zlp:1; 218 unsigned int target_frame; 219#define TARGET_FRAME_INITIAL 0xFFFFFFFF 220 bool frame_overrun; 221 222 char name[10]; 223}; 224 225/** 226 * struct dwc2_hsotg_req - data transfer request 227 * @req: The USB gadget request 228 * @queue: The list of requests for the endpoint this is queued for. 229 * @saved_req_buf: variable to save req.buf when bounce buffers are used. 230 */ 231struct dwc2_hsotg_req { 232 struct usb_request req; 233 struct list_head queue; 234 void *saved_req_buf; 235}; 236 237#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 238#define call_gadget(_hs, _entry) \ 239do { \ 240 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \ 241 (_hs)->driver && (_hs)->driver->_entry) { \ 242 spin_unlock(&_hs->lock); \ 243 (_hs)->driver->_entry(&(_hs)->gadget); \ 244 spin_lock(&_hs->lock); \ 245 } \ 246} while (0) 247#else 248#define call_gadget(_hs, _entry) do {} while (0) 249#endif 250 251struct dwc2_hsotg; 252struct dwc2_host_chan; 253 254/* Device States */ 255enum dwc2_lx_state { 256 DWC2_L0, /* On state */ 257 DWC2_L1, /* LPM sleep state */ 258 DWC2_L2, /* USB suspend state */ 259 DWC2_L3, /* Off state */ 260}; 261 262/* 263 * Gadget periodic tx fifo sizes as used by legacy driver 264 * EP0 is not included 265 */ 266#define DWC2_G_P_LEGACY_TX_FIFO_SIZE {256, 256, 256, 256, 768, 768, 768, \ 267 768, 0, 0, 0, 0, 0, 0, 0} 268 269/* Gadget ep0 states */ 270enum dwc2_ep0_state { 271 DWC2_EP0_SETUP, 272 DWC2_EP0_DATA_IN, 273 DWC2_EP0_DATA_OUT, 274 DWC2_EP0_STATUS_IN, 275 DWC2_EP0_STATUS_OUT, 276}; 277 278/** 279 * struct dwc2_core_params - Parameters for configuring the core 280 * 281 * @otg_cap: Specifies the OTG capabilities. 282 * 0 - HNP and SRP capable 283 * 1 - SRP Only capable 284 * 2 - No HNP/SRP capable (always available) 285 * Defaults to best available option (0, 1, then 2) 286 * @otg_ver: OTG version supported 287 * 0 - 1.3 (default) 288 * 1 - 2.0 289 * @dma_enable: Specifies whether to use slave or DMA mode for accessing 290 * the data FIFOs. The driver will automatically detect the 291 * value for this parameter if none is specified. 292 * 0 - Slave (always available) 293 * 1 - DMA (default, if available) 294 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use 295 * address DMA mode or descriptor DMA mode for accessing 296 * the data FIFOs. The driver will automatically detect the 297 * value for this if none is specified. 298 * 0 - Address DMA 299 * 1 - Descriptor DMA (default, if available) 300 * @dma_desc_fs_enable: When DMA mode is enabled, specifies whether to use 301 * address DMA mode or descriptor DMA mode for accessing 302 * the data FIFOs in Full Speed mode only. The driver 303 * will automatically detect the value for this if none is 304 * specified. 305 * 0 - Address DMA 306 * 1 - Descriptor DMA in FS (default, if available) 307 * @speed: Specifies the maximum speed of operation in host and 308 * device mode. The actual speed depends on the speed of 309 * the attached device and the value of phy_type. 310 * 0 - High Speed 311 * (default when phy_type is UTMI+ or ULPI) 312 * 1 - Full Speed 313 * (default when phy_type is Full Speed) 314 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters 315 * 1 - Allow dynamic FIFO sizing (default, if available) 316 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs 317 * are enabled 318 * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when 319 * dynamic FIFO sizing is enabled 320 * 16 to 32768 321 * Actual maximum value is autodetected and also 322 * the default. 323 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO 324 * in host mode when dynamic FIFO sizing is enabled 325 * 16 to 32768 326 * Actual maximum value is autodetected and also 327 * the default. 328 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in 329 * host mode when dynamic FIFO sizing is enabled 330 * 16 to 32768 331 * Actual maximum value is autodetected and also 332 * the default. 333 * @max_transfer_size: The maximum transfer size supported, in bytes 334 * 2047 to 65,535 335 * Actual maximum value is autodetected and also 336 * the default. 337 * @max_packet_count: The maximum number of packets in a transfer 338 * 15 to 511 339 * Actual maximum value is autodetected and also 340 * the default. 341 * @host_channels: The number of host channel registers to use 342 * 1 to 16 343 * Actual maximum value is autodetected and also 344 * the default. 345 * @phy_type: Specifies the type of PHY interface to use. By default, 346 * the driver will automatically detect the phy_type. 347 * 0 - Full Speed Phy 348 * 1 - UTMI+ Phy 349 * 2 - ULPI Phy 350 * Defaults to best available option (2, 1, then 0) 351 * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter 352 * is applicable for a phy_type of UTMI+ or ULPI. (For a 353 * ULPI phy_type, this parameter indicates the data width 354 * between the MAC and the ULPI Wrapper.) Also, this 355 * parameter is applicable only if the OTG_HSPHY_WIDTH cC 356 * parameter was set to "8 and 16 bits", meaning that the 357 * core has been configured to work at either data path 358 * width. 359 * 8 or 16 (default 16 if available) 360 * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single 361 * data rate. This parameter is only applicable if phy_type 362 * is ULPI. 363 * 0 - single data rate ULPI interface with 8 bit wide 364 * data bus (default) 365 * 1 - double data rate ULPI interface with 4 bit wide 366 * data bus 367 * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or 368 * external supply to drive the VBus 369 * 0 - Internal supply (default) 370 * 1 - External supply 371 * @i2c_enable: Specifies whether to use the I2Cinterface for a full 372 * speed PHY. This parameter is only applicable if phy_type 373 * is FS. 374 * 0 - No (default) 375 * 1 - Yes 376 * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only 377 * 0 - No (default) 378 * 1 - Yes 379 * @host_support_fs_ls_low_power: Specifies whether low power mode is supported 380 * when attached to a Full Speed or Low Speed device in 381 * host mode. 382 * 0 - Don't support low power mode (default) 383 * 1 - Support low power mode 384 * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode 385 * when connected to a Low Speed device in host 386 * mode. This parameter is applicable only if 387 * host_support_fs_ls_low_power is enabled. 388 * 0 - 48 MHz 389 * (default when phy_type is UTMI+ or ULPI) 390 * 1 - 6 MHz 391 * (default when phy_type is Full Speed) 392 * @ts_dline: Enable Term Select Dline pulsing 393 * 0 - No (default) 394 * 1 - Yes 395 * @reload_ctl: Allow dynamic reloading of HFIR register during runtime 396 * 0 - No (default for core < 2.92a) 397 * 1 - Yes (default for core >= 2.92a) 398 * @ahbcfg: This field allows the default value of the GAHBCFG 399 * register to be overridden 400 * -1 - GAHBCFG value will be set to 0x06 401 * (INCR4, default) 402 * all others - GAHBCFG value will be overridden with 403 * this value 404 * Not all bits can be controlled like this, the 405 * bits defined by GAHBCFG_CTRL_MASK are controlled 406 * by the driver and are ignored in this 407 * configuration value. 408 * @uframe_sched: True to enable the microframe scheduler 409 * @external_id_pin_ctl: Specifies whether ID pin is handled externally. 410 * Disable CONIDSTSCHNG controller interrupt in such 411 * case. 412 * 0 - No (default) 413 * 1 - Yes 414 * @hibernation: Specifies whether the controller support hibernation. 415 * If hibernation is enabled, the controller will enter 416 * hibernation in both peripheral and host mode when 417 * needed. 418 * 0 - No (default) 419 * 1 - Yes 420 * 421 * The following parameters may be specified when starting the module. These 422 * parameters define how the DWC_otg controller should be configured. A 423 * value of -1 (or any other out of range value) for any parameter means 424 * to read the value from hardware (if possible) or use the builtin 425 * default described above. 426 */ 427struct dwc2_core_params { 428 /* 429 * Don't add any non-int members here, this will break 430 * dwc2_set_all_params! 431 */ 432 int otg_cap; 433 int otg_ver; 434 int dma_enable; 435 int dma_desc_enable; 436 int dma_desc_fs_enable; 437 int speed; 438 int enable_dynamic_fifo; 439 int en_multiple_tx_fifo; 440 int host_rx_fifo_size; 441 int host_nperio_tx_fifo_size; 442 int host_perio_tx_fifo_size; 443 int max_transfer_size; 444 int max_packet_count; 445 int host_channels; 446 int phy_type; 447 int phy_utmi_width; 448 int phy_ulpi_ddr; 449 int phy_ulpi_ext_vbus; 450 int i2c_enable; 451 int ulpi_fs_ls; 452 int host_support_fs_ls_low_power; 453 int host_ls_low_power_phy_clk; 454 int ts_dline; 455 int reload_ctl; 456 int ahbcfg; 457 int uframe_sched; 458 int external_id_pin_ctl; 459 int hibernation; 460}; 461 462/** 463 * struct dwc2_hw_params - Autodetected parameters. 464 * 465 * These parameters are the various parameters read from hardware 466 * registers during initialization. They typically contain the best 467 * supported or maximum value that can be configured in the 468 * corresponding dwc2_core_params value. 469 * 470 * The values that are not in dwc2_core_params are documented below. 471 * 472 * @op_mode Mode of Operation 473 * 0 - HNP- and SRP-Capable OTG (Host & Device) 474 * 1 - SRP-Capable OTG (Host & Device) 475 * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device) 476 * 3 - SRP-Capable Device 477 * 4 - Non-OTG Device 478 * 5 - SRP-Capable Host 479 * 6 - Non-OTG Host 480 * @arch Architecture 481 * 0 - Slave only 482 * 1 - External DMA 483 * 2 - Internal DMA 484 * @power_optimized Are power optimizations enabled? 485 * @num_dev_ep Number of device endpoints available 486 * @num_dev_perio_in_ep Number of device periodic IN endpoints 487 * available 488 * @dev_token_q_depth Device Mode IN Token Sequence Learning Queue 489 * Depth 490 * 0 to 30 491 * @host_perio_tx_q_depth 492 * Host Mode Periodic Request Queue Depth 493 * 2, 4 or 8 494 * @nperio_tx_q_depth 495 * Non-Periodic Request Queue Depth 496 * 2, 4 or 8 497 * @hs_phy_type High-speed PHY interface type 498 * 0 - High-speed interface not supported 499 * 1 - UTMI+ 500 * 2 - ULPI 501 * 3 - UTMI+ and ULPI 502 * @fs_phy_type Full-speed PHY interface type 503 * 0 - Full speed interface not supported 504 * 1 - Dedicated full speed interface 505 * 2 - FS pins shared with UTMI+ pins 506 * 3 - FS pins shared with ULPI pins 507 * @total_fifo_size: Total internal RAM for FIFOs (bytes) 508 * @utmi_phy_data_width UTMI+ PHY data width 509 * 0 - 8 bits 510 * 1 - 16 bits 511 * 2 - 8 or 16 bits 512 * @snpsid: Value from SNPSID register 513 * @dev_ep_dirs: Direction of device endpoints (GHWCFG1) 514 */ 515struct dwc2_hw_params { 516 unsigned op_mode:3; 517 unsigned arch:2; 518 unsigned dma_desc_enable:1; 519 unsigned dma_desc_fs_enable:1; 520 unsigned enable_dynamic_fifo:1; 521 unsigned en_multiple_tx_fifo:1; 522 unsigned host_rx_fifo_size:16; 523 unsigned host_nperio_tx_fifo_size:16; 524 unsigned dev_nperio_tx_fifo_size:16; 525 unsigned host_perio_tx_fifo_size:16; 526 unsigned nperio_tx_q_depth:3; 527 unsigned host_perio_tx_q_depth:3; 528 unsigned dev_token_q_depth:5; 529 unsigned max_transfer_size:26; 530 unsigned max_packet_count:11; 531 unsigned host_channels:5; 532 unsigned hs_phy_type:2; 533 unsigned fs_phy_type:2; 534 unsigned i2c_enable:1; 535 unsigned num_dev_ep:4; 536 unsigned num_dev_perio_in_ep:4; 537 unsigned total_fifo_size:16; 538 unsigned power_optimized:1; 539 unsigned utmi_phy_data_width:2; 540 u32 snpsid; 541 u32 dev_ep_dirs; 542}; 543 544/* Size of control and EP0 buffers */ 545#define DWC2_CTRL_BUFF_SIZE 8 546 547/** 548 * struct dwc2_gregs_backup - Holds global registers state before entering partial 549 * power down 550 * @gotgctl: Backup of GOTGCTL register 551 * @gintmsk: Backup of GINTMSK register 552 * @gahbcfg: Backup of GAHBCFG register 553 * @gusbcfg: Backup of GUSBCFG register 554 * @grxfsiz: Backup of GRXFSIZ register 555 * @gnptxfsiz: Backup of GNPTXFSIZ register 556 * @gi2cctl: Backup of GI2CCTL register 557 * @hptxfsiz: Backup of HPTXFSIZ register 558 * @gdfifocfg: Backup of GDFIFOCFG register 559 * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint 560 * @gpwrdn: Backup of GPWRDN register 561 */ 562struct dwc2_gregs_backup { 563 u32 gotgctl; 564 u32 gintmsk; 565 u32 gahbcfg; 566 u32 gusbcfg; 567 u32 grxfsiz; 568 u32 gnptxfsiz; 569 u32 gi2cctl; 570 u32 hptxfsiz; 571 u32 pcgcctl; 572 u32 gdfifocfg; 573 u32 dtxfsiz[MAX_EPS_CHANNELS]; 574 u32 gpwrdn; 575 bool valid; 576}; 577 578/** 579 * struct dwc2_dregs_backup - Holds device registers state before entering partial 580 * power down 581 * @dcfg: Backup of DCFG register 582 * @dctl: Backup of DCTL register 583 * @daintmsk: Backup of DAINTMSK register 584 * @diepmsk: Backup of DIEPMSK register 585 * @doepmsk: Backup of DOEPMSK register 586 * @diepctl: Backup of DIEPCTL register 587 * @dieptsiz: Backup of DIEPTSIZ register 588 * @diepdma: Backup of DIEPDMA register 589 * @doepctl: Backup of DOEPCTL register 590 * @doeptsiz: Backup of DOEPTSIZ register 591 * @doepdma: Backup of DOEPDMA register 592 */ 593struct dwc2_dregs_backup { 594 u32 dcfg; 595 u32 dctl; 596 u32 daintmsk; 597 u32 diepmsk; 598 u32 doepmsk; 599 u32 diepctl[MAX_EPS_CHANNELS]; 600 u32 dieptsiz[MAX_EPS_CHANNELS]; 601 u32 diepdma[MAX_EPS_CHANNELS]; 602 u32 doepctl[MAX_EPS_CHANNELS]; 603 u32 doeptsiz[MAX_EPS_CHANNELS]; 604 u32 doepdma[MAX_EPS_CHANNELS]; 605 bool valid; 606}; 607 608/** 609 * struct dwc2_hregs_backup - Holds host registers state before entering partial 610 * power down 611 * @hcfg: Backup of HCFG register 612 * @haintmsk: Backup of HAINTMSK register 613 * @hcintmsk: Backup of HCINTMSK register 614 * @hptr0: Backup of HPTR0 register 615 * @hfir: Backup of HFIR register 616 */ 617struct dwc2_hregs_backup { 618 u32 hcfg; 619 u32 haintmsk; 620 u32 hcintmsk[MAX_EPS_CHANNELS]; 621 u32 hprt0; 622 u32 hfir; 623 bool valid; 624}; 625 626/* 627 * Constants related to high speed periodic scheduling 628 * 629 * We have a periodic schedule that is DWC2_HS_SCHEDULE_UFRAMES long. From a 630 * reservation point of view it's assumed that the schedule goes right back to 631 * the beginning after the end of the schedule. 632 * 633 * What does that mean for scheduling things with a long interval? It means 634 * we'll reserve time for them in every possible microframe that they could 635 * ever be scheduled in. ...but we'll still only actually schedule them as 636 * often as they were requested. 637 * 638 * We keep our schedule in a "bitmap" structure. This simplifies having 639 * to keep track of and merge intervals: we just let the bitmap code do most 640 * of the heavy lifting. In a way scheduling is much like memory allocation. 641 * 642 * We schedule 100us per uframe or 80% of 125us (the maximum amount you're 643 * supposed to schedule for periodic transfers). That's according to spec. 644 * 645 * Note that though we only schedule 80% of each microframe, the bitmap that we 646 * keep the schedule in is tightly packed (AKA it doesn't have 100us worth of 647 * space for each uFrame). 648 * 649 * Requirements: 650 * - DWC2_HS_SCHEDULE_UFRAMES must even divide 0x4000 (HFNUM_MAX_FRNUM + 1) 651 * - DWC2_HS_SCHEDULE_UFRAMES must be 8 times DWC2_LS_SCHEDULE_FRAMES (probably 652 * could be any multiple of 8 times DWC2_LS_SCHEDULE_FRAMES, but there might 653 * be bugs). The 8 comes from the USB spec: number of microframes per frame. 654 */ 655#define DWC2_US_PER_UFRAME 125 656#define DWC2_HS_PERIODIC_US_PER_UFRAME 100 657 658#define DWC2_HS_SCHEDULE_UFRAMES 8 659#define DWC2_HS_SCHEDULE_US (DWC2_HS_SCHEDULE_UFRAMES * \ 660 DWC2_HS_PERIODIC_US_PER_UFRAME) 661 662/* 663 * Constants related to low speed scheduling 664 * 665 * For high speed we schedule every 1us. For low speed that's a bit overkill, 666 * so we make up a unit called a "slice" that's worth 25us. There are 40 667 * slices in a full frame and we can schedule 36 of those (90%) for periodic 668 * transfers. 669 * 670 * Our low speed schedule can be as short as 1 frame or could be longer. When 671 * we only schedule 1 frame it means that we'll need to reserve a time every 672 * frame even for things that only transfer very rarely, so something that runs 673 * every 2048 frames will get time reserved in every frame. Our low speed 674 * schedule can be longer and we'll be able to handle more overlap, but that 675 * will come at increased memory cost and increased time to schedule. 676 * 677 * Note: one other advantage of a short low speed schedule is that if we mess 678 * up and miss scheduling we can jump in and use any of the slots that we 679 * happened to reserve. 680 * 681 * With 25 us per slice and 1 frame in the schedule, we only need 4 bytes for 682 * the schedule. There will be one schedule per TT. 683 * 684 * Requirements: 685 * - DWC2_US_PER_SLICE must evenly divide DWC2_LS_PERIODIC_US_PER_FRAME. 686 */ 687#define DWC2_US_PER_SLICE 25 688#define DWC2_SLICES_PER_UFRAME (DWC2_US_PER_UFRAME / DWC2_US_PER_SLICE) 689 690#define DWC2_ROUND_US_TO_SLICE(us) \ 691 (DIV_ROUND_UP((us), DWC2_US_PER_SLICE) * \ 692 DWC2_US_PER_SLICE) 693 694#define DWC2_LS_PERIODIC_US_PER_FRAME \ 695 900 696#define DWC2_LS_PERIODIC_SLICES_PER_FRAME \ 697 (DWC2_LS_PERIODIC_US_PER_FRAME / \ 698 DWC2_US_PER_SLICE) 699 700#define DWC2_LS_SCHEDULE_FRAMES 1 701#define DWC2_LS_SCHEDULE_SLICES (DWC2_LS_SCHEDULE_FRAMES * \ 702 DWC2_LS_PERIODIC_SLICES_PER_FRAME) 703 704/** 705 * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic 706 * and periodic schedules 707 * 708 * These are common for both host and peripheral modes: 709 * 710 * @dev: The struct device pointer 711 * @regs: Pointer to controller regs 712 * @hw_params: Parameters that were autodetected from the 713 * hardware registers 714 * @core_params: Parameters that define how the core should be configured 715 * @op_state: The operational State, during transitions (a_host=> 716 * a_peripheral and b_device=>b_host) this may not match 717 * the core, but allows the software to determine 718 * transitions 719 * @dr_mode: Requested mode of operation, one of following: 720 * - USB_DR_MODE_PERIPHERAL 721 * - USB_DR_MODE_HOST 722 * - USB_DR_MODE_OTG 723 * @hcd_enabled Host mode sub-driver initialization indicator. 724 * @gadget_enabled Peripheral mode sub-driver initialization indicator. 725 * @ll_hw_enabled Status of low-level hardware resources. 726 * @phy: The otg phy transceiver structure for phy control. 727 * @uphy: The otg phy transceiver structure for old USB phy control. 728 * @plat: The platform specific configuration data. This can be removed once 729 * all SoCs support usb transceiver. 730 * @supplies: Definition of USB power supplies 731 * @phyif: PHY interface width 732 * @lock: Spinlock that protects all the driver data structures 733 * @priv: Stores a pointer to the struct usb_hcd 734 * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth 735 * transfer are in process of being queued 736 * @srp_success: Stores status of SRP request in the case of a FS PHY 737 * with an I2C interface 738 * @wq_otg: Workqueue object used for handling of some interrupts 739 * @wf_otg: Work object for handling Connector ID Status Change 740 * interrupt 741 * @wkp_timer: Timer object for handling Wakeup Detected interrupt 742 * @lx_state: Lx state of connected device 743 * @gregs_backup: Backup of global registers during suspend 744 * @dregs_backup: Backup of device registers during suspend 745 * @hregs_backup: Backup of host registers during suspend 746 * 747 * These are for host mode: 748 * 749 * @flags: Flags for handling root port state changes 750 * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule. 751 * Transfers associated with these QHs are not currently 752 * assigned to a host channel. 753 * @non_periodic_sched_active: Active QHs in the non-periodic schedule. 754 * Transfers associated with these QHs are currently 755 * assigned to a host channel. 756 * @non_periodic_qh_ptr: Pointer to next QH to process in the active 757 * non-periodic schedule 758 * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a 759 * list of QHs for periodic transfers that are _not_ 760 * scheduled for the next frame. Each QH in the list has an 761 * interval counter that determines when it needs to be 762 * scheduled for execution. This scheduling mechanism 763 * allows only a simple calculation for periodic bandwidth 764 * used (i.e. must assume that all periodic transfers may 765 * need to execute in the same frame). However, it greatly 766 * simplifies scheduling and should be sufficient for the 767 * vast majority of OTG hosts, which need to connect to a 768 * small number of peripherals at one time. Items move from 769 * this list to periodic_sched_ready when the QH interval 770 * counter is 0 at SOF. 771 * @periodic_sched_ready: List of periodic QHs that are ready for execution in 772 * the next frame, but have not yet been assigned to host 773 * channels. Items move from this list to 774 * periodic_sched_assigned as host channels become 775 * available during the current frame. 776 * @periodic_sched_assigned: List of periodic QHs to be executed in the next 777 * frame that are assigned to host channels. Items move 778 * from this list to periodic_sched_queued as the 779 * transactions for the QH are queued to the DWC_otg 780 * controller. 781 * @periodic_sched_queued: List of periodic QHs that have been queued for 782 * execution. Items move from this list to either 783 * periodic_sched_inactive or periodic_sched_ready when the 784 * channel associated with the transfer is released. If the 785 * interval for the QH is 1, the item moves to 786 * periodic_sched_ready because it must be rescheduled for 787 * the next frame. Otherwise, the item moves to 788 * periodic_sched_inactive. 789 * @split_order: List keeping track of channels doing splits, in order. 790 * @periodic_usecs: Total bandwidth claimed so far for periodic transfers. 791 * This value is in microseconds per (micro)frame. The 792 * assumption is that all periodic transfers may occur in 793 * the same (micro)frame. 794 * @hs_periodic_bitmap: Bitmap used by the microframe scheduler any time the 795 * host is in high speed mode; low speed schedules are 796 * stored elsewhere since we need one per TT. 797 * @frame_number: Frame number read from the core at SOF. The value ranges 798 * from 0 to HFNUM_MAX_FRNUM. 799 * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for 800 * SOF enable/disable. 801 * @free_hc_list: Free host channels in the controller. This is a list of 802 * struct dwc2_host_chan items. 803 * @periodic_channels: Number of host channels assigned to periodic transfers. 804 * Currently assuming that there is a dedicated host 805 * channel for each periodic transaction and at least one 806 * host channel is available for non-periodic transactions. 807 * @non_periodic_channels: Number of host channels assigned to non-periodic 808 * transfers 809 * @available_host_channels Number of host channels available for the microframe 810 * scheduler to use 811 * @hc_ptr_array: Array of pointers to the host channel descriptors. 812 * Allows accessing a host channel descriptor given the 813 * host channel number. This is useful in interrupt 814 * handlers. 815 * @status_buf: Buffer used for data received during the status phase of 816 * a control transfer. 817 * @status_buf_dma: DMA address for status_buf 818 * @start_work: Delayed work for handling host A-cable connection 819 * @reset_work: Delayed work for handling a port reset 820 * @otg_port: OTG port number 821 * @frame_list: Frame list 822 * @frame_list_dma: Frame list DMA address 823 * @frame_list_sz: Frame list size 824 * @desc_gen_cache: Kmem cache for generic descriptors 825 * @desc_hsisoc_cache: Kmem cache for hs isochronous descriptors 826 * 827 * These are for peripheral mode: 828 * 829 * @driver: USB gadget driver 830 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos. 831 * @num_of_eps: Number of available EPs (excluding EP0) 832 * @debug_root: Root directrory for debugfs. 833 * @debug_file: Main status file for debugfs. 834 * @debug_testmode: Testmode status file for debugfs. 835 * @debug_fifo: FIFO status file for debugfs. 836 * @ep0_reply: Request used for ep0 reply. 837 * @ep0_buff: Buffer for EP0 reply data, if needed. 838 * @ctrl_buff: Buffer for EP0 control requests. 839 * @ctrl_req: Request for EP0 control packets. 840 * @ep0_state: EP0 control transfers state 841 * @test_mode: USB test mode requested by the host 842 * @eps: The endpoints being supplied to the gadget framework 843 * @g_using_dma: Indicate if dma usage is enabled 844 * @g_rx_fifo_sz: Contains rx fifo size value 845 * @g_np_g_tx_fifo_sz: Contains Non-Periodic tx fifo size value 846 * @g_tx_fifo_sz: Contains tx fifo size value per endpoints 847 */ 848struct dwc2_hsotg { 849 struct device *dev; 850 void __iomem *regs; 851 /** Params detected from hardware */ 852 struct dwc2_hw_params hw_params; 853 /** Params to actually use */ 854 struct dwc2_core_params *core_params; 855 enum usb_otg_state op_state; 856 enum usb_dr_mode dr_mode; 857 unsigned int hcd_enabled:1; 858 unsigned int gadget_enabled:1; 859 unsigned int ll_hw_enabled:1; 860 861 struct phy *phy; 862 struct usb_phy *uphy; 863 struct dwc2_hsotg_plat *plat; 864 struct regulator_bulk_data supplies[ARRAY_SIZE(dwc2_hsotg_supply_names)]; 865 u32 phyif; 866 867 spinlock_t lock; 868 void *priv; 869 int irq; 870 struct clk *clk; 871 struct reset_control *reset; 872 873 unsigned int queuing_high_bandwidth:1; 874 unsigned int srp_success:1; 875 876 struct workqueue_struct *wq_otg; 877 struct work_struct wf_otg; 878 struct timer_list wkp_timer; 879 enum dwc2_lx_state lx_state; 880 struct dwc2_gregs_backup gr_backup; 881 struct dwc2_dregs_backup dr_backup; 882 struct dwc2_hregs_backup hr_backup; 883 884 struct dentry *debug_root; 885 struct debugfs_regset32 *regset; 886 887 /* DWC OTG HW Release versions */ 888#define DWC2_CORE_REV_2_71a 0x4f54271a 889#define DWC2_CORE_REV_2_90a 0x4f54290a 890#define DWC2_CORE_REV_2_92a 0x4f54292a 891#define DWC2_CORE_REV_2_94a 0x4f54294a 892#define DWC2_CORE_REV_3_00a 0x4f54300a 893 894#if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 895 union dwc2_hcd_internal_flags { 896 u32 d32; 897 struct { 898 unsigned port_connect_status_change:1; 899 unsigned port_connect_status:1; 900 unsigned port_reset_change:1; 901 unsigned port_enable_change:1; 902 unsigned port_suspend_change:1; 903 unsigned port_over_current_change:1; 904 unsigned port_l1_change:1; 905 unsigned reserved:25; 906 } b; 907 } flags; 908 909 struct list_head non_periodic_sched_inactive; 910 struct list_head non_periodic_sched_active; 911 struct list_head *non_periodic_qh_ptr; 912 struct list_head periodic_sched_inactive; 913 struct list_head periodic_sched_ready; 914 struct list_head periodic_sched_assigned; 915 struct list_head periodic_sched_queued; 916 struct list_head split_order; 917 u16 periodic_usecs; 918 unsigned long hs_periodic_bitmap[ 919 DIV_ROUND_UP(DWC2_HS_SCHEDULE_US, BITS_PER_LONG)]; 920 u16 frame_number; 921 u16 periodic_qh_count; 922 bool bus_suspended; 923 bool new_connection; 924 925 u16 last_frame_num; 926 927#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 928#define FRAME_NUM_ARRAY_SIZE 1000 929 u16 *frame_num_array; 930 u16 *last_frame_num_array; 931 int frame_num_idx; 932 int dumped_frame_num_array; 933#endif 934 935 struct list_head free_hc_list; 936 int periodic_channels; 937 int non_periodic_channels; 938 int available_host_channels; 939 struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS]; 940 u8 *status_buf; 941 dma_addr_t status_buf_dma; 942#define DWC2_HCD_STATUS_BUF_SIZE 64 943 944 struct delayed_work start_work; 945 struct delayed_work reset_work; 946 u8 otg_port; 947 u32 *frame_list; 948 dma_addr_t frame_list_dma; 949 u32 frame_list_sz; 950 struct kmem_cache *desc_gen_cache; 951 struct kmem_cache *desc_hsisoc_cache; 952 953#ifdef DEBUG 954 u32 frrem_samples; 955 u64 frrem_accum; 956 957 u32 hfnum_7_samples_a; 958 u64 hfnum_7_frrem_accum_a; 959 u32 hfnum_0_samples_a; 960 u64 hfnum_0_frrem_accum_a; 961 u32 hfnum_other_samples_a; 962 u64 hfnum_other_frrem_accum_a; 963 964 u32 hfnum_7_samples_b; 965 u64 hfnum_7_frrem_accum_b; 966 u32 hfnum_0_samples_b; 967 u64 hfnum_0_frrem_accum_b; 968 u32 hfnum_other_samples_b; 969 u64 hfnum_other_frrem_accum_b; 970#endif 971#endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */ 972 973#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 974 /* Gadget structures */ 975 struct usb_gadget_driver *driver; 976 int fifo_mem; 977 unsigned int dedicated_fifos:1; 978 unsigned char num_of_eps; 979 u32 fifo_map; 980 981 struct usb_request *ep0_reply; 982 struct usb_request *ctrl_req; 983 void *ep0_buff; 984 void *ctrl_buff; 985 enum dwc2_ep0_state ep0_state; 986 u8 test_mode; 987 988 struct usb_gadget gadget; 989 unsigned int enabled:1; 990 unsigned int connected:1; 991 struct dwc2_hsotg_ep *eps_in[MAX_EPS_CHANNELS]; 992 struct dwc2_hsotg_ep *eps_out[MAX_EPS_CHANNELS]; 993 u32 g_using_dma; 994 u32 g_rx_fifo_sz; 995 u32 g_np_g_tx_fifo_sz; 996 u32 g_tx_fifo_sz[MAX_EPS_CHANNELS]; 997#endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */ 998}; 999 1000/* Reasons for halting a host channel */
1001enum dwc2_halt_status { 1002 DWC2_HC_XFER_NO_HALT_STATUS, 1003 DWC2_HC_XFER_COMPLETE, 1004 DWC2_HC_XFER_URB_COMPLETE, 1005 DWC2_HC_XFER_ACK, 1006 DWC2_HC_XFER_NAK, 1007 DWC2_HC_XFER_NYET, 1008 DWC2_HC_XFER_STALL, 1009 DWC2_HC_XFER_XACT_ERR, 1010 DWC2_HC_XFER_FRAME_OVERRUN, 1011 DWC2_HC_XFER_BABBLE_ERR, 1012 DWC2_HC_XFER_DATA_TOGGLE_ERR, 1013 DWC2_HC_XFER_AHB_ERR, 1014 DWC2_HC_XFER_PERIODIC_INCOMPLETE, 1015 DWC2_HC_XFER_URB_DEQUEUE, 1016}; 1017 1018/* 1019 * The following functions support initialization of the core driver component 1020 * and the DWC_otg controller 1021 */ 1022extern int dwc2_core_reset(struct dwc2_hsotg *hsotg); 1023extern int dwc2_core_reset_and_force_dr_mode(struct dwc2_hsotg *hsotg); 1024extern int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg); 1025extern int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore); 1026 1027void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg); 1028 1029extern bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg); 1030 1031/* 1032 * Common core Functions. 1033 * The following functions support managing the DWC_otg controller in either 1034 * device or host mode. 1035 */ 1036extern void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes); 1037extern void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num); 1038extern void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg); 1039 1040extern void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd); 1041extern void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd); 1042 1043/* This function should be called on every hardware interrupt. */ 1044extern irqreturn_t dwc2_handle_common_intr(int irq, void *dev); 1045 1046/* OTG Core Parameters */ 1047 1048/* 1049 * Specifies the OTG capabilities. The driver will automatically 1050 * detect the value for this parameter if none is specified. 1051 * 0 - HNP and SRP capable (default) 1052 * 1 - SRP Only capable 1053 * 2 - No HNP/SRP capable 1054 */ 1055extern void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val); 1056#define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0 1057#define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1 1058#define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2 1059 1060/* 1061 * Specifies whether to use slave or DMA mode for accessing the data 1062 * FIFOs. The driver will automatically detect the value for this 1063 * parameter if none is specified. 1064 * 0 - Slave 1065 * 1 - DMA (default, if available) 1066 */ 1067extern void dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val); 1068 1069/* 1070 * When DMA mode is enabled specifies whether to use 1071 * address DMA or DMA Descritor mode for accessing the data 1072 * FIFOs in device mode. The driver will automatically detect 1073 * the value for this parameter if none is specified. 1074 * 0 - address DMA 1075 * 1 - DMA Descriptor(default, if available) 1076 */ 1077extern void dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val); 1078 1079/* 1080 * When DMA mode is enabled specifies whether to use 1081 * address DMA or DMA Descritor mode with full speed devices 1082 * for accessing the data FIFOs in host mode. 1083 * 0 - address DMA 1084 * 1 - FS DMA Descriptor(default, if available) 1085 */ 1086extern void dwc2_set_param_dma_desc_fs_enable(struct dwc2_hsotg *hsotg, 1087 int val); 1088 1089/* 1090 * Specifies the maximum speed of operation in host and device mode. 1091 * The actual speed depends on the speed of the attached device and 1092 * the value of phy_type. The actual speed depends on the speed of the 1093 * attached device. 1094 * 0 - High Speed (default) 1095 * 1 - Full Speed 1096 */ 1097extern void dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val); 1098#define DWC2_SPEED_PARAM_HIGH 0 1099#define DWC2_SPEED_PARAM_FULL 1 1100 1101/* 1102 * Specifies whether low power mode is supported when attached 1103 * to a Full Speed or Low Speed device in host mode. 1104 * 1105 * 0 - Don't support low power mode (default) 1106 * 1 - Support low power mode 1107 */ 1108extern void dwc2_set_param_host_support_fs_ls_low_power( 1109 struct dwc2_hsotg *hsotg, int val); 1110 1111/* 1112 * Specifies the PHY clock rate in low power mode when connected to a 1113 * Low Speed device in host mode. This parameter is applicable only if 1114 * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS 1115 * then defaults to 6 MHZ otherwise 48 MHZ. 1116 * 1117 * 0 - 48 MHz 1118 * 1 - 6 MHz 1119 */ 1120extern void dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg, 1121 int val); 1122#define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0 1123#define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1 1124 1125/* 1126 * 0 - Use cC FIFO size parameters 1127 * 1 - Allow dynamic FIFO sizing (default) 1128 */ 1129extern void dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg, 1130 int val); 1131 1132/* 1133 * Number of 4-byte words in the Rx FIFO in host mode when dynamic 1134 * FIFO sizing is enabled. 1135 * 16 to 32768 (default 1024) 1136 */ 1137extern void dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val); 1138 1139/* 1140 * Number of 4-byte words in the non-periodic Tx FIFO in host mode 1141 * when Dynamic FIFO sizing is enabled in the core. 1142 * 16 to 32768 (default 256) 1143 */ 1144extern void dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg, 1145 int val); 1146 1147/* 1148 * Number of 4-byte words in the host periodic Tx FIFO when dynamic 1149 * FIFO sizing is enabled. 1150 * 16 to 32768 (default 256) 1151 */ 1152extern void dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg, 1153 int val); 1154 1155/* 1156 * The maximum transfer size supported in bytes. 1157 * 2047 to 65,535 (default 65,535) 1158 */ 1159extern void dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val); 1160 1161/* 1162 * The maximum number of packets in a transfer. 1163 * 15 to 511 (default 511) 1164 */ 1165extern void dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val); 1166 1167/* 1168 * The number of host channel registers to use. 1169 * 1 to 16 (default 11) 1170 * Note: The FPGA configuration supports a maximum of 11 host channels. 1171 */ 1172extern void dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val); 1173 1174/* 1175 * Specifies the type of PHY interface to use. By default, the driver 1176 * will automatically detect the phy_type. 1177 * 1178 * 0 - Full Speed PHY 1179 * 1 - UTMI+ (default) 1180 * 2 - ULPI 1181 */ 1182extern void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val); 1183#define DWC2_PHY_TYPE_PARAM_FS 0 1184#define DWC2_PHY_TYPE_PARAM_UTMI 1 1185#define DWC2_PHY_TYPE_PARAM_ULPI 2 1186 1187/* 1188 * Specifies the UTMI+ Data Width. This parameter is 1189 * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI 1190 * PHY_TYPE, this parameter indicates the data width between 1191 * the MAC and the ULPI Wrapper.) Also, this parameter is 1192 * applicable only if the OTG_HSPHY_WIDTH cC parameter was set 1193 * to "8 and 16 bits", meaning that the core has been 1194 * configured to work at either data path width. 1195 * 1196 * 8 or 16 bits (default 16) 1197 */ 1198extern void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val); 1199 1200/* 1201 * Specifies whether the ULPI operates at double or single 1202 * data rate. This parameter is only applicable if PHY_TYPE is 1203 * ULPI. 1204 * 1205 * 0 - single data rate ULPI interface with 8 bit wide data 1206 * bus (default) 1207 * 1 - double data rate ULPI interface with 4 bit wide data 1208 * bus 1209 */ 1210extern void dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val); 1211 1212/* 1213 * Specifies whether to use the internal or external supply to 1214 * drive the vbus with a ULPI phy. 1215 */ 1216extern void dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val); 1217#define DWC2_PHY_ULPI_INTERNAL_VBUS 0 1218#define DWC2_PHY_ULPI_EXTERNAL_VBUS 1 1219 1220/* 1221 * Specifies whether to use the I2Cinterface for full speed PHY. This 1222 * parameter is only applicable if PHY_TYPE is FS. 1223 * 0 - No (default) 1224 * 1 - Yes 1225 */ 1226extern void dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val); 1227 1228extern void dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val); 1229 1230extern void dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val); 1231 1232/* 1233 * Specifies whether dedicated transmit FIFOs are 1234 * enabled for non periodic IN endpoints in device mode 1235 * 0 - No 1236 * 1 - Yes 1237 */ 1238extern void dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg, 1239 int val); 1240 1241extern void dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val); 1242 1243extern void dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val); 1244 1245extern void dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val); 1246 1247extern void dwc2_set_parameters(struct dwc2_hsotg *hsotg, 1248 const struct dwc2_core_params *params); 1249 1250extern void dwc2_set_all_params(struct dwc2_core_params *params, int value); 1251 1252extern int dwc2_get_hwparams(struct dwc2_hsotg *hsotg); 1253 1254extern int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg); 1255extern int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg); 1256 1257/* 1258 * The following functions check the controller's OTG operation mode 1259 * capability (GHWCFG2.OTG_MODE). 1260 * 1261 * These functions can be used before the internal hsotg->hw_params 1262 * are read in and cached so they always read directly from the 1263 * GHWCFG2 register. 1264 */ 1265unsigned dwc2_op_mode(struct dwc2_hsotg *hsotg); 1266bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg); 1267bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg); 1268bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg); 1269 1270/* 1271 * Returns the mode of operation, host or device 1272 */ 1273static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg) 1274{ 1275 return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) != 0; 1276} 1277static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg) 1278{ 1279 return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) == 0; 1280} 1281 1282/* 1283 * Dump core registers and SPRAM 1284 */ 1285extern void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg); 1286extern void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg); 1287extern void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg); 1288 1289/* 1290 * Return OTG version - either 1.3 or 2.0 1291 */ 1292extern u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg); 1293 1294/* Gadget defines */ 1295#if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1296extern int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg); 1297extern int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2); 1298extern int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2); 1299extern int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq); 1300extern void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, 1301 bool reset); 1302extern void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg); 1303extern void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2); 1304extern int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode); 1305#define dwc2_is_device_connected(hsotg) (hsotg->connected) 1306int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg); 1307int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg); 1308#else 1309static inline int dwc2_hsotg_remove(struct dwc2_hsotg *dwc2) 1310{ return 0; } 1311static inline int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2) 1312{ return 0; } 1313static inline int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2) 1314{ return 0; } 1315static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq) 1316{ return 0; } 1317static inline void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2, 1318 bool reset) {} 1319static inline void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) {} 1320static inline void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2) {} 1321static inline int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, 1322 int testmode) 1323{ return 0; } 1324#define dwc2_is_device_connected(hsotg) (0) 1325static inline int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg) 1326{ return 0; } 1327static inline int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg) 1328{ return 0; } 1329#endif 1330 1331#if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 1332extern int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg); 1333extern int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us); 1334extern void dwc2_hcd_connect(struct dwc2_hsotg *hsotg); 1335extern void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force); 1336extern void dwc2_hcd_start(struct dwc2_hsotg *hsotg); 1337int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg); 1338int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg); 1339#else 1340static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) 1341{ return 0; } 1342static inline int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, 1343 int us) 1344{ return 0; } 1345static inline void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) {} 1346static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) {} 1347static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {} 1348static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {} 1349static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq) 1350{ return 0; } 1351static inline int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg) 1352{ return 0; } 1353static inline int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg) 1354{ return 0; } 1355 1356#endif 1357 1358#endif /* __DWC2_CORE_H__ */ 1359