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27#ifndef _UAPI_I915_DRM_H_
28#define _UAPI_I915_DRM_H_
29
30#include "drm.h"
31
32#if defined(__cplusplus)
33extern "C" {
34#endif
35
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60
61#define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR"
62#define I915_ERROR_UEVENT "ERROR"
63#define I915_RESET_UEVENT "RESET"
64
65
66
67#define I915_NR_TEX_REGIONS 255
68
69#define I915_LOG_MIN_TEX_REGION_SIZE 14
70
71typedef struct _drm_i915_init {
72 enum {
73 I915_INIT_DMA = 0x01,
74 I915_CLEANUP_DMA = 0x02,
75 I915_RESUME_DMA = 0x03
76 } func;
77 unsigned int mmio_offset;
78 int sarea_priv_offset;
79 unsigned int ring_start;
80 unsigned int ring_end;
81 unsigned int ring_size;
82 unsigned int front_offset;
83 unsigned int back_offset;
84 unsigned int depth_offset;
85 unsigned int w;
86 unsigned int h;
87 unsigned int pitch;
88 unsigned int pitch_bits;
89 unsigned int back_pitch;
90 unsigned int depth_pitch;
91 unsigned int cpp;
92 unsigned int chipset;
93} drm_i915_init_t;
94
95typedef struct _drm_i915_sarea {
96 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
97 int last_upload;
98 int last_enqueue;
99 int last_dispatch;
100 int ctxOwner;
101 int texAge;
102 int pf_enabled;
103 int pf_active;
104 int pf_current_page;
105 int perf_boxes;
106 int width, height;
107
108 drm_handle_t front_handle;
109 int front_offset;
110 int front_size;
111
112 drm_handle_t back_handle;
113 int back_offset;
114 int back_size;
115
116 drm_handle_t depth_handle;
117 int depth_offset;
118 int depth_size;
119
120 drm_handle_t tex_handle;
121 int tex_offset;
122 int tex_size;
123 int log_tex_granularity;
124 int pitch;
125 int rotation;
126 int rotated_offset;
127 int rotated_size;
128 int rotated_pitch;
129 int virtualX, virtualY;
130
131 unsigned int front_tiled;
132 unsigned int back_tiled;
133 unsigned int depth_tiled;
134 unsigned int rotated_tiled;
135 unsigned int rotated2_tiled;
136
137 int pipeA_x;
138 int pipeA_y;
139 int pipeA_w;
140 int pipeA_h;
141 int pipeB_x;
142 int pipeB_y;
143 int pipeB_w;
144 int pipeB_h;
145
146
147 drm_handle_t unused_handle;
148 __u32 unused1, unused2, unused3;
149
150
151
152
153 __u32 front_bo_handle;
154 __u32 back_bo_handle;
155 __u32 unused_bo_handle;
156 __u32 depth_bo_handle;
157
158} drm_i915_sarea_t;
159
160
161#define planeA_x pipeA_x
162#define planeA_y pipeA_y
163#define planeA_w pipeA_w
164#define planeA_h pipeA_h
165#define planeB_x pipeB_x
166#define planeB_y pipeB_y
167#define planeB_w pipeB_w
168#define planeB_h pipeB_h
169
170
171
172#define I915_BOX_RING_EMPTY 0x1
173#define I915_BOX_FLIP 0x2
174#define I915_BOX_WAIT 0x4
175#define I915_BOX_TEXTURE_LOAD 0x8
176#define I915_BOX_LOST_CONTEXT 0x10
177
178
179
180
181
182
183
184
185#define DRM_I915_INIT 0x00
186#define DRM_I915_FLUSH 0x01
187#define DRM_I915_FLIP 0x02
188#define DRM_I915_BATCHBUFFER 0x03
189#define DRM_I915_IRQ_EMIT 0x04
190#define DRM_I915_IRQ_WAIT 0x05
191#define DRM_I915_GETPARAM 0x06
192#define DRM_I915_SETPARAM 0x07
193#define DRM_I915_ALLOC 0x08
194#define DRM_I915_FREE 0x09
195#define DRM_I915_INIT_HEAP 0x0a
196#define DRM_I915_CMDBUFFER 0x0b
197#define DRM_I915_DESTROY_HEAP 0x0c
198#define DRM_I915_SET_VBLANK_PIPE 0x0d
199#define DRM_I915_GET_VBLANK_PIPE 0x0e
200#define DRM_I915_VBLANK_SWAP 0x0f
201#define DRM_I915_HWS_ADDR 0x11
202#define DRM_I915_GEM_INIT 0x13
203#define DRM_I915_GEM_EXECBUFFER 0x14
204#define DRM_I915_GEM_PIN 0x15
205#define DRM_I915_GEM_UNPIN 0x16
206#define DRM_I915_GEM_BUSY 0x17
207#define DRM_I915_GEM_THROTTLE 0x18
208#define DRM_I915_GEM_ENTERVT 0x19
209#define DRM_I915_GEM_LEAVEVT 0x1a
210#define DRM_I915_GEM_CREATE 0x1b
211#define DRM_I915_GEM_PREAD 0x1c
212#define DRM_I915_GEM_PWRITE 0x1d
213#define DRM_I915_GEM_MMAP 0x1e
214#define DRM_I915_GEM_SET_DOMAIN 0x1f
215#define DRM_I915_GEM_SW_FINISH 0x20
216#define DRM_I915_GEM_SET_TILING 0x21
217#define DRM_I915_GEM_GET_TILING 0x22
218#define DRM_I915_GEM_GET_APERTURE 0x23
219#define DRM_I915_GEM_MMAP_GTT 0x24
220#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25
221#define DRM_I915_GEM_MADVISE 0x26
222#define DRM_I915_OVERLAY_PUT_IMAGE 0x27
223#define DRM_I915_OVERLAY_ATTRS 0x28
224#define DRM_I915_GEM_EXECBUFFER2 0x29
225#define DRM_I915_GET_SPRITE_COLORKEY 0x2a
226#define DRM_I915_SET_SPRITE_COLORKEY 0x2b
227#define DRM_I915_GEM_WAIT 0x2c
228#define DRM_I915_GEM_CONTEXT_CREATE 0x2d
229#define DRM_I915_GEM_CONTEXT_DESTROY 0x2e
230#define DRM_I915_GEM_SET_CACHING 0x2f
231#define DRM_I915_GEM_GET_CACHING 0x30
232#define DRM_I915_REG_READ 0x31
233#define DRM_I915_GET_RESET_STATS 0x32
234#define DRM_I915_GEM_USERPTR 0x33
235#define DRM_I915_GEM_CONTEXT_GETPARAM 0x34
236#define DRM_I915_GEM_CONTEXT_SETPARAM 0x35
237
238#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
239#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
240#define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
241#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
242#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
243#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
244#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
245#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
246#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
247#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
248#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
249#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
250#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
251#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
252#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
253#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
254#define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init)
255#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
256#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
257#define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
258#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
259#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
260#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
261#define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching)
262#define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching)
263#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
264#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
265#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
266#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
267#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
268#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
269#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
270#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
271#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
272#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
273#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
274#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
275#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
276#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)
277#define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
278#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image)
279#define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
280#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
281#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
282#define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
283#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
284#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
285#define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
286#define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
287#define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr)
288#define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param)
289#define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param)
290
291
292
293
294typedef struct drm_i915_batchbuffer {
295 int start;
296 int used;
297 int DR1;
298 int DR4;
299 int num_cliprects;
300 struct drm_clip_rect __user *cliprects;
301} drm_i915_batchbuffer_t;
302
303
304
305
306typedef struct _drm_i915_cmdbuffer {
307 char __user *buf;
308 int sz;
309 int DR1;
310 int DR4;
311 int num_cliprects;
312 struct drm_clip_rect __user *cliprects;
313} drm_i915_cmdbuffer_t;
314
315
316
317typedef struct drm_i915_irq_emit {
318 int __user *irq_seq;
319} drm_i915_irq_emit_t;
320
321typedef struct drm_i915_irq_wait {
322 int irq_seq;
323} drm_i915_irq_wait_t;
324
325
326
327#define I915_PARAM_IRQ_ACTIVE 1
328#define I915_PARAM_ALLOW_BATCHBUFFER 2
329#define I915_PARAM_LAST_DISPATCH 3
330#define I915_PARAM_CHIPSET_ID 4
331#define I915_PARAM_HAS_GEM 5
332#define I915_PARAM_NUM_FENCES_AVAIL 6
333#define I915_PARAM_HAS_OVERLAY 7
334#define I915_PARAM_HAS_PAGEFLIPPING 8
335#define I915_PARAM_HAS_EXECBUF2 9
336#define I915_PARAM_HAS_BSD 10
337#define I915_PARAM_HAS_BLT 11
338#define I915_PARAM_HAS_RELAXED_FENCING 12
339#define I915_PARAM_HAS_COHERENT_RINGS 13
340#define I915_PARAM_HAS_EXEC_CONSTANTS 14
341#define I915_PARAM_HAS_RELAXED_DELTA 15
342#define I915_PARAM_HAS_GEN7_SOL_RESET 16
343#define I915_PARAM_HAS_LLC 17
344#define I915_PARAM_HAS_ALIASING_PPGTT 18
345#define I915_PARAM_HAS_WAIT_TIMEOUT 19
346#define I915_PARAM_HAS_SEMAPHORES 20
347#define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21
348#define I915_PARAM_HAS_VEBOX 22
349#define I915_PARAM_HAS_SECURE_BATCHES 23
350#define I915_PARAM_HAS_PINNED_BATCHES 24
351#define I915_PARAM_HAS_EXEC_NO_RELOC 25
352#define I915_PARAM_HAS_EXEC_HANDLE_LUT 26
353#define I915_PARAM_HAS_WT 27
354#define I915_PARAM_CMD_PARSER_VERSION 28
355#define I915_PARAM_HAS_COHERENT_PHYS_GTT 29
356#define I915_PARAM_MMAP_VERSION 30
357#define I915_PARAM_HAS_BSD2 31
358#define I915_PARAM_REVISION 32
359#define I915_PARAM_SUBSLICE_TOTAL 33
360#define I915_PARAM_EU_TOTAL 34
361#define I915_PARAM_HAS_GPU_RESET 35
362#define I915_PARAM_HAS_RESOURCE_STREAMER 36
363#define I915_PARAM_HAS_EXEC_SOFTPIN 37
364#define I915_PARAM_HAS_POOLED_EU 38
365#define I915_PARAM_MIN_EU_IN_POOL 39
366
367typedef struct drm_i915_getparam {
368 __s32 param;
369
370
371
372
373 int __user *value;
374} drm_i915_getparam_t;
375
376
377
378#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
379#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
380#define I915_SETPARAM_ALLOW_BATCHBUFFER 3
381#define I915_SETPARAM_NUM_USED_FENCES 4
382
383typedef struct drm_i915_setparam {
384 int param;
385 int value;
386} drm_i915_setparam_t;
387
388
389
390#define I915_MEM_REGION_AGP 1
391
392typedef struct drm_i915_mem_alloc {
393 int region;
394 int alignment;
395 int size;
396 int __user *region_offset;
397} drm_i915_mem_alloc_t;
398
399typedef struct drm_i915_mem_free {
400 int region;
401 int region_offset;
402} drm_i915_mem_free_t;
403
404typedef struct drm_i915_mem_init_heap {
405 int region;
406 int size;
407 int start;
408} drm_i915_mem_init_heap_t;
409
410
411
412
413typedef struct drm_i915_mem_destroy_heap {
414 int region;
415} drm_i915_mem_destroy_heap_t;
416
417
418
419#define DRM_I915_VBLANK_PIPE_A 1
420#define DRM_I915_VBLANK_PIPE_B 2
421
422typedef struct drm_i915_vblank_pipe {
423 int pipe;
424} drm_i915_vblank_pipe_t;
425
426
427
428typedef struct drm_i915_vblank_swap {
429 drm_drawable_t drawable;
430 enum drm_vblank_seq_type seqtype;
431 unsigned int sequence;
432} drm_i915_vblank_swap_t;
433
434typedef struct drm_i915_hws_addr {
435 __u64 addr;
436} drm_i915_hws_addr_t;
437
438struct drm_i915_gem_init {
439
440
441
442
443 __u64 gtt_start;
444
445
446
447
448 __u64 gtt_end;
449};
450
451struct drm_i915_gem_create {
452
453
454
455
456
457 __u64 size;
458
459
460
461
462
463 __u32 handle;
464 __u32 pad;
465};
466
467struct drm_i915_gem_pread {
468
469 __u32 handle;
470 __u32 pad;
471
472 __u64 offset;
473
474 __u64 size;
475
476
477
478
479
480 __u64 data_ptr;
481};
482
483struct drm_i915_gem_pwrite {
484
485 __u32 handle;
486 __u32 pad;
487
488 __u64 offset;
489
490 __u64 size;
491
492
493
494
495
496 __u64 data_ptr;
497};
498
499struct drm_i915_gem_mmap {
500
501 __u32 handle;
502 __u32 pad;
503
504 __u64 offset;
505
506
507
508
509
510 __u64 size;
511
512
513
514
515
516 __u64 addr_ptr;
517
518
519
520
521
522
523 __u64 flags;
524#define I915_MMAP_WC 0x1
525};
526
527struct drm_i915_gem_mmap_gtt {
528
529 __u32 handle;
530 __u32 pad;
531
532
533
534
535
536 __u64 offset;
537};
538
539struct drm_i915_gem_set_domain {
540
541 __u32 handle;
542
543
544 __u32 read_domains;
545
546
547 __u32 write_domain;
548};
549
550struct drm_i915_gem_sw_finish {
551
552 __u32 handle;
553};
554
555struct drm_i915_gem_relocation_entry {
556
557
558
559
560
561
562
563
564 __u32 target_handle;
565
566
567
568
569
570 __u32 delta;
571
572
573 __u64 offset;
574
575
576
577
578
579
580
581
582
583 __u64 presumed_offset;
584
585
586
587
588 __u32 read_domains;
589
590
591
592
593
594
595
596
597 __u32 write_domain;
598};
599
600
601
602
603
604
605
606
607
608#define I915_GEM_DOMAIN_CPU 0x00000001
609
610#define I915_GEM_DOMAIN_RENDER 0x00000002
611
612#define I915_GEM_DOMAIN_SAMPLER 0x00000004
613
614#define I915_GEM_DOMAIN_COMMAND 0x00000008
615
616#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010
617
618#define I915_GEM_DOMAIN_VERTEX 0x00000020
619
620#define I915_GEM_DOMAIN_GTT 0x00000040
621
622
623struct drm_i915_gem_exec_object {
624
625
626
627
628 __u32 handle;
629
630
631 __u32 relocation_count;
632
633
634
635
636 __u64 relocs_ptr;
637
638
639 __u64 alignment;
640
641
642
643
644
645 __u64 offset;
646};
647
648struct drm_i915_gem_execbuffer {
649
650
651
652
653
654
655
656
657
658
659 __u64 buffers_ptr;
660 __u32 buffer_count;
661
662
663 __u32 batch_start_offset;
664
665 __u32 batch_len;
666 __u32 DR1;
667 __u32 DR4;
668 __u32 num_cliprects;
669
670 __u64 cliprects_ptr;
671};
672
673struct drm_i915_gem_exec_object2 {
674
675
676
677
678 __u32 handle;
679
680
681 __u32 relocation_count;
682
683
684
685
686 __u64 relocs_ptr;
687
688
689 __u64 alignment;
690
691
692
693
694
695
696
697
698
699 __u64 offset;
700
701#define EXEC_OBJECT_NEEDS_FENCE (1<<0)
702#define EXEC_OBJECT_NEEDS_GTT (1<<1)
703#define EXEC_OBJECT_WRITE (1<<2)
704#define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3)
705#define EXEC_OBJECT_PINNED (1<<4)
706#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_PINNED<<1)
707 __u64 flags;
708
709 __u64 rsvd1;
710 __u64 rsvd2;
711};
712
713struct drm_i915_gem_execbuffer2 {
714
715
716
717 __u64 buffers_ptr;
718 __u32 buffer_count;
719
720
721 __u32 batch_start_offset;
722
723 __u32 batch_len;
724 __u32 DR1;
725 __u32 DR4;
726 __u32 num_cliprects;
727
728 __u64 cliprects_ptr;
729#define I915_EXEC_RING_MASK (7<<0)
730#define I915_EXEC_DEFAULT (0<<0)
731#define I915_EXEC_RENDER (1<<0)
732#define I915_EXEC_BSD (2<<0)
733#define I915_EXEC_BLT (3<<0)
734#define I915_EXEC_VEBOX (4<<0)
735
736
737
738
739
740
741
742#define I915_EXEC_CONSTANTS_MASK (3<<6)
743#define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6)
744#define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6)
745#define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6)
746 __u64 flags;
747 __u64 rsvd1;
748 __u64 rsvd2;
749};
750
751
752#define I915_EXEC_GEN7_SOL_RESET (1<<8)
753
754
755
756
757#define I915_EXEC_SECURE (1<<9)
758
759
760
761
762
763
764
765
766#define I915_EXEC_IS_PINNED (1<<10)
767
768
769
770
771
772
773#define I915_EXEC_NO_RELOC (1<<11)
774
775
776
777
778#define I915_EXEC_HANDLE_LUT (1<<12)
779
780
781#define I915_EXEC_BSD_SHIFT (13)
782#define I915_EXEC_BSD_MASK (3 << I915_EXEC_BSD_SHIFT)
783
784#define I915_EXEC_BSD_DEFAULT (0 << I915_EXEC_BSD_SHIFT)
785#define I915_EXEC_BSD_RING1 (1 << I915_EXEC_BSD_SHIFT)
786#define I915_EXEC_BSD_RING2 (2 << I915_EXEC_BSD_SHIFT)
787
788
789
790
791#define I915_EXEC_RESOURCE_STREAMER (1<<15)
792
793#define __I915_EXEC_UNKNOWN_FLAGS -(I915_EXEC_RESOURCE_STREAMER<<1)
794
795#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)
796#define i915_execbuffer2_set_context_id(eb2, context) \
797 (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK
798#define i915_execbuffer2_get_context_id(eb2) \
799 ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK)
800
801struct drm_i915_gem_pin {
802
803 __u32 handle;
804 __u32 pad;
805
806
807 __u64 alignment;
808
809
810 __u64 offset;
811};
812
813struct drm_i915_gem_unpin {
814
815 __u32 handle;
816 __u32 pad;
817};
818
819struct drm_i915_gem_busy {
820
821 __u32 handle;
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853 __u32 busy;
854};
855
856
857
858
859
860
861
862#define I915_CACHING_NONE 0
863
864
865
866
867
868
869
870#define I915_CACHING_CACHED 1
871
872
873
874
875
876
877
878
879
880
881#define I915_CACHING_DISPLAY 2
882
883struct drm_i915_gem_caching {
884
885
886 __u32 handle;
887
888
889
890
891
892
893
894 __u32 caching;
895};
896
897#define I915_TILING_NONE 0
898#define I915_TILING_X 1
899#define I915_TILING_Y 2
900
901#define I915_BIT_6_SWIZZLE_NONE 0
902#define I915_BIT_6_SWIZZLE_9 1
903#define I915_BIT_6_SWIZZLE_9_10 2
904#define I915_BIT_6_SWIZZLE_9_11 3
905#define I915_BIT_6_SWIZZLE_9_10_11 4
906
907#define I915_BIT_6_SWIZZLE_UNKNOWN 5
908
909#define I915_BIT_6_SWIZZLE_9_17 6
910#define I915_BIT_6_SWIZZLE_9_10_17 7
911
912struct drm_i915_gem_set_tiling {
913
914 __u32 handle;
915
916
917
918
919
920
921
922
923
924
925
926
927
928 __u32 tiling_mode;
929
930
931
932
933
934 __u32 stride;
935
936
937
938
939
940 __u32 swizzle_mode;
941};
942
943struct drm_i915_gem_get_tiling {
944
945 __u32 handle;
946
947
948
949
950
951 __u32 tiling_mode;
952
953
954
955
956
957 __u32 swizzle_mode;
958
959
960
961
962
963 __u32 phys_swizzle_mode;
964};
965
966struct drm_i915_gem_get_aperture {
967
968 __u64 aper_size;
969
970
971
972
973
974 __u64 aper_available_size;
975};
976
977struct drm_i915_get_pipe_from_crtc_id {
978
979 __u32 crtc_id;
980
981
982 __u32 pipe;
983};
984
985#define I915_MADV_WILLNEED 0
986#define I915_MADV_DONTNEED 1
987#define __I915_MADV_PURGED 2
988
989struct drm_i915_gem_madvise {
990
991 __u32 handle;
992
993
994
995
996 __u32 madv;
997
998
999 __u32 retained;
1000};
1001
1002
1003#define I915_OVERLAY_TYPE_MASK 0xff
1004#define I915_OVERLAY_YUV_PLANAR 0x01
1005#define I915_OVERLAY_YUV_PACKED 0x02
1006#define I915_OVERLAY_RGB 0x03
1007
1008#define I915_OVERLAY_DEPTH_MASK 0xff00
1009#define I915_OVERLAY_RGB24 0x1000
1010#define I915_OVERLAY_RGB16 0x2000
1011#define I915_OVERLAY_RGB15 0x3000
1012#define I915_OVERLAY_YUV422 0x0100
1013#define I915_OVERLAY_YUV411 0x0200
1014#define I915_OVERLAY_YUV420 0x0300
1015#define I915_OVERLAY_YUV410 0x0400
1016
1017#define I915_OVERLAY_SWAP_MASK 0xff0000
1018#define I915_OVERLAY_NO_SWAP 0x000000
1019#define I915_OVERLAY_UV_SWAP 0x010000
1020#define I915_OVERLAY_Y_SWAP 0x020000
1021#define I915_OVERLAY_Y_AND_UV_SWAP 0x030000
1022
1023#define I915_OVERLAY_FLAGS_MASK 0xff000000
1024#define I915_OVERLAY_ENABLE 0x01000000
1025
1026struct drm_intel_overlay_put_image {
1027
1028 __u32 flags;
1029
1030 __u32 bo_handle;
1031
1032 __u16 stride_Y;
1033 __u16 stride_UV;
1034 __u32 offset_Y;
1035 __u32 offset_U;
1036 __u32 offset_V;
1037
1038 __u16 src_width;
1039 __u16 src_height;
1040
1041 __u16 src_scan_width;
1042 __u16 src_scan_height;
1043
1044 __u32 crtc_id;
1045 __u16 dst_x;
1046 __u16 dst_y;
1047 __u16 dst_width;
1048 __u16 dst_height;
1049};
1050
1051
1052#define I915_OVERLAY_UPDATE_ATTRS (1<<0)
1053#define I915_OVERLAY_UPDATE_GAMMA (1<<1)
1054#define I915_OVERLAY_DISABLE_DEST_COLORKEY (1<<2)
1055struct drm_intel_overlay_attrs {
1056 __u32 flags;
1057 __u32 color_key;
1058 __s32 brightness;
1059 __u32 contrast;
1060 __u32 saturation;
1061 __u32 gamma0;
1062 __u32 gamma1;
1063 __u32 gamma2;
1064 __u32 gamma3;
1065 __u32 gamma4;
1066 __u32 gamma5;
1067};
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090#define I915_SET_COLORKEY_NONE (1<<0)
1091#define I915_SET_COLORKEY_DESTINATION (1<<1)
1092#define I915_SET_COLORKEY_SOURCE (1<<2)
1093struct drm_intel_sprite_colorkey {
1094 __u32 plane_id;
1095 __u32 min_value;
1096 __u32 channel_mask;
1097 __u32 max_value;
1098 __u32 flags;
1099};
1100
1101struct drm_i915_gem_wait {
1102
1103 __u32 bo_handle;
1104 __u32 flags;
1105
1106 __s64 timeout_ns;
1107};
1108
1109struct drm_i915_gem_context_create {
1110
1111 __u32 ctx_id;
1112 __u32 pad;
1113};
1114
1115struct drm_i915_gem_context_destroy {
1116 __u32 ctx_id;
1117 __u32 pad;
1118};
1119
1120struct drm_i915_reg_read {
1121
1122
1123
1124
1125
1126
1127 __u64 offset;
1128 __u64 val;
1129};
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139struct drm_i915_reset_stats {
1140 __u32 ctx_id;
1141 __u32 flags;
1142
1143
1144 __u32 reset_count;
1145
1146
1147 __u32 batch_active;
1148
1149
1150 __u32 batch_pending;
1151
1152 __u32 pad;
1153};
1154
1155struct drm_i915_gem_userptr {
1156 __u64 user_ptr;
1157 __u64 user_size;
1158 __u32 flags;
1159#define I915_USERPTR_READ_ONLY 0x1
1160#define I915_USERPTR_UNSYNCHRONIZED 0x80000000
1161
1162
1163
1164
1165
1166 __u32 handle;
1167};
1168
1169struct drm_i915_gem_context_param {
1170 __u32 ctx_id;
1171 __u32 size;
1172 __u64 param;
1173#define I915_CONTEXT_PARAM_BAN_PERIOD 0x1
1174#define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2
1175#define I915_CONTEXT_PARAM_GTT_SIZE 0x3
1176#define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4
1177 __u64 value;
1178};
1179
1180#if defined(__cplusplus)
1181}
1182#endif
1183
1184#endif
1185