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128#undef DEBUG
129
130#include <linux/kernel.h>
131#include <linux/errno.h>
132#include <linux/io.h>
133#include <linux/clk.h>
134#include <linux/clk-provider.h>
135#include <linux/delay.h>
136#include <linux/err.h>
137#include <linux/list.h>
138#include <linux/mutex.h>
139#include <linux/spinlock.h>
140#include <linux/slab.h>
141#include <linux/bootmem.h>
142#include <linux/cpu.h>
143#include <linux/of.h>
144#include <linux/of_address.h>
145
146#include <asm/system_misc.h>
147
148#include "clock.h"
149#include "omap_hwmod.h"
150
151#include "soc.h"
152#include "common.h"
153#include "clockdomain.h"
154#include "powerdomain.h"
155#include "cm2xxx.h"
156#include "cm3xxx.h"
157#include "cm33xx.h"
158#include "prm.h"
159#include "prm3xxx.h"
160#include "prm44xx.h"
161#include "prm33xx.h"
162#include "prminst44xx.h"
163#include "mux.h"
164#include "pm.h"
165
166
167#define MPU_INITIATOR_NAME "mpu"
168
169
170
171
172
173#define LINKS_PER_OCP_IF 2
174
175
176
177
178
179#define OMAP4_RST_CTRL_ST_OFFSET 4
180
181
182
183
184#define MOD_CLK_MAX_NAME_LEN 32
185
186
187
188
189
190
191
192
193
194
195struct omap_hwmod_soc_ops {
196 void (*enable_module)(struct omap_hwmod *oh);
197 int (*disable_module)(struct omap_hwmod *oh);
198 int (*wait_target_ready)(struct omap_hwmod *oh);
199 int (*assert_hardreset)(struct omap_hwmod *oh,
200 struct omap_hwmod_rst_info *ohri);
201 int (*deassert_hardreset)(struct omap_hwmod *oh,
202 struct omap_hwmod_rst_info *ohri);
203 int (*is_hardreset_asserted)(struct omap_hwmod *oh,
204 struct omap_hwmod_rst_info *ohri);
205 int (*init_clkdm)(struct omap_hwmod *oh);
206 void (*update_context_lost)(struct omap_hwmod *oh);
207 int (*get_context_lost)(struct omap_hwmod *oh);
208 int (*disable_direct_prcm)(struct omap_hwmod *oh);
209};
210
211
212static struct omap_hwmod_soc_ops soc_ops;
213
214
215static LIST_HEAD(omap_hwmod_list);
216
217
218static struct omap_hwmod *mpu_oh;
219
220
221static DEFINE_SPINLOCK(io_chain_lock);
222
223
224
225
226
227
228static struct omap_hwmod_link *linkspace;
229
230
231
232
233
234
235static unsigned short free_ls, max_ls, ls_supp;
236
237
238static bool inited;
239
240
241
242
243
244
245
246
247
248
249
250
251
252static struct omap_hwmod_ocp_if *_fetch_next_ocp_if(struct list_head **p,
253 int *i)
254{
255 struct omap_hwmod_ocp_if *oi;
256
257 oi = list_entry(*p, struct omap_hwmod_link, node)->ocp_if;
258 *p = (*p)->next;
259
260 *i = *i + 1;
261
262 return oi;
263}
264
265
266
267
268
269
270
271
272
273static int _update_sysc_cache(struct omap_hwmod *oh)
274{
275 if (!oh->class->sysc) {
276 WARN(1, "omap_hwmod: %s: cannot read OCP_SYSCONFIG: not defined on hwmod's class\n", oh->name);
277 return -EINVAL;
278 }
279
280
281
282 oh->_sysc_cache = omap_hwmod_read(oh, oh->class->sysc->sysc_offs);
283
284 if (!(oh->class->sysc->sysc_flags & SYSC_NO_CACHE))
285 oh->_int_flags |= _HWMOD_SYSCONFIG_LOADED;
286
287 return 0;
288}
289
290
291
292
293
294
295
296
297
298static void _write_sysconfig(u32 v, struct omap_hwmod *oh)
299{
300 if (!oh->class->sysc) {
301 WARN(1, "omap_hwmod: %s: cannot write OCP_SYSCONFIG: not defined on hwmod's class\n", oh->name);
302 return;
303 }
304
305
306
307
308 oh->_sysc_cache = v;
309
310
311
312
313
314
315
316 if (oh->class->unlock)
317 oh->class->unlock(oh);
318
319 omap_hwmod_write(v, oh, oh->class->sysc->sysc_offs);
320
321 if (oh->class->lock)
322 oh->class->lock(oh);
323}
324
325
326
327
328
329
330
331
332
333
334
335static int _set_master_standbymode(struct omap_hwmod *oh, u8 standbymode,
336 u32 *v)
337{
338 u32 mstandby_mask;
339 u8 mstandby_shift;
340
341 if (!oh->class->sysc ||
342 !(oh->class->sysc->sysc_flags & SYSC_HAS_MIDLEMODE))
343 return -EINVAL;
344
345 if (!oh->class->sysc->sysc_fields) {
346 WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
347 return -EINVAL;
348 }
349
350 mstandby_shift = oh->class->sysc->sysc_fields->midle_shift;
351 mstandby_mask = (0x3 << mstandby_shift);
352
353 *v &= ~mstandby_mask;
354 *v |= __ffs(standbymode) << mstandby_shift;
355
356 return 0;
357}
358
359
360
361
362
363
364
365
366
367
368
369static int _set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode, u32 *v)
370{
371 u32 sidle_mask;
372 u8 sidle_shift;
373
374 if (!oh->class->sysc ||
375 !(oh->class->sysc->sysc_flags & SYSC_HAS_SIDLEMODE))
376 return -EINVAL;
377
378 if (!oh->class->sysc->sysc_fields) {
379 WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
380 return -EINVAL;
381 }
382
383 sidle_shift = oh->class->sysc->sysc_fields->sidle_shift;
384 sidle_mask = (0x3 << sidle_shift);
385
386 *v &= ~sidle_mask;
387 *v |= __ffs(idlemode) << sidle_shift;
388
389 return 0;
390}
391
392
393
394
395
396
397
398
399
400
401
402
403static int _set_clockactivity(struct omap_hwmod *oh, u8 clockact, u32 *v)
404{
405 u32 clkact_mask;
406 u8 clkact_shift;
407
408 if (!oh->class->sysc ||
409 !(oh->class->sysc->sysc_flags & SYSC_HAS_CLOCKACTIVITY))
410 return -EINVAL;
411
412 if (!oh->class->sysc->sysc_fields) {
413 WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
414 return -EINVAL;
415 }
416
417 clkact_shift = oh->class->sysc->sysc_fields->clkact_shift;
418 clkact_mask = (0x3 << clkact_shift);
419
420 *v &= ~clkact_mask;
421 *v |= clockact << clkact_shift;
422
423 return 0;
424}
425
426
427
428
429
430
431
432
433
434static int _set_softreset(struct omap_hwmod *oh, u32 *v)
435{
436 u32 softrst_mask;
437
438 if (!oh->class->sysc ||
439 !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET))
440 return -EINVAL;
441
442 if (!oh->class->sysc->sysc_fields) {
443 WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
444 return -EINVAL;
445 }
446
447 softrst_mask = (0x1 << oh->class->sysc->sysc_fields->srst_shift);
448
449 *v |= softrst_mask;
450
451 return 0;
452}
453
454
455
456
457
458
459
460
461
462static int _clear_softreset(struct omap_hwmod *oh, u32 *v)
463{
464 u32 softrst_mask;
465
466 if (!oh->class->sysc ||
467 !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET))
468 return -EINVAL;
469
470 if (!oh->class->sysc->sysc_fields) {
471 WARN(1,
472 "omap_hwmod: %s: sysc_fields absent for sysconfig class\n",
473 oh->name);
474 return -EINVAL;
475 }
476
477 softrst_mask = (0x1 << oh->class->sysc->sysc_fields->srst_shift);
478
479 *v &= ~softrst_mask;
480
481 return 0;
482}
483
484
485
486
487
488
489
490
491
492
493
494static int _wait_softreset_complete(struct omap_hwmod *oh)
495{
496 struct omap_hwmod_class_sysconfig *sysc;
497 u32 softrst_mask;
498 int c = 0;
499
500 sysc = oh->class->sysc;
501
502 if (sysc->sysc_flags & SYSS_HAS_RESET_STATUS)
503 omap_test_timeout((omap_hwmod_read(oh, sysc->syss_offs)
504 & SYSS_RESETDONE_MASK),
505 MAX_MODULE_SOFTRESET_WAIT, c);
506 else if (sysc->sysc_flags & SYSC_HAS_RESET_STATUS) {
507 softrst_mask = (0x1 << sysc->sysc_fields->srst_shift);
508 omap_test_timeout(!(omap_hwmod_read(oh, sysc->sysc_offs)
509 & softrst_mask),
510 MAX_MODULE_SOFTRESET_WAIT, c);
511 }
512
513 return c;
514}
515
516
517
518
519
520
521
522
523
524
525
526
527
528static int _set_dmadisable(struct omap_hwmod *oh)
529{
530 u32 v;
531 u32 dmadisable_mask;
532
533 if (!oh->class->sysc ||
534 !(oh->class->sysc->sysc_flags & SYSC_HAS_DMADISABLE))
535 return -EINVAL;
536
537 if (!oh->class->sysc->sysc_fields) {
538 WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
539 return -EINVAL;
540 }
541
542
543 if (oh->_state != _HWMOD_STATE_ENABLED) {
544 pr_warn("omap_hwmod: %s: dma can be disabled only from enabled state\n", oh->name);
545 return -EINVAL;
546 }
547
548 pr_debug("omap_hwmod: %s: setting DMADISABLE\n", oh->name);
549
550 v = oh->_sysc_cache;
551 dmadisable_mask =
552 (0x1 << oh->class->sysc->sysc_fields->dmadisable_shift);
553 v |= dmadisable_mask;
554 _write_sysconfig(v, oh);
555
556 return 0;
557}
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle,
573 u32 *v)
574{
575 u32 autoidle_mask;
576 u8 autoidle_shift;
577
578 if (!oh->class->sysc ||
579 !(oh->class->sysc->sysc_flags & SYSC_HAS_AUTOIDLE))
580 return -EINVAL;
581
582 if (!oh->class->sysc->sysc_fields) {
583 WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
584 return -EINVAL;
585 }
586
587 autoidle_shift = oh->class->sysc->sysc_fields->autoidle_shift;
588 autoidle_mask = (0x1 << autoidle_shift);
589
590 *v &= ~autoidle_mask;
591 *v |= autoidle << autoidle_shift;
592
593 return 0;
594}
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610static void _set_idle_ioring_wakeup(struct omap_hwmod *oh, bool set_wake)
611{
612 struct omap_device_pad *pad;
613 bool change = false;
614 u16 prev_idle;
615 int j;
616
617 if (!oh->mux || !oh->mux->enabled)
618 return;
619
620 for (j = 0; j < oh->mux->nr_pads_dynamic; j++) {
621 pad = oh->mux->pads_dynamic[j];
622
623 if (!(pad->flags & OMAP_DEVICE_PAD_WAKEUP))
624 continue;
625
626 prev_idle = pad->idle;
627
628 if (set_wake)
629 pad->idle |= OMAP_WAKEUP_EN;
630 else
631 pad->idle &= ~OMAP_WAKEUP_EN;
632
633 if (prev_idle != pad->idle)
634 change = true;
635 }
636
637 if (change && oh->_state == _HWMOD_STATE_IDLE)
638 omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE);
639}
640
641
642
643
644
645
646
647
648static int _enable_wakeup(struct omap_hwmod *oh, u32 *v)
649{
650 if (!oh->class->sysc ||
651 !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) ||
652 (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) ||
653 (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)))
654 return -EINVAL;
655
656 if (!oh->class->sysc->sysc_fields) {
657 WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
658 return -EINVAL;
659 }
660
661 if (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)
662 *v |= 0x1 << oh->class->sysc->sysc_fields->enwkup_shift;
663
664 if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)
665 _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART_WKUP, v);
666 if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)
667 _set_master_standbymode(oh, HWMOD_IDLEMODE_SMART_WKUP, v);
668
669
670
671 return 0;
672}
673
674
675
676
677
678
679
680
681static int _disable_wakeup(struct omap_hwmod *oh, u32 *v)
682{
683 if (!oh->class->sysc ||
684 !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) ||
685 (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) ||
686 (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)))
687 return -EINVAL;
688
689 if (!oh->class->sysc->sysc_fields) {
690 WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
691 return -EINVAL;
692 }
693
694 if (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)
695 *v &= ~(0x1 << oh->class->sysc->sysc_fields->enwkup_shift);
696
697 if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)
698 _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART, v);
699 if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)
700 _set_master_standbymode(oh, HWMOD_IDLEMODE_SMART, v);
701
702
703
704 return 0;
705}
706
707static struct clockdomain *_get_clkdm(struct omap_hwmod *oh)
708{
709 struct clk_hw_omap *clk;
710
711 if (oh->clkdm) {
712 return oh->clkdm;
713 } else if (oh->_clk) {
714 if (__clk_get_flags(oh->_clk) & CLK_IS_BASIC)
715 return NULL;
716 clk = to_clk_hw_omap(__clk_get_hw(oh->_clk));
717 return clk->clkdm;
718 }
719 return NULL;
720}
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh)
736{
737 struct clockdomain *clkdm, *init_clkdm;
738
739 clkdm = _get_clkdm(oh);
740 init_clkdm = _get_clkdm(init_oh);
741
742 if (!clkdm || !init_clkdm)
743 return -EINVAL;
744
745 if (clkdm && clkdm->flags & CLKDM_NO_AUTODEPS)
746 return 0;
747
748 return clkdm_add_sleepdep(clkdm, init_clkdm);
749}
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh)
765{
766 struct clockdomain *clkdm, *init_clkdm;
767
768 clkdm = _get_clkdm(oh);
769 init_clkdm = _get_clkdm(init_oh);
770
771 if (!clkdm || !init_clkdm)
772 return -EINVAL;
773
774 if (clkdm && clkdm->flags & CLKDM_NO_AUTODEPS)
775 return 0;
776
777 return clkdm_del_sleepdep(clkdm, init_clkdm);
778}
779
780
781
782
783
784
785
786
787
788static int _init_main_clk(struct omap_hwmod *oh)
789{
790 int ret = 0;
791 char name[MOD_CLK_MAX_NAME_LEN];
792 struct clk *clk;
793
794
795 if (strlen(oh->name) + 7 > MOD_CLK_MAX_NAME_LEN)
796 pr_warn("%s: warning: cropping name for %s\n", __func__,
797 oh->name);
798
799 strncpy(name, oh->name, MOD_CLK_MAX_NAME_LEN - 7);
800 strcat(name, "_mod_ck");
801
802 clk = clk_get(NULL, name);
803 if (!IS_ERR(clk)) {
804 oh->_clk = clk;
805 soc_ops.disable_direct_prcm(oh);
806 oh->main_clk = kstrdup(name, GFP_KERNEL);
807 } else {
808 if (!oh->main_clk)
809 return 0;
810
811 oh->_clk = clk_get(NULL, oh->main_clk);
812 }
813
814 if (IS_ERR(oh->_clk)) {
815 pr_warn("omap_hwmod: %s: cannot clk_get main_clk %s\n",
816 oh->name, oh->main_clk);
817 return -EINVAL;
818 }
819
820
821
822
823
824
825
826
827 clk_prepare(oh->_clk);
828
829 if (!_get_clkdm(oh))
830 pr_debug("omap_hwmod: %s: missing clockdomain for %s.\n",
831 oh->name, oh->main_clk);
832
833 return ret;
834}
835
836
837
838
839
840
841
842
843static int _init_interface_clks(struct omap_hwmod *oh)
844{
845 struct omap_hwmod_ocp_if *os;
846 struct list_head *p;
847 struct clk *c;
848 int i = 0;
849 int ret = 0;
850
851 p = oh->slave_ports.next;
852
853 while (i < oh->slaves_cnt) {
854 os = _fetch_next_ocp_if(&p, &i);
855 if (!os->clk)
856 continue;
857
858 c = clk_get(NULL, os->clk);
859 if (IS_ERR(c)) {
860 pr_warn("omap_hwmod: %s: cannot clk_get interface_clk %s\n",
861 oh->name, os->clk);
862 ret = -EINVAL;
863 continue;
864 }
865 os->_clk = c;
866
867
868
869
870
871
872
873
874 clk_prepare(os->_clk);
875 }
876
877 return ret;
878}
879
880
881
882
883
884
885
886
887static int _init_opt_clks(struct omap_hwmod *oh)
888{
889 struct omap_hwmod_opt_clk *oc;
890 struct clk *c;
891 int i;
892 int ret = 0;
893
894 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) {
895 c = clk_get(NULL, oc->clk);
896 if (IS_ERR(c)) {
897 pr_warn("omap_hwmod: %s: cannot clk_get opt_clk %s\n",
898 oh->name, oc->clk);
899 ret = -EINVAL;
900 continue;
901 }
902 oc->_clk = c;
903
904
905
906
907
908
909
910
911 clk_prepare(oc->_clk);
912 }
913
914 return ret;
915}
916
917static void _enable_optional_clocks(struct omap_hwmod *oh)
918{
919 struct omap_hwmod_opt_clk *oc;
920 int i;
921
922 pr_debug("omap_hwmod: %s: enabling optional clocks\n", oh->name);
923
924 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
925 if (oc->_clk) {
926 pr_debug("omap_hwmod: enable %s:%s\n", oc->role,
927 __clk_get_name(oc->_clk));
928 clk_enable(oc->_clk);
929 }
930}
931
932static void _disable_optional_clocks(struct omap_hwmod *oh)
933{
934 struct omap_hwmod_opt_clk *oc;
935 int i;
936
937 pr_debug("omap_hwmod: %s: disabling optional clocks\n", oh->name);
938
939 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
940 if (oc->_clk) {
941 pr_debug("omap_hwmod: disable %s:%s\n", oc->role,
942 __clk_get_name(oc->_clk));
943 clk_disable(oc->_clk);
944 }
945}
946
947
948
949
950
951
952
953
954static int _enable_clocks(struct omap_hwmod *oh)
955{
956 struct omap_hwmod_ocp_if *os;
957 struct list_head *p;
958 int i = 0;
959
960 pr_debug("omap_hwmod: %s: enabling clocks\n", oh->name);
961
962 if (oh->_clk)
963 clk_enable(oh->_clk);
964
965 p = oh->slave_ports.next;
966
967 while (i < oh->slaves_cnt) {
968 os = _fetch_next_ocp_if(&p, &i);
969
970 if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE))
971 clk_enable(os->_clk);
972 }
973
974 if (oh->flags & HWMOD_OPT_CLKS_NEEDED)
975 _enable_optional_clocks(oh);
976
977
978
979 return 0;
980}
981
982
983
984
985
986
987
988static int _disable_clocks(struct omap_hwmod *oh)
989{
990 struct omap_hwmod_ocp_if *os;
991 struct list_head *p;
992 int i = 0;
993
994 pr_debug("omap_hwmod: %s: disabling clocks\n", oh->name);
995
996 if (oh->_clk)
997 clk_disable(oh->_clk);
998
999 p = oh->slave_ports.next;
1000
1001 while (i < oh->slaves_cnt) {
1002 os = _fetch_next_ocp_if(&p, &i);
1003
1004 if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE))
1005 clk_disable(os->_clk);
1006 }
1007
1008 if (oh->flags & HWMOD_OPT_CLKS_NEEDED)
1009 _disable_optional_clocks(oh);
1010
1011
1012
1013 return 0;
1014}
1015
1016
1017
1018
1019
1020
1021
1022
1023static void _omap4_enable_module(struct omap_hwmod *oh)
1024{
1025 if (!oh->clkdm || !oh->prcm.omap4.modulemode)
1026 return;
1027
1028 pr_debug("omap_hwmod: %s: %s: %d\n",
1029 oh->name, __func__, oh->prcm.omap4.modulemode);
1030
1031 omap_cm_module_enable(oh->prcm.omap4.modulemode,
1032 oh->clkdm->prcm_partition,
1033 oh->clkdm->cm_inst, oh->prcm.omap4.clkctrl_offs);
1034}
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045static int _omap4_wait_target_disable(struct omap_hwmod *oh)
1046{
1047 if (!oh)
1048 return -EINVAL;
1049
1050 if (oh->_int_flags & _HWMOD_NO_MPU_PORT || !oh->clkdm)
1051 return 0;
1052
1053 if (oh->flags & HWMOD_NO_IDLEST)
1054 return 0;
1055
1056 if (!oh->prcm.omap4.clkctrl_offs &&
1057 !(oh->prcm.omap4.flags & HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET))
1058 return 0;
1059
1060 return omap_cm_wait_module_idle(oh->clkdm->prcm_partition,
1061 oh->clkdm->cm_inst,
1062 oh->prcm.omap4.clkctrl_offs, 0);
1063}
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073static int _count_mpu_irqs(struct omap_hwmod *oh)
1074{
1075 struct omap_hwmod_irq_info *ohii;
1076 int i = 0;
1077
1078 if (!oh || !oh->mpu_irqs)
1079 return 0;
1080
1081 do {
1082 ohii = &oh->mpu_irqs[i++];
1083 } while (ohii->irq != -1);
1084
1085 return i-1;
1086}
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096static int _count_sdma_reqs(struct omap_hwmod *oh)
1097{
1098 struct omap_hwmod_dma_info *ohdi;
1099 int i = 0;
1100
1101 if (!oh || !oh->sdma_reqs)
1102 return 0;
1103
1104 do {
1105 ohdi = &oh->sdma_reqs[i++];
1106 } while (ohdi->dma_req != -1);
1107
1108 return i-1;
1109}
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119static int _count_ocp_if_addr_spaces(struct omap_hwmod_ocp_if *os)
1120{
1121 struct omap_hwmod_addr_space *mem;
1122 int i = 0;
1123
1124 if (!os || !os->addr)
1125 return 0;
1126
1127 do {
1128 mem = &os->addr[i++];
1129 } while (mem->pa_start != mem->pa_end);
1130
1131 return i-1;
1132}
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151static int _get_mpu_irq_by_name(struct omap_hwmod *oh, const char *name,
1152 unsigned int *irq)
1153{
1154 int i;
1155 bool found = false;
1156
1157 if (!oh->mpu_irqs)
1158 return -ENOENT;
1159
1160 i = 0;
1161 while (oh->mpu_irqs[i].irq != -1) {
1162 if (name == oh->mpu_irqs[i].name ||
1163 !strcmp(name, oh->mpu_irqs[i].name)) {
1164 found = true;
1165 break;
1166 }
1167 i++;
1168 }
1169
1170 if (!found)
1171 return -ENOENT;
1172
1173 *irq = oh->mpu_irqs[i].irq;
1174
1175 return 0;
1176}
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194static int _get_sdma_req_by_name(struct omap_hwmod *oh, const char *name,
1195 unsigned int *dma)
1196{
1197 int i;
1198 bool found = false;
1199
1200 if (!oh->sdma_reqs)
1201 return -ENOENT;
1202
1203 i = 0;
1204 while (oh->sdma_reqs[i].dma_req != -1) {
1205 if (name == oh->sdma_reqs[i].name ||
1206 !strcmp(name, oh->sdma_reqs[i].name)) {
1207 found = true;
1208 break;
1209 }
1210 i++;
1211 }
1212
1213 if (!found)
1214 return -ENOENT;
1215
1216 *dma = oh->sdma_reqs[i].dma_req;
1217
1218 return 0;
1219}
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239static int _get_addr_space_by_name(struct omap_hwmod *oh, const char *name,
1240 u32 *pa_start, u32 *pa_end)
1241{
1242 int i, j;
1243 struct omap_hwmod_ocp_if *os;
1244 struct list_head *p = NULL;
1245 bool found = false;
1246
1247 p = oh->slave_ports.next;
1248
1249 i = 0;
1250 while (i < oh->slaves_cnt) {
1251 os = _fetch_next_ocp_if(&p, &i);
1252
1253 if (!os->addr)
1254 return -ENOENT;
1255
1256 j = 0;
1257 while (os->addr[j].pa_start != os->addr[j].pa_end) {
1258 if (name == os->addr[j].name ||
1259 !strcmp(name, os->addr[j].name)) {
1260 found = true;
1261 break;
1262 }
1263 j++;
1264 }
1265
1266 if (found)
1267 break;
1268 }
1269
1270 if (!found)
1271 return -ENOENT;
1272
1273 *pa_start = os->addr[j].pa_start;
1274 *pa_end = os->addr[j].pa_end;
1275
1276 return 0;
1277}
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288static void __init _save_mpu_port_index(struct omap_hwmod *oh)
1289{
1290 struct omap_hwmod_ocp_if *os = NULL;
1291 struct list_head *p;
1292 int i = 0;
1293
1294 if (!oh)
1295 return;
1296
1297 oh->_int_flags |= _HWMOD_NO_MPU_PORT;
1298
1299 p = oh->slave_ports.next;
1300
1301 while (i < oh->slaves_cnt) {
1302 os = _fetch_next_ocp_if(&p, &i);
1303 if (os->user & OCP_USER_MPU) {
1304 oh->_mpu_port = os;
1305 oh->_int_flags &= ~_HWMOD_NO_MPU_PORT;
1306 break;
1307 }
1308 }
1309
1310 return;
1311}
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326static struct omap_hwmod_ocp_if *_find_mpu_rt_port(struct omap_hwmod *oh)
1327{
1328 if (!oh || oh->_int_flags & _HWMOD_NO_MPU_PORT || oh->slaves_cnt == 0)
1329 return NULL;
1330
1331 return oh->_mpu_port;
1332};
1333
1334
1335
1336
1337
1338
1339
1340
1341static struct omap_hwmod_addr_space * __init _find_mpu_rt_addr_space(struct omap_hwmod *oh)
1342{
1343 struct omap_hwmod_ocp_if *os;
1344 struct omap_hwmod_addr_space *mem;
1345 int found = 0, i = 0;
1346
1347 os = _find_mpu_rt_port(oh);
1348 if (!os || !os->addr)
1349 return NULL;
1350
1351 do {
1352 mem = &os->addr[i++];
1353 if (mem->flags & ADDR_TYPE_RT)
1354 found = 1;
1355 } while (!found && mem->pa_start != mem->pa_end);
1356
1357 return (found) ? mem : NULL;
1358}
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371static void _enable_sysc(struct omap_hwmod *oh)
1372{
1373 u8 idlemode, sf;
1374 u32 v;
1375 bool clkdm_act;
1376 struct clockdomain *clkdm;
1377
1378 if (!oh->class->sysc)
1379 return;
1380
1381
1382
1383
1384
1385
1386
1387 if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET)
1388 _enable_optional_clocks(oh);
1389 _wait_softreset_complete(oh);
1390 if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET)
1391 _disable_optional_clocks(oh);
1392
1393 v = oh->_sysc_cache;
1394 sf = oh->class->sysc->sysc_flags;
1395
1396 clkdm = _get_clkdm(oh);
1397 if (sf & SYSC_HAS_SIDLEMODE) {
1398 if (oh->flags & HWMOD_SWSUP_SIDLE ||
1399 oh->flags & HWMOD_SWSUP_SIDLE_ACT) {
1400 idlemode = HWMOD_IDLEMODE_NO;
1401 } else {
1402 if (sf & SYSC_HAS_ENAWAKEUP)
1403 _enable_wakeup(oh, &v);
1404 if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)
1405 idlemode = HWMOD_IDLEMODE_SMART_WKUP;
1406 else
1407 idlemode = HWMOD_IDLEMODE_SMART;
1408 }
1409
1410
1411
1412
1413
1414 clkdm_act = (clkdm && clkdm->flags & CLKDM_ACTIVE_WITH_MPU);
1415 if (clkdm_act && !(oh->class->sysc->idlemodes &
1416 (SIDLE_SMART | SIDLE_SMART_WKUP)))
1417 idlemode = HWMOD_IDLEMODE_FORCE;
1418
1419 _set_slave_idlemode(oh, idlemode, &v);
1420 }
1421
1422 if (sf & SYSC_HAS_MIDLEMODE) {
1423 if (oh->flags & HWMOD_FORCE_MSTANDBY) {
1424 idlemode = HWMOD_IDLEMODE_FORCE;
1425 } else if (oh->flags & HWMOD_SWSUP_MSTANDBY) {
1426 idlemode = HWMOD_IDLEMODE_NO;
1427 } else {
1428 if (sf & SYSC_HAS_ENAWAKEUP)
1429 _enable_wakeup(oh, &v);
1430 if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)
1431 idlemode = HWMOD_IDLEMODE_SMART_WKUP;
1432 else
1433 idlemode = HWMOD_IDLEMODE_SMART;
1434 }
1435 _set_master_standbymode(oh, idlemode, &v);
1436 }
1437
1438
1439
1440
1441
1442
1443 if ((oh->flags & HWMOD_SET_DEFAULT_CLOCKACT) &&
1444 (sf & SYSC_HAS_CLOCKACTIVITY))
1445 _set_clockactivity(oh, oh->class->sysc->clockact, &v);
1446
1447 _write_sysconfig(v, oh);
1448
1449
1450
1451
1452
1453 if (sf & SYSC_HAS_AUTOIDLE) {
1454 idlemode = (oh->flags & HWMOD_NO_OCP_AUTOIDLE) ?
1455 0 : 1;
1456 _set_module_autoidle(oh, idlemode, &v);
1457 _write_sysconfig(v, oh);
1458 }
1459}
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470static void _idle_sysc(struct omap_hwmod *oh)
1471{
1472 u8 idlemode, sf;
1473 u32 v;
1474
1475 if (!oh->class->sysc)
1476 return;
1477
1478 v = oh->_sysc_cache;
1479 sf = oh->class->sysc->sysc_flags;
1480
1481 if (sf & SYSC_HAS_SIDLEMODE) {
1482 if (oh->flags & HWMOD_SWSUP_SIDLE) {
1483 idlemode = HWMOD_IDLEMODE_FORCE;
1484 } else {
1485 if (sf & SYSC_HAS_ENAWAKEUP)
1486 _enable_wakeup(oh, &v);
1487 if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)
1488 idlemode = HWMOD_IDLEMODE_SMART_WKUP;
1489 else
1490 idlemode = HWMOD_IDLEMODE_SMART;
1491 }
1492 _set_slave_idlemode(oh, idlemode, &v);
1493 }
1494
1495 if (sf & SYSC_HAS_MIDLEMODE) {
1496 if ((oh->flags & HWMOD_SWSUP_MSTANDBY) ||
1497 (oh->flags & HWMOD_FORCE_MSTANDBY)) {
1498 idlemode = HWMOD_IDLEMODE_FORCE;
1499 } else {
1500 if (sf & SYSC_HAS_ENAWAKEUP)
1501 _enable_wakeup(oh, &v);
1502 if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)
1503 idlemode = HWMOD_IDLEMODE_SMART_WKUP;
1504 else
1505 idlemode = HWMOD_IDLEMODE_SMART;
1506 }
1507 _set_master_standbymode(oh, idlemode, &v);
1508 }
1509
1510
1511 if (oh->_sysc_cache != v)
1512 _write_sysconfig(v, oh);
1513}
1514
1515
1516
1517
1518
1519
1520
1521
1522static void _shutdown_sysc(struct omap_hwmod *oh)
1523{
1524 u32 v;
1525 u8 sf;
1526
1527 if (!oh->class->sysc)
1528 return;
1529
1530 v = oh->_sysc_cache;
1531 sf = oh->class->sysc->sysc_flags;
1532
1533 if (sf & SYSC_HAS_SIDLEMODE)
1534 _set_slave_idlemode(oh, HWMOD_IDLEMODE_FORCE, &v);
1535
1536 if (sf & SYSC_HAS_MIDLEMODE)
1537 _set_master_standbymode(oh, HWMOD_IDLEMODE_FORCE, &v);
1538
1539 if (sf & SYSC_HAS_AUTOIDLE)
1540 _set_module_autoidle(oh, 1, &v);
1541
1542 _write_sysconfig(v, oh);
1543}
1544
1545
1546
1547
1548
1549
1550
1551static struct omap_hwmod *_lookup(const char *name)
1552{
1553 struct omap_hwmod *oh, *temp_oh;
1554
1555 oh = NULL;
1556
1557 list_for_each_entry(temp_oh, &omap_hwmod_list, node) {
1558 if (!strcmp(name, temp_oh->name)) {
1559 oh = temp_oh;
1560 break;
1561 }
1562 }
1563
1564 return oh;
1565}
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575static int _init_clkdm(struct omap_hwmod *oh)
1576{
1577 if (!oh->clkdm_name) {
1578 pr_debug("omap_hwmod: %s: missing clockdomain\n", oh->name);
1579 return 0;
1580 }
1581
1582 oh->clkdm = clkdm_lookup(oh->clkdm_name);
1583 if (!oh->clkdm) {
1584 pr_warn("omap_hwmod: %s: could not associate to clkdm %s\n",
1585 oh->name, oh->clkdm_name);
1586 return 0;
1587 }
1588
1589 pr_debug("omap_hwmod: %s: associated to clkdm %s\n",
1590 oh->name, oh->clkdm_name);
1591
1592 return 0;
1593}
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605static int _init_clocks(struct omap_hwmod *oh, void *data)
1606{
1607 int ret = 0;
1608
1609 if (oh->_state != _HWMOD_STATE_REGISTERED)
1610 return 0;
1611
1612 pr_debug("omap_hwmod: %s: looking up clocks\n", oh->name);
1613
1614 if (soc_ops.init_clkdm)
1615 ret |= soc_ops.init_clkdm(oh);
1616
1617 ret |= _init_main_clk(oh);
1618 ret |= _init_interface_clks(oh);
1619 ret |= _init_opt_clks(oh);
1620
1621 if (!ret)
1622 oh->_state = _HWMOD_STATE_CLKS_INITED;
1623 else
1624 pr_warn("omap_hwmod: %s: cannot _init_clocks\n", oh->name);
1625
1626 return ret;
1627}
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638static int _lookup_hardreset(struct omap_hwmod *oh, const char *name,
1639 struct omap_hwmod_rst_info *ohri)
1640{
1641 int i;
1642
1643 for (i = 0; i < oh->rst_lines_cnt; i++) {
1644 const char *rst_line = oh->rst_lines[i].name;
1645 if (!strcmp(rst_line, name)) {
1646 ohri->rst_shift = oh->rst_lines[i].rst_shift;
1647 ohri->st_shift = oh->rst_lines[i].st_shift;
1648 pr_debug("omap_hwmod: %s: %s: %s: rst %d st %d\n",
1649 oh->name, __func__, rst_line, ohri->rst_shift,
1650 ohri->st_shift);
1651
1652 return 0;
1653 }
1654 }
1655
1656 return -ENOENT;
1657}
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672static int _assert_hardreset(struct omap_hwmod *oh, const char *name)
1673{
1674 struct omap_hwmod_rst_info ohri;
1675 int ret = -EINVAL;
1676
1677 if (!oh)
1678 return -EINVAL;
1679
1680 if (!soc_ops.assert_hardreset)
1681 return -ENOSYS;
1682
1683 ret = _lookup_hardreset(oh, name, &ohri);
1684 if (ret < 0)
1685 return ret;
1686
1687 ret = soc_ops.assert_hardreset(oh, &ohri);
1688
1689 return ret;
1690}
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
1706{
1707 struct omap_hwmod_rst_info ohri;
1708 int ret = -EINVAL;
1709
1710 if (!oh)
1711 return -EINVAL;
1712
1713 if (!soc_ops.deassert_hardreset)
1714 return -ENOSYS;
1715
1716 ret = _lookup_hardreset(oh, name, &ohri);
1717 if (ret < 0)
1718 return ret;
1719
1720 if (oh->clkdm) {
1721
1722
1723
1724
1725
1726 clkdm_deny_idle(oh->clkdm);
1727 ret = clkdm_hwmod_enable(oh->clkdm, oh);
1728 if (ret) {
1729 WARN(1, "omap_hwmod: %s: could not enable clockdomain %s: %d\n",
1730 oh->name, oh->clkdm->name, ret);
1731 return ret;
1732 }
1733 }
1734
1735 _enable_clocks(oh);
1736 if (soc_ops.enable_module)
1737 soc_ops.enable_module(oh);
1738
1739 ret = soc_ops.deassert_hardreset(oh, &ohri);
1740
1741 if (soc_ops.disable_module)
1742 soc_ops.disable_module(oh);
1743 _disable_clocks(oh);
1744
1745 if (ret == -EBUSY)
1746 pr_warn("omap_hwmod: %s: failed to hardreset\n", oh->name);
1747
1748 if (oh->clkdm) {
1749
1750
1751
1752
1753 clkdm_allow_idle(oh->clkdm);
1754
1755 clkdm_hwmod_disable(oh->clkdm, oh);
1756 }
1757
1758 return ret;
1759}
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773static int _read_hardreset(struct omap_hwmod *oh, const char *name)
1774{
1775 struct omap_hwmod_rst_info ohri;
1776 int ret = -EINVAL;
1777
1778 if (!oh)
1779 return -EINVAL;
1780
1781 if (!soc_ops.is_hardreset_asserted)
1782 return -ENOSYS;
1783
1784 ret = _lookup_hardreset(oh, name, &ohri);
1785 if (ret < 0)
1786 return ret;
1787
1788 return soc_ops.is_hardreset_asserted(oh, &ohri);
1789}
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801static bool _are_all_hardreset_lines_asserted(struct omap_hwmod *oh)
1802{
1803 int i, rst_cnt = 0;
1804
1805 if (oh->rst_lines_cnt == 0)
1806 return false;
1807
1808 for (i = 0; i < oh->rst_lines_cnt; i++)
1809 if (_read_hardreset(oh, oh->rst_lines[i].name) > 0)
1810 rst_cnt++;
1811
1812 if (oh->rst_lines_cnt == rst_cnt)
1813 return true;
1814
1815 return false;
1816}
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829static bool _are_any_hardreset_lines_asserted(struct omap_hwmod *oh)
1830{
1831 int rst_cnt = 0;
1832 int i;
1833
1834 for (i = 0; i < oh->rst_lines_cnt && rst_cnt == 0; i++)
1835 if (_read_hardreset(oh, oh->rst_lines[i].name) > 0)
1836 rst_cnt++;
1837
1838 return (rst_cnt) ? true : false;
1839}
1840
1841
1842
1843
1844
1845
1846
1847
1848static int _omap4_disable_module(struct omap_hwmod *oh)
1849{
1850 int v;
1851
1852 if (!oh->clkdm || !oh->prcm.omap4.modulemode)
1853 return -EINVAL;
1854
1855
1856
1857
1858
1859 if (_are_any_hardreset_lines_asserted(oh))
1860 return 0;
1861
1862 pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__);
1863
1864 omap_cm_module_disable(oh->clkdm->prcm_partition, oh->clkdm->cm_inst,
1865 oh->prcm.omap4.clkctrl_offs);
1866
1867 v = _omap4_wait_target_disable(oh);
1868 if (v)
1869 pr_warn("omap_hwmod: %s: _wait_target_disable failed\n",
1870 oh->name);
1871
1872 return 0;
1873}
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891static int _ocp_softreset(struct omap_hwmod *oh)
1892{
1893 u32 v;
1894 int c = 0;
1895 int ret = 0;
1896
1897 if (!oh->class->sysc ||
1898 !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET))
1899 return -ENOENT;
1900
1901
1902 if (oh->_state != _HWMOD_STATE_ENABLED) {
1903 pr_warn("omap_hwmod: %s: reset can only be entered from enabled state\n",
1904 oh->name);
1905 return -EINVAL;
1906 }
1907
1908
1909 if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET)
1910 _enable_optional_clocks(oh);
1911
1912 pr_debug("omap_hwmod: %s: resetting via OCP SOFTRESET\n", oh->name);
1913
1914 v = oh->_sysc_cache;
1915 ret = _set_softreset(oh, &v);
1916 if (ret)
1917 goto dis_opt_clks;
1918
1919 _write_sysconfig(v, oh);
1920
1921 if (oh->class->sysc->srst_udelay)
1922 udelay(oh->class->sysc->srst_udelay);
1923
1924 c = _wait_softreset_complete(oh);
1925 if (c == MAX_MODULE_SOFTRESET_WAIT) {
1926 pr_warn("omap_hwmod: %s: softreset failed (waited %d usec)\n",
1927 oh->name, MAX_MODULE_SOFTRESET_WAIT);
1928 ret = -ETIMEDOUT;
1929 goto dis_opt_clks;
1930 } else {
1931 pr_debug("omap_hwmod: %s: softreset in %d usec\n", oh->name, c);
1932 }
1933
1934 ret = _clear_softreset(oh, &v);
1935 if (ret)
1936 goto dis_opt_clks;
1937
1938 _write_sysconfig(v, oh);
1939
1940
1941
1942
1943
1944
1945dis_opt_clks:
1946 if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET)
1947 _disable_optional_clocks(oh);
1948
1949 return ret;
1950}
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985static int _reset(struct omap_hwmod *oh)
1986{
1987 int i, r;
1988
1989 pr_debug("omap_hwmod: %s: resetting\n", oh->name);
1990
1991 if (oh->class->reset) {
1992 r = oh->class->reset(oh);
1993 } else {
1994 if (oh->rst_lines_cnt > 0) {
1995 for (i = 0; i < oh->rst_lines_cnt; i++)
1996 _assert_hardreset(oh, oh->rst_lines[i].name);
1997 return 0;
1998 } else {
1999 r = _ocp_softreset(oh);
2000 if (r == -ENOENT)
2001 r = 0;
2002 }
2003 }
2004
2005 _set_dmadisable(oh);
2006
2007
2008
2009
2010
2011
2012 if (oh->class->sysc) {
2013 _update_sysc_cache(oh);
2014 _enable_sysc(oh);
2015 }
2016
2017 return r;
2018}
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032static void _reconfigure_io_chain(void)
2033{
2034 unsigned long flags;
2035
2036 spin_lock_irqsave(&io_chain_lock, flags);
2037
2038 omap_prm_reconfigure_io_chain();
2039
2040 spin_unlock_irqrestore(&io_chain_lock, flags);
2041}
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052static void _omap4_update_context_lost(struct omap_hwmod *oh)
2053{
2054 if (oh->prcm.omap4.flags & HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT)
2055 return;
2056
2057 if (!prm_was_any_context_lost_old(oh->clkdm->pwrdm.ptr->prcm_partition,
2058 oh->clkdm->pwrdm.ptr->prcm_offs,
2059 oh->prcm.omap4.context_offs))
2060 return;
2061
2062 oh->prcm.omap4.context_lost_counter++;
2063 prm_clear_context_loss_flags_old(oh->clkdm->pwrdm.ptr->prcm_partition,
2064 oh->clkdm->pwrdm.ptr->prcm_offs,
2065 oh->prcm.omap4.context_offs);
2066}
2067
2068
2069
2070
2071
2072
2073
2074static int _omap4_get_context_lost(struct omap_hwmod *oh)
2075{
2076 return oh->prcm.omap4.context_lost_counter;
2077}
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088static int _enable_preprogram(struct omap_hwmod *oh)
2089{
2090 if (!oh->class->enable_preprogram)
2091 return 0;
2092
2093 return oh->class->enable_preprogram(oh);
2094}
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104static int _enable(struct omap_hwmod *oh)
2105{
2106 int r;
2107
2108 pr_debug("omap_hwmod: %s: enabling\n", oh->name);
2109
2110
2111
2112
2113
2114
2115 if (oh->_int_flags & _HWMOD_SKIP_ENABLE) {
2116
2117
2118
2119
2120
2121 if (oh->mux)
2122 omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED);
2123
2124 oh->_int_flags &= ~_HWMOD_SKIP_ENABLE;
2125 return 0;
2126 }
2127
2128 if (oh->_state != _HWMOD_STATE_INITIALIZED &&
2129 oh->_state != _HWMOD_STATE_IDLE &&
2130 oh->_state != _HWMOD_STATE_DISABLED) {
2131 WARN(1, "omap_hwmod: %s: enabled state can only be entered from initialized, idle, or disabled state\n",
2132 oh->name);
2133 return -EINVAL;
2134 }
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145 if (_are_all_hardreset_lines_asserted(oh))
2146 return 0;
2147
2148
2149 if (oh->mux && (!oh->mux->enabled ||
2150 ((oh->_state == _HWMOD_STATE_IDLE) &&
2151 oh->mux->pads_dynamic))) {
2152 omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED);
2153 _reconfigure_io_chain();
2154 } else if (oh->flags & HWMOD_RECONFIG_IO_CHAIN) {
2155 _reconfigure_io_chain();
2156 }
2157
2158 _add_initiator_dep(oh, mpu_oh);
2159
2160 if (oh->clkdm) {
2161
2162
2163
2164
2165
2166 clkdm_deny_idle(oh->clkdm);
2167 r = clkdm_hwmod_enable(oh->clkdm, oh);
2168 if (r) {
2169 WARN(1, "omap_hwmod: %s: could not enable clockdomain %s: %d\n",
2170 oh->name, oh->clkdm->name, r);
2171 return r;
2172 }
2173 }
2174
2175 _enable_clocks(oh);
2176 if (soc_ops.enable_module)
2177 soc_ops.enable_module(oh);
2178 if (oh->flags & HWMOD_BLOCK_WFI)
2179 cpu_idle_poll_ctrl(true);
2180
2181 if (soc_ops.update_context_lost)
2182 soc_ops.update_context_lost(oh);
2183
2184 r = (soc_ops.wait_target_ready) ? soc_ops.wait_target_ready(oh) :
2185 -EINVAL;
2186 if (oh->clkdm)
2187 clkdm_allow_idle(oh->clkdm);
2188
2189 if (!r) {
2190 oh->_state = _HWMOD_STATE_ENABLED;
2191
2192
2193 if (oh->class->sysc) {
2194 if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED))
2195 _update_sysc_cache(oh);
2196 _enable_sysc(oh);
2197 }
2198 r = _enable_preprogram(oh);
2199 } else {
2200 if (soc_ops.disable_module)
2201 soc_ops.disable_module(oh);
2202 _disable_clocks(oh);
2203 pr_err("omap_hwmod: %s: _wait_target_ready failed: %d\n",
2204 oh->name, r);
2205
2206 if (oh->clkdm)
2207 clkdm_hwmod_disable(oh->clkdm, oh);
2208 }
2209
2210 return r;
2211}
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221static int _idle(struct omap_hwmod *oh)
2222{
2223 if (oh->flags & HWMOD_NO_IDLE) {
2224 oh->_int_flags |= _HWMOD_SKIP_ENABLE;
2225 return 0;
2226 }
2227
2228 pr_debug("omap_hwmod: %s: idling\n", oh->name);
2229
2230 if (_are_all_hardreset_lines_asserted(oh))
2231 return 0;
2232
2233 if (oh->_state != _HWMOD_STATE_ENABLED) {
2234 WARN(1, "omap_hwmod: %s: idle state can only be entered from enabled state\n",
2235 oh->name);
2236 return -EINVAL;
2237 }
2238
2239 if (oh->class->sysc)
2240 _idle_sysc(oh);
2241 _del_initiator_dep(oh, mpu_oh);
2242
2243 if (oh->clkdm)
2244 clkdm_deny_idle(oh->clkdm);
2245
2246 if (oh->flags & HWMOD_BLOCK_WFI)
2247 cpu_idle_poll_ctrl(false);
2248 if (soc_ops.disable_module)
2249 soc_ops.disable_module(oh);
2250
2251
2252
2253
2254
2255
2256
2257 _disable_clocks(oh);
2258 if (oh->clkdm) {
2259 clkdm_allow_idle(oh->clkdm);
2260 clkdm_hwmod_disable(oh->clkdm, oh);
2261 }
2262
2263
2264 if (oh->mux && oh->mux->pads_dynamic) {
2265 omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE);
2266 _reconfigure_io_chain();
2267 } else if (oh->flags & HWMOD_RECONFIG_IO_CHAIN) {
2268 _reconfigure_io_chain();
2269 }
2270
2271 oh->_state = _HWMOD_STATE_IDLE;
2272
2273 return 0;
2274}
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285static int _shutdown(struct omap_hwmod *oh)
2286{
2287 int ret, i;
2288 u8 prev_state;
2289
2290 if (_are_all_hardreset_lines_asserted(oh))
2291 return 0;
2292
2293 if (oh->_state != _HWMOD_STATE_IDLE &&
2294 oh->_state != _HWMOD_STATE_ENABLED) {
2295 WARN(1, "omap_hwmod: %s: disabled state can only be entered from idle, or enabled state\n",
2296 oh->name);
2297 return -EINVAL;
2298 }
2299
2300 pr_debug("omap_hwmod: %s: disabling\n", oh->name);
2301
2302 if (oh->class->pre_shutdown) {
2303 prev_state = oh->_state;
2304 if (oh->_state == _HWMOD_STATE_IDLE)
2305 _enable(oh);
2306 ret = oh->class->pre_shutdown(oh);
2307 if (ret) {
2308 if (prev_state == _HWMOD_STATE_IDLE)
2309 _idle(oh);
2310 return ret;
2311 }
2312 }
2313
2314 if (oh->class->sysc) {
2315 if (oh->_state == _HWMOD_STATE_IDLE)
2316 _enable(oh);
2317 _shutdown_sysc(oh);
2318 }
2319
2320
2321 if (oh->_state == _HWMOD_STATE_ENABLED) {
2322 _del_initiator_dep(oh, mpu_oh);
2323
2324 if (oh->flags & HWMOD_BLOCK_WFI)
2325 cpu_idle_poll_ctrl(false);
2326 if (soc_ops.disable_module)
2327 soc_ops.disable_module(oh);
2328 _disable_clocks(oh);
2329 if (oh->clkdm)
2330 clkdm_hwmod_disable(oh->clkdm, oh);
2331 }
2332
2333
2334 for (i = 0; i < oh->rst_lines_cnt; i++)
2335 _assert_hardreset(oh, oh->rst_lines[i].name);
2336
2337
2338 if (oh->mux)
2339 omap_hwmod_mux(oh->mux, _HWMOD_STATE_DISABLED);
2340
2341 oh->_state = _HWMOD_STATE_DISABLED;
2342
2343 return 0;
2344}
2345
2346static int of_dev_find_hwmod(struct device_node *np,
2347 struct omap_hwmod *oh)
2348{
2349 int count, i, res;
2350 const char *p;
2351
2352 count = of_property_count_strings(np, "ti,hwmods");
2353 if (count < 1)
2354 return -ENODEV;
2355
2356 for (i = 0; i < count; i++) {
2357 res = of_property_read_string_index(np, "ti,hwmods",
2358 i, &p);
2359 if (res)
2360 continue;
2361 if (!strcmp(p, oh->name)) {
2362 pr_debug("omap_hwmod: dt %s[%i] uses hwmod %s\n",
2363 np->name, i, oh->name);
2364 return i;
2365 }
2366 }
2367
2368 return -ENODEV;
2369}
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382static int of_dev_hwmod_lookup(struct device_node *np,
2383 struct omap_hwmod *oh,
2384 int *index,
2385 struct device_node **found)
2386{
2387 struct device_node *np0 = NULL;
2388 int res;
2389
2390 res = of_dev_find_hwmod(np, oh);
2391 if (res >= 0) {
2392 *found = np;
2393 *index = res;
2394 return 0;
2395 }
2396
2397 for_each_child_of_node(np, np0) {
2398 struct device_node *fc;
2399 int i;
2400
2401 res = of_dev_hwmod_lookup(np0, oh, &i, &fc);
2402 if (res == 0) {
2403 *found = fc;
2404 *index = i;
2405 return 0;
2406 }
2407 }
2408
2409 *found = NULL;
2410 *index = 0;
2411
2412 return -ENODEV;
2413}
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432static int __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data,
2433 int index, struct device_node *np)
2434{
2435 struct omap_hwmod_addr_space *mem;
2436 void __iomem *va_start = NULL;
2437
2438 if (!oh)
2439 return -EINVAL;
2440
2441 _save_mpu_port_index(oh);
2442
2443
2444 if (!oh->class->sysc)
2445 return 0;
2446
2447
2448 if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
2449 return -ENXIO;
2450
2451 mem = _find_mpu_rt_addr_space(oh);
2452 if (!mem) {
2453 pr_debug("omap_hwmod: %s: no MPU register target found\n",
2454 oh->name);
2455
2456
2457 if (!np) {
2458 pr_err("omap_hwmod: %s: no dt node\n", oh->name);
2459 return -ENXIO;
2460 }
2461
2462 va_start = of_iomap(np, index + oh->mpu_rt_idx);
2463 } else {
2464 va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start);
2465 }
2466
2467 if (!va_start) {
2468 if (mem)
2469 pr_err("omap_hwmod: %s: Could not ioremap\n", oh->name);
2470 else
2471 pr_err("omap_hwmod: %s: Missing dt reg%i for %s\n",
2472 oh->name, index, np->full_name);
2473 return -ENXIO;
2474 }
2475
2476 pr_debug("omap_hwmod: %s: MPU register target at va %p\n",
2477 oh->name, va_start);
2478
2479 oh->_mpu_rt_va = va_start;
2480 return 0;
2481}
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496static int __init _init(struct omap_hwmod *oh, void *data)
2497{
2498 int r, index;
2499 struct device_node *np = NULL;
2500
2501 if (oh->_state != _HWMOD_STATE_REGISTERED)
2502 return 0;
2503
2504 if (of_have_populated_dt()) {
2505 struct device_node *bus;
2506
2507 bus = of_find_node_by_name(NULL, "ocp");
2508 if (!bus)
2509 return -ENODEV;
2510
2511 r = of_dev_hwmod_lookup(bus, oh, &index, &np);
2512 if (r)
2513 pr_debug("omap_hwmod: %s missing dt data\n", oh->name);
2514 else if (np && index)
2515 pr_warn("omap_hwmod: %s using broken dt data from %s\n",
2516 oh->name, np->name);
2517 }
2518
2519 r = _init_mpu_rt_base(oh, NULL, index, np);
2520 if (r < 0) {
2521 WARN(1, "omap_hwmod: %s: doesn't have mpu register target base\n",
2522 oh->name);
2523 return 0;
2524 }
2525
2526 r = _init_clocks(oh, NULL);
2527 if (r < 0) {
2528 WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh->name);
2529 return -EINVAL;
2530 }
2531
2532 if (np) {
2533 if (of_find_property(np, "ti,no-reset-on-init", NULL))
2534 oh->flags |= HWMOD_INIT_NO_RESET;
2535 if (of_find_property(np, "ti,no-idle-on-init", NULL))
2536 oh->flags |= HWMOD_INIT_NO_IDLE;
2537 if (of_find_property(np, "ti,no-idle", NULL))
2538 oh->flags |= HWMOD_NO_IDLE;
2539 }
2540
2541 oh->_state = _HWMOD_STATE_INITIALIZED;
2542
2543 return 0;
2544}
2545
2546
2547
2548
2549
2550
2551
2552
2553
2554static void __init _setup_iclk_autoidle(struct omap_hwmod *oh)
2555{
2556 struct omap_hwmod_ocp_if *os;
2557 struct list_head *p;
2558 int i = 0;
2559 if (oh->_state != _HWMOD_STATE_INITIALIZED)
2560 return;
2561
2562 p = oh->slave_ports.next;
2563
2564 while (i < oh->slaves_cnt) {
2565 os = _fetch_next_ocp_if(&p, &i);
2566 if (!os->_clk)
2567 continue;
2568
2569 if (os->flags & OCPIF_SWSUP_IDLE) {
2570
2571 } else {
2572
2573 clk_enable(os->_clk);
2574 }
2575 }
2576
2577 return;
2578}
2579
2580
2581
2582
2583
2584
2585
2586
2587
2588
2589static int __init _setup_reset(struct omap_hwmod *oh)
2590{
2591 int r;
2592
2593 if (oh->_state != _HWMOD_STATE_INITIALIZED)
2594 return -EINVAL;
2595
2596 if (oh->flags & HWMOD_EXT_OPT_MAIN_CLK)
2597 return -EPERM;
2598
2599 if (oh->rst_lines_cnt == 0) {
2600 r = _enable(oh);
2601 if (r) {
2602 pr_warn("omap_hwmod: %s: cannot be enabled for reset (%d)\n",
2603 oh->name, oh->_state);
2604 return -EINVAL;
2605 }
2606 }
2607
2608 if (!(oh->flags & HWMOD_INIT_NO_RESET))
2609 r = _reset(oh);
2610
2611 return r;
2612}
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641
2642
2643
2644
2645
2646
2647
2648
2649
2650static void __init _setup_postsetup(struct omap_hwmod *oh)
2651{
2652 u8 postsetup_state;
2653
2654 if (oh->rst_lines_cnt > 0)
2655 return;
2656
2657 postsetup_state = oh->_postsetup_state;
2658 if (postsetup_state == _HWMOD_STATE_UNKNOWN)
2659 postsetup_state = _HWMOD_STATE_ENABLED;
2660
2661
2662
2663
2664
2665 if ((oh->flags & (HWMOD_INIT_NO_IDLE | HWMOD_NO_IDLE)) &&
2666 (postsetup_state == _HWMOD_STATE_IDLE)) {
2667 oh->_int_flags |= _HWMOD_SKIP_ENABLE;
2668 postsetup_state = _HWMOD_STATE_ENABLED;
2669 }
2670
2671 if (postsetup_state == _HWMOD_STATE_IDLE)
2672 _idle(oh);
2673 else if (postsetup_state == _HWMOD_STATE_DISABLED)
2674 _shutdown(oh);
2675 else if (postsetup_state != _HWMOD_STATE_ENABLED)
2676 WARN(1, "hwmod: %s: unknown postsetup state %d! defaulting to enabled\n",
2677 oh->name, postsetup_state);
2678
2679 return;
2680}
2681
2682
2683
2684
2685
2686
2687
2688
2689
2690
2691
2692
2693
2694
2695
2696
2697
2698static int __init _setup(struct omap_hwmod *oh, void *data)
2699{
2700 if (oh->_state != _HWMOD_STATE_INITIALIZED)
2701 return 0;
2702
2703 if (oh->parent_hwmod) {
2704 int r;
2705
2706 r = _enable(oh->parent_hwmod);
2707 WARN(r, "hwmod: %s: setup: failed to enable parent hwmod %s\n",
2708 oh->name, oh->parent_hwmod->name);
2709 }
2710
2711 _setup_iclk_autoidle(oh);
2712
2713 if (!_setup_reset(oh))
2714 _setup_postsetup(oh);
2715
2716 if (oh->parent_hwmod) {
2717 u8 postsetup_state;
2718
2719 postsetup_state = oh->parent_hwmod->_postsetup_state;
2720
2721 if (postsetup_state == _HWMOD_STATE_IDLE)
2722 _idle(oh->parent_hwmod);
2723 else if (postsetup_state == _HWMOD_STATE_DISABLED)
2724 _shutdown(oh->parent_hwmod);
2725 else if (postsetup_state != _HWMOD_STATE_ENABLED)
2726 WARN(1, "hwmod: %s: unknown postsetup state %d! defaulting to enabled\n",
2727 oh->parent_hwmod->name, postsetup_state);
2728 }
2729
2730 return 0;
2731}
2732
2733
2734
2735
2736
2737
2738
2739
2740
2741
2742
2743
2744
2745
2746
2747
2748
2749
2750static int __init _register(struct omap_hwmod *oh)
2751{
2752 if (!oh || !oh->name || !oh->class || !oh->class->name ||
2753 (oh->_state != _HWMOD_STATE_UNKNOWN))
2754 return -EINVAL;
2755
2756 pr_debug("omap_hwmod: %s: registering\n", oh->name);
2757
2758 if (_lookup(oh->name))
2759 return -EEXIST;
2760
2761 list_add_tail(&oh->node, &omap_hwmod_list);
2762
2763 INIT_LIST_HEAD(&oh->master_ports);
2764 INIT_LIST_HEAD(&oh->slave_ports);
2765 spin_lock_init(&oh->_lock);
2766 lockdep_set_class(&oh->_lock, &oh->hwmod_key);
2767
2768 oh->_state = _HWMOD_STATE_REGISTERED;
2769
2770
2771
2772
2773
2774 if (!strcmp(oh->name, MPU_INITIATOR_NAME))
2775 mpu_oh = oh;
2776
2777 return 0;
2778}
2779
2780
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793static int __init _alloc_links(struct omap_hwmod_link **ml,
2794 struct omap_hwmod_link **sl)
2795{
2796 unsigned int sz;
2797
2798 if ((free_ls + LINKS_PER_OCP_IF) <= max_ls) {
2799 *ml = &linkspace[free_ls++];
2800 *sl = &linkspace[free_ls++];
2801 return 0;
2802 }
2803
2804 sz = sizeof(struct omap_hwmod_link) * LINKS_PER_OCP_IF;
2805
2806 *sl = NULL;
2807 *ml = memblock_virt_alloc(sz, 0);
2808
2809 *sl = (void *)(*ml) + sizeof(struct omap_hwmod_link);
2810
2811 ls_supp++;
2812 pr_debug("omap_hwmod: supplemental link allocations needed: %d\n",
2813 ls_supp * LINKS_PER_OCP_IF);
2814
2815 return 0;
2816};
2817
2818
2819
2820
2821
2822
2823
2824
2825
2826
2827
2828
2829static int __init _add_link(struct omap_hwmod_ocp_if *oi)
2830{
2831 struct omap_hwmod_link *ml, *sl;
2832
2833 pr_debug("omap_hwmod: %s -> %s: adding link\n", oi->master->name,
2834 oi->slave->name);
2835
2836 _alloc_links(&ml, &sl);
2837
2838 ml->ocp_if = oi;
2839 list_add(&ml->node, &oi->master->master_ports);
2840 oi->master->masters_cnt++;
2841
2842 sl->ocp_if = oi;
2843 list_add(&sl->node, &oi->slave->slave_ports);
2844 oi->slave->slaves_cnt++;
2845
2846 return 0;
2847}
2848
2849
2850
2851
2852
2853
2854
2855
2856
2857
2858
2859
2860
2861
2862static int __init _register_link(struct omap_hwmod_ocp_if *oi)
2863{
2864 if (!oi || !oi->master || !oi->slave || !oi->user)
2865 return -EINVAL;
2866
2867 if (oi->_int_flags & _OCPIF_INT_FLAGS_REGISTERED)
2868 return -EEXIST;
2869
2870 pr_debug("omap_hwmod: registering link from %s to %s\n",
2871 oi->master->name, oi->slave->name);
2872
2873
2874
2875
2876
2877 if (oi->master->_state != _HWMOD_STATE_REGISTERED)
2878 _register(oi->master);
2879
2880 if (oi->slave->_state != _HWMOD_STATE_REGISTERED)
2881 _register(oi->slave);
2882
2883 _add_link(oi);
2884
2885 oi->_int_flags |= _OCPIF_INT_FLAGS_REGISTERED;
2886
2887 return 0;
2888}
2889
2890
2891
2892
2893
2894
2895
2896
2897
2898
2899
2900
2901
2902
2903
2904
2905static int __init _alloc_linkspace(struct omap_hwmod_ocp_if **ois)
2906{
2907 unsigned int i = 0;
2908 unsigned int sz;
2909
2910 if (linkspace) {
2911 WARN(1, "linkspace already allocated\n");
2912 return -EEXIST;
2913 }
2914
2915 if (max_ls == 0)
2916 while (ois[i++])
2917 max_ls += LINKS_PER_OCP_IF;
2918
2919 sz = sizeof(struct omap_hwmod_link) * max_ls;
2920
2921 pr_debug("omap_hwmod: %s: allocating %d byte linkspace (%d links)\n",
2922 __func__, sz, max_ls);
2923
2924 linkspace = memblock_virt_alloc(sz, 0);
2925
2926 return 0;
2927}
2928
2929
2930
2931
2932
2933
2934
2935
2936
2937
2938
2939
2940static int _omap2xxx_3xxx_wait_target_ready(struct omap_hwmod *oh)
2941{
2942 if (!oh)
2943 return -EINVAL;
2944
2945 if (oh->flags & HWMOD_NO_IDLEST)
2946 return 0;
2947
2948 if (!_find_mpu_rt_port(oh))
2949 return 0;
2950
2951
2952
2953 return omap_cm_wait_module_ready(0, oh->prcm.omap2.module_offs,
2954 oh->prcm.omap2.idlest_reg_id,
2955 oh->prcm.omap2.idlest_idle_bit);
2956}
2957
2958
2959
2960
2961
2962
2963
2964
2965
2966
2967static int _omap4_wait_target_ready(struct omap_hwmod *oh)
2968{
2969 if (!oh)
2970 return -EINVAL;
2971
2972 if (oh->flags & HWMOD_NO_IDLEST || !oh->clkdm)
2973 return 0;
2974
2975 if (!_find_mpu_rt_port(oh))
2976 return 0;
2977
2978 if (!oh->prcm.omap4.clkctrl_offs &&
2979 !(oh->prcm.omap4.flags & HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET))
2980 return 0;
2981
2982
2983
2984 return omap_cm_wait_module_ready(oh->clkdm->prcm_partition,
2985 oh->clkdm->cm_inst,
2986 oh->prcm.omap4.clkctrl_offs, 0);
2987}
2988
2989
2990
2991
2992
2993
2994
2995
2996
2997
2998
2999
3000static int _omap2_assert_hardreset(struct omap_hwmod *oh,
3001 struct omap_hwmod_rst_info *ohri)
3002{
3003 return omap_prm_assert_hardreset(ohri->rst_shift, 0,
3004 oh->prcm.omap2.module_offs, 0);
3005}
3006
3007
3008
3009
3010
3011
3012
3013
3014
3015
3016
3017
3018static int _omap2_deassert_hardreset(struct omap_hwmod *oh,
3019 struct omap_hwmod_rst_info *ohri)
3020{
3021 return omap_prm_deassert_hardreset(ohri->rst_shift, ohri->st_shift, 0,
3022 oh->prcm.omap2.module_offs, 0, 0);
3023}
3024
3025
3026
3027
3028
3029
3030
3031
3032
3033
3034
3035
3036
3037static int _omap2_is_hardreset_asserted(struct omap_hwmod *oh,
3038 struct omap_hwmod_rst_info *ohri)
3039{
3040 return omap_prm_is_hardreset_asserted(ohri->st_shift, 0,
3041 oh->prcm.omap2.module_offs, 0);
3042}
3043
3044
3045
3046
3047
3048
3049
3050
3051
3052
3053
3054
3055
3056static int _omap4_assert_hardreset(struct omap_hwmod *oh,
3057 struct omap_hwmod_rst_info *ohri)
3058{
3059 if (!oh->clkdm)
3060 return -EINVAL;
3061
3062 return omap_prm_assert_hardreset(ohri->rst_shift,
3063 oh->clkdm->pwrdm.ptr->prcm_partition,
3064 oh->clkdm->pwrdm.ptr->prcm_offs,
3065 oh->prcm.omap4.rstctrl_offs);
3066}
3067
3068
3069
3070
3071
3072
3073
3074
3075
3076
3077
3078
3079
3080static int _omap4_deassert_hardreset(struct omap_hwmod *oh,
3081 struct omap_hwmod_rst_info *ohri)
3082{
3083 if (!oh->clkdm)
3084 return -EINVAL;
3085
3086 if (ohri->st_shift)
3087 pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n",
3088 oh->name, ohri->name);
3089 return omap_prm_deassert_hardreset(ohri->rst_shift, ohri->rst_shift,
3090 oh->clkdm->pwrdm.ptr->prcm_partition,
3091 oh->clkdm->pwrdm.ptr->prcm_offs,
3092 oh->prcm.omap4.rstctrl_offs,
3093 oh->prcm.omap4.rstctrl_offs +
3094 OMAP4_RST_CTRL_ST_OFFSET);
3095}
3096
3097
3098
3099
3100
3101
3102
3103
3104
3105
3106
3107
3108
3109static int _omap4_is_hardreset_asserted(struct omap_hwmod *oh,
3110 struct omap_hwmod_rst_info *ohri)
3111{
3112 if (!oh->clkdm)
3113 return -EINVAL;
3114
3115 return omap_prm_is_hardreset_asserted(ohri->rst_shift,
3116 oh->clkdm->pwrdm.ptr->
3117 prcm_partition,
3118 oh->clkdm->pwrdm.ptr->prcm_offs,
3119 oh->prcm.omap4.rstctrl_offs);
3120}
3121
3122
3123
3124
3125
3126
3127
3128
3129
3130static int _omap4_disable_direct_prcm(struct omap_hwmod *oh)
3131{
3132 if (!oh)
3133 return -EINVAL;
3134
3135 oh->prcm.omap4.clkctrl_offs = 0;
3136 oh->prcm.omap4.modulemode = 0;
3137
3138 return 0;
3139}
3140
3141
3142
3143
3144
3145
3146
3147
3148
3149
3150
3151
3152
3153static int _am33xx_deassert_hardreset(struct omap_hwmod *oh,
3154 struct omap_hwmod_rst_info *ohri)
3155{
3156 return omap_prm_deassert_hardreset(ohri->rst_shift, ohri->st_shift,
3157 oh->clkdm->pwrdm.ptr->prcm_partition,
3158 oh->clkdm->pwrdm.ptr->prcm_offs,
3159 oh->prcm.omap4.rstctrl_offs,
3160 oh->prcm.omap4.rstst_offs);
3161}
3162
3163
3164
3165u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs)
3166{
3167 if (oh->flags & HWMOD_16BIT_REG)
3168 return readw_relaxed(oh->_mpu_rt_va + reg_offs);
3169 else
3170 return readl_relaxed(oh->_mpu_rt_va + reg_offs);
3171}
3172
3173void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs)
3174{
3175 if (oh->flags & HWMOD_16BIT_REG)
3176 writew_relaxed(v, oh->_mpu_rt_va + reg_offs);
3177 else
3178 writel_relaxed(v, oh->_mpu_rt_va + reg_offs);
3179}
3180
3181
3182
3183
3184
3185
3186
3187
3188
3189
3190int omap_hwmod_softreset(struct omap_hwmod *oh)
3191{
3192 u32 v;
3193 int ret;
3194
3195 if (!oh || !(oh->_sysc_cache))
3196 return -EINVAL;
3197
3198 v = oh->_sysc_cache;
3199 ret = _set_softreset(oh, &v);
3200 if (ret)
3201 goto error;
3202 _write_sysconfig(v, oh);
3203
3204 ret = _clear_softreset(oh, &v);
3205 if (ret)
3206 goto error;
3207 _write_sysconfig(v, oh);
3208
3209error:
3210 return ret;
3211}
3212
3213
3214
3215
3216
3217
3218
3219
3220struct omap_hwmod *omap_hwmod_lookup(const char *name)
3221{
3222 struct omap_hwmod *oh;
3223
3224 if (!name)
3225 return NULL;
3226
3227 oh = _lookup(name);
3228
3229 return oh;
3230}
3231
3232
3233
3234
3235
3236
3237
3238
3239
3240
3241
3242
3243
3244int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data),
3245 void *data)
3246{
3247 struct omap_hwmod *temp_oh;
3248 int ret = 0;
3249
3250 if (!fn)
3251 return -EINVAL;
3252
3253 list_for_each_entry(temp_oh, &omap_hwmod_list, node) {
3254 ret = (*fn)(temp_oh, data);
3255 if (ret)
3256 break;
3257 }
3258
3259 return ret;
3260}
3261
3262
3263
3264
3265
3266
3267
3268
3269
3270
3271
3272
3273int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois)
3274{
3275 int r, i;
3276
3277 if (!inited)
3278 return -EINVAL;
3279
3280 if (!ois)
3281 return 0;
3282
3283 if (ois[0] == NULL)
3284 return 0;
3285
3286 if (!linkspace) {
3287 if (_alloc_linkspace(ois)) {
3288 pr_err("omap_hwmod: could not allocate link space\n");
3289 return -ENOMEM;
3290 }
3291 }
3292
3293 i = 0;
3294 do {
3295 r = _register_link(ois[i]);
3296 WARN(r && r != -EEXIST,
3297 "omap_hwmod: _register_link(%s -> %s) returned %d\n",
3298 ois[i]->master->name, ois[i]->slave->name, r);
3299 } while (ois[++i]);
3300
3301 return 0;
3302}
3303
3304
3305
3306
3307
3308
3309
3310
3311
3312
3313
3314static void __init _ensure_mpu_hwmod_is_setup(struct omap_hwmod *oh)
3315{
3316 if (!mpu_oh || mpu_oh->_state == _HWMOD_STATE_UNKNOWN)
3317 pr_err("omap_hwmod: %s: MPU initiator hwmod %s not yet registered\n",
3318 __func__, MPU_INITIATOR_NAME);
3319 else if (mpu_oh->_state == _HWMOD_STATE_REGISTERED && oh != mpu_oh)
3320 omap_hwmod_setup_one(MPU_INITIATOR_NAME);
3321}
3322
3323
3324
3325
3326
3327
3328
3329
3330
3331
3332
3333
3334int __init omap_hwmod_setup_one(const char *oh_name)
3335{
3336 struct omap_hwmod *oh;
3337
3338 pr_debug("omap_hwmod: %s: %s\n", oh_name, __func__);
3339
3340 oh = _lookup(oh_name);
3341 if (!oh) {
3342 WARN(1, "omap_hwmod: %s: hwmod not yet registered\n", oh_name);
3343 return -EINVAL;
3344 }
3345
3346 _ensure_mpu_hwmod_is_setup(oh);
3347
3348 _init(oh, NULL);
3349 _setup(oh, NULL);
3350
3351 return 0;
3352}
3353
3354
3355
3356
3357
3358
3359
3360
3361
3362static int __init omap_hwmod_setup_all(void)
3363{
3364 _ensure_mpu_hwmod_is_setup(NULL);
3365
3366 omap_hwmod_for_each(_init, NULL);
3367 omap_hwmod_for_each(_setup, NULL);
3368
3369 return 0;
3370}
3371omap_postcore_initcall(omap_hwmod_setup_all);
3372
3373
3374
3375
3376
3377
3378
3379
3380int omap_hwmod_enable(struct omap_hwmod *oh)
3381{
3382 int r;
3383 unsigned long flags;
3384
3385 if (!oh)
3386 return -EINVAL;
3387
3388 spin_lock_irqsave(&oh->_lock, flags);
3389 r = _enable(oh);
3390 spin_unlock_irqrestore(&oh->_lock, flags);
3391
3392 return r;
3393}
3394
3395
3396
3397
3398
3399
3400
3401
3402int omap_hwmod_idle(struct omap_hwmod *oh)
3403{
3404 int r;
3405 unsigned long flags;
3406
3407 if (!oh)
3408 return -EINVAL;
3409
3410 spin_lock_irqsave(&oh->_lock, flags);
3411 r = _idle(oh);
3412 spin_unlock_irqrestore(&oh->_lock, flags);
3413
3414 return r;
3415}
3416
3417
3418
3419
3420
3421
3422
3423
3424
3425int omap_hwmod_shutdown(struct omap_hwmod *oh)
3426{
3427 int r;
3428 unsigned long flags;
3429
3430 if (!oh)
3431 return -EINVAL;
3432
3433 spin_lock_irqsave(&oh->_lock, flags);
3434 r = _shutdown(oh);
3435 spin_unlock_irqrestore(&oh->_lock, flags);
3436
3437 return r;
3438}
3439
3440
3441
3442
3443
3444
3445
3446
3447
3448
3449
3450
3451
3452
3453
3454
3455
3456
3457
3458
3459
3460int omap_hwmod_count_resources(struct omap_hwmod *oh, unsigned long flags)
3461{
3462 int ret = 0;
3463
3464 if (flags & IORESOURCE_IRQ)
3465 ret += _count_mpu_irqs(oh);
3466
3467 if (flags & IORESOURCE_DMA)
3468 ret += _count_sdma_reqs(oh);
3469
3470 if (flags & IORESOURCE_MEM) {
3471 int i = 0;
3472 struct omap_hwmod_ocp_if *os;
3473 struct list_head *p = oh->slave_ports.next;
3474
3475 while (i < oh->slaves_cnt) {
3476 os = _fetch_next_ocp_if(&p, &i);
3477 ret += _count_ocp_if_addr_spaces(os);
3478 }
3479 }
3480
3481 return ret;
3482}
3483
3484
3485
3486
3487
3488
3489
3490
3491
3492
3493
3494int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
3495{
3496 struct omap_hwmod_ocp_if *os;
3497 struct list_head *p;
3498 int i, j, mpu_irqs_cnt, sdma_reqs_cnt, addr_cnt;
3499 int r = 0;
3500
3501
3502
3503 mpu_irqs_cnt = _count_mpu_irqs(oh);
3504 for (i = 0; i < mpu_irqs_cnt; i++) {
3505 unsigned int irq;
3506
3507 if (oh->xlate_irq)
3508 irq = oh->xlate_irq((oh->mpu_irqs + i)->irq);
3509 else
3510 irq = (oh->mpu_irqs + i)->irq;
3511 (res + r)->name = (oh->mpu_irqs + i)->name;
3512 (res + r)->start = irq;
3513 (res + r)->end = irq;
3514 (res + r)->flags = IORESOURCE_IRQ;
3515 r++;
3516 }
3517
3518 sdma_reqs_cnt = _count_sdma_reqs(oh);
3519 for (i = 0; i < sdma_reqs_cnt; i++) {
3520 (res + r)->name = (oh->sdma_reqs + i)->name;
3521 (res + r)->start = (oh->sdma_reqs + i)->dma_req;
3522 (res + r)->end = (oh->sdma_reqs + i)->dma_req;
3523 (res + r)->flags = IORESOURCE_DMA;
3524 r++;
3525 }
3526
3527 p = oh->slave_ports.next;
3528
3529 i = 0;
3530 while (i < oh->slaves_cnt) {
3531 os = _fetch_next_ocp_if(&p, &i);
3532 addr_cnt = _count_ocp_if_addr_spaces(os);
3533
3534 for (j = 0; j < addr_cnt; j++) {
3535 (res + r)->name = (os->addr + j)->name;
3536 (res + r)->start = (os->addr + j)->pa_start;
3537 (res + r)->end = (os->addr + j)->pa_end;
3538 (res + r)->flags = IORESOURCE_MEM;
3539 r++;
3540 }
3541 }
3542
3543 return r;
3544}
3545
3546
3547
3548
3549
3550
3551
3552
3553
3554
3555
3556int omap_hwmod_fill_dma_resources(struct omap_hwmod *oh, struct resource *res)
3557{
3558 int i, sdma_reqs_cnt;
3559 int r = 0;
3560
3561 sdma_reqs_cnt = _count_sdma_reqs(oh);
3562 for (i = 0; i < sdma_reqs_cnt; i++) {
3563 (res + r)->name = (oh->sdma_reqs + i)->name;
3564 (res + r)->start = (oh->sdma_reqs + i)->dma_req;
3565 (res + r)->end = (oh->sdma_reqs + i)->dma_req;
3566 (res + r)->flags = IORESOURCE_DMA;
3567 r++;
3568 }
3569
3570 return r;
3571}
3572
3573
3574
3575
3576
3577
3578
3579
3580
3581
3582
3583
3584
3585
3586
3587
3588
3589
3590
3591
3592
3593
3594
3595int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type,
3596 const char *name, struct resource *rsrc)
3597{
3598 int r;
3599 unsigned int irq, dma;
3600 u32 pa_start, pa_end;
3601
3602 if (!oh || !rsrc)
3603 return -EINVAL;
3604
3605 if (type == IORESOURCE_IRQ) {
3606 r = _get_mpu_irq_by_name(oh, name, &irq);
3607 if (r)
3608 return r;
3609
3610 rsrc->start = irq;
3611 rsrc->end = irq;
3612 } else if (type == IORESOURCE_DMA) {
3613 r = _get_sdma_req_by_name(oh, name, &dma);
3614 if (r)
3615 return r;
3616
3617 rsrc->start = dma;
3618 rsrc->end = dma;
3619 } else if (type == IORESOURCE_MEM) {
3620 r = _get_addr_space_by_name(oh, name, &pa_start, &pa_end);
3621 if (r)
3622 return r;
3623
3624 rsrc->start = pa_start;
3625 rsrc->end = pa_end;
3626 } else {
3627 return -EINVAL;
3628 }
3629
3630 rsrc->flags = type;
3631 rsrc->name = name;
3632
3633 return 0;
3634}
3635
3636
3637
3638
3639
3640
3641
3642
3643
3644
3645
3646
3647struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh)
3648{
3649 struct clk *c;
3650 struct omap_hwmod_ocp_if *oi;
3651 struct clockdomain *clkdm;
3652 struct clk_hw_omap *clk;
3653
3654 if (!oh)
3655 return NULL;
3656
3657 if (oh->clkdm)
3658 return oh->clkdm->pwrdm.ptr;
3659
3660 if (oh->_clk) {
3661 c = oh->_clk;
3662 } else {
3663 oi = _find_mpu_rt_port(oh);
3664 if (!oi)
3665 return NULL;
3666 c = oi->_clk;
3667 }
3668
3669 clk = to_clk_hw_omap(__clk_get_hw(c));
3670 clkdm = clk->clkdm;
3671 if (!clkdm)
3672 return NULL;
3673
3674 return clkdm->pwrdm.ptr;
3675}
3676
3677
3678
3679
3680
3681
3682
3683
3684
3685
3686void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh)
3687{
3688 if (!oh)
3689 return NULL;
3690
3691 if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
3692 return NULL;
3693
3694 if (oh->_state == _HWMOD_STATE_UNKNOWN)
3695 return NULL;
3696
3697 return oh->_mpu_rt_va;
3698}
3699
3700
3701
3702
3703
3704
3705
3706
3707
3708
3709
3710
3711
3712
3713
3714
3715
3716
3717
3718int omap_hwmod_enable_wakeup(struct omap_hwmod *oh)
3719{
3720 unsigned long flags;
3721 u32 v;
3722
3723 spin_lock_irqsave(&oh->_lock, flags);
3724
3725 if (oh->class->sysc &&
3726 (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) {
3727 v = oh->_sysc_cache;
3728 _enable_wakeup(oh, &v);
3729 _write_sysconfig(v, oh);
3730 }
3731
3732 _set_idle_ioring_wakeup(oh, true);
3733 spin_unlock_irqrestore(&oh->_lock, flags);
3734
3735 return 0;
3736}
3737
3738
3739
3740
3741
3742
3743
3744
3745
3746
3747
3748
3749
3750
3751int omap_hwmod_disable_wakeup(struct omap_hwmod *oh)
3752{
3753 unsigned long flags;
3754 u32 v;
3755
3756 spin_lock_irqsave(&oh->_lock, flags);
3757
3758 if (oh->class->sysc &&
3759 (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) {
3760 v = oh->_sysc_cache;
3761 _disable_wakeup(oh, &v);
3762 _write_sysconfig(v, oh);
3763 }
3764
3765 _set_idle_ioring_wakeup(oh, false);
3766 spin_unlock_irqrestore(&oh->_lock, flags);
3767
3768 return 0;
3769}
3770
3771
3772
3773
3774
3775
3776
3777
3778
3779
3780
3781
3782
3783int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name)
3784{
3785 int ret;
3786 unsigned long flags;
3787
3788 if (!oh)
3789 return -EINVAL;
3790
3791 spin_lock_irqsave(&oh->_lock, flags);
3792 ret = _assert_hardreset(oh, name);
3793 spin_unlock_irqrestore(&oh->_lock, flags);
3794
3795 return ret;
3796}
3797
3798
3799
3800
3801
3802
3803
3804
3805
3806
3807
3808
3809
3810int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name)
3811{
3812 int ret;
3813 unsigned long flags;
3814
3815 if (!oh)
3816 return -EINVAL;
3817
3818 spin_lock_irqsave(&oh->_lock, flags);
3819 ret = _deassert_hardreset(oh, name);
3820 spin_unlock_irqrestore(&oh->_lock, flags);
3821
3822 return ret;
3823}
3824
3825
3826
3827
3828
3829
3830
3831
3832
3833
3834
3835
3836
3837int omap_hwmod_for_each_by_class(const char *classname,
3838 int (*fn)(struct omap_hwmod *oh,
3839 void *user),
3840 void *user)
3841{
3842 struct omap_hwmod *temp_oh;
3843 int ret = 0;
3844
3845 if (!classname || !fn)
3846 return -EINVAL;
3847
3848 pr_debug("omap_hwmod: %s: looking for modules of class %s\n",
3849 __func__, classname);
3850
3851 list_for_each_entry(temp_oh, &omap_hwmod_list, node) {
3852 if (!strcmp(temp_oh->class->name, classname)) {
3853 pr_debug("omap_hwmod: %s: %s: calling callback fn\n",
3854 __func__, temp_oh->name);
3855 ret = (*fn)(temp_oh, user);
3856 if (ret)
3857 break;
3858 }
3859 }
3860
3861 if (ret)
3862 pr_debug("omap_hwmod: %s: iterator terminated early: %d\n",
3863 __func__, ret);
3864
3865 return ret;
3866}
3867
3868
3869
3870
3871
3872
3873
3874
3875
3876
3877
3878
3879int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state)
3880{
3881 int ret;
3882 unsigned long flags;
3883
3884 if (!oh)
3885 return -EINVAL;
3886
3887 if (state != _HWMOD_STATE_DISABLED &&
3888 state != _HWMOD_STATE_ENABLED &&
3889 state != _HWMOD_STATE_IDLE)
3890 return -EINVAL;
3891
3892 spin_lock_irqsave(&oh->_lock, flags);
3893
3894 if (oh->_state != _HWMOD_STATE_REGISTERED) {
3895 ret = -EINVAL;
3896 goto ohsps_unlock;
3897 }
3898
3899 oh->_postsetup_state = state;
3900 ret = 0;
3901
3902ohsps_unlock:
3903 spin_unlock_irqrestore(&oh->_lock, flags);
3904
3905 return ret;
3906}
3907
3908
3909
3910
3911
3912
3913
3914
3915
3916
3917
3918
3919int omap_hwmod_get_context_loss_count(struct omap_hwmod *oh)
3920{
3921 struct powerdomain *pwrdm;
3922 int ret = 0;
3923
3924 if (soc_ops.get_context_lost)
3925 return soc_ops.get_context_lost(oh);
3926
3927 pwrdm = omap_hwmod_get_pwrdm(oh);
3928 if (pwrdm)
3929 ret = pwrdm_get_context_loss_count(pwrdm);
3930
3931 return ret;
3932}
3933
3934
3935
3936
3937
3938
3939
3940
3941void __init omap_hwmod_init(void)
3942{
3943 if (cpu_is_omap24xx()) {
3944 soc_ops.wait_target_ready = _omap2xxx_3xxx_wait_target_ready;
3945 soc_ops.assert_hardreset = _omap2_assert_hardreset;
3946 soc_ops.deassert_hardreset = _omap2_deassert_hardreset;
3947 soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted;
3948 } else if (cpu_is_omap34xx()) {
3949 soc_ops.wait_target_ready = _omap2xxx_3xxx_wait_target_ready;
3950 soc_ops.assert_hardreset = _omap2_assert_hardreset;
3951 soc_ops.deassert_hardreset = _omap2_deassert_hardreset;
3952 soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted;
3953 soc_ops.init_clkdm = _init_clkdm;
3954 } else if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) {
3955 soc_ops.enable_module = _omap4_enable_module;
3956 soc_ops.disable_module = _omap4_disable_module;
3957 soc_ops.wait_target_ready = _omap4_wait_target_ready;
3958 soc_ops.assert_hardreset = _omap4_assert_hardreset;
3959 soc_ops.deassert_hardreset = _omap4_deassert_hardreset;
3960 soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted;
3961 soc_ops.init_clkdm = _init_clkdm;
3962 soc_ops.update_context_lost = _omap4_update_context_lost;
3963 soc_ops.get_context_lost = _omap4_get_context_lost;
3964 soc_ops.disable_direct_prcm = _omap4_disable_direct_prcm;
3965 } else if (cpu_is_ti814x() || cpu_is_ti816x() || soc_is_am33xx() ||
3966 soc_is_am43xx()) {
3967 soc_ops.enable_module = _omap4_enable_module;
3968 soc_ops.disable_module = _omap4_disable_module;
3969 soc_ops.wait_target_ready = _omap4_wait_target_ready;
3970 soc_ops.assert_hardreset = _omap4_assert_hardreset;
3971 soc_ops.deassert_hardreset = _am33xx_deassert_hardreset;
3972 soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted;
3973 soc_ops.init_clkdm = _init_clkdm;
3974 soc_ops.disable_direct_prcm = _omap4_disable_direct_prcm;
3975 } else {
3976 WARN(1, "omap_hwmod: unknown SoC type\n");
3977 }
3978
3979 inited = true;
3980}
3981
3982
3983
3984
3985
3986
3987
3988
3989const char *omap_hwmod_get_main_clk(struct omap_hwmod *oh)
3990{
3991 if (!oh)
3992 return NULL;
3993
3994 return oh->main_clk;
3995}
3996