1#ifndef __iop_mpu_defs_h
2#define __iop_mpu_defs_h
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17#ifndef REG_RD
18#define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
21#endif
22
23#ifndef REG_WR
24#define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27#endif
28
29#ifndef REG_RD_VECT
30#define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
34#endif
35
36#ifndef REG_WR_VECT
37#define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
41#endif
42
43#ifndef REG_RD_INT
44#define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46#endif
47
48#ifndef REG_WR_INT
49#define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51#endif
52
53#ifndef REG_RD_INT_VECT
54#define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
57#endif
58
59#ifndef REG_WR_INT_VECT
60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
63#endif
64
65#ifndef REG_TYPE_CONV
66#define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68#endif
69
70#ifndef reg_page_size
71#define reg_page_size 8192
72#endif
73
74#ifndef REG_ADDR
75#define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77#endif
78
79#ifndef REG_ADDR_VECT
80#define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
83#endif
84
85
86
87#define STRIDE_iop_mpu_rw_r 4
88
89typedef unsigned int reg_iop_mpu_rw_r;
90#define REG_RD_ADDR_iop_mpu_rw_r 0
91#define REG_WR_ADDR_iop_mpu_rw_r 0
92
93
94typedef struct {
95 unsigned int en : 1;
96 unsigned int dummy1 : 31;
97} reg_iop_mpu_rw_ctrl;
98#define REG_RD_ADDR_iop_mpu_rw_ctrl 128
99#define REG_WR_ADDR_iop_mpu_rw_ctrl 128
100
101
102typedef struct {
103 unsigned int addr : 12;
104 unsigned int dummy1 : 20;
105} reg_iop_mpu_r_pc;
106#define REG_RD_ADDR_iop_mpu_r_pc 132
107
108
109typedef struct {
110 unsigned int instr_reg_busy : 1;
111 unsigned int intr_busy : 1;
112 unsigned int intr_vect : 16;
113 unsigned int dummy1 : 14;
114} reg_iop_mpu_r_stat;
115#define REG_RD_ADDR_iop_mpu_r_stat 136
116
117
118typedef unsigned int reg_iop_mpu_rw_instr;
119#define REG_RD_ADDR_iop_mpu_rw_instr 140
120#define REG_WR_ADDR_iop_mpu_rw_instr 140
121
122
123typedef unsigned int reg_iop_mpu_rw_immediate;
124#define REG_RD_ADDR_iop_mpu_rw_immediate 144
125#define REG_WR_ADDR_iop_mpu_rw_immediate 144
126
127
128typedef struct {
129 unsigned int intr_vect : 16;
130 unsigned int pc : 12;
131 unsigned int en : 1;
132 unsigned int instr_reg_busy : 1;
133 unsigned int intr_busy : 1;
134 unsigned int dummy1 : 1;
135} reg_iop_mpu_r_trace;
136#define REG_RD_ADDR_iop_mpu_r_trace 148
137
138
139typedef struct {
140 unsigned int r0 : 1;
141 unsigned int r1 : 1;
142 unsigned int r2 : 1;
143 unsigned int r3 : 1;
144 unsigned int r4 : 1;
145 unsigned int r5 : 1;
146 unsigned int r6 : 1;
147 unsigned int r7 : 1;
148 unsigned int r8 : 1;
149 unsigned int r9 : 1;
150 unsigned int r10 : 1;
151 unsigned int r11 : 1;
152 unsigned int r12 : 1;
153 unsigned int r13 : 1;
154 unsigned int r14 : 1;
155 unsigned int r15 : 1;
156 unsigned int dummy1 : 16;
157} reg_iop_mpu_r_wr_stat;
158#define REG_RD_ADDR_iop_mpu_r_wr_stat 152
159
160#define STRIDE_iop_mpu_rw_thread 4
161
162typedef struct {
163 unsigned int addr : 12;
164 unsigned int dummy1 : 20;
165} reg_iop_mpu_rw_thread;
166#define REG_RD_ADDR_iop_mpu_rw_thread 156
167#define REG_WR_ADDR_iop_mpu_rw_thread 156
168
169#define STRIDE_iop_mpu_rw_intr 4
170
171typedef struct {
172 unsigned int addr : 12;
173 unsigned int dummy1 : 20;
174} reg_iop_mpu_rw_intr;
175#define REG_RD_ADDR_iop_mpu_rw_intr 196
176#define REG_WR_ADDR_iop_mpu_rw_intr 196
177
178
179
180enum {
181 regk_iop_mpu_no = 0x00000000,
182 regk_iop_mpu_r_pc_default = 0x00000000,
183 regk_iop_mpu_rw_ctrl_default = 0x00000000,
184 regk_iop_mpu_rw_intr_size = 0x00000010,
185 regk_iop_mpu_rw_r_size = 0x00000010,
186 regk_iop_mpu_rw_thread_default = 0x00000000,
187 regk_iop_mpu_rw_thread_size = 0x00000004,
188 regk_iop_mpu_yes = 0x00000001
189};
190#endif
191