LXR linux/arch/ia64/include/asm/sn/arch.h

   1/*
   2 * This file is subject to the terms and conditions of the GNU General Public
   3 * License.  See the file "COPYING" in the main directory of this archive
   4 * for more details.
   5 *
   6 * SGI specific setup.
   7 *
   8 * Copyright (C) 1995-1997,1999,2001-2005 Silicon Graphics, Inc.  All rights reserved.
   9 * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
  10 */
  11#ifndef _ASM_IA64_SN_ARCH_H
  12#define _ASM_IA64_SN_ARCH_H
  13
  14#include <linux/numa.h>
  15#include <asm/types.h>
  16#include <asm/percpu.h>
  17#include <asm/sn/types.h>
  18#include <asm/sn/sn_cpuid.h>
  19
  20/*
  21 * This is the maximum number of NUMALINK nodes that can be part of a single
  22 * SSI kernel. This number includes C-brick, M-bricks, and TIOs. Nodes in
  23 * remote partitions are NOT included in this number.
  24 * The number of compact nodes cannot exceed size of a coherency domain.
  25 * The purpose of this define is to specify a node count that includes
  26 * all C/M/TIO nodes in an SSI system.
  27 *
  28 * SGI system can currently support up to 256 C/M nodes plus additional TIO nodes.
  29 *
  30 *      Note: ACPI20 has an architectural limit of 256 nodes. When we upgrade
  31 *      to ACPI3.0, this limit will be removed. The notion of "compact nodes"
  32 *      should be deleted and TIOs should be included in MAX_NUMNODES.
  33 */
  34#define MAX_TIO_NODES           MAX_NUMNODES
  35#define MAX_COMPACT_NODES       (MAX_NUMNODES + MAX_TIO_NODES)
  36
  37/*
  38 * Maximum number of nodes in all partitions and in all coherency domains.
  39 * This is the total number of nodes accessible in the numalink fabric. It
  40 * includes all C & M bricks, plus all TIOs.
  41 *
  42 * This value is also the value of the maximum number of NASIDs in the numalink
  43 * fabric.
  44 */
  45#define MAX_NUMALINK_NODES      16384
  46
  47/*
  48 * The following defines attributes of the HUB chip. These attributes are
  49 * frequently referenced. They are kept in the per-cpu data areas of each cpu.
  50 * They are kept together in a struct to minimize cache misses.
  51 */
  52struct sn_hub_info_s {
  53        u8 shub2;
  54        u8 nasid_shift;
  55        u8 as_shift;
  56        u8 shub_1_1_found;
  57        u16 nasid_bitmask;
  58};
  59DECLARE_PER_CPU(struct sn_hub_info_s, __sn_hub_info);
  60#define sn_hub_info     this_cpu_ptr(&__sn_hub_info)
  61#define is_shub2()      (sn_hub_info->shub2)
  62#define is_shub1()      (sn_hub_info->shub2 == 0)
  63
  64/*
  65 * Use this macro to test if shub 1.1 wars should be enabled
  66 */
  67#define enable_shub_wars_1_1()  (sn_hub_info->shub_1_1_found)
  68
  69
  70/*
  71 * Compact node ID to nasid mappings kept in the per-cpu data areas of each
  72 * cpu.
  73 */
  74DECLARE_PER_CPU(short, __sn_cnodeid_to_nasid[MAX_COMPACT_NODES]);
  75#define sn_cnodeid_to_nasid     this_cpu_ptr(&__sn_cnodeid_to_nasid[0])
  76
  77
  78extern u8 sn_partition_id;
  79extern u8 sn_system_size;
  80extern u8 sn_sharing_domain_size;
  81extern u8 sn_region_size;
  82
  83extern void sn_flush_all_caches(long addr, long bytes);
  84extern bool sn_cpu_disable_allowed(int cpu);
  85
  86#endif /* _ASM_IA64_SN_ARCH_H */
  87