LXR linux/arch/m68k/coldfire/m5307.c

   1/***************************************************************************/
   2
   3/*
   4 *      m5307.c  -- platform support for ColdFire 5307 based boards
   5 *
   6 *      Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
   7 *      Copyright (C) 2000, Lineo (www.lineo.com)
   8 */
   9
  10/***************************************************************************/
  11
  12#include <linux/kernel.h>
  13#include <linux/param.h>
  14#include <linux/init.h>
  15#include <linux/io.h>
  16#include <asm/machdep.h>
  17#include <asm/coldfire.h>
  18#include <asm/mcfsim.h>
  19#include <asm/mcfwdebug.h>
  20#include <asm/mcfclk.h>
  21
  22/***************************************************************************/
  23
  24/*
  25 *      Some platforms need software versions of the GPIO data registers.
  26 */
  27unsigned short ppdata;
  28unsigned char ledbank = 0xff;
  29
  30/***************************************************************************/
  31
  32DEFINE_CLK(pll, "pll.0", MCF_CLK);
  33DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
  34DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
  35DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
  36DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
  37DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
  38
  39struct clk *mcf_clks[] = {
  40        &clk_pll,
  41        &clk_sys,
  42        &clk_mcftmr0,
  43        &clk_mcftmr1,
  44        &clk_mcfuart0,
  45        &clk_mcfuart1,
  46        NULL
  47};
  48
  49/***************************************************************************/
  50
  51void __init config_BSP(char *commandp, int size)
  52{
  53#if defined(CONFIG_NETtel) || \
  54    defined(CONFIG_SECUREEDGEMP3) || defined(CONFIG_CLEOPATRA)
  55        /* Copy command line from FLASH to local buffer... */
  56        memcpy(commandp, (char *) 0xf0004000, size);
  57        commandp[size-1] = 0;
  58#endif
  59
  60        mach_sched_init = hw_timer_init;
  61
  62        /* Only support the external interrupts on their primary level */
  63        mcf_mapirq2imr(25, MCFINTC_EINT1);
  64        mcf_mapirq2imr(27, MCFINTC_EINT3);
  65        mcf_mapirq2imr(29, MCFINTC_EINT5);
  66        mcf_mapirq2imr(31, MCFINTC_EINT7);
  67
  68#ifdef CONFIG_BDM_DISABLE
  69        /*
  70         * Disable the BDM clocking.  This also turns off most of the rest of
  71         * the BDM device.  This is good for EMC reasons. This option is not
  72         * incompatible with the memory protection option.
  73         */
  74        wdebug(MCFDEBUG_CSR, MCFDEBUG_CSR_PSTCLK);
  75#endif
  76}
  77
  78/***************************************************************************/
  79