LXR linux/arch/powerpc/include/asm/dcr-native.h

   1/*
   2 * (c) Copyright 2006 Benjamin Herrenschmidt, IBM Corp.
   3 *                    <benh@kernel.crashing.org>
   4 *
   5 *   This program is free software;  you can redistribute it and/or modify
   6 *   it under the terms of the GNU General Public License as published by
   7 *   the Free Software Foundation; either version 2 of the License, or
   8 *   (at your option) any later version.
   9 *
  10 *   This program is distributed in the hope that it will be useful,
  11 *   but WITHOUT ANY WARRANTY;  without even the implied warranty of
  12 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  13 *   the GNU General Public License for more details.
  14 *
  15 *   You should have received a copy of the GNU General Public License
  16 *   along with this program;  if not, write to the Free Software
  17 *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  18 */
  19
  20#ifndef _ASM_POWERPC_DCR_NATIVE_H
  21#define _ASM_POWERPC_DCR_NATIVE_H
  22#ifdef __KERNEL__
  23#ifndef __ASSEMBLY__
  24
  25#include <linux/spinlock.h>
  26#include <asm/cputable.h>
  27#include <asm/cpu_has_feature.h>
  28
  29typedef struct {
  30        unsigned int base;
  31} dcr_host_native_t;
  32
  33static inline bool dcr_map_ok_native(dcr_host_native_t host)
  34{
  35        return true;
  36}
  37
  38#define dcr_map_native(dev, dcr_n, dcr_c) \
  39        ((dcr_host_native_t){ .base = (dcr_n) })
  40#define dcr_unmap_native(host, dcr_c)           do {} while (0)
  41#define dcr_read_native(host, dcr_n)            mfdcr(dcr_n + host.base)
  42#define dcr_write_native(host, dcr_n, value)    mtdcr(dcr_n + host.base, value)
  43
  44/* Table based DCR accessors */
  45extern void __mtdcr(unsigned int reg, unsigned int val);
  46extern unsigned int __mfdcr(unsigned int reg);
  47
  48/* mfdcrx/mtdcrx instruction based accessors. We hand code
  49 * the opcodes in order not to depend on newer binutils
  50 */
  51static inline unsigned int mfdcrx(unsigned int reg)
  52{
  53        unsigned int ret;
  54        asm volatile(".long 0x7c000206 | (%0 << 21) | (%1 << 16)"
  55                     : "=r" (ret) : "r" (reg));
  56        return ret;
  57}
  58
  59static inline void mtdcrx(unsigned int reg, unsigned int val)
  60{
  61        asm volatile(".long 0x7c000306 | (%0 << 21) | (%1 << 16)"
  62                     : : "r" (val), "r" (reg));
  63}
  64
  65#define mfdcr(rn)                                               \
  66        ({unsigned int rval;                                    \
  67        if (__builtin_constant_p(rn) && rn < 1024)              \
  68                asm volatile("mfdcr %0," __stringify(rn)        \
  69                              : "=r" (rval));                   \
  70        else if (likely(cpu_has_feature(CPU_FTR_INDEXED_DCR)))  \
  71                rval = mfdcrx(rn);                              \
  72        else                                                    \
  73                rval = __mfdcr(rn);                             \
  74        rval;})
  75
  76#define mtdcr(rn, v)                                            \
  77do {                                                            \
  78        if (__builtin_constant_p(rn) && rn < 1024)              \
  79                asm volatile("mtdcr " __stringify(rn) ",%0"     \
  80                              : : "r" (v));                     \
  81        else if (likely(cpu_has_feature(CPU_FTR_INDEXED_DCR)))  \
  82                mtdcrx(rn, v);                                  \
  83        else                                                    \
  84                __mtdcr(rn, v);                                 \
  85} while (0)
  86
  87/* R/W of indirect DCRs make use of standard naming conventions for DCRs */
  88extern spinlock_t dcr_ind_lock;
  89
  90static inline unsigned __mfdcri(int base_addr, int base_data, int reg)
  91{
  92        unsigned long flags;
  93        unsigned int val;
  94
  95        spin_lock_irqsave(&dcr_ind_lock, flags);
  96        if (cpu_has_feature(CPU_FTR_INDEXED_DCR)) {
  97                mtdcrx(base_addr, reg);
  98                val = mfdcrx(base_data);
  99        } else {
 100                __mtdcr(base_addr, reg);
 101                val = __mfdcr(base_data);
 102        }
 103        spin_unlock_irqrestore(&dcr_ind_lock, flags);
 104        return val;
 105}
 106
 107static inline void __mtdcri(int base_addr, int base_data, int reg,
 108                            unsigned val)
 109{
 110        unsigned long flags;
 111
 112        spin_lock_irqsave(&dcr_ind_lock, flags);
 113        if (cpu_has_feature(CPU_FTR_INDEXED_DCR)) {
 114                mtdcrx(base_addr, reg);
 115                mtdcrx(base_data, val);
 116        } else {
 117                __mtdcr(base_addr, reg);
 118                __mtdcr(base_data, val);
 119        }
 120        spin_unlock_irqrestore(&dcr_ind_lock, flags);
 121}
 122
 123static inline void __dcri_clrset(int base_addr, int base_data, int reg,
 124                                 unsigned clr, unsigned set)
 125{
 126        unsigned long flags;
 127        unsigned int val;
 128
 129        spin_lock_irqsave(&dcr_ind_lock, flags);
 130        if (cpu_has_feature(CPU_FTR_INDEXED_DCR)) {
 131                mtdcrx(base_addr, reg);
 132                val = (mfdcrx(base_data) & ~clr) | set;
 133                mtdcrx(base_data, val);
 134        } else {
 135                __mtdcr(base_addr, reg);
 136                val = (__mfdcr(base_data) & ~clr) | set;
 137                __mtdcr(base_data, val);
 138        }
 139        spin_unlock_irqrestore(&dcr_ind_lock, flags);
 140}
 141
 142#define mfdcri(base, reg)       __mfdcri(DCRN_ ## base ## _CONFIG_ADDR, \
 143                                         DCRN_ ## base ## _CONFIG_DATA, \
 144                                         reg)
 145
 146#define mtdcri(base, reg, data) __mtdcri(DCRN_ ## base ## _CONFIG_ADDR, \
 147                                         DCRN_ ## base ## _CONFIG_DATA, \
 148                                         reg, data)
 149
 150#define dcri_clrset(base, reg, clr, set)        __dcri_clrset(DCRN_ ## base ## _CONFIG_ADDR,    \
 151                                                              DCRN_ ## base ## _CONFIG_DATA,    \
 152                                                              reg, clr, set)
 153
 154#endif /* __ASSEMBLY__ */
 155#endif /* __KERNEL__ */
 156#endif /* _ASM_POWERPC_DCR_NATIVE_H */
 157