1
2
3
4
5
6
7#include <linux/clk-provider.h>
8#include <linux/err.h>
9#include <linux/device.h>
10#include <linux/of_address.h>
11#include <linux/slab.h>
12
13static DEFINE_SPINLOCK(clklock);
14
15#define MAX_FREQ 33333333
16#define MIN_FREQ 8000000
17
18struct pll_clock {
19 struct clk_hw hw;
20 void __iomem *sckcr;
21 void __iomem *pllcr;
22};
23
24#define to_pll_clock(_hw) container_of(_hw, struct pll_clock, hw)
25
26static unsigned long pll_recalc_rate(struct clk_hw *hw,
27 unsigned long parent_rate)
28{
29 struct pll_clock *pll_clock = to_pll_clock(hw);
30 int mul = 1 << (readb(pll_clock->pllcr) & 3);
31
32 return parent_rate * mul;
33}
34
35static long pll_round_rate(struct clk_hw *hw, unsigned long rate,
36 unsigned long *prate)
37{
38 int i, m = -1;
39 long offset[3];
40
41 if (rate > MAX_FREQ)
42 rate = MAX_FREQ;
43 if (rate < MIN_FREQ)
44 rate = MIN_FREQ;
45
46 for (i = 0; i < 3; i++)
47 offset[i] = abs(rate - (*prate * (1 << i)));
48 for (i = 0; i < 3; i++)
49 if (m < 0)
50 m = i;
51 else
52 m = (offset[i] < offset[m])?i:m;
53
54 return *prate * (1 << m);
55}
56
57static int pll_set_rate(struct clk_hw *hw, unsigned long rate,
58 unsigned long parent_rate)
59{
60 int pll;
61 unsigned char val;
62 unsigned long flags;
63 struct pll_clock *pll_clock = to_pll_clock(hw);
64
65 pll = ((rate / parent_rate) / 2) & 0x03;
66 spin_lock_irqsave(&clklock, flags);
67 val = readb(pll_clock->sckcr);
68 val |= 0x08;
69 writeb(val, pll_clock->sckcr);
70 val = readb(pll_clock->pllcr);
71 val &= ~0x03;
72 val |= pll;
73 writeb(val, pll_clock->pllcr);
74 spin_unlock_irqrestore(&clklock, flags);
75 return 0;
76}
77
78static const struct clk_ops pll_ops = {
79 .recalc_rate = pll_recalc_rate,
80 .round_rate = pll_round_rate,
81 .set_rate = pll_set_rate,
82};
83
84static void __init h8s2678_pll_clk_setup(struct device_node *node)
85{
86 unsigned int num_parents;
87 const char *clk_name = node->name;
88 const char *parent_name;
89 struct pll_clock *pll_clock;
90 struct clk_init_data init;
91 int ret;
92
93 num_parents = of_clk_get_parent_count(node);
94 if (!num_parents) {
95 pr_err("%s: no parent found", clk_name);
96 return;
97 }
98
99
100 pll_clock = kzalloc(sizeof(*pll_clock), GFP_KERNEL);
101 if (!pll_clock)
102 return;
103
104 pll_clock->sckcr = of_iomap(node, 0);
105 if (pll_clock->sckcr == NULL) {
106 pr_err("%s: failed to map divide register", clk_name);
107 goto free_clock;
108 }
109
110 pll_clock->pllcr = of_iomap(node, 1);
111 if (pll_clock->pllcr == NULL) {
112 pr_err("%s: failed to map multiply register", clk_name);
113 goto unmap_sckcr;
114 }
115
116 parent_name = of_clk_get_parent_name(node, 0);
117 init.name = clk_name;
118 init.ops = &pll_ops;
119 init.flags = CLK_IS_BASIC;
120 init.parent_names = &parent_name;
121 init.num_parents = 1;
122 pll_clock->hw.init = &init;
123
124 ret = clk_hw_register(NULL, &pll_clock->hw);
125 if (ret) {
126 pr_err("%s: failed to register %s div clock (%d)\n",
127 __func__, clk_name, ret);
128 goto unmap_pllcr;
129 }
130
131 of_clk_add_hw_provider(node, of_clk_hw_simple_get, &pll_clock->hw);
132 return;
133
134unmap_pllcr:
135 iounmap(pll_clock->pllcr);
136unmap_sckcr:
137 iounmap(pll_clock->sckcr);
138free_clock:
139 kfree(pll_clock);
140}
141
142CLK_OF_DECLARE(h8s2678_div_clk, "renesas,h8s2678-pll-clock",
143 h8s2678_pll_clk_setup);
144
