LXR linux/drivers/clk/rockchip/clk-mmc-phase.c

   1/*
   2 * Copyright 2014 Google, Inc
   3 * Author: Alexandru M Stan <amstan@chromium.org>
   4 *
   5 * This program is free software; you can redistribute it and/or modify
   6 * it under the terms of the GNU General Public License as published by
   7 * the Free Software Foundation; either version 2 of the License, or
   8 * (at your option) any later version.
   9 *
  10 * This program is distributed in the hope that it will be useful,
  11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 * GNU General Public License for more details.
  14 */
  15
  16#include <linux/slab.h>
  17#include <linux/clk.h>
  18#include <linux/clk-provider.h>
  19#include <linux/io.h>
  20#include <linux/kernel.h>
  21#include "clk.h"
  22
  23struct rockchip_mmc_clock {
  24        struct clk_hw   hw;
  25        void __iomem    *reg;
  26        int             id;
  27        int             shift;
  28};
  29
  30#define to_mmc_clock(_hw) container_of(_hw, struct rockchip_mmc_clock, hw)
  31
  32#define RK3288_MMC_CLKGEN_DIV 2
  33
  34static unsigned long rockchip_mmc_recalc(struct clk_hw *hw,
  35                                         unsigned long parent_rate)
  36{
  37        return parent_rate / RK3288_MMC_CLKGEN_DIV;
  38}
  39
  40#define ROCKCHIP_MMC_DELAY_SEL BIT(10)
  41#define ROCKCHIP_MMC_DEGREE_MASK 0x3
  42#define ROCKCHIP_MMC_DELAYNUM_OFFSET 2
  43#define ROCKCHIP_MMC_DELAYNUM_MASK (0xff << ROCKCHIP_MMC_DELAYNUM_OFFSET)
  44
  45#define PSECS_PER_SEC 1000000000000LL
  46
  47/*
  48 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
  49 * simplify calculations. So 45degs could be anywhere between 33deg and 57.8deg.
  50 */
  51#define ROCKCHIP_MMC_DELAY_ELEMENT_PSEC 60
  52
  53static int rockchip_mmc_get_phase(struct clk_hw *hw)
  54{
  55        struct rockchip_mmc_clock *mmc_clock = to_mmc_clock(hw);
  56        unsigned long rate = clk_get_rate(hw->clk);
  57        u32 raw_value;
  58        u16 degrees;
  59        u32 delay_num = 0;
  60
  61        raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift);
  62
  63        degrees = (raw_value & ROCKCHIP_MMC_DEGREE_MASK) * 90;
  64
  65        if (raw_value & ROCKCHIP_MMC_DELAY_SEL) {
  66                /* degrees/delaynum * 10000 */
  67                unsigned long factor = (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10) *
  68                                        36 * (rate / 1000000);
  69
  70                delay_num = (raw_value & ROCKCHIP_MMC_DELAYNUM_MASK);
  71                delay_num >>= ROCKCHIP_MMC_DELAYNUM_OFFSET;
  72                degrees += DIV_ROUND_CLOSEST(delay_num * factor, 10000);
  73        }
  74
  75        return degrees % 360;
  76}
  77
  78static int rockchip_mmc_set_phase(struct clk_hw *hw, int degrees)
  79{
  80        struct rockchip_mmc_clock *mmc_clock = to_mmc_clock(hw);
  81        unsigned long rate = clk_get_rate(hw->clk);
  82        u8 nineties, remainder;
  83        u8 delay_num;
  84        u32 raw_value;
  85        u32 delay;
  86
  87        nineties = degrees / 90;
  88        remainder = (degrees % 90);
  89
  90        /*
  91         * Due to the inexact nature of the "fine" delay, we might
  92         * actually go non-monotonic.  We don't go _too_ monotonic
  93         * though, so we should be OK.  Here are options of how we may
  94         * work:
  95         *
  96         * Ideally we end up with:
  97         *   1.0, 2.0, ..., 69.0, 70.0, ...,  89.0, 90.0
  98         *
  99         * On one extreme (if delay is actually 44ps):
 100         *   .73, 1.5, ..., 50.6, 51.3, ...,  65.3, 90.0
 101         * The other (if delay is actually 77ps):
 102         *   1.3, 2.6, ..., 88.6. 89.8, ..., 114.0, 90
 103         *
 104         * It's possible we might make a delay that is up to 25
 105         * degrees off from what we think we're making.  That's OK
 106         * though because we should be REALLY far from any bad range.
 107         */
 108
 109        /*
 110         * Convert to delay; do a little extra work to make sure we
 111         * don't overflow 32-bit / 64-bit numbers.
 112         */
 113        delay = 10000000; /* PSECS_PER_SEC / 10000 / 10 */
 114        delay *= remainder;
 115        delay = DIV_ROUND_CLOSEST(delay,
 116                        (rate / 1000) * 36 *
 117                                (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10));
 118
 119        delay_num = (u8) min_t(u32, delay, 255);
 120
 121        raw_value = delay_num ? ROCKCHIP_MMC_DELAY_SEL : 0;
 122        raw_value |= delay_num << ROCKCHIP_MMC_DELAYNUM_OFFSET;
 123        raw_value |= nineties;
 124        writel(HIWORD_UPDATE(raw_value, 0x07ff, mmc_clock->shift),
 125               mmc_clock->reg);
 126
 127        pr_debug("%s->set_phase(%d) delay_nums=%u reg[0x%p]=0x%03x actual_degrees=%d\n",
 128                clk_hw_get_name(hw), degrees, delay_num,
 129                mmc_clock->reg, raw_value>>(mmc_clock->shift),
 130                rockchip_mmc_get_phase(hw)
 131        );
 132
 133        return 0;
 134}
 135
 136static const struct clk_ops rockchip_mmc_clk_ops = {
 137        .recalc_rate    = rockchip_mmc_recalc,
 138        .get_phase      = rockchip_mmc_get_phase,
 139        .set_phase      = rockchip_mmc_set_phase,
 140};
 141
 142struct clk *rockchip_clk_register_mmc(const char *name,
 143                                const char *const *parent_names, u8 num_parents,
 144                                void __iomem *reg, int shift)
 145{
 146        struct clk_init_data init;
 147        struct rockchip_mmc_clock *mmc_clock;
 148        struct clk *clk;
 149
 150        mmc_clock = kmalloc(sizeof(*mmc_clock), GFP_KERNEL);
 151        if (!mmc_clock)
 152                return ERR_PTR(-ENOMEM);
 153
 154        init.name = name;
 155        init.flags = 0;
 156        init.num_parents = num_parents;
 157        init.parent_names = parent_names;
 158        init.ops = &rockchip_mmc_clk_ops;
 159
 160        mmc_clock->hw.init = &init;
 161        mmc_clock->reg = reg;
 162        mmc_clock->shift = shift;
 163
 164        clk = clk_register(NULL, &mmc_clock->hw);
 165        if (IS_ERR(clk))
 166                kfree(mmc_clock);
 167
 168        return clk;
 169}
 170