1#ifndef SMU72_DISCRETE_H 2#define SMU72_DISCRETE_H 3 4#include "smu72.h" 5 6#if !defined(SMC_MICROCODE) 7#pragma pack(push, 1) 8#endif 9 10struct SMIO_Pattern { 11 uint16_t Voltage; 12 uint8_t Smio; 13 uint8_t padding; 14}; 15 16typedef struct SMIO_Pattern SMIO_Pattern; 17 18struct SMIO_Table { 19 SMIO_Pattern Pattern[SMU_MAX_SMIO_LEVELS]; 20}; 21 22typedef struct SMIO_Table SMIO_Table; 23 24struct SMU72_Discrete_GraphicsLevel { 25 SMU_VoltageLevel MinVoltage; 26 27 uint32_t SclkFrequency; 28 29 uint8_t pcieDpmLevel; 30 uint8_t DeepSleepDivId; 31 uint16_t ActivityLevel; 32 33 uint32_t CgSpllFuncCntl3; 34 uint32_t CgSpllFuncCntl4; 35 uint32_t SpllSpreadSpectrum; 36 uint32_t SpllSpreadSpectrum2; 37 uint32_t CcPwrDynRm; 38 uint32_t CcPwrDynRm1; 39 uint8_t SclkDid; 40 uint8_t DisplayWatermark; 41 uint8_t EnabledForActivity; 42 uint8_t EnabledForThrottle; 43 uint8_t UpHyst; 44 uint8_t DownHyst; 45 uint8_t VoltageDownHyst; 46 uint8_t PowerThrottle; 47}; 48 49typedef struct SMU72_Discrete_GraphicsLevel SMU72_Discrete_GraphicsLevel; 50 51struct SMU72_Discrete_ACPILevel { 52 uint32_t Flags; 53 SMU_VoltageLevel MinVoltage; 54 uint32_t SclkFrequency; 55 uint8_t SclkDid; 56 uint8_t DisplayWatermark; 57 uint8_t DeepSleepDivId; 58 uint8_t padding; 59 uint32_t CgSpllFuncCntl; 60 uint32_t CgSpllFuncCntl2; 61 uint32_t CgSpllFuncCntl3; 62 uint32_t CgSpllFuncCntl4; 63 uint32_t SpllSpreadSpectrum; 64 uint32_t SpllSpreadSpectrum2; 65 uint32_t CcPwrDynRm; 66 uint32_t CcPwrDynRm1; 67}; 68 69typedef struct SMU72_Discrete_ACPILevel SMU72_Discrete_ACPILevel; 70 71struct SMU72_Discrete_Ulv { 72 uint32_t CcPwrDynRm; 73 uint32_t CcPwrDynRm1; 74 uint16_t VddcOffset; 75 uint8_t VddcOffsetVid; 76 uint8_t VddcPhase; 77 uint32_t Reserved; 78}; 79 80typedef struct SMU72_Discrete_Ulv SMU72_Discrete_Ulv; 81 82struct SMU72_Discrete_MemoryLevel { 83 SMU_VoltageLevel MinVoltage; 84 uint32_t MinMvdd; 85 86 uint32_t MclkFrequency; 87 88 uint8_t EdcReadEnable; 89 uint8_t EdcWriteEnable; 90 uint8_t RttEnable; 91 uint8_t StutterEnable; 92 93 uint8_t StrobeEnable; 94 uint8_t StrobeRatio; 95 uint8_t EnabledForThrottle; 96 uint8_t EnabledForActivity; 97 98 uint8_t UpHyst; 99 uint8_t DownHyst; 100 uint8_t VoltageDownHyst; 101 uint8_t padding; 102 103 uint16_t ActivityLevel; 104 uint8_t DisplayWatermark; 105 uint8_t padding1; 106 107 uint32_t MpllFuncCntl; 108 uint32_t MpllFuncCntl_1; 109 uint32_t MpllFuncCntl_2; 110 uint32_t MpllAdFuncCntl; 111 uint32_t MpllDqFuncCntl; 112 uint32_t MclkPwrmgtCntl; 113 uint32_t DllCntl; 114 uint32_t MpllSs1; 115 uint32_t MpllSs2; 116}; 117 118typedef struct SMU72_Discrete_MemoryLevel SMU72_Discrete_MemoryLevel; 119 120struct SMU72_Discrete_LinkLevel { 121 uint8_t PcieGenSpeed; /*< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 */ 122 uint8_t PcieLaneCount; /*< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 */ 123 uint8_t EnabledForActivity; 124 uint8_t SPC; 125 uint32_t DownThreshold; 126 uint32_t UpThreshold; 127 uint32_t Reserved; 128}; 129 130typedef struct SMU72_Discrete_LinkLevel SMU72_Discrete_LinkLevel; 131 132/* MC ARB DRAM Timing registers. */ 133struct SMU72_Discrete_MCArbDramTimingTableEntry { 134 uint32_t McArbDramTiming; 135 uint32_t McArbDramTiming2; 136 uint8_t McArbBurstTime; 137 uint8_t padding[3]; 138}; 139 140typedef struct SMU72_Discrete_MCArbDramTimingTableEntry SMU72_Discrete_MCArbDramTimingTableEntry; 141 142struct SMU72_Discrete_MCArbDramTimingTable { 143 SMU72_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS]; 144}; 145 146typedef struct SMU72_Discrete_MCArbDramTimingTable SMU72_Discrete_MCArbDramTimingTable; 147 148/* UVD VCLK/DCLK state (level) definition. */ 149struct SMU72_Discrete_UvdLevel { 150 uint32_t VclkFrequency; 151 uint32_t DclkFrequency; 152 SMU_VoltageLevel MinVoltage; 153 uint8_t VclkDivider; 154 uint8_t DclkDivider; 155 uint8_t padding[2]; 156}; 157 158typedef struct SMU72_Discrete_UvdLevel SMU72_Discrete_UvdLevel; 159 160/* Clocks for other external blocks (VCE, ACP, SAMU). */ 161struct SMU72_Discrete_ExtClkLevel { 162 uint32_t Frequency; 163 SMU_VoltageLevel MinVoltage; 164 uint8_t Divider; 165 uint8_t padding[3]; 166}; 167 168typedef struct SMU72_Discrete_ExtClkLevel SMU72_Discrete_ExtClkLevel; 169 170struct SMU72_Discrete_StateInfo { 171 uint32_t SclkFrequency; 172 uint32_t MclkFrequency; 173 uint32_t VclkFrequency; 174 uint32_t DclkFrequency; 175 uint32_t SamclkFrequency; 176 uint32_t AclkFrequency; 177 uint32_t EclkFrequency; 178 uint16_t MvddVoltage; 179 uint16_t padding16; 180 uint8_t DisplayWatermark; 181 uint8_t McArbIndex; 182 uint8_t McRegIndex; 183 uint8_t SeqIndex; 184 uint8_t SclkDid; 185 int8_t SclkIndex; 186 int8_t MclkIndex; 187 uint8_t PCIeGen; 188 189}; 190 191typedef struct SMU72_Discrete_StateInfo SMU72_Discrete_StateInfo; 192 193struct SMU72_Discrete_DpmTable { 194 /* Multi-DPM controller settings */ 195 SMU72_PIDController GraphicsPIDController; 196 SMU72_PIDController MemoryPIDController; 197 SMU72_PIDController LinkPIDController; 198 199 uint32_t SystemFlags; 200 201 /* SMIO masks for voltage and phase controls */ 202 uint32_t VRConfig; 203 uint32_t SmioMask1; 204 uint32_t SmioMask2; 205 SMIO_Table SmioTable1; 206 SMIO_Table SmioTable2; 207 208 uint32_t VddcLevelCount; 209 uint32_t VddciLevelCount; 210 uint32_t VddGfxLevelCount; 211 uint32_t MvddLevelCount; 212 213 uint16_t VddcTable[SMU72_MAX_LEVELS_VDDC]; 214 uint16_t VddGfxTable[SMU72_MAX_LEVELS_VDDGFX]; 215 uint16_t VddciTable[SMU72_MAX_LEVELS_VDDCI]; 216 217 uint8_t BapmVddGfxVidHiSidd[SMU72_MAX_LEVELS_VDDGFX]; 218 uint8_t BapmVddGfxVidLoSidd[SMU72_MAX_LEVELS_VDDGFX]; 219 uint8_t BapmVddGfxVidHiSidd2[SMU72_MAX_LEVELS_VDDGFX]; 220 221 uint8_t BapmVddcVidHiSidd[SMU72_MAX_LEVELS_VDDC]; 222 uint8_t BapmVddcVidLoSidd[SMU72_MAX_LEVELS_VDDC]; 223 uint8_t BapmVddcVidHiSidd2[SMU72_MAX_LEVELS_VDDC]; 224 225 uint8_t GraphicsDpmLevelCount; 226 uint8_t MemoryDpmLevelCount; 227 uint8_t LinkLevelCount; 228 uint8_t MasterDeepSleepControl; 229 230 uint8_t UvdLevelCount; 231 uint8_t VceLevelCount; 232 uint8_t AcpLevelCount; 233 uint8_t SamuLevelCount; 234 235 uint8_t ThermOutGpio; 236 uint8_t ThermOutPolarity; 237 uint8_t ThermOutMode; 238 uint8_t DPMFreezeAndForced; 239 uint32_t Reserved[4]; 240 241 /* State table entries for each DPM state */ 242 SMU72_Discrete_GraphicsLevel GraphicsLevel[SMU72_MAX_LEVELS_GRAPHICS]; 243 SMU72_Discrete_MemoryLevel MemoryACPILevel; 244 SMU72_Discrete_MemoryLevel MemoryLevel[SMU72_MAX_LEVELS_MEMORY]; 245 SMU72_Discrete_LinkLevel LinkLevel[SMU72_MAX_LEVELS_LINK]; 246 SMU72_Discrete_ACPILevel ACPILevel; 247 SMU72_Discrete_UvdLevel UvdLevel[SMU72_MAX_LEVELS_UVD]; 248 SMU72_Discrete_ExtClkLevel VceLevel[SMU72_MAX_LEVELS_VCE]; 249 SMU72_Discrete_ExtClkLevel AcpLevel[SMU72_MAX_LEVELS_ACP]; 250 SMU72_Discrete_ExtClkLevel SamuLevel[SMU72_MAX_LEVELS_SAMU]; 251 SMU72_Discrete_Ulv Ulv; 252 253 uint32_t SclkStepSize; 254 uint32_t Smio[SMU72_MAX_ENTRIES_SMIO]; 255 256 uint8_t UvdBootLevel; 257 uint8_t VceBootLevel; 258 uint8_t AcpBootLevel; 259 uint8_t SamuBootLevel; 260 261 uint8_t GraphicsBootLevel; 262 uint8_t GraphicsVoltageChangeEnable; 263 uint8_t GraphicsThermThrottleEnable; 264 uint8_t GraphicsInterval; 265 266 uint8_t VoltageInterval; 267 uint8_t ThermalInterval; 268 uint16_t TemperatureLimitHigh; 269 270 uint16_t TemperatureLimitLow; 271 uint8_t MemoryBootLevel; 272 uint8_t MemoryVoltageChangeEnable; 273 274 uint16_t BootMVdd; 275 uint8_t MemoryInterval; 276 uint8_t MemoryThermThrottleEnable; 277 278 uint16_t VoltageResponseTime; 279 uint16_t PhaseResponseTime; 280 281 uint8_t PCIeBootLinkLevel; 282 uint8_t PCIeGenInterval; 283 uint8_t DTEInterval; 284 uint8_t DTEMode; 285 286 uint8_t SVI2Enable; 287 uint8_t VRHotGpio; 288 uint8_t AcDcGpio; 289 uint8_t ThermGpio; 290 291 uint16_t PPM_PkgPwrLimit; 292 uint16_t PPM_TemperatureLimit; 293 294 uint16_t DefaultTdp; 295 uint16_t TargetTdp; 296 297 uint16_t FpsHighThreshold; 298 uint16_t FpsLowThreshold; 299 300 uint16_t BAPMTI_R[SMU72_DTE_ITERATIONS][SMU72_DTE_SOURCES][SMU72_DTE_SINKS]; 301 uint16_t BAPMTI_RC[SMU72_DTE_ITERATIONS][SMU72_DTE_SOURCES][SMU72_DTE_SINKS]; 302 303 uint8_t DTEAmbientTempBase; 304 uint8_t DTETjOffset; 305 uint8_t GpuTjMax; 306 uint8_t GpuTjHyst; 307 308 SMU_VoltageLevel BootVoltage; 309 310 uint32_t BAPM_TEMP_GRADIENT; 311 312 uint32_t LowSclkInterruptThreshold; 313 uint32_t VddGfxReChkWait; 314 315 uint8_t ClockStretcherAmount; 316 317 uint8_t Sclk_CKS_masterEn0_7; 318 uint8_t Sclk_CKS_masterEn8_15; 319 uint8_t padding[1]; 320 321 uint8_t Sclk_voltageOffset[8]; 322 323 SMU_ClockStretcherDataTable ClockStretcherDataTable; 324 SMU_CKS_LOOKUPTable CKS_LOOKUPTable; 325}; 326 327typedef struct SMU72_Discrete_DpmTable SMU72_Discrete_DpmTable; 328 329/* --------------------------------------------------- AC Timing Parameters ------------------------------------------------ */ 330#define SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE 16 331#define SMU72_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT SMU72_MAX_LEVELS_MEMORY /* DPM */ 332 333struct SMU72_Discrete_MCRegisterAddress { 334 uint16_t s0; 335 uint16_t s1; 336}; 337 338typedef struct SMU72_Discrete_MCRegisterAddress SMU72_Discrete_MCRegisterAddress; 339 340struct SMU72_Discrete_MCRegisterSet { 341 uint32_t value[SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE]; 342}; 343 344typedef struct SMU72_Discrete_MCRegisterSet SMU72_Discrete_MCRegisterSet; 345 346struct SMU72_Discrete_MCRegisters { 347 uint8_t last; 348 uint8_t reserved[3]; 349 SMU72_Discrete_MCRegisterAddress address[SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE]; 350 SMU72_Discrete_MCRegisterSet data[SMU72_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT]; 351}; 352 353typedef struct SMU72_Discrete_MCRegisters SMU72_Discrete_MCRegisters; 354 355 356/* --------------------------------------------------- Fan Table ----------------------------------------------------------- */ 357 358struct SMU72_Discrete_FanTable { 359 uint16_t FdoMode; 360 int16_t TempMin; 361 int16_t TempMed; 362 int16_t TempMax; 363 int16_t Slope1; 364 int16_t Slope2; 365 int16_t FdoMin; 366 int16_t HystUp; 367 int16_t HystDown; 368 int16_t HystSlope; 369 int16_t TempRespLim; 370 int16_t TempCurr; 371 int16_t SlopeCurr; 372 int16_t PwmCurr; 373 uint32_t RefreshPeriod; 374 int16_t FdoMax; 375 uint8_t TempSrc; 376 int8_t FanControl_GL_Flag; 377}; 378 379typedef struct SMU72_Discrete_FanTable SMU72_Discrete_FanTable; 380 381#define SMU7_DISCRETE_GPIO_SCLK_DEBUG 4 382#define SMU7_DISCRETE_GPIO_SCLK_DEBUG_BIT (0x1 << SMU7_DISCRETE_GPIO_SCLK_DEBUG) 383 384struct SMU7_MclkDpmScoreboard { 385 386 uint32_t PercentageBusy; 387 388 int32_t PIDError; 389 int32_t PIDIntegral; 390 int32_t PIDOutput; 391 392 uint32_t SigmaDeltaAccum; 393 uint32_t SigmaDeltaOutput; 394 uint32_t SigmaDeltaLevel; 395 396 uint32_t UtilizationSetpoint; 397 398 uint8_t TdpClampMode; 399 uint8_t TdcClampMode; 400 uint8_t ThermClampMode; 401 uint8_t VoltageBusy; 402 403 int8_t CurrLevel; 404 int8_t TargLevel; 405 uint8_t LevelChangeInProgress; 406 uint8_t UpHyst; 407 408 uint8_t DownHyst; 409 uint8_t VoltageDownHyst; 410 uint8_t DpmEnable; 411 uint8_t DpmRunning; 412 413 uint8_t DpmForce; 414 uint8_t DpmForceLevel; 415 uint8_t DisplayWatermark; 416 uint8_t McArbIndex; 417 418 uint32_t MinimumPerfMclk; 419 420 uint8_t AcpiReq; 421 uint8_t AcpiAck; 422 uint8_t MclkSwitchInProgress; 423 uint8_t MclkSwitchCritical; 424 425 uint8_t IgnoreVBlank; 426 uint8_t TargetMclkIndex; 427 uint8_t TargetMvddIndex; 428 uint8_t MclkSwitchResult; 429 430 uint16_t VbiFailureCount; 431 uint8_t VbiWaitCounter; 432 uint8_t EnabledLevelsChange; 433 434 uint16_t LevelResidencyCountersN[SMU72_MAX_LEVELS_MEMORY]; 435 uint16_t LevelSwitchCounters[SMU72_MAX_LEVELS_MEMORY]; 436 437 void (*TargetStateCalculator)(uint8_t); 438 void (*SavedTargetStateCalculator)(uint8_t); 439 440 uint16_t AutoDpmInterval; 441 uint16_t AutoDpmRange; 442 443 uint16_t VbiTimeoutCount; 444 uint16_t MclkSwitchingTime; 445 446 uint8_t fastSwitch; 447 uint8_t Save_PIC_VDDGFX_EXIT; 448 uint8_t Save_PIC_VDDGFX_ENTER; 449 uint8_t padding; 450 451}; 452 453typedef struct SMU7_MclkDpmScoreboard SMU7_MclkDpmScoreboard; 454 455struct SMU7_UlvScoreboard { 456 uint8_t EnterUlv; 457 uint8_t ExitUlv; 458 uint8_t UlvActive; 459 uint8_t WaitingForUlv; 460 uint8_t UlvEnable; 461 uint8_t UlvRunning; 462 uint8_t UlvMasterEnable; 463 uint8_t padding; 464 uint32_t UlvAbortedCount; 465 uint32_t UlvTimeStamp; 466}; 467 468typedef struct SMU7_UlvScoreboard SMU7_UlvScoreboard; 469 470struct VddgfxSavedRegisters { 471 uint32_t GPU_DBG[3]; 472 uint32_t MEC_BaseAddress_Hi; 473 uint32_t MEC_BaseAddress_Lo; 474 uint32_t THM_TMON0_CTRL2__RDIR_PRESENT; 475 uint32_t THM_TMON1_CTRL2__RDIR_PRESENT; 476 uint32_t CP_INT_CNTL; 477}; 478 479typedef struct VddgfxSavedRegisters VddgfxSavedRegisters; 480 481struct SMU7_VddGfxScoreboard { 482 uint8_t VddGfxEnable; 483 uint8_t VddGfxActive; 484 uint8_t VPUResetOccured; 485 uint8_t padding; 486 487 uint32_t VddGfxEnteredCount; 488 uint32_t VddGfxAbortedCount; 489 490 uint32_t VddGfxVid; 491 492 VddgfxSavedRegisters SavedRegisters; 493}; 494 495typedef struct SMU7_VddGfxScoreboard SMU7_VddGfxScoreboard; 496 497struct SMU7_TdcLimitScoreboard { 498 uint8_t Enable; 499 uint8_t Running; 500 uint16_t Alpha; 501 uint32_t FilteredIddc; 502 uint32_t IddcLimit; 503 uint32_t IddcHyst; 504 SMU7_HystController_Data HystControllerData; 505}; 506 507typedef struct SMU7_TdcLimitScoreboard SMU7_TdcLimitScoreboard; 508 509struct SMU7_PkgPwrLimitScoreboard { 510 uint8_t Enable; 511 uint8_t Running; 512 uint16_t Alpha; 513 uint32_t FilteredPkgPwr; 514 uint32_t Limit; 515 uint32_t Hyst; 516 uint32_t LimitFromDriver; 517 SMU7_HystController_Data HystControllerData; 518}; 519 520typedef struct SMU7_PkgPwrLimitScoreboard SMU7_PkgPwrLimitScoreboard; 521 522struct SMU7_BapmScoreboard { 523 uint32_t source_powers[SMU72_DTE_SOURCES]; 524 uint32_t source_powers_last[SMU72_DTE_SOURCES]; 525 int32_t entity_temperatures[SMU72_NUM_GPU_TES]; 526 int32_t initial_entity_temperatures[SMU72_NUM_GPU_TES]; 527 int32_t Limit; 528 int32_t Hyst; 529 int32_t therm_influence_coeff_table[SMU72_DTE_ITERATIONS * SMU72_DTE_SOURCES * SMU72_DTE_SINKS * 2]; 530 int32_t therm_node_table[SMU72_DTE_ITERATIONS * SMU72_DTE_SOURCES * SMU72_DTE_SINKS]; 531 uint16_t ConfigTDPPowerScalar; 532 uint16_t FanSpeedPowerScalar; 533 uint16_t OverDrivePowerScalar; 534 uint16_t OverDriveLimitScalar; 535 uint16_t FinalPowerScalar; 536 uint8_t VariantID; 537 uint8_t spare997; 538 539 SMU7_HystController_Data HystControllerData; 540 541 int32_t temperature_gradient_slope; 542 int32_t temperature_gradient; 543 uint32_t measured_temperature; 544}; 545 546 547typedef struct SMU7_BapmScoreboard SMU7_BapmScoreboard; 548 549struct SMU7_AcpiScoreboard { 550 uint32_t SavedInterruptMask[2]; 551 uint8_t LastACPIRequest; 552 uint8_t CgBifResp; 553 uint8_t RequestType; 554 uint8_t Padding; 555 SMU72_Discrete_ACPILevel D0Level; 556}; 557 558typedef struct SMU7_AcpiScoreboard SMU7_AcpiScoreboard; 559 560struct SMU72_Discrete_PmFuses { 561 /* dw1 */ 562 uint8_t SviLoadLineEn; 563 uint8_t SviLoadLineVddC; 564 uint8_t SviLoadLineTrimVddC; 565 uint8_t SviLoadLineOffsetVddC; 566 567 /* dw2 */ 568 uint16_t TDC_VDDC_PkgLimit; 569 uint8_t TDC_VDDC_ThrottleReleaseLimitPerc; 570 uint8_t TDC_MAWt; 571 572 /* dw3 */ 573 uint8_t TdcWaterfallCtl; 574 uint8_t LPMLTemperatureMin; 575 uint8_t LPMLTemperatureMax; 576 uint8_t Reserved; 577 578 /* dw4-dw7 */ 579 uint8_t LPMLTemperatureScaler[16]; 580 581 /* dw8-dw9 */ 582 int16_t FuzzyFan_ErrorSetDelta; 583 int16_t FuzzyFan_ErrorRateSetDelta; 584 int16_t FuzzyFan_PwmSetDelta; 585 uint16_t Reserved6; 586 587 /* dw10-dw14 */ 588 uint8_t GnbLPML[16]; 589 590 /* dw15 */ 591 uint8_t GnbLPMLMaxVid; 592 uint8_t GnbLPMLMinVid; 593 uint8_t Reserved1[2]; 594 595 /* dw16 */ 596 uint16_t BapmVddCBaseLeakageHiSidd; 597 uint16_t BapmVddCBaseLeakageLoSidd; 598}; 599 600typedef struct SMU72_Discrete_PmFuses SMU72_Discrete_PmFuses; 601 602struct SMU7_Discrete_Log_Header_Table { 603 uint32_t version; 604 uint32_t asic_id; 605 uint16_t flags; 606 uint16_t entry_size; 607 uint32_t total_size; 608 uint32_t num_of_entries; 609 uint8_t type; 610 uint8_t mode; 611 uint8_t filler_0[2]; 612 uint32_t filler_1[2]; 613}; 614 615typedef struct SMU7_Discrete_Log_Header_Table SMU7_Discrete_Log_Header_Table; 616 617struct SMU7_Discrete_Log_Cntl { 618 uint8_t Enabled; 619 uint8_t Type; 620 uint8_t padding[2]; 621 uint32_t BufferSize; 622 uint32_t SamplesLogged; 623 uint32_t SampleSize; 624 uint32_t AddrL; 625 uint32_t AddrH; 626}; 627 628typedef struct SMU7_Discrete_Log_Cntl SMU7_Discrete_Log_Cntl; 629 630#define CAC_ACC_NW_NUM_OF_SIGNALS 87 631 632struct SMU7_Discrete_Cac_Collection_Table { 633 uint32_t temperature; 634 uint32_t cac_acc_nw[CAC_ACC_NW_NUM_OF_SIGNALS]; 635}; 636 637typedef struct SMU7_Discrete_Cac_Collection_Table SMU7_Discrete_Cac_Collection_Table; 638 639struct SMU7_Discrete_Cac_Verification_Table { 640 uint32_t VddcTotalPower; 641 uint32_t VddcLeakagePower; 642 uint32_t VddcConstantPower; 643 uint32_t VddcGfxDynamicPower; 644 uint32_t VddcUvdDynamicPower; 645 uint32_t VddcVceDynamicPower; 646 uint32_t VddcAcpDynamicPower; 647 uint32_t VddcPcieDynamicPower; 648 uint32_t VddcDceDynamicPower; 649 uint32_t VddcCurrent; 650 uint32_t VddcVoltage; 651 uint32_t VddciTotalPower; 652 uint32_t VddciLeakagePower; 653 uint32_t VddciConstantPower; 654 uint32_t VddciDynamicPower; 655 uint32_t Vddr1TotalPower; 656 uint32_t Vddr1LeakagePower; 657 uint32_t Vddr1ConstantPower; 658 uint32_t Vddr1DynamicPower; 659 uint32_t spare[4]; 660 uint32_t temperature; 661}; 662 663typedef struct SMU7_Discrete_Cac_Verification_Table SMU7_Discrete_Cac_Verification_Table; 664 665struct SMU7_Discrete_Pm_Status_Table { 666 /* Thermal entities */ 667 int32_t T_meas_max; 668 int32_t T_meas_acc; 669 int32_t T_calc_max; 670 int32_t T_calc_acc; 671 uint32_t P_scalar_acc; 672 uint32_t P_calc_max; 673 uint32_t P_calc_acc; 674 675 /*Voltage domains */ 676 uint32_t I_calc_max; 677 uint32_t I_calc_acc; 678 uint32_t I_calc_acc_vddci; 679 uint32_t V_calc_noload_acc; 680 uint32_t V_calc_load_acc; 681 uint32_t V_calc_noload_acc_vddci; 682 uint32_t P_meas_acc; 683 uint32_t V_meas_noload_acc; 684 uint32_t V_meas_load_acc; 685 uint32_t I_meas_acc; 686 uint32_t P_meas_acc_vddci; 687 uint32_t V_meas_noload_acc_vddci; 688 uint32_t V_meas_load_acc_vddci; 689 uint32_t I_meas_acc_vddci; 690 691 /*Frequency */ 692 uint16_t Sclk_dpm_residency[8]; 693 uint16_t Uvd_dpm_residency[8]; 694 uint16_t Vce_dpm_residency[8]; 695 uint16_t Mclk_dpm_residency[4]; 696 697 /*Chip */ 698 uint32_t P_vddci_acc; 699 uint32_t P_vddr1_acc; 700 uint32_t P_nte1_acc; 701 uint32_t PkgPwr_max; 702 uint32_t PkgPwr_acc; 703 uint32_t MclkSwitchingTime_max; 704 uint32_t MclkSwitchingTime_acc; 705 uint32_t FanPwm_acc; 706 uint32_t FanRpm_acc; 707 708 uint32_t AccCnt; 709}; 710 711typedef struct SMU7_Discrete_Pm_Status_Table SMU7_Discrete_Pm_Status_Table; 712 713/*FIXME THESE NEED TO BE UPDATED */ 714#define SMU7_SCLK_CAC 0x561 715#define SMU7_MCLK_CAC 0xF9 716#define SMU7_VCLK_CAC 0x2DE 717#define SMU7_DCLK_CAC 0x2DE 718#define SMU7_ECLK_CAC 0x25E 719#define SMU7_ACLK_CAC 0x25E 720#define SMU7_SAMCLK_CAC 0x25E 721#define SMU7_DISPCLK_CAC 0x100 722#define SMU7_CAC_CONSTANT 0x2EE3430 723#define SMU7_CAC_CONSTANT_SHIFT 18 724 725#define SMU7_VDDCI_MCLK_CONST 1765 726#define SMU7_VDDCI_MCLK_CONST_SHIFT 16 727#define SMU7_VDDCI_VDDCI_CONST 50958 728#define SMU7_VDDCI_VDDCI_CONST_SHIFT 14 729#define SMU7_VDDCI_CONST 11781 730 731#define SMU7_12C_VDDCI_MCLK_CONST 1623 732#define SMU7_12C_VDDCI_MCLK_CONST_SHIFT 15 733#define SMU7_12C_VDDCI_VDDCI_CONST 40088 734#define SMU7_12C_VDDCI_VDDCI_CONST_SHIFT 13 735#define SMU7_12C_VDDCI_CONST 20856 736 737#define SMU7_VDDCI_STROBE_PWR 1331 738 739#define SMU7_VDDR1_CONST 693 740#define SMU7_VDDR1_CAC_WEIGHT 20 741#define SMU7_VDDR1_CAC_WEIGHT_SHIFT 19 742#define SMU7_VDDR1_STROBE_PWR 512 743 744#define SMU7_AREA_COEFF_UVD 0xA78 745#define SMU7_AREA_COEFF_VCE 0x190A 746#define SMU7_AREA_COEFF_ACP 0x22D1 747#define SMU7_AREA_COEFF_SAMU 0x534 748 749/*ThermOutMode values */ 750#define SMU7_THERM_OUT_MODE_DISABLE 0x0 751#define SMU7_THERM_OUT_MODE_THERM_ONLY 0x1 752#define SMU7_THERM_OUT_MODE_THERM_VRHOT 0x2 753 754#if !defined(SMC_MICROCODE) 755#pragma pack(pop) 756#endif 757 758 759#endif 760 761