linux/drivers/gpu/drm/sti/sti_hda.c
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   1/*
   2 * Copyright (C) STMicroelectronics SA 2014
   3 * Author: Fabien Dessenne <fabien.dessenne@st.com> for STMicroelectronics.
   4 * License terms:  GNU General Public License (GPL), version 2
   5 */
   6
   7#include <linux/clk.h>
   8#include <linux/component.h>
   9#include <linux/module.h>
  10#include <linux/platform_device.h>
  11#include <linux/seq_file.h>
  12
  13#include <drm/drmP.h>
  14#include <drm/drm_atomic_helper.h>
  15#include <drm/drm_crtc_helper.h>
  16
  17/* HDformatter registers */
  18#define HDA_ANA_CFG                     0x0000
  19#define HDA_ANA_SCALE_CTRL_Y            0x0004
  20#define HDA_ANA_SCALE_CTRL_CB           0x0008
  21#define HDA_ANA_SCALE_CTRL_CR           0x000C
  22#define HDA_ANA_ANC_CTRL                0x0010
  23#define HDA_ANA_SRC_Y_CFG               0x0014
  24#define HDA_COEFF_Y_PH1_TAP123          0x0018
  25#define HDA_COEFF_Y_PH1_TAP456          0x001C
  26#define HDA_COEFF_Y_PH2_TAP123          0x0020
  27#define HDA_COEFF_Y_PH2_TAP456          0x0024
  28#define HDA_COEFF_Y_PH3_TAP123          0x0028
  29#define HDA_COEFF_Y_PH3_TAP456          0x002C
  30#define HDA_COEFF_Y_PH4_TAP123          0x0030
  31#define HDA_COEFF_Y_PH4_TAP456          0x0034
  32#define HDA_ANA_SRC_C_CFG               0x0040
  33#define HDA_COEFF_C_PH1_TAP123          0x0044
  34#define HDA_COEFF_C_PH1_TAP456          0x0048
  35#define HDA_COEFF_C_PH2_TAP123          0x004C
  36#define HDA_COEFF_C_PH2_TAP456          0x0050
  37#define HDA_COEFF_C_PH3_TAP123          0x0054
  38#define HDA_COEFF_C_PH3_TAP456          0x0058
  39#define HDA_COEFF_C_PH4_TAP123          0x005C
  40#define HDA_COEFF_C_PH4_TAP456          0x0060
  41#define HDA_SYNC_AWGI                   0x0300
  42
  43/* HDA_ANA_CFG */
  44#define CFG_AWG_ASYNC_EN                BIT(0)
  45#define CFG_AWG_ASYNC_HSYNC_MTD         BIT(1)
  46#define CFG_AWG_ASYNC_VSYNC_MTD         BIT(2)
  47#define CFG_AWG_SYNC_DEL                BIT(3)
  48#define CFG_AWG_FLTR_MODE_SHIFT         4
  49#define CFG_AWG_FLTR_MODE_MASK          (0xF << CFG_AWG_FLTR_MODE_SHIFT)
  50#define CFG_AWG_FLTR_MODE_SD            (0 << CFG_AWG_FLTR_MODE_SHIFT)
  51#define CFG_AWG_FLTR_MODE_ED            (1 << CFG_AWG_FLTR_MODE_SHIFT)
  52#define CFG_AWG_FLTR_MODE_HD            (2 << CFG_AWG_FLTR_MODE_SHIFT)
  53#define CFG_SYNC_ON_PBPR_MASK           BIT(8)
  54#define CFG_PREFILTER_EN_MASK           BIT(9)
  55#define CFG_PBPR_SYNC_OFF_SHIFT         16
  56#define CFG_PBPR_SYNC_OFF_MASK          (0x7FF << CFG_PBPR_SYNC_OFF_SHIFT)
  57#define CFG_PBPR_SYNC_OFF_VAL           0x117 /* Voltage dependent. stiH416 */
  58
  59/* Default scaling values */
  60#define SCALE_CTRL_Y_DFLT               0x00C50256
  61#define SCALE_CTRL_CB_DFLT              0x00DB0249
  62#define SCALE_CTRL_CR_DFLT              0x00DB0249
  63
  64/* Video DACs control */
  65#define DAC_CFG_HD_HZUVW_OFF_MASK       BIT(1)
  66
  67/* Upsampler values for the alternative 2X Filter */
  68#define SAMPLER_COEF_NB                 8
  69#define HDA_ANA_SRC_Y_CFG_ALT_2X        0x01130000
  70static u32 coef_y_alt_2x[] = {
  71        0x00FE83FB, 0x1F900401, 0x00000000, 0x00000000,
  72        0x00F408F9, 0x055F7C25, 0x00000000, 0x00000000
  73};
  74
  75#define HDA_ANA_SRC_C_CFG_ALT_2X        0x01750004
  76static u32 coef_c_alt_2x[] = {
  77        0x001305F7, 0x05274BD0, 0x00000000, 0x00000000,
  78        0x0004907C, 0x09C80B9D, 0x00000000, 0x00000000
  79};
  80
  81/* Upsampler values for the 4X Filter */
  82#define HDA_ANA_SRC_Y_CFG_4X            0x01ED0005
  83#define HDA_ANA_SRC_C_CFG_4X            0x01ED0004
  84static u32 coef_yc_4x[] = {
  85        0x00FC827F, 0x008FE20B, 0x00F684FC, 0x050F7C24,
  86        0x00F4857C, 0x0A1F402E, 0x00FA027F, 0x0E076E1D
  87};
  88
  89/* AWG instructions for some video modes */
  90#define AWG_MAX_INST                    64
  91
  92/* 720p@50 */
  93static u32 AWGi_720p_50[] = {
  94        0x00000971, 0x00000C26, 0x0000013B, 0x00000CDA,
  95        0x00000104, 0x00000E7E, 0x00000E7F, 0x0000013B,
  96        0x00000D8E, 0x00000104, 0x00001804, 0x00000971,
  97        0x00000C26, 0x0000003B, 0x00000FB4, 0x00000FB5,
  98        0x00000104, 0x00001AE8
  99};
 100
 101#define NN_720p_50 ARRAY_SIZE(AWGi_720p_50)
 102
 103/* 720p@60 */
 104static u32 AWGi_720p_60[] = {
 105        0x00000971, 0x00000C26, 0x0000013B, 0x00000CDA,
 106        0x00000104, 0x00000E7E, 0x00000E7F, 0x0000013B,
 107        0x00000C44, 0x00000104, 0x00001804, 0x00000971,
 108        0x00000C26, 0x0000003B, 0x00000F0F, 0x00000F10,
 109        0x00000104, 0x00001AE8
 110};
 111
 112#define NN_720p_60 ARRAY_SIZE(AWGi_720p_60)
 113
 114/* 1080p@30 */
 115static u32 AWGi_1080p_30[] = {
 116        0x00000971, 0x00000C2A, 0x0000013B, 0x00000C56,
 117        0x00000104, 0x00000FDC, 0x00000FDD, 0x0000013B,
 118        0x00000C2A, 0x00000104, 0x00001804, 0x00000971,
 119        0x00000C2A, 0x0000003B, 0x00000EBE, 0x00000EBF,
 120        0x00000EBF, 0x00000104, 0x00001A2F, 0x00001C4B,
 121        0x00001C52
 122};
 123
 124#define NN_1080p_30 ARRAY_SIZE(AWGi_1080p_30)
 125
 126/* 1080p@25 */
 127static u32 AWGi_1080p_25[] = {
 128        0x00000971, 0x00000C2A, 0x0000013B, 0x00000C56,
 129        0x00000104, 0x00000FDC, 0x00000FDD, 0x0000013B,
 130        0x00000DE2, 0x00000104, 0x00001804, 0x00000971,
 131        0x00000C2A, 0x0000003B, 0x00000F51, 0x00000F51,
 132        0x00000F52, 0x00000104, 0x00001A2F, 0x00001C4B,
 133        0x00001C52
 134};
 135
 136#define NN_1080p_25 ARRAY_SIZE(AWGi_1080p_25)
 137
 138/* 1080p@24 */
 139static u32 AWGi_1080p_24[] = {
 140        0x00000971, 0x00000C2A, 0x0000013B, 0x00000C56,
 141        0x00000104, 0x00000FDC, 0x00000FDD, 0x0000013B,
 142        0x00000E50, 0x00000104, 0x00001804, 0x00000971,
 143        0x00000C2A, 0x0000003B, 0x00000F76, 0x00000F76,
 144        0x00000F76, 0x00000104, 0x00001A2F, 0x00001C4B,
 145        0x00001C52
 146};
 147
 148#define NN_1080p_24 ARRAY_SIZE(AWGi_1080p_24)
 149
 150/* 720x480p@60 */
 151static u32 AWGi_720x480p_60[] = {
 152        0x00000904, 0x00000F18, 0x0000013B, 0x00001805,
 153        0x00000904, 0x00000C3D, 0x0000003B, 0x00001A06
 154};
 155
 156#define NN_720x480p_60 ARRAY_SIZE(AWGi_720x480p_60)
 157
 158/* Video mode category */
 159enum sti_hda_vid_cat {
 160        VID_SD,
 161        VID_ED,
 162        VID_HD_74M,
 163        VID_HD_148M
 164};
 165
 166struct sti_hda_video_config {
 167        struct drm_display_mode mode;
 168        u32 *awg_instr;
 169        int nb_instr;
 170        enum sti_hda_vid_cat vid_cat;
 171};
 172
 173/* HD analog supported modes
 174 * Interlaced modes may be added when supported by the whole display chain
 175 */
 176static const struct sti_hda_video_config hda_supported_modes[] = {
 177        /* 1080p30 74.250Mhz */
 178        {{DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
 179                   2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
 180                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
 181         AWGi_1080p_30, NN_1080p_30, VID_HD_74M},
 182        /* 1080p30 74.176Mhz */
 183        {{DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74176, 1920, 2008,
 184                   2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
 185                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
 186         AWGi_1080p_30, NN_1080p_30, VID_HD_74M},
 187        /* 1080p24 74.250Mhz */
 188        {{DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
 189                   2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
 190                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
 191         AWGi_1080p_24, NN_1080p_24, VID_HD_74M},
 192        /* 1080p24 74.176Mhz */
 193        {{DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74176, 1920, 2558,
 194                   2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
 195                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
 196         AWGi_1080p_24, NN_1080p_24, VID_HD_74M},
 197        /* 1080p25 74.250Mhz */
 198        {{DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
 199                   2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
 200                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
 201         AWGi_1080p_25, NN_1080p_25, VID_HD_74M},
 202        /* 720p60 74.250Mhz */
 203        {{DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
 204                   1430, 1650, 0, 720, 725, 730, 750, 0,
 205                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
 206         AWGi_720p_60, NN_720p_60, VID_HD_74M},
 207        /* 720p60 74.176Mhz */
 208        {{DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74176, 1280, 1390,
 209                   1430, 1650, 0, 720, 725, 730, 750, 0,
 210                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
 211         AWGi_720p_60, NN_720p_60, VID_HD_74M},
 212        /* 720p50 74.250Mhz */
 213        {{DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
 214                   1760, 1980, 0, 720, 725, 730, 750, 0,
 215                   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
 216         AWGi_720p_50, NN_720p_50, VID_HD_74M},
 217        /* 720x480p60 27.027Mhz */
 218        {{DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27027, 720, 736,
 219                   798, 858, 0, 480, 489, 495, 525, 0,
 220                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC)},
 221         AWGi_720x480p_60, NN_720x480p_60, VID_ED},
 222        /* 720x480p60 27.000Mhz */
 223        {{DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
 224                   798, 858, 0, 480, 489, 495, 525, 0,
 225                   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC)},
 226         AWGi_720x480p_60, NN_720x480p_60, VID_ED}
 227};
 228
 229/**
 230 * STI hd analog structure
 231 *
 232 * @dev: driver device
 233 * @drm_dev: pointer to drm device
 234 * @mode: current display mode selected
 235 * @regs: HD analog register
 236 * @video_dacs_ctrl: video DACS control register
 237 * @enabled: true if HD analog is enabled else false
 238 */
 239struct sti_hda {
 240        struct device dev;
 241        struct drm_device *drm_dev;
 242        struct drm_display_mode mode;
 243        void __iomem *regs;
 244        void __iomem *video_dacs_ctrl;
 245        struct clk *clk_pix;
 246        struct clk *clk_hddac;
 247        bool enabled;
 248};
 249
 250struct sti_hda_connector {
 251        struct drm_connector drm_connector;
 252        struct drm_encoder *encoder;
 253        struct sti_hda *hda;
 254};
 255
 256#define to_sti_hda_connector(x) \
 257        container_of(x, struct sti_hda_connector, drm_connector)
 258
 259static u32 hda_read(struct sti_hda *hda, int offset)
 260{
 261        return readl(hda->regs + offset);
 262}
 263
 264static void hda_write(struct sti_hda *hda, u32 val, int offset)
 265{
 266        writel(val, hda->regs + offset);
 267}
 268
 269/**
 270 * Search for a video mode in the supported modes table
 271 *
 272 * @mode: mode being searched
 273 * @idx: index of the found mode
 274 *
 275 * Return true if mode is found
 276 */
 277static bool hda_get_mode_idx(struct drm_display_mode mode, int *idx)
 278{
 279        unsigned int i;
 280
 281        for (i = 0; i < ARRAY_SIZE(hda_supported_modes); i++)
 282                if (drm_mode_equal(&hda_supported_modes[i].mode, &mode)) {
 283                        *idx = i;
 284                        return true;
 285                }
 286        return false;
 287}
 288
 289/**
 290 * Enable the HD DACS
 291 *
 292 * @hda: pointer to HD analog structure
 293 * @enable: true if HD DACS need to be enabled, else false
 294 */
 295static void hda_enable_hd_dacs(struct sti_hda *hda, bool enable)
 296{
 297        if (hda->video_dacs_ctrl) {
 298                u32 val;
 299
 300                val = readl(hda->video_dacs_ctrl);
 301                if (enable)
 302                        val &= ~DAC_CFG_HD_HZUVW_OFF_MASK;
 303                else
 304                        val |= DAC_CFG_HD_HZUVW_OFF_MASK;
 305
 306                writel(val, hda->video_dacs_ctrl);
 307        }
 308}
 309
 310#define DBGFS_DUMP(reg) seq_printf(s, "\n  %-25s 0x%08X", #reg, \
 311                                   readl(hda->regs + reg))
 312
 313static void hda_dbg_cfg(struct seq_file *s, int val)
 314{
 315        seq_puts(s, "\tAWG ");
 316        seq_puts(s, val & CFG_AWG_ASYNC_EN ? "enabled" : "disabled");
 317}
 318
 319static void hda_dbg_awg_microcode(struct seq_file *s, void __iomem *reg)
 320{
 321        unsigned int i;
 322
 323        seq_puts(s, "\n\n");
 324        seq_puts(s, "  HDA AWG microcode:");
 325        for (i = 0; i < AWG_MAX_INST; i++) {
 326                if (i % 8 == 0)
 327                        seq_printf(s, "\n  %04X:", i);
 328                seq_printf(s, " %04X", readl(reg + i * 4));
 329        }
 330}
 331
 332static void hda_dbg_video_dacs_ctrl(struct seq_file *s, void __iomem *reg)
 333{
 334        u32 val = readl(reg);
 335
 336        seq_puts(s, "\n");
 337        seq_printf(s, "\n  %-25s 0x%08X", "VIDEO_DACS_CONTROL", val);
 338        seq_puts(s, "\tHD DACs ");
 339        seq_puts(s, val & DAC_CFG_HD_HZUVW_OFF_MASK ? "disabled" : "enabled");
 340}
 341
 342static int hda_dbg_show(struct seq_file *s, void *data)
 343{
 344        struct drm_info_node *node = s->private;
 345        struct sti_hda *hda = (struct sti_hda *)node->info_ent->data;
 346
 347        seq_printf(s, "HD Analog: (vaddr = 0x%p)", hda->regs);
 348        DBGFS_DUMP(HDA_ANA_CFG);
 349        hda_dbg_cfg(s, readl(hda->regs + HDA_ANA_CFG));
 350        DBGFS_DUMP(HDA_ANA_SCALE_CTRL_Y);
 351        DBGFS_DUMP(HDA_ANA_SCALE_CTRL_CB);
 352        DBGFS_DUMP(HDA_ANA_SCALE_CTRL_CR);
 353        DBGFS_DUMP(HDA_ANA_ANC_CTRL);
 354        DBGFS_DUMP(HDA_ANA_SRC_Y_CFG);
 355        DBGFS_DUMP(HDA_ANA_SRC_C_CFG);
 356        hda_dbg_awg_microcode(s, hda->regs + HDA_SYNC_AWGI);
 357        if (hda->video_dacs_ctrl)
 358                hda_dbg_video_dacs_ctrl(s, hda->video_dacs_ctrl);
 359        seq_puts(s, "\n");
 360
 361        return 0;
 362}
 363
 364static struct drm_info_list hda_debugfs_files[] = {
 365        { "hda", hda_dbg_show, 0, NULL },
 366};
 367
 368static void hda_debugfs_exit(struct sti_hda *hda, struct drm_minor *minor)
 369{
 370        drm_debugfs_remove_files(hda_debugfs_files,
 371                                 ARRAY_SIZE(hda_debugfs_files),
 372                                 minor);
 373}
 374
 375static int hda_debugfs_init(struct sti_hda *hda, struct drm_minor *minor)
 376{
 377        unsigned int i;
 378
 379        for (i = 0; i < ARRAY_SIZE(hda_debugfs_files); i++)
 380                hda_debugfs_files[i].data = hda;
 381
 382        return drm_debugfs_create_files(hda_debugfs_files,
 383                                        ARRAY_SIZE(hda_debugfs_files),
 384                                        minor->debugfs_root, minor);
 385}
 386
 387/**
 388 * Configure AWG, writing instructions
 389 *
 390 * @hda: pointer to HD analog structure
 391 * @awg_instr: pointer to AWG instructions table
 392 * @nb: nb of AWG instructions
 393 */
 394static void sti_hda_configure_awg(struct sti_hda *hda, u32 *awg_instr, int nb)
 395{
 396        unsigned int i;
 397
 398        DRM_DEBUG_DRIVER("\n");
 399
 400        for (i = 0; i < nb; i++)
 401                hda_write(hda, awg_instr[i], HDA_SYNC_AWGI + i * 4);
 402        for (i = nb; i < AWG_MAX_INST; i++)
 403                hda_write(hda, 0, HDA_SYNC_AWGI + i * 4);
 404}
 405
 406static void sti_hda_disable(struct drm_bridge *bridge)
 407{
 408        struct sti_hda *hda = bridge->driver_private;
 409        u32 val;
 410
 411        if (!hda->enabled)
 412                return;
 413
 414        DRM_DEBUG_DRIVER("\n");
 415
 416        /* Disable HD DAC and AWG */
 417        val = hda_read(hda, HDA_ANA_CFG);
 418        val &= ~CFG_AWG_ASYNC_EN;
 419        hda_write(hda, val, HDA_ANA_CFG);
 420        hda_write(hda, 0, HDA_ANA_ANC_CTRL);
 421
 422        hda_enable_hd_dacs(hda, false);
 423
 424        /* Disable/unprepare hda clock */
 425        clk_disable_unprepare(hda->clk_hddac);
 426        clk_disable_unprepare(hda->clk_pix);
 427
 428        hda->enabled = false;
 429}
 430
 431static void sti_hda_pre_enable(struct drm_bridge *bridge)
 432{
 433        struct sti_hda *hda = bridge->driver_private;
 434        u32 val, i, mode_idx;
 435        u32 src_filter_y, src_filter_c;
 436        u32 *coef_y, *coef_c;
 437        u32 filter_mode;
 438
 439        DRM_DEBUG_DRIVER("\n");
 440
 441        if (hda->enabled)
 442                return;
 443
 444        /* Prepare/enable clocks */
 445        if (clk_prepare_enable(hda->clk_pix))
 446                DRM_ERROR("Failed to prepare/enable hda_pix clk\n");
 447        if (clk_prepare_enable(hda->clk_hddac))
 448                DRM_ERROR("Failed to prepare/enable hda_hddac clk\n");
 449
 450        if (!hda_get_mode_idx(hda->mode, &mode_idx)) {
 451                DRM_ERROR("Undefined mode\n");
 452                return;
 453        }
 454
 455        switch (hda_supported_modes[mode_idx].vid_cat) {
 456        case VID_HD_148M:
 457                DRM_ERROR("Beyond HD analog capabilities\n");
 458                return;
 459        case VID_HD_74M:
 460                /* HD use alternate 2x filter */
 461                filter_mode = CFG_AWG_FLTR_MODE_HD;
 462                src_filter_y = HDA_ANA_SRC_Y_CFG_ALT_2X;
 463                src_filter_c = HDA_ANA_SRC_C_CFG_ALT_2X;
 464                coef_y = coef_y_alt_2x;
 465                coef_c = coef_c_alt_2x;
 466                break;
 467        case VID_ED:
 468                /* ED uses 4x filter */
 469                filter_mode = CFG_AWG_FLTR_MODE_ED;
 470                src_filter_y = HDA_ANA_SRC_Y_CFG_4X;
 471                src_filter_c = HDA_ANA_SRC_C_CFG_4X;
 472                coef_y = coef_yc_4x;
 473                coef_c = coef_yc_4x;
 474                break;
 475        case VID_SD:
 476                DRM_ERROR("Not supported\n");
 477                return;
 478        default:
 479                DRM_ERROR("Undefined resolution\n");
 480                return;
 481        }
 482        DRM_DEBUG_DRIVER("Using HDA mode #%d\n", mode_idx);
 483
 484        /* Enable HD Video DACs */
 485        hda_enable_hd_dacs(hda, true);
 486
 487        /* Configure scaler */
 488        hda_write(hda, SCALE_CTRL_Y_DFLT, HDA_ANA_SCALE_CTRL_Y);
 489        hda_write(hda, SCALE_CTRL_CB_DFLT, HDA_ANA_SCALE_CTRL_CB);
 490        hda_write(hda, SCALE_CTRL_CR_DFLT, HDA_ANA_SCALE_CTRL_CR);
 491
 492        /* Configure sampler */
 493        hda_write(hda , src_filter_y, HDA_ANA_SRC_Y_CFG);
 494        hda_write(hda, src_filter_c,  HDA_ANA_SRC_C_CFG);
 495        for (i = 0; i < SAMPLER_COEF_NB; i++) {
 496                hda_write(hda, coef_y[i], HDA_COEFF_Y_PH1_TAP123 + i * 4);
 497                hda_write(hda, coef_c[i], HDA_COEFF_C_PH1_TAP123 + i * 4);
 498        }
 499
 500        /* Configure main HDFormatter */
 501        val = 0;
 502        val |= (hda->mode.flags & DRM_MODE_FLAG_INTERLACE) ?
 503            0 : CFG_AWG_ASYNC_VSYNC_MTD;
 504        val |= (CFG_PBPR_SYNC_OFF_VAL << CFG_PBPR_SYNC_OFF_SHIFT);
 505        val |= filter_mode;
 506        hda_write(hda, val, HDA_ANA_CFG);
 507
 508        /* Configure AWG */
 509        sti_hda_configure_awg(hda, hda_supported_modes[mode_idx].awg_instr,
 510                              hda_supported_modes[mode_idx].nb_instr);
 511
 512        /* Enable AWG */
 513        val = hda_read(hda, HDA_ANA_CFG);
 514        val |= CFG_AWG_ASYNC_EN;
 515        hda_write(hda, val, HDA_ANA_CFG);
 516
 517        hda->enabled = true;
 518}
 519
 520static void sti_hda_set_mode(struct drm_bridge *bridge,
 521                struct drm_display_mode *mode,
 522                struct drm_display_mode *adjusted_mode)
 523{
 524        struct sti_hda *hda = bridge->driver_private;
 525        u32 mode_idx;
 526        int hddac_rate;
 527        int ret;
 528
 529        DRM_DEBUG_DRIVER("\n");
 530
 531        memcpy(&hda->mode, mode, sizeof(struct drm_display_mode));
 532
 533        if (!hda_get_mode_idx(hda->mode, &mode_idx)) {
 534                DRM_ERROR("Undefined mode\n");
 535                return;
 536        }
 537
 538        switch (hda_supported_modes[mode_idx].vid_cat) {
 539        case VID_HD_74M:
 540                /* HD use alternate 2x filter */
 541                hddac_rate = mode->clock * 1000 * 2;
 542                break;
 543        case VID_ED:
 544                /* ED uses 4x filter */
 545                hddac_rate = mode->clock * 1000 * 4;
 546                break;
 547        default:
 548                DRM_ERROR("Undefined mode\n");
 549                return;
 550        }
 551
 552        /* HD DAC = 148.5Mhz or 108 Mhz */
 553        ret = clk_set_rate(hda->clk_hddac, hddac_rate);
 554        if (ret < 0)
 555                DRM_ERROR("Cannot set rate (%dHz) for hda_hddac clk\n",
 556                          hddac_rate);
 557
 558        /* HDformatter clock = compositor clock */
 559        ret = clk_set_rate(hda->clk_pix, mode->clock * 1000);
 560        if (ret < 0)
 561                DRM_ERROR("Cannot set rate (%dHz) for hda_pix clk\n",
 562                          mode->clock * 1000);
 563}
 564
 565static void sti_hda_bridge_nope(struct drm_bridge *bridge)
 566{
 567        /* do nothing */
 568}
 569
 570static const struct drm_bridge_funcs sti_hda_bridge_funcs = {
 571        .pre_enable = sti_hda_pre_enable,
 572        .enable = sti_hda_bridge_nope,
 573        .disable = sti_hda_disable,
 574        .post_disable = sti_hda_bridge_nope,
 575        .mode_set = sti_hda_set_mode,
 576};
 577
 578static int sti_hda_connector_get_modes(struct drm_connector *connector)
 579{
 580        unsigned int i;
 581        int count = 0;
 582        struct sti_hda_connector *hda_connector
 583                = to_sti_hda_connector(connector);
 584        struct sti_hda *hda = hda_connector->hda;
 585
 586        DRM_DEBUG_DRIVER("\n");
 587
 588        for (i = 0; i < ARRAY_SIZE(hda_supported_modes); i++) {
 589                struct drm_display_mode *mode =
 590                        drm_mode_duplicate(hda->drm_dev,
 591                                        &hda_supported_modes[i].mode);
 592                if (!mode)
 593                        continue;
 594                mode->vrefresh = drm_mode_vrefresh(mode);
 595
 596                /* the first mode is the preferred mode */
 597                if (i == 0)
 598                        mode->type |= DRM_MODE_TYPE_PREFERRED;
 599
 600                drm_mode_probed_add(connector, mode);
 601                count++;
 602        }
 603
 604        return count;
 605}
 606
 607#define CLK_TOLERANCE_HZ 50
 608
 609static int sti_hda_connector_mode_valid(struct drm_connector *connector,
 610                                        struct drm_display_mode *mode)
 611{
 612        int target = mode->clock * 1000;
 613        int target_min = target - CLK_TOLERANCE_HZ;
 614        int target_max = target + CLK_TOLERANCE_HZ;
 615        int result;
 616        int idx;
 617        struct sti_hda_connector *hda_connector
 618                = to_sti_hda_connector(connector);
 619        struct sti_hda *hda = hda_connector->hda;
 620
 621        if (!hda_get_mode_idx(*mode, &idx)) {
 622                return MODE_BAD;
 623        } else {
 624                result = clk_round_rate(hda->clk_pix, target);
 625
 626                DRM_DEBUG_DRIVER("target rate = %d => available rate = %d\n",
 627                                 target, result);
 628
 629                if ((result < target_min) || (result > target_max)) {
 630                        DRM_DEBUG_DRIVER("hda pixclk=%d not supported\n",
 631                                         target);
 632                        return MODE_BAD;
 633                }
 634        }
 635
 636        return MODE_OK;
 637}
 638
 639static const
 640struct drm_connector_helper_funcs sti_hda_connector_helper_funcs = {
 641        .get_modes = sti_hda_connector_get_modes,
 642        .mode_valid = sti_hda_connector_mode_valid,
 643};
 644
 645static enum drm_connector_status
 646sti_hda_connector_detect(struct drm_connector *connector, bool force)
 647{
 648        return connector_status_connected;
 649}
 650
 651static int sti_hda_late_register(struct drm_connector *connector)
 652{
 653        struct sti_hda_connector *hda_connector
 654                = to_sti_hda_connector(connector);
 655        struct sti_hda *hda = hda_connector->hda;
 656
 657        if (hda_debugfs_init(hda, hda->drm_dev->primary)) {
 658                DRM_ERROR("HDA debugfs setup failed\n");
 659                return -EINVAL;
 660        }
 661
 662        return 0;
 663}
 664
 665static const struct drm_connector_funcs sti_hda_connector_funcs = {
 666        .dpms = drm_atomic_helper_connector_dpms,
 667        .fill_modes = drm_helper_probe_single_connector_modes,
 668        .detect = sti_hda_connector_detect,
 669        .destroy = drm_connector_cleanup,
 670        .reset = drm_atomic_helper_connector_reset,
 671        .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 672        .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 673        .late_register = sti_hda_late_register,
 674};
 675
 676static struct drm_encoder *sti_hda_find_encoder(struct drm_device *dev)
 677{
 678        struct drm_encoder *encoder;
 679
 680        list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 681                if (encoder->encoder_type == DRM_MODE_ENCODER_DAC)
 682                        return encoder;
 683        }
 684
 685        return NULL;
 686}
 687
 688static int sti_hda_bind(struct device *dev, struct device *master, void *data)
 689{
 690        struct sti_hda *hda = dev_get_drvdata(dev);
 691        struct drm_device *drm_dev = data;
 692        struct drm_encoder *encoder;
 693        struct sti_hda_connector *connector;
 694        struct drm_connector *drm_connector;
 695        struct drm_bridge *bridge;
 696        int err;
 697
 698        /* Set the drm device handle */
 699        hda->drm_dev = drm_dev;
 700
 701        encoder = sti_hda_find_encoder(drm_dev);
 702        if (!encoder)
 703                return -ENOMEM;
 704
 705        connector = devm_kzalloc(dev, sizeof(*connector), GFP_KERNEL);
 706        if (!connector)
 707                return -ENOMEM;
 708
 709        connector->hda = hda;
 710
 711                bridge = devm_kzalloc(dev, sizeof(*bridge), GFP_KERNEL);
 712        if (!bridge)
 713                return -ENOMEM;
 714
 715        bridge->driver_private = hda;
 716        bridge->funcs = &sti_hda_bridge_funcs;
 717        drm_bridge_attach(drm_dev, bridge);
 718
 719        encoder->bridge = bridge;
 720        connector->encoder = encoder;
 721
 722        drm_connector = (struct drm_connector *)connector;
 723
 724        drm_connector->polled = DRM_CONNECTOR_POLL_HPD;
 725
 726        drm_connector_init(drm_dev, drm_connector,
 727                        &sti_hda_connector_funcs, DRM_MODE_CONNECTOR_Component);
 728        drm_connector_helper_add(drm_connector,
 729                        &sti_hda_connector_helper_funcs);
 730
 731        err = drm_mode_connector_attach_encoder(drm_connector, encoder);
 732        if (err) {
 733                DRM_ERROR("Failed to attach a connector to a encoder\n");
 734                goto err_sysfs;
 735        }
 736
 737        /* force to disable hd dacs at startup */
 738        hda_enable_hd_dacs(hda, false);
 739
 740        return 0;
 741
 742err_sysfs:
 743        drm_bridge_remove(bridge);
 744        return -EINVAL;
 745}
 746
 747static void sti_hda_unbind(struct device *dev,
 748                struct device *master, void *data)
 749{
 750        struct sti_hda *hda = dev_get_drvdata(dev);
 751        struct drm_device *drm_dev = data;
 752
 753        hda_debugfs_exit(hda, drm_dev->primary);
 754}
 755
 756static const struct component_ops sti_hda_ops = {
 757        .bind = sti_hda_bind,
 758        .unbind = sti_hda_unbind,
 759};
 760
 761static int sti_hda_probe(struct platform_device *pdev)
 762{
 763        struct device *dev = &pdev->dev;
 764        struct sti_hda *hda;
 765        struct resource *res;
 766
 767        DRM_INFO("%s\n", __func__);
 768
 769        hda = devm_kzalloc(dev, sizeof(*hda), GFP_KERNEL);
 770        if (!hda)
 771                return -ENOMEM;
 772
 773        hda->dev = pdev->dev;
 774
 775        /* Get resources */
 776        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hda-reg");
 777        if (!res) {
 778                DRM_ERROR("Invalid hda resource\n");
 779                return -ENOMEM;
 780        }
 781        hda->regs = devm_ioremap_nocache(dev, res->start, resource_size(res));
 782        if (!hda->regs)
 783                return -ENOMEM;
 784
 785        res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 786                        "video-dacs-ctrl");
 787        if (res) {
 788                hda->video_dacs_ctrl = devm_ioremap_nocache(dev, res->start,
 789                                resource_size(res));
 790                if (!hda->video_dacs_ctrl)
 791                        return -ENOMEM;
 792        } else {
 793                /* If no existing video-dacs-ctrl resource continue the probe */
 794                DRM_DEBUG_DRIVER("No video-dacs-ctrl resource\n");
 795                hda->video_dacs_ctrl = NULL;
 796        }
 797
 798        /* Get clock resources */
 799        hda->clk_pix = devm_clk_get(dev, "pix");
 800        if (IS_ERR(hda->clk_pix)) {
 801                DRM_ERROR("Cannot get hda_pix clock\n");
 802                return PTR_ERR(hda->clk_pix);
 803        }
 804
 805        hda->clk_hddac = devm_clk_get(dev, "hddac");
 806        if (IS_ERR(hda->clk_hddac)) {
 807                DRM_ERROR("Cannot get hda_hddac clock\n");
 808                return PTR_ERR(hda->clk_hddac);
 809        }
 810
 811        platform_set_drvdata(pdev, hda);
 812
 813        return component_add(&pdev->dev, &sti_hda_ops);
 814}
 815
 816static int sti_hda_remove(struct platform_device *pdev)
 817{
 818        component_del(&pdev->dev, &sti_hda_ops);
 819        return 0;
 820}
 821
 822static const struct of_device_id hda_of_match[] = {
 823        { .compatible = "st,stih416-hda", },
 824        { .compatible = "st,stih407-hda", },
 825        { /* end node */ }
 826};
 827MODULE_DEVICE_TABLE(of, hda_of_match);
 828
 829struct platform_driver sti_hda_driver = {
 830        .driver = {
 831                .name = "sti-hda",
 832                .owner = THIS_MODULE,
 833                .of_match_table = hda_of_match,
 834        },
 835        .probe = sti_hda_probe,
 836        .remove = sti_hda_remove,
 837};
 838
 839MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>");
 840MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver");
 841MODULE_LICENSE("GPL");
 842