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23#include <linux/kernel.h>
24#include <linux/init.h>
25#include <linux/module.h>
26#include <linux/string.h>
27#include <linux/slab.h>
28#include "dvb_frontend.h"
29#include "lgs8gl5.h"
30
31
32#define REG_RESET 0x02
33#define REG_RESET_OFF 0x01
34#define REG_03 0x03
35#define REG_04 0x04
36#define REG_07 0x07
37#define REG_09 0x09
38#define REG_0A 0x0a
39#define REG_0B 0x0b
40#define REG_0C 0x0c
41#define REG_37 0x37
42#define REG_STRENGTH 0x4b
43#define REG_STRENGTH_MASK 0x7f
44#define REG_STRENGTH_CARRIER 0x80
45#define REG_INVERSION 0x7c
46#define REG_INVERSION_ON 0x80
47#define REG_7D 0x7d
48#define REG_7E 0x7e
49#define REG_A2 0xa2
50#define REG_STATUS 0xa4
51#define REG_STATUS_SYNC 0x04
52#define REG_STATUS_LOCK 0x01
53
54
55struct lgs8gl5_state {
56 struct i2c_adapter *i2c;
57 const struct lgs8gl5_config *config;
58 struct dvb_frontend frontend;
59};
60
61
62static int debug;
63#define dprintk(args...) \
64 do { \
65 if (debug) \
66 printk(KERN_DEBUG "lgs8gl5: " args); \
67 } while (0)
68
69
70
71static int
72lgs8gl5_write_reg(struct lgs8gl5_state *state, u8 reg, u8 data)
73{
74 int ret;
75 u8 buf[] = {reg, data};
76 struct i2c_msg msg = {
77 .addr = state->config->demod_address,
78 .flags = 0,
79 .buf = buf,
80 .len = 2
81 };
82
83 ret = i2c_transfer(state->i2c, &msg, 1);
84 if (ret != 1)
85 dprintk("%s: error (reg=0x%02x, val=0x%02x, ret=%i)\n",
86 __func__, reg, data, ret);
87 return (ret != 1) ? -1 : 0;
88}
89
90
91
92static int
93lgs8gl5_read_reg(struct lgs8gl5_state *state, u8 reg)
94{
95 int ret;
96 u8 b0[] = {reg};
97 u8 b1[] = {0};
98 struct i2c_msg msg[2] = {
99 {
100 .addr = state->config->demod_address,
101 .flags = 0,
102 .buf = b0,
103 .len = 1
104 },
105 {
106 .addr = state->config->demod_address,
107 .flags = I2C_M_RD,
108 .buf = b1,
109 .len = 1
110 }
111 };
112
113 ret = i2c_transfer(state->i2c, msg, 2);
114 if (ret != 2)
115 return -EIO;
116
117 return b1[0];
118}
119
120
121static int
122lgs8gl5_update_reg(struct lgs8gl5_state *state, u8 reg, u8 data)
123{
124 lgs8gl5_read_reg(state, reg);
125 lgs8gl5_write_reg(state, reg, data);
126 return 0;
127}
128
129
130
131
132static int
133lgs8gl5_update_alt_reg(struct lgs8gl5_state *state, u8 reg, u8 data)
134{
135 int ret;
136 u8 b0[] = {reg};
137 u8 b1[] = {0};
138 u8 b2[] = {reg, data};
139 struct i2c_msg msg[3] = {
140 {
141 .addr = state->config->demod_address + 2,
142 .flags = 0,
143 .buf = b0,
144 .len = 1
145 },
146 {
147 .addr = state->config->demod_address + 2,
148 .flags = I2C_M_RD,
149 .buf = b1,
150 .len = 1
151 },
152 {
153 .addr = state->config->demod_address + 2,
154 .flags = 0,
155 .buf = b2,
156 .len = 2
157 },
158 };
159
160 ret = i2c_transfer(state->i2c, msg, 3);
161 return (ret != 3) ? -1 : 0;
162}
163
164
165static void
166lgs8gl5_soft_reset(struct lgs8gl5_state *state)
167{
168 u8 val;
169
170 dprintk("%s\n", __func__);
171
172 val = lgs8gl5_read_reg(state, REG_RESET);
173 lgs8gl5_write_reg(state, REG_RESET, val & ~REG_RESET_OFF);
174 lgs8gl5_write_reg(state, REG_RESET, val | REG_RESET_OFF);
175 msleep(5);
176}
177
178
179
180static void
181lgs8gl5_start_demod(struct lgs8gl5_state *state)
182{
183 u8 val;
184 int n;
185
186 dprintk("%s\n", __func__);
187
188 lgs8gl5_update_alt_reg(state, 0xc2, 0x28);
189 lgs8gl5_soft_reset(state);
190 lgs8gl5_update_reg(state, REG_07, 0x10);
191 lgs8gl5_update_reg(state, REG_07, 0x10);
192 lgs8gl5_write_reg(state, REG_09, 0x0e);
193 lgs8gl5_write_reg(state, REG_0A, 0xe5);
194 lgs8gl5_write_reg(state, REG_0B, 0x35);
195 lgs8gl5_write_reg(state, REG_0C, 0x30);
196
197 lgs8gl5_update_reg(state, REG_03, 0x00);
198 lgs8gl5_update_reg(state, REG_7E, 0x01);
199 lgs8gl5_update_alt_reg(state, 0xc5, 0x00);
200 lgs8gl5_update_reg(state, REG_04, 0x02);
201 lgs8gl5_update_reg(state, REG_37, 0x01);
202 lgs8gl5_soft_reset(state);
203
204
205 for (n = 0; n < 10; n++) {
206 val = lgs8gl5_read_reg(state, REG_STRENGTH);
207 dprintk("Wait for carrier[%d] 0x%02X\n", n, val);
208 if (val & REG_STRENGTH_CARRIER)
209 break;
210 msleep(4);
211 }
212 if (!(val & REG_STRENGTH_CARRIER))
213 return;
214
215
216 for (n = 0; n < 20; n++) {
217 val = lgs8gl5_read_reg(state, REG_STATUS);
218 dprintk("Wait for lock[%d] 0x%02X\n", n, val);
219 if (val & REG_STATUS_LOCK)
220 break;
221 msleep(12);
222 }
223 if (!(val & REG_STATUS_LOCK))
224 return;
225
226 lgs8gl5_write_reg(state, REG_7D, lgs8gl5_read_reg(state, REG_A2));
227 lgs8gl5_soft_reset(state);
228}
229
230
231static int
232lgs8gl5_init(struct dvb_frontend *fe)
233{
234 struct lgs8gl5_state *state = fe->demodulator_priv;
235
236 dprintk("%s\n", __func__);
237
238 lgs8gl5_update_alt_reg(state, 0xc2, 0x28);
239 lgs8gl5_soft_reset(state);
240 lgs8gl5_update_reg(state, REG_07, 0x10);
241 lgs8gl5_update_reg(state, REG_07, 0x10);
242 lgs8gl5_write_reg(state, REG_09, 0x0e);
243 lgs8gl5_write_reg(state, REG_0A, 0xe5);
244 lgs8gl5_write_reg(state, REG_0B, 0x35);
245 lgs8gl5_write_reg(state, REG_0C, 0x30);
246
247 return 0;
248}
249
250
251static int
252lgs8gl5_read_status(struct dvb_frontend *fe, enum fe_status *status)
253{
254 struct lgs8gl5_state *state = fe->demodulator_priv;
255 u8 level = lgs8gl5_read_reg(state, REG_STRENGTH);
256 u8 flags = lgs8gl5_read_reg(state, REG_STATUS);
257
258 *status = 0;
259
260 if ((level & REG_STRENGTH_MASK) > 0)
261 *status |= FE_HAS_SIGNAL;
262 if (level & REG_STRENGTH_CARRIER)
263 *status |= FE_HAS_CARRIER;
264 if (flags & REG_STATUS_SYNC)
265 *status |= FE_HAS_SYNC;
266 if (flags & REG_STATUS_LOCK)
267 *status |= FE_HAS_LOCK;
268
269 return 0;
270}
271
272
273static int
274lgs8gl5_read_ber(struct dvb_frontend *fe, u32 *ber)
275{
276 *ber = 0;
277
278 return 0;
279}
280
281
282static int
283lgs8gl5_read_signal_strength(struct dvb_frontend *fe, u16 *signal_strength)
284{
285 struct lgs8gl5_state *state = fe->demodulator_priv;
286 u8 level = lgs8gl5_read_reg(state, REG_STRENGTH);
287 *signal_strength = (level & REG_STRENGTH_MASK) << 8;
288
289 return 0;
290}
291
292
293static int
294lgs8gl5_read_snr(struct dvb_frontend *fe, u16 *snr)
295{
296 struct lgs8gl5_state *state = fe->demodulator_priv;
297 u8 level = lgs8gl5_read_reg(state, REG_STRENGTH);
298 *snr = (level & REG_STRENGTH_MASK) << 8;
299
300 return 0;
301}
302
303
304static int
305lgs8gl5_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
306{
307 *ucblocks = 0;
308
309 return 0;
310}
311
312
313static int
314lgs8gl5_set_frontend(struct dvb_frontend *fe)
315{
316 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
317 struct lgs8gl5_state *state = fe->demodulator_priv;
318
319 dprintk("%s\n", __func__);
320
321 if (p->bandwidth_hz != 8000000)
322 return -EINVAL;
323
324 if (fe->ops.tuner_ops.set_params) {
325 fe->ops.tuner_ops.set_params(fe);
326 if (fe->ops.i2c_gate_ctrl)
327 fe->ops.i2c_gate_ctrl(fe, 0);
328 }
329
330
331
332 lgs8gl5_start_demod(state);
333
334 return 0;
335}
336
337
338static int
339lgs8gl5_get_frontend(struct dvb_frontend *fe,
340 struct dtv_frontend_properties *p)
341{
342 struct lgs8gl5_state *state = fe->demodulator_priv;
343
344 u8 inv = lgs8gl5_read_reg(state, REG_INVERSION);
345
346 p->inversion = (inv & REG_INVERSION_ON) ? INVERSION_ON : INVERSION_OFF;
347
348 p->code_rate_HP = FEC_1_2;
349 p->code_rate_LP = FEC_7_8;
350 p->guard_interval = GUARD_INTERVAL_1_32;
351 p->transmission_mode = TRANSMISSION_MODE_2K;
352 p->modulation = QAM_64;
353 p->hierarchy = HIERARCHY_NONE;
354 p->bandwidth_hz = 8000000;
355
356 return 0;
357}
358
359
360static int
361lgs8gl5_get_tune_settings(struct dvb_frontend *fe,
362 struct dvb_frontend_tune_settings *fesettings)
363{
364 fesettings->min_delay_ms = 240;
365 fesettings->step_size = 0;
366 fesettings->max_drift = 0;
367 return 0;
368}
369
370
371static void
372lgs8gl5_release(struct dvb_frontend *fe)
373{
374 struct lgs8gl5_state *state = fe->demodulator_priv;
375 kfree(state);
376}
377
378
379static struct dvb_frontend_ops lgs8gl5_ops;
380
381
382struct dvb_frontend*
383lgs8gl5_attach(const struct lgs8gl5_config *config, struct i2c_adapter *i2c)
384{
385 struct lgs8gl5_state *state = NULL;
386
387 dprintk("%s\n", __func__);
388
389
390 state = kzalloc(sizeof(struct lgs8gl5_state), GFP_KERNEL);
391 if (state == NULL)
392 goto error;
393
394
395 state->config = config;
396 state->i2c = i2c;
397
398
399 if (lgs8gl5_read_reg(state, REG_RESET) < 0)
400 goto error;
401
402
403 memcpy(&state->frontend.ops, &lgs8gl5_ops,
404 sizeof(struct dvb_frontend_ops));
405 state->frontend.demodulator_priv = state;
406 return &state->frontend;
407
408error:
409 kfree(state);
410 return NULL;
411}
412EXPORT_SYMBOL(lgs8gl5_attach);
413
414
415static struct dvb_frontend_ops lgs8gl5_ops = {
416 .delsys = { SYS_DTMB },
417 .info = {
418 .name = "Legend Silicon LGS-8GL5 DMB-TH",
419 .frequency_min = 474000000,
420 .frequency_max = 858000000,
421 .frequency_stepsize = 10000,
422 .frequency_tolerance = 0,
423 .caps = FE_CAN_FEC_AUTO |
424 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_32 |
425 FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
426 FE_CAN_TRANSMISSION_MODE_AUTO |
427 FE_CAN_BANDWIDTH_AUTO |
428 FE_CAN_GUARD_INTERVAL_AUTO |
429 FE_CAN_HIERARCHY_AUTO |
430 FE_CAN_RECOVER
431 },
432
433 .release = lgs8gl5_release,
434
435 .init = lgs8gl5_init,
436
437 .set_frontend = lgs8gl5_set_frontend,
438 .get_frontend = lgs8gl5_get_frontend,
439 .get_tune_settings = lgs8gl5_get_tune_settings,
440
441 .read_status = lgs8gl5_read_status,
442 .read_ber = lgs8gl5_read_ber,
443 .read_signal_strength = lgs8gl5_read_signal_strength,
444 .read_snr = lgs8gl5_read_snr,
445 .read_ucblocks = lgs8gl5_read_ucblocks,
446};
447
448
449module_param(debug, int, 0644);
450MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
451
452MODULE_DESCRIPTION("Legend Silicon LGS-8GL5 DMB-TH Demodulator driver");
453MODULE_AUTHOR("Timothy Lee");
454MODULE_LICENSE("GPL");
455
