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11#include <linux/delay.h>
12#include <linux/i2c.h>
13#include <linux/slab.h>
14#include <linux/v4l2-mediabus.h>
15#include <linux/videodev2.h>
16#include <linux/module.h>
17
18#include <media/i2c/rj54n1cb0c.h>
19#include <media/soc_camera.h>
20#include <media/v4l2-clk.h>
21#include <media/v4l2-subdev.h>
22#include <media/v4l2-ctrls.h>
23
24#define RJ54N1_DEV_CODE 0x0400
25#define RJ54N1_DEV_CODE2 0x0401
26#define RJ54N1_OUT_SEL 0x0403
27#define RJ54N1_XY_OUTPUT_SIZE_S_H 0x0404
28#define RJ54N1_X_OUTPUT_SIZE_S_L 0x0405
29#define RJ54N1_Y_OUTPUT_SIZE_S_L 0x0406
30#define RJ54N1_XY_OUTPUT_SIZE_P_H 0x0407
31#define RJ54N1_X_OUTPUT_SIZE_P_L 0x0408
32#define RJ54N1_Y_OUTPUT_SIZE_P_L 0x0409
33#define RJ54N1_LINE_LENGTH_PCK_S_H 0x040a
34#define RJ54N1_LINE_LENGTH_PCK_S_L 0x040b
35#define RJ54N1_LINE_LENGTH_PCK_P_H 0x040c
36#define RJ54N1_LINE_LENGTH_PCK_P_L 0x040d
37#define RJ54N1_RESIZE_N 0x040e
38#define RJ54N1_RESIZE_N_STEP 0x040f
39#define RJ54N1_RESIZE_STEP 0x0410
40#define RJ54N1_RESIZE_HOLD_H 0x0411
41#define RJ54N1_RESIZE_HOLD_L 0x0412
42#define RJ54N1_H_OBEN_OFS 0x0413
43#define RJ54N1_V_OBEN_OFS 0x0414
44#define RJ54N1_RESIZE_CONTROL 0x0415
45#define RJ54N1_STILL_CONTROL 0x0417
46#define RJ54N1_INC_USE_SEL_H 0x0425
47#define RJ54N1_INC_USE_SEL_L 0x0426
48#define RJ54N1_MIRROR_STILL_MODE 0x0427
49#define RJ54N1_INIT_START 0x0428
50#define RJ54N1_SCALE_1_2_LEV 0x0429
51#define RJ54N1_SCALE_4_LEV 0x042a
52#define RJ54N1_Y_GAIN 0x04d8
53#define RJ54N1_APT_GAIN_UP 0x04fa
54#define RJ54N1_RA_SEL_UL 0x0530
55#define RJ54N1_BYTE_SWAP 0x0531
56#define RJ54N1_OUT_SIGPO 0x053b
57#define RJ54N1_WB_SEL_WEIGHT_I 0x054e
58#define RJ54N1_BIT8_WB 0x0569
59#define RJ54N1_HCAPS_WB 0x056a
60#define RJ54N1_VCAPS_WB 0x056b
61#define RJ54N1_HCAPE_WB 0x056c
62#define RJ54N1_VCAPE_WB 0x056d
63#define RJ54N1_EXPOSURE_CONTROL 0x058c
64#define RJ54N1_FRAME_LENGTH_S_H 0x0595
65#define RJ54N1_FRAME_LENGTH_S_L 0x0596
66#define RJ54N1_FRAME_LENGTH_P_H 0x0597
67#define RJ54N1_FRAME_LENGTH_P_L 0x0598
68#define RJ54N1_PEAK_H 0x05b7
69#define RJ54N1_PEAK_50 0x05b8
70#define RJ54N1_PEAK_60 0x05b9
71#define RJ54N1_PEAK_DIFF 0x05ba
72#define RJ54N1_IOC 0x05ef
73#define RJ54N1_TG_BYPASS 0x0700
74#define RJ54N1_PLL_L 0x0701
75#define RJ54N1_PLL_N 0x0702
76#define RJ54N1_PLL_EN 0x0704
77#define RJ54N1_RATIO_TG 0x0706
78#define RJ54N1_RATIO_T 0x0707
79#define RJ54N1_RATIO_R 0x0708
80#define RJ54N1_RAMP_TGCLK_EN 0x0709
81#define RJ54N1_OCLK_DSP 0x0710
82#define RJ54N1_RATIO_OP 0x0711
83#define RJ54N1_RATIO_O 0x0712
84#define RJ54N1_OCLK_SEL_EN 0x0713
85#define RJ54N1_CLK_RST 0x0717
86#define RJ54N1_RESET_STANDBY 0x0718
87#define RJ54N1_FWFLG 0x07fe
88
89#define E_EXCLK (1 << 7)
90#define SOFT_STDBY (1 << 4)
91#define SEN_RSTX (1 << 2)
92#define TG_RSTX (1 << 1)
93#define DSP_RSTX (1 << 0)
94
95#define RESIZE_HOLD_SEL (1 << 2)
96#define RESIZE_GO (1 << 1)
97
98
99
100
101
102#define RJ54N1_COLUMN_SKIP 0
103#define RJ54N1_ROW_SKIP 0
104#define RJ54N1_MAX_WIDTH 1600
105#define RJ54N1_MAX_HEIGHT 1200
106
107#define PLL_L 2
108#define PLL_N 0x31
109
110
111
112
113struct rj54n1_datafmt {
114 u32 code;
115 enum v4l2_colorspace colorspace;
116};
117
118
119static const struct rj54n1_datafmt *rj54n1_find_datafmt(
120 u32 code, const struct rj54n1_datafmt *fmt,
121 int n)
122{
123 int i;
124 for (i = 0; i < n; i++)
125 if (fmt[i].code == code)
126 return fmt + i;
127
128 return NULL;
129}
130
131static const struct rj54n1_datafmt rj54n1_colour_fmts[] = {
132 {MEDIA_BUS_FMT_YUYV8_2X8, V4L2_COLORSPACE_JPEG},
133 {MEDIA_BUS_FMT_YVYU8_2X8, V4L2_COLORSPACE_JPEG},
134 {MEDIA_BUS_FMT_RGB565_2X8_LE, V4L2_COLORSPACE_SRGB},
135 {MEDIA_BUS_FMT_RGB565_2X8_BE, V4L2_COLORSPACE_SRGB},
136 {MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE, V4L2_COLORSPACE_SRGB},
137 {MEDIA_BUS_FMT_SBGGR10_2X8_PADLO_LE, V4L2_COLORSPACE_SRGB},
138 {MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_BE, V4L2_COLORSPACE_SRGB},
139 {MEDIA_BUS_FMT_SBGGR10_2X8_PADLO_BE, V4L2_COLORSPACE_SRGB},
140 {MEDIA_BUS_FMT_SBGGR10_1X10, V4L2_COLORSPACE_SRGB},
141};
142
143struct rj54n1_clock_div {
144 u8 ratio_tg;
145 u8 ratio_t;
146 u8 ratio_r;
147 u8 ratio_op;
148 u8 ratio_o;
149};
150
151struct rj54n1 {
152 struct v4l2_subdev subdev;
153 struct v4l2_ctrl_handler hdl;
154 struct v4l2_clk *clk;
155 struct rj54n1_clock_div clk_div;
156 const struct rj54n1_datafmt *fmt;
157 struct v4l2_rect rect;
158 unsigned int tgclk_mhz;
159 bool auto_wb;
160 unsigned short width;
161 unsigned short height;
162 unsigned short resize;
163 unsigned short scale;
164 u8 bank;
165};
166
167struct rj54n1_reg_val {
168 u16 reg;
169 u8 val;
170};
171
172static const struct rj54n1_reg_val bank_4[] = {
173 {0x417, 0},
174 {0x42c, 0},
175 {0x42d, 0xf0},
176 {0x42e, 0},
177 {0x42f, 0x50},
178 {0x430, 0xf5},
179 {0x431, 0x16},
180 {0x432, 0x20},
181 {0x433, 0},
182 {0x434, 0xc8},
183 {0x43c, 8},
184 {0x43e, 0x90},
185 {0x445, 0x83},
186 {0x4ba, 0x58},
187 {0x4bb, 4},
188 {0x4bc, 0x20},
189 {0x4db, 4},
190 {0x4fe, 2},
191};
192
193static const struct rj54n1_reg_val bank_5[] = {
194 {0x514, 0},
195 {0x516, 0},
196 {0x518, 0},
197 {0x51a, 0},
198 {0x51d, 0xff},
199 {0x56f, 0x28},
200 {0x575, 0x40},
201 {0x5bc, 0x48},
202 {0x5c1, 6},
203 {0x5e5, 0x11},
204 {0x5e6, 0x43},
205 {0x5e7, 0x33},
206 {0x5e8, 0x21},
207 {0x5e9, 0x30},
208 {0x5ea, 0x0},
209 {0x5eb, 0xa5},
210 {0x5ec, 0xff},
211 {0x5fe, 2},
212};
213
214static const struct rj54n1_reg_val bank_7[] = {
215 {0x70a, 0},
216 {0x714, 0xff},
217 {0x715, 0xff},
218 {0x716, 0x1f},
219 {0x7FE, 2},
220};
221
222static const struct rj54n1_reg_val bank_8[] = {
223 {0x800, 0x00},
224 {0x801, 0x01},
225 {0x802, 0x61},
226 {0x805, 0x00},
227 {0x806, 0x00},
228 {0x807, 0x00},
229 {0x808, 0x00},
230 {0x809, 0x01},
231 {0x80A, 0x61},
232 {0x80B, 0x00},
233 {0x80C, 0x01},
234 {0x80D, 0x00},
235 {0x80E, 0x00},
236 {0x80F, 0x00},
237 {0x810, 0x00},
238 {0x811, 0x01},
239 {0x812, 0x61},
240 {0x813, 0x00},
241 {0x814, 0x11},
242 {0x815, 0x00},
243 {0x816, 0x41},
244 {0x817, 0x00},
245 {0x818, 0x51},
246 {0x819, 0x01},
247 {0x81A, 0x1F},
248 {0x81B, 0x00},
249 {0x81C, 0x01},
250 {0x81D, 0x00},
251 {0x81E, 0x11},
252 {0x81F, 0x00},
253 {0x820, 0x41},
254 {0x821, 0x00},
255 {0x822, 0x51},
256 {0x823, 0x00},
257 {0x824, 0x00},
258 {0x825, 0x00},
259 {0x826, 0x47},
260 {0x827, 0x01},
261 {0x828, 0x4F},
262 {0x829, 0x00},
263 {0x82A, 0x00},
264 {0x82B, 0x00},
265 {0x82C, 0x30},
266 {0x82D, 0x00},
267 {0x82E, 0x40},
268 {0x82F, 0x00},
269 {0x830, 0xB3},
270 {0x831, 0x00},
271 {0x832, 0xE3},
272 {0x833, 0x00},
273 {0x834, 0x00},
274 {0x835, 0x00},
275 {0x836, 0x00},
276 {0x837, 0x00},
277 {0x838, 0x00},
278 {0x839, 0x01},
279 {0x83A, 0x61},
280 {0x83B, 0x00},
281 {0x83C, 0x01},
282 {0x83D, 0x00},
283 {0x83E, 0x00},
284 {0x83F, 0x00},
285 {0x840, 0x00},
286 {0x841, 0x01},
287 {0x842, 0x61},
288 {0x843, 0x00},
289 {0x844, 0x1D},
290 {0x845, 0x00},
291 {0x846, 0x00},
292 {0x847, 0x00},
293 {0x848, 0x00},
294 {0x849, 0x01},
295 {0x84A, 0x1F},
296 {0x84B, 0x00},
297 {0x84C, 0x05},
298 {0x84D, 0x00},
299 {0x84E, 0x19},
300 {0x84F, 0x01},
301 {0x850, 0x21},
302 {0x851, 0x01},
303 {0x852, 0x5D},
304 {0x853, 0x00},
305 {0x854, 0x00},
306 {0x855, 0x00},
307 {0x856, 0x19},
308 {0x857, 0x01},
309 {0x858, 0x21},
310 {0x859, 0x00},
311 {0x85A, 0x00},
312 {0x85B, 0x00},
313 {0x85C, 0x00},
314 {0x85D, 0x00},
315 {0x85E, 0x00},
316 {0x85F, 0x00},
317 {0x860, 0xB3},
318 {0x861, 0x00},
319 {0x862, 0xE3},
320 {0x863, 0x00},
321 {0x864, 0x00},
322 {0x865, 0x00},
323 {0x866, 0x00},
324 {0x867, 0x00},
325 {0x868, 0x00},
326 {0x869, 0xE2},
327 {0x86A, 0x00},
328 {0x86B, 0x01},
329 {0x86C, 0x06},
330 {0x86D, 0x00},
331 {0x86E, 0x00},
332 {0x86F, 0x00},
333 {0x870, 0x60},
334 {0x871, 0x8C},
335 {0x872, 0x10},
336 {0x873, 0x00},
337 {0x874, 0xE0},
338 {0x875, 0x00},
339 {0x876, 0x27},
340 {0x877, 0x01},
341 {0x878, 0x00},
342 {0x879, 0x00},
343 {0x87A, 0x00},
344 {0x87B, 0x03},
345 {0x87C, 0x00},
346 {0x87D, 0x00},
347 {0x87E, 0x00},
348 {0x87F, 0x00},
349 {0x880, 0x00},
350 {0x881, 0x00},
351 {0x882, 0x00},
352 {0x883, 0x00},
353 {0x884, 0x00},
354 {0x885, 0x00},
355 {0x886, 0xF8},
356 {0x887, 0x00},
357 {0x888, 0x03},
358 {0x889, 0x00},
359 {0x88A, 0x64},
360 {0x88B, 0x00},
361 {0x88C, 0x03},
362 {0x88D, 0x00},
363 {0x88E, 0xB1},
364 {0x88F, 0x00},
365 {0x890, 0x03},
366 {0x891, 0x01},
367 {0x892, 0x1D},
368 {0x893, 0x00},
369 {0x894, 0x03},
370 {0x895, 0x01},
371 {0x896, 0x4B},
372 {0x897, 0x00},
373 {0x898, 0xE5},
374 {0x899, 0x00},
375 {0x89A, 0x01},
376 {0x89B, 0x00},
377 {0x89C, 0x01},
378 {0x89D, 0x04},
379 {0x89E, 0xC8},
380 {0x89F, 0x00},
381 {0x8A0, 0x01},
382 {0x8A1, 0x01},
383 {0x8A2, 0x61},
384 {0x8A3, 0x00},
385 {0x8A4, 0x01},
386 {0x8A5, 0x00},
387 {0x8A6, 0x00},
388 {0x8A7, 0x00},
389 {0x8A8, 0x00},
390 {0x8A9, 0x00},
391 {0x8AA, 0x7F},
392 {0x8AB, 0x03},
393 {0x8AC, 0x00},
394 {0x8AD, 0x00},
395 {0x8AE, 0x00},
396 {0x8AF, 0x00},
397 {0x8B0, 0x00},
398 {0x8B1, 0x00},
399 {0x8B6, 0x00},
400 {0x8B7, 0x01},
401 {0x8B8, 0x00},
402 {0x8B9, 0x00},
403 {0x8BA, 0x02},
404 {0x8BB, 0x00},
405 {0x8BC, 0xFF},
406 {0x8BD, 0x00},
407 {0x8FE, 2},
408};
409
410static const struct rj54n1_reg_val bank_10[] = {
411 {0x10bf, 0x69}
412};
413
414
415static const struct rj54n1_clock_div clk_div = {
416 .ratio_tg = 3 ,
417 .ratio_t = 4 ,
418 .ratio_r = 4 ,
419 .ratio_op = 1 ,
420 .ratio_o = 9 ,
421};
422
423static struct rj54n1 *to_rj54n1(const struct i2c_client *client)
424{
425 return container_of(i2c_get_clientdata(client), struct rj54n1, subdev);
426}
427
428static int reg_read(struct i2c_client *client, const u16 reg)
429{
430 struct rj54n1 *rj54n1 = to_rj54n1(client);
431 int ret;
432
433
434 if (rj54n1->bank != reg >> 8) {
435 dev_dbg(&client->dev, "[0x%x] = 0x%x\n", 0xff, reg >> 8);
436 ret = i2c_smbus_write_byte_data(client, 0xff, reg >> 8);
437 if (ret < 0)
438 return ret;
439 rj54n1->bank = reg >> 8;
440 }
441 return i2c_smbus_read_byte_data(client, reg & 0xff);
442}
443
444static int reg_write(struct i2c_client *client, const u16 reg,
445 const u8 data)
446{
447 struct rj54n1 *rj54n1 = to_rj54n1(client);
448 int ret;
449
450
451 if (rj54n1->bank != reg >> 8) {
452 dev_dbg(&client->dev, "[0x%x] = 0x%x\n", 0xff, reg >> 8);
453 ret = i2c_smbus_write_byte_data(client, 0xff, reg >> 8);
454 if (ret < 0)
455 return ret;
456 rj54n1->bank = reg >> 8;
457 }
458 dev_dbg(&client->dev, "[0x%x] = 0x%x\n", reg & 0xff, data);
459 return i2c_smbus_write_byte_data(client, reg & 0xff, data);
460}
461
462static int reg_set(struct i2c_client *client, const u16 reg,
463 const u8 data, const u8 mask)
464{
465 int ret;
466
467 ret = reg_read(client, reg);
468 if (ret < 0)
469 return ret;
470 return reg_write(client, reg, (ret & ~mask) | (data & mask));
471}
472
473static int reg_write_multiple(struct i2c_client *client,
474 const struct rj54n1_reg_val *rv, const int n)
475{
476 int i, ret;
477
478 for (i = 0; i < n; i++) {
479 ret = reg_write(client, rv->reg, rv->val);
480 if (ret < 0)
481 return ret;
482 rv++;
483 }
484
485 return 0;
486}
487
488static int rj54n1_enum_mbus_code(struct v4l2_subdev *sd,
489 struct v4l2_subdev_pad_config *cfg,
490 struct v4l2_subdev_mbus_code_enum *code)
491{
492 if (code->pad || code->index >= ARRAY_SIZE(rj54n1_colour_fmts))
493 return -EINVAL;
494
495 code->code = rj54n1_colour_fmts[code->index].code;
496 return 0;
497}
498
499static int rj54n1_s_stream(struct v4l2_subdev *sd, int enable)
500{
501 struct i2c_client *client = v4l2_get_subdevdata(sd);
502
503
504 return reg_set(client, RJ54N1_STILL_CONTROL, (!enable) << 7, 0x80);
505}
506
507static int rj54n1_set_rect(struct i2c_client *client,
508 u16 reg_x, u16 reg_y, u16 reg_xy,
509 u32 width, u32 height)
510{
511 int ret;
512
513 ret = reg_write(client, reg_xy,
514 ((width >> 4) & 0x70) |
515 ((height >> 8) & 7));
516
517 if (!ret)
518 ret = reg_write(client, reg_x, width & 0xff);
519 if (!ret)
520 ret = reg_write(client, reg_y, height & 0xff);
521
522 return ret;
523}
524
525
526
527
528
529static int rj54n1_commit(struct i2c_client *client)
530{
531 int ret = reg_write(client, RJ54N1_INIT_START, 1);
532 msleep(10);
533 if (!ret)
534 ret = reg_write(client, RJ54N1_INIT_START, 0);
535 return ret;
536}
537
538static int rj54n1_sensor_scale(struct v4l2_subdev *sd, s32 *in_w, s32 *in_h,
539 s32 *out_w, s32 *out_h);
540
541static int rj54n1_set_selection(struct v4l2_subdev *sd,
542 struct v4l2_subdev_pad_config *cfg,
543 struct v4l2_subdev_selection *sel)
544{
545 struct i2c_client *client = v4l2_get_subdevdata(sd);
546 struct rj54n1 *rj54n1 = to_rj54n1(client);
547 const struct v4l2_rect *rect = &sel->r;
548 int dummy = 0, output_w, output_h,
549 input_w = rect->width, input_h = rect->height;
550 int ret;
551
552 if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE ||
553 sel->target != V4L2_SEL_TGT_CROP)
554 return -EINVAL;
555
556
557 soc_camera_limit_side(&dummy, &input_w,
558 RJ54N1_COLUMN_SKIP, 8, RJ54N1_MAX_WIDTH);
559
560 soc_camera_limit_side(&dummy, &input_h,
561 RJ54N1_ROW_SKIP, 8, RJ54N1_MAX_HEIGHT);
562
563 output_w = (input_w * 1024 + rj54n1->resize / 2) / rj54n1->resize;
564 output_h = (input_h * 1024 + rj54n1->resize / 2) / rj54n1->resize;
565
566 dev_dbg(&client->dev, "Scaling for %dx%d : %u = %dx%d\n",
567 input_w, input_h, rj54n1->resize, output_w, output_h);
568
569 ret = rj54n1_sensor_scale(sd, &input_w, &input_h, &output_w, &output_h);
570 if (ret < 0)
571 return ret;
572
573 rj54n1->width = output_w;
574 rj54n1->height = output_h;
575 rj54n1->resize = ret;
576 rj54n1->rect.width = input_w;
577 rj54n1->rect.height = input_h;
578
579 return 0;
580}
581
582static int rj54n1_get_selection(struct v4l2_subdev *sd,
583 struct v4l2_subdev_pad_config *cfg,
584 struct v4l2_subdev_selection *sel)
585{
586 struct i2c_client *client = v4l2_get_subdevdata(sd);
587 struct rj54n1 *rj54n1 = to_rj54n1(client);
588
589 if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE)
590 return -EINVAL;
591
592 switch (sel->target) {
593 case V4L2_SEL_TGT_CROP_BOUNDS:
594 case V4L2_SEL_TGT_CROP_DEFAULT:
595 sel->r.left = RJ54N1_COLUMN_SKIP;
596 sel->r.top = RJ54N1_ROW_SKIP;
597 sel->r.width = RJ54N1_MAX_WIDTH;
598 sel->r.height = RJ54N1_MAX_HEIGHT;
599 return 0;
600 case V4L2_SEL_TGT_CROP:
601 sel->r = rj54n1->rect;
602 return 0;
603 default:
604 return -EINVAL;
605 }
606}
607
608static int rj54n1_get_fmt(struct v4l2_subdev *sd,
609 struct v4l2_subdev_pad_config *cfg,
610 struct v4l2_subdev_format *format)
611{
612 struct v4l2_mbus_framefmt *mf = &format->format;
613 struct i2c_client *client = v4l2_get_subdevdata(sd);
614 struct rj54n1 *rj54n1 = to_rj54n1(client);
615
616 if (format->pad)
617 return -EINVAL;
618
619 mf->code = rj54n1->fmt->code;
620 mf->colorspace = rj54n1->fmt->colorspace;
621 mf->field = V4L2_FIELD_NONE;
622 mf->width = rj54n1->width;
623 mf->height = rj54n1->height;
624
625 return 0;
626}
627
628
629
630
631
632
633static int rj54n1_sensor_scale(struct v4l2_subdev *sd, s32 *in_w, s32 *in_h,
634 s32 *out_w, s32 *out_h)
635{
636 struct i2c_client *client = v4l2_get_subdevdata(sd);
637 struct rj54n1 *rj54n1 = to_rj54n1(client);
638 unsigned int skip, resize, input_w = *in_w, input_h = *in_h,
639 output_w = *out_w, output_h = *out_h;
640 u16 inc_sel, wb_bit8, wb_left, wb_right, wb_top, wb_bottom;
641 unsigned int peak, peak_50, peak_60;
642 int ret;
643
644
645
646
647
648
649
650 if (output_w > max(512U, input_w / 2)) {
651 if (2 * output_w > RJ54N1_MAX_WIDTH) {
652 input_w = RJ54N1_MAX_WIDTH;
653 output_w = RJ54N1_MAX_WIDTH / 2;
654 } else {
655 input_w = output_w * 2;
656 }
657
658 dev_dbg(&client->dev, "Adjusted output width: in %u, out %u\n",
659 input_w, output_w);
660 }
661
662 if (output_h > max(384U, input_h / 2)) {
663 if (2 * output_h > RJ54N1_MAX_HEIGHT) {
664 input_h = RJ54N1_MAX_HEIGHT;
665 output_h = RJ54N1_MAX_HEIGHT / 2;
666 } else {
667 input_h = output_h * 2;
668 }
669
670 dev_dbg(&client->dev, "Adjusted output height: in %u, out %u\n",
671 input_h, output_h);
672 }
673
674
675 ret = rj54n1_set_rect(client, RJ54N1_X_OUTPUT_SIZE_S_L,
676 RJ54N1_Y_OUTPUT_SIZE_S_L,
677 RJ54N1_XY_OUTPUT_SIZE_S_H, output_w, output_h);
678 if (!ret)
679 ret = rj54n1_set_rect(client, RJ54N1_X_OUTPUT_SIZE_P_L,
680 RJ54N1_Y_OUTPUT_SIZE_P_L,
681 RJ54N1_XY_OUTPUT_SIZE_P_H, output_w, output_h);
682
683 if (ret < 0)
684 return ret;
685
686 if (output_w > input_w && output_h > input_h) {
687 input_w = output_w;
688 input_h = output_h;
689
690 resize = 1024;
691 } else {
692 unsigned int resize_x, resize_y;
693 resize_x = (input_w * 1024 + output_w / 2) / output_w;
694 resize_y = (input_h * 1024 + output_h / 2) / output_h;
695
696
697 if (resize_x > resize_y &&
698 (output_h * resize_x + 512) / 1024 > RJ54N1_MAX_HEIGHT)
699 resize = (RJ54N1_MAX_HEIGHT * 1024 + output_h / 2) /
700 output_h;
701 else if (resize_y > resize_x &&
702 (output_w * resize_y + 512) / 1024 > RJ54N1_MAX_WIDTH)
703 resize = (RJ54N1_MAX_WIDTH * 1024 + output_w / 2) /
704 output_w;
705 else
706 resize = max(resize_x, resize_y);
707
708
709 switch (resize) {
710 case 2040 ... 2047:
711 resize = 2039;
712 break;
713 case 4080 ... 4095:
714 resize = 4079;
715 break;
716 case 8160 ... 8191:
717 resize = 8159;
718 break;
719 case 16320 ... 16384:
720 resize = 16319;
721 }
722 }
723
724
725 ret = reg_write(client, RJ54N1_RESIZE_HOLD_L, resize & 0xff);
726 if (!ret)
727 ret = reg_write(client, RJ54N1_RESIZE_HOLD_H, resize >> 8);
728
729 if (ret < 0)
730 return ret;
731
732
733
734
735
736
737
738
739
740
741
742
743
744 skip = min(resize / 1024, 15U);
745
746 inc_sel = 1 << skip;
747
748 if (inc_sel <= 2)
749 inc_sel = 0xc;
750 else if (resize & 1023 && skip < 15)
751 inc_sel |= 1 << (skip + 1);
752
753 ret = reg_write(client, RJ54N1_INC_USE_SEL_L, inc_sel & 0xfc);
754 if (!ret)
755 ret = reg_write(client, RJ54N1_INC_USE_SEL_H, inc_sel >> 8);
756
757 if (!rj54n1->auto_wb) {
758
759 wb_left = output_w / 16;
760 wb_right = (3 * output_w / 4 - 3) / 4;
761 wb_top = output_h / 16;
762 wb_bottom = (3 * output_h / 4 - 3) / 4;
763 wb_bit8 = ((wb_left >> 2) & 0x40) | ((wb_top >> 4) & 0x10) |
764 ((wb_right >> 6) & 4) | ((wb_bottom >> 8) & 1);
765
766 if (!ret)
767 ret = reg_write(client, RJ54N1_BIT8_WB, wb_bit8);
768 if (!ret)
769 ret = reg_write(client, RJ54N1_HCAPS_WB, wb_left);
770 if (!ret)
771 ret = reg_write(client, RJ54N1_VCAPS_WB, wb_top);
772 if (!ret)
773 ret = reg_write(client, RJ54N1_HCAPE_WB, wb_right);
774 if (!ret)
775 ret = reg_write(client, RJ54N1_VCAPE_WB, wb_bottom);
776 }
777
778
779 peak = 12 * RJ54N1_MAX_WIDTH * (1 << 14) * resize / rj54n1->tgclk_mhz /
780 10000;
781 peak_50 = peak / 6;
782 peak_60 = peak / 5;
783
784 if (!ret)
785 ret = reg_write(client, RJ54N1_PEAK_H,
786 ((peak_50 >> 4) & 0xf0) | (peak_60 >> 8));
787 if (!ret)
788 ret = reg_write(client, RJ54N1_PEAK_50, peak_50);
789 if (!ret)
790 ret = reg_write(client, RJ54N1_PEAK_60, peak_60);
791 if (!ret)
792 ret = reg_write(client, RJ54N1_PEAK_DIFF, peak / 150);
793
794
795 if (!ret)
796 ret = reg_write(client, RJ54N1_RESIZE_CONTROL,
797 RESIZE_HOLD_SEL | RESIZE_GO | 1);
798
799 if (ret < 0)
800 return ret;
801
802
803 msleep(230);
804
805 ret = reg_write(client, RJ54N1_RESIZE_CONTROL, RESIZE_HOLD_SEL | 1);
806 if (ret < 0)
807 return ret;
808
809 *in_w = (output_w * resize + 512) / 1024;
810 *in_h = (output_h * resize + 512) / 1024;
811 *out_w = output_w;
812 *out_h = output_h;
813
814 dev_dbg(&client->dev, "Scaled for %dx%d : %u = %ux%u, skip %u\n",
815 *in_w, *in_h, resize, output_w, output_h, skip);
816
817 return resize;
818}
819
820static int rj54n1_set_clock(struct i2c_client *client)
821{
822 struct rj54n1 *rj54n1 = to_rj54n1(client);
823 int ret;
824
825
826 ret = reg_write(client, RJ54N1_RESET_STANDBY, E_EXCLK | SOFT_STDBY);
827
828 if (!ret)
829 ret = reg_write(client, RJ54N1_RESET_STANDBY, E_EXCLK);
830
831 if (!ret)
832 ret = reg_write(client, RJ54N1_PLL_L, PLL_L);
833 if (!ret)
834 ret = reg_write(client, RJ54N1_PLL_N, PLL_N);
835
836
837 if (!ret)
838 ret = reg_write(client, RJ54N1_RATIO_TG,
839 rj54n1->clk_div.ratio_tg);
840 if (!ret)
841 ret = reg_write(client, RJ54N1_RATIO_T,
842 rj54n1->clk_div.ratio_t);
843 if (!ret)
844 ret = reg_write(client, RJ54N1_RATIO_R,
845 rj54n1->clk_div.ratio_r);
846
847
848 if (!ret)
849 ret = reg_write(client, RJ54N1_RAMP_TGCLK_EN, 3);
850
851
852 if (!ret)
853 ret = reg_write(client, RJ54N1_OCLK_DSP, 0);
854
855
856 if (!ret)
857 ret = reg_write(client, RJ54N1_RATIO_OP,
858 rj54n1->clk_div.ratio_op);
859 if (!ret)
860 ret = reg_write(client, RJ54N1_RATIO_O,
861 rj54n1->clk_div.ratio_o);
862
863
864 if (!ret)
865 ret = reg_write(client, RJ54N1_OCLK_SEL_EN, 1);
866
867
868 if (!ret)
869 ret = reg_write(client, RJ54N1_TG_BYPASS, 2);
870
871
872 if (!ret)
873 ret = reg_write(client, RJ54N1_RESET_STANDBY,
874 E_EXCLK | SEN_RSTX);
875
876 if (!ret)
877 ret = reg_write(client, RJ54N1_PLL_EN, 1);
878
879
880 msleep(10);
881
882
883 if (!ret)
884 ret = reg_write(client, RJ54N1_CLK_RST, 1);
885
886 if (!ret)
887 ret = reg_read(client, RJ54N1_CLK_RST);
888 if (ret != 1) {
889 dev_err(&client->dev,
890 "Resetting RJ54N1CB0C clock failed: %d!\n", ret);
891 return -EIO;
892 }
893
894
895 ret = reg_set(client, RJ54N1_OCLK_DSP, 1, 1);
896
897
898 if (!ret)
899 ret = reg_write(client, RJ54N1_OCLK_SEL_EN, 1);
900
901 return ret;
902}
903
904static int rj54n1_reg_init(struct i2c_client *client)
905{
906 struct rj54n1 *rj54n1 = to_rj54n1(client);
907 int ret = rj54n1_set_clock(client);
908
909 if (!ret)
910 ret = reg_write_multiple(client, bank_7, ARRAY_SIZE(bank_7));
911 if (!ret)
912 ret = reg_write_multiple(client, bank_10, ARRAY_SIZE(bank_10));
913
914
915 if (!ret)
916 ret = reg_write(client, RJ54N1_SCALE_1_2_LEV, 3 | (7 << 4));
917 if (!ret)
918 ret = reg_write(client, RJ54N1_SCALE_4_LEV, 0xf);
919
920
921 if (!ret)
922 ret = reg_write(client, RJ54N1_RESIZE_CONTROL,
923 RESIZE_HOLD_SEL | 1);
924
925
926 if (!ret)
927 ret = reg_write(client, RJ54N1_Y_GAIN, 0x84);
928
929
930
931
932
933 if (!ret)
934 ret = reg_write(client, RJ54N1_MIRROR_STILL_MODE, 0x27);
935
936 if (!ret)
937 ret = reg_write_multiple(client, bank_4, ARRAY_SIZE(bank_4));
938
939
940 if (!ret)
941 ret = reg_write(client, RJ54N1_EXPOSURE_CONTROL, 0x80);
942
943 if (!ret)
944 ret = reg_read(client, RJ54N1_WB_SEL_WEIGHT_I);
945 if (ret >= 0) {
946 rj54n1->auto_wb = ret & 0x80;
947 ret = reg_write_multiple(client, bank_5, ARRAY_SIZE(bank_5));
948 }
949 if (!ret)
950 ret = reg_write_multiple(client, bank_8, ARRAY_SIZE(bank_8));
951
952 if (!ret)
953 ret = reg_write(client, RJ54N1_RESET_STANDBY,
954 E_EXCLK | DSP_RSTX | SEN_RSTX);
955
956
957 if (!ret)
958 ret = rj54n1_commit(client);
959
960
961 if (!ret)
962 ret = reg_write(client, RJ54N1_RESET_STANDBY,
963 E_EXCLK | DSP_RSTX | TG_RSTX | SEN_RSTX);
964
965
966 if (!ret)
967 ret = reg_write(client, RJ54N1_FWFLG, 2);
968
969
970 msleep(700);
971
972 return ret;
973}
974
975static int rj54n1_set_fmt(struct v4l2_subdev *sd,
976 struct v4l2_subdev_pad_config *cfg,
977 struct v4l2_subdev_format *format)
978{
979 struct v4l2_mbus_framefmt *mf = &format->format;
980 struct i2c_client *client = v4l2_get_subdevdata(sd);
981 struct rj54n1 *rj54n1 = to_rj54n1(client);
982 const struct rj54n1_datafmt *fmt;
983 int output_w, output_h, max_w, max_h,
984 input_w = rj54n1->rect.width, input_h = rj54n1->rect.height;
985 int align = mf->code == MEDIA_BUS_FMT_SBGGR10_1X10 ||
986 mf->code == MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_BE ||
987 mf->code == MEDIA_BUS_FMT_SBGGR10_2X8_PADLO_BE ||
988 mf->code == MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE ||
989 mf->code == MEDIA_BUS_FMT_SBGGR10_2X8_PADLO_LE;
990 int ret;
991
992 if (format->pad)
993 return -EINVAL;
994
995 dev_dbg(&client->dev, "%s: code = %d, width = %u, height = %u\n",
996 __func__, mf->code, mf->width, mf->height);
997
998 fmt = rj54n1_find_datafmt(mf->code, rj54n1_colour_fmts,
999 ARRAY_SIZE(rj54n1_colour_fmts));
1000 if (!fmt) {
1001 fmt = rj54n1->fmt;
1002 mf->code = fmt->code;
1003 }
1004
1005 mf->field = V4L2_FIELD_NONE;
1006 mf->colorspace = fmt->colorspace;
1007
1008 v4l_bound_align_image(&mf->width, 112, RJ54N1_MAX_WIDTH, align,
1009 &mf->height, 84, RJ54N1_MAX_HEIGHT, align, 0);
1010
1011 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1012 cfg->try_fmt = *mf;
1013 return 0;
1014 }
1015
1016
1017
1018
1019
1020 ret = reg_read(client, RJ54N1_RESET_STANDBY);
1021 if (ret < 0)
1022 return ret;
1023
1024 if (!(ret & E_EXCLK)) {
1025 ret = rj54n1_reg_init(client);
1026 if (ret < 0)
1027 return ret;
1028 }
1029
1030
1031 switch (mf->code) {
1032 case MEDIA_BUS_FMT_YUYV8_2X8:
1033 ret = reg_write(client, RJ54N1_OUT_SEL, 0);
1034 if (!ret)
1035 ret = reg_set(client, RJ54N1_BYTE_SWAP, 8, 8);
1036 break;
1037 case MEDIA_BUS_FMT_YVYU8_2X8:
1038 ret = reg_write(client, RJ54N1_OUT_SEL, 0);
1039 if (!ret)
1040 ret = reg_set(client, RJ54N1_BYTE_SWAP, 0, 8);
1041 break;
1042 case MEDIA_BUS_FMT_RGB565_2X8_LE:
1043 ret = reg_write(client, RJ54N1_OUT_SEL, 0x11);
1044 if (!ret)
1045 ret = reg_set(client, RJ54N1_BYTE_SWAP, 8, 8);
1046 break;
1047 case MEDIA_BUS_FMT_RGB565_2X8_BE:
1048 ret = reg_write(client, RJ54N1_OUT_SEL, 0x11);
1049 if (!ret)
1050 ret = reg_set(client, RJ54N1_BYTE_SWAP, 0, 8);
1051 break;
1052 case MEDIA_BUS_FMT_SBGGR10_2X8_PADLO_LE:
1053 ret = reg_write(client, RJ54N1_OUT_SEL, 4);
1054 if (!ret)
1055 ret = reg_set(client, RJ54N1_BYTE_SWAP, 8, 8);
1056 if (!ret)
1057 ret = reg_write(client, RJ54N1_RA_SEL_UL, 0);
1058 break;
1059 case MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE:
1060 ret = reg_write(client, RJ54N1_OUT_SEL, 4);
1061 if (!ret)
1062 ret = reg_set(client, RJ54N1_BYTE_SWAP, 8, 8);
1063 if (!ret)
1064 ret = reg_write(client, RJ54N1_RA_SEL_UL, 8);
1065 break;
1066 case MEDIA_BUS_FMT_SBGGR10_2X8_PADLO_BE:
1067 ret = reg_write(client, RJ54N1_OUT_SEL, 4);
1068 if (!ret)
1069 ret = reg_set(client, RJ54N1_BYTE_SWAP, 0, 8);
1070 if (!ret)
1071 ret = reg_write(client, RJ54N1_RA_SEL_UL, 0);
1072 break;
1073 case MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_BE:
1074 ret = reg_write(client, RJ54N1_OUT_SEL, 4);
1075 if (!ret)
1076 ret = reg_set(client, RJ54N1_BYTE_SWAP, 0, 8);
1077 if (!ret)
1078 ret = reg_write(client, RJ54N1_RA_SEL_UL, 8);
1079 break;
1080 case MEDIA_BUS_FMT_SBGGR10_1X10:
1081 ret = reg_write(client, RJ54N1_OUT_SEL, 5);
1082 break;
1083 default:
1084 ret = -EINVAL;
1085 }
1086
1087
1088 if (!ret)
1089 ret = reg_set(client, RJ54N1_OCLK_SEL_EN,
1090 (mf->code == MEDIA_BUS_FMT_SBGGR10_1X10) << 1, 2);
1091
1092 if (ret < 0)
1093 return ret;
1094
1095
1096 max_w = mf->width * (16 * 1024 - 1) / 1024;
1097 if (input_w > max_w)
1098 input_w = max_w;
1099 max_h = mf->height * (16 * 1024 - 1) / 1024;
1100 if (input_h > max_h)
1101 input_h = max_h;
1102
1103 output_w = mf->width;
1104 output_h = mf->height;
1105
1106 ret = rj54n1_sensor_scale(sd, &input_w, &input_h, &output_w, &output_h);
1107 if (ret < 0)
1108 return ret;
1109
1110 fmt = rj54n1_find_datafmt(mf->code, rj54n1_colour_fmts,
1111 ARRAY_SIZE(rj54n1_colour_fmts));
1112
1113 rj54n1->fmt = fmt;
1114 rj54n1->resize = ret;
1115 rj54n1->rect.width = input_w;
1116 rj54n1->rect.height = input_h;
1117 rj54n1->width = output_w;
1118 rj54n1->height = output_h;
1119
1120 mf->width = output_w;
1121 mf->height = output_h;
1122 mf->field = V4L2_FIELD_NONE;
1123 mf->colorspace = fmt->colorspace;
1124
1125 return 0;
1126}
1127
1128#ifdef CONFIG_VIDEO_ADV_DEBUG
1129static int rj54n1_g_register(struct v4l2_subdev *sd,
1130 struct v4l2_dbg_register *reg)
1131{
1132 struct i2c_client *client = v4l2_get_subdevdata(sd);
1133
1134 if (reg->reg < 0x400 || reg->reg > 0x1fff)
1135
1136 return -EINVAL;
1137
1138 reg->size = 1;
1139 reg->val = reg_read(client, reg->reg);
1140
1141 if (reg->val > 0xff)
1142 return -EIO;
1143
1144 return 0;
1145}
1146
1147static int rj54n1_s_register(struct v4l2_subdev *sd,
1148 const struct v4l2_dbg_register *reg)
1149{
1150 struct i2c_client *client = v4l2_get_subdevdata(sd);
1151
1152 if (reg->reg < 0x400 || reg->reg > 0x1fff)
1153
1154 return -EINVAL;
1155
1156 if (reg_write(client, reg->reg, reg->val) < 0)
1157 return -EIO;
1158
1159 return 0;
1160}
1161#endif
1162
1163static int rj54n1_s_power(struct v4l2_subdev *sd, int on)
1164{
1165 struct i2c_client *client = v4l2_get_subdevdata(sd);
1166 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
1167 struct rj54n1 *rj54n1 = to_rj54n1(client);
1168
1169 return soc_camera_set_power(&client->dev, ssdd, rj54n1->clk, on);
1170}
1171
1172static int rj54n1_s_ctrl(struct v4l2_ctrl *ctrl)
1173{
1174 struct rj54n1 *rj54n1 = container_of(ctrl->handler, struct rj54n1, hdl);
1175 struct v4l2_subdev *sd = &rj54n1->subdev;
1176 struct i2c_client *client = v4l2_get_subdevdata(sd);
1177 int data;
1178
1179 switch (ctrl->id) {
1180 case V4L2_CID_VFLIP:
1181 if (ctrl->val)
1182 data = reg_set(client, RJ54N1_MIRROR_STILL_MODE, 0, 1);
1183 else
1184 data = reg_set(client, RJ54N1_MIRROR_STILL_MODE, 1, 1);
1185 if (data < 0)
1186 return -EIO;
1187 return 0;
1188 case V4L2_CID_HFLIP:
1189 if (ctrl->val)
1190 data = reg_set(client, RJ54N1_MIRROR_STILL_MODE, 0, 2);
1191 else
1192 data = reg_set(client, RJ54N1_MIRROR_STILL_MODE, 2, 2);
1193 if (data < 0)
1194 return -EIO;
1195 return 0;
1196 case V4L2_CID_GAIN:
1197 if (reg_write(client, RJ54N1_Y_GAIN, ctrl->val * 2) < 0)
1198 return -EIO;
1199 return 0;
1200 case V4L2_CID_AUTO_WHITE_BALANCE:
1201
1202 if (reg_set(client, RJ54N1_WB_SEL_WEIGHT_I, ctrl->val << 7,
1203 0x80) < 0)
1204 return -EIO;
1205 rj54n1->auto_wb = ctrl->val;
1206 return 0;
1207 }
1208
1209 return -EINVAL;
1210}
1211
1212static const struct v4l2_ctrl_ops rj54n1_ctrl_ops = {
1213 .s_ctrl = rj54n1_s_ctrl,
1214};
1215
1216static struct v4l2_subdev_core_ops rj54n1_subdev_core_ops = {
1217#ifdef CONFIG_VIDEO_ADV_DEBUG
1218 .g_register = rj54n1_g_register,
1219 .s_register = rj54n1_s_register,
1220#endif
1221 .s_power = rj54n1_s_power,
1222};
1223
1224static int rj54n1_g_mbus_config(struct v4l2_subdev *sd,
1225 struct v4l2_mbus_config *cfg)
1226{
1227 struct i2c_client *client = v4l2_get_subdevdata(sd);
1228 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
1229
1230 cfg->flags =
1231 V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_PCLK_SAMPLE_FALLING |
1232 V4L2_MBUS_MASTER | V4L2_MBUS_DATA_ACTIVE_HIGH |
1233 V4L2_MBUS_HSYNC_ACTIVE_HIGH | V4L2_MBUS_VSYNC_ACTIVE_HIGH;
1234 cfg->type = V4L2_MBUS_PARALLEL;
1235 cfg->flags = soc_camera_apply_board_flags(ssdd, cfg);
1236
1237 return 0;
1238}
1239
1240static int rj54n1_s_mbus_config(struct v4l2_subdev *sd,
1241 const struct v4l2_mbus_config *cfg)
1242{
1243 struct i2c_client *client = v4l2_get_subdevdata(sd);
1244 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
1245
1246
1247 if (soc_camera_apply_board_flags(ssdd, cfg) &
1248 V4L2_MBUS_PCLK_SAMPLE_RISING)
1249 return reg_write(client, RJ54N1_OUT_SIGPO, 1 << 4);
1250 else
1251 return reg_write(client, RJ54N1_OUT_SIGPO, 0);
1252}
1253
1254static struct v4l2_subdev_video_ops rj54n1_subdev_video_ops = {
1255 .s_stream = rj54n1_s_stream,
1256 .g_mbus_config = rj54n1_g_mbus_config,
1257 .s_mbus_config = rj54n1_s_mbus_config,
1258};
1259
1260static const struct v4l2_subdev_pad_ops rj54n1_subdev_pad_ops = {
1261 .enum_mbus_code = rj54n1_enum_mbus_code,
1262 .get_selection = rj54n1_get_selection,
1263 .set_selection = rj54n1_set_selection,
1264 .get_fmt = rj54n1_get_fmt,
1265 .set_fmt = rj54n1_set_fmt,
1266};
1267
1268static struct v4l2_subdev_ops rj54n1_subdev_ops = {
1269 .core = &rj54n1_subdev_core_ops,
1270 .video = &rj54n1_subdev_video_ops,
1271 .pad = &rj54n1_subdev_pad_ops,
1272};
1273
1274
1275
1276
1277
1278static int rj54n1_video_probe(struct i2c_client *client,
1279 struct rj54n1_pdata *priv)
1280{
1281 struct rj54n1 *rj54n1 = to_rj54n1(client);
1282 int data1, data2;
1283 int ret;
1284
1285 ret = rj54n1_s_power(&rj54n1->subdev, 1);
1286 if (ret < 0)
1287 return ret;
1288
1289
1290 data1 = reg_read(client, RJ54N1_DEV_CODE);
1291 data2 = reg_read(client, RJ54N1_DEV_CODE2);
1292
1293 if (data1 != 0x51 || data2 != 0x10) {
1294 ret = -ENODEV;
1295 dev_info(&client->dev, "No RJ54N1CB0C found, read 0x%x:0x%x\n",
1296 data1, data2);
1297 goto done;
1298 }
1299
1300
1301 ret = reg_write(client, RJ54N1_IOC, priv->ioctl_high << 7);
1302 if (ret < 0)
1303 goto done;
1304
1305 dev_info(&client->dev, "Detected a RJ54N1CB0C chip ID 0x%x:0x%x\n",
1306 data1, data2);
1307
1308 ret = v4l2_ctrl_handler_setup(&rj54n1->hdl);
1309
1310done:
1311 rj54n1_s_power(&rj54n1->subdev, 0);
1312 return ret;
1313}
1314
1315static int rj54n1_probe(struct i2c_client *client,
1316 const struct i2c_device_id *did)
1317{
1318 struct rj54n1 *rj54n1;
1319 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
1320 struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
1321 struct rj54n1_pdata *rj54n1_priv;
1322 int ret;
1323
1324 if (!ssdd || !ssdd->drv_priv) {
1325 dev_err(&client->dev, "RJ54N1CB0C: missing platform data!\n");
1326 return -EINVAL;
1327 }
1328
1329 rj54n1_priv = ssdd->drv_priv;
1330
1331 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) {
1332 dev_warn(&adapter->dev,
1333 "I2C-Adapter doesn't support I2C_FUNC_SMBUS_BYTE\n");
1334 return -EIO;
1335 }
1336
1337 rj54n1 = devm_kzalloc(&client->dev, sizeof(struct rj54n1), GFP_KERNEL);
1338 if (!rj54n1)
1339 return -ENOMEM;
1340
1341 v4l2_i2c_subdev_init(&rj54n1->subdev, client, &rj54n1_subdev_ops);
1342 v4l2_ctrl_handler_init(&rj54n1->hdl, 4);
1343 v4l2_ctrl_new_std(&rj54n1->hdl, &rj54n1_ctrl_ops,
1344 V4L2_CID_VFLIP, 0, 1, 1, 0);
1345 v4l2_ctrl_new_std(&rj54n1->hdl, &rj54n1_ctrl_ops,
1346 V4L2_CID_HFLIP, 0, 1, 1, 0);
1347 v4l2_ctrl_new_std(&rj54n1->hdl, &rj54n1_ctrl_ops,
1348 V4L2_CID_GAIN, 0, 127, 1, 66);
1349 v4l2_ctrl_new_std(&rj54n1->hdl, &rj54n1_ctrl_ops,
1350 V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, 1);
1351 rj54n1->subdev.ctrl_handler = &rj54n1->hdl;
1352 if (rj54n1->hdl.error)
1353 return rj54n1->hdl.error;
1354
1355 rj54n1->clk_div = clk_div;
1356 rj54n1->rect.left = RJ54N1_COLUMN_SKIP;
1357 rj54n1->rect.top = RJ54N1_ROW_SKIP;
1358 rj54n1->rect.width = RJ54N1_MAX_WIDTH;
1359 rj54n1->rect.height = RJ54N1_MAX_HEIGHT;
1360 rj54n1->width = RJ54N1_MAX_WIDTH;
1361 rj54n1->height = RJ54N1_MAX_HEIGHT;
1362 rj54n1->fmt = &rj54n1_colour_fmts[0];
1363 rj54n1->resize = 1024;
1364 rj54n1->tgclk_mhz = (rj54n1_priv->mclk_freq / PLL_L * PLL_N) /
1365 (clk_div.ratio_tg + 1) / (clk_div.ratio_t + 1);
1366
1367 rj54n1->clk = v4l2_clk_get(&client->dev, "mclk");
1368 if (IS_ERR(rj54n1->clk)) {
1369 ret = PTR_ERR(rj54n1->clk);
1370 goto eclkget;
1371 }
1372
1373 ret = rj54n1_video_probe(client, rj54n1_priv);
1374 if (ret < 0) {
1375 v4l2_clk_put(rj54n1->clk);
1376eclkget:
1377 v4l2_ctrl_handler_free(&rj54n1->hdl);
1378 }
1379
1380 return ret;
1381}
1382
1383static int rj54n1_remove(struct i2c_client *client)
1384{
1385 struct rj54n1 *rj54n1 = to_rj54n1(client);
1386 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
1387
1388 v4l2_clk_put(rj54n1->clk);
1389 v4l2_device_unregister_subdev(&rj54n1->subdev);
1390 if (ssdd->free_bus)
1391 ssdd->free_bus(ssdd);
1392 v4l2_ctrl_handler_free(&rj54n1->hdl);
1393
1394 return 0;
1395}
1396
1397static const struct i2c_device_id rj54n1_id[] = {
1398 { "rj54n1cb0c", 0 },
1399 { }
1400};
1401MODULE_DEVICE_TABLE(i2c, rj54n1_id);
1402
1403static struct i2c_driver rj54n1_i2c_driver = {
1404 .driver = {
1405 .name = "rj54n1cb0c",
1406 },
1407 .probe = rj54n1_probe,
1408 .remove = rj54n1_remove,
1409 .id_table = rj54n1_id,
1410};
1411
1412module_i2c_driver(rj54n1_i2c_driver);
1413
1414MODULE_DESCRIPTION("Sharp RJ54N1CB0C Camera driver");
1415MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
1416MODULE_LICENSE("GPL v2");
1417
