LXR linux/drivers/net/ethernet/dlink/dl2k.h

   1/*  D-Link DL2000-based Gigabit Ethernet Adapter Linux driver */
   2/*
   3    Copyright (c) 2001, 2002 by D-Link Corporation
   4    Written by Edward Peng.<edward_peng@dlink.com.tw>
   5    Created 03-May-2001, base on Linux' sundance.c.
   6
   7    This program is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 2 of the License, or
  10    (at your option) any later version.
  11*/
  12
  13#ifndef __DL2K_H__
  14#define __DL2K_H__
  15
  16#include <linux/module.h>
  17#include <linux/kernel.h>
  18#include <linux/string.h>
  19#include <linux/timer.h>
  20#include <linux/errno.h>
  21#include <linux/ioport.h>
  22#include <linux/slab.h>
  23#include <linux/interrupt.h>
  24#include <linux/pci.h>
  25#include <linux/netdevice.h>
  26#include <linux/etherdevice.h>
  27#include <linux/skbuff.h>
  28#include <linux/crc32.h>
  29#include <linux/ethtool.h>
  30#include <linux/mii.h>
  31#include <linux/bitops.h>
  32#include <asm/processor.h>      /* Processor type for cache alignment. */
  33#include <asm/io.h>
  34#include <asm/uaccess.h>
  35#include <linux/delay.h>
  36#include <linux/spinlock.h>
  37#include <linux/time.h>
  38#define TX_RING_SIZE    256
  39#define TX_QUEUE_LEN    (TX_RING_SIZE - 1) /* Limit ring entries actually used.*/
  40#define RX_RING_SIZE    256
  41#define TX_TOTAL_SIZE   TX_RING_SIZE*sizeof(struct netdev_desc)
  42#define RX_TOTAL_SIZE   RX_RING_SIZE*sizeof(struct netdev_desc)
  43
  44/* Offsets to the device registers.
  45   Unlike software-only systems, device drivers interact with complex hardware.
  46   It's not useful to define symbolic names for every register bit in the
  47   device.  The name can only partially document the semantics and make
  48   the driver longer and more difficult to read.
  49   In general, only the important configuration values or bits changed
  50   multiple times should be defined symbolically.
  51*/
  52enum dl2x_offsets {
  53        /* I/O register offsets */
  54        DMACtrl = 0x00,
  55        RxDMAStatus = 0x08,
  56        TFDListPtr0 = 0x10,
  57        TFDListPtr1 = 0x14,
  58        TxDMABurstThresh = 0x18,
  59        TxDMAUrgentThresh = 0x19,
  60        TxDMAPollPeriod = 0x1a,
  61        RFDListPtr0 = 0x1c,
  62        RFDListPtr1 = 0x20,
  63        RxDMABurstThresh = 0x24,
  64        RxDMAUrgentThresh = 0x25,
  65        RxDMAPollPeriod = 0x26,
  66        RxDMAIntCtrl = 0x28,
  67        DebugCtrl = 0x2c,
  68        ASICCtrl = 0x30,
  69        FifoCtrl = 0x38,
  70        RxEarlyThresh = 0x3a,
  71        FlowOffThresh = 0x3c,
  72        FlowOnThresh = 0x3e,
  73        TxStartThresh = 0x44,
  74        EepromData = 0x48,
  75        EepromCtrl = 0x4a,
  76        ExpromAddr = 0x4c,
  77        Exprodata = 0x50,
  78        WakeEvent = 0x51,
  79        CountDown = 0x54,
  80        IntStatusAck = 0x5a,
  81        IntEnable = 0x5c,
  82        IntStatus = 0x5e,
  83        TxStatus = 0x60,
  84        MACCtrl = 0x6c,
  85        VLANTag = 0x70,
  86        PhyCtrl = 0x76,
  87        StationAddr0 = 0x78,
  88        StationAddr1 = 0x7a,
  89        StationAddr2 = 0x7c,
  90        VLANId = 0x80,
  91        MaxFrameSize = 0x86,
  92        ReceiveMode = 0x88,
  93        HashTable0 = 0x8c,
  94        HashTable1 = 0x90,
  95        RmonStatMask = 0x98,
  96        StatMask = 0x9c,
  97        RxJumboFrames = 0xbc,
  98        TCPCheckSumErrors = 0xc0,
  99        IPCheckSumErrors = 0xc2,
 100        UDPCheckSumErrors = 0xc4,
 101        TxJumboFrames = 0xf4,
 102        /* Ethernet MIB statistic register offsets */
 103        OctetRcvOk = 0xa8,
 104        McstOctetRcvOk = 0xac,
 105        BcstOctetRcvOk = 0xb0,
 106        FramesRcvOk = 0xb4,
 107        McstFramesRcvdOk = 0xb8,
 108        BcstFramesRcvdOk = 0xbe,
 109        MacControlFramesRcvd = 0xc6,
 110        FrameTooLongErrors = 0xc8,
 111        InRangeLengthErrors = 0xca,
 112        FramesCheckSeqErrors = 0xcc,
 113        FramesLostRxErrors = 0xce,
 114        OctetXmtOk = 0xd0,
 115        McstOctetXmtOk = 0xd4,
 116        BcstOctetXmtOk = 0xd8,
 117        FramesXmtOk = 0xdc,
 118        McstFramesXmtdOk = 0xe0,
 119        FramesWDeferredXmt = 0xe4,
 120        LateCollisions = 0xe8,
 121        MultiColFrames = 0xec,
 122        SingleColFrames = 0xf0,
 123        BcstFramesXmtdOk = 0xf6,
 124        CarrierSenseErrors = 0xf8,
 125        MacControlFramesXmtd = 0xfa,
 126        FramesAbortXSColls = 0xfc,
 127        FramesWEXDeferal = 0xfe,
 128        /* RMON statistic register offsets */
 129        EtherStatsCollisions = 0x100,
 130        EtherStatsOctetsTransmit = 0x104,
 131        EtherStatsPktsTransmit = 0x108,
 132        EtherStatsPkts64OctetTransmit = 0x10c,
 133        EtherStats65to127OctetsTransmit = 0x110,
 134        EtherStatsPkts128to255OctetsTransmit = 0x114,
 135        EtherStatsPkts256to511OctetsTransmit = 0x118,
 136        EtherStatsPkts512to1023OctetsTransmit = 0x11c,
 137        EtherStatsPkts1024to1518OctetsTransmit = 0x120,
 138        EtherStatsCRCAlignErrors = 0x124,
 139        EtherStatsUndersizePkts = 0x128,
 140        EtherStatsFragments = 0x12c,
 141        EtherStatsJabbers = 0x130,
 142        EtherStatsOctets = 0x134,
 143        EtherStatsPkts = 0x138,
 144        EtherStats64Octets = 0x13c,
 145        EtherStatsPkts65to127Octets = 0x140,
 146        EtherStatsPkts128to255Octets = 0x144,
 147        EtherStatsPkts256to511Octets = 0x148,
 148        EtherStatsPkts512to1023Octets = 0x14c,
 149        EtherStatsPkts1024to1518Octets = 0x150,
 150};
 151
 152/* Bits in the interrupt status/mask registers. */
 153enum IntStatus_bits {
 154        InterruptStatus = 0x0001,
 155        HostError = 0x0002,
 156        MACCtrlFrame = 0x0008,
 157        TxComplete = 0x0004,
 158        RxComplete = 0x0010,
 159        RxEarly = 0x0020,
 160        IntRequested = 0x0040,
 161        UpdateStats = 0x0080,
 162        LinkEvent = 0x0100,
 163        TxDMAComplete = 0x0200,
 164        RxDMAComplete = 0x0400,
 165        RFDListEnd = 0x0800,
 166        RxDMAPriority = 0x1000,
 167};
 168
 169/* Bits in the ReceiveMode register. */
 170enum ReceiveMode_bits {
 171        ReceiveUnicast = 0x0001,
 172        ReceiveMulticast = 0x0002,
 173        ReceiveBroadcast = 0x0004,
 174        ReceiveAllFrames = 0x0008,
 175        ReceiveMulticastHash = 0x0010,
 176        ReceiveIPMulticast = 0x0020,
 177        ReceiveVLANMatch = 0x0100,
 178        ReceiveVLANHash = 0x0200,
 179};
 180/* Bits in MACCtrl. */
 181enum MACCtrl_bits {
 182        DuplexSelect = 0x20,
 183        TxFlowControlEnable = 0x80,
 184        RxFlowControlEnable = 0x0100,
 185        RcvFCS = 0x200,
 186        AutoVLANtagging = 0x1000,
 187        AutoVLANuntagging = 0x2000,
 188        StatsEnable = 0x00200000,
 189        StatsDisable = 0x00400000,
 190        StatsEnabled = 0x00800000,
 191        TxEnable = 0x01000000,
 192        TxDisable = 0x02000000,
 193        TxEnabled = 0x04000000,
 194        RxEnable = 0x08000000,
 195        RxDisable = 0x10000000,
 196        RxEnabled = 0x20000000,
 197};
 198
 199enum ASICCtrl_LoWord_bits {
 200        PhyMedia = 0x0080,
 201};
 202
 203enum ASICCtrl_HiWord_bits {
 204        GlobalReset = 0x0001,
 205        RxReset = 0x0002,
 206        TxReset = 0x0004,
 207        DMAReset = 0x0008,
 208        FIFOReset = 0x0010,
 209        NetworkReset = 0x0020,
 210        HostReset = 0x0040,
 211        ResetBusy = 0x0400,
 212};
 213
 214#define IPG_AC_LED_MODE         BIT(14)
 215#define IPG_AC_LED_SPEED        BIT(27)
 216#define IPG_AC_LED_MODE_BIT_1   BIT(29)
 217
 218/* Transmit Frame Control bits */
 219enum TFC_bits {
 220        DwordAlign = 0x00000000,
 221        WordAlignDisable = 0x00030000,
 222        WordAlign = 0x00020000,
 223        TCPChecksumEnable = 0x00040000,
 224        UDPChecksumEnable = 0x00080000,
 225        IPChecksumEnable = 0x00100000,
 226        FCSAppendDisable = 0x00200000,
 227        TxIndicate = 0x00400000,
 228        TxDMAIndicate = 0x00800000,
 229        FragCountShift = 24,
 230        VLANTagInsert = 0x0000000010000000,
 231        TFDDone = 0x80000000,
 232        VIDShift = 32,
 233        UsePriorityShift = 48,
 234};
 235
 236/* Receive Frames Status bits */
 237enum RFS_bits {
 238        RxFIFOOverrun = 0x00010000,
 239        RxRuntFrame = 0x00020000,
 240        RxAlignmentError = 0x00040000,
 241        RxFCSError = 0x00080000,
 242        RxOverSizedFrame = 0x00100000,
 243        RxLengthError = 0x00200000,
 244        VLANDetected = 0x00400000,
 245        TCPDetected = 0x00800000,
 246        TCPError = 0x01000000,
 247        UDPDetected = 0x02000000,
 248        UDPError = 0x04000000,
 249        IPDetected = 0x08000000,
 250        IPError = 0x10000000,
 251        FrameStart = 0x20000000,
 252        FrameEnd = 0x40000000,
 253        RFDDone = 0x80000000,
 254        TCIShift = 32,
 255        RFS_Errors = 0x003f0000,
 256};
 257
 258#define MII_RESET_TIME_OUT              10000
 259/* MII register */
 260enum _mii_reg {
 261        MII_PHY_SCR = 16,
 262};
 263
 264/* PCS register */
 265enum _pcs_reg {
 266        PCS_BMCR = 0,
 267        PCS_BMSR = 1,
 268        PCS_ANAR = 4,
 269        PCS_ANLPAR = 5,
 270        PCS_ANER = 6,
 271        PCS_ANNPT = 7,
 272        PCS_ANLPRNP = 8,
 273        PCS_ESR = 15,
 274};
 275
 276/* IEEE Extened Status Register */
 277enum _mii_esr {
 278        MII_ESR_1000BX_FD = 0x8000,
 279        MII_ESR_1000BX_HD = 0x4000,
 280        MII_ESR_1000BT_FD = 0x2000,
 281        MII_ESR_1000BT_HD = 0x1000,
 282};
 283/* PHY Specific Control Register */
 284#if 0
 285typedef union t_MII_PHY_SCR {
 286        u16 image;
 287        struct {
 288                u16 disable_jabber:1;   // bit 0
 289                u16 polarity_reversal:1;        // bit 1
 290                u16 SEQ_test:1; // bit 2
 291                u16 _bit_3:1;   // bit 3
 292                u16 disable_CLK125:1;   // bit 4
 293                u16 mdi_crossover_mode:2;       // bit 6:5
 294                u16 enable_ext_dist:1;  // bit 7
 295                u16 _bit_8_9:2; // bit 9:8
 296                u16 force_link:1;       // bit 10
 297                u16 assert_CRS:1;       // bit 11
 298                u16 rcv_fifo_depth:2;   // bit 13:12
 299                u16 xmit_fifo_depth:2;  // bit 15:14
 300        } bits;
 301} PHY_SCR_t, *PPHY_SCR_t;
 302#endif
 303
 304typedef enum t_MII_ADMIN_STATUS {
 305        adm_reset,
 306        adm_operational,
 307        adm_loopback,
 308        adm_power_down,
 309        adm_isolate
 310} MII_ADMIN_t, *PMII_ADMIN_t;
 311
 312/* Physical Coding Sublayer Management (PCS) */
 313/* PCS control and status registers bitmap as the same as MII */
 314/* PCS Extended Status register bitmap as the same as MII */
 315/* PCS ANAR */
 316enum _pcs_anar {
 317        PCS_ANAR_NEXT_PAGE = 0x8000,
 318        PCS_ANAR_REMOTE_FAULT = 0x3000,
 319        PCS_ANAR_ASYMMETRIC = 0x0100,
 320        PCS_ANAR_PAUSE = 0x0080,
 321        PCS_ANAR_HALF_DUPLEX = 0x0040,
 322        PCS_ANAR_FULL_DUPLEX = 0x0020,
 323};
 324/* PCS ANLPAR */
 325enum _pcs_anlpar {
 326        PCS_ANLPAR_NEXT_PAGE = PCS_ANAR_NEXT_PAGE,
 327        PCS_ANLPAR_REMOTE_FAULT = PCS_ANAR_REMOTE_FAULT,
 328        PCS_ANLPAR_ASYMMETRIC = PCS_ANAR_ASYMMETRIC,
 329        PCS_ANLPAR_PAUSE = PCS_ANAR_PAUSE,
 330        PCS_ANLPAR_HALF_DUPLEX = PCS_ANAR_HALF_DUPLEX,
 331        PCS_ANLPAR_FULL_DUPLEX = PCS_ANAR_FULL_DUPLEX,
 332};
 333
 334typedef struct t_SROM {
 335        u16 config_param;       /* 0x00 */
 336        u16 asic_ctrl;          /* 0x02 */
 337        u16 sub_vendor_id;      /* 0x04 */
 338        u16 sub_system_id;      /* 0x06 */
 339        u16 pci_base_1;         /* 0x08 (IP1000A only) */
 340        u16 pci_base_2;         /* 0x0a (IP1000A only) */
 341        u16 led_mode;           /* 0x0c (IP1000A only) */
 342        u16 reserved1[9];       /* 0x0e-0x1f */
 343        u8 mac_addr[6];         /* 0x20-0x25 */
 344        u8 reserved2[10];       /* 0x26-0x2f */
 345        u8 sib[204];            /* 0x30-0xfb */
 346        u32 crc;                /* 0xfc-0xff */
 347} SROM_t, *PSROM_t;
 348
 349/* Ioctl custom data */
 350struct ioctl_data {
 351        char signature[10];
 352        int cmd;
 353        int len;
 354        char *data;
 355};
 356
 357/* The Rx and Tx buffer descriptors. */
 358struct netdev_desc {
 359        __le64 next_desc;
 360        __le64 status;
 361        __le64 fraginfo;
 362};
 363
 364#define PRIV_ALIGN      15      /* Required alignment mask */
 365/* Use  __attribute__((aligned (L1_CACHE_BYTES)))  to maintain alignment
 366   within the structure. */
 367struct netdev_private {
 368        /* Descriptor rings first for alignment. */
 369        struct netdev_desc *rx_ring;
 370        struct netdev_desc *tx_ring;
 371        struct sk_buff *rx_skbuff[RX_RING_SIZE];
 372        struct sk_buff *tx_skbuff[TX_RING_SIZE];
 373        dma_addr_t tx_ring_dma;
 374        dma_addr_t rx_ring_dma;
 375        struct pci_dev *pdev;
 376        void __iomem *ioaddr;
 377        void __iomem *eeprom_addr;
 378        spinlock_t tx_lock;
 379        spinlock_t rx_lock;
 380        struct net_device_stats stats;
 381        unsigned int rx_buf_sz;         /* Based on MTU+slack. */
 382        unsigned int speed;             /* Operating speed */
 383        unsigned int vlan;              /* VLAN Id */
 384        unsigned int chip_id;           /* PCI table chip id */
 385        unsigned int rx_coalesce;       /* Maximum frames each RxDMAComplete intr */
 386        unsigned int rx_timeout;        /* Wait time between RxDMAComplete intr */
 387        unsigned int tx_coalesce;       /* Maximum frames each tx interrupt */
 388        unsigned int full_duplex:1;     /* Full-duplex operation requested. */
 389        unsigned int an_enable:2;       /* Auto-Negotiated Enable */
 390        unsigned int jumbo:1;           /* Jumbo frame enable */
 391        unsigned int coalesce:1;        /* Rx coalescing enable */
 392        unsigned int tx_flow:1;         /* Tx flow control enable */
 393        unsigned int rx_flow:1;         /* Rx flow control enable */
 394        unsigned int phy_media:1;       /* 1: fiber, 0: copper */
 395        unsigned int link_status:1;     /* Current link status */
 396        struct netdev_desc *last_tx;    /* Last Tx descriptor used. */
 397        unsigned long cur_rx, old_rx;   /* Producer/consumer ring indices */
 398        unsigned long cur_tx, old_tx;
 399        struct timer_list timer;
 400        int wake_polarity;
 401        char name[256];         /* net device description */
 402        u8 duplex_polarity;
 403        u16 mcast_filter[4];
 404        u16 advertising;        /* NWay media advertisement */
 405        u16 negotiate;          /* Negotiated media */
 406        int phy_addr;           /* PHY addresses. */
 407        u16 led_mode;           /* LED mode read from EEPROM (IP1000A only) */
 408};
 409
 410/* The station address location in the EEPROM. */
 411/* The struct pci_device_id consist of:
 412        vendor, device          Vendor and device ID to match (or PCI_ANY_ID)
 413        subvendor, subdevice    Subsystem vendor and device ID to match (or PCI_ANY_ID)
 414        class                   Device class to match. The class_mask tells which bits
 415        class_mask              of the class are honored during the comparison.
 416        driver_data             Data private to the driver.
 417*/
 418#define CHIP_IP1000A    1
 419
 420static const struct pci_device_id rio_pci_tbl[] = {
 421        {0x1186, 0x4000, PCI_ANY_ID, PCI_ANY_ID, },
 422        {0x13f0, 0x1021, PCI_ANY_ID, PCI_ANY_ID, },
 423        { PCI_VDEVICE(SUNDANCE, 0x1023), CHIP_IP1000A },
 424        { PCI_VDEVICE(SUNDANCE, 0x2021), CHIP_IP1000A },
 425        { PCI_VDEVICE(DLINK,    0x9021), CHIP_IP1000A },
 426        { PCI_VDEVICE(DLINK,    0x4020), CHIP_IP1000A },
 427        { }
 428};
 429MODULE_DEVICE_TABLE (pci, rio_pci_tbl);
 430#define TX_TIMEOUT  (4*HZ)
 431#define PACKET_SIZE             1536
 432#define MAX_JUMBO               8000
 433#define RIO_IO_SIZE             340
 434#define DEFAULT_RXC             5
 435#define DEFAULT_RXT             750
 436#define DEFAULT_TXC             1
 437#define MAX_TXC                 8
 438#endif                          /* __DL2K_H__ */
 439