1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23#ifndef __GIANFAR_H
24#define __GIANFAR_H
25
26#include <linux/kernel.h>
27#include <linux/sched.h>
28#include <linux/string.h>
29#include <linux/errno.h>
30#include <linux/slab.h>
31#include <linux/interrupt.h>
32#include <linux/delay.h>
33#include <linux/netdevice.h>
34#include <linux/etherdevice.h>
35#include <linux/skbuff.h>
36#include <linux/spinlock.h>
37#include <linux/mm.h>
38#include <linux/mii.h>
39#include <linux/phy.h>
40
41#include <asm/io.h>
42#include <asm/irq.h>
43#include <asm/uaccess.h>
44#include <linux/module.h>
45#include <linux/crc32.h>
46#include <linux/workqueue.h>
47#include <linux/ethtool.h>
48
49struct ethtool_flow_spec_container {
50 struct ethtool_rx_flow_spec fs;
51 struct list_head list;
52};
53
54struct ethtool_rx_list {
55 struct list_head list;
56 unsigned int count;
57};
58
59
60#define GFAR_DEV_WEIGHT 64
61
62
63#define GMAC_FCB_LEN 8
64
65
66#define GMAC_TXPAL_LEN 16
67
68
69#define DEFAULT_PADDING 2
70
71
72#define RXBUF_ALIGNMENT 64
73
74#define PHY_INIT_TIMEOUT 100000
75
76#define DRV_NAME "gfar-enet"
77extern const char gfar_driver_version[];
78
79
80#define MAX_TX_QS 0x8
81#define MAX_RX_QS 0x8
82
83
84#define MAXGROUPS 0x2
85
86
87#define DEFAULT_TX_RING_SIZE 256
88#define DEFAULT_RX_RING_SIZE 256
89
90#define GFAR_RX_BUFF_ALLOC 16
91
92#define GFAR_RX_MAX_RING_SIZE 256
93#define GFAR_TX_MAX_RING_SIZE 256
94
95#define GFAR_MAX_FIFO_THRESHOLD 511
96#define GFAR_MAX_FIFO_STARVE 511
97#define GFAR_MAX_FIFO_STARVE_OFF 511
98
99#define FBTHR_SHIFT 24
100#define DEFAULT_RX_LFC_THR 16
101#define DEFAULT_LFC_PTVVAL 4
102
103
104#define GFAR_RXB_SIZE roundup(1536 + 8, 64)
105#define GFAR_SKBFRAG_SIZE (RXBUF_ALIGNMENT + GFAR_RXB_SIZE \
106 + SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
107#define GFAR_RXB_TRUESIZE 2048
108
109#define TX_RING_MOD_MASK(size) (size-1)
110#define RX_RING_MOD_MASK(size) (size-1)
111#define GFAR_JUMBO_FRAME_SIZE 9600
112
113#define DEFAULT_FIFO_TX_THR 0x100
114#define DEFAULT_FIFO_TX_STARVE 0x40
115#define DEFAULT_FIFO_TX_STARVE_OFF 0x80
116#define DEFAULT_BD_STASH 1
117#define DEFAULT_STASH_LENGTH 96
118#define DEFAULT_STASH_INDEX 0
119
120
121#define GFAR_EM_NUM 15
122
123
124
125
126
127
128
129
130
131
132
133#define GFAR_GBIT_TIME 512
134#define GFAR_100_TIME 2560
135#define GFAR_10_TIME 25600
136
137#define DEFAULT_TX_COALESCE 1
138#define DEFAULT_TXCOUNT 16
139#define DEFAULT_TXTIME 21
140
141#define DEFAULT_RXTIME 21
142
143#define DEFAULT_RX_COALESCE 0
144#define DEFAULT_RXCOUNT 0
145
146#define GFAR_SUPPORTED (SUPPORTED_10baseT_Half \
147 | SUPPORTED_10baseT_Full \
148 | SUPPORTED_100baseT_Half \
149 | SUPPORTED_100baseT_Full \
150 | SUPPORTED_Autoneg \
151 | SUPPORTED_MII)
152
153#define GFAR_SUPPORTED_GBIT SUPPORTED_1000baseT_Full
154
155
156#define MII_TBICON 0x11
157
158
159#define TBICON_CLK_SELECT 0x0020
160
161
162#define MACCFG1_SOFT_RESET 0x80000000
163#define MACCFG1_RESET_RX_MC 0x00080000
164#define MACCFG1_RESET_TX_MC 0x00040000
165#define MACCFG1_RESET_RX_FUN 0x00020000
166#define MACCFG1_RESET_TX_FUN 0x00010000
167#define MACCFG1_LOOPBACK 0x00000100
168#define MACCFG1_RX_FLOW 0x00000020
169#define MACCFG1_TX_FLOW 0x00000010
170#define MACCFG1_SYNCD_RX_EN 0x00000008
171#define MACCFG1_RX_EN 0x00000004
172#define MACCFG1_SYNCD_TX_EN 0x00000002
173#define MACCFG1_TX_EN 0x00000001
174
175#define MACCFG2_INIT_SETTINGS 0x00007205
176#define MACCFG2_FULL_DUPLEX 0x00000001
177#define MACCFG2_IF 0x00000300
178#define MACCFG2_MII 0x00000100
179#define MACCFG2_GMII 0x00000200
180#define MACCFG2_HUGEFRAME 0x00000020
181#define MACCFG2_LENGTHCHECK 0x00000010
182#define MACCFG2_MPEN 0x00000008
183
184#define ECNTRL_FIFM 0x00008000
185#define ECNTRL_INIT_SETTINGS 0x00001000
186#define ECNTRL_TBI_MODE 0x00000020
187#define ECNTRL_REDUCED_MODE 0x00000010
188#define ECNTRL_R100 0x00000008
189#define ECNTRL_REDUCED_MII_MODE 0x00000004
190#define ECNTRL_SGMII_MODE 0x00000002
191
192#define MRBLR_INIT_SETTINGS DEFAULT_RX_BUFFER_SIZE
193
194#define MINFLR_INIT_SETTINGS 0x00000040
195
196
197#define TQUEUE_EN0 0x00008000
198#define TQUEUE_EN1 0x00004000
199#define TQUEUE_EN2 0x00002000
200#define TQUEUE_EN3 0x00001000
201#define TQUEUE_EN4 0x00000800
202#define TQUEUE_EN5 0x00000400
203#define TQUEUE_EN6 0x00000200
204#define TQUEUE_EN7 0x00000100
205#define TQUEUE_EN_ALL 0x0000FF00
206
207#define TR03WT_WT0_MASK 0xFF000000
208#define TR03WT_WT1_MASK 0x00FF0000
209#define TR03WT_WT2_MASK 0x0000FF00
210#define TR03WT_WT3_MASK 0x000000FF
211
212#define TR47WT_WT4_MASK 0xFF000000
213#define TR47WT_WT5_MASK 0x00FF0000
214#define TR47WT_WT6_MASK 0x0000FF00
215#define TR47WT_WT7_MASK 0x000000FF
216
217
218#define RQUEUE_EX0 0x00800000
219#define RQUEUE_EX1 0x00400000
220#define RQUEUE_EX2 0x00200000
221#define RQUEUE_EX3 0x00100000
222#define RQUEUE_EX4 0x00080000
223#define RQUEUE_EX5 0x00040000
224#define RQUEUE_EX6 0x00020000
225#define RQUEUE_EX7 0x00010000
226#define RQUEUE_EX_ALL 0x00FF0000
227
228#define RQUEUE_EN0 0x00000080
229#define RQUEUE_EN1 0x00000040
230#define RQUEUE_EN2 0x00000020
231#define RQUEUE_EN3 0x00000010
232#define RQUEUE_EN4 0x00000008
233#define RQUEUE_EN5 0x00000004
234#define RQUEUE_EN6 0x00000002
235#define RQUEUE_EN7 0x00000001
236#define RQUEUE_EN_ALL 0x000000FF
237
238
239#define DMACTRL_INIT_SETTINGS 0x000000c3
240#define DMACTRL_GRS 0x00000010
241#define DMACTRL_GTS 0x00000008
242
243#define TSTAT_CLEAR_THALT_ALL 0xFF000000
244#define TSTAT_CLEAR_THALT 0x80000000
245#define TSTAT_CLEAR_THALT0 0x80000000
246#define TSTAT_CLEAR_THALT1 0x40000000
247#define TSTAT_CLEAR_THALT2 0x20000000
248#define TSTAT_CLEAR_THALT3 0x10000000
249#define TSTAT_CLEAR_THALT4 0x08000000
250#define TSTAT_CLEAR_THALT5 0x04000000
251#define TSTAT_CLEAR_THALT6 0x02000000
252#define TSTAT_CLEAR_THALT7 0x01000000
253
254
255#define IC_ICEN 0x80000000
256#define IC_ICFT_MASK 0x1fe00000
257#define IC_ICFT_SHIFT 21
258#define mk_ic_icft(x) \
259 (((unsigned int)x << IC_ICFT_SHIFT)&IC_ICFT_MASK)
260#define IC_ICTT_MASK 0x0000ffff
261#define mk_ic_ictt(x) (x&IC_ICTT_MASK)
262
263#define mk_ic_value(count, time) (IC_ICEN | \
264 mk_ic_icft(count) | \
265 mk_ic_ictt(time))
266#define get_icft_value(ic) (((unsigned long)ic & IC_ICFT_MASK) >> \
267 IC_ICFT_SHIFT)
268#define get_ictt_value(ic) ((unsigned long)ic & IC_ICTT_MASK)
269
270#define DEFAULT_TXIC mk_ic_value(DEFAULT_TXCOUNT, DEFAULT_TXTIME)
271#define DEFAULT_RXIC mk_ic_value(DEFAULT_RXCOUNT, DEFAULT_RXTIME)
272
273#define skip_bd(bdp, stride, base, ring_size) ({ \
274 typeof(bdp) new_bd = (bdp) + (stride); \
275 (new_bd >= (base) + (ring_size)) ? (new_bd - (ring_size)) : new_bd; })
276
277#define next_bd(bdp, base, ring_size) skip_bd(bdp, 1, base, ring_size)
278
279#define RCTRL_TS_ENABLE 0x01000000
280#define RCTRL_PAL_MASK 0x001f0000
281#define RCTRL_LFC 0x00004000
282#define RCTRL_VLEX 0x00002000
283#define RCTRL_FILREN 0x00001000
284#define RCTRL_GHTX 0x00000400
285#define RCTRL_IPCSEN 0x00000200
286#define RCTRL_TUCSEN 0x00000100
287#define RCTRL_PRSDEP_MASK 0x000000c0
288#define RCTRL_PRSDEP_INIT 0x000000c0
289#define RCTRL_PRSFM 0x00000020
290#define RCTRL_PROM 0x00000008
291#define RCTRL_EMEN 0x00000002
292#define RCTRL_REQ_PARSER (RCTRL_VLEX | RCTRL_IPCSEN | \
293 RCTRL_TUCSEN | RCTRL_FILREN)
294#define RCTRL_CHECKSUMMING (RCTRL_IPCSEN | RCTRL_TUCSEN | \
295 RCTRL_PRSDEP_INIT)
296#define RCTRL_EXTHASH (RCTRL_GHTX)
297#define RCTRL_VLAN (RCTRL_PRSDEP_INIT)
298#define RCTRL_PADDING(x) ((x << 16) & RCTRL_PAL_MASK)
299
300
301#define RSTAT_CLEAR_RHALT 0x00800000
302#define RSTAT_CLEAR_RXF0 0x00000080
303#define RSTAT_RXF_MASK 0x000000ff
304
305#define TCTRL_IPCSEN 0x00004000
306#define TCTRL_TUCSEN 0x00002000
307#define TCTRL_VLINS 0x00001000
308#define TCTRL_THDF 0x00000800
309#define TCTRL_RFCPAUSE 0x00000010
310#define TCTRL_TFCPAUSE 0x00000008
311#define TCTRL_TXSCHED_MASK 0x00000006
312#define TCTRL_TXSCHED_INIT 0x00000000
313
314#define TCTRL_TXSCHED_PRIO 0x00000002
315
316#define TCTRL_TXSCHED_WRRS 0x00000004
317
318
319
320
321#define DEFAULT_WRRS_WEIGHT 0x18181818
322
323#define TCTRL_INIT_CSUM (TCTRL_TUCSEN | TCTRL_IPCSEN)
324
325#define IEVENT_INIT_CLEAR 0xffffffff
326#define IEVENT_BABR 0x80000000
327#define IEVENT_RXC 0x40000000
328#define IEVENT_BSY 0x20000000
329#define IEVENT_EBERR 0x10000000
330#define IEVENT_MSRO 0x04000000
331#define IEVENT_GTSC 0x02000000
332#define IEVENT_BABT 0x01000000
333#define IEVENT_TXC 0x00800000
334#define IEVENT_TXE 0x00400000
335#define IEVENT_TXB 0x00200000
336#define IEVENT_TXF 0x00100000
337#define IEVENT_LC 0x00040000
338#define IEVENT_CRL 0x00020000
339#define IEVENT_XFUN 0x00010000
340#define IEVENT_RXB0 0x00008000
341#define IEVENT_MAG 0x00000800
342#define IEVENT_GRSC 0x00000100
343#define IEVENT_RXF0 0x00000080
344#define IEVENT_FGPI 0x00000010
345#define IEVENT_FIR 0x00000008
346#define IEVENT_FIQ 0x00000004
347#define IEVENT_DPE 0x00000002
348#define IEVENT_PERR 0x00000001
349#define IEVENT_RX_MASK (IEVENT_RXB0 | IEVENT_RXF0 | IEVENT_BSY)
350#define IEVENT_TX_MASK (IEVENT_TXB | IEVENT_TXF)
351#define IEVENT_RTX_MASK (IEVENT_RX_MASK | IEVENT_TX_MASK)
352#define IEVENT_ERR_MASK \
353(IEVENT_RXC | IEVENT_BSY | IEVENT_EBERR | IEVENT_MSRO | \
354 IEVENT_BABT | IEVENT_TXC | IEVENT_TXE | IEVENT_LC \
355 | IEVENT_CRL | IEVENT_XFUN | IEVENT_DPE | IEVENT_PERR \
356 | IEVENT_MAG | IEVENT_BABR)
357
358#define IMASK_INIT_CLEAR 0x00000000
359#define IMASK_BABR 0x80000000
360#define IMASK_RXC 0x40000000
361#define IMASK_BSY 0x20000000
362#define IMASK_EBERR 0x10000000
363#define IMASK_MSRO 0x04000000
364#define IMASK_GTSC 0x02000000
365#define IMASK_BABT 0x01000000
366#define IMASK_TXC 0x00800000
367#define IMASK_TXEEN 0x00400000
368#define IMASK_TXBEN 0x00200000
369#define IMASK_TXFEN 0x00100000
370#define IMASK_LC 0x00040000
371#define IMASK_CRL 0x00020000
372#define IMASK_XFUN 0x00010000
373#define IMASK_RXB0 0x00008000
374#define IMASK_MAG 0x00000800
375#define IMASK_GRSC 0x00000100
376#define IMASK_RXFEN0 0x00000080
377#define IMASK_FGPI 0x00000010
378#define IMASK_FIR 0x00000008
379#define IMASK_FIQ 0x00000004
380#define IMASK_DPE 0x00000002
381#define IMASK_PERR 0x00000001
382#define IMASK_DEFAULT (IMASK_TXEEN | IMASK_TXFEN | IMASK_TXBEN | \
383 IMASK_RXFEN0 | IMASK_BSY | IMASK_EBERR | IMASK_BABR | \
384 IMASK_XFUN | IMASK_RXC | IMASK_BABT | IMASK_DPE \
385 | IMASK_PERR)
386#define IMASK_RX_DEFAULT (IMASK_RXFEN0 | IMASK_BSY)
387#define IMASK_TX_DEFAULT (IMASK_TXFEN | IMASK_TXBEN)
388
389#define IMASK_RX_DISABLED ((~(IMASK_RX_DEFAULT)) & IMASK_DEFAULT)
390#define IMASK_TX_DISABLED ((~(IMASK_TX_DEFAULT)) & IMASK_DEFAULT)
391
392
393#define FIFO_TX_THR_MASK 0x01ff
394#define FIFO_TX_STARVE_MASK 0x01ff
395#define FIFO_TX_STARVE_OFF_MASK 0x01ff
396
397
398
399
400#define ATTR_BDSTASH 0x00000800
401
402#define ATTR_BUFSTASH 0x00004000
403
404#define ATTR_SNOOPING 0x000000c0
405#define ATTR_INIT_SETTINGS ATTR_SNOOPING
406
407#define ATTRELI_INIT_SETTINGS 0x0
408#define ATTRELI_EL_MASK 0x3fff0000
409#define ATTRELI_EL(x) (x << 16)
410#define ATTRELI_EI_MASK 0x00003fff
411#define ATTRELI_EI(x) (x)
412
413#define BD_LFLAG(flags) ((flags) << 16)
414#define BD_LENGTH_MASK 0x0000ffff
415
416#define FPR_FILER_MASK 0xFFFFFFFF
417#define MAX_FILER_IDX 0xFF
418
419
420
421#define DEFAULT_8RXQ_RIR0 0x05397700
422
423#define DEFAULT_2RXQ_RIR0 0x04104100
424
425
426#define RQFCR_GPI 0x80000000
427#define RQFCR_HASHTBL_Q 0x00000000
428#define RQFCR_HASHTBL_0 0x00020000
429#define RQFCR_HASHTBL_1 0x00040000
430#define RQFCR_HASHTBL_2 0x00060000
431#define RQFCR_HASHTBL_3 0x00080000
432#define RQFCR_HASH 0x00010000
433#define RQFCR_QUEUE 0x0000FC00
434#define RQFCR_CLE 0x00000200
435#define RQFCR_RJE 0x00000100
436#define RQFCR_AND 0x00000080
437#define RQFCR_CMP_EXACT 0x00000000
438#define RQFCR_CMP_MATCH 0x00000020
439#define RQFCR_CMP_NOEXACT 0x00000040
440#define RQFCR_CMP_NOMATCH 0x00000060
441
442
443#define RQFCR_PID_MASK 0x00000000
444#define RQFCR_PID_PARSE 0x00000001
445#define RQFCR_PID_ARB 0x00000002
446#define RQFCR_PID_DAH 0x00000003
447#define RQFCR_PID_DAL 0x00000004
448#define RQFCR_PID_SAH 0x00000005
449#define RQFCR_PID_SAL 0x00000006
450#define RQFCR_PID_ETY 0x00000007
451#define RQFCR_PID_VID 0x00000008
452#define RQFCR_PID_PRI 0x00000009
453#define RQFCR_PID_TOS 0x0000000A
454#define RQFCR_PID_L4P 0x0000000B
455#define RQFCR_PID_DIA 0x0000000C
456#define RQFCR_PID_SIA 0x0000000D
457#define RQFCR_PID_DPT 0x0000000E
458#define RQFCR_PID_SPT 0x0000000F
459
460
461#define RQFPR_HDR_GE_512 0x00200000
462#define RQFPR_LERR 0x00100000
463#define RQFPR_RAR 0x00080000
464#define RQFPR_RARQ 0x00040000
465#define RQFPR_AR 0x00020000
466#define RQFPR_ARQ 0x00010000
467#define RQFPR_EBC 0x00008000
468#define RQFPR_VLN 0x00004000
469#define RQFPR_CFI 0x00002000
470#define RQFPR_JUM 0x00001000
471#define RQFPR_IPF 0x00000800
472#define RQFPR_FIF 0x00000400
473#define RQFPR_IPV4 0x00000200
474#define RQFPR_IPV6 0x00000100
475#define RQFPR_ICC 0x00000080
476#define RQFPR_ICV 0x00000040
477#define RQFPR_TCP 0x00000020
478#define RQFPR_UDP 0x00000010
479#define RQFPR_TUC 0x00000008
480#define RQFPR_TUV 0x00000004
481#define RQFPR_PER 0x00000002
482#define RQFPR_EER 0x00000001
483
484
485#define TXBD_READY 0x8000
486#define TXBD_PADCRC 0x4000
487#define TXBD_WRAP 0x2000
488#define TXBD_INTERRUPT 0x1000
489#define TXBD_LAST 0x0800
490#define TXBD_CRC 0x0400
491#define TXBD_DEF 0x0200
492#define TXBD_HUGEFRAME 0x0080
493#define TXBD_LATECOLLISION 0x0080
494#define TXBD_RETRYLIMIT 0x0040
495#define TXBD_RETRYCOUNTMASK 0x003c
496#define TXBD_UNDERRUN 0x0002
497#define TXBD_TOE 0x0002
498
499
500#define TXFCB_VLN 0x80
501#define TXFCB_IP 0x40
502#define TXFCB_IP6 0x20
503#define TXFCB_TUP 0x10
504#define TXFCB_UDP 0x08
505#define TXFCB_CIP 0x04
506#define TXFCB_CTU 0x02
507#define TXFCB_NPH 0x01
508#define TXFCB_DEFAULT (TXFCB_IP|TXFCB_TUP|TXFCB_CTU|TXFCB_NPH)
509
510
511#define RXBD_EMPTY 0x8000
512#define RXBD_RO1 0x4000
513#define RXBD_WRAP 0x2000
514#define RXBD_INTERRUPT 0x1000
515#define RXBD_LAST 0x0800
516#define RXBD_FIRST 0x0400
517#define RXBD_MISS 0x0100
518#define RXBD_BROADCAST 0x0080
519#define RXBD_MULTICAST 0x0040
520#define RXBD_LARGE 0x0020
521#define RXBD_NONOCTET 0x0010
522#define RXBD_SHORT 0x0008
523#define RXBD_CRCERR 0x0004
524#define RXBD_OVERRUN 0x0002
525#define RXBD_TRUNCATED 0x0001
526#define RXBD_STATS 0x01ff
527#define RXBD_ERR (RXBD_LARGE | RXBD_SHORT | RXBD_NONOCTET \
528 | RXBD_CRCERR | RXBD_OVERRUN \
529 | RXBD_TRUNCATED)
530
531
532#define RXFCB_VLN 0x8000
533#define RXFCB_IP 0x4000
534#define RXFCB_IP6 0x2000
535#define RXFCB_TUP 0x1000
536#define RXFCB_CIP 0x0800
537#define RXFCB_CTU 0x0400
538#define RXFCB_EIP 0x0200
539#define RXFCB_ETU 0x0100
540#define RXFCB_CSUM_MASK 0x0f00
541#define RXFCB_PERR_MASK 0x000c
542#define RXFCB_PERR_BADL3 0x0008
543
544#define GFAR_INT_NAME_MAX (IFNAMSIZ + 6)
545
546#define GFAR_WOL_MAGIC 0x00000001
547#define GFAR_WOL_FILER_UCAST 0x00000002
548
549struct txbd8
550{
551 union {
552 struct {
553 __be16 status;
554 __be16 length;
555 };
556 __be32 lstatus;
557 };
558 __be32 bufPtr;
559};
560
561struct txfcb {
562 u8 flags;
563 u8 ptp;
564 u8 l4os;
565 u8 l3os;
566 __be16 phcs;
567 __be16 vlctl;
568};
569
570struct rxbd8
571{
572 union {
573 struct {
574 __be16 status;
575 __be16 length;
576 };
577 __be32 lstatus;
578 };
579 __be32 bufPtr;
580};
581
582struct rxfcb {
583 __be16 flags;
584 u8 rq;
585 u8 pro;
586 u16 reserved;
587 __be16 vlctl;
588};
589
590struct gianfar_skb_cb {
591 unsigned int bytes_sent;
592};
593
594#define GFAR_CB(skb) ((struct gianfar_skb_cb *)((skb)->cb))
595
596struct rmon_mib
597{
598 u32 tr64;
599 u32 tr127;
600 u32 tr255;
601 u32 tr511;
602 u32 tr1k;
603 u32 trmax;
604 u32 trmgv;
605 u32 rbyt;
606 u32 rpkt;
607 u32 rfcs;
608 u32 rmca;
609 u32 rbca;
610 u32 rxcf;
611 u32 rxpf;
612 u32 rxuo;
613 u32 raln;
614 u32 rflr;
615 u32 rcde;
616 u32 rcse;
617 u32 rund;
618 u32 rovr;
619 u32 rfrg;
620 u32 rjbr;
621 u32 rdrp;
622 u32 tbyt;
623 u32 tpkt;
624 u32 tmca;
625 u32 tbca;
626 u32 txpf;
627 u32 tdfr;
628 u32 tedf;
629 u32 tscl;
630 u32 tmcl;
631 u32 tlcl;
632 u32 txcl;
633 u32 tncl;
634 u8 res1[4];
635 u32 tdrp;
636 u32 tjbr;
637 u32 tfcs;
638 u32 txcf;
639 u32 tovr;
640 u32 tund;
641 u32 tfrg;
642 u32 car1;
643 u32 car2;
644 u32 cam1;
645 u32 cam2;
646};
647
648struct gfar_extra_stats {
649 atomic64_t rx_alloc_err;
650 atomic64_t rx_large;
651 atomic64_t rx_short;
652 atomic64_t rx_nonoctet;
653 atomic64_t rx_crcerr;
654 atomic64_t rx_overrun;
655 atomic64_t rx_bsy;
656 atomic64_t rx_babr;
657 atomic64_t rx_trunc;
658 atomic64_t eberr;
659 atomic64_t tx_babt;
660 atomic64_t tx_underrun;
661 atomic64_t tx_timeout;
662};
663
664#define GFAR_RMON_LEN ((sizeof(struct rmon_mib) - 16)/sizeof(u32))
665#define GFAR_EXTRA_STATS_LEN \
666 (sizeof(struct gfar_extra_stats)/sizeof(atomic64_t))
667
668
669#define GFAR_STATS_LEN (GFAR_RMON_LEN + GFAR_EXTRA_STATS_LEN)
670
671struct gfar {
672 u32 tsec_id;
673 u32 tsec_id2;
674 u8 res1[8];
675 u32 ievent;
676 u32 imask;
677 u32 edis;
678 u32 emapg;
679 u32 ecntrl;
680 u32 minflr;
681 u32 ptv;
682 u32 dmactrl;
683 u32 tbipa;
684 u8 res2[28];
685 u32 fifo_rx_pause;
686
687 u32 fifo_rx_pause_shutoff;
688
689 u32 fifo_rx_alarm;
690
691 u32 fifo_rx_alarm_shutoff;
692
693 u8 res3[44];
694 u32 fifo_tx_thr;
695 u8 res4[8];
696 u32 fifo_tx_starve;
697 u32 fifo_tx_starve_shutoff;
698 u8 res5[96];
699 u32 tctrl;
700 u32 tstat;
701 u32 dfvlan;
702 u32 tbdlen;
703 u32 txic;
704 u32 tqueue;
705 u8 res7[40];
706 u32 tr03wt;
707 u32 tr47wt;
708 u8 res8[52];
709 u32 tbdbph;
710 u8 res9a[4];
711 u32 tbptr0;
712 u8 res9b[4];
713 u32 tbptr1;
714 u8 res9c[4];
715 u32 tbptr2;
716 u8 res9d[4];
717 u32 tbptr3;
718 u8 res9e[4];
719 u32 tbptr4;
720 u8 res9f[4];
721 u32 tbptr5;
722 u8 res9g[4];
723 u32 tbptr6;
724 u8 res9h[4];
725 u32 tbptr7;
726 u8 res9[64];
727 u32 tbaseh;
728 u32 tbase0;
729 u8 res10a[4];
730 u32 tbase1;
731 u8 res10b[4];
732 u32 tbase2;
733 u8 res10c[4];
734 u32 tbase3;
735 u8 res10d[4];
736 u32 tbase4;
737 u8 res10e[4];
738 u32 tbase5;
739 u8 res10f[4];
740 u32 tbase6;
741 u8 res10g[4];
742 u32 tbase7;
743 u8 res10[192];
744 u32 rctrl;
745 u32 rstat;
746 u8 res12[8];
747 u32 rxic;
748 u32 rqueue;
749 u32 rir0;
750 u32 rir1;
751 u32 rir2;
752 u32 rir3;
753 u8 res13[8];
754 u32 rbifx;
755 u32 rqfar;
756 u32 rqfcr;
757 u32 rqfpr;
758 u32 mrblr;
759 u8 res14[56];
760 u32 rbdbph;
761 u8 res15a[4];
762 u32 rbptr0;
763 u8 res15b[4];
764 u32 rbptr1;
765 u8 res15c[4];
766 u32 rbptr2;
767 u8 res15d[4];
768 u32 rbptr3;
769 u8 res15e[4];
770 u32 rbptr4;
771 u8 res15f[4];
772 u32 rbptr5;
773 u8 res15g[4];
774 u32 rbptr6;
775 u8 res15h[4];
776 u32 rbptr7;
777 u8 res16[64];
778 u32 rbaseh;
779 u32 rbase0;
780 u8 res17a[4];
781 u32 rbase1;
782 u8 res17b[4];
783 u32 rbase2;
784 u8 res17c[4];
785 u32 rbase3;
786 u8 res17d[4];
787 u32 rbase4;
788 u8 res17e[4];
789 u32 rbase5;
790 u8 res17f[4];
791 u32 rbase6;
792 u8 res17g[4];
793 u32 rbase7;
794 u8 res17[192];
795 u32 maccfg1;
796 u32 maccfg2;
797 u32 ipgifg;
798 u32 hafdup;
799 u32 maxfrm;
800 u8 res18[12];
801 u8 gfar_mii_regs[24];
802 u32 ifctrl;
803 u32 ifstat;
804 u32 macstnaddr1;
805 u32 macstnaddr2;
806 u32 mac01addr1;
807 u32 mac01addr2;
808 u32 mac02addr1;
809 u32 mac02addr2;
810 u32 mac03addr1;
811 u32 mac03addr2;
812 u32 mac04addr1;
813 u32 mac04addr2;
814 u32 mac05addr1;
815 u32 mac05addr2;
816 u32 mac06addr1;
817 u32 mac06addr2;
818 u32 mac07addr1;
819 u32 mac07addr2;
820 u32 mac08addr1;
821 u32 mac08addr2;
822 u32 mac09addr1;
823 u32 mac09addr2;
824 u32 mac10addr1;
825 u32 mac10addr2;
826 u32 mac11addr1;
827 u32 mac11addr2;
828 u32 mac12addr1;
829 u32 mac12addr2;
830 u32 mac13addr1;
831 u32 mac13addr2;
832 u32 mac14addr1;
833 u32 mac14addr2;
834 u32 mac15addr1;
835 u32 mac15addr2;
836 u8 res20[192];
837 struct rmon_mib rmon;
838 u32 rrej;
839 u8 res21[188];
840 u32 igaddr0;
841 u32 igaddr1;
842 u32 igaddr2;
843 u32 igaddr3;
844 u32 igaddr4;
845 u32 igaddr5;
846 u32 igaddr6;
847 u32 igaddr7;
848 u8 res22[96];
849 u32 gaddr0;
850 u32 gaddr1;
851 u32 gaddr2;
852 u32 gaddr3;
853 u32 gaddr4;
854 u32 gaddr5;
855 u32 gaddr6;
856 u32 gaddr7;
857 u8 res23a[352];
858 u32 fifocfg;
859 u8 res23b[252];
860 u8 res23c[248];
861 u32 attr;
862 u32 attreli;
863 u32 rqprm0;
864 u32 rqprm1;
865 u32 rqprm2;
866 u32 rqprm3;
867 u32 rqprm4;
868 u32 rqprm5;
869 u32 rqprm6;
870 u32 rqprm7;
871 u8 res24[36];
872 u32 rfbptr0;
873 u8 res24a[4];
874 u32 rfbptr1;
875 u8 res24b[4];
876 u32 rfbptr2;
877 u8 res24c[4];
878 u32 rfbptr3;
879 u8 res24d[4];
880 u32 rfbptr4;
881 u8 res24e[4];
882 u32 rfbptr5;
883 u8 res24f[4];
884 u32 rfbptr6;
885 u8 res24g[4];
886 u32 rfbptr7;
887 u8 res24h[4];
888 u8 res24x[556];
889 u32 isrg0;
890 u32 isrg1;
891 u32 isrg2;
892 u32 isrg3;
893 u8 res25[16];
894 u32 rxic0;
895 u32 rxic1;
896 u32 rxic2;
897 u32 rxic3;
898 u32 rxic4;
899 u32 rxic5;
900 u32 rxic6;
901 u32 rxic7;
902 u8 res26[32];
903 u32 txic0;
904 u32 txic1;
905 u32 txic2;
906 u32 txic3;
907 u32 txic4;
908 u32 txic5;
909 u32 txic6;
910 u32 txic7;
911 u8 res27[208];
912};
913
914
915#define FSL_GIANFAR_DEV_HAS_GIGABIT 0x00000001
916#define FSL_GIANFAR_DEV_HAS_COALESCE 0x00000002
917#define FSL_GIANFAR_DEV_HAS_RMON 0x00000004
918#define FSL_GIANFAR_DEV_HAS_MULTI_INTR 0x00000008
919#define FSL_GIANFAR_DEV_HAS_CSUM 0x00000010
920#define FSL_GIANFAR_DEV_HAS_VLAN 0x00000020
921#define FSL_GIANFAR_DEV_HAS_EXTENDED_HASH 0x00000040
922#define FSL_GIANFAR_DEV_HAS_MAGIC_PACKET 0x00000100
923#define FSL_GIANFAR_DEV_HAS_BD_STASHING 0x00000200
924#define FSL_GIANFAR_DEV_HAS_BUF_STASHING 0x00000400
925#define FSL_GIANFAR_DEV_HAS_TIMER 0x00000800
926#define FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER 0x00001000
927#define FSL_GIANFAR_DEV_HAS_RX_FILER 0x00002000
928
929#if (MAXGROUPS == 2)
930#define DEFAULT_MAPPING 0xAA
931#else
932#define DEFAULT_MAPPING 0xFF
933#endif
934
935#define ISRG_RR0 0x80000000
936#define ISRG_TR0 0x00800000
937
938
939
940
941
942
943enum {
944 SQ_SG_MODE = 0,
945 MQ_MG_MODE
946};
947
948
949
950
951
952
953
954
955
956
957
958
959enum gfar_poll_mode {
960 GFAR_SQ_POLLING = 0,
961 GFAR_MQ_POLLING
962};
963
964
965
966
967struct tx_q_stats {
968 unsigned long tx_packets;
969 unsigned long tx_bytes;
970};
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992struct gfar_priv_tx_q {
993
994 spinlock_t txlock __attribute__ ((aligned (SMP_CACHE_BYTES)));
995 struct txbd8 *tx_bd_base;
996 struct txbd8 *cur_tx;
997 unsigned int num_txbdfree;
998 unsigned short skb_curtx;
999 unsigned short tx_ring_size;
1000 struct tx_q_stats stats;
1001 struct gfar_priv_grp *grp;
1002
1003 struct net_device *dev;
1004 struct sk_buff **tx_skbuff;
1005 struct txbd8 *dirty_tx;
1006 unsigned short skb_dirtytx;
1007 unsigned short qindex;
1008
1009 unsigned int txcoalescing;
1010 unsigned long txic;
1011 dma_addr_t tx_bd_dma_base;
1012};
1013
1014
1015
1016
1017struct rx_q_stats {
1018 unsigned long rx_packets;
1019 unsigned long rx_bytes;
1020 unsigned long rx_dropped;
1021};
1022
1023struct gfar_rx_buff {
1024 dma_addr_t dma;
1025 struct page *page;
1026 unsigned int page_offset;
1027};
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042struct gfar_priv_rx_q {
1043 struct gfar_rx_buff *rx_buff __aligned(SMP_CACHE_BYTES);
1044 struct rxbd8 *rx_bd_base;
1045 struct net_device *ndev;
1046 struct device *dev;
1047 u16 rx_ring_size;
1048 u16 qindex;
1049 struct gfar_priv_grp *grp;
1050 u16 next_to_clean;
1051 u16 next_to_use;
1052 u16 next_to_alloc;
1053 struct sk_buff *skb;
1054 struct rx_q_stats stats;
1055 u32 __iomem *rfbptr;
1056 unsigned char rxcoalescing;
1057 unsigned long rxic;
1058 dma_addr_t rx_bd_dma_base;
1059};
1060
1061enum gfar_irqinfo_id {
1062 GFAR_TX = 0,
1063 GFAR_RX = 1,
1064 GFAR_ER = 2,
1065 GFAR_NUM_IRQS = 3
1066};
1067
1068struct gfar_irqinfo {
1069 unsigned int irq;
1070 char name[GFAR_INT_NAME_MAX];
1071};
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081struct gfar_priv_grp {
1082 spinlock_t grplock __aligned(SMP_CACHE_BYTES);
1083 struct napi_struct napi_rx;
1084 struct napi_struct napi_tx;
1085 struct gfar __iomem *regs;
1086 struct gfar_priv_tx_q *tx_queue;
1087 struct gfar_priv_rx_q *rx_queue;
1088 unsigned int tstat;
1089 unsigned int rstat;
1090
1091 struct gfar_private *priv;
1092 unsigned long num_tx_queues;
1093 unsigned long tx_bit_map;
1094 unsigned long num_rx_queues;
1095 unsigned long rx_bit_map;
1096
1097 struct gfar_irqinfo *irqinfo[GFAR_NUM_IRQS];
1098};
1099
1100#define gfar_irq(grp, ID) \
1101 ((grp)->irqinfo[GFAR_##ID])
1102
1103enum gfar_errata {
1104 GFAR_ERRATA_74 = 0x01,
1105 GFAR_ERRATA_76 = 0x02,
1106 GFAR_ERRATA_A002 = 0x04,
1107 GFAR_ERRATA_12 = 0x08,
1108};
1109
1110enum gfar_dev_state {
1111 GFAR_DOWN = 1,
1112 GFAR_RESETTING
1113};
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124struct gfar_private {
1125 struct device *dev;
1126 struct net_device *ndev;
1127 enum gfar_errata errata;
1128
1129 u16 uses_rxfcb;
1130 u16 padding;
1131 u32 device_flags;
1132
1133
1134 int hwts_rx_en;
1135 int hwts_tx_en;
1136
1137 struct gfar_priv_tx_q *tx_queue[MAX_TX_QS];
1138 struct gfar_priv_rx_q *rx_queue[MAX_RX_QS];
1139 struct gfar_priv_grp gfargrp[MAXGROUPS];
1140
1141 unsigned long state;
1142
1143 unsigned short mode;
1144 unsigned short poll_mode;
1145 unsigned int num_tx_queues;
1146 unsigned int num_rx_queues;
1147 unsigned int num_grps;
1148 int tx_actual_en;
1149
1150
1151 struct gfar_extra_stats extra_stats;
1152
1153
1154 phy_interface_t interface;
1155 struct device_node *phy_node;
1156 struct device_node *tbi_node;
1157 struct mii_bus *mii_bus;
1158 int oldspeed;
1159 int oldduplex;
1160 int oldlink;
1161
1162 uint32_t msg_enable;
1163
1164 struct work_struct reset_task;
1165
1166 struct platform_device *ofdev;
1167 unsigned char
1168 extended_hash:1,
1169 bd_stash_en:1,
1170 rx_filer_enable:1,
1171
1172 prio_sched_en:1,
1173
1174 pause_aneg_en:1,
1175 tx_pause_en:1,
1176 rx_pause_en:1;
1177
1178
1179 unsigned int total_tx_ring_size;
1180 unsigned int total_rx_ring_size;
1181
1182 u32 rqueue;
1183 u32 tqueue;
1184
1185
1186 unsigned int rx_stash_size;
1187 unsigned int rx_stash_index;
1188
1189 u32 cur_filer_idx;
1190
1191
1192 struct ethtool_rx_list rx_list;
1193 struct mutex rx_queue_access;
1194
1195
1196 u32 __iomem *hash_regs[16];
1197 int hash_width;
1198
1199
1200 u16 wol_opts;
1201 u16 wol_supported;
1202
1203
1204 unsigned int ftp_rqfpr[MAX_FILER_IDX + 1];
1205 unsigned int ftp_rqfcr[MAX_FILER_IDX + 1];
1206};
1207
1208
1209static inline int gfar_has_errata(struct gfar_private *priv,
1210 enum gfar_errata err)
1211{
1212 return priv->errata & err;
1213}
1214
1215static inline u32 gfar_read(unsigned __iomem *addr)
1216{
1217 u32 val;
1218 val = ioread32be(addr);
1219 return val;
1220}
1221
1222static inline void gfar_write(unsigned __iomem *addr, u32 val)
1223{
1224 iowrite32be(val, addr);
1225}
1226
1227static inline void gfar_write_filer(struct gfar_private *priv,
1228 unsigned int far, unsigned int fcr, unsigned int fpr)
1229{
1230 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1231
1232 gfar_write(®s->rqfar, far);
1233 gfar_write(®s->rqfcr, fcr);
1234 gfar_write(®s->rqfpr, fpr);
1235}
1236
1237static inline void gfar_read_filer(struct gfar_private *priv,
1238 unsigned int far, unsigned int *fcr, unsigned int *fpr)
1239{
1240 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1241
1242 gfar_write(®s->rqfar, far);
1243 *fcr = gfar_read(®s->rqfcr);
1244 *fpr = gfar_read(®s->rqfpr);
1245}
1246
1247static inline void gfar_write_isrg(struct gfar_private *priv)
1248{
1249 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1250 u32 __iomem *baddr = ®s->isrg0;
1251 u32 isrg = 0;
1252 int grp_idx, i;
1253
1254 for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
1255 struct gfar_priv_grp *grp = &priv->gfargrp[grp_idx];
1256
1257 for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) {
1258 isrg |= (ISRG_RR0 >> i);
1259 }
1260
1261 for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) {
1262 isrg |= (ISRG_TR0 >> i);
1263 }
1264
1265 gfar_write(baddr, isrg);
1266
1267 baddr++;
1268 isrg = 0;
1269 }
1270}
1271
1272static inline int gfar_is_dma_stopped(struct gfar_private *priv)
1273{
1274 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1275
1276 return ((gfar_read(®s->ievent) & (IEVENT_GRSC | IEVENT_GTSC)) ==
1277 (IEVENT_GRSC | IEVENT_GTSC));
1278}
1279
1280static inline int gfar_is_rx_dma_stopped(struct gfar_private *priv)
1281{
1282 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1283
1284 return gfar_read(®s->ievent) & IEVENT_GRSC;
1285}
1286
1287static inline void gfar_wmb(void)
1288{
1289#if defined(CONFIG_PPC)
1290
1291
1292
1293
1294
1295
1296
1297 eieio();
1298#else
1299 wmb();
1300#endif
1301}
1302
1303static inline void gfar_clear_txbd_status(struct txbd8 *bdp)
1304{
1305 u32 lstatus = be32_to_cpu(bdp->lstatus);
1306
1307 lstatus &= BD_LFLAG(TXBD_WRAP);
1308 bdp->lstatus = cpu_to_be32(lstatus);
1309}
1310
1311static inline int gfar_rxbd_unused(struct gfar_priv_rx_q *rxq)
1312{
1313 if (rxq->next_to_clean > rxq->next_to_use)
1314 return rxq->next_to_clean - rxq->next_to_use - 1;
1315
1316 return rxq->rx_ring_size + rxq->next_to_clean - rxq->next_to_use - 1;
1317}
1318
1319static inline u32 gfar_rxbd_dma_lastfree(struct gfar_priv_rx_q *rxq)
1320{
1321 struct rxbd8 *bdp;
1322 u32 bdp_dma;
1323 int i;
1324
1325 i = rxq->next_to_use ? rxq->next_to_use - 1 : rxq->rx_ring_size - 1;
1326 bdp = &rxq->rx_bd_base[i];
1327 bdp_dma = lower_32_bits(rxq->rx_bd_dma_base);
1328 bdp_dma += (uintptr_t)bdp - (uintptr_t)rxq->rx_bd_base;
1329
1330 return bdp_dma;
1331}
1332
1333irqreturn_t gfar_receive(int irq, void *dev_id);
1334int startup_gfar(struct net_device *dev);
1335void stop_gfar(struct net_device *dev);
1336void reset_gfar(struct net_device *dev);
1337void gfar_mac_reset(struct gfar_private *priv);
1338void gfar_halt(struct gfar_private *priv);
1339void gfar_start(struct gfar_private *priv);
1340void gfar_phy_test(struct mii_bus *bus, struct phy_device *phydev, int enable,
1341 u32 regnum, u32 read);
1342void gfar_configure_coalescing_all(struct gfar_private *priv);
1343int gfar_set_features(struct net_device *dev, netdev_features_t features);
1344
1345extern const struct ethtool_ops gfar_ethtool_ops;
1346
1347#define MAX_FILER_CACHE_IDX (2*(MAX_FILER_IDX))
1348
1349#define RQFCR_PID_PRI_MASK 0xFFFFFFF8
1350#define RQFCR_PID_L4P_MASK 0xFFFFFF00
1351#define RQFCR_PID_VID_MASK 0xFFFFF000
1352#define RQFCR_PID_PORT_MASK 0xFFFF0000
1353#define RQFCR_PID_MAC_MASK 0xFF000000
1354
1355struct gfar_mask_entry {
1356 unsigned int mask;
1357 unsigned int start;
1358 unsigned int end;
1359 unsigned int block;
1360};
1361
1362
1363struct gfar_filer_entry {
1364 u32 ctrl;
1365 u32 prop;
1366};
1367
1368
1369
1370struct filer_table {
1371 u32 index;
1372 struct gfar_filer_entry fe[MAX_FILER_CACHE_IDX + 20];
1373};
1374
1375
1376extern int gfar_phc_index;
1377
1378#endif
1379