1/* Intel(R) Gigabit Ethernet Linux driver 2 * Copyright(c) 2007-2014 Intel Corporation. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program; if not, see <http://www.gnu.org/licenses/>. 15 * 16 * The full GNU General Public License is included in this distribution in 17 * the file called "COPYING". 18 * 19 * Contact Information: 20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 22 */ 23 24#ifndef _E1000_DEFINES_H_ 25#define _E1000_DEFINES_H_ 26 27/* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 28#define REQ_TX_DESCRIPTOR_MULTIPLE 8 29#define REQ_RX_DESCRIPTOR_MULTIPLE 8 30 31/* Definitions for power management and wakeup registers */ 32/* Wake Up Control */ 33#define E1000_WUC_PME_EN 0x00000002 /* PME Enable */ 34 35/* Wake Up Filter Control */ 36#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ 37#define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ 38#define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ 39#define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ 40#define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ 41 42/* Extended Device Control */ 43#define E1000_CTRL_EXT_SDP2_DATA 0x00000040 /* Value of SW Defineable Pin 2 */ 44#define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* Value of SW Defineable Pin 3 */ 45#define E1000_CTRL_EXT_SDP2_DIR 0x00000400 /* SDP2 Data direction */ 46#define E1000_CTRL_EXT_SDP3_DIR 0x00000800 /* SDP3 Data direction */ 47 48/* Physical Func Reset Done Indication */ 49#define E1000_CTRL_EXT_PFRSTD 0x00004000 50#define E1000_CTRL_EXT_SDLPE 0X00040000 /* SerDes Low Power Enable */ 51#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 52#define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000 53#define E1000_CTRL_EXT_LINK_MODE_1000BASE_KX 0x00400000 54#define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000 55#define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000 56#define E1000_CTRL_EXT_EIAME 0x01000000 57#define E1000_CTRL_EXT_IRCA 0x00000001 58/* Interrupt delay cancellation */ 59/* Driver loaded bit for FW */ 60#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 61/* Interrupt acknowledge Auto-mask */ 62/* Clear Interrupt timers after IMS clear */ 63/* packet buffer parity error detection enabled */ 64/* descriptor FIFO parity error detection enable */ 65#define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */ 66#define E1000_CTRL_EXT_PHYPDEN 0x00100000 67#define E1000_I2CCMD_REG_ADDR_SHIFT 16 68#define E1000_I2CCMD_PHY_ADDR_SHIFT 24 69#define E1000_I2CCMD_OPCODE_READ 0x08000000 70#define E1000_I2CCMD_OPCODE_WRITE 0x00000000 71#define E1000_I2CCMD_READY 0x20000000 72#define E1000_I2CCMD_ERROR 0x80000000 73#define E1000_I2CCMD_SFP_DATA_ADDR(a) (0x0000 + (a)) 74#define E1000_I2CCMD_SFP_DIAG_ADDR(a) (0x0100 + (a)) 75#define E1000_MAX_SGMII_PHY_REG_ADDR 255 76#define E1000_I2CCMD_PHY_TIMEOUT 200 77#define E1000_IVAR_VALID 0x80 78#define E1000_GPIE_NSICR 0x00000001 79#define E1000_GPIE_MSIX_MODE 0x00000010 80#define E1000_GPIE_EIAME 0x40000000 81#define E1000_GPIE_PBA 0x80000000 82 83/* Receive Descriptor bit definitions */ 84#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ 85#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ 86#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ 87#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 88#define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ 89#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ 90#define E1000_RXD_STAT_TS 0x10000 /* Pkt was time stamped */ 91 92#define E1000_RXDEXT_STATERR_LB 0x00040000 93#define E1000_RXDEXT_STATERR_CE 0x01000000 94#define E1000_RXDEXT_STATERR_SE 0x02000000 95#define E1000_RXDEXT_STATERR_SEQ 0x04000000 96#define E1000_RXDEXT_STATERR_CXE 0x10000000 97#define E1000_RXDEXT_STATERR_TCPE 0x20000000 98#define E1000_RXDEXT_STATERR_IPE 0x40000000 99#define E1000_RXDEXT_STATERR_RXE 0x80000000 100 101/* Same mask, but for extended and packet split descriptors */ 102#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \ 103 E1000_RXDEXT_STATERR_CE | \ 104 E1000_RXDEXT_STATERR_SE | \ 105 E1000_RXDEXT_STATERR_SEQ | \ 106 E1000_RXDEXT_STATERR_CXE | \ 107 E1000_RXDEXT_STATERR_RXE) 108 109#define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 110#define E1000_MRQC_RSS_FIELD_IPV4 0x00020000 111#define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000 112#define E1000_MRQC_RSS_FIELD_IPV6 0x00100000 113#define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 114 115 116/* Management Control */ 117#define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ 118#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ 119#define E1000_MANC_EN_BMC2OS 0x10000000 /* OSBMC is Enabled or not */ 120/* Enable Neighbor Discovery Filtering */ 121#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ 122#define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ 123/* Enable MAC address filtering */ 124#define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 125 126/* Receive Control */ 127#define E1000_RCTL_EN 0x00000002 /* enable */ 128#define E1000_RCTL_SBP 0x00000004 /* store bad packet */ 129#define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */ 130#define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */ 131#define E1000_RCTL_LPE 0x00000020 /* long packet enable */ 132#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ 133#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ 134#define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */ 135#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ 136#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ 137#define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */ 138#define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */ 139#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ 140#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ 141#define E1000_RCTL_DPF 0x00400000 /* Discard Pause Frames */ 142#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ 143#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ 144 145/* Use byte values for the following shift parameters 146 * Usage: 147 * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) & 148 * E1000_PSRCTL_BSIZE0_MASK) | 149 * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) & 150 * E1000_PSRCTL_BSIZE1_MASK) | 151 * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) & 152 * E1000_PSRCTL_BSIZE2_MASK) | 153 * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |; 154 * E1000_PSRCTL_BSIZE3_MASK)) 155 * where value0 = [128..16256], default=256 156 * value1 = [1024..64512], default=4096 157 * value2 = [0..64512], default=4096 158 * value3 = [0..64512], default=0 159 */ 160 161#define E1000_PSRCTL_BSIZE0_MASK 0x0000007F 162#define E1000_PSRCTL_BSIZE1_MASK 0x00003F00 163#define E1000_PSRCTL_BSIZE2_MASK 0x003F0000 164#define E1000_PSRCTL_BSIZE3_MASK 0x3F000000 165 166#define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */ 167#define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */ 168#define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */ 169#define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */ 170 171/* SWFW_SYNC Definitions */ 172#define E1000_SWFW_EEP_SM 0x1 173#define E1000_SWFW_PHY0_SM 0x2 174#define E1000_SWFW_PHY1_SM 0x4 175#define E1000_SWFW_PHY2_SM 0x20 176#define E1000_SWFW_PHY3_SM 0x40 177 178/* FACTPS Definitions */ 179/* Device Control */ 180#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ 181#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */ 182#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ 183#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ 184#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ 185#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ 186#define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ 187#define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ 188#define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ 189#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ 190#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ 191/* Defined polarity of Dock/Undock indication in SDP[0] */ 192/* Reset both PHY ports, through PHYRST_N pin */ 193/* enable link status from external LINK_0 and LINK_1 pins */ 194#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ 195#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ 196#define E1000_CTRL_SDP0_DIR 0x00400000 /* SDP0 Data direction */ 197#define E1000_CTRL_SDP1_DIR 0x00800000 /* SDP1 Data direction */ 198#define E1000_CTRL_RST 0x04000000 /* Global reset */ 199#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ 200#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ 201#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ 202#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ 203/* Initiate an interrupt to manageability engine */ 204#define E1000_CTRL_I2C_ENA 0x02000000 /* I2C enable */ 205 206/* Bit definitions for the Management Data IO (MDIO) and Management Data 207 * Clock (MDC) pins in the Device Control Register. 208 */ 209 210#define E1000_CONNSW_ENRGSRC 0x4 211#define E1000_CONNSW_PHYSD 0x400 212#define E1000_CONNSW_PHY_PDN 0x800 213#define E1000_CONNSW_SERDESD 0x200 214#define E1000_CONNSW_AUTOSENSE_CONF 0x2 215#define E1000_CONNSW_AUTOSENSE_EN 0x1 216#define E1000_PCS_CFG_PCS_EN 8 217#define E1000_PCS_LCTL_FLV_LINK_UP 1 218#define E1000_PCS_LCTL_FSV_100 2 219#define E1000_PCS_LCTL_FSV_1000 4 220#define E1000_PCS_LCTL_FDV_FULL 8 221#define E1000_PCS_LCTL_FSD 0x10 222#define E1000_PCS_LCTL_FORCE_LINK 0x20 223#define E1000_PCS_LCTL_FORCE_FCTRL 0x80 224#define E1000_PCS_LCTL_AN_ENABLE 0x10000 225#define E1000_PCS_LCTL_AN_RESTART 0x20000 226#define E1000_PCS_LCTL_AN_TIMEOUT 0x40000 227#define E1000_ENABLE_SERDES_LOOPBACK 0x0410 228 229#define E1000_PCS_LSTS_LINK_OK 1 230#define E1000_PCS_LSTS_SPEED_100 2 231#define E1000_PCS_LSTS_SPEED_1000 4 232#define E1000_PCS_LSTS_DUPLEX_FULL 8 233#define E1000_PCS_LSTS_SYNK_OK 0x10 234 235/* Device Status */ 236#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ 237#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ 238#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ 239#define E1000_STATUS_FUNC_SHIFT 2 240#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ 241#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ 242#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ 243#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ 244/* Change in Dock/Undock state. Clear on write '0'. */ 245/* Status of Master requests. */ 246#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 247/* BMC external code execution disabled */ 248 249#define E1000_STATUS_2P5_SKU 0x00001000 /* Val of 2.5GBE SKU strap */ 250#define E1000_STATUS_2P5_SKU_OVER 0x00002000 /* Val of 2.5GBE SKU Over */ 251/* Constants used to intrepret the masked PCI-X bus speed. */ 252 253#define SPEED_10 10 254#define SPEED_100 100 255#define SPEED_1000 1000 256#define SPEED_2500 2500 257#define HALF_DUPLEX 1 258#define FULL_DUPLEX 2 259 260 261#define ADVERTISE_10_HALF 0x0001 262#define ADVERTISE_10_FULL 0x0002 263#define ADVERTISE_100_HALF 0x0004 264#define ADVERTISE_100_FULL 0x0008 265#define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */ 266#define ADVERTISE_1000_FULL 0x0020 267 268/* 1000/H is not supported, nor spec-compliant. */ 269#define E1000_ALL_SPEED_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 270 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 271 ADVERTISE_1000_FULL) 272#define E1000_ALL_NOT_GIG (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 273 ADVERTISE_100_HALF | ADVERTISE_100_FULL) 274#define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL) 275#define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL) 276#define E1000_ALL_FULL_DUPLEX (ADVERTISE_10_FULL | ADVERTISE_100_FULL | \ 277 ADVERTISE_1000_FULL) 278#define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF) 279 280#define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX 281 282/* LED Control */ 283#define E1000_LEDCTL_LED0_MODE_SHIFT 0 284#define E1000_LEDCTL_LED0_BLINK 0x00000080 285#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F 286#define E1000_LEDCTL_LED0_IVRT 0x00000040 287 288#define E1000_LEDCTL_MODE_LED_ON 0xE 289#define E1000_LEDCTL_MODE_LED_OFF 0xF 290 291/* Transmit Descriptor bit definitions */ 292#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 293#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 294#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ 295#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 296#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ 297#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ 298#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 299/* Extended desc bits for Linksec and timesync */ 300 301/* Transmit Control */ 302#define E1000_TCTL_EN 0x00000002 /* enable tx */ 303#define E1000_TCTL_PSP 0x00000008 /* pad short packets */ 304#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ 305#define E1000_TCTL_COLD 0x003ff000 /* collision distance */ 306#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ 307 308/* DMA Coalescing register fields */ 309#define E1000_DMACR_DMACWT_MASK 0x00003FFF /* DMA Coal Watchdog Timer */ 310#define E1000_DMACR_DMACTHR_MASK 0x00FF0000 /* DMA Coal Rx Threshold */ 311#define E1000_DMACR_DMACTHR_SHIFT 16 312#define E1000_DMACR_DMAC_LX_MASK 0x30000000 /* Lx when no PCIe trans */ 313#define E1000_DMACR_DMAC_LX_SHIFT 28 314#define E1000_DMACR_DMAC_EN 0x80000000 /* Enable DMA Coalescing */ 315/* DMA Coalescing BMC-to-OS Watchdog Enable */ 316#define E1000_DMACR_DC_BMC2OSW_EN 0x00008000 317 318#define E1000_DMCTXTH_DMCTTHR_MASK 0x00000FFF /* DMA Coal Tx Threshold */ 319 320#define E1000_DMCTLX_TTLX_MASK 0x00000FFF /* Time to LX request */ 321 322#define E1000_DMCRTRH_UTRESH_MASK 0x0007FFFF /* Rx Traffic Rate Thresh */ 323#define E1000_DMCRTRH_LRPRCW 0x80000000 /* Rx pkt rate curr window */ 324 325#define E1000_DMCCNT_CCOUNT_MASK 0x01FFFFFF /* DMA Coal Rx Current Cnt */ 326 327#define E1000_FCRTC_RTH_COAL_MASK 0x0003FFF0 /* FC Rx Thresh High val */ 328#define E1000_FCRTC_RTH_COAL_SHIFT 4 329#define E1000_PCIEMISC_LX_DECISION 0x00000080 /* Lx power decision */ 330 331/* Timestamp in Rx buffer */ 332#define E1000_RXPBS_CFG_TS_EN 0x80000000 333 334#define I210_RXPBSIZE_DEFAULT 0x000000A2 /* RXPBSIZE default */ 335#define I210_TXPBSIZE_DEFAULT 0x04000014 /* TXPBSIZE default */ 336 337/* SerDes Control */ 338#define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400 339 340/* Receive Checksum Control */ 341#define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */ 342#define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ 343#define E1000_RXCSUM_CRCOFL 0x00000800 /* CRC32 offload enable */ 344#define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ 345 346/* Header split receive */ 347#define E1000_RFCTL_IPV6_EX_DIS 0x00010000 348#define E1000_RFCTL_LEF 0x00040000 349 350/* Collision related configuration parameters */ 351#define E1000_COLLISION_THRESHOLD 15 352#define E1000_CT_SHIFT 4 353#define E1000_COLLISION_DISTANCE 63 354#define E1000_COLD_SHIFT 12 355 356/* Ethertype field values */ 357#define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */ 358 359/* As per the EAS the maximum supported size is 9.5KB (9728 bytes) */ 360#define MAX_JUMBO_FRAME_SIZE 0x2600 361 362/* PBA constants */ 363#define E1000_PBA_34K 0x0022 364#define E1000_PBA_64K 0x0040 /* 64KB */ 365 366/* SW Semaphore Register */ 367#define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ 368#define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ 369 370/* Interrupt Cause Read */ 371#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ 372#define E1000_ICR_LSC 0x00000004 /* Link Status Change */ 373#define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */ 374#define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */ 375#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */ 376#define E1000_ICR_VMMB 0x00000100 /* VM MB event */ 377#define E1000_ICR_TS 0x00080000 /* Time Sync Interrupt */ 378#define E1000_ICR_DRSTA 0x40000000 /* Device Reset Asserted */ 379/* If this bit asserted, the driver should claim the interrupt */ 380#define E1000_ICR_INT_ASSERTED 0x80000000 381/* LAN connected device generates an interrupt */ 382#define E1000_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */ 383 384/* Extended Interrupt Cause Read */ 385#define E1000_EICR_RX_QUEUE0 0x00000001 /* Rx Queue 0 Interrupt */ 386#define E1000_EICR_RX_QUEUE1 0x00000002 /* Rx Queue 1 Interrupt */ 387#define E1000_EICR_RX_QUEUE2 0x00000004 /* Rx Queue 2 Interrupt */ 388#define E1000_EICR_RX_QUEUE3 0x00000008 /* Rx Queue 3 Interrupt */ 389#define E1000_EICR_TX_QUEUE0 0x00000100 /* Tx Queue 0 Interrupt */ 390#define E1000_EICR_TX_QUEUE1 0x00000200 /* Tx Queue 1 Interrupt */ 391#define E1000_EICR_TX_QUEUE2 0x00000400 /* Tx Queue 2 Interrupt */ 392#define E1000_EICR_TX_QUEUE3 0x00000800 /* Tx Queue 3 Interrupt */ 393#define E1000_EICR_OTHER 0x80000000 /* Interrupt Cause Active */ 394/* TCP Timer */ 395 396/* This defines the bits that are set in the Interrupt Mask 397 * Set/Read Register. Each bit is documented below: 398 * o RXT0 = Receiver Timer Interrupt (ring 0) 399 * o TXDW = Transmit Descriptor Written Back 400 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) 401 * o RXSEQ = Receive Sequence Error 402 * o LSC = Link Status Change 403 */ 404#define IMS_ENABLE_MASK ( \ 405 E1000_IMS_RXT0 | \ 406 E1000_IMS_TXDW | \ 407 E1000_IMS_RXDMT0 | \ 408 E1000_IMS_RXSEQ | \ 409 E1000_IMS_LSC | \ 410 E1000_IMS_DOUTSYNC) 411 412/* Interrupt Mask Set */ 413#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 414#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */ 415#define E1000_IMS_VMMB E1000_ICR_VMMB /* Mail box activity */ 416#define E1000_IMS_TS E1000_ICR_TS /* Time Sync Interrupt */ 417#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ 418#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 419#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ 420#define E1000_IMS_DRSTA E1000_ICR_DRSTA /* Device Reset Asserted */ 421#define E1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */ 422 423/* Extended Interrupt Mask Set */ 424#define E1000_EIMS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */ 425 426/* Interrupt Cause Set */ 427#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ 428#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 429#define E1000_ICS_DRSTA E1000_ICR_DRSTA /* Device Reset Aserted */ 430 431/* Extended Interrupt Cause Set */ 432/* E1000_EITR_CNT_IGNR is only for 82576 and newer */ 433#define E1000_EITR_CNT_IGNR 0x80000000 /* Don't reset counters on write */ 434 435 436/* Transmit Descriptor Control */ 437/* Enable the counting of descriptors still to be processed. */ 438 439/* Flow Control Constants */ 440#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001 441#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 442#define FLOW_CONTROL_TYPE 0x8808 443 444/* Transmit Config Word */ 445#define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */ 446#define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */ 447 448/* 802.1q VLAN Packet Size */ 449#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMA'd) */ 450#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ 451 452/* Receive Address */ 453/* Number of high/low register pairs in the RAR. The RAR (Receive Address 454 * Registers) holds the directed and multicast addresses that we monitor. 455 * Technically, we have 16 spots. However, we reserve one of these spots 456 * (RAR[15]) for our directed address used by controllers with 457 * manageability enabled, allowing us room for 15 multicast addresses. 458 */ 459#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ 460#define E1000_RAL_MAC_ADDR_LEN 4 461#define E1000_RAH_MAC_ADDR_LEN 2 462#define E1000_RAH_POOL_MASK 0x03FC0000 463#define E1000_RAH_POOL_1 0x00040000 464 465/* Error Codes */ 466#define E1000_ERR_NVM 1 467#define E1000_ERR_PHY 2 468#define E1000_ERR_CONFIG 3 469#define E1000_ERR_PARAM 4 470#define E1000_ERR_MAC_INIT 5 471#define E1000_ERR_RESET 9 472#define E1000_ERR_MASTER_REQUESTS_PENDING 10 473#define E1000_BLK_PHY_RESET 12 474#define E1000_ERR_SWFW_SYNC 13 475#define E1000_NOT_IMPLEMENTED 14 476#define E1000_ERR_MBX 15 477#define E1000_ERR_INVALID_ARGUMENT 16 478#define E1000_ERR_NO_SPACE 17 479#define E1000_ERR_NVM_PBA_SECTION 18 480#define E1000_ERR_INVM_VALUE_NOT_FOUND 19 481#define E1000_ERR_I2C 20 482 483/* Loop limit on how long we wait for auto-negotiation to complete */ 484#define COPPER_LINK_UP_LIMIT 10 485#define PHY_AUTO_NEG_LIMIT 45 486#define PHY_FORCE_LIMIT 20 487/* Number of 100 microseconds we wait for PCI Express master disable */ 488#define MASTER_DISABLE_TIMEOUT 800 489/* Number of milliseconds we wait for PHY configuration done after MAC reset */ 490#define PHY_CFG_TIMEOUT 100 491/* Number of 2 milliseconds we wait for acquiring MDIO ownership. */ 492/* Number of milliseconds for NVM auto read done after MAC reset. */ 493#define AUTO_READ_DONE_TIMEOUT 10 494 495/* Flow Control */ 496#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ 497 498#define E1000_TSYNCTXCTL_VALID 0x00000001 /* tx timestamp valid */ 499#define E1000_TSYNCTXCTL_ENABLED 0x00000010 /* enable tx timestampping */ 500 501#define E1000_TSYNCRXCTL_VALID 0x00000001 /* rx timestamp valid */ 502#define E1000_TSYNCRXCTL_TYPE_MASK 0x0000000E /* rx type mask */ 503#define E1000_TSYNCRXCTL_TYPE_L2_V2 0x00 504#define E1000_TSYNCRXCTL_TYPE_L4_V1 0x02 505#define E1000_TSYNCRXCTL_TYPE_L2_L4_V2 0x04 506#define E1000_TSYNCRXCTL_TYPE_ALL 0x08 507#define E1000_TSYNCRXCTL_TYPE_EVENT_V2 0x0A 508#define E1000_TSYNCRXCTL_ENABLED 0x00000010 /* enable rx timestampping */ 509 510#define E1000_TSYNCRXCFG_PTP_V1_CTRLT_MASK 0x000000FF 511#define E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE 0x00 512#define E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE 0x01 513#define E1000_TSYNCRXCFG_PTP_V1_FOLLOWUP_MESSAGE 0x02 514#define E1000_TSYNCRXCFG_PTP_V1_DELAY_RESP_MESSAGE 0x03 515#define E1000_TSYNCRXCFG_PTP_V1_MANAGEMENT_MESSAGE 0x04 516 517#define E1000_TSYNCRXCFG_PTP_V2_MSGID_MASK 0x00000F00 518#define E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE 0x0000 519#define E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE 0x0100 520#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_REQ_MESSAGE 0x0200 521#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_RESP_MESSAGE 0x0300 522#define E1000_TSYNCRXCFG_PTP_V2_FOLLOWUP_MESSAGE 0x0800 523#define E1000_TSYNCRXCFG_PTP_V2_DELAY_RESP_MESSAGE 0x0900 524#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_FOLLOWUP_MESSAGE 0x0A00 525#define E1000_TSYNCRXCFG_PTP_V2_ANNOUNCE_MESSAGE 0x0B00 526#define E1000_TSYNCRXCFG_PTP_V2_SIGNALLING_MESSAGE 0x0C00 527#define E1000_TSYNCRXCFG_PTP_V2_MANAGEMENT_MESSAGE 0x0D00 528 529#define E1000_TIMINCA_16NS_SHIFT 24 530 531/* Time Sync Interrupt Cause/Mask Register Bits */ 532 533#define TSINTR_SYS_WRAP BIT(0) /* SYSTIM Wrap around. */ 534#define TSINTR_TXTS BIT(1) /* Transmit Timestamp. */ 535#define TSINTR_RXTS BIT(2) /* Receive Timestamp. */ 536#define TSINTR_TT0 BIT(3) /* Target Time 0 Trigger. */ 537#define TSINTR_TT1 BIT(4) /* Target Time 1 Trigger. */ 538#define TSINTR_AUTT0 BIT(5) /* Auxiliary Timestamp 0 Taken. */ 539#define TSINTR_AUTT1 BIT(6) /* Auxiliary Timestamp 1 Taken. */ 540#define TSINTR_TADJ BIT(7) /* Time Adjust Done. */ 541 542#define TSYNC_INTERRUPTS TSINTR_TXTS 543#define E1000_TSICR_TXTS TSINTR_TXTS 544 545/* TSAUXC Configuration Bits */ 546#define TSAUXC_EN_TT0 BIT(0) /* Enable target time 0. */ 547#define TSAUXC_EN_TT1 BIT(1) /* Enable target time 1. */ 548#define TSAUXC_EN_CLK0 BIT(2) /* Enable Configurable Frequency Clock 0. */ 549#define TSAUXC_SAMP_AUT0 BIT(3) /* Latch SYSTIML/H into AUXSTMPL/0. */ 550#define TSAUXC_ST0 BIT(4) /* Start Clock 0 Toggle on Target Time 0. */ 551#define TSAUXC_EN_CLK1 BIT(5) /* Enable Configurable Frequency Clock 1. */ 552#define TSAUXC_SAMP_AUT1 BIT(6) /* Latch SYSTIML/H into AUXSTMPL/1. */ 553#define TSAUXC_ST1 BIT(7) /* Start Clock 1 Toggle on Target Time 1. */ 554#define TSAUXC_EN_TS0 BIT(8) /* Enable hardware timestamp 0. */ 555#define TSAUXC_AUTT0 BIT(9) /* Auxiliary Timestamp Taken. */ 556#define TSAUXC_EN_TS1 BIT(10) /* Enable hardware timestamp 0. */ 557#define TSAUXC_AUTT1 BIT(11) /* Auxiliary Timestamp Taken. */ 558#define TSAUXC_PLSG BIT(17) /* Generate a pulse. */ 559#define TSAUXC_DISABLE BIT(31) /* Disable SYSTIM Count Operation. */ 560 561/* SDP Configuration Bits */ 562#define AUX0_SEL_SDP0 (0u << 0) /* Assign SDP0 to auxiliary time stamp 0. */ 563#define AUX0_SEL_SDP1 (1u << 0) /* Assign SDP1 to auxiliary time stamp 0. */ 564#define AUX0_SEL_SDP2 (2u << 0) /* Assign SDP2 to auxiliary time stamp 0. */ 565#define AUX0_SEL_SDP3 (3u << 0) /* Assign SDP3 to auxiliary time stamp 0. */ 566#define AUX0_TS_SDP_EN (1u << 2) /* Enable auxiliary time stamp trigger 0. */ 567#define AUX1_SEL_SDP0 (0u << 3) /* Assign SDP0 to auxiliary time stamp 1. */ 568#define AUX1_SEL_SDP1 (1u << 3) /* Assign SDP1 to auxiliary time stamp 1. */ 569#define AUX1_SEL_SDP2 (2u << 3) /* Assign SDP2 to auxiliary time stamp 1. */ 570#define AUX1_SEL_SDP3 (3u << 3) /* Assign SDP3 to auxiliary time stamp 1. */ 571#define AUX1_TS_SDP_EN (1u << 5) /* Enable auxiliary time stamp trigger 1. */ 572#define TS_SDP0_SEL_TT0 (0u << 6) /* Target time 0 is output on SDP0. */ 573#define TS_SDP0_SEL_TT1 (1u << 6) /* Target time 1 is output on SDP0. */ 574#define TS_SDP0_SEL_FC0 (2u << 6) /* Freq clock 0 is output on SDP0. */ 575#define TS_SDP0_SEL_FC1 (3u << 6) /* Freq clock 1 is output on SDP0. */ 576#define TS_SDP0_EN (1u << 8) /* SDP0 is assigned to Tsync. */ 577#define TS_SDP1_SEL_TT0 (0u << 9) /* Target time 0 is output on SDP1. */ 578#define TS_SDP1_SEL_TT1 (1u << 9) /* Target time 1 is output on SDP1. */ 579#define TS_SDP1_SEL_FC0 (2u << 9) /* Freq clock 0 is output on SDP1. */ 580#define TS_SDP1_SEL_FC1 (3u << 9) /* Freq clock 1 is output on SDP1. */ 581#define TS_SDP1_EN (1u << 11) /* SDP1 is assigned to Tsync. */ 582#define TS_SDP2_SEL_TT0 (0u << 12) /* Target time 0 is output on SDP2. */ 583#define TS_SDP2_SEL_TT1 (1u << 12) /* Target time 1 is output on SDP2. */ 584#define TS_SDP2_SEL_FC0 (2u << 12) /* Freq clock 0 is output on SDP2. */ 585#define TS_SDP2_SEL_FC1 (3u << 12) /* Freq clock 1 is output on SDP2. */ 586#define TS_SDP2_EN (1u << 14) /* SDP2 is assigned to Tsync. */ 587#define TS_SDP3_SEL_TT0 (0u << 15) /* Target time 0 is output on SDP3. */ 588#define TS_SDP3_SEL_TT1 (1u << 15) /* Target time 1 is output on SDP3. */ 589#define TS_SDP3_SEL_FC0 (2u << 15) /* Freq clock 0 is output on SDP3. */ 590#define TS_SDP3_SEL_FC1 (3u << 15) /* Freq clock 1 is output on SDP3. */ 591#define TS_SDP3_EN (1u << 17) /* SDP3 is assigned to Tsync. */ 592 593#define E1000_MDICNFG_EXT_MDIO 0x80000000 /* MDI ext/int destination */ 594#define E1000_MDICNFG_COM_MDIO 0x40000000 /* MDI shared w/ lan 0 */ 595#define E1000_MDICNFG_PHY_MASK 0x03E00000 596#define E1000_MDICNFG_PHY_SHIFT 21 597 598#define E1000_MEDIA_PORT_COPPER 1 599#define E1000_MEDIA_PORT_OTHER 2 600#define E1000_M88E1112_AUTO_COPPER_SGMII 0x2 601#define E1000_M88E1112_AUTO_COPPER_BASEX 0x3 602#define E1000_M88E1112_STATUS_LINK 0x0004 /* Interface Link Bit */ 603#define E1000_M88E1112_MAC_CTRL_1 0x10 604#define E1000_M88E1112_MAC_CTRL_1_MODE_MASK 0x0380 /* Mode Select */ 605#define E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT 7 606#define E1000_M88E1112_PAGE_ADDR 0x16 607#define E1000_M88E1112_STATUS 0x01 608#define E1000_M88E1512_CFG_REG_1 0x0010 609#define E1000_M88E1512_CFG_REG_2 0x0011 610#define E1000_M88E1512_CFG_REG_3 0x0007 611#define E1000_M88E1512_MODE 0x0014 612 613/* PCI Express Control */ 614#define E1000_GCR_CMPL_TMOUT_MASK 0x0000F000 615#define E1000_GCR_CMPL_TMOUT_10ms 0x00001000 616#define E1000_GCR_CMPL_TMOUT_RESEND 0x00010000 617#define E1000_GCR_CAP_VER2 0x00040000 618 619/* mPHY Address Control and Data Registers */ 620#define E1000_MPHY_ADDR_CTL 0x0024 /* mPHY Address Control Register */ 621#define E1000_MPHY_ADDR_CTL_OFFSET_MASK 0xFFFF0000 622#define E1000_MPHY_DATA 0x0E10 /* mPHY Data Register */ 623 624/* mPHY PCS CLK Register */ 625#define E1000_MPHY_PCS_CLK_REG_OFFSET 0x0004 /* mPHY PCS CLK AFE CSR Offset */ 626/* mPHY Near End Digital Loopback Override Bit */ 627#define E1000_MPHY_PCS_CLK_REG_DIGINELBEN 0x10 628 629#define E1000_PCS_LCTL_FORCE_FCTRL 0x80 630#define E1000_PCS_LSTS_AN_COMPLETE 0x10000 631 632/* PHY Control Register */ 633#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ 634#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ 635#define MII_CR_POWER_DOWN 0x0800 /* Power down */ 636#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ 637#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ 638#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ 639#define MII_CR_SPEED_1000 0x0040 640#define MII_CR_SPEED_100 0x2000 641#define MII_CR_SPEED_10 0x0000 642 643/* PHY Status Register */ 644#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ 645#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ 646 647/* Autoneg Advertisement Register */ 648#define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ 649#define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ 650#define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ 651#define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ 652#define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */ 653#define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ 654 655/* Link Partner Ability Register (Base Page) */ 656#define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */ 657#define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */ 658 659/* Autoneg Expansion Register */ 660 661/* 1000BASE-T Control Register */ 662#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ 663#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ 664#define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */ 665 /* 0=Configure PHY as Slave */ 666#define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */ 667 /* 0=Automatic Master/Slave config */ 668 669/* 1000BASE-T Status Register */ 670#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ 671#define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ 672 673 674/* PHY 1000 MII Register/Bit Definitions */ 675/* PHY Registers defined by IEEE */ 676#define PHY_CONTROL 0x00 /* Control Register */ 677#define PHY_STATUS 0x01 /* Status Register */ 678#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ 679#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ 680#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ 681#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ 682#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ 683#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ 684 685/* NVM Control */ 686#define E1000_EECD_SK 0x00000001 /* NVM Clock */ 687#define E1000_EECD_CS 0x00000002 /* NVM Chip Select */ 688#define E1000_EECD_DI 0x00000004 /* NVM Data In */ 689#define E1000_EECD_DO 0x00000008 /* NVM Data Out */ 690#define E1000_EECD_REQ 0x00000040 /* NVM Access Request */ 691#define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */ 692#define E1000_EECD_PRES 0x00000100 /* NVM Present */ 693/* NVM Addressing bits based on type 0=small, 1=large */ 694#define E1000_EECD_ADDR_BITS 0x00000400 695#define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */ 696#define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */ 697#define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */ 698#define E1000_EECD_SIZE_EX_SHIFT 11 699#define E1000_EECD_FLUPD_I210 0x00800000 /* Update FLASH */ 700#define E1000_EECD_FLUDONE_I210 0x04000000 /* Update FLASH done*/ 701#define E1000_EECD_FLASH_DETECTED_I210 0x00080000 /* FLASH detected */ 702#define E1000_FLUDONE_ATTEMPTS 20000 703#define E1000_EERD_EEWR_MAX_COUNT 512 /* buffered EEPROM words rw */ 704#define E1000_I210_FIFO_SEL_RX 0x00 705#define E1000_I210_FIFO_SEL_TX_QAV(_i) (0x02 + (_i)) 706#define E1000_I210_FIFO_SEL_TX_LEGACY E1000_I210_FIFO_SEL_TX_QAV(0) 707#define E1000_I210_FIFO_SEL_BMC2OS_TX 0x06 708#define E1000_I210_FIFO_SEL_BMC2OS_RX 0x01 709#define E1000_I210_FLASH_SECTOR_SIZE 0x1000 /* 4KB FLASH sector unit size */ 710/* Secure FLASH mode requires removing MSb */ 711#define E1000_I210_FW_PTR_MASK 0x7FFF 712/* Firmware code revision field word offset*/ 713#define E1000_I210_FW_VER_OFFSET 328 714#define E1000_EECD_FLUPD_I210 0x00800000 /* Update FLASH */ 715#define E1000_EECD_FLUDONE_I210 0x04000000 /* Update FLASH done*/ 716#define E1000_FLUDONE_ATTEMPTS 20000 717#define E1000_EERD_EEWR_MAX_COUNT 512 /* buffered EEPROM words rw */ 718#define E1000_I210_FIFO_SEL_RX 0x00 719#define E1000_I210_FIFO_SEL_TX_QAV(_i) (0x02 + (_i)) 720#define E1000_I210_FIFO_SEL_TX_LEGACY E1000_I210_FIFO_SEL_TX_QAV(0) 721#define E1000_I210_FIFO_SEL_BMC2OS_TX 0x06 722#define E1000_I210_FIFO_SEL_BMC2OS_RX 0x01 723 724 725/* Offset to data in NVM read/write registers */ 726#define E1000_NVM_RW_REG_DATA 16 727#define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ 728#define E1000_NVM_RW_REG_START 1 /* Start operation */ 729#define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ 730#define E1000_NVM_POLL_READ 0 /* Flag for polling for read complete */ 731 732/* NVM Word Offsets */ 733#define NVM_COMPAT 0x0003 734#define NVM_ID_LED_SETTINGS 0x0004 /* SERDES output amplitude */ 735#define NVM_VERSION 0x0005 736#define NVM_INIT_CONTROL2_REG 0x000F 737#define NVM_INIT_CONTROL3_PORT_B 0x0014 738#define NVM_INIT_CONTROL3_PORT_A 0x0024 739#define NVM_ALT_MAC_ADDR_PTR 0x0037 740#define NVM_CHECKSUM_REG 0x003F 741#define NVM_COMPATIBILITY_REG_3 0x0003 742#define NVM_COMPATIBILITY_BIT_MASK 0x8000 743#define NVM_MAC_ADDR 0x0000 744#define NVM_SUB_DEV_ID 0x000B 745#define NVM_SUB_VEN_ID 0x000C 746#define NVM_DEV_ID 0x000D 747#define NVM_VEN_ID 0x000E 748#define NVM_INIT_CTRL_2 0x000F 749#define NVM_INIT_CTRL_4 0x0013 750#define NVM_LED_1_CFG 0x001C 751#define NVM_LED_0_2_CFG 0x001F 752#define NVM_ETRACK_WORD 0x0042 753#define NVM_ETRACK_HIWORD 0x0043 754#define NVM_COMB_VER_OFF 0x0083 755#define NVM_COMB_VER_PTR 0x003d 756 757/* NVM version defines */ 758#define NVM_MAJOR_MASK 0xF000 759#define NVM_MINOR_MASK 0x0FF0 760#define NVM_IMAGE_ID_MASK 0x000F 761#define NVM_COMB_VER_MASK 0x00FF 762#define NVM_MAJOR_SHIFT 12 763#define NVM_MINOR_SHIFT 4 764#define NVM_COMB_VER_SHFT 8 765#define NVM_VER_INVALID 0xFFFF 766#define NVM_ETRACK_SHIFT 16 767#define NVM_ETRACK_VALID 0x8000 768#define NVM_NEW_DEC_MASK 0x0F00 769#define NVM_HEX_CONV 16 770#define NVM_HEX_TENS 10 771 772#define NVM_ETS_CFG 0x003E 773#define NVM_ETS_LTHRES_DELTA_MASK 0x07C0 774#define NVM_ETS_LTHRES_DELTA_SHIFT 6 775#define NVM_ETS_TYPE_MASK 0x0038 776#define NVM_ETS_TYPE_SHIFT 3 777#define NVM_ETS_TYPE_EMC 0x000 778#define NVM_ETS_NUM_SENSORS_MASK 0x0007 779#define NVM_ETS_DATA_LOC_MASK 0x3C00 780#define NVM_ETS_DATA_LOC_SHIFT 10 781#define NVM_ETS_DATA_INDEX_MASK 0x0300 782#define NVM_ETS_DATA_INDEX_SHIFT 8 783#define NVM_ETS_DATA_HTHRESH_MASK 0x00FF 784 785#define E1000_NVM_CFG_DONE_PORT_0 0x040000 /* MNG config cycle done */ 786#define E1000_NVM_CFG_DONE_PORT_1 0x080000 /* ...for second port */ 787#define E1000_NVM_CFG_DONE_PORT_2 0x100000 /* ...for third port */ 788#define E1000_NVM_CFG_DONE_PORT_3 0x200000 /* ...for fourth port */ 789 790#define NVM_82580_LAN_FUNC_OFFSET(a) (a ? (0x40 + (0x40 * a)) : 0) 791 792/* Mask bits for fields in Word 0x24 of the NVM */ 793#define NVM_WORD24_COM_MDIO 0x0008 /* MDIO interface shared */ 794#define NVM_WORD24_EXT_MDIO 0x0004 /* MDIO accesses routed external */ 795 796/* Mask bits for fields in Word 0x0f of the NVM */ 797#define NVM_WORD0F_PAUSE_MASK 0x3000 798#define NVM_WORD0F_ASM_DIR 0x2000 799 800/* Mask bits for fields in Word 0x1a of the NVM */ 801 802/* length of string needed to store part num */ 803#define E1000_PBANUM_LENGTH 11 804 805/* For checksumming, the sum of all words in the NVM should equal 0xBABA. */ 806#define NVM_SUM 0xBABA 807 808#define NVM_PBA_OFFSET_0 8 809#define NVM_PBA_OFFSET_1 9 810#define NVM_RESERVED_WORD 0xFFFF 811#define NVM_PBA_PTR_GUARD 0xFAFA 812#define NVM_WORD_SIZE_BASE_SHIFT 6 813 814/* NVM Commands - Microwire */ 815 816/* NVM Commands - SPI */ 817#define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ 818#define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */ 819#define NVM_READ_OPCODE_SPI 0x03 /* NVM read opcode */ 820#define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */ 821#define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */ 822#define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */ 823 824/* SPI NVM Status Register */ 825#define NVM_STATUS_RDY_SPI 0x01 826 827/* Word definitions for ID LED Settings */ 828#define ID_LED_RESERVED_0000 0x0000 829#define ID_LED_RESERVED_FFFF 0xFFFF 830#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ 831 (ID_LED_OFF1_OFF2 << 8) | \ 832 (ID_LED_DEF1_DEF2 << 4) | \ 833 (ID_LED_DEF1_DEF2)) 834#define ID_LED_DEF1_DEF2 0x1 835#define ID_LED_DEF1_ON2 0x2 836#define ID_LED_DEF1_OFF2 0x3 837#define ID_LED_ON1_DEF2 0x4 838#define ID_LED_ON1_ON2 0x5 839#define ID_LED_ON1_OFF2 0x6 840#define ID_LED_OFF1_DEF2 0x7 841#define ID_LED_OFF1_ON2 0x8 842#define ID_LED_OFF1_OFF2 0x9 843 844#define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF 845#define IGP_ACTIVITY_LED_ENABLE 0x0300 846#define IGP_LED3_MODE 0x07000000 847 848/* PCI/PCI-X/PCI-EX Config space */ 849#define PCIE_DEVICE_CONTROL2 0x28 850#define PCIE_DEVICE_CONTROL2_16ms 0x0005 851 852#define PHY_REVISION_MASK 0xFFFFFFF0 853#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ 854#define MAX_PHY_MULTI_PAGE_REG 0xF 855 856/* Bit definitions for valid PHY IDs. */ 857/* I = Integrated 858 * E = External 859 */ 860#define M88E1111_I_PHY_ID 0x01410CC0 861#define M88E1112_E_PHY_ID 0x01410C90 862#define I347AT4_E_PHY_ID 0x01410DC0 863#define IGP03E1000_E_PHY_ID 0x02A80390 864#define I82580_I_PHY_ID 0x015403A0 865#define I350_I_PHY_ID 0x015403B0 866#define M88_VENDOR 0x0141 867#define I210_I_PHY_ID 0x01410C00 868#define M88E1543_E_PHY_ID 0x01410EA0 869#define M88E1512_E_PHY_ID 0x01410DD0 870 871/* M88E1000 Specific Registers */ 872#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */ 873#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */ 874#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */ 875 876#define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */ 877#define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */ 878 879/* M88E1000 PHY Specific Control Register */ 880#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */ 881/* 1=CLK125 low, 0=CLK125 toggling */ 882#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */ 883 /* Manual MDI configuration */ 884#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ 885/* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */ 886#define M88E1000_PSCR_AUTO_X_1000T 0x0040 887/* Auto crossover enabled all speeds */ 888#define M88E1000_PSCR_AUTO_X_MODE 0x0060 889/* 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold 890 * 0=Normal 10BASE-T Rx Threshold 891 */ 892/* 1=5-bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */ 893#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */ 894 895/* M88E1000 PHY Specific Status Register */ 896#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */ 897#define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */ 898#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */ 899/* 0 = <50M 900 * 1 = 50-80M 901 * 2 = 80-110M 902 * 3 = 110-140M 903 * 4 = >140M 904 */ 905#define M88E1000_PSSR_CABLE_LENGTH 0x0380 906#define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ 907#define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ 908 909#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7 910 911/* M88E1000 Extended PHY Specific Control Register */ 912/* 1 = Lost lock detect enabled. 913 * Will assert lost lock and bring 914 * link down if idle not seen 915 * within 1ms in 1000BASE-T 916 */ 917/* Number of times we will attempt to autonegotiate before downshifting if we 918 * are the master 919 */ 920#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00 921#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000 922/* Number of times we will attempt to autonegotiate before downshifting if we 923 * are the slave 924 */ 925#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300 926#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100 927#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ 928 929/* Intel i347-AT4 Registers */ 930 931#define I347AT4_PCDL0 0x10 /* Pair 0 PHY Cable Diagnostics Length */ 932#define I347AT4_PCDL1 0x11 /* Pair 1 PHY Cable Diagnostics Length */ 933#define I347AT4_PCDL2 0x12 /* Pair 2 PHY Cable Diagnostics Length */ 934#define I347AT4_PCDL3 0x13 /* Pair 3 PHY Cable Diagnostics Length */ 935#define I347AT4_PCDC 0x15 /* PHY Cable Diagnostics Control */ 936#define I347AT4_PAGE_SELECT 0x16 937 938/* i347-AT4 Extended PHY Specific Control Register */ 939 940/* Number of times we will attempt to autonegotiate before downshifting if we 941 * are the master 942 */ 943#define I347AT4_PSCR_DOWNSHIFT_ENABLE 0x0800 944#define I347AT4_PSCR_DOWNSHIFT_MASK 0x7000 945#define I347AT4_PSCR_DOWNSHIFT_1X 0x0000 946#define I347AT4_PSCR_DOWNSHIFT_2X 0x1000 947#define I347AT4_PSCR_DOWNSHIFT_3X 0x2000 948#define I347AT4_PSCR_DOWNSHIFT_4X 0x3000 949#define I347AT4_PSCR_DOWNSHIFT_5X 0x4000 950#define I347AT4_PSCR_DOWNSHIFT_6X 0x5000 951#define I347AT4_PSCR_DOWNSHIFT_7X 0x6000 952#define I347AT4_PSCR_DOWNSHIFT_8X 0x7000 953 954/* i347-AT4 PHY Cable Diagnostics Control */ 955#define I347AT4_PCDC_CABLE_LENGTH_UNIT 0x0400 /* 0=cm 1=meters */ 956 957/* Marvell 1112 only registers */ 958#define M88E1112_VCT_DSP_DISTANCE 0x001A 959 960/* M88EC018 Rev 2 specific DownShift settings */ 961#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00 962#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800 963 964/* MDI Control */ 965#define E1000_MDIC_DATA_MASK 0x0000FFFF 966#define E1000_MDIC_REG_MASK 0x001F0000 967#define E1000_MDIC_REG_SHIFT 16 968#define E1000_MDIC_PHY_MASK 0x03E00000 969#define E1000_MDIC_PHY_SHIFT 21 970#define E1000_MDIC_OP_WRITE 0x04000000 971#define E1000_MDIC_OP_READ 0x08000000 972#define E1000_MDIC_READY 0x10000000 973#define E1000_MDIC_INT_EN 0x20000000 974#define E1000_MDIC_ERROR 0x40000000 975#define E1000_MDIC_DEST 0x80000000 976 977/* Thermal Sensor */ 978#define E1000_THSTAT_PWR_DOWN 0x00000001 /* Power Down Event */ 979#define E1000_THSTAT_LINK_THROTTLE 0x00000002 /* Link Speed Throttle Event */ 980 981/* Energy Efficient Ethernet */ 982#define E1000_IPCNFG_EEE_1G_AN 0x00000008 /* EEE Enable 1G AN */ 983#define E1000_IPCNFG_EEE_100M_AN 0x00000004 /* EEE Enable 100M AN */ 984#define E1000_EEER_TX_LPI_EN 0x00010000 /* EEE Tx LPI Enable */ 985#define E1000_EEER_RX_LPI_EN 0x00020000 /* EEE Rx LPI Enable */ 986#define E1000_EEER_FRC_AN 0x10000000 /* Enable EEE in loopback */ 987#define E1000_EEER_LPI_FC 0x00040000 /* EEE Enable on FC */ 988#define E1000_EEE_SU_LPI_CLK_STP 0X00800000 /* EEE LPI Clock Stop */ 989#define E1000_EEER_EEE_NEG 0x20000000 /* EEE capability nego */ 990#define E1000_EEE_LP_ADV_ADDR_I350 0x040F /* EEE LP Advertisement */ 991#define E1000_EEE_LP_ADV_DEV_I210 7 /* EEE LP Adv Device */ 992#define E1000_EEE_LP_ADV_ADDR_I210 61 /* EEE LP Adv Register */ 993#define E1000_MMDAC_FUNC_DATA 0x4000 /* Data, no post increment */ 994#define E1000_M88E1543_PAGE_ADDR 0x16 /* Page Offset Register */ 995#define E1000_M88E1543_EEE_CTRL_1 0x0 996#define E1000_M88E1543_EEE_CTRL_1_MS 0x0001 /* EEE Master/Slave */ 997#define E1000_M88E1543_FIBER_CTRL 0x0 998#define E1000_EEE_ADV_DEV_I354 7 999#define E1000_EEE_ADV_ADDR_I354 60 1000#define E1000_EEE_ADV_100_SUPPORTED BIT(1) /* 100BaseTx EEE Supported */
1001#define E1000_EEE_ADV_1000_SUPPORTED BIT(2) /* 1000BaseT EEE Supported */ 1002#define E1000_PCS_STATUS_DEV_I354 3 1003#define E1000_PCS_STATUS_ADDR_I354 1 1004#define E1000_PCS_STATUS_TX_LPI_IND 0x0200 /* Tx in LPI state */ 1005#define E1000_PCS_STATUS_RX_LPI_RCVD 0x0400 1006#define E1000_PCS_STATUS_TX_LPI_RCVD 0x0800 1007 1008/* SerDes Control */ 1009#define E1000_GEN_CTL_READY 0x80000000 1010#define E1000_GEN_CTL_ADDRESS_SHIFT 8 1011#define E1000_GEN_POLL_TIMEOUT 640 1012 1013#define E1000_VFTA_ENTRY_SHIFT 5 1014#define E1000_VFTA_ENTRY_MASK 0x7F 1015#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F 1016 1017/* DMA Coalescing register fields */ 1018#define E1000_PCIEMISC_LX_DECISION 0x00000080 /* Lx power on DMA coal */ 1019 1020/* Tx Rate-Scheduler Config fields */ 1021#define E1000_RTTBCNRC_RS_ENA 0x80000000 1022#define E1000_RTTBCNRC_RF_DEC_MASK 0x00003FFF 1023#define E1000_RTTBCNRC_RF_INT_SHIFT 14 1024#define E1000_RTTBCNRC_RF_INT_MASK \ 1025 (E1000_RTTBCNRC_RF_DEC_MASK << E1000_RTTBCNRC_RF_INT_SHIFT) 1026 1027#define E1000_VLAPQF_QUEUE_SEL(_n, q_idx) (q_idx << ((_n) * 4)) 1028#define E1000_VLAPQF_P_VALID(_n) (0x1 << (3 + (_n) * 4)) 1029#define E1000_VLAPQF_QUEUE_MASK 0x03 1030 1031#endif 1032