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38#ifndef _MLXSW_REG_H
39#define _MLXSW_REG_H
40
41#include <linux/string.h>
42#include <linux/bitops.h>
43#include <linux/if_vlan.h>
44
45#include "item.h"
46#include "port.h"
47
48struct mlxsw_reg_info {
49 u16 id;
50 u16 len;
51};
52
53#define MLXSW_REG(type) (&mlxsw_reg_##type)
54#define MLXSW_REG_LEN(type) MLXSW_REG(type)->len
55#define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len)
56
57
58
59
60
61#define MLXSW_REG_SGCR_ID 0x2000
62#define MLXSW_REG_SGCR_LEN 0x10
63
64static const struct mlxsw_reg_info mlxsw_reg_sgcr = {
65 .id = MLXSW_REG_SGCR_ID,
66 .len = MLXSW_REG_SGCR_LEN,
67};
68
69
70
71
72
73
74
75MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1);
76
77static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb)
78{
79 MLXSW_REG_ZERO(sgcr, payload);
80 mlxsw_reg_sgcr_llb_set(payload, !!llb);
81}
82
83
84
85
86
87#define MLXSW_REG_SPAD_ID 0x2002
88#define MLXSW_REG_SPAD_LEN 0x10
89
90static const struct mlxsw_reg_info mlxsw_reg_spad = {
91 .id = MLXSW_REG_SPAD_ID,
92 .len = MLXSW_REG_SPAD_LEN,
93};
94
95
96
97
98
99
100
101MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6);
102
103
104
105
106
107
108
109#define MLXSW_REG_SMID_ID 0x2007
110#define MLXSW_REG_SMID_LEN 0x240
111
112static const struct mlxsw_reg_info mlxsw_reg_smid = {
113 .id = MLXSW_REG_SMID_ID,
114 .len = MLXSW_REG_SMID_LEN,
115};
116
117
118
119
120
121MLXSW_ITEM32(reg, smid, swid, 0x00, 24, 8);
122
123
124
125
126
127
128MLXSW_ITEM32(reg, smid, mid, 0x00, 0, 16);
129
130
131
132
133
134MLXSW_ITEM_BIT_ARRAY(reg, smid, port, 0x20, 0x20, 1);
135
136
137
138
139
140MLXSW_ITEM_BIT_ARRAY(reg, smid, port_mask, 0x220, 0x20, 1);
141
142static inline void mlxsw_reg_smid_pack(char *payload, u16 mid,
143 u8 port, bool set)
144{
145 MLXSW_REG_ZERO(smid, payload);
146 mlxsw_reg_smid_swid_set(payload, 0);
147 mlxsw_reg_smid_mid_set(payload, mid);
148 mlxsw_reg_smid_port_set(payload, port, set);
149 mlxsw_reg_smid_port_mask_set(payload, port, 1);
150}
151
152
153
154
155
156#define MLXSW_REG_SSPR_ID 0x2008
157#define MLXSW_REG_SSPR_LEN 0x8
158
159static const struct mlxsw_reg_info mlxsw_reg_sspr = {
160 .id = MLXSW_REG_SSPR_ID,
161 .len = MLXSW_REG_SSPR_LEN,
162};
163
164
165
166
167
168
169
170
171
172
173
174MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1);
175
176
177
178
179
180
181MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8);
182
183
184
185
186
187
188
189MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8);
190
191
192
193
194
195
196
197
198
199MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16);
200
201static inline void mlxsw_reg_sspr_pack(char *payload, u8 local_port)
202{
203 MLXSW_REG_ZERO(sspr, payload);
204 mlxsw_reg_sspr_m_set(payload, 1);
205 mlxsw_reg_sspr_local_port_set(payload, local_port);
206 mlxsw_reg_sspr_sub_port_set(payload, 0);
207 mlxsw_reg_sspr_system_port_set(payload, local_port);
208}
209
210
211
212
213
214
215#define MLXSW_REG_SFDAT_ID 0x2009
216#define MLXSW_REG_SFDAT_LEN 0x8
217
218static const struct mlxsw_reg_info mlxsw_reg_sfdat = {
219 .id = MLXSW_REG_SFDAT_ID,
220 .len = MLXSW_REG_SFDAT_LEN,
221};
222
223
224
225
226
227MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8);
228
229
230
231
232
233
234
235
236MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20);
237
238static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time)
239{
240 MLXSW_REG_ZERO(sfdat, payload);
241 mlxsw_reg_sfdat_swid_set(payload, 0);
242 mlxsw_reg_sfdat_age_time_set(payload, age_time);
243}
244
245
246
247
248
249
250
251
252#define MLXSW_REG_SFD_ID 0x200A
253#define MLXSW_REG_SFD_BASE_LEN 0x10
254#define MLXSW_REG_SFD_REC_LEN 0x10
255#define MLXSW_REG_SFD_REC_MAX_COUNT 64
256#define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \
257 MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT)
258
259static const struct mlxsw_reg_info mlxsw_reg_sfd = {
260 .id = MLXSW_REG_SFD_ID,
261 .len = MLXSW_REG_SFD_LEN,
262};
263
264
265
266
267
268MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8);
269
270enum mlxsw_reg_sfd_op {
271
272 MLXSW_REG_SFD_OP_QUERY_DUMP = 0,
273
274 MLXSW_REG_SFD_OP_QUERY_QUERY = 1,
275
276 MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2,
277
278
279
280 MLXSW_REG_SFD_OP_WRITE_TEST = 0,
281
282
283
284
285 MLXSW_REG_SFD_OP_WRITE_EDIT = 1,
286
287
288
289
290
291 MLXSW_REG_SFD_OP_WRITE_REMOVE = 2,
292
293
294
295 MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2,
296};
297
298
299
300
301
302MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2);
303
304
305
306
307
308
309
310
311MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30);
312
313
314
315
316
317
318
319
320MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8);
321
322static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op,
323 u32 record_locator)
324{
325 MLXSW_REG_ZERO(sfd, payload);
326 mlxsw_reg_sfd_op_set(payload, op);
327 mlxsw_reg_sfd_record_locator_set(payload, record_locator);
328}
329
330
331
332
333
334MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8,
335 MLXSW_REG_SFD_REC_LEN, 0x00, false);
336
337enum mlxsw_reg_sfd_rec_type {
338 MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0,
339 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1,
340 MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2,
341};
342
343
344
345
346
347MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4,
348 MLXSW_REG_SFD_REC_LEN, 0x00, false);
349
350enum mlxsw_reg_sfd_rec_policy {
351
352 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0,
353
354
355
356 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1,
357
358 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3,
359};
360
361
362
363
364
365MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2,
366 MLXSW_REG_SFD_REC_LEN, 0x00, false);
367
368
369
370
371
372
373
374MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1,
375 MLXSW_REG_SFD_REC_LEN, 0x00, false);
376
377
378
379
380
381MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6,
382 MLXSW_REG_SFD_REC_LEN, 0x02);
383
384enum mlxsw_reg_sfd_rec_action {
385
386 MLXSW_REG_SFD_REC_ACTION_NOP = 0,
387
388 MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1,
389
390 MLXSW_REG_SFD_REC_ACTION_TRAP = 2,
391
392 MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3,
393 MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15,
394};
395
396
397
398
399
400
401MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4,
402 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
403
404
405
406
407
408
409
410MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
411 MLXSW_REG_SFD_REC_LEN, 0x08, false);
412
413
414
415
416
417
418
419
420
421
422
423MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
424 MLXSW_REG_SFD_REC_LEN, 0x08, false);
425
426
427
428
429
430MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16,
431 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
432
433static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index,
434 enum mlxsw_reg_sfd_rec_type rec_type,
435 const char *mac,
436 enum mlxsw_reg_sfd_rec_action action)
437{
438 u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload);
439
440 if (rec_index >= num_rec)
441 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1);
442 mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0);
443 mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type);
444 mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac);
445 mlxsw_reg_sfd_rec_action_set(payload, rec_index, action);
446}
447
448static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index,
449 enum mlxsw_reg_sfd_rec_policy policy,
450 const char *mac, u16 fid_vid,
451 enum mlxsw_reg_sfd_rec_action action,
452 u8 local_port)
453{
454 mlxsw_reg_sfd_rec_pack(payload, rec_index,
455 MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action);
456 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
457 mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0);
458 mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid);
459 mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port);
460}
461
462static inline void mlxsw_reg_sfd_uc_unpack(char *payload, int rec_index,
463 char *mac, u16 *p_fid_vid,
464 u8 *p_local_port)
465{
466 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac);
467 *p_fid_vid = mlxsw_reg_sfd_uc_fid_vid_get(payload, rec_index);
468 *p_local_port = mlxsw_reg_sfd_uc_system_port_get(payload, rec_index);
469}
470
471
472
473
474
475
476MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
477 MLXSW_REG_SFD_REC_LEN, 0x08, false);
478
479
480
481
482
483
484
485
486
487
488
489MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
490 MLXSW_REG_SFD_REC_LEN, 0x08, false);
491
492
493
494
495
496MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12,
497 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
498
499
500
501
502
503MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10,
504 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
505
506static inline void
507mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index,
508 enum mlxsw_reg_sfd_rec_policy policy,
509 const char *mac, u16 fid_vid,
510 enum mlxsw_reg_sfd_rec_action action, u16 lag_vid,
511 u16 lag_id)
512{
513 mlxsw_reg_sfd_rec_pack(payload, rec_index,
514 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG,
515 mac, action);
516 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
517 mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0);
518 mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid);
519 mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid);
520 mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id);
521}
522
523static inline void mlxsw_reg_sfd_uc_lag_unpack(char *payload, int rec_index,
524 char *mac, u16 *p_vid,
525 u16 *p_lag_id)
526{
527 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac);
528 *p_vid = mlxsw_reg_sfd_uc_lag_fid_vid_get(payload, rec_index);
529 *p_lag_id = mlxsw_reg_sfd_uc_lag_lag_id_get(payload, rec_index);
530}
531
532
533
534
535
536
537
538
539MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13,
540 MLXSW_REG_SFD_REC_LEN, 0x08, false);
541
542
543
544
545
546
547MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
548 MLXSW_REG_SFD_REC_LEN, 0x08, false);
549
550
551
552
553
554
555
556MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
557 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
558
559static inline void
560mlxsw_reg_sfd_mc_pack(char *payload, int rec_index,
561 const char *mac, u16 fid_vid,
562 enum mlxsw_reg_sfd_rec_action action, u16 mid)
563{
564 mlxsw_reg_sfd_rec_pack(payload, rec_index,
565 MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action);
566 mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF);
567 mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid);
568 mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid);
569}
570
571
572
573
574
575
576#define MLXSW_REG_SFN_ID 0x200B
577#define MLXSW_REG_SFN_BASE_LEN 0x10
578#define MLXSW_REG_SFN_REC_LEN 0x10
579#define MLXSW_REG_SFN_REC_MAX_COUNT 64
580#define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \
581 MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT)
582
583static const struct mlxsw_reg_info mlxsw_reg_sfn = {
584 .id = MLXSW_REG_SFN_ID,
585 .len = MLXSW_REG_SFN_LEN,
586};
587
588
589
590
591
592MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8);
593
594
595
596
597
598MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1);
599
600
601
602
603
604
605
606
607
608MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8);
609
610static inline void mlxsw_reg_sfn_pack(char *payload)
611{
612 MLXSW_REG_ZERO(sfn, payload);
613 mlxsw_reg_sfn_swid_set(payload, 0);
614 mlxsw_reg_sfn_end_set(payload, 1);
615 mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT);
616}
617
618
619
620
621
622MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8,
623 MLXSW_REG_SFN_REC_LEN, 0x00, false);
624
625enum mlxsw_reg_sfn_rec_type {
626
627 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5,
628
629 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6,
630
631 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7,
632
633 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8,
634};
635
636
637
638
639
640MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4,
641 MLXSW_REG_SFN_REC_LEN, 0x00, false);
642
643
644
645
646
647MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6,
648 MLXSW_REG_SFN_REC_LEN, 0x02);
649
650
651
652
653
654
655MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8,
656 MLXSW_REG_SFN_REC_LEN, 0x08, false);
657
658
659
660
661
662MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16,
663 MLXSW_REG_SFN_REC_LEN, 0x08, false);
664
665
666
667
668
669MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16,
670 MLXSW_REG_SFN_REC_LEN, 0x0C, false);
671
672static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index,
673 char *mac, u16 *p_vid,
674 u8 *p_local_port)
675{
676 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
677 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
678 *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index);
679}
680
681
682
683
684
685MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10,
686 MLXSW_REG_SFN_REC_LEN, 0x0C, false);
687
688static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index,
689 char *mac, u16 *p_vid,
690 u16 *p_lag_id)
691{
692 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
693 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
694 *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index);
695}
696
697
698
699
700
701#define MLXSW_REG_SPMS_ID 0x200D
702#define MLXSW_REG_SPMS_LEN 0x404
703
704static const struct mlxsw_reg_info mlxsw_reg_spms = {
705 .id = MLXSW_REG_SPMS_ID,
706 .len = MLXSW_REG_SPMS_LEN,
707};
708
709
710
711
712
713MLXSW_ITEM32(reg, spms, local_port, 0x00, 16, 8);
714
715enum mlxsw_reg_spms_state {
716 MLXSW_REG_SPMS_STATE_NO_CHANGE,
717 MLXSW_REG_SPMS_STATE_DISCARDING,
718 MLXSW_REG_SPMS_STATE_LEARNING,
719 MLXSW_REG_SPMS_STATE_FORWARDING,
720};
721
722
723
724
725
726
727
728
729
730MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2);
731
732static inline void mlxsw_reg_spms_pack(char *payload, u8 local_port)
733{
734 MLXSW_REG_ZERO(spms, payload);
735 mlxsw_reg_spms_local_port_set(payload, local_port);
736}
737
738static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid,
739 enum mlxsw_reg_spms_state state)
740{
741 mlxsw_reg_spms_state_set(payload, vid, state);
742}
743
744
745
746
747
748#define MLXSW_REG_SPVID_ID 0x200E
749#define MLXSW_REG_SPVID_LEN 0x08
750
751static const struct mlxsw_reg_info mlxsw_reg_spvid = {
752 .id = MLXSW_REG_SPVID_ID,
753 .len = MLXSW_REG_SPVID_LEN,
754};
755
756
757
758
759
760MLXSW_ITEM32(reg, spvid, local_port, 0x00, 16, 8);
761
762
763
764
765
766
767MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8);
768
769
770
771
772
773MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12);
774
775static inline void mlxsw_reg_spvid_pack(char *payload, u8 local_port, u16 pvid)
776{
777 MLXSW_REG_ZERO(spvid, payload);
778 mlxsw_reg_spvid_local_port_set(payload, local_port);
779 mlxsw_reg_spvid_pvid_set(payload, pvid);
780}
781
782
783
784
785
786
787
788#define MLXSW_REG_SPVM_ID 0x200F
789#define MLXSW_REG_SPVM_BASE_LEN 0x04
790#define MLXSW_REG_SPVM_REC_LEN 0x04
791#define MLXSW_REG_SPVM_REC_MAX_COUNT 256
792#define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \
793 MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT)
794
795static const struct mlxsw_reg_info mlxsw_reg_spvm = {
796 .id = MLXSW_REG_SPVM_ID,
797 .len = MLXSW_REG_SPVM_LEN,
798};
799
800
801
802
803
804
805
806MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1);
807
808
809
810
811
812
813MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1);
814
815
816
817
818
819MLXSW_ITEM32(reg, spvm, local_port, 0x00, 16, 8);
820
821
822
823
824
825
826MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8);
827
828
829
830
831
832MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8);
833
834
835
836
837
838MLXSW_ITEM32_INDEXED(reg, spvm, rec_i,
839 MLXSW_REG_SPVM_BASE_LEN, 14, 1,
840 MLXSW_REG_SPVM_REC_LEN, 0, false);
841
842
843
844
845
846MLXSW_ITEM32_INDEXED(reg, spvm, rec_e,
847 MLXSW_REG_SPVM_BASE_LEN, 13, 1,
848 MLXSW_REG_SPVM_REC_LEN, 0, false);
849
850
851
852
853
854
855MLXSW_ITEM32_INDEXED(reg, spvm, rec_u,
856 MLXSW_REG_SPVM_BASE_LEN, 12, 1,
857 MLXSW_REG_SPVM_REC_LEN, 0, false);
858
859
860
861
862
863MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid,
864 MLXSW_REG_SPVM_BASE_LEN, 0, 12,
865 MLXSW_REG_SPVM_REC_LEN, 0, false);
866
867static inline void mlxsw_reg_spvm_pack(char *payload, u8 local_port,
868 u16 vid_begin, u16 vid_end,
869 bool is_member, bool untagged)
870{
871 int size = vid_end - vid_begin + 1;
872 int i;
873
874 MLXSW_REG_ZERO(spvm, payload);
875 mlxsw_reg_spvm_local_port_set(payload, local_port);
876 mlxsw_reg_spvm_num_rec_set(payload, size);
877
878 for (i = 0; i < size; i++) {
879 mlxsw_reg_spvm_rec_i_set(payload, i, is_member);
880 mlxsw_reg_spvm_rec_e_set(payload, i, is_member);
881 mlxsw_reg_spvm_rec_u_set(payload, i, untagged);
882 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i);
883 }
884}
885
886
887
888
889
890
891#define MLXSW_REG_SPAFT_ID 0x2010
892#define MLXSW_REG_SPAFT_LEN 0x08
893
894static const struct mlxsw_reg_info mlxsw_reg_spaft = {
895 .id = MLXSW_REG_SPAFT_ID,
896 .len = MLXSW_REG_SPAFT_LEN,
897};
898
899
900
901
902
903
904
905MLXSW_ITEM32(reg, spaft, local_port, 0x00, 16, 8);
906
907
908
909
910
911
912MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8);
913
914
915
916
917
918MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1);
919
920
921
922
923
924MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1);
925
926
927
928
929
930MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1);
931
932static inline void mlxsw_reg_spaft_pack(char *payload, u8 local_port,
933 bool allow_untagged)
934{
935 MLXSW_REG_ZERO(spaft, payload);
936 mlxsw_reg_spaft_local_port_set(payload, local_port);
937 mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged);
938 mlxsw_reg_spaft_allow_prio_tagged_set(payload, true);
939 mlxsw_reg_spaft_allow_tagged_set(payload, true);
940}
941
942
943
944
945
946
947#define MLXSW_REG_SFGC_ID 0x2011
948#define MLXSW_REG_SFGC_LEN 0x10
949
950static const struct mlxsw_reg_info mlxsw_reg_sfgc = {
951 .id = MLXSW_REG_SFGC_ID,
952 .len = MLXSW_REG_SFGC_LEN,
953};
954
955enum mlxsw_reg_sfgc_type {
956 MLXSW_REG_SFGC_TYPE_BROADCAST,
957 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST,
958 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4,
959 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6,
960 MLXSW_REG_SFGC_TYPE_RESERVED,
961 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP,
962 MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL,
963 MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST,
964 MLXSW_REG_SFGC_TYPE_MAX,
965};
966
967
968
969
970
971MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4);
972
973enum mlxsw_reg_sfgc_bridge_type {
974 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0,
975 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1,
976};
977
978
979
980
981
982
983MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3);
984
985enum mlxsw_flood_table_type {
986 MLXSW_REG_SFGC_TABLE_TYPE_VID = 1,
987 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2,
988 MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0,
989 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFEST = 3,
990 MLXSW_REG_SFGC_TABLE_TYPE_FID = 4,
991};
992
993
994
995
996
997
998
999MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3);
1000
1001
1002
1003
1004
1005
1006MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6);
1007
1008
1009
1010
1011
1012MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16);
1013
1014
1015
1016
1017
1018MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8);
1019
1020
1021
1022
1023
1024MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24);
1025
1026static inline void
1027mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type,
1028 enum mlxsw_reg_sfgc_bridge_type bridge_type,
1029 enum mlxsw_flood_table_type table_type,
1030 unsigned int flood_table)
1031{
1032 MLXSW_REG_ZERO(sfgc, payload);
1033 mlxsw_reg_sfgc_type_set(payload, type);
1034 mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type);
1035 mlxsw_reg_sfgc_table_type_set(payload, table_type);
1036 mlxsw_reg_sfgc_flood_table_set(payload, flood_table);
1037 mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID);
1038}
1039
1040
1041
1042
1043
1044
1045#define MLXSW_REG_SFTR_ID 0x2012
1046#define MLXSW_REG_SFTR_LEN 0x420
1047
1048static const struct mlxsw_reg_info mlxsw_reg_sftr = {
1049 .id = MLXSW_REG_SFTR_ID,
1050 .len = MLXSW_REG_SFTR_LEN,
1051};
1052
1053
1054
1055
1056
1057MLXSW_ITEM32(reg, sftr, swid, 0x00, 24, 8);
1058
1059
1060
1061
1062
1063
1064MLXSW_ITEM32(reg, sftr, flood_table, 0x00, 16, 6);
1065
1066
1067
1068
1069
1070
1071MLXSW_ITEM32(reg, sftr, index, 0x00, 0, 16);
1072
1073
1074
1075
1076
1077MLXSW_ITEM32(reg, sftr, table_type, 0x04, 16, 3);
1078
1079
1080
1081
1082
1083MLXSW_ITEM32(reg, sftr, range, 0x04, 0, 16);
1084
1085
1086
1087
1088
1089MLXSW_ITEM_BIT_ARRAY(reg, sftr, port, 0x20, 0x20, 1);
1090
1091
1092
1093
1094
1095MLXSW_ITEM_BIT_ARRAY(reg, sftr, port_mask, 0x220, 0x20, 1);
1096
1097static inline void mlxsw_reg_sftr_pack(char *payload,
1098 unsigned int flood_table,
1099 unsigned int index,
1100 enum mlxsw_flood_table_type table_type,
1101 unsigned int range, u8 port, bool set)
1102{
1103 MLXSW_REG_ZERO(sftr, payload);
1104 mlxsw_reg_sftr_swid_set(payload, 0);
1105 mlxsw_reg_sftr_flood_table_set(payload, flood_table);
1106 mlxsw_reg_sftr_index_set(payload, index);
1107 mlxsw_reg_sftr_table_type_set(payload, table_type);
1108 mlxsw_reg_sftr_range_set(payload, range);
1109 mlxsw_reg_sftr_port_set(payload, port, set);
1110 mlxsw_reg_sftr_port_mask_set(payload, port, 1);
1111}
1112
1113
1114
1115
1116
1117
1118#define MLXSW_REG_SFDF_ID 0x2013
1119#define MLXSW_REG_SFDF_LEN 0x14
1120
1121static const struct mlxsw_reg_info mlxsw_reg_sfdf = {
1122 .id = MLXSW_REG_SFDF_ID,
1123 .len = MLXSW_REG_SFDF_LEN,
1124};
1125
1126
1127
1128
1129
1130MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8);
1131
1132enum mlxsw_reg_sfdf_flush_type {
1133 MLXSW_REG_SFDF_FLUSH_PER_SWID,
1134 MLXSW_REG_SFDF_FLUSH_PER_FID,
1135 MLXSW_REG_SFDF_FLUSH_PER_PORT,
1136 MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID,
1137 MLXSW_REG_SFDF_FLUSH_PER_LAG,
1138 MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID,
1139};
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4);
1152
1153
1154
1155
1156
1157
1158
1159MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1);
1160
1161static inline void mlxsw_reg_sfdf_pack(char *payload,
1162 enum mlxsw_reg_sfdf_flush_type type)
1163{
1164 MLXSW_REG_ZERO(sfdf, payload);
1165 mlxsw_reg_sfdf_flush_type_set(payload, type);
1166 mlxsw_reg_sfdf_flush_static_set(payload, true);
1167}
1168
1169
1170
1171
1172
1173MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16);
1174
1175
1176
1177
1178
1179MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16);
1180
1181
1182
1183
1184
1185MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16);
1186
1187
1188
1189
1190
1191MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10);
1192
1193
1194
1195
1196
1197MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10);
1198
1199
1200
1201
1202
1203
1204
1205#define MLXSW_REG_SLDR_ID 0x2014
1206#define MLXSW_REG_SLDR_LEN 0x0C
1207
1208static const struct mlxsw_reg_info mlxsw_reg_sldr = {
1209 .id = MLXSW_REG_SLDR_ID,
1210 .len = MLXSW_REG_SLDR_LEN,
1211};
1212
1213enum mlxsw_reg_sldr_op {
1214
1215 MLXSW_REG_SLDR_OP_LAG_CREATE,
1216 MLXSW_REG_SLDR_OP_LAG_DESTROY,
1217
1218 MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST,
1219
1220 MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST,
1221};
1222
1223
1224
1225
1226
1227MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3);
1228
1229
1230
1231
1232
1233MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10);
1234
1235static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id)
1236{
1237 MLXSW_REG_ZERO(sldr, payload);
1238 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE);
1239 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1240}
1241
1242static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id)
1243{
1244 MLXSW_REG_ZERO(sldr, payload);
1245 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY);
1246 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1247}
1248
1249
1250
1251
1252
1253
1254
1255MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8);
1256
1257
1258
1259
1260
1261MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false);
1262
1263static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id,
1264 u8 local_port)
1265{
1266 MLXSW_REG_ZERO(sldr, payload);
1267 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST);
1268 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1269 mlxsw_reg_sldr_num_ports_set(payload, 1);
1270 mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
1271}
1272
1273static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id,
1274 u8 local_port)
1275{
1276 MLXSW_REG_ZERO(sldr, payload);
1277 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST);
1278 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1279 mlxsw_reg_sldr_num_ports_set(payload, 1);
1280 mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
1281}
1282
1283
1284
1285
1286
1287
1288#define MLXSW_REG_SLCR_ID 0x2015
1289#define MLXSW_REG_SLCR_LEN 0x10
1290
1291static const struct mlxsw_reg_info mlxsw_reg_slcr = {
1292 .id = MLXSW_REG_SLCR_ID,
1293 .len = MLXSW_REG_SLCR_LEN,
1294};
1295
1296enum mlxsw_reg_slcr_pp {
1297
1298 MLXSW_REG_SLCR_PP_GLOBAL,
1299
1300 MLXSW_REG_SLCR_PP_PER_PORT,
1301};
1302
1303
1304
1305
1306
1307
1308MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1);
1309
1310
1311
1312
1313
1314
1315
1316
1317MLXSW_ITEM32(reg, slcr, local_port, 0x00, 16, 8);
1318
1319enum mlxsw_reg_slcr_type {
1320 MLXSW_REG_SLCR_TYPE_CRC,
1321 MLXSW_REG_SLCR_TYPE_XOR,
1322 MLXSW_REG_SLCR_TYPE_RANDOM,
1323};
1324
1325
1326
1327
1328
1329MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4);
1330
1331
1332#define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0)
1333
1334#define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1)
1335
1336#define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2)
1337#define MLXSW_REG_SLCR_LAG_HASH_SMAC \
1338 (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \
1339 MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP)
1340
1341#define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3)
1342
1343#define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4)
1344#define MLXSW_REG_SLCR_LAG_HASH_DMAC \
1345 (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \
1346 MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP)
1347
1348#define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5)
1349
1350#define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6)
1351#define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \
1352 (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \
1353 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP)
1354
1355#define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7)
1356
1357#define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8)
1358#define MLXSW_REG_SLCR_LAG_HASH_VLANID \
1359 (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \
1360 MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP)
1361
1362#define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9)
1363
1364#define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10)
1365
1366#define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11)
1367
1368#define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12)
1369
1370#define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13)
1371
1372#define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14)
1373
1374#define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15)
1375
1376#define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16)
1377
1378#define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17)
1379
1380#define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19)
1381
1382
1383
1384
1385
1386
1387
1388
1389MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20);
1390
1391static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash)
1392{
1393 MLXSW_REG_ZERO(slcr, payload);
1394 mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL);
1395 mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_CRC);
1396 mlxsw_reg_slcr_lag_hash_set(payload, lag_hash);
1397}
1398
1399
1400
1401
1402
1403
1404#define MLXSW_REG_SLCOR_ID 0x2016
1405#define MLXSW_REG_SLCOR_LEN 0x10
1406
1407static const struct mlxsw_reg_info mlxsw_reg_slcor = {
1408 .id = MLXSW_REG_SLCOR_ID,
1409 .len = MLXSW_REG_SLCOR_LEN,
1410};
1411
1412enum mlxsw_reg_slcor_col {
1413
1414 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT,
1415 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED,
1416 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED,
1417 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT,
1418};
1419
1420
1421
1422
1423
1424MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2);
1425
1426
1427
1428
1429
1430
1431MLXSW_ITEM32(reg, slcor, local_port, 0x00, 16, 8);
1432
1433
1434
1435
1436
1437MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10);
1438
1439
1440
1441
1442
1443
1444MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10);
1445
1446static inline void mlxsw_reg_slcor_pack(char *payload,
1447 u8 local_port, u16 lag_id,
1448 enum mlxsw_reg_slcor_col col)
1449{
1450 MLXSW_REG_ZERO(slcor, payload);
1451 mlxsw_reg_slcor_col_set(payload, col);
1452 mlxsw_reg_slcor_local_port_set(payload, local_port);
1453 mlxsw_reg_slcor_lag_id_set(payload, lag_id);
1454}
1455
1456static inline void mlxsw_reg_slcor_port_add_pack(char *payload,
1457 u8 local_port, u16 lag_id,
1458 u8 port_index)
1459{
1460 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1461 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT);
1462 mlxsw_reg_slcor_port_index_set(payload, port_index);
1463}
1464
1465static inline void mlxsw_reg_slcor_port_remove_pack(char *payload,
1466 u8 local_port, u16 lag_id)
1467{
1468 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1469 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT);
1470}
1471
1472static inline void mlxsw_reg_slcor_col_enable_pack(char *payload,
1473 u8 local_port, u16 lag_id)
1474{
1475 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1476 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
1477}
1478
1479static inline void mlxsw_reg_slcor_col_disable_pack(char *payload,
1480 u8 local_port, u16 lag_id)
1481{
1482 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1483 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
1484}
1485
1486
1487
1488
1489
1490#define MLXSW_REG_SPMLR_ID 0x2018
1491#define MLXSW_REG_SPMLR_LEN 0x8
1492
1493static const struct mlxsw_reg_info mlxsw_reg_spmlr = {
1494 .id = MLXSW_REG_SPMLR_ID,
1495 .len = MLXSW_REG_SPMLR_LEN,
1496};
1497
1498
1499
1500
1501
1502MLXSW_ITEM32(reg, spmlr, local_port, 0x00, 16, 8);
1503
1504
1505
1506
1507
1508
1509MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8);
1510
1511enum mlxsw_reg_spmlr_learn_mode {
1512 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0,
1513 MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2,
1514 MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3,
1515};
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2);
1529
1530static inline void mlxsw_reg_spmlr_pack(char *payload, u8 local_port,
1531 enum mlxsw_reg_spmlr_learn_mode mode)
1532{
1533 MLXSW_REG_ZERO(spmlr, payload);
1534 mlxsw_reg_spmlr_local_port_set(payload, local_port);
1535 mlxsw_reg_spmlr_sub_port_set(payload, 0);
1536 mlxsw_reg_spmlr_learn_mode_set(payload, mode);
1537}
1538
1539
1540
1541
1542
1543
1544#define MLXSW_REG_SVFA_ID 0x201C
1545#define MLXSW_REG_SVFA_LEN 0x10
1546
1547static const struct mlxsw_reg_info mlxsw_reg_svfa = {
1548 .id = MLXSW_REG_SVFA_ID,
1549 .len = MLXSW_REG_SVFA_LEN,
1550};
1551
1552
1553
1554
1555
1556MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8);
1557
1558
1559
1560
1561
1562
1563
1564MLXSW_ITEM32(reg, svfa, local_port, 0x00, 16, 8);
1565
1566enum mlxsw_reg_svfa_mt {
1567 MLXSW_REG_SVFA_MT_VID_TO_FID,
1568 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
1569};
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3);
1580
1581
1582
1583
1584
1585
1586
1587
1588MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1);
1589
1590
1591
1592
1593
1594MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16);
1595
1596
1597
1598
1599
1600MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12);
1601
1602
1603
1604
1605
1606
1607
1608MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8);
1609
1610
1611
1612
1613
1614
1615
1616MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24);
1617
1618static inline void mlxsw_reg_svfa_pack(char *payload, u8 local_port,
1619 enum mlxsw_reg_svfa_mt mt, bool valid,
1620 u16 fid, u16 vid)
1621{
1622 MLXSW_REG_ZERO(svfa, payload);
1623 local_port = mt == MLXSW_REG_SVFA_MT_VID_TO_FID ? 0 : local_port;
1624 mlxsw_reg_svfa_swid_set(payload, 0);
1625 mlxsw_reg_svfa_local_port_set(payload, local_port);
1626 mlxsw_reg_svfa_mapping_table_set(payload, mt);
1627 mlxsw_reg_svfa_v_set(payload, valid);
1628 mlxsw_reg_svfa_fid_set(payload, fid);
1629 mlxsw_reg_svfa_vid_set(payload, vid);
1630}
1631
1632
1633
1634
1635
1636#define MLXSW_REG_SVPE_ID 0x201E
1637#define MLXSW_REG_SVPE_LEN 0x4
1638
1639static const struct mlxsw_reg_info mlxsw_reg_svpe = {
1640 .id = MLXSW_REG_SVPE_ID,
1641 .len = MLXSW_REG_SVPE_LEN,
1642};
1643
1644
1645
1646
1647
1648
1649
1650MLXSW_ITEM32(reg, svpe, local_port, 0x00, 16, 8);
1651
1652
1653
1654
1655
1656
1657
1658MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1);
1659
1660static inline void mlxsw_reg_svpe_pack(char *payload, u8 local_port,
1661 bool enable)
1662{
1663 MLXSW_REG_ZERO(svpe, payload);
1664 mlxsw_reg_svpe_local_port_set(payload, local_port);
1665 mlxsw_reg_svpe_vp_en_set(payload, enable);
1666}
1667
1668
1669
1670
1671
1672#define MLXSW_REG_SFMR_ID 0x201F
1673#define MLXSW_REG_SFMR_LEN 0x18
1674
1675static const struct mlxsw_reg_info mlxsw_reg_sfmr = {
1676 .id = MLXSW_REG_SFMR_ID,
1677 .len = MLXSW_REG_SFMR_LEN,
1678};
1679
1680enum mlxsw_reg_sfmr_op {
1681 MLXSW_REG_SFMR_OP_CREATE_FID,
1682 MLXSW_REG_SFMR_OP_DESTROY_FID,
1683};
1684
1685
1686
1687
1688
1689
1690
1691MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4);
1692
1693
1694
1695
1696
1697MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16);
1698
1699
1700
1701
1702
1703
1704
1705MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16);
1706
1707
1708
1709
1710
1711
1712
1713
1714MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1);
1715
1716
1717
1718
1719
1720
1721
1722MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24);
1723
1724
1725
1726
1727
1728
1729
1730
1731MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1);
1732
1733
1734
1735
1736
1737
1738
1739MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24);
1740
1741static inline void mlxsw_reg_sfmr_pack(char *payload,
1742 enum mlxsw_reg_sfmr_op op, u16 fid,
1743 u16 fid_offset)
1744{
1745 MLXSW_REG_ZERO(sfmr, payload);
1746 mlxsw_reg_sfmr_op_set(payload, op);
1747 mlxsw_reg_sfmr_fid_set(payload, fid);
1748 mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset);
1749 mlxsw_reg_sfmr_vtfp_set(payload, false);
1750 mlxsw_reg_sfmr_vv_set(payload, false);
1751}
1752
1753
1754
1755
1756
1757#define MLXSW_REG_SPVMLR_ID 0x2020
1758#define MLXSW_REG_SPVMLR_BASE_LEN 0x04
1759#define MLXSW_REG_SPVMLR_REC_LEN 0x04
1760#define MLXSW_REG_SPVMLR_REC_MAX_COUNT 256
1761#define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \
1762 MLXSW_REG_SPVMLR_REC_LEN * \
1763 MLXSW_REG_SPVMLR_REC_MAX_COUNT)
1764
1765static const struct mlxsw_reg_info mlxsw_reg_spvmlr = {
1766 .id = MLXSW_REG_SPVMLR_ID,
1767 .len = MLXSW_REG_SPVMLR_LEN,
1768};
1769
1770
1771
1772
1773
1774
1775
1776MLXSW_ITEM32(reg, spvmlr, local_port, 0x00, 16, 8);
1777
1778
1779
1780
1781
1782MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8);
1783
1784
1785
1786
1787
1788
1789MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN,
1790 31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
1791
1792
1793
1794
1795
1796MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12,
1797 MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
1798
1799static inline void mlxsw_reg_spvmlr_pack(char *payload, u8 local_port,
1800 u16 vid_begin, u16 vid_end,
1801 bool learn_enable)
1802{
1803 int num_rec = vid_end - vid_begin + 1;
1804 int i;
1805
1806 WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT);
1807
1808 MLXSW_REG_ZERO(spvmlr, payload);
1809 mlxsw_reg_spvmlr_local_port_set(payload, local_port);
1810 mlxsw_reg_spvmlr_num_rec_set(payload, num_rec);
1811
1812 for (i = 0; i < num_rec; i++) {
1813 mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable);
1814 mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i);
1815 }
1816}
1817
1818
1819
1820
1821
1822
1823#define MLXSW_REG_QTCT_ID 0x400A
1824#define MLXSW_REG_QTCT_LEN 0x08
1825
1826static const struct mlxsw_reg_info mlxsw_reg_qtct = {
1827 .id = MLXSW_REG_QTCT_ID,
1828 .len = MLXSW_REG_QTCT_LEN,
1829};
1830
1831
1832
1833
1834
1835
1836
1837MLXSW_ITEM32(reg, qtct, local_port, 0x00, 16, 8);
1838
1839
1840
1841
1842
1843
1844MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8);
1845
1846
1847
1848
1849
1850MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4);
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4);
1861
1862static inline void mlxsw_reg_qtct_pack(char *payload, u8 local_port,
1863 u8 switch_prio, u8 tclass)
1864{
1865 MLXSW_REG_ZERO(qtct, payload);
1866 mlxsw_reg_qtct_local_port_set(payload, local_port);
1867 mlxsw_reg_qtct_switch_prio_set(payload, switch_prio);
1868 mlxsw_reg_qtct_tclass_set(payload, tclass);
1869}
1870
1871
1872
1873
1874
1875#define MLXSW_REG_QEEC_ID 0x400D
1876#define MLXSW_REG_QEEC_LEN 0x1C
1877
1878static const struct mlxsw_reg_info mlxsw_reg_qeec = {
1879 .id = MLXSW_REG_QEEC_ID,
1880 .len = MLXSW_REG_QEEC_LEN,
1881};
1882
1883
1884
1885
1886
1887
1888
1889MLXSW_ITEM32(reg, qeec, local_port, 0x00, 16, 8);
1890
1891enum mlxsw_reg_qeec_hr {
1892 MLXSW_REG_QEEC_HIERARCY_PORT,
1893 MLXSW_REG_QEEC_HIERARCY_GROUP,
1894 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
1895 MLXSW_REG_QEEC_HIERARCY_TC,
1896};
1897
1898
1899
1900
1901
1902
1903
1904
1905MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4);
1906
1907
1908
1909
1910
1911MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8);
1912
1913
1914
1915
1916
1917
1918
1919MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8);
1920
1921enum {
1922 MLXSW_REG_QEEC_BYTES_MODE,
1923 MLXSW_REG_QEEC_PACKETS_MODE,
1924};
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1);
1936
1937
1938
1939
1940
1941
1942
1943
1944MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1);
1945
1946
1947#define MLXSW_REG_QEEC_MAS_DIS 200000000
1948
1949
1950
1951
1952
1953
1954
1955MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 28);
1956
1957
1958
1959
1960
1961
1962
1963
1964MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1);
1965
1966
1967
1968
1969
1970
1971
1972
1973MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1);
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8);
1984
1985static inline void mlxsw_reg_qeec_pack(char *payload, u8 local_port,
1986 enum mlxsw_reg_qeec_hr hr, u8 index,
1987 u8 next_index)
1988{
1989 MLXSW_REG_ZERO(qeec, payload);
1990 mlxsw_reg_qeec_local_port_set(payload, local_port);
1991 mlxsw_reg_qeec_element_hierarchy_set(payload, hr);
1992 mlxsw_reg_qeec_element_index_set(payload, index);
1993 mlxsw_reg_qeec_next_element_index_set(payload, next_index);
1994}
1995
1996
1997
1998
1999
2000#define MLXSW_REG_PMLP_ID 0x5002
2001#define MLXSW_REG_PMLP_LEN 0x40
2002
2003static const struct mlxsw_reg_info mlxsw_reg_pmlp = {
2004 .id = MLXSW_REG_PMLP_ID,
2005 .len = MLXSW_REG_PMLP_LEN,
2006};
2007
2008
2009
2010
2011
2012
2013MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1);
2014
2015
2016
2017
2018
2019MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8);
2020
2021
2022
2023
2024
2025
2026
2027
2028MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8);
2029
2030
2031
2032
2033
2034MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false);
2035
2036
2037
2038
2039
2040MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 2, 0x04, 0x00, false);
2041
2042
2043
2044
2045
2046
2047MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 2, 0x04, 0x00, false);
2048
2049static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port)
2050{
2051 MLXSW_REG_ZERO(pmlp, payload);
2052 mlxsw_reg_pmlp_local_port_set(payload, local_port);
2053}
2054
2055
2056
2057
2058
2059#define MLXSW_REG_PMTU_ID 0x5003
2060#define MLXSW_REG_PMTU_LEN 0x10
2061
2062static const struct mlxsw_reg_info mlxsw_reg_pmtu = {
2063 .id = MLXSW_REG_PMTU_ID,
2064 .len = MLXSW_REG_PMTU_LEN,
2065};
2066
2067
2068
2069
2070
2071MLXSW_ITEM32(reg, pmtu, local_port, 0x00, 16, 8);
2072
2073
2074
2075
2076
2077
2078
2079
2080MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16);
2081
2082
2083
2084
2085
2086
2087
2088MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16);
2089
2090
2091
2092
2093
2094
2095
2096
2097MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16);
2098
2099static inline void mlxsw_reg_pmtu_pack(char *payload, u8 local_port,
2100 u16 new_mtu)
2101{
2102 MLXSW_REG_ZERO(pmtu, payload);
2103 mlxsw_reg_pmtu_local_port_set(payload, local_port);
2104 mlxsw_reg_pmtu_max_mtu_set(payload, 0);
2105 mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu);
2106 mlxsw_reg_pmtu_oper_mtu_set(payload, 0);
2107}
2108
2109
2110
2111
2112
2113
2114
2115
2116#define MLXSW_REG_PTYS_ID 0x5004
2117#define MLXSW_REG_PTYS_LEN 0x40
2118
2119static const struct mlxsw_reg_info mlxsw_reg_ptys = {
2120 .id = MLXSW_REG_PTYS_ID,
2121 .len = MLXSW_REG_PTYS_LEN,
2122};
2123
2124
2125
2126
2127
2128MLXSW_ITEM32(reg, ptys, local_port, 0x00, 16, 8);
2129
2130#define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2)
2131
2132
2133
2134
2135
2136
2137
2138
2139MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3);
2140
2141enum {
2142 MLXSW_REG_PTYS_AN_STATUS_NA,
2143 MLXSW_REG_PTYS_AN_STATUS_OK,
2144 MLXSW_REG_PTYS_AN_STATUS_FAIL,
2145};
2146
2147
2148
2149
2150
2151MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4);
2152
2153#define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0)
2154#define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1)
2155#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2)
2156#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3)
2157#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4)
2158#define MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2 BIT(5)
2159#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6)
2160#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7)
2161#define MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4 BIT(8)
2162#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12)
2163#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13)
2164#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14)
2165#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15)
2166#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16)
2167#define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2 BIT(18)
2168#define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19)
2169#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20)
2170#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21)
2171#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22)
2172#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23)
2173#define MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX BIT(24)
2174#define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T BIT(25)
2175#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T BIT(26)
2176#define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27)
2177#define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28)
2178#define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29)
2179#define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30)
2180#define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31)
2181
2182
2183
2184
2185
2186MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32);
2187
2188
2189
2190
2191
2192MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32);
2193
2194
2195
2196
2197
2198MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32);
2199
2200
2201
2202
2203
2204
2205MLXSW_ITEM32(reg, ptys, eth_proto_lp_advertise, 0x30, 0, 32);
2206
2207static inline void mlxsw_reg_ptys_pack(char *payload, u8 local_port,
2208 u32 proto_admin)
2209{
2210 MLXSW_REG_ZERO(ptys, payload);
2211 mlxsw_reg_ptys_local_port_set(payload, local_port);
2212 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH);
2213 mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin);
2214}
2215
2216static inline void mlxsw_reg_ptys_unpack(char *payload, u32 *p_eth_proto_cap,
2217 u32 *p_eth_proto_adm,
2218 u32 *p_eth_proto_oper)
2219{
2220 if (p_eth_proto_cap)
2221 *p_eth_proto_cap = mlxsw_reg_ptys_eth_proto_cap_get(payload);
2222 if (p_eth_proto_adm)
2223 *p_eth_proto_adm = mlxsw_reg_ptys_eth_proto_admin_get(payload);
2224 if (p_eth_proto_oper)
2225 *p_eth_proto_oper = mlxsw_reg_ptys_eth_proto_oper_get(payload);
2226}
2227
2228
2229
2230
2231
2232#define MLXSW_REG_PPAD_ID 0x5005
2233#define MLXSW_REG_PPAD_LEN 0x10
2234
2235static const struct mlxsw_reg_info mlxsw_reg_ppad = {
2236 .id = MLXSW_REG_PPAD_ID,
2237 .len = MLXSW_REG_PPAD_LEN,
2238};
2239
2240
2241
2242
2243
2244
2245
2246MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1);
2247
2248
2249
2250
2251
2252MLXSW_ITEM32(reg, ppad, local_port, 0x00, 16, 8);
2253
2254
2255
2256
2257
2258
2259MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6);
2260
2261static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac,
2262 u8 local_port)
2263{
2264 MLXSW_REG_ZERO(ppad, payload);
2265 mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac);
2266 mlxsw_reg_ppad_local_port_set(payload, local_port);
2267}
2268
2269
2270
2271
2272
2273#define MLXSW_REG_PAOS_ID 0x5006
2274#define MLXSW_REG_PAOS_LEN 0x10
2275
2276static const struct mlxsw_reg_info mlxsw_reg_paos = {
2277 .id = MLXSW_REG_PAOS_ID,
2278 .len = MLXSW_REG_PAOS_LEN,
2279};
2280
2281
2282
2283
2284
2285
2286
2287
2288MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8);
2289
2290
2291
2292
2293
2294MLXSW_ITEM32(reg, paos, local_port, 0x00, 16, 8);
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4);
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4);
2316
2317
2318
2319
2320
2321MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1);
2322
2323
2324
2325
2326
2327
2328MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1);
2329
2330
2331
2332
2333
2334
2335
2336
2337MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2);
2338
2339static inline void mlxsw_reg_paos_pack(char *payload, u8 local_port,
2340 enum mlxsw_port_admin_status status)
2341{
2342 MLXSW_REG_ZERO(paos, payload);
2343 mlxsw_reg_paos_swid_set(payload, 0);
2344 mlxsw_reg_paos_local_port_set(payload, local_port);
2345 mlxsw_reg_paos_admin_status_set(payload, status);
2346 mlxsw_reg_paos_oper_status_set(payload, 0);
2347 mlxsw_reg_paos_ase_set(payload, 1);
2348 mlxsw_reg_paos_ee_set(payload, 1);
2349 mlxsw_reg_paos_e_set(payload, 1);
2350}
2351
2352
2353
2354
2355
2356#define MLXSW_REG_PFCC_ID 0x5007
2357#define MLXSW_REG_PFCC_LEN 0x20
2358
2359static const struct mlxsw_reg_info mlxsw_reg_pfcc = {
2360 .id = MLXSW_REG_PFCC_ID,
2361 .len = MLXSW_REG_PFCC_LEN,
2362};
2363
2364
2365
2366
2367
2368MLXSW_ITEM32(reg, pfcc, local_port, 0x00, 16, 8);
2369
2370
2371
2372
2373
2374
2375
2376MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2);
2377
2378
2379
2380
2381
2382
2383
2384
2385MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1);
2386
2387
2388
2389
2390
2391
2392
2393
2394MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1);
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4);
2407
2408
2409
2410
2411
2412
2413MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8);
2414
2415
2416
2417
2418
2419
2420MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8);
2421
2422
2423
2424
2425
2426
2427
2428MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1);
2429
2430
2431
2432
2433
2434
2435
2436MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1);
2437
2438
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8);
2449
2450
2451
2452
2453
2454
2455
2456MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1);
2457
2458
2459
2460
2461
2462
2463
2464MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1);
2465
2466
2467
2468
2469
2470
2471
2472
2473MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8);
2474
2475#define MLXSW_REG_PFCC_ALL_PRIO 0xFF
2476
2477static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en)
2478{
2479 mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO);
2480 mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO);
2481 mlxsw_reg_pfcc_pfctx_set(payload, pfc_en);
2482 mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en);
2483}
2484
2485static inline void mlxsw_reg_pfcc_pack(char *payload, u8 local_port)
2486{
2487 MLXSW_REG_ZERO(pfcc, payload);
2488 mlxsw_reg_pfcc_local_port_set(payload, local_port);
2489}
2490
2491
2492
2493
2494
2495#define MLXSW_REG_PPCNT_ID 0x5008
2496#define MLXSW_REG_PPCNT_LEN 0x100
2497
2498static const struct mlxsw_reg_info mlxsw_reg_ppcnt = {
2499 .id = MLXSW_REG_PPCNT_ID,
2500 .len = MLXSW_REG_PPCNT_LEN,
2501};
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8);
2513
2514
2515
2516
2517
2518
2519
2520MLXSW_ITEM32(reg, ppcnt, local_port, 0x00, 16, 8);
2521
2522
2523
2524
2525
2526
2527
2528MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2);
2529
2530enum mlxsw_reg_ppcnt_grp {
2531 MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0,
2532 MLXSW_REG_PPCNT_PRIO_CNT = 0x10,
2533 MLXSW_REG_PPCNT_TC_CNT = 0x11,
2534};
2535
2536
2537
2538
2539
2540
2541
2542
2543
2544
2545
2546
2547
2548
2549
2550
2551MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6);
2552
2553
2554
2555
2556
2557
2558
2559MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1);
2560
2561
2562
2563
2564
2565
2566
2567
2568
2569MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5);
2570
2571
2572
2573
2574
2575
2576MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok,
2577 0x08 + 0x00, 0, 64);
2578
2579
2580
2581
2582MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok,
2583 0x08 + 0x08, 0, 64);
2584
2585
2586
2587
2588MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors,
2589 0x08 + 0x10, 0, 64);
2590
2591
2592
2593
2594MLXSW_ITEM64(reg, ppcnt, a_alignment_errors,
2595 0x08 + 0x18, 0, 64);
2596
2597
2598
2599
2600MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok,
2601 0x08 + 0x20, 0, 64);
2602
2603
2604
2605
2606MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok,
2607 0x08 + 0x28, 0, 64);
2608
2609
2610
2611
2612MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok,
2613 0x08 + 0x30, 0, 64);
2614
2615
2616
2617
2618MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok,
2619 0x08 + 0x38, 0, 64);
2620
2621
2622
2623
2624MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok,
2625 0x08 + 0x40, 0, 64);
2626
2627
2628
2629
2630MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok,
2631 0x08 + 0x48, 0, 64);
2632
2633
2634
2635
2636MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors,
2637 0x08 + 0x50, 0, 64);
2638
2639
2640
2641
2642MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field,
2643 0x08 + 0x58, 0, 64);
2644
2645
2646
2647
2648MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors,
2649 0x08 + 0x60, 0, 64);
2650
2651
2652
2653
2654MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier,
2655 0x08 + 0x68, 0, 64);
2656
2657
2658
2659
2660MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted,
2661 0x08 + 0x70, 0, 64);
2662
2663
2664
2665
2666MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received,
2667 0x08 + 0x78, 0, 64);
2668
2669
2670
2671
2672MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received,
2673 0x08 + 0x80, 0, 64);
2674
2675
2676
2677
2678MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received,
2679 0x08 + 0x88, 0, 64);
2680
2681
2682
2683
2684MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted,
2685 0x08 + 0x90, 0, 64);
2686
2687
2688
2689
2690
2691
2692MLXSW_ITEM64(reg, ppcnt, rx_octets, 0x08 + 0x00, 0, 64);
2693
2694
2695
2696
2697MLXSW_ITEM64(reg, ppcnt, rx_frames, 0x08 + 0x20, 0, 64);
2698
2699
2700
2701
2702MLXSW_ITEM64(reg, ppcnt, tx_octets, 0x08 + 0x28, 0, 64);
2703
2704
2705
2706
2707MLXSW_ITEM64(reg, ppcnt, tx_frames, 0x08 + 0x48, 0, 64);
2708
2709
2710
2711
2712MLXSW_ITEM64(reg, ppcnt, rx_pause, 0x08 + 0x50, 0, 64);
2713
2714
2715
2716
2717MLXSW_ITEM64(reg, ppcnt, rx_pause_duration, 0x08 + 0x58, 0, 64);
2718
2719
2720
2721
2722MLXSW_ITEM64(reg, ppcnt, tx_pause, 0x08 + 0x60, 0, 64);
2723
2724
2725
2726
2727MLXSW_ITEM64(reg, ppcnt, tx_pause_duration, 0x08 + 0x68, 0, 64);
2728
2729
2730
2731
2732MLXSW_ITEM64(reg, ppcnt, tx_pause_transition, 0x08 + 0x70, 0, 64);
2733
2734
2735
2736
2737
2738
2739
2740
2741
2742MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue, 0x08 + 0x00, 0, 64);
2743
2744
2745
2746
2747
2748
2749MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc, 0x08 + 0x08, 0, 64);
2750
2751static inline void mlxsw_reg_ppcnt_pack(char *payload, u8 local_port,
2752 enum mlxsw_reg_ppcnt_grp grp,
2753 u8 prio_tc)
2754{
2755 MLXSW_REG_ZERO(ppcnt, payload);
2756 mlxsw_reg_ppcnt_swid_set(payload, 0);
2757 mlxsw_reg_ppcnt_local_port_set(payload, local_port);
2758 mlxsw_reg_ppcnt_pnat_set(payload, 0);
2759 mlxsw_reg_ppcnt_grp_set(payload, grp);
2760 mlxsw_reg_ppcnt_clr_set(payload, 0);
2761 mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc);
2762}
2763
2764
2765
2766
2767
2768#define MLXSW_REG_PPTB_ID 0x500B
2769#define MLXSW_REG_PPTB_LEN 0x10
2770
2771static const struct mlxsw_reg_info mlxsw_reg_pptb = {
2772 .id = MLXSW_REG_PPTB_ID,
2773 .len = MLXSW_REG_PPTB_LEN,
2774};
2775
2776enum {
2777 MLXSW_REG_PPTB_MM_UM,
2778 MLXSW_REG_PPTB_MM_UNICAST,
2779 MLXSW_REG_PPTB_MM_MULTICAST,
2780};
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2);
2792
2793
2794
2795
2796
2797MLXSW_ITEM32(reg, pptb, local_port, 0x00, 16, 8);
2798
2799
2800
2801
2802
2803MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1);
2804
2805
2806
2807
2808
2809
2810MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8);
2811
2812
2813
2814
2815
2816
2817MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4);
2818
2819
2820
2821
2822
2823
2824MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8);
2825
2826
2827
2828
2829
2830
2831
2832
2833MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4);
2834
2835
2836
2837
2838
2839
2840MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4);
2841
2842#define MLXSW_REG_PPTB_ALL_PRIO 0xFF
2843
2844static inline void mlxsw_reg_pptb_pack(char *payload, u8 local_port)
2845{
2846 MLXSW_REG_ZERO(pptb, payload);
2847 mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM);
2848 mlxsw_reg_pptb_local_port_set(payload, local_port);
2849 mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO);
2850 mlxsw_reg_pptb_pm_msb_set(payload, MLXSW_REG_PPTB_ALL_PRIO);
2851}
2852
2853static inline void mlxsw_reg_pptb_prio_to_buff_pack(char *payload, u8 prio,
2854 u8 buff)
2855{
2856 mlxsw_reg_pptb_prio_to_buff_set(payload, prio, buff);
2857 mlxsw_reg_pptb_prio_to_buff_msb_set(payload, prio, buff);
2858}
2859
2860
2861
2862
2863
2864
2865#define MLXSW_REG_PBMC_ID 0x500C
2866#define MLXSW_REG_PBMC_LEN 0x6C
2867
2868static const struct mlxsw_reg_info mlxsw_reg_pbmc = {
2869 .id = MLXSW_REG_PBMC_ID,
2870 .len = MLXSW_REG_PBMC_LEN,
2871};
2872
2873
2874
2875
2876
2877MLXSW_ITEM32(reg, pbmc, local_port, 0x00, 16, 8);
2878
2879
2880
2881
2882
2883
2884MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16);
2885
2886
2887
2888
2889
2890
2891
2892MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16);
2893
2894#define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11
2895
2896
2897
2898
2899
2900
2901
2902MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false);
2903
2904
2905
2906
2907
2908
2909
2910
2911MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false);
2912
2913
2914
2915
2916
2917
2918MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false);
2919
2920
2921
2922
2923
2924
2925
2926
2927
2928
2929MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16,
2930 0x08, 0x04, false);
2931
2932
2933
2934
2935
2936
2937
2938
2939
2940
2941MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16,
2942 0x08, 0x04, false);
2943
2944static inline void mlxsw_reg_pbmc_pack(char *payload, u8 local_port,
2945 u16 xoff_timer_value, u16 xoff_refresh)
2946{
2947 MLXSW_REG_ZERO(pbmc, payload);
2948 mlxsw_reg_pbmc_local_port_set(payload, local_port);
2949 mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value);
2950 mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh);
2951}
2952
2953static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload,
2954 int buf_index,
2955 u16 size)
2956{
2957 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1);
2958 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0);
2959 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size);
2960}
2961
2962static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload,
2963 int buf_index, u16 size,
2964 u16 threshold)
2965{
2966 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0);
2967 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0);
2968 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size);
2969 mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold);
2970 mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold);
2971}
2972
2973
2974
2975
2976
2977
2978#define MLXSW_REG_PSPA_ID 0x500D
2979#define MLXSW_REG_PSPA_LEN 0x8
2980
2981static const struct mlxsw_reg_info mlxsw_reg_pspa = {
2982 .id = MLXSW_REG_PSPA_ID,
2983 .len = MLXSW_REG_PSPA_LEN,
2984};
2985
2986
2987
2988
2989
2990MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8);
2991
2992
2993
2994
2995
2996MLXSW_ITEM32(reg, pspa, local_port, 0x00, 16, 8);
2997
2998
2999
3000
3001
3002
3003MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8);
3004
3005static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u8 local_port)
3006{
3007 MLXSW_REG_ZERO(pspa, payload);
3008 mlxsw_reg_pspa_swid_set(payload, swid);
3009 mlxsw_reg_pspa_local_port_set(payload, local_port);
3010 mlxsw_reg_pspa_sub_port_set(payload, 0);
3011}
3012
3013
3014
3015
3016
3017#define MLXSW_REG_HTGT_ID 0x7002
3018#define MLXSW_REG_HTGT_LEN 0x100
3019
3020static const struct mlxsw_reg_info mlxsw_reg_htgt = {
3021 .id = MLXSW_REG_HTGT_ID,
3022 .len = MLXSW_REG_HTGT_LEN,
3023};
3024
3025
3026
3027
3028
3029MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8);
3030
3031#define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0
3032
3033
3034
3035
3036
3037MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4);
3038
3039enum mlxsw_reg_htgt_trap_group {
3040 MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
3041 MLXSW_REG_HTGT_TRAP_GROUP_RX,
3042 MLXSW_REG_HTGT_TRAP_GROUP_CTRL,
3043};
3044
3045
3046
3047
3048
3049
3050
3051MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8);
3052
3053enum {
3054 MLXSW_REG_HTGT_POLICER_DISABLE,
3055 MLXSW_REG_HTGT_POLICER_ENABLE,
3056};
3057
3058
3059
3060
3061
3062MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1);
3063
3064
3065
3066
3067
3068MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8);
3069
3070#define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0
3071
3072
3073
3074
3075
3076
3077
3078
3079
3080
3081MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2);
3082
3083
3084
3085
3086
3087MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3);
3088
3089
3090
3091
3092
3093
3094
3095
3096
3097
3098
3099
3100MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4);
3101
3102
3103
3104
3105
3106MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6);
3107
3108#define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_EMAD 0x15
3109#define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_RX 0x14
3110#define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_CTRL 0x13
3111
3112
3113
3114
3115
3116MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6);
3117
3118static inline void mlxsw_reg_htgt_pack(char *payload,
3119 enum mlxsw_reg_htgt_trap_group group)
3120{
3121 u8 swid, rdq;
3122
3123 MLXSW_REG_ZERO(htgt, payload);
3124 switch (group) {
3125 case MLXSW_REG_HTGT_TRAP_GROUP_EMAD:
3126 swid = MLXSW_PORT_SWID_ALL_SWIDS;
3127 rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_EMAD;
3128 break;
3129 case MLXSW_REG_HTGT_TRAP_GROUP_RX:
3130 swid = 0;
3131 rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_RX;
3132 break;
3133 case MLXSW_REG_HTGT_TRAP_GROUP_CTRL:
3134 swid = 0;
3135 rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_CTRL;
3136 break;
3137 }
3138 mlxsw_reg_htgt_swid_set(payload, swid);
3139 mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL);
3140 mlxsw_reg_htgt_trap_group_set(payload, group);
3141 mlxsw_reg_htgt_pide_set(payload, MLXSW_REG_HTGT_POLICER_DISABLE);
3142 mlxsw_reg_htgt_pid_set(payload, 0);
3143 mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU);
3144 mlxsw_reg_htgt_mirroring_agent_set(payload, 0);
3145 mlxsw_reg_htgt_priority_set(payload, 0);
3146 mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, 7);
3147 mlxsw_reg_htgt_local_path_rdq_set(payload, rdq);
3148}
3149
3150
3151
3152
3153
3154#define MLXSW_REG_HPKT_ID 0x7003
3155#define MLXSW_REG_HPKT_LEN 0x10
3156
3157static const struct mlxsw_reg_info mlxsw_reg_hpkt = {
3158 .id = MLXSW_REG_HPKT_ID,
3159 .len = MLXSW_REG_HPKT_LEN,
3160};
3161
3162enum {
3163 MLXSW_REG_HPKT_ACK_NOT_REQUIRED,
3164 MLXSW_REG_HPKT_ACK_REQUIRED,
3165};
3166
3167
3168
3169
3170
3171
3172
3173
3174
3175MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1);
3176
3177enum mlxsw_reg_hpkt_action {
3178 MLXSW_REG_HPKT_ACTION_FORWARD,
3179 MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU,
3180 MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU,
3181 MLXSW_REG_HPKT_ACTION_DISCARD,
3182 MLXSW_REG_HPKT_ACTION_SOFT_DISCARD,
3183 MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD,
3184};
3185
3186
3187
3188
3189
3190
3191
3192
3193
3194
3195
3196
3197
3198
3199MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3);
3200
3201
3202
3203
3204
3205MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6);
3206
3207
3208
3209
3210
3211
3212
3213
3214MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 9);
3215
3216enum {
3217 MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT,
3218 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER,
3219 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER,
3220};
3221
3222
3223
3224
3225
3226
3227
3228
3229MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2);
3230
3231static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id)
3232{
3233 enum mlxsw_reg_htgt_trap_group trap_group;
3234
3235 MLXSW_REG_ZERO(hpkt, payload);
3236 mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED);
3237 mlxsw_reg_hpkt_action_set(payload, action);
3238 switch (trap_id) {
3239 case MLXSW_TRAP_ID_ETHEMAD:
3240 case MLXSW_TRAP_ID_PUDE:
3241 trap_group = MLXSW_REG_HTGT_TRAP_GROUP_EMAD;
3242 break;
3243 default:
3244 trap_group = MLXSW_REG_HTGT_TRAP_GROUP_RX;
3245 break;
3246 }
3247 mlxsw_reg_hpkt_trap_group_set(payload, trap_group);
3248 mlxsw_reg_hpkt_trap_id_set(payload, trap_id);
3249 mlxsw_reg_hpkt_ctrl_set(payload, MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT);
3250}
3251
3252
3253
3254
3255
3256#define MLXSW_REG_RGCR_ID 0x8001
3257#define MLXSW_REG_RGCR_LEN 0x28
3258
3259static const struct mlxsw_reg_info mlxsw_reg_rgcr = {
3260 .id = MLXSW_REG_RGCR_ID,
3261 .len = MLXSW_REG_RGCR_LEN,
3262};
3263
3264
3265
3266
3267
3268MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1);
3269
3270
3271
3272
3273
3274MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1);
3275
3276
3277
3278
3279
3280
3281MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16);
3282
3283
3284
3285
3286
3287
3288
3289
3290
3291MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1);
3292
3293
3294
3295
3296
3297
3298
3299
3300
3301
3302MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2);
3303
3304
3305
3306
3307
3308
3309
3310
3311
3312
3313
3314
3315
3316
3317
3318MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8);
3319
3320static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en)
3321{
3322 MLXSW_REG_ZERO(rgcr, payload);
3323 mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en);
3324}
3325
3326
3327
3328
3329
3330#define MLXSW_REG_RITR_ID 0x8002
3331#define MLXSW_REG_RITR_LEN 0x40
3332
3333static const struct mlxsw_reg_info mlxsw_reg_ritr = {
3334 .id = MLXSW_REG_RITR_ID,
3335 .len = MLXSW_REG_RITR_LEN,
3336};
3337
3338
3339
3340
3341
3342MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1);
3343
3344
3345
3346
3347
3348
3349MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1);
3350
3351
3352
3353
3354
3355
3356MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1);
3357
3358enum mlxsw_reg_ritr_if_type {
3359 MLXSW_REG_RITR_VLAN_IF,
3360 MLXSW_REG_RITR_FID_IF,
3361 MLXSW_REG_RITR_SP_IF,
3362};
3363
3364
3365
3366
3367
3368
3369
3370
3371MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3);
3372
3373enum {
3374 MLXSW_REG_RITR_RIF_CREATE,
3375 MLXSW_REG_RITR_RIF_DEL,
3376};
3377
3378
3379
3380
3381
3382
3383
3384
3385
3386
3387MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2);
3388
3389
3390
3391
3392
3393MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16);
3394
3395
3396
3397
3398
3399
3400
3401
3402MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1);
3403
3404
3405
3406
3407
3408
3409
3410
3411MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1);
3412
3413
3414
3415
3416
3417
3418
3419
3420MLXSW_ITEM32(reg, ritr, lb_en, 0x04, 24, 1);
3421
3422
3423
3424
3425
3426MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16);
3427
3428
3429
3430
3431
3432MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16);
3433
3434
3435
3436
3437
3438MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8);
3439
3440
3441
3442
3443
3444
3445MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6);
3446
3447
3448
3449
3450
3451
3452
3453MLXSW_ITEM32(reg, ritr, vlan_if_vid, 0x08, 0, 12);
3454
3455
3456
3457
3458
3459
3460
3461
3462MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16);
3463
3464static inline void mlxsw_reg_ritr_fid_set(char *payload,
3465 enum mlxsw_reg_ritr_if_type rif_type,
3466 u16 fid)
3467{
3468 if (rif_type == MLXSW_REG_RITR_FID_IF)
3469 mlxsw_reg_ritr_fid_if_fid_set(payload, fid);
3470 else
3471 mlxsw_reg_ritr_vlan_if_vid_set(payload, fid);
3472}
3473
3474
3475
3476
3477
3478
3479
3480
3481MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1);
3482
3483
3484
3485
3486
3487
3488MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16);
3489
3490
3491
3492
3493
3494MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12);
3495
3496static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif)
3497{
3498 MLXSW_REG_ZERO(ritr, payload);
3499 mlxsw_reg_ritr_rif_set(payload, rif);
3500}
3501
3502static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag,
3503 u16 system_port, u16 vid)
3504{
3505 mlxsw_reg_ritr_sp_if_lag_set(payload, lag);
3506 mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port);
3507 mlxsw_reg_ritr_sp_if_vid_set(payload, vid);
3508}
3509
3510static inline void mlxsw_reg_ritr_pack(char *payload, bool enable,
3511 enum mlxsw_reg_ritr_if_type type,
3512 u16 rif, u16 mtu, const char *mac)
3513{
3514 bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL;
3515
3516 MLXSW_REG_ZERO(ritr, payload);
3517 mlxsw_reg_ritr_enable_set(payload, enable);
3518 mlxsw_reg_ritr_ipv4_set(payload, 1);
3519 mlxsw_reg_ritr_type_set(payload, type);
3520 mlxsw_reg_ritr_op_set(payload, op);
3521 mlxsw_reg_ritr_rif_set(payload, rif);
3522 mlxsw_reg_ritr_ipv4_fe_set(payload, 1);
3523 mlxsw_reg_ritr_lb_en_set(payload, 1);
3524 mlxsw_reg_ritr_mtu_set(payload, mtu);
3525 mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac);
3526}
3527
3528
3529
3530
3531
3532
3533#define MLXSW_REG_RATR_ID 0x8008
3534#define MLXSW_REG_RATR_LEN 0x2C
3535
3536static const struct mlxsw_reg_info mlxsw_reg_ratr = {
3537 .id = MLXSW_REG_RATR_ID,
3538 .len = MLXSW_REG_RATR_LEN,
3539};
3540
3541enum mlxsw_reg_ratr_op {
3542
3543 MLXSW_REG_RATR_OP_QUERY_READ = 0,
3544
3545 MLXSW_REG_RATR_OP_QUERY_READ_CLEAR = 2,
3546
3547 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY = 1,
3548
3549
3550
3551
3552
3553
3554 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY = 3,
3555};
3556
3557
3558
3559
3560
3561
3562
3563MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4);
3564
3565
3566
3567
3568
3569
3570
3571
3572
3573
3574
3575
3576
3577MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1);
3578
3579
3580
3581
3582
3583
3584MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1);
3585
3586
3587
3588
3589
3590
3591
3592
3593MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16);
3594
3595
3596
3597
3598
3599MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16);
3600
3601enum mlxsw_reg_ratr_trap_action {
3602 MLXSW_REG_RATR_TRAP_ACTION_NOP,
3603 MLXSW_REG_RATR_TRAP_ACTION_TRAP,
3604 MLXSW_REG_RATR_TRAP_ACTION_MIRROR_TO_CPU,
3605 MLXSW_REG_RATR_TRAP_ACTION_MIRROR,
3606 MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS,
3607};
3608
3609
3610
3611
3612
3613MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4);
3614
3615enum mlxsw_reg_ratr_trap_id {
3616 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS0 = 0,
3617 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS1 = 1,
3618};
3619
3620
3621
3622
3623
3624MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8);
3625
3626
3627
3628
3629
3630
3631
3632MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8);
3633
3634
3635
3636
3637
3638MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6);
3639
3640static inline void
3641mlxsw_reg_ratr_pack(char *payload,
3642 enum mlxsw_reg_ratr_op op, bool valid,
3643 u32 adjacency_index, u16 egress_rif)
3644{
3645 MLXSW_REG_ZERO(ratr, payload);
3646 mlxsw_reg_ratr_op_set(payload, op);
3647 mlxsw_reg_ratr_v_set(payload, valid);
3648 mlxsw_reg_ratr_adjacency_index_low_set(payload, adjacency_index);
3649 mlxsw_reg_ratr_adjacency_index_high_set(payload, adjacency_index >> 16);
3650 mlxsw_reg_ratr_egress_router_interface_set(payload, egress_rif);
3651}
3652
3653static inline void mlxsw_reg_ratr_eth_entry_pack(char *payload,
3654 const char *dest_mac)
3655{
3656 mlxsw_reg_ratr_eth_destination_mac_memcpy_to(payload, dest_mac);
3657}
3658
3659
3660
3661
3662
3663#define MLXSW_REG_RALTA_ID 0x8010
3664#define MLXSW_REG_RALTA_LEN 0x04
3665
3666static const struct mlxsw_reg_info mlxsw_reg_ralta = {
3667 .id = MLXSW_REG_RALTA_ID,
3668 .len = MLXSW_REG_RALTA_LEN,
3669};
3670
3671
3672
3673
3674
3675
3676
3677MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2);
3678
3679enum mlxsw_reg_ralxx_protocol {
3680 MLXSW_REG_RALXX_PROTOCOL_IPV4,
3681 MLXSW_REG_RALXX_PROTOCOL_IPV6,
3682};
3683
3684
3685
3686
3687
3688
3689MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4);
3690
3691
3692
3693
3694
3695
3696
3697MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8);
3698
3699static inline void mlxsw_reg_ralta_pack(char *payload, bool alloc,
3700 enum mlxsw_reg_ralxx_protocol protocol,
3701 u8 tree_id)
3702{
3703 MLXSW_REG_ZERO(ralta, payload);
3704 mlxsw_reg_ralta_op_set(payload, !alloc);
3705 mlxsw_reg_ralta_protocol_set(payload, protocol);
3706 mlxsw_reg_ralta_tree_id_set(payload, tree_id);
3707}
3708
3709
3710
3711
3712
3713
3714
3715
3716
3717
3718#define MLXSW_REG_RALST_ID 0x8011
3719#define MLXSW_REG_RALST_LEN 0x104
3720
3721static const struct mlxsw_reg_info mlxsw_reg_ralst = {
3722 .id = MLXSW_REG_RALST_ID,
3723 .len = MLXSW_REG_RALST_LEN,
3724};
3725
3726
3727
3728
3729
3730
3731
3732MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8);
3733
3734
3735
3736
3737
3738MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8);
3739
3740#define MLXSW_REG_RALST_BIN_NO_CHILD 0xff
3741#define MLXSW_REG_RALST_BIN_OFFSET 0x04
3742#define MLXSW_REG_RALST_BIN_COUNT 128
3743
3744
3745
3746
3747
3748
3749
3750MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false);
3751
3752
3753
3754
3755
3756
3757
3758MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00,
3759 false);
3760
3761static inline void mlxsw_reg_ralst_pack(char *payload, u8 root_bin, u8 tree_id)
3762{
3763 MLXSW_REG_ZERO(ralst, payload);
3764
3765
3766 memset(payload + MLXSW_REG_RALST_BIN_OFFSET,
3767 MLXSW_REG_RALST_BIN_NO_CHILD, MLXSW_REG_RALST_BIN_COUNT * 2);
3768
3769 mlxsw_reg_ralst_root_bin_set(payload, root_bin);
3770 mlxsw_reg_ralst_tree_id_set(payload, tree_id);
3771}
3772
3773static inline void mlxsw_reg_ralst_bin_pack(char *payload, u8 bin_number,
3774 u8 left_child_bin,
3775 u8 right_child_bin)
3776{
3777 int bin_index = bin_number - 1;
3778
3779 mlxsw_reg_ralst_left_child_bin_set(payload, bin_index, left_child_bin);
3780 mlxsw_reg_ralst_right_child_bin_set(payload, bin_index,
3781 right_child_bin);
3782}
3783
3784
3785
3786
3787
3788#define MLXSW_REG_RALTB_ID 0x8012
3789#define MLXSW_REG_RALTB_LEN 0x04
3790
3791static const struct mlxsw_reg_info mlxsw_reg_raltb = {
3792 .id = MLXSW_REG_RALTB_ID,
3793 .len = MLXSW_REG_RALTB_LEN,
3794};
3795
3796
3797
3798
3799
3800
3801MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16);
3802
3803
3804
3805
3806
3807MLXSW_ITEM32(reg, raltb, protocol, 0x00, 12, 4);
3808
3809
3810
3811
3812
3813
3814
3815MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8);
3816
3817static inline void mlxsw_reg_raltb_pack(char *payload, u16 virtual_router,
3818 enum mlxsw_reg_ralxx_protocol protocol,
3819 u8 tree_id)
3820{
3821 MLXSW_REG_ZERO(raltb, payload);
3822 mlxsw_reg_raltb_virtual_router_set(payload, virtual_router);
3823 mlxsw_reg_raltb_protocol_set(payload, protocol);
3824 mlxsw_reg_raltb_tree_id_set(payload, tree_id);
3825}
3826
3827
3828
3829
3830
3831
3832#define MLXSW_REG_RALUE_ID 0x8013
3833#define MLXSW_REG_RALUE_LEN 0x38
3834
3835static const struct mlxsw_reg_info mlxsw_reg_ralue = {
3836 .id = MLXSW_REG_RALUE_ID,
3837 .len = MLXSW_REG_RALUE_LEN,
3838};
3839
3840
3841
3842
3843
3844MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4);
3845
3846enum mlxsw_reg_ralue_op {
3847
3848 MLXSW_REG_RALUE_OP_QUERY_READ = 0,
3849
3850
3851
3852 MLXSW_REG_RALUE_OP_QUERY_CLEAR = 1,
3853
3854
3855
3856
3857 MLXSW_REG_RALUE_OP_WRITE_WRITE = 0,
3858
3859
3860
3861
3862 MLXSW_REG_RALUE_OP_WRITE_UPDATE = 1,
3863
3864
3865
3866 MLXSW_REG_RALUE_OP_WRITE_CLEAR = 2,
3867
3868
3869
3870 MLXSW_REG_RALUE_OP_WRITE_DELETE = 3,
3871};
3872
3873
3874
3875
3876
3877MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3);
3878
3879
3880
3881
3882
3883
3884
3885
3886MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1);
3887
3888
3889
3890
3891
3892
3893MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16);
3894
3895#define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE BIT(0)
3896#define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN BIT(1)
3897#define MLXSW_REG_RALUE_OP_U_MASK_ACTION BIT(2)
3898
3899
3900
3901
3902
3903
3904
3905
3906MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3);
3907
3908
3909
3910
3911
3912
3913
3914MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8);
3915
3916
3917
3918
3919
3920
3921
3922
3923
3924MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32);
3925
3926enum mlxsw_reg_ralue_entry_type {
3927 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_ENTRY = 1,
3928 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY = 2,
3929 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_AND_ROUTE_ENTRY = 3,
3930};
3931
3932
3933
3934
3935
3936
3937MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2);
3938
3939
3940
3941
3942
3943
3944
3945
3946
3947MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8);
3948
3949enum mlxsw_reg_ralue_action_type {
3950 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE,
3951 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL,
3952 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME,
3953};
3954
3955
3956
3957
3958
3959
3960
3961
3962
3963
3964MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2);
3965
3966enum mlxsw_reg_ralue_trap_action {
3967 MLXSW_REG_RALUE_TRAP_ACTION_NOP,
3968 MLXSW_REG_RALUE_TRAP_ACTION_TRAP,
3969 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR_TO_CPU,
3970 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR,
3971 MLXSW_REG_RALUE_TRAP_ACTION_DISCARD_ERROR,
3972};
3973
3974
3975
3976
3977
3978
3979MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4);
3980
3981
3982
3983
3984
3985
3986
3987MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9);
3988
3989
3990
3991
3992
3993
3994MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24);
3995
3996
3997
3998
3999
4000
4001
4002
4003
4004MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13);
4005
4006
4007
4008
4009
4010
4011MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16);
4012
4013
4014
4015
4016
4017
4018
4019
4020
4021
4022
4023MLXSW_ITEM32(reg, ralue, v, 0x24, 31, 1);
4024
4025
4026
4027
4028
4029
4030
4031MLXSW_ITEM32(reg, ralue, tunnel_ptr, 0x24, 0, 24);
4032
4033static inline void mlxsw_reg_ralue_pack(char *payload,
4034 enum mlxsw_reg_ralxx_protocol protocol,
4035 enum mlxsw_reg_ralue_op op,
4036 u16 virtual_router, u8 prefix_len)
4037{
4038 MLXSW_REG_ZERO(ralue, payload);
4039 mlxsw_reg_ralue_protocol_set(payload, protocol);
4040 mlxsw_reg_ralue_op_set(payload, op);
4041 mlxsw_reg_ralue_virtual_router_set(payload, virtual_router);
4042 mlxsw_reg_ralue_prefix_len_set(payload, prefix_len);
4043 mlxsw_reg_ralue_entry_type_set(payload,
4044 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY);
4045 mlxsw_reg_ralue_bmp_len_set(payload, prefix_len);
4046}
4047
4048static inline void mlxsw_reg_ralue_pack4(char *payload,
4049 enum mlxsw_reg_ralxx_protocol protocol,
4050 enum mlxsw_reg_ralue_op op,
4051 u16 virtual_router, u8 prefix_len,
4052 u32 dip)
4053{
4054 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len);
4055 mlxsw_reg_ralue_dip4_set(payload, dip);
4056}
4057
4058static inline void
4059mlxsw_reg_ralue_act_remote_pack(char *payload,
4060 enum mlxsw_reg_ralue_trap_action trap_action,
4061 u16 trap_id, u32 adjacency_index, u16 ecmp_size)
4062{
4063 mlxsw_reg_ralue_action_type_set(payload,
4064 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE);
4065 mlxsw_reg_ralue_trap_action_set(payload, trap_action);
4066 mlxsw_reg_ralue_trap_id_set(payload, trap_id);
4067 mlxsw_reg_ralue_adjacency_index_set(payload, adjacency_index);
4068 mlxsw_reg_ralue_ecmp_size_set(payload, ecmp_size);
4069}
4070
4071static inline void
4072mlxsw_reg_ralue_act_local_pack(char *payload,
4073 enum mlxsw_reg_ralue_trap_action trap_action,
4074 u16 trap_id, u16 local_erif)
4075{
4076 mlxsw_reg_ralue_action_type_set(payload,
4077 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL);
4078 mlxsw_reg_ralue_trap_action_set(payload, trap_action);
4079 mlxsw_reg_ralue_trap_id_set(payload, trap_id);
4080 mlxsw_reg_ralue_local_erif_set(payload, local_erif);
4081}
4082
4083static inline void
4084mlxsw_reg_ralue_act_ip2me_pack(char *payload)
4085{
4086 mlxsw_reg_ralue_action_type_set(payload,
4087 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME);
4088}
4089
4090
4091
4092
4093
4094
4095#define MLXSW_REG_RAUHT_ID 0x8014
4096#define MLXSW_REG_RAUHT_LEN 0x74
4097
4098static const struct mlxsw_reg_info mlxsw_reg_rauht = {
4099 .id = MLXSW_REG_RAUHT_ID,
4100 .len = MLXSW_REG_RAUHT_LEN,
4101};
4102
4103enum mlxsw_reg_rauht_type {
4104 MLXSW_REG_RAUHT_TYPE_IPV4,
4105 MLXSW_REG_RAUHT_TYPE_IPV6,
4106};
4107
4108
4109
4110
4111MLXSW_ITEM32(reg, rauht, type, 0x00, 24, 2);
4112
4113enum mlxsw_reg_rauht_op {
4114 MLXSW_REG_RAUHT_OP_QUERY_READ = 0,
4115
4116 MLXSW_REG_RAUHT_OP_QUERY_CLEAR_ON_READ = 1,
4117
4118
4119
4120 MLXSW_REG_RAUHT_OP_WRITE_ADD = 0,
4121
4122
4123
4124 MLXSW_REG_RAUHT_OP_WRITE_UPDATE = 1,
4125
4126
4127
4128
4129 MLXSW_REG_RAUHT_OP_WRITE_CLEAR_ACTIVITY = 2,
4130
4131 MLXSW_REG_RAUHT_OP_WRITE_DELETE = 3,
4132
4133 MLXSW_REG_RAUHT_OP_WRITE_DELETE_ALL = 4,
4134
4135
4136
4137};
4138
4139
4140
4141
4142MLXSW_ITEM32(reg, rauht, op, 0x00, 20, 3);
4143
4144
4145
4146
4147
4148
4149
4150
4151MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1);
4152
4153
4154
4155
4156
4157MLXSW_ITEM32(reg, rauht, rif, 0x00, 0, 16);
4158
4159
4160
4161
4162
4163MLXSW_ITEM32(reg, rauht, dip4, 0x1C, 0x0, 32);
4164
4165enum mlxsw_reg_rauht_trap_action {
4166 MLXSW_REG_RAUHT_TRAP_ACTION_NOP,
4167 MLXSW_REG_RAUHT_TRAP_ACTION_TRAP,
4168 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR_TO_CPU,
4169 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR,
4170 MLXSW_REG_RAUHT_TRAP_ACTION_DISCARD_ERRORS,
4171};
4172
4173
4174
4175
4176MLXSW_ITEM32(reg, rauht, trap_action, 0x60, 28, 4);
4177
4178enum mlxsw_reg_rauht_trap_id {
4179 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS0,
4180 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS1,
4181};
4182
4183
4184
4185
4186
4187
4188
4189
4190MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9);
4191
4192
4193
4194
4195
4196MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8);
4197
4198
4199
4200
4201
4202MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24);
4203
4204
4205
4206
4207
4208MLXSW_ITEM_BUF(reg, rauht, mac, 0x6E, 6);
4209
4210static inline void mlxsw_reg_rauht_pack(char *payload,
4211 enum mlxsw_reg_rauht_op op, u16 rif,
4212 const char *mac)
4213{
4214 MLXSW_REG_ZERO(rauht, payload);
4215 mlxsw_reg_rauht_op_set(payload, op);
4216 mlxsw_reg_rauht_rif_set(payload, rif);
4217 mlxsw_reg_rauht_mac_memcpy_to(payload, mac);
4218}
4219
4220static inline void mlxsw_reg_rauht_pack4(char *payload,
4221 enum mlxsw_reg_rauht_op op, u16 rif,
4222 const char *mac, u32 dip)
4223{
4224 mlxsw_reg_rauht_pack(payload, op, rif, mac);
4225 mlxsw_reg_rauht_dip4_set(payload, dip);
4226}
4227
4228
4229
4230
4231
4232
4233
4234#define MLXSW_REG_RALEU_ID 0x8015
4235#define MLXSW_REG_RALEU_LEN 0x28
4236
4237static const struct mlxsw_reg_info mlxsw_reg_raleu = {
4238 .id = MLXSW_REG_RALEU_ID,
4239 .len = MLXSW_REG_RALEU_LEN,
4240};
4241
4242
4243
4244
4245
4246MLXSW_ITEM32(reg, raleu, protocol, 0x00, 24, 4);
4247
4248
4249
4250
4251
4252
4253MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16);
4254
4255
4256
4257
4258
4259MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24);
4260
4261
4262
4263
4264
4265MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13);
4266
4267
4268
4269
4270
4271MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24);
4272
4273
4274
4275
4276
4277MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13);
4278
4279static inline void mlxsw_reg_raleu_pack(char *payload,
4280 enum mlxsw_reg_ralxx_protocol protocol,
4281 u16 virtual_router,
4282 u32 adjacency_index, u16 ecmp_size,
4283 u32 new_adjacency_index,
4284 u16 new_ecmp_size)
4285{
4286 MLXSW_REG_ZERO(raleu, payload);
4287 mlxsw_reg_raleu_protocol_set(payload, protocol);
4288 mlxsw_reg_raleu_virtual_router_set(payload, virtual_router);
4289 mlxsw_reg_raleu_adjacency_index_set(payload, adjacency_index);
4290 mlxsw_reg_raleu_ecmp_size_set(payload, ecmp_size);
4291 mlxsw_reg_raleu_new_adjacency_index_set(payload, new_adjacency_index);
4292 mlxsw_reg_raleu_new_ecmp_size_set(payload, new_ecmp_size);
4293}
4294
4295
4296
4297
4298
4299
4300
4301
4302
4303
4304#define MLXSW_REG_RAUHTD_ID 0x8018
4305#define MLXSW_REG_RAUHTD_BASE_LEN 0x20
4306#define MLXSW_REG_RAUHTD_REC_LEN 0x20
4307#define MLXSW_REG_RAUHTD_REC_MAX_NUM 32
4308#define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \
4309 MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN)
4310#define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 4
4311
4312static const struct mlxsw_reg_info mlxsw_reg_rauhtd = {
4313 .id = MLXSW_REG_RAUHTD_ID,
4314 .len = MLXSW_REG_RAUHTD_LEN,
4315};
4316
4317#define MLXSW_REG_RAUHTD_FILTER_A BIT(0)
4318#define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3)
4319
4320
4321
4322
4323
4324
4325
4326
4327MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8);
4328
4329enum mlxsw_reg_rauhtd_op {
4330 MLXSW_REG_RAUHTD_OP_DUMP,
4331 MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR,
4332};
4333
4334
4335
4336
4337MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2);
4338
4339
4340
4341
4342
4343
4344
4345
4346
4347MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8);
4348
4349
4350
4351
4352
4353
4354MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1);
4355
4356enum mlxsw_reg_rauhtd_type {
4357 MLXSW_REG_RAUHTD_TYPE_IPV4,
4358 MLXSW_REG_RAUHTD_TYPE_IPV6,
4359};
4360
4361
4362
4363
4364
4365
4366
4367MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4);
4368
4369
4370
4371
4372
4373
4374MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16);
4375
4376static inline void mlxsw_reg_rauhtd_pack(char *payload,
4377 enum mlxsw_reg_rauhtd_type type)
4378{
4379 MLXSW_REG_ZERO(rauhtd, payload);
4380 mlxsw_reg_rauhtd_filter_fields_set(payload, MLXSW_REG_RAUHTD_FILTER_A);
4381 mlxsw_reg_rauhtd_op_set(payload, MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR);
4382 mlxsw_reg_rauhtd_num_rec_set(payload, MLXSW_REG_RAUHTD_REC_MAX_NUM);
4383 mlxsw_reg_rauhtd_entry_a_set(payload, 1);
4384 mlxsw_reg_rauhtd_type_set(payload, type);
4385}
4386
4387
4388
4389
4390
4391
4392
4393
4394
4395MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries,
4396 MLXSW_REG_RAUHTD_BASE_LEN, 28, 2,
4397 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false);
4398
4399
4400
4401
4402
4403
4404
4405MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2,
4406 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false);
4407
4408#define MLXSW_REG_RAUHTD_IPV4_ENT_LEN 0x8
4409
4410
4411
4412
4413
4414
4415MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1,
4416 MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false);
4417
4418
4419
4420
4421
4422MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0,
4423 16, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false);
4424
4425
4426
4427
4428
4429MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0,
4430 32, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x04, false);
4431
4432static inline void mlxsw_reg_rauhtd_ent_ipv4_unpack(char *payload,
4433 int ent_index, u16 *p_rif,
4434 u32 *p_dip)
4435{
4436 *p_rif = mlxsw_reg_rauhtd_ipv4_ent_rif_get(payload, ent_index);
4437 *p_dip = mlxsw_reg_rauhtd_ipv4_ent_dip_get(payload, ent_index);
4438}
4439
4440
4441
4442
4443
4444#define MLXSW_REG_MFCR_ID 0x9001
4445#define MLXSW_REG_MFCR_LEN 0x08
4446
4447static const struct mlxsw_reg_info mlxsw_reg_mfcr = {
4448 .id = MLXSW_REG_MFCR_ID,
4449 .len = MLXSW_REG_MFCR_LEN,
4450};
4451
4452enum mlxsw_reg_mfcr_pwm_frequency {
4453 MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00,
4454 MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01,
4455 MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02,
4456 MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40,
4457 MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41,
4458 MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42,
4459 MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43,
4460 MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44,
4461};
4462
4463
4464
4465
4466
4467MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 6);
4468
4469#define MLXSW_MFCR_TACHOS_MAX 10
4470
4471
4472
4473
4474
4475MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX);
4476
4477#define MLXSW_MFCR_PWMS_MAX 5
4478
4479
4480
4481
4482
4483MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX);
4484
4485static inline void
4486mlxsw_reg_mfcr_pack(char *payload,
4487 enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency)
4488{
4489 MLXSW_REG_ZERO(mfcr, payload);
4490 mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency);
4491}
4492
4493static inline void
4494mlxsw_reg_mfcr_unpack(char *payload,
4495 enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency,
4496 u16 *p_tacho_active, u8 *p_pwm_active)
4497{
4498 *p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload);
4499 *p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload);
4500 *p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload);
4501}
4502
4503
4504
4505
4506
4507#define MLXSW_REG_MFSC_ID 0x9002
4508#define MLXSW_REG_MFSC_LEN 0x08
4509
4510static const struct mlxsw_reg_info mlxsw_reg_mfsc = {
4511 .id = MLXSW_REG_MFSC_ID,
4512 .len = MLXSW_REG_MFSC_LEN,
4513};
4514
4515
4516
4517
4518
4519MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3);
4520
4521
4522
4523
4524
4525
4526MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8);
4527
4528static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm,
4529 u8 pwm_duty_cycle)
4530{
4531 MLXSW_REG_ZERO(mfsc, payload);
4532 mlxsw_reg_mfsc_pwm_set(payload, pwm);
4533 mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle);
4534}
4535
4536
4537
4538
4539
4540
4541#define MLXSW_REG_MFSM_ID 0x9003
4542#define MLXSW_REG_MFSM_LEN 0x08
4543
4544static const struct mlxsw_reg_info mlxsw_reg_mfsm = {
4545 .id = MLXSW_REG_MFSM_ID,
4546 .len = MLXSW_REG_MFSM_LEN,
4547};
4548
4549
4550
4551
4552
4553MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4);
4554
4555
4556
4557
4558
4559MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16);
4560
4561static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho)
4562{
4563 MLXSW_REG_ZERO(mfsm, payload);
4564 mlxsw_reg_mfsm_tacho_set(payload, tacho);
4565}
4566
4567
4568
4569
4570
4571
4572#define MLXSW_REG_MTCAP_ID 0x9009
4573#define MLXSW_REG_MTCAP_LEN 0x08
4574
4575static const struct mlxsw_reg_info mlxsw_reg_mtcap = {
4576 .id = MLXSW_REG_MTCAP_ID,
4577 .len = MLXSW_REG_MTCAP_LEN,
4578};
4579
4580
4581
4582
4583
4584
4585MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7);
4586
4587
4588
4589
4590
4591
4592
4593#define MLXSW_REG_MTMP_ID 0x900A
4594#define MLXSW_REG_MTMP_LEN 0x20
4595
4596static const struct mlxsw_reg_info mlxsw_reg_mtmp = {
4597 .id = MLXSW_REG_MTMP_ID,
4598 .len = MLXSW_REG_MTMP_LEN,
4599};
4600
4601
4602
4603
4604
4605
4606
4607MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 7);
4608
4609
4610#define MLXSW_REG_MTMP_TEMP_TO_MC(val) (val * 125)
4611
4612
4613
4614
4615
4616
4617MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16);
4618
4619
4620
4621
4622
4623MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1);
4624
4625
4626
4627
4628
4629MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1);
4630
4631
4632
4633
4634
4635
4636MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16);
4637
4638#define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8
4639
4640
4641
4642
4643
4644MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE);
4645
4646static inline void mlxsw_reg_mtmp_pack(char *payload, u8 sensor_index,
4647 bool max_temp_enable,
4648 bool max_temp_reset)
4649{
4650 MLXSW_REG_ZERO(mtmp, payload);
4651 mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index);
4652 mlxsw_reg_mtmp_mte_set(payload, max_temp_enable);
4653 mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset);
4654}
4655
4656static inline void mlxsw_reg_mtmp_unpack(char *payload, unsigned int *p_temp,
4657 unsigned int *p_max_temp,
4658 char *sensor_name)
4659{
4660 u16 temp;
4661
4662 if (p_temp) {
4663 temp = mlxsw_reg_mtmp_temperature_get(payload);
4664 *p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
4665 }
4666 if (p_max_temp) {
4667 temp = mlxsw_reg_mtmp_max_temperature_get(payload);
4668 *p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
4669 }
4670 if (sensor_name)
4671 mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name);
4672}
4673
4674
4675
4676
4677
4678
4679#define MLXSW_REG_MPAT_ID 0x901A
4680#define MLXSW_REG_MPAT_LEN 0x78
4681
4682static const struct mlxsw_reg_info mlxsw_reg_mpat = {
4683 .id = MLXSW_REG_MPAT_ID,
4684 .len = MLXSW_REG_MPAT_LEN,
4685};
4686
4687
4688
4689
4690
4691MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4);
4692
4693
4694
4695
4696
4697MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16);
4698
4699
4700
4701
4702
4703MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1);
4704
4705
4706
4707
4708
4709
4710
4711
4712
4713
4714MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1);
4715
4716
4717
4718
4719
4720
4721
4722
4723
4724MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1);
4725
4726static inline void mlxsw_reg_mpat_pack(char *payload, u8 pa_id,
4727 u16 system_port, bool e)
4728{
4729 MLXSW_REG_ZERO(mpat, payload);
4730 mlxsw_reg_mpat_pa_id_set(payload, pa_id);
4731 mlxsw_reg_mpat_system_port_set(payload, system_port);
4732 mlxsw_reg_mpat_e_set(payload, e);
4733 mlxsw_reg_mpat_qos_set(payload, 1);
4734 mlxsw_reg_mpat_be_set(payload, 1);
4735}
4736
4737
4738
4739
4740
4741
4742#define MLXSW_REG_MPAR_ID 0x901B
4743#define MLXSW_REG_MPAR_LEN 0x08
4744
4745static const struct mlxsw_reg_info mlxsw_reg_mpar = {
4746 .id = MLXSW_REG_MPAR_ID,
4747 .len = MLXSW_REG_MPAR_LEN,
4748};
4749
4750
4751
4752
4753
4754MLXSW_ITEM32(reg, mpar, local_port, 0x00, 16, 8);
4755
4756enum mlxsw_reg_mpar_i_e {
4757 MLXSW_REG_MPAR_TYPE_EGRESS,
4758 MLXSW_REG_MPAR_TYPE_INGRESS,
4759};
4760
4761
4762
4763
4764
4765MLXSW_ITEM32(reg, mpar, i_e, 0x00, 0, 4);
4766
4767
4768
4769
4770
4771
4772MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1);
4773
4774
4775
4776
4777
4778MLXSW_ITEM32(reg, mpar, pa_id, 0x04, 0, 4);
4779
4780static inline void mlxsw_reg_mpar_pack(char *payload, u8 local_port,
4781 enum mlxsw_reg_mpar_i_e i_e,
4782 bool enable, u8 pa_id)
4783{
4784 MLXSW_REG_ZERO(mpar, payload);
4785 mlxsw_reg_mpar_local_port_set(payload, local_port);
4786 mlxsw_reg_mpar_enable_set(payload, enable);
4787 mlxsw_reg_mpar_i_e_set(payload, i_e);
4788 mlxsw_reg_mpar_pa_id_set(payload, pa_id);
4789}
4790
4791
4792
4793
4794
4795#define MLXSW_REG_MLCR_ID 0x902B
4796#define MLXSW_REG_MLCR_LEN 0x0C
4797
4798static const struct mlxsw_reg_info mlxsw_reg_mlcr = {
4799 .id = MLXSW_REG_MLCR_ID,
4800 .len = MLXSW_REG_MLCR_LEN,
4801};
4802
4803
4804
4805
4806
4807MLXSW_ITEM32(reg, mlcr, local_port, 0x00, 16, 8);
4808
4809#define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF
4810
4811
4812
4813
4814
4815
4816
4817MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16);
4818
4819
4820
4821
4822
4823
4824MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16);
4825
4826static inline void mlxsw_reg_mlcr_pack(char *payload, u8 local_port,
4827 bool active)
4828{
4829 MLXSW_REG_ZERO(mlcr, payload);
4830 mlxsw_reg_mlcr_local_port_set(payload, local_port);
4831 mlxsw_reg_mlcr_beacon_duration_set(payload, active ?
4832 MLXSW_REG_MLCR_DURATION_MAX : 0);
4833}
4834
4835
4836
4837
4838
4839#define MLXSW_REG_SBPR_ID 0xB001
4840#define MLXSW_REG_SBPR_LEN 0x14
4841
4842static const struct mlxsw_reg_info mlxsw_reg_sbpr = {
4843 .id = MLXSW_REG_SBPR_ID,
4844 .len = MLXSW_REG_SBPR_LEN,
4845};
4846
4847
4848enum mlxsw_reg_sbxx_dir {
4849 MLXSW_REG_SBXX_DIR_INGRESS,
4850 MLXSW_REG_SBXX_DIR_EGRESS,
4851};
4852
4853
4854
4855
4856
4857MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2);
4858
4859
4860
4861
4862
4863MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4);
4864
4865
4866
4867
4868
4869MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24);
4870
4871enum mlxsw_reg_sbpr_mode {
4872 MLXSW_REG_SBPR_MODE_STATIC,
4873 MLXSW_REG_SBPR_MODE_DYNAMIC,
4874};
4875
4876
4877
4878
4879
4880MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4);
4881
4882static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool,
4883 enum mlxsw_reg_sbxx_dir dir,
4884 enum mlxsw_reg_sbpr_mode mode, u32 size)
4885{
4886 MLXSW_REG_ZERO(sbpr, payload);
4887 mlxsw_reg_sbpr_pool_set(payload, pool);
4888 mlxsw_reg_sbpr_dir_set(payload, dir);
4889 mlxsw_reg_sbpr_mode_set(payload, mode);
4890 mlxsw_reg_sbpr_size_set(payload, size);
4891}
4892
4893
4894
4895
4896
4897
4898
4899#define MLXSW_REG_SBCM_ID 0xB002
4900#define MLXSW_REG_SBCM_LEN 0x28
4901
4902static const struct mlxsw_reg_info mlxsw_reg_sbcm = {
4903 .id = MLXSW_REG_SBCM_ID,
4904 .len = MLXSW_REG_SBCM_LEN,
4905};
4906
4907
4908
4909
4910
4911
4912
4913MLXSW_ITEM32(reg, sbcm, local_port, 0x00, 16, 8);
4914
4915
4916
4917
4918
4919
4920
4921
4922
4923MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6);
4924
4925
4926
4927
4928
4929MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2);
4930
4931
4932
4933
4934
4935MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24);
4936
4937
4938#define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1
4939#define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14
4940
4941
4942
4943
4944
4945
4946
4947
4948
4949
4950
4951
4952MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24);
4953
4954
4955
4956
4957
4958MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4);
4959
4960static inline void mlxsw_reg_sbcm_pack(char *payload, u8 local_port, u8 pg_buff,
4961 enum mlxsw_reg_sbxx_dir dir,
4962 u32 min_buff, u32 max_buff, u8 pool)
4963{
4964 MLXSW_REG_ZERO(sbcm, payload);
4965 mlxsw_reg_sbcm_local_port_set(payload, local_port);
4966 mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff);
4967 mlxsw_reg_sbcm_dir_set(payload, dir);
4968 mlxsw_reg_sbcm_min_buff_set(payload, min_buff);
4969 mlxsw_reg_sbcm_max_buff_set(payload, max_buff);
4970 mlxsw_reg_sbcm_pool_set(payload, pool);
4971}
4972
4973
4974
4975
4976
4977
4978
4979#define MLXSW_REG_SBPM_ID 0xB003
4980#define MLXSW_REG_SBPM_LEN 0x28
4981
4982static const struct mlxsw_reg_info mlxsw_reg_sbpm = {
4983 .id = MLXSW_REG_SBPM_ID,
4984 .len = MLXSW_REG_SBPM_LEN,
4985};
4986
4987
4988
4989
4990
4991
4992
4993MLXSW_ITEM32(reg, sbpm, local_port, 0x00, 16, 8);
4994
4995
4996
4997
4998
4999MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4);
5000
5001
5002
5003
5004
5005MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2);
5006
5007
5008
5009
5010
5011MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24);
5012
5013
5014
5015
5016
5017
5018
5019MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1);
5020
5021
5022
5023
5024
5025
5026MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24);
5027
5028
5029
5030
5031
5032MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24);
5033
5034
5035
5036
5037
5038
5039
5040
5041
5042
5043
5044
5045MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24);
5046
5047static inline void mlxsw_reg_sbpm_pack(char *payload, u8 local_port, u8 pool,
5048 enum mlxsw_reg_sbxx_dir dir, bool clr,
5049 u32 min_buff, u32 max_buff)
5050{
5051 MLXSW_REG_ZERO(sbpm, payload);
5052 mlxsw_reg_sbpm_local_port_set(payload, local_port);
5053 mlxsw_reg_sbpm_pool_set(payload, pool);
5054 mlxsw_reg_sbpm_dir_set(payload, dir);
5055 mlxsw_reg_sbpm_clr_set(payload, clr);
5056 mlxsw_reg_sbpm_min_buff_set(payload, min_buff);
5057 mlxsw_reg_sbpm_max_buff_set(payload, max_buff);
5058}
5059
5060static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy,
5061 u32 *p_max_buff_occupancy)
5062{
5063 *p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload);
5064 *p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload);
5065}
5066
5067
5068
5069
5070
5071
5072
5073#define MLXSW_REG_SBMM_ID 0xB004
5074#define MLXSW_REG_SBMM_LEN 0x28
5075
5076static const struct mlxsw_reg_info mlxsw_reg_sbmm = {
5077 .id = MLXSW_REG_SBMM_ID,
5078 .len = MLXSW_REG_SBMM_LEN,
5079};
5080
5081
5082
5083
5084
5085MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4);
5086
5087
5088
5089
5090
5091MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24);
5092
5093
5094
5095
5096
5097
5098
5099
5100
5101
5102
5103
5104MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24);
5105
5106
5107
5108
5109
5110MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4);
5111
5112static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff,
5113 u32 max_buff, u8 pool)
5114{
5115 MLXSW_REG_ZERO(sbmm, payload);
5116 mlxsw_reg_sbmm_prio_set(payload, prio);
5117 mlxsw_reg_sbmm_min_buff_set(payload, min_buff);
5118 mlxsw_reg_sbmm_max_buff_set(payload, max_buff);
5119 mlxsw_reg_sbmm_pool_set(payload, pool);
5120}
5121
5122
5123
5124
5125
5126
5127
5128
5129
5130#define MLXSW_REG_SBSR_ID 0xB005
5131#define MLXSW_REG_SBSR_BASE_LEN 0x5C
5132#define MLXSW_REG_SBSR_REC_LEN 0x8
5133#define MLXSW_REG_SBSR_REC_MAX_COUNT 120
5134#define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN + \
5135 MLXSW_REG_SBSR_REC_LEN * \
5136 MLXSW_REG_SBSR_REC_MAX_COUNT)
5137
5138static const struct mlxsw_reg_info mlxsw_reg_sbsr = {
5139 .id = MLXSW_REG_SBSR_ID,
5140 .len = MLXSW_REG_SBSR_LEN,
5141};
5142
5143
5144
5145
5146
5147
5148
5149MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1);
5150
5151
5152
5153
5154
5155
5156
5157
5158MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1);
5159
5160
5161
5162
5163
5164
5165
5166
5167
5168MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1);
5169
5170
5171
5172
5173
5174
5175
5176
5177MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1);
5178
5179
5180
5181
5182
5183
5184
5185
5186
5187MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1);
5188
5189static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr)
5190{
5191 MLXSW_REG_ZERO(sbsr, payload);
5192 mlxsw_reg_sbsr_clr_set(payload, clr);
5193}
5194
5195
5196
5197
5198
5199MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN,
5200 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false);
5201
5202
5203
5204
5205
5206
5207MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN,
5208 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false);
5209
5210static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index,
5211 u32 *p_buff_occupancy,
5212 u32 *p_max_buff_occupancy)
5213{
5214 *p_buff_occupancy =
5215 mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index);
5216 *p_max_buff_occupancy =
5217 mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index);
5218}
5219
5220
5221
5222
5223
5224
5225
5226
5227
5228#define MLXSW_REG_SBIB_ID 0xB006
5229#define MLXSW_REG_SBIB_LEN 0x10
5230
5231static const struct mlxsw_reg_info mlxsw_reg_sbib = {
5232 .id = MLXSW_REG_SBIB_ID,
5233 .len = MLXSW_REG_SBIB_LEN,
5234};
5235
5236
5237
5238
5239
5240
5241MLXSW_ITEM32(reg, sbib, local_port, 0x00, 16, 8);
5242
5243
5244
5245
5246
5247
5248
5249MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24);
5250
5251static inline void mlxsw_reg_sbib_pack(char *payload, u8 local_port,
5252 u32 buff_size)
5253{
5254 MLXSW_REG_ZERO(sbib, payload);
5255 mlxsw_reg_sbib_local_port_set(payload, local_port);
5256 mlxsw_reg_sbib_buff_size_set(payload, buff_size);
5257}
5258
5259static inline const char *mlxsw_reg_id_str(u16 reg_id)
5260{
5261 switch (reg_id) {
5262 case MLXSW_REG_SGCR_ID:
5263 return "SGCR";
5264 case MLXSW_REG_SPAD_ID:
5265 return "SPAD";
5266 case MLXSW_REG_SMID_ID:
5267 return "SMID";
5268 case MLXSW_REG_SSPR_ID:
5269 return "SSPR";
5270 case MLXSW_REG_SFDAT_ID:
5271 return "SFDAT";
5272 case MLXSW_REG_SFD_ID:
5273 return "SFD";
5274 case MLXSW_REG_SFN_ID:
5275 return "SFN";
5276 case MLXSW_REG_SPMS_ID:
5277 return "SPMS";
5278 case MLXSW_REG_SPVID_ID:
5279 return "SPVID";
5280 case MLXSW_REG_SPVM_ID:
5281 return "SPVM";
5282 case MLXSW_REG_SPAFT_ID:
5283 return "SPAFT";
5284 case MLXSW_REG_SFGC_ID:
5285 return "SFGC";
5286 case MLXSW_REG_SFTR_ID:
5287 return "SFTR";
5288 case MLXSW_REG_SFDF_ID:
5289 return "SFDF";
5290 case MLXSW_REG_SLDR_ID:
5291 return "SLDR";
5292 case MLXSW_REG_SLCR_ID:
5293 return "SLCR";
5294 case MLXSW_REG_SLCOR_ID:
5295 return "SLCOR";
5296 case MLXSW_REG_SPMLR_ID:
5297 return "SPMLR";
5298 case MLXSW_REG_SVFA_ID:
5299 return "SVFA";
5300 case MLXSW_REG_SVPE_ID:
5301 return "SVPE";
5302 case MLXSW_REG_SFMR_ID:
5303 return "SFMR";
5304 case MLXSW_REG_SPVMLR_ID:
5305 return "SPVMLR";
5306 case MLXSW_REG_QTCT_ID:
5307 return "QTCT";
5308 case MLXSW_REG_QEEC_ID:
5309 return "QEEC";
5310 case MLXSW_REG_PMLP_ID:
5311 return "PMLP";
5312 case MLXSW_REG_PMTU_ID:
5313 return "PMTU";
5314 case MLXSW_REG_PTYS_ID:
5315 return "PTYS";
5316 case MLXSW_REG_PPAD_ID:
5317 return "PPAD";
5318 case MLXSW_REG_PAOS_ID:
5319 return "PAOS";
5320 case MLXSW_REG_PFCC_ID:
5321 return "PFCC";
5322 case MLXSW_REG_PPCNT_ID:
5323 return "PPCNT";
5324 case MLXSW_REG_PPTB_ID:
5325 return "PPTB";
5326 case MLXSW_REG_PBMC_ID:
5327 return "PBMC";
5328 case MLXSW_REG_PSPA_ID:
5329 return "PSPA";
5330 case MLXSW_REG_HTGT_ID:
5331 return "HTGT";
5332 case MLXSW_REG_HPKT_ID:
5333 return "HPKT";
5334 case MLXSW_REG_RGCR_ID:
5335 return "RGCR";
5336 case MLXSW_REG_RITR_ID:
5337 return "RITR";
5338 case MLXSW_REG_RATR_ID:
5339 return "RATR";
5340 case MLXSW_REG_RALTA_ID:
5341 return "RALTA";
5342 case MLXSW_REG_RALST_ID:
5343 return "RALST";
5344 case MLXSW_REG_RALTB_ID:
5345 return "RALTB";
5346 case MLXSW_REG_RALUE_ID:
5347 return "RALUE";
5348 case MLXSW_REG_RAUHT_ID:
5349 return "RAUHT";
5350 case MLXSW_REG_RALEU_ID:
5351 return "RALEU";
5352 case MLXSW_REG_RAUHTD_ID:
5353 return "RAUHTD";
5354 case MLXSW_REG_MFCR_ID:
5355 return "MFCR";
5356 case MLXSW_REG_MFSC_ID:
5357 return "MFSC";
5358 case MLXSW_REG_MFSM_ID:
5359 return "MFSM";
5360 case MLXSW_REG_MTCAP_ID:
5361 return "MTCAP";
5362 case MLXSW_REG_MPAT_ID:
5363 return "MPAT";
5364 case MLXSW_REG_MPAR_ID:
5365 return "MPAR";
5366 case MLXSW_REG_MTMP_ID:
5367 return "MTMP";
5368 case MLXSW_REG_MLCR_ID:
5369 return "MLCR";
5370 case MLXSW_REG_SBPR_ID:
5371 return "SBPR";
5372 case MLXSW_REG_SBCM_ID:
5373 return "SBCM";
5374 case MLXSW_REG_SBPM_ID:
5375 return "SBPM";
5376 case MLXSW_REG_SBMM_ID:
5377 return "SBMM";
5378 case MLXSW_REG_SBSR_ID:
5379 return "SBSR";
5380 case MLXSW_REG_SBIB_ID:
5381 return "SBIB";
5382 default:
5383 return "*UNKNOWN*";
5384 }
5385}
5386
5387
5388
5389
5390
5391#define MLXSW_REG_PUDE_LEN 0x10
5392
5393
5394
5395
5396
5397MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8);
5398
5399
5400
5401
5402
5403MLXSW_ITEM32(reg, pude, local_port, 0x00, 16, 8);
5404
5405
5406
5407
5408
5409
5410
5411
5412
5413
5414MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4);
5415
5416
5417
5418
5419
5420
5421
5422
5423
5424MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4);
5425
5426#endif
5427