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18#ifndef _HTT_H_
19#define _HTT_H_
20
21#include <linux/bug.h>
22#include <linux/interrupt.h>
23#include <linux/dmapool.h>
24#include <linux/hashtable.h>
25#include <linux/kfifo.h>
26#include <net/mac80211.h>
27
28#include "htc.h"
29#include "hw.h"
30#include "rx_desc.h"
31#include "hw.h"
32
33enum htt_dbg_stats_type {
34 HTT_DBG_STATS_WAL_PDEV_TXRX = 1 << 0,
35 HTT_DBG_STATS_RX_REORDER = 1 << 1,
36 HTT_DBG_STATS_RX_RATE_INFO = 1 << 2,
37 HTT_DBG_STATS_TX_PPDU_LOG = 1 << 3,
38 HTT_DBG_STATS_TX_RATE_INFO = 1 << 4,
39
40
41 HTT_DBG_NUM_STATS
42};
43
44enum htt_h2t_msg_type {
45 HTT_H2T_MSG_TYPE_VERSION_REQ = 0,
46 HTT_H2T_MSG_TYPE_TX_FRM = 1,
47 HTT_H2T_MSG_TYPE_RX_RING_CFG = 2,
48 HTT_H2T_MSG_TYPE_STATS_REQ = 3,
49 HTT_H2T_MSG_TYPE_SYNC = 4,
50 HTT_H2T_MSG_TYPE_AGGR_CFG = 5,
51 HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG = 6,
52
53
54
55 HTT_H2T_MSG_TYPE_MGMT_TX = 7,
56 HTT_H2T_MSG_TYPE_TX_FETCH_RESP = 11,
57
58 HTT_H2T_NUM_MSGS
59};
60
61struct htt_cmd_hdr {
62 u8 msg_type;
63} __packed;
64
65struct htt_ver_req {
66 u8 pad[sizeof(u32) - sizeof(struct htt_cmd_hdr)];
67} __packed;
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87struct htt_data_tx_desc_frag {
88 union {
89 struct double_word_addr {
90 __le32 paddr;
91 __le32 len;
92 } __packed dword_addr;
93 struct triple_word_addr {
94 __le32 paddr_lo;
95 __le16 paddr_hi;
96 __le16 len_16;
97 } __packed tword_addr;
98 } __packed;
99} __packed;
100
101struct htt_msdu_ext_desc {
102 __le32 tso_flag[3];
103 __le16 ip_identification;
104 u8 flags;
105 u8 reserved;
106 struct htt_data_tx_desc_frag frags[6];
107};
108
109#define HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE BIT(0)
110#define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV4_CSUM_ENABLE BIT(1)
111#define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV6_CSUM_ENABLE BIT(2)
112#define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE BIT(3)
113#define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE BIT(4)
114
115#define HTT_MSDU_CHECKSUM_ENABLE (HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE \
116 | HTT_MSDU_EXT_DESC_FLAG_UDP_IPV4_CSUM_ENABLE \
117 | HTT_MSDU_EXT_DESC_FLAG_UDP_IPV6_CSUM_ENABLE \
118 | HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE \
119 | HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE)
120
121enum htt_data_tx_desc_flags0 {
122 HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT = 1 << 0,
123 HTT_DATA_TX_DESC_FLAGS0_NO_AGGR = 1 << 1,
124 HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT = 1 << 2,
125 HTT_DATA_TX_DESC_FLAGS0_NO_CLASSIFY = 1 << 3,
126 HTT_DATA_TX_DESC_FLAGS0_RSVD0 = 1 << 4
127#define HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE_MASK 0xE0
128#define HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE_LSB 5
129};
130
131enum htt_data_tx_desc_flags1 {
132#define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_BITS 6
133#define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_MASK 0x003F
134#define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_LSB 0
135#define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_BITS 5
136#define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_MASK 0x07C0
137#define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_LSB 6
138 HTT_DATA_TX_DESC_FLAGS1_POSTPONED = 1 << 11,
139 HTT_DATA_TX_DESC_FLAGS1_MORE_IN_BATCH = 1 << 12,
140 HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD = 1 << 13,
141 HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD = 1 << 14,
142 HTT_DATA_TX_DESC_FLAGS1_RSVD1 = 1 << 15
143};
144
145enum htt_data_tx_ext_tid {
146 HTT_DATA_TX_EXT_TID_NON_QOS_MCAST_BCAST = 16,
147 HTT_DATA_TX_EXT_TID_MGMT = 17,
148 HTT_DATA_TX_EXT_TID_INVALID = 31
149};
150
151#define HTT_INVALID_PEERID 0xFFFF
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165struct htt_data_tx_desc {
166 u8 flags0;
167 __le16 flags1;
168 __le16 len;
169 __le16 id;
170 __le32 frags_paddr;
171 union {
172 __le32 peerid;
173 struct {
174 __le16 peerid;
175 __le16 freq;
176 } __packed offchan_tx;
177 } __packed;
178 u8 prefetch[0];
179} __packed;
180
181enum htt_rx_ring_flags {
182 HTT_RX_RING_FLAGS_MAC80211_HDR = 1 << 0,
183 HTT_RX_RING_FLAGS_MSDU_PAYLOAD = 1 << 1,
184 HTT_RX_RING_FLAGS_PPDU_START = 1 << 2,
185 HTT_RX_RING_FLAGS_PPDU_END = 1 << 3,
186 HTT_RX_RING_FLAGS_MPDU_START = 1 << 4,
187 HTT_RX_RING_FLAGS_MPDU_END = 1 << 5,
188 HTT_RX_RING_FLAGS_MSDU_START = 1 << 6,
189 HTT_RX_RING_FLAGS_MSDU_END = 1 << 7,
190 HTT_RX_RING_FLAGS_RX_ATTENTION = 1 << 8,
191 HTT_RX_RING_FLAGS_FRAG_INFO = 1 << 9,
192 HTT_RX_RING_FLAGS_UNICAST_RX = 1 << 10,
193 HTT_RX_RING_FLAGS_MULTICAST_RX = 1 << 11,
194 HTT_RX_RING_FLAGS_CTRL_RX = 1 << 12,
195 HTT_RX_RING_FLAGS_MGMT_RX = 1 << 13,
196 HTT_RX_RING_FLAGS_NULL_RX = 1 << 14,
197 HTT_RX_RING_FLAGS_PHY_DATA_RX = 1 << 15
198};
199
200#define HTT_RX_RING_SIZE_MIN 128
201#define HTT_RX_RING_SIZE_MAX 2048
202
203struct htt_rx_ring_setup_ring {
204 __le32 fw_idx_shadow_reg_paddr;
205 __le32 rx_ring_base_paddr;
206 __le16 rx_ring_len;
207 __le16 rx_ring_bufsize;
208 __le16 flags;
209 __le16 fw_idx_init_val;
210
211
212 __le16 mac80211_hdr_offset;
213 __le16 msdu_payload_offset;
214 __le16 ppdu_start_offset;
215 __le16 ppdu_end_offset;
216 __le16 mpdu_start_offset;
217 __le16 mpdu_end_offset;
218 __le16 msdu_start_offset;
219 __le16 msdu_end_offset;
220 __le16 rx_attention_offset;
221 __le16 frag_info_offset;
222} __packed;
223
224struct htt_rx_ring_setup_hdr {
225 u8 num_rings;
226 __le16 rsvd0;
227} __packed;
228
229struct htt_rx_ring_setup {
230 struct htt_rx_ring_setup_hdr hdr;
231 struct htt_rx_ring_setup_ring rings[0];
232} __packed;
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247struct htt_stats_req {
248 u8 upload_types[3];
249 u8 rsvd0;
250 u8 reset_types[3];
251 struct {
252 u8 mpdu_bytes;
253 u8 mpdu_num_msdus;
254 u8 msdu_bytes;
255 } __packed;
256 u8 stat_type;
257 __le32 cookie_lsb;
258 __le32 cookie_msb;
259} __packed;
260
261#define HTT_STATS_REQ_CFG_STAT_TYPE_INVALID 0xff
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282struct htt_oob_sync_req {
283 u8 sync_count;
284 __le16 rsvd0;
285} __packed;
286
287struct htt_aggr_conf {
288 u8 max_num_ampdu_subframes;
289
290 u8 max_num_amsdu_subframes;
291} __packed;
292
293#define HTT_MGMT_FRM_HDR_DOWNLOAD_LEN 32
294struct htt_mgmt_tx_desc_qca99x0 {
295 __le32 rate;
296} __packed;
297
298struct htt_mgmt_tx_desc {
299 u8 pad[sizeof(u32) - sizeof(struct htt_cmd_hdr)];
300 __le32 msdu_paddr;
301 __le32 desc_id;
302 __le32 len;
303 __le32 vdev_id;
304 u8 hdr[HTT_MGMT_FRM_HDR_DOWNLOAD_LEN];
305 union {
306 struct htt_mgmt_tx_desc_qca99x0 qca99x0;
307 } __packed;
308} __packed;
309
310enum htt_mgmt_tx_status {
311 HTT_MGMT_TX_STATUS_OK = 0,
312 HTT_MGMT_TX_STATUS_RETRY = 1,
313 HTT_MGMT_TX_STATUS_DROP = 2
314};
315
316
317
318enum htt_main_t2h_msg_type {
319 HTT_MAIN_T2H_MSG_TYPE_VERSION_CONF = 0x0,
320 HTT_MAIN_T2H_MSG_TYPE_RX_IND = 0x1,
321 HTT_MAIN_T2H_MSG_TYPE_RX_FLUSH = 0x2,
322 HTT_MAIN_T2H_MSG_TYPE_PEER_MAP = 0x3,
323 HTT_MAIN_T2H_MSG_TYPE_PEER_UNMAP = 0x4,
324 HTT_MAIN_T2H_MSG_TYPE_RX_ADDBA = 0x5,
325 HTT_MAIN_T2H_MSG_TYPE_RX_DELBA = 0x6,
326 HTT_MAIN_T2H_MSG_TYPE_TX_COMPL_IND = 0x7,
327 HTT_MAIN_T2H_MSG_TYPE_PKTLOG = 0x8,
328 HTT_MAIN_T2H_MSG_TYPE_STATS_CONF = 0x9,
329 HTT_MAIN_T2H_MSG_TYPE_RX_FRAG_IND = 0xa,
330 HTT_MAIN_T2H_MSG_TYPE_SEC_IND = 0xb,
331 HTT_MAIN_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd,
332 HTT_MAIN_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0xe,
333 HTT_MAIN_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND = 0xf,
334 HTT_MAIN_T2H_MSG_TYPE_RX_PN_IND = 0x10,
335 HTT_MAIN_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND = 0x11,
336 HTT_MAIN_T2H_MSG_TYPE_TEST,
337
338 HTT_MAIN_T2H_NUM_MSGS
339};
340
341enum htt_10x_t2h_msg_type {
342 HTT_10X_T2H_MSG_TYPE_VERSION_CONF = 0x0,
343 HTT_10X_T2H_MSG_TYPE_RX_IND = 0x1,
344 HTT_10X_T2H_MSG_TYPE_RX_FLUSH = 0x2,
345 HTT_10X_T2H_MSG_TYPE_PEER_MAP = 0x3,
346 HTT_10X_T2H_MSG_TYPE_PEER_UNMAP = 0x4,
347 HTT_10X_T2H_MSG_TYPE_RX_ADDBA = 0x5,
348 HTT_10X_T2H_MSG_TYPE_RX_DELBA = 0x6,
349 HTT_10X_T2H_MSG_TYPE_TX_COMPL_IND = 0x7,
350 HTT_10X_T2H_MSG_TYPE_PKTLOG = 0x8,
351 HTT_10X_T2H_MSG_TYPE_STATS_CONF = 0x9,
352 HTT_10X_T2H_MSG_TYPE_RX_FRAG_IND = 0xa,
353 HTT_10X_T2H_MSG_TYPE_SEC_IND = 0xb,
354 HTT_10X_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc,
355 HTT_10X_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd,
356 HTT_10X_T2H_MSG_TYPE_TEST = 0xe,
357 HTT_10X_T2H_MSG_TYPE_CHAN_CHANGE = 0xf,
358 HTT_10X_T2H_MSG_TYPE_AGGR_CONF = 0x11,
359 HTT_10X_T2H_MSG_TYPE_STATS_NOUPLOAD = 0x12,
360 HTT_10X_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0x13,
361
362 HTT_10X_T2H_NUM_MSGS
363};
364
365enum htt_tlv_t2h_msg_type {
366 HTT_TLV_T2H_MSG_TYPE_VERSION_CONF = 0x0,
367 HTT_TLV_T2H_MSG_TYPE_RX_IND = 0x1,
368 HTT_TLV_T2H_MSG_TYPE_RX_FLUSH = 0x2,
369 HTT_TLV_T2H_MSG_TYPE_PEER_MAP = 0x3,
370 HTT_TLV_T2H_MSG_TYPE_PEER_UNMAP = 0x4,
371 HTT_TLV_T2H_MSG_TYPE_RX_ADDBA = 0x5,
372 HTT_TLV_T2H_MSG_TYPE_RX_DELBA = 0x6,
373 HTT_TLV_T2H_MSG_TYPE_TX_COMPL_IND = 0x7,
374 HTT_TLV_T2H_MSG_TYPE_PKTLOG = 0x8,
375 HTT_TLV_T2H_MSG_TYPE_STATS_CONF = 0x9,
376 HTT_TLV_T2H_MSG_TYPE_RX_FRAG_IND = 0xa,
377 HTT_TLV_T2H_MSG_TYPE_SEC_IND = 0xb,
378 HTT_TLV_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc,
379 HTT_TLV_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd,
380 HTT_TLV_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0xe,
381 HTT_TLV_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND = 0xf,
382 HTT_TLV_T2H_MSG_TYPE_RX_PN_IND = 0x10,
383 HTT_TLV_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND = 0x11,
384 HTT_TLV_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND = 0x12,
385
386 HTT_TLV_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE = 0x14,
387 HTT_TLV_T2H_MSG_TYPE_CHAN_CHANGE = 0x15,
388 HTT_TLV_T2H_MSG_TYPE_RX_OFLD_PKT_ERR = 0x16,
389 HTT_TLV_T2H_MSG_TYPE_TEST,
390
391 HTT_TLV_T2H_NUM_MSGS
392};
393
394enum htt_10_4_t2h_msg_type {
395 HTT_10_4_T2H_MSG_TYPE_VERSION_CONF = 0x0,
396 HTT_10_4_T2H_MSG_TYPE_RX_IND = 0x1,
397 HTT_10_4_T2H_MSG_TYPE_RX_FLUSH = 0x2,
398 HTT_10_4_T2H_MSG_TYPE_PEER_MAP = 0x3,
399 HTT_10_4_T2H_MSG_TYPE_PEER_UNMAP = 0x4,
400 HTT_10_4_T2H_MSG_TYPE_RX_ADDBA = 0x5,
401 HTT_10_4_T2H_MSG_TYPE_RX_DELBA = 0x6,
402 HTT_10_4_T2H_MSG_TYPE_TX_COMPL_IND = 0x7,
403 HTT_10_4_T2H_MSG_TYPE_PKTLOG = 0x8,
404 HTT_10_4_T2H_MSG_TYPE_STATS_CONF = 0x9,
405 HTT_10_4_T2H_MSG_TYPE_RX_FRAG_IND = 0xa,
406 HTT_10_4_T2H_MSG_TYPE_SEC_IND = 0xb,
407 HTT_10_4_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc,
408 HTT_10_4_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd,
409 HTT_10_4_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0xe,
410 HTT_10_4_T2H_MSG_TYPE_CHAN_CHANGE = 0xf,
411 HTT_10_4_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND = 0x10,
412 HTT_10_4_T2H_MSG_TYPE_RX_PN_IND = 0x11,
413 HTT_10_4_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND = 0x12,
414 HTT_10_4_T2H_MSG_TYPE_TEST = 0x13,
415 HTT_10_4_T2H_MSG_TYPE_EN_STATS = 0x14,
416 HTT_10_4_T2H_MSG_TYPE_AGGR_CONF = 0x15,
417 HTT_10_4_T2H_MSG_TYPE_TX_FETCH_IND = 0x16,
418 HTT_10_4_T2H_MSG_TYPE_TX_FETCH_CONFIRM = 0x17,
419 HTT_10_4_T2H_MSG_TYPE_STATS_NOUPLOAD = 0x18,
420
421 HTT_10_4_T2H_MSG_TYPE_TX_MODE_SWITCH_IND = 0x30,
422
423 HTT_10_4_T2H_NUM_MSGS
424};
425
426enum htt_t2h_msg_type {
427 HTT_T2H_MSG_TYPE_VERSION_CONF,
428 HTT_T2H_MSG_TYPE_RX_IND,
429 HTT_T2H_MSG_TYPE_RX_FLUSH,
430 HTT_T2H_MSG_TYPE_PEER_MAP,
431 HTT_T2H_MSG_TYPE_PEER_UNMAP,
432 HTT_T2H_MSG_TYPE_RX_ADDBA,
433 HTT_T2H_MSG_TYPE_RX_DELBA,
434 HTT_T2H_MSG_TYPE_TX_COMPL_IND,
435 HTT_T2H_MSG_TYPE_PKTLOG,
436 HTT_T2H_MSG_TYPE_STATS_CONF,
437 HTT_T2H_MSG_TYPE_RX_FRAG_IND,
438 HTT_T2H_MSG_TYPE_SEC_IND,
439 HTT_T2H_MSG_TYPE_RC_UPDATE_IND,
440 HTT_T2H_MSG_TYPE_TX_INSPECT_IND,
441 HTT_T2H_MSG_TYPE_MGMT_TX_COMPLETION,
442 HTT_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND,
443 HTT_T2H_MSG_TYPE_RX_PN_IND,
444 HTT_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND,
445 HTT_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND,
446 HTT_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE,
447 HTT_T2H_MSG_TYPE_CHAN_CHANGE,
448 HTT_T2H_MSG_TYPE_RX_OFLD_PKT_ERR,
449 HTT_T2H_MSG_TYPE_AGGR_CONF,
450 HTT_T2H_MSG_TYPE_STATS_NOUPLOAD,
451 HTT_T2H_MSG_TYPE_TEST,
452 HTT_T2H_MSG_TYPE_EN_STATS,
453 HTT_T2H_MSG_TYPE_TX_FETCH_IND,
454 HTT_T2H_MSG_TYPE_TX_FETCH_CONFIRM,
455 HTT_T2H_MSG_TYPE_TX_MODE_SWITCH_IND,
456
457 HTT_T2H_NUM_MSGS
458};
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465struct htt_resp_hdr {
466 u8 msg_type;
467} __packed;
468
469#define HTT_RESP_HDR_MSG_TYPE_OFFSET 0
470#define HTT_RESP_HDR_MSG_TYPE_MASK 0xff
471#define HTT_RESP_HDR_MSG_TYPE_LSB 0
472
473
474struct htt_ver_resp {
475 u8 minor;
476 u8 major;
477 u8 rsvd0;
478} __packed;
479
480struct htt_mgmt_tx_completion {
481 u8 rsvd0;
482 u8 rsvd1;
483 u8 rsvd2;
484 __le32 desc_id;
485 __le32 status;
486} __packed;
487
488#define HTT_RX_INDICATION_INFO0_EXT_TID_MASK (0x1F)
489#define HTT_RX_INDICATION_INFO0_EXT_TID_LSB (0)
490#define HTT_RX_INDICATION_INFO0_FLUSH_VALID (1 << 5)
491#define HTT_RX_INDICATION_INFO0_RELEASE_VALID (1 << 6)
492
493#define HTT_RX_INDICATION_INFO1_FLUSH_START_SEQNO_MASK 0x0000003F
494#define HTT_RX_INDICATION_INFO1_FLUSH_START_SEQNO_LSB 0
495#define HTT_RX_INDICATION_INFO1_FLUSH_END_SEQNO_MASK 0x00000FC0
496#define HTT_RX_INDICATION_INFO1_FLUSH_END_SEQNO_LSB 6
497#define HTT_RX_INDICATION_INFO1_RELEASE_START_SEQNO_MASK 0x0003F000
498#define HTT_RX_INDICATION_INFO1_RELEASE_START_SEQNO_LSB 12
499#define HTT_RX_INDICATION_INFO1_RELEASE_END_SEQNO_MASK 0x00FC0000
500#define HTT_RX_INDICATION_INFO1_RELEASE_END_SEQNO_LSB 18
501#define HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES_MASK 0xFF000000
502#define HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES_LSB 24
503
504struct htt_rx_indication_hdr {
505 u8 info0;
506 __le16 peer_id;
507 __le32 info1;
508} __packed;
509
510#define HTT_RX_INDICATION_INFO0_PHY_ERR_VALID (1 << 0)
511#define HTT_RX_INDICATION_INFO0_LEGACY_RATE_MASK (0x1E)
512#define HTT_RX_INDICATION_INFO0_LEGACY_RATE_LSB (1)
513#define HTT_RX_INDICATION_INFO0_LEGACY_RATE_CCK (1 << 5)
514#define HTT_RX_INDICATION_INFO0_END_VALID (1 << 6)
515#define HTT_RX_INDICATION_INFO0_START_VALID (1 << 7)
516
517#define HTT_RX_INDICATION_INFO1_VHT_SIG_A1_MASK 0x00FFFFFF
518#define HTT_RX_INDICATION_INFO1_VHT_SIG_A1_LSB 0
519#define HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE_MASK 0xFF000000
520#define HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE_LSB 24
521
522#define HTT_RX_INDICATION_INFO2_VHT_SIG_A1_MASK 0x00FFFFFF
523#define HTT_RX_INDICATION_INFO2_VHT_SIG_A1_LSB 0
524#define HTT_RX_INDICATION_INFO2_SERVICE_MASK 0xFF000000
525#define HTT_RX_INDICATION_INFO2_SERVICE_LSB 24
526
527enum htt_rx_legacy_rate {
528 HTT_RX_OFDM_48 = 0,
529 HTT_RX_OFDM_24 = 1,
530 HTT_RX_OFDM_12,
531 HTT_RX_OFDM_6,
532 HTT_RX_OFDM_54,
533 HTT_RX_OFDM_36,
534 HTT_RX_OFDM_18,
535 HTT_RX_OFDM_9,
536
537
538 HTT_RX_CCK_11_LP = 0,
539 HTT_RX_CCK_5_5_LP = 1,
540 HTT_RX_CCK_2_LP,
541 HTT_RX_CCK_1_LP,
542
543 HTT_RX_CCK_11_SP,
544 HTT_RX_CCK_5_5_SP,
545 HTT_RX_CCK_2_SP
546};
547
548enum htt_rx_legacy_rate_type {
549 HTT_RX_LEGACY_RATE_OFDM = 0,
550 HTT_RX_LEGACY_RATE_CCK
551};
552
553enum htt_rx_preamble_type {
554 HTT_RX_LEGACY = 0x4,
555 HTT_RX_HT = 0x8,
556 HTT_RX_HT_WITH_TXBF = 0x9,
557 HTT_RX_VHT = 0xC,
558 HTT_RX_VHT_WITH_TXBF = 0xD,
559};
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571struct htt_rx_indication_ppdu {
572 u8 combined_rssi;
573 u8 sub_usec_timestamp;
574 u8 phy_err_code;
575 u8 info0;
576 struct {
577 u8 pri20_db;
578 u8 ext20_db;
579 u8 ext40_db;
580 u8 ext80_db;
581 } __packed rssi_chains[4];
582 __le32 tsf;
583 __le32 usec_timestamp;
584 __le32 info1;
585 __le32 info2;
586} __packed;
587
588enum htt_rx_mpdu_status {
589 HTT_RX_IND_MPDU_STATUS_UNKNOWN = 0x0,
590 HTT_RX_IND_MPDU_STATUS_OK,
591 HTT_RX_IND_MPDU_STATUS_ERR_FCS,
592 HTT_RX_IND_MPDU_STATUS_ERR_DUP,
593 HTT_RX_IND_MPDU_STATUS_ERR_REPLAY,
594 HTT_RX_IND_MPDU_STATUS_ERR_INV_PEER,
595
596 HTT_RX_IND_MPDU_STATUS_UNAUTH_PEER,
597 HTT_RX_IND_MPDU_STATUS_OUT_OF_SYNC,
598
599 HTT_RX_IND_MPDU_STATUS_MGMT_CTRL,
600 HTT_RX_IND_MPDU_STATUS_TKIP_MIC_ERR,
601 HTT_RX_IND_MPDU_STATUS_DECRYPT_ERR,
602 HTT_RX_IND_MPDU_STATUS_MPDU_LENGTH_ERR,
603 HTT_RX_IND_MPDU_STATUS_ENCRYPT_REQUIRED_ERR,
604 HTT_RX_IND_MPDU_STATUS_PRIVACY_ERR,
605
606
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608
609
610 HTT_RX_IND_MPDU_STATUS_ERR_MISC = 0xFF
611};
612
613struct htt_rx_indication_mpdu_range {
614 u8 mpdu_count;
615 u8 mpdu_range_status;
616 u8 pad0;
617 u8 pad1;
618} __packed;
619
620struct htt_rx_indication_prefix {
621 __le16 fw_rx_desc_bytes;
622 u8 pad0;
623 u8 pad1;
624};
625
626struct htt_rx_indication {
627 struct htt_rx_indication_hdr hdr;
628 struct htt_rx_indication_ppdu ppdu;
629 struct htt_rx_indication_prefix prefix;
630
631
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635
636
637 struct fw_rx_desc_base fw_desc;
638
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641
642
643 struct htt_rx_indication_mpdu_range mpdu_ranges[0];
644} __packed;
645
646static inline struct htt_rx_indication_mpdu_range *
647 htt_rx_ind_get_mpdu_ranges(struct htt_rx_indication *rx_ind)
648{
649 void *ptr = rx_ind;
650
651 ptr += sizeof(rx_ind->hdr)
652 + sizeof(rx_ind->ppdu)
653 + sizeof(rx_ind->prefix)
654 + roundup(__le16_to_cpu(rx_ind->prefix.fw_rx_desc_bytes), 4);
655 return ptr;
656}
657
658enum htt_rx_flush_mpdu_status {
659 HTT_RX_FLUSH_MPDU_DISCARD = 0,
660 HTT_RX_FLUSH_MPDU_REORDER = 1,
661};
662
663
664
665
666
667
668
669struct htt_rx_flush {
670 __le16 peer_id;
671 u8 tid;
672 u8 rsvd0;
673 u8 mpdu_status;
674 u8 seq_num_start;
675 u8 seq_num_end;
676};
677
678struct htt_rx_peer_map {
679 u8 vdev_id;
680 __le16 peer_id;
681 u8 addr[6];
682 u8 rsvd0;
683 u8 rsvd1;
684} __packed;
685
686struct htt_rx_peer_unmap {
687 u8 rsvd0;
688 __le16 peer_id;
689} __packed;
690
691enum htt_security_types {
692 HTT_SECURITY_NONE,
693 HTT_SECURITY_WEP128,
694 HTT_SECURITY_WEP104,
695 HTT_SECURITY_WEP40,
696 HTT_SECURITY_TKIP,
697 HTT_SECURITY_TKIP_NOMIC,
698 HTT_SECURITY_AES_CCMP,
699 HTT_SECURITY_WAPI,
700
701 HTT_NUM_SECURITY_TYPES
702};
703
704enum htt_security_flags {
705#define HTT_SECURITY_TYPE_MASK 0x7F
706#define HTT_SECURITY_TYPE_LSB 0
707 HTT_SECURITY_IS_UNICAST = 1 << 7
708};
709
710struct htt_security_indication {
711 union {
712
713 u8 flags;
714 struct {
715 u8 security_type:7,
716 is_unicast:1;
717 } __packed;
718 } __packed;
719 __le16 peer_id;
720 u8 michael_key[8];
721 u8 wapi_rsc[16];
722} __packed;
723
724#define HTT_RX_BA_INFO0_TID_MASK 0x000F
725#define HTT_RX_BA_INFO0_TID_LSB 0
726#define HTT_RX_BA_INFO0_PEER_ID_MASK 0xFFF0
727#define HTT_RX_BA_INFO0_PEER_ID_LSB 4
728
729struct htt_rx_addba {
730 u8 window_size;
731 __le16 info0;
732} __packed;
733
734struct htt_rx_delba {
735 u8 rsvd0;
736 __le16 info0;
737} __packed;
738
739enum htt_data_tx_status {
740 HTT_DATA_TX_STATUS_OK = 0,
741 HTT_DATA_TX_STATUS_DISCARD = 1,
742 HTT_DATA_TX_STATUS_NO_ACK = 2,
743 HTT_DATA_TX_STATUS_POSTPONE = 3,
744 HTT_DATA_TX_STATUS_DOWNLOAD_FAIL = 128
745};
746
747enum htt_data_tx_flags {
748#define HTT_DATA_TX_STATUS_MASK 0x07
749#define HTT_DATA_TX_STATUS_LSB 0
750#define HTT_DATA_TX_TID_MASK 0x78
751#define HTT_DATA_TX_TID_LSB 3
752 HTT_DATA_TX_TID_INVALID = 1 << 7
753};
754
755#define HTT_TX_COMPL_INV_MSDU_ID 0xFFFF
756
757struct htt_data_tx_completion {
758 union {
759 u8 flags;
760 struct {
761 u8 status:3,
762 tid:4,
763 tid_invalid:1;
764 } __packed;
765 } __packed;
766 u8 num_msdus;
767 u8 rsvd0;
768 __le16 msdus[0];
769} __packed;
770
771struct htt_tx_compl_ind_base {
772 u32 hdr;
773 u16 payload[1];
774} __packed;
775
776struct htt_rc_tx_done_params {
777 u32 rate_code;
778 u32 rate_code_flags;
779 u32 flags;
780 u32 num_enqued;
781 u32 num_retries;
782 u32 num_failed;
783 u32 ack_rssi;
784 u32 time_stamp;
785 u32 is_probe;
786};
787
788struct htt_rc_update {
789 u8 vdev_id;
790 __le16 peer_id;
791 u8 addr[6];
792 u8 num_elems;
793 u8 rsvd0;
794 struct htt_rc_tx_done_params params[0];
795} __packed;
796
797
798struct htt_rx_fragment_indication {
799 union {
800 u8 info0;
801 struct {
802 u8 ext_tid:5,
803 flush_valid:1;
804 } __packed;
805 } __packed;
806 __le16 peer_id;
807 __le32 info1;
808 __le16 fw_rx_desc_bytes;
809 __le16 rsvd0;
810
811 u8 fw_msdu_rx_desc[0];
812} __packed;
813
814#define HTT_RX_FRAG_IND_INFO0_EXT_TID_MASK 0x1F
815#define HTT_RX_FRAG_IND_INFO0_EXT_TID_LSB 0
816#define HTT_RX_FRAG_IND_INFO0_FLUSH_VALID_MASK 0x20
817#define HTT_RX_FRAG_IND_INFO0_FLUSH_VALID_LSB 5
818
819#define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_START_MASK 0x0000003F
820#define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_START_LSB 0
821#define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_END_MASK 0x00000FC0
822#define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_END_LSB 6
823
824struct htt_rx_pn_ind {
825 __le16 peer_id;
826 u8 tid;
827 u8 seqno_start;
828 u8 seqno_end;
829 u8 pn_ie_count;
830 u8 reserved;
831 u8 pn_ies[0];
832} __packed;
833
834struct htt_rx_offload_msdu {
835 __le16 msdu_len;
836 __le16 peer_id;
837 u8 vdev_id;
838 u8 tid;
839 u8 fw_desc;
840 u8 payload[0];
841} __packed;
842
843struct htt_rx_offload_ind {
844 u8 reserved;
845 __le16 msdu_count;
846} __packed;
847
848struct htt_rx_in_ord_msdu_desc {
849 __le32 msdu_paddr;
850 __le16 msdu_len;
851 u8 fw_desc;
852 u8 reserved;
853} __packed;
854
855struct htt_rx_in_ord_ind {
856 u8 info;
857 __le16 peer_id;
858 u8 vdev_id;
859 u8 reserved;
860 __le16 msdu_count;
861 struct htt_rx_in_ord_msdu_desc msdu_descs[0];
862} __packed;
863
864#define HTT_RX_IN_ORD_IND_INFO_TID_MASK 0x0000001f
865#define HTT_RX_IN_ORD_IND_INFO_TID_LSB 0
866#define HTT_RX_IN_ORD_IND_INFO_OFFLOAD_MASK 0x00000020
867#define HTT_RX_IN_ORD_IND_INFO_OFFLOAD_LSB 5
868#define HTT_RX_IN_ORD_IND_INFO_FRAG_MASK 0x00000040
869#define HTT_RX_IN_ORD_IND_INFO_FRAG_LSB 6
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904
905struct htt_rx_test {
906 u8 num_ints;
907 __le16 num_chars;
908
909
910
911
912 u8 payload[0];
913} __packed;
914
915static inline __le32 *htt_rx_test_get_ints(struct htt_rx_test *rx_test)
916{
917 return (__le32 *)rx_test->payload;
918}
919
920static inline u8 *htt_rx_test_get_chars(struct htt_rx_test *rx_test)
921{
922 return rx_test->payload + (rx_test->num_ints * sizeof(__le32));
923}
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942
943
944struct htt_pktlog_msg {
945 u8 pad[3];
946 u8 payload[0];
947} __packed;
948
949struct htt_dbg_stats_rx_reorder_stats {
950
951 __le32 deliver_non_qos;
952
953
954 __le32 deliver_in_order;
955
956
957 __le32 deliver_flush_timeout;
958
959
960 __le32 deliver_flush_oow;
961
962
963 __le32 deliver_flush_delba;
964
965
966 __le32 fcs_error;
967
968
969 __le32 mgmt_ctrl;
970
971
972 __le32 invalid_peer;
973
974
975 __le32 dup_non_aggr;
976
977
978 __le32 dup_past;
979
980
981 __le32 dup_in_reorder;
982
983
984 __le32 reorder_timeout;
985
986
987 __le32 invalid_bar_ssn;
988
989
990 __le32 ssn_reset;
991};
992
993struct htt_dbg_stats_wal_tx_stats {
994
995 __le32 comp_queued;
996
997
998 __le32 comp_delivered;
999
1000
1001 __le32 msdu_enqued;
1002
1003
1004 __le32 mpdu_enqued;
1005
1006
1007 __le32 wmm_drop;
1008
1009
1010 __le32 local_enqued;
1011
1012
1013 __le32 local_freed;
1014
1015
1016 __le32 hw_queued;
1017
1018
1019 __le32 hw_reaped;
1020
1021
1022 __le32 underrun;
1023
1024
1025 __le32 tx_abort;
1026
1027
1028 __le32 mpdus_requed;
1029
1030
1031 __le32 tx_ko;
1032
1033
1034 __le32 data_rc;
1035
1036
1037 __le32 self_triggers;
1038
1039
1040 __le32 sw_retry_failure;
1041
1042
1043 __le32 illgl_rate_phy_err;
1044
1045
1046 __le32 pdev_cont_xretry;
1047
1048
1049 __le32 pdev_tx_timeout;
1050
1051
1052 __le32 pdev_resets;
1053
1054 __le32 phy_underrun;
1055
1056
1057 __le32 txop_ovf;
1058} __packed;
1059
1060struct htt_dbg_stats_wal_rx_stats {
1061
1062 __le32 mid_ppdu_route_change;
1063
1064
1065 __le32 status_rcvd;
1066
1067
1068 __le32 r0_frags;
1069 __le32 r1_frags;
1070 __le32 r2_frags;
1071 __le32 r3_frags;
1072
1073
1074 __le32 htt_msdus;
1075 __le32 htt_mpdus;
1076
1077
1078 __le32 loc_msdus;
1079 __le32 loc_mpdus;
1080
1081
1082 __le32 oversize_amsdu;
1083
1084
1085 __le32 phy_errs;
1086
1087
1088 __le32 phy_err_drop;
1089
1090
1091 __le32 mpdu_errs;
1092} __packed;
1093
1094struct htt_dbg_stats_wal_peer_stats {
1095 __le32 dummy;
1096} __packed;
1097
1098struct htt_dbg_stats_wal_pdev_txrx {
1099 struct htt_dbg_stats_wal_tx_stats tx_stats;
1100 struct htt_dbg_stats_wal_rx_stats rx_stats;
1101 struct htt_dbg_stats_wal_peer_stats peer_stats;
1102} __packed;
1103
1104struct htt_dbg_stats_rx_rate_info {
1105 __le32 mcs[10];
1106 __le32 sgi[10];
1107 __le32 nss[4];
1108 __le32 stbc[10];
1109 __le32 bw[3];
1110 __le32 pream[6];
1111 __le32 ldpc;
1112 __le32 txbf;
1113};
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1133
1134
1135
1136enum htt_dbg_stats_status {
1137 HTT_DBG_STATS_STATUS_PRESENT = 0,
1138 HTT_DBG_STATS_STATUS_PARTIAL = 1,
1139 HTT_DBG_STATS_STATUS_ERROR = 2,
1140 HTT_DBG_STATS_STATUS_INVALID = 3,
1141 HTT_DBG_STATS_STATUS_SERIES_DONE = 7
1142};
1143
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1218
1219
1220#define HTT_STATS_CONF_ITEM_INFO_STAT_TYPE_MASK 0x1F
1221#define HTT_STATS_CONF_ITEM_INFO_STAT_TYPE_LSB 0
1222#define HTT_STATS_CONF_ITEM_INFO_STATUS_MASK 0xE0
1223#define HTT_STATS_CONF_ITEM_INFO_STATUS_LSB 5
1224
1225struct htt_stats_conf_item {
1226 union {
1227 u8 info;
1228 struct {
1229 u8 stat_type:5;
1230 u8 status:3;
1231 } __packed;
1232 } __packed;
1233 u8 pad;
1234 __le16 length;
1235 u8 payload[0];
1236} __packed;
1237
1238struct htt_stats_conf {
1239 u8 pad[3];
1240 __le32 cookie_lsb;
1241 __le32 cookie_msb;
1242
1243
1244 struct htt_stats_conf_item items[0];
1245} __packed;
1246
1247static inline struct htt_stats_conf_item *htt_stats_conf_next_item(
1248 const struct htt_stats_conf_item *item)
1249{
1250 return (void *)item + sizeof(*item) + roundup(item->length, 4);
1251}
1252
1253
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1300
1301
1302struct htt_frag_desc_bank_id {
1303 __le16 bank_min_id;
1304 __le16 bank_max_id;
1305} __packed;
1306
1307
1308
1309#define HTT_FRAG_DESC_BANK_MAX 4
1310
1311#define HTT_FRAG_DESC_BANK_CFG_INFO_PDEV_ID_MASK 0x03
1312#define HTT_FRAG_DESC_BANK_CFG_INFO_PDEV_ID_LSB 0
1313#define HTT_FRAG_DESC_BANK_CFG_INFO_SWAP BIT(2)
1314#define HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_VALID BIT(3)
1315#define HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_DEPTH_TYPE_MASK BIT(4)
1316#define HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_DEPTH_TYPE_LSB 4
1317
1318enum htt_q_depth_type {
1319 HTT_Q_DEPTH_TYPE_BYTES = 0,
1320 HTT_Q_DEPTH_TYPE_MSDUS = 1,
1321};
1322
1323#define HTT_TX_Q_STATE_NUM_PEERS (TARGET_10_4_NUM_QCACHE_PEERS_MAX + \
1324 TARGET_10_4_NUM_VDEVS)
1325#define HTT_TX_Q_STATE_NUM_TIDS 8
1326#define HTT_TX_Q_STATE_ENTRY_SIZE 1
1327#define HTT_TX_Q_STATE_ENTRY_MULTIPLIER 0
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340struct htt_q_state_conf {
1341 __le32 paddr;
1342 __le16 num_peers;
1343 __le16 num_tids;
1344 u8 record_size;
1345 u8 record_multiplier;
1346 u8 pad[2];
1347} __packed;
1348
1349struct htt_frag_desc_bank_cfg {
1350 u8 info;
1351 u8 num_banks;
1352 u8 desc_size;
1353 __le32 bank_base_addrs[HTT_FRAG_DESC_BANK_MAX];
1354 struct htt_frag_desc_bank_id bank_id[HTT_FRAG_DESC_BANK_MAX];
1355 struct htt_q_state_conf q_state;
1356} __packed;
1357
1358#define HTT_TX_Q_STATE_ENTRY_COEFFICIENT 128
1359#define HTT_TX_Q_STATE_ENTRY_FACTOR_MASK 0x3f
1360#define HTT_TX_Q_STATE_ENTRY_FACTOR_LSB 0
1361#define HTT_TX_Q_STATE_ENTRY_EXP_MASK 0xc0
1362#define HTT_TX_Q_STATE_ENTRY_EXP_LSB 6
1363
1364
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1381
1382
1383
1384
1385struct htt_q_state {
1386 u8 count[HTT_TX_Q_STATE_NUM_TIDS][HTT_TX_Q_STATE_NUM_PEERS];
1387 u32 map[HTT_TX_Q_STATE_NUM_TIDS][(HTT_TX_Q_STATE_NUM_PEERS + 31) / 32];
1388 __le32 seq;
1389} __packed;
1390
1391#define HTT_TX_FETCH_RECORD_INFO_PEER_ID_MASK 0x0fff
1392#define HTT_TX_FETCH_RECORD_INFO_PEER_ID_LSB 0
1393#define HTT_TX_FETCH_RECORD_INFO_TID_MASK 0xf000
1394#define HTT_TX_FETCH_RECORD_INFO_TID_LSB 12
1395
1396struct htt_tx_fetch_record {
1397 __le16 info;
1398 __le16 num_msdus;
1399 __le32 num_bytes;
1400} __packed;
1401
1402struct htt_tx_fetch_ind {
1403 u8 pad0;
1404 __le16 fetch_seq_num;
1405 __le32 token;
1406 __le16 num_resp_ids;
1407 __le16 num_records;
1408 struct htt_tx_fetch_record records[0];
1409 __le32 resp_ids[0];
1410} __packed;
1411
1412static inline void *
1413ath10k_htt_get_tx_fetch_ind_resp_ids(struct htt_tx_fetch_ind *ind)
1414{
1415 return (void *)&ind->records[le16_to_cpu(ind->num_records)];
1416}
1417
1418struct htt_tx_fetch_resp {
1419 u8 pad0;
1420 __le16 resp_id;
1421 __le16 fetch_seq_num;
1422 __le16 num_records;
1423 __le32 token;
1424 struct htt_tx_fetch_record records[0];
1425} __packed;
1426
1427struct htt_tx_fetch_confirm {
1428 u8 pad0;
1429 __le16 num_resp_ids;
1430 __le32 resp_ids[0];
1431} __packed;
1432
1433enum htt_tx_mode_switch_mode {
1434 HTT_TX_MODE_SWITCH_PUSH = 0,
1435 HTT_TX_MODE_SWITCH_PUSH_PULL = 1,
1436};
1437
1438#define HTT_TX_MODE_SWITCH_IND_INFO0_ENABLE BIT(0)
1439#define HTT_TX_MODE_SWITCH_IND_INFO0_NUM_RECORDS_MASK 0xfffe
1440#define HTT_TX_MODE_SWITCH_IND_INFO0_NUM_RECORDS_LSB 1
1441
1442#define HTT_TX_MODE_SWITCH_IND_INFO1_MODE_MASK 0x0003
1443#define HTT_TX_MODE_SWITCH_IND_INFO1_MODE_LSB 0
1444#define HTT_TX_MODE_SWITCH_IND_INFO1_THRESHOLD_MASK 0xfffc
1445#define HTT_TX_MODE_SWITCH_IND_INFO1_THRESHOLD_LSB 2
1446
1447#define HTT_TX_MODE_SWITCH_RECORD_INFO0_PEER_ID_MASK 0x0fff
1448#define HTT_TX_MODE_SWITCH_RECORD_INFO0_PEER_ID_LSB 0
1449#define HTT_TX_MODE_SWITCH_RECORD_INFO0_TID_MASK 0xf000
1450#define HTT_TX_MODE_SWITCH_RECORD_INFO0_TID_LSB 12
1451
1452struct htt_tx_mode_switch_record {
1453 __le16 info0;
1454 __le16 num_max_msdus;
1455} __packed;
1456
1457struct htt_tx_mode_switch_ind {
1458 u8 pad0;
1459 __le16 info0;
1460 __le16 info1;
1461 u8 pad1[2];
1462 struct htt_tx_mode_switch_record records[0];
1463} __packed;
1464
1465struct htt_channel_change {
1466 u8 pad[3];
1467 __le32 freq;
1468 __le32 center_freq1;
1469 __le32 center_freq2;
1470 __le32 phymode;
1471} __packed;
1472
1473union htt_rx_pn_t {
1474
1475 u32 pn24;
1476
1477
1478 u64 pn48;
1479
1480
1481 u64 pn128[2];
1482};
1483
1484struct htt_cmd {
1485 struct htt_cmd_hdr hdr;
1486 union {
1487 struct htt_ver_req ver_req;
1488 struct htt_mgmt_tx_desc mgmt_tx;
1489 struct htt_data_tx_desc data_tx;
1490 struct htt_rx_ring_setup rx_setup;
1491 struct htt_stats_req stats_req;
1492 struct htt_oob_sync_req oob_sync_req;
1493 struct htt_aggr_conf aggr_conf;
1494 struct htt_frag_desc_bank_cfg frag_desc_bank_cfg;
1495 struct htt_tx_fetch_resp tx_fetch_resp;
1496 };
1497} __packed;
1498
1499struct htt_resp {
1500 struct htt_resp_hdr hdr;
1501 union {
1502 struct htt_ver_resp ver_resp;
1503 struct htt_mgmt_tx_completion mgmt_tx_completion;
1504 struct htt_data_tx_completion data_tx_completion;
1505 struct htt_rx_indication rx_ind;
1506 struct htt_rx_fragment_indication rx_frag_ind;
1507 struct htt_rx_peer_map peer_map;
1508 struct htt_rx_peer_unmap peer_unmap;
1509 struct htt_rx_flush rx_flush;
1510 struct htt_rx_addba rx_addba;
1511 struct htt_rx_delba rx_delba;
1512 struct htt_security_indication security_indication;
1513 struct htt_rc_update rc_update;
1514 struct htt_rx_test rx_test;
1515 struct htt_pktlog_msg pktlog_msg;
1516 struct htt_stats_conf stats_conf;
1517 struct htt_rx_pn_ind rx_pn_ind;
1518 struct htt_rx_offload_ind rx_offload_ind;
1519 struct htt_rx_in_ord_ind rx_in_ord_ind;
1520 struct htt_tx_fetch_ind tx_fetch_ind;
1521 struct htt_tx_fetch_confirm tx_fetch_confirm;
1522 struct htt_tx_mode_switch_ind tx_mode_switch_ind;
1523 struct htt_channel_change chan_change;
1524 };
1525} __packed;
1526
1527
1528
1529struct htt_tx_done {
1530 u16 msdu_id;
1531 u16 status;
1532};
1533
1534enum htt_tx_compl_state {
1535 HTT_TX_COMPL_STATE_NONE,
1536 HTT_TX_COMPL_STATE_ACK,
1537 HTT_TX_COMPL_STATE_NOACK,
1538 HTT_TX_COMPL_STATE_DISCARD,
1539};
1540
1541struct htt_peer_map_event {
1542 u8 vdev_id;
1543 u16 peer_id;
1544 u8 addr[ETH_ALEN];
1545};
1546
1547struct htt_peer_unmap_event {
1548 u16 peer_id;
1549};
1550
1551struct ath10k_htt_txbuf {
1552 struct htt_data_tx_desc_frag frags[2];
1553 struct ath10k_htc_hdr htc_hdr;
1554 struct htt_cmd_hdr cmd_hdr;
1555 struct htt_data_tx_desc cmd_tx;
1556} __packed;
1557
1558struct ath10k_htt {
1559 struct ath10k *ar;
1560 enum ath10k_htc_ep_id eid;
1561
1562 u8 target_version_major;
1563 u8 target_version_minor;
1564 struct completion target_version_received;
1565 u8 max_num_amsdu;
1566 u8 max_num_ampdu;
1567
1568 const enum htt_t2h_msg_type *t2h_msg_types;
1569 u32 t2h_msg_types_max;
1570
1571 struct {
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581 struct sk_buff **netbufs_ring;
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593 bool in_ord_rx;
1594 DECLARE_HASHTABLE(skb_table, 4);
1595
1596
1597
1598
1599
1600
1601
1602 __le32 *paddrs_ring;
1603
1604
1605
1606
1607
1608 dma_addr_t base_paddr;
1609
1610
1611 int size;
1612
1613
1614 unsigned size_mask;
1615
1616
1617 int fill_level;
1618
1619
1620 int fill_cnt;
1621
1622
1623
1624
1625
1626
1627
1628 struct {
1629 __le32 *vaddr;
1630 dma_addr_t paddr;
1631 } alloc_idx;
1632
1633
1634 struct {
1635 unsigned msdu_payld;
1636 } sw_rd_idx;
1637
1638
1639
1640
1641
1642 struct timer_list refill_retry_timer;
1643
1644
1645 spinlock_t lock;
1646 } rx_ring;
1647
1648 unsigned int prefetch_len;
1649
1650
1651 spinlock_t tx_lock;
1652 int max_num_pending_tx;
1653 int num_pending_tx;
1654 int num_pending_mgmt_tx;
1655 struct idr pending_tx;
1656 wait_queue_head_t empty_tx_wq;
1657
1658
1659 DECLARE_KFIFO_PTR(txdone_fifo, struct htt_tx_done);
1660
1661
1662
1663 bool rx_confused;
1664 atomic_t num_mpdus_ready;
1665
1666
1667
1668 struct sk_buff_head rx_compl_q;
1669 struct sk_buff_head rx_in_ord_compl_q;
1670 struct sk_buff_head tx_fetch_ind_q;
1671
1672
1673 struct ieee80211_rx_status rx_status;
1674
1675 struct {
1676 dma_addr_t paddr;
1677 struct htt_msdu_ext_desc *vaddr;
1678 } frag_desc;
1679
1680 struct {
1681 dma_addr_t paddr;
1682 struct ath10k_htt_txbuf *vaddr;
1683 } txbuf;
1684
1685 struct {
1686 bool enabled;
1687 struct htt_q_state *vaddr;
1688 dma_addr_t paddr;
1689 u16 num_push_allowed;
1690 u16 num_peers;
1691 u16 num_tids;
1692 enum htt_tx_mode_switch_mode mode;
1693 enum htt_q_depth_type type;
1694 } tx_q_state;
1695};
1696
1697#define RX_HTT_HDR_STATUS_LEN 64
1698
1699
1700
1701
1702struct htt_rx_desc {
1703 union {
1704
1705
1706 struct fw_rx_desc_base fw_desc;
1707 u32 pad;
1708 } __packed;
1709 struct {
1710 struct rx_attention attention;
1711 struct rx_frag_info frag_info;
1712 struct rx_mpdu_start mpdu_start;
1713 struct rx_msdu_start msdu_start;
1714 struct rx_msdu_end msdu_end;
1715 struct rx_mpdu_end mpdu_end;
1716 struct rx_ppdu_start ppdu_start;
1717 struct rx_ppdu_end ppdu_end;
1718 } __packed;
1719 u8 rx_hdr_status[RX_HTT_HDR_STATUS_LEN];
1720 u8 msdu_payload[0];
1721};
1722
1723#define HTT_RX_DESC_ALIGN 8
1724
1725#define HTT_MAC_ADDR_LEN 6
1726
1727
1728
1729
1730
1731
1732#define HTT_RX_BUF_SIZE 1920
1733#define HTT_RX_MSDU_SIZE (HTT_RX_BUF_SIZE - (int)sizeof(struct htt_rx_desc))
1734
1735
1736
1737#define ATH10K_HTT_MAX_NUM_REFILL 100
1738
1739
1740
1741
1742
1743
1744#define HTT_LOG2_MAX_CACHE_LINE_SIZE 7
1745#define HTT_MAX_CACHE_LINE_SIZE_MASK ((1 << HTT_LOG2_MAX_CACHE_LINE_SIZE) - 1)
1746
1747
1748
1749
1750#define ATH10K_HTT_MAX_NUM_AMSDU_DEFAULT 3
1751#define ATH10K_HTT_MAX_NUM_AMPDU_DEFAULT 64
1752
1753int ath10k_htt_connect(struct ath10k_htt *htt);
1754int ath10k_htt_init(struct ath10k *ar);
1755int ath10k_htt_setup(struct ath10k_htt *htt);
1756
1757int ath10k_htt_tx_alloc(struct ath10k_htt *htt);
1758void ath10k_htt_tx_free(struct ath10k_htt *htt);
1759
1760int ath10k_htt_rx_alloc(struct ath10k_htt *htt);
1761int ath10k_htt_rx_ring_refill(struct ath10k *ar);
1762void ath10k_htt_rx_free(struct ath10k_htt *htt);
1763
1764void ath10k_htt_htc_tx_complete(struct ath10k *ar, struct sk_buff *skb);
1765void ath10k_htt_htc_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb);
1766bool ath10k_htt_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb);
1767int ath10k_htt_h2t_ver_req_msg(struct ath10k_htt *htt);
1768int ath10k_htt_h2t_stats_req(struct ath10k_htt *htt, u8 mask, u64 cookie);
1769int ath10k_htt_send_frag_desc_bank_cfg(struct ath10k_htt *htt);
1770int ath10k_htt_send_rx_ring_cfg_ll(struct ath10k_htt *htt);
1771int ath10k_htt_h2t_aggr_cfg_msg(struct ath10k_htt *htt,
1772 u8 max_subfrms_ampdu,
1773 u8 max_subfrms_amsdu);
1774void ath10k_htt_hif_tx_complete(struct ath10k *ar, struct sk_buff *skb);
1775int ath10k_htt_tx_fetch_resp(struct ath10k *ar,
1776 __le32 token,
1777 __le16 fetch_seq_num,
1778 struct htt_tx_fetch_record *records,
1779 size_t num_records);
1780
1781void ath10k_htt_tx_txq_update(struct ieee80211_hw *hw,
1782 struct ieee80211_txq *txq);
1783void ath10k_htt_tx_txq_recalc(struct ieee80211_hw *hw,
1784 struct ieee80211_txq *txq);
1785void ath10k_htt_tx_txq_sync(struct ath10k *ar);
1786void ath10k_htt_tx_dec_pending(struct ath10k_htt *htt);
1787int ath10k_htt_tx_inc_pending(struct ath10k_htt *htt);
1788void ath10k_htt_tx_mgmt_dec_pending(struct ath10k_htt *htt);
1789int ath10k_htt_tx_mgmt_inc_pending(struct ath10k_htt *htt, bool is_mgmt,
1790 bool is_presp);
1791
1792int ath10k_htt_tx_alloc_msdu_id(struct ath10k_htt *htt, struct sk_buff *skb);
1793void ath10k_htt_tx_free_msdu_id(struct ath10k_htt *htt, u16 msdu_id);
1794int ath10k_htt_mgmt_tx(struct ath10k_htt *htt, struct sk_buff *);
1795int ath10k_htt_tx(struct ath10k_htt *htt,
1796 enum ath10k_hw_txrx_mode txmode,
1797 struct sk_buff *msdu);
1798void ath10k_htt_rx_pktlog_completion_handler(struct ath10k *ar,
1799 struct sk_buff *skb);
1800int ath10k_htt_txrx_compl_task(struct ath10k *ar, int budget);
1801
1802#endif
1803