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17#include <linux/types.h>
18#include "core.h"
19#include "hw.h"
20
21const struct ath10k_hw_regs qca988x_regs = {
22 .rtc_soc_base_address = 0x00004000,
23 .rtc_wmac_base_address = 0x00005000,
24 .soc_core_base_address = 0x00009000,
25 .ce_wrapper_base_address = 0x00057000,
26 .ce0_base_address = 0x00057400,
27 .ce1_base_address = 0x00057800,
28 .ce2_base_address = 0x00057c00,
29 .ce3_base_address = 0x00058000,
30 .ce4_base_address = 0x00058400,
31 .ce5_base_address = 0x00058800,
32 .ce6_base_address = 0x00058c00,
33 .ce7_base_address = 0x00059000,
34 .soc_reset_control_si0_rst_mask = 0x00000001,
35 .soc_reset_control_ce_rst_mask = 0x00040000,
36 .soc_chip_id_address = 0x000000ec,
37 .scratch_3_address = 0x00000030,
38 .fw_indicator_address = 0x00009030,
39 .pcie_local_base_address = 0x00080000,
40 .ce_wrap_intr_sum_host_msi_lsb = 0x00000008,
41 .ce_wrap_intr_sum_host_msi_mask = 0x0000ff00,
42 .pcie_intr_fw_mask = 0x00000400,
43 .pcie_intr_ce_mask_all = 0x0007f800,
44 .pcie_intr_clr_address = 0x00000014,
45};
46
47const struct ath10k_hw_regs qca6174_regs = {
48 .rtc_soc_base_address = 0x00000800,
49 .rtc_wmac_base_address = 0x00001000,
50 .soc_core_base_address = 0x0003a000,
51 .ce_wrapper_base_address = 0x00034000,
52 .ce0_base_address = 0x00034400,
53 .ce1_base_address = 0x00034800,
54 .ce2_base_address = 0x00034c00,
55 .ce3_base_address = 0x00035000,
56 .ce4_base_address = 0x00035400,
57 .ce5_base_address = 0x00035800,
58 .ce6_base_address = 0x00035c00,
59 .ce7_base_address = 0x00036000,
60 .soc_reset_control_si0_rst_mask = 0x00000000,
61 .soc_reset_control_ce_rst_mask = 0x00000001,
62 .soc_chip_id_address = 0x000000f0,
63 .scratch_3_address = 0x00000028,
64 .fw_indicator_address = 0x0003a028,
65 .pcie_local_base_address = 0x00080000,
66 .ce_wrap_intr_sum_host_msi_lsb = 0x00000008,
67 .ce_wrap_intr_sum_host_msi_mask = 0x0000ff00,
68 .pcie_intr_fw_mask = 0x00000400,
69 .pcie_intr_ce_mask_all = 0x0007f800,
70 .pcie_intr_clr_address = 0x00000014,
71};
72
73const struct ath10k_hw_regs qca99x0_regs = {
74 .rtc_soc_base_address = 0x00080000,
75 .rtc_wmac_base_address = 0x00000000,
76 .soc_core_base_address = 0x00082000,
77 .ce_wrapper_base_address = 0x0004d000,
78 .ce0_base_address = 0x0004a000,
79 .ce1_base_address = 0x0004a400,
80 .ce2_base_address = 0x0004a800,
81 .ce3_base_address = 0x0004ac00,
82 .ce4_base_address = 0x0004b000,
83 .ce5_base_address = 0x0004b400,
84 .ce6_base_address = 0x0004b800,
85 .ce7_base_address = 0x0004bc00,
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96 .soc_reset_control_si0_rst_mask = 0x00000001,
97 .soc_reset_control_ce_rst_mask = 0x00000100,
98 .soc_chip_id_address = 0x000000ec,
99 .scratch_3_address = 0x00040050,
100 .fw_indicator_address = 0x00040050,
101 .pcie_local_base_address = 0x00000000,
102 .ce_wrap_intr_sum_host_msi_lsb = 0x0000000c,
103 .ce_wrap_intr_sum_host_msi_mask = 0x00fff000,
104 .pcie_intr_fw_mask = 0x00100000,
105 .pcie_intr_ce_mask_all = 0x000fff00,
106 .pcie_intr_clr_address = 0x00000010,
107};
108
109const struct ath10k_hw_regs qca4019_regs = {
110 .rtc_soc_base_address = 0x00080000,
111 .soc_core_base_address = 0x00082000,
112 .ce_wrapper_base_address = 0x0004d000,
113 .ce0_base_address = 0x0004a000,
114 .ce1_base_address = 0x0004a400,
115 .ce2_base_address = 0x0004a800,
116 .ce3_base_address = 0x0004ac00,
117 .ce4_base_address = 0x0004b000,
118 .ce5_base_address = 0x0004b400,
119 .ce6_base_address = 0x0004b800,
120 .ce7_base_address = 0x0004bc00,
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130 .soc_reset_control_si0_rst_mask = 0x00000001,
131 .soc_reset_control_ce_rst_mask = 0x00000100,
132 .soc_chip_id_address = 0x000000ec,
133 .fw_indicator_address = 0x0004f00c,
134 .ce_wrap_intr_sum_host_msi_lsb = 0x0000000c,
135 .ce_wrap_intr_sum_host_msi_mask = 0x00fff000,
136 .pcie_intr_fw_mask = 0x00100000,
137 .pcie_intr_ce_mask_all = 0x000fff00,
138 .pcie_intr_clr_address = 0x00000010,
139};
140
141const struct ath10k_hw_values qca988x_values = {
142 .rtc_state_val_on = 3,
143 .ce_count = 8,
144 .msi_assign_ce_max = 7,
145 .num_target_ce_config_wlan = 7,
146 .ce_desc_meta_data_mask = 0xFFFC,
147 .ce_desc_meta_data_lsb = 2,
148};
149
150const struct ath10k_hw_values qca6174_values = {
151 .rtc_state_val_on = 3,
152 .ce_count = 8,
153 .msi_assign_ce_max = 7,
154 .num_target_ce_config_wlan = 7,
155 .ce_desc_meta_data_mask = 0xFFFC,
156 .ce_desc_meta_data_lsb = 2,
157};
158
159const struct ath10k_hw_values qca99x0_values = {
160 .rtc_state_val_on = 5,
161 .ce_count = 12,
162 .msi_assign_ce_max = 12,
163 .num_target_ce_config_wlan = 10,
164 .ce_desc_meta_data_mask = 0xFFF0,
165 .ce_desc_meta_data_lsb = 4,
166};
167
168const struct ath10k_hw_values qca9888_values = {
169 .rtc_state_val_on = 3,
170 .ce_count = 12,
171 .msi_assign_ce_max = 12,
172 .num_target_ce_config_wlan = 10,
173 .ce_desc_meta_data_mask = 0xFFF0,
174 .ce_desc_meta_data_lsb = 4,
175};
176
177const struct ath10k_hw_values qca4019_values = {
178 .ce_count = 12,
179 .num_target_ce_config_wlan = 10,
180 .ce_desc_meta_data_mask = 0xFFF0,
181 .ce_desc_meta_data_lsb = 4,
182};
183
184void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey,
185 u32 cc, u32 rcc, u32 cc_prev, u32 rcc_prev)
186{
187 u32 cc_fix = 0;
188 u32 rcc_fix = 0;
189 enum ath10k_hw_cc_wraparound_type wraparound_type;
190
191 survey->filled |= SURVEY_INFO_TIME |
192 SURVEY_INFO_TIME_BUSY;
193
194 wraparound_type = ar->hw_params.cc_wraparound_type;
195
196 if (cc < cc_prev || rcc < rcc_prev) {
197 switch (wraparound_type) {
198 case ATH10K_HW_CC_WRAP_SHIFTED_ALL:
199 if (cc < cc_prev) {
200 cc_fix = 0x7fffffff;
201 survey->filled &= ~SURVEY_INFO_TIME_BUSY;
202 }
203 break;
204 case ATH10K_HW_CC_WRAP_SHIFTED_EACH:
205 if (cc < cc_prev)
206 cc_fix = 0x7fffffff;
207
208 if (rcc < rcc_prev)
209 rcc_fix = 0x7fffffff;
210 break;
211 case ATH10K_HW_CC_WRAP_DISABLED:
212 break;
213 }
214 }
215
216 cc -= cc_prev - cc_fix;
217 rcc -= rcc_prev - rcc_fix;
218
219 survey->time = CCNT_TO_MSEC(ar, cc);
220 survey->time_busy = CCNT_TO_MSEC(ar, rcc);
221}
222
223const struct ath10k_hw_ops qca988x_ops = {
224};
225
226static int ath10k_qca99x0_rx_desc_get_l3_pad_bytes(struct htt_rx_desc *rxd)
227{
228 return MS(__le32_to_cpu(rxd->msdu_end.qca99x0.info1),
229 RX_MSDU_END_INFO1_L3_HDR_PAD);
230}
231
232const struct ath10k_hw_ops qca99x0_ops = {
233 .rx_desc_get_l3_pad_bytes = ath10k_qca99x0_rx_desc_get_l3_pad_bytes,
234};
235
