1/* 2 * AD9833/AD9834/AD9837/AD9838 SPI DDS driver 3 * 4 * Copyright 2010-2011 Analog Devices Inc. 5 * 6 * Licensed under the GPL-2. 7 */ 8#ifndef IIO_DDS_AD9834_H_ 9#define IIO_DDS_AD9834_H_ 10 11/* Registers */ 12 13#define AD9834_REG_CMD 0 14#define AD9834_REG_FREQ0 BIT(14) 15#define AD9834_REG_FREQ1 BIT(15) 16#define AD9834_REG_PHASE0 (BIT(15) | BIT(14)) 17#define AD9834_REG_PHASE1 (BIT(15) | BIT(14) | BIT(13)) 18 19/* Command Control Bits */ 20 21#define AD9834_B28 BIT(13) 22#define AD9834_HLB BIT(12) 23#define AD9834_FSEL BIT(11) 24#define AD9834_PSEL BIT(10) 25#define AD9834_PIN_SW BIT(9) 26#define AD9834_RESET BIT(8) 27#define AD9834_SLEEP1 BIT(7) 28#define AD9834_SLEEP12 BIT(6) 29#define AD9834_OPBITEN BIT(5) 30#define AD9834_SIGN_PIB BIT(4) 31#define AD9834_DIV2 BIT(3) 32#define AD9834_MODE BIT(1) 33 34#define AD9834_FREQ_BITS 28 35#define AD9834_PHASE_BITS 12 36 37#define RES_MASK(bits) (BIT(bits) - 1) 38 39/** 40 * struct ad9834_state - driver instance specific data 41 * @spi: spi_device 42 * @reg: supply regulator 43 * @mclk: external master clock 44 * @control: cached control word 45 * @xfer: default spi transfer 46 * @msg: default spi message 47 * @freq_xfer: tuning word spi transfer 48 * @freq_msg: tuning word spi message 49 * @data: spi transmit buffer 50 * @freq_data: tuning word spi transmit buffer 51 */ 52 53struct ad9834_state { 54 struct spi_device *spi; 55 struct regulator *reg; 56 unsigned int mclk; 57 unsigned short control; 58 unsigned short devid; 59 struct spi_transfer xfer; 60 struct spi_message msg; 61 struct spi_transfer freq_xfer[2]; 62 struct spi_message freq_msg; 63 64 /* 65 * DMA (thus cache coherency maintenance) requires the 66 * transfer buffers to live in their own cache lines. 67 */ 68 __be16 data ____cacheline_aligned; 69 __be16 freq_data[2]; 70}; 71 72/* 73 * TODO: struct ad7887_platform_data needs to go into include/linux/iio 74 */ 75 76/** 77 * struct ad9834_platform_data - platform specific information 78 * @mclk: master clock in Hz 79 * @freq0: power up freq0 tuning word in Hz 80 * @freq1: power up freq1 tuning word in Hz 81 * @phase0: power up phase0 value [0..4095] correlates with 0..2PI 82 * @phase1: power up phase1 value [0..4095] correlates with 0..2PI 83 * @en_div2: digital output/2 is passed to the SIGN BIT OUT pin 84 * @en_signbit_msb_out: the MSB (or MSB/2) of the DAC data is connected to the 85 * SIGN BIT OUT pin. en_div2 controls whether it is the MSB 86 * or MSB/2 that is output. if en_signbit_msb_out=false, 87 * the on-board comparator is connected to SIGN BIT OUT 88 */ 89 90struct ad9834_platform_data { 91 unsigned int mclk; 92 unsigned int freq0; 93 unsigned int freq1; 94 unsigned short phase0; 95 unsigned short phase1; 96 bool en_div2; 97 bool en_signbit_msb_out; 98}; 99 100/** 101 * ad9834_supported_device_ids: 102 */ 103 104enum ad9834_supported_device_ids { 105 ID_AD9833, 106 ID_AD9834, 107 ID_AD9837, 108 ID_AD9838, 109}; 110 111#endif /* IIO_DDS_AD9834_H_ */ 112