LXR linux/drivers/staging/rtl8188eu/include/odm.h

   1/******************************************************************************
   2 *
   3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4 *
   5 * This program is free software; you can redistribute it and/or modify it
   6 * under the terms of version 2 of the GNU General Public License as
   7 * published by the Free Software Foundation.
   8 *
   9 * This program is distributed in the hope that it will be useful, but WITHOUT
  10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12 * more details.
  13 *
  14 ******************************************************************************/
  15
  16
  17#ifndef __HALDMOUTSRC_H__
  18#define __HALDMOUTSRC_H__
  19
  20/*  Definition */
  21/*  Define all team support ability. */
  22
  23/*  Define for all teams. Please Define the constant in your precomp header. */
  24
  25/* define               DM_ODM_SUPPORT_AP                       0 */
  26/* define               DM_ODM_SUPPORT_ADSL                     0 */
  27/* define               DM_ODM_SUPPORT_CE                       0 */
  28/* define               DM_ODM_SUPPORT_MP                       1 */
  29
  30/*  Define ODM SW team support flag. */
  31
  32/*  Antenna Switch Relative Definition. */
  33
  34/*  Add new function SwAntDivCheck8192C(). */
  35/*  This is the main function of Antenna diversity function before link. */
  36/*  Mainly, it just retains last scan result and scan again. */
  37/*  After that, it compares the scan result to see which one gets better
  38 *  RSSI. It selects antenna with better receiving power and returns better
  39 *  scan result. */
  40
  41#define TP_MODE                 0
  42#define RSSI_MODE               1
  43#define TRAFFIC_LOW             0
  44#define TRAFFIC_HIGH            1
  45
  46/* 3 Tx Power Tracking */
  47/* 3============================================================ */
  48#define         DPK_DELTA_MAPPING_NUM   13
  49#define         index_mapping_HP_NUM    15
  50
  51
  52/*  */
  53/* 3 PSD Handler */
  54/* 3============================================================ */
  55
  56#define AFH_PSD         1       /* 0:normal PSD scan, 1: only do 20 pts PSD */
  57#define MODE_40M        0       /* 0:20M, 1:40M */
  58#define PSD_TH2         3
  59#define PSD_CHM         20   /*  Minimum channel number for BT AFH */
  60#define SIR_STEP_SIZE   3
  61#define Smooth_Size_1   5
  62#define Smooth_TH_1     3
  63#define Smooth_Size_2   10
  64#define Smooth_TH_2     4
  65#define Smooth_Size_3   20
  66#define Smooth_TH_3     4
  67#define Smooth_Step_Size 5
  68#define Adaptive_SIR    1
  69#define PSD_RESCAN      4
  70#define PSD_SCAN_INTERVAL       700 /* ms */
  71
  72/* 8723A High Power IGI Setting */
  73#define DM_DIG_HIGH_PWR_IGI_LOWER_BOUND 0x22
  74#define DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND 0x28
  75#define DM_DIG_HIGH_PWR_THRESHOLD       0x3a
  76
  77/*  LPS define */
  78#define DM_DIG_FA_TH0_LPS               4 /*  4 in lps */
  79#define DM_DIG_FA_TH1_LPS               15 /*  15 lps */
  80#define DM_DIG_FA_TH2_LPS               30 /*  30 lps */
  81#define RSSI_OFFSET_DIG                 0x05;
  82
  83/* ANT Test */
  84#define ANTTESTALL              0x00    /* Ant A or B will be Testing */
  85#define ANTTESTA                0x01    /* Ant A will be Testing */
  86#define ANTTESTB                0x02    /* Ant B will be testing */
  87
  88struct rtw_dig {
  89        u8              Dig_Enable_Flag;
  90        u8              Dig_Ext_Port_Stage;
  91
  92        int             RssiLowThresh;
  93        int             RssiHighThresh;
  94
  95        u32             FALowThresh;
  96        u32             FAHighThresh;
  97
  98        u8              CurSTAConnectState;
  99        u8              PreSTAConnectState;
 100        u8              CurMultiSTAConnectState;
 101
 102        u8              PreIGValue;
 103        u8              CurIGValue;
 104        u8              BackupIGValue;
 105
 106        s8              BackoffVal;
 107        s8              BackoffVal_range_max;
 108        s8              BackoffVal_range_min;
 109        u8              rx_gain_range_max;
 110        u8              rx_gain_range_min;
 111        u8              Rssi_val_min;
 112
 113        u8              PreCCK_CCAThres;
 114        u8              CurCCK_CCAThres;
 115        u8              PreCCKPDState;
 116        u8              CurCCKPDState;
 117
 118        u8              LargeFAHit;
 119        u8              ForbiddenIGI;
 120        u32             Recover_cnt;
 121
 122        u8              DIG_Dynamic_MIN_0;
 123        u8              DIG_Dynamic_MIN_1;
 124        bool            bMediaConnect_0;
 125        bool            bMediaConnect_1;
 126
 127        u32             AntDiv_RSSI_max;
 128        u32             RSSI_max;
 129};
 130
 131struct rtl_ps {
 132        u8              PreCCAState;
 133        u8              CurCCAState;
 134
 135        u8              PreRFState;
 136        u8              CurRFState;
 137
 138        int                 Rssi_val_min;
 139
 140        u8              initialize;
 141        u32             Reg874, RegC70, Reg85C, RegA74;
 142
 143};
 144
 145struct false_alarm_stats {
 146        u32     Cnt_Parity_Fail;
 147        u32     Cnt_Rate_Illegal;
 148        u32     Cnt_Crc8_fail;
 149        u32     Cnt_Mcs_fail;
 150        u32     Cnt_Ofdm_fail;
 151        u32     Cnt_Cck_fail;
 152        u32     Cnt_all;
 153        u32     Cnt_Fast_Fsync;
 154        u32     Cnt_SB_Search_fail;
 155        u32     Cnt_OFDM_CCA;
 156        u32     Cnt_CCK_CCA;
 157        u32     Cnt_CCA_all;
 158        u32     Cnt_BW_USC;     /* Gary */
 159        u32     Cnt_BW_LSC;     /* Gary */
 160};
 161
 162struct rx_hpc {
 163        u8              RXHP_flag;
 164        u8              PSD_func_trigger;
 165        u8              PSD_bitmap_RXHP[80];
 166        u8              Pre_IGI;
 167        u8              Cur_IGI;
 168        u8              Pre_pw_th;
 169        u8              Cur_pw_th;
 170        bool            First_time_enter;
 171        bool            RXHP_enable;
 172        u8              TP_Mode;
 173        struct timer_list PSDTimer;
 174};
 175
 176#define ASSOCIATE_ENTRY_NUM     32 /*  Max size of AsocEntry[]. */
 177#define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM
 178
 179/*  This indicates two different steps. */
 180/*  In SWAW_STEP_PEAK, driver needs to switch antenna and listen to
 181 *  the signal on the air. */
 182/*  In SWAW_STEP_DETERMINE, driver just compares the signal captured in
 183 *  SWAW_STEP_PEAK with original RSSI to determine if it is necessary to
 184 *  switch antenna. */
 185
 186#define SWAW_STEP_PEAK          0
 187#define SWAW_STEP_DETERMINE     1
 188
 189#define TP_MODE                 0
 190#define RSSI_MODE               1
 191#define TRAFFIC_LOW             0
 192#define TRAFFIC_HIGH            1
 193
 194struct sw_ant_switch {
 195        u8      try_flag;
 196        s32     PreRSSI;
 197        u8      CurAntenna;
 198        u8      PreAntenna;
 199        u8      RSSI_Trying;
 200        u8      TestMode;
 201        u8      bTriggerAntennaSwitch;
 202        u8      SelectAntennaMap;
 203        u8      RSSI_target;
 204
 205        /*  Before link Antenna Switch check */
 206        u8      SWAS_NoLink_State;
 207        u32     SWAS_NoLink_BK_Reg860;
 208        bool    ANTA_ON;        /* To indicate Ant A is or not */
 209        bool    ANTB_ON;        /* To indicate Ant B is on or not */
 210
 211        s32     RSSI_sum_A;
 212        s32     RSSI_sum_B;
 213        s32     RSSI_cnt_A;
 214        s32     RSSI_cnt_B;
 215        u64     lastTxOkCnt;
 216        u64     lastRxOkCnt;
 217        u64     TXByteCnt_A;
 218        u64     TXByteCnt_B;
 219        u64     RXByteCnt_A;
 220        u64     RXByteCnt_B;
 221        u8      TrafficLoad;
 222        struct timer_list SwAntennaSwitchTimer;
 223        /* Hybrid Antenna Diversity */
 224        u32     CCK_Ant1_Cnt[ASSOCIATE_ENTRY_NUM];
 225        u32     CCK_Ant2_Cnt[ASSOCIATE_ENTRY_NUM];
 226        u32     OFDM_Ant1_Cnt[ASSOCIATE_ENTRY_NUM];
 227        u32     OFDM_Ant2_Cnt[ASSOCIATE_ENTRY_NUM];
 228        u32     RSSI_Ant1_Sum[ASSOCIATE_ENTRY_NUM];
 229        u32     RSSI_Ant2_Sum[ASSOCIATE_ENTRY_NUM];
 230        u8      TxAnt[ASSOCIATE_ENTRY_NUM];
 231        u8      TargetSTA;
 232        u8      antsel;
 233        u8      RxIdleAnt;
 234};
 235
 236struct edca_turbo {
 237        bool bCurrentTurboEDCA;
 238        bool bIsCurRDLState;
 239        u32     prv_traffic_idx; /*  edca turbo */
 240};
 241
 242struct odm_rate_adapt {
 243        u8      Type;           /*  DM_Type_ByFW/DM_Type_ByDriver */
 244        u8      HighRSSIThresh; /*  if RSSI > HighRSSIThresh    => RATRState is DM_RATR_STA_HIGH */
 245        u8      LowRSSIThresh;  /*  if RSSI <= LowRSSIThresh    => RATRState is DM_RATR_STA_LOW */
 246        u8      RATRState;      /*  Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW */
 247        u32     LastRATR;       /*  RATR Register Content */
 248};
 249
 250#define IQK_MAC_REG_NUM         4
 251#define IQK_ADDA_REG_NUM        16
 252#define IQK_BB_REG_NUM_MAX      10
 253#define IQK_BB_REG_NUM          9
 254#define HP_THERMAL_NUM          8
 255
 256#define AVG_THERMAL_NUM         8
 257#define IQK_Matrix_REG_NUM      8
 258#define IQK_Matrix_Settings_NUM 1+24+21
 259
 260#define DM_Type_ByFWi           0
 261#define DM_Type_ByDriver        1
 262
 263/*  Declare for common info */
 264
 265struct odm_phy_status_info {
 266        u8      RxPWDBAll;
 267        u8      SignalQuality;   /*  in 0-100 index. */
 268        u8      RxMIMOSignalQuality[MAX_PATH_NUM_92CS]; /* EVM */
 269        u8      RxMIMOSignalStrength[MAX_PATH_NUM_92CS];/*  in 0~100 index */
 270        s8      RxPower; /*  in dBm Translate from PWdB */
 271        s8      RecvSignalPower;/*  Real power in dBm for this packet, no
 272                                 * beautification and aggregation. Keep this raw
 273                                 * info to be used for the other procedures. */
 274        u8      BTRxRSSIPercentage;
 275        u8      SignalStrength; /*  in 0-100 index. */
 276        u8      RxPwr[MAX_PATH_NUM_92CS];/* per-path's pwdb */
 277        u8      RxSNR[MAX_PATH_NUM_92CS];/* per-path's SNR */
 278};
 279
 280struct odm_phy_dbg_info {
 281        /* ODM Write,debug info */
 282        s8      RxSNRdB[MAX_PATH_NUM_92CS];
 283        u64     NumQryPhyStatus;
 284        u64     NumQryPhyStatusCCK;
 285        u64     NumQryPhyStatusOFDM;
 286        /* Others */
 287        s32     RxEVM[MAX_PATH_NUM_92CS];
 288};
 289
 290struct odm_per_pkt_info {
 291        s8      Rate;
 292        u8      StationID;
 293        bool    bPacketMatchBSSID;
 294        bool    bPacketToSelf;
 295        bool    bPacketBeacon;
 296};
 297
 298struct odm_mac_status_info {
 299        u8      test;
 300};
 301
 302enum odm_ability {
 303        /*  BB Team */
 304        ODM_DIG                 = 0x00000001,
 305        ODM_HIGH_POWER          = 0x00000002,
 306        ODM_CCK_CCA_TH          = 0x00000004,
 307        ODM_FA_STATISTICS       = 0x00000008,
 308        ODM_RAMASK              = 0x00000010,
 309        ODM_RSSI_MONITOR        = 0x00000020,
 310        ODM_SW_ANTDIV           = 0x00000040,
 311        ODM_HW_ANTDIV           = 0x00000080,
 312        ODM_BB_PWRSV            = 0x00000100,
 313        ODM_2TPATHDIV           = 0x00000200,
 314        ODM_1TPATHDIV           = 0x00000400,
 315        ODM_PSD2AFH             = 0x00000800
 316};
 317
 318/*  2011/10/20 MH Define Common info enum for all team. */
 319
 320enum odm_common_info_def {
 321        /*  Fixed value: */
 322
 323        /* HOOK BEFORE REG INIT----------- */
 324        ODM_CMNINFO_PLATFORM = 0,
 325        ODM_CMNINFO_ABILITY,            /* ODM_ABILITY_E */
 326        ODM_CMNINFO_INTERFACE,          /* ODM_INTERFACE_E */
 327        ODM_CMNINFO_MP_TEST_CHIP,
 328        ODM_CMNINFO_IC_TYPE,            /* ODM_IC_TYPE_E */
 329        ODM_CMNINFO_CUT_VER,            /* ODM_CUT_VERSION_E */
 330        ODM_CMNINFO_RF_TYPE,            /* ODM_RF_PATH_E or ODM_RF_TYPE_E? */
 331        ODM_CMNINFO_BOARD_TYPE,         /* ODM_BOARD_TYPE_E */
 332        ODM_CMNINFO_EXT_LNA,            /* true */
 333        ODM_CMNINFO_EXT_PA,
 334        ODM_CMNINFO_EXT_TRSW,
 335        ODM_CMNINFO_PATCH_ID,           /* CUSTOMER ID */
 336        ODM_CMNINFO_BINHCT_TEST,
 337        ODM_CMNINFO_BWIFI_TEST,
 338        ODM_CMNINFO_SMART_CONCURRENT,
 339        /* HOOK BEFORE REG INIT-----------  */
 340
 341        /*  Dynamic value: */
 342/*  POINTER REFERENCE-----------  */
 343        ODM_CMNINFO_MAC_PHY_MODE,       /*  ODM_MAC_PHY_MODE_E */
 344        ODM_CMNINFO_TX_UNI,
 345        ODM_CMNINFO_RX_UNI,
 346        ODM_CMNINFO_WM_MODE,            /*  ODM_WIRELESS_MODE_E */
 347        ODM_CMNINFO_BAND,               /*  ODM_BAND_TYPE_E */
 348        ODM_CMNINFO_SEC_CHNL_OFFSET,    /*  ODM_SEC_CHNL_OFFSET_E */
 349        ODM_CMNINFO_SEC_MODE,           /*  ODM_SECURITY_E */
 350        ODM_CMNINFO_BW,                 /*  ODM_BW_E */
 351        ODM_CMNINFO_CHNL,
 352
 353        ODM_CMNINFO_DMSP_GET_VALUE,
 354        ODM_CMNINFO_BUDDY_ADAPTOR,
 355        ODM_CMNINFO_DMSP_IS_MASTER,
 356        ODM_CMNINFO_SCAN,
 357        ODM_CMNINFO_POWER_SAVING,
 358        ODM_CMNINFO_ONE_PATH_CCA,       /*  ODM_CCA_PATH_E */
 359        ODM_CMNINFO_DRV_STOP,
 360        ODM_CMNINFO_PNP_IN,
 361        ODM_CMNINFO_INIT_ON,
 362        ODM_CMNINFO_ANT_TEST,
 363        ODM_CMNINFO_NET_CLOSED,
 364        ODM_CMNINFO_MP_MODE,
 365/*  POINTER REFERENCE----------- */
 366
 367/* CALL BY VALUE------------- */
 368        ODM_CMNINFO_WIFI_DIRECT,
 369        ODM_CMNINFO_WIFI_DISPLAY,
 370        ODM_CMNINFO_LINK,
 371        ODM_CMNINFO_RSSI_MIN,
 372        ODM_CMNINFO_DBG_COMP,                   /*  u64 */
 373        ODM_CMNINFO_DBG_LEVEL,                  /*  u32 */
 374        ODM_CMNINFO_RA_THRESHOLD_HIGH,          /*  u8 */
 375        ODM_CMNINFO_RA_THRESHOLD_LOW,           /*  u8 */
 376        ODM_CMNINFO_RF_ANTENNA_TYPE,            /*  u8 */
 377        ODM_CMNINFO_BT_DISABLED,
 378        ODM_CMNINFO_BT_OPERATION,
 379        ODM_CMNINFO_BT_DIG,
 380        ODM_CMNINFO_BT_BUSY,                    /* Check Bt is using or not */
 381        ODM_CMNINFO_BT_DISABLE_EDCA,
 382/* CALL BY VALUE-------------*/
 383
 384        /*  Dynamic ptr array hook itms. */
 385        ODM_CMNINFO_STA_STATUS,
 386        ODM_CMNINFO_PHY_STATUS,
 387        ODM_CMNINFO_MAC_STATUS,
 388        ODM_CMNINFO_MAX,
 389};
 390
 391/*  2011/10/20 MH Define ODM support ability.  ODM_CMNINFO_ABILITY */
 392
 393enum odm_ability_def {
 394        /*  BB ODM section BIT 0-15 */
 395        ODM_BB_DIG                      = BIT(0),
 396        ODM_BB_RA_MASK                  = BIT(1),
 397        ODM_BB_DYNAMIC_TXPWR            = BIT(2),
 398        ODM_BB_FA_CNT                   = BIT(3),
 399        ODM_BB_RSSI_MONITOR             = BIT(4),
 400        ODM_BB_CCK_PD                   = BIT(5),
 401        ODM_BB_ANT_DIV                  = BIT(6),
 402        ODM_BB_PWR_SAVE                 = BIT(7),
 403        ODM_BB_PWR_TRA                  = BIT(8),
 404        ODM_BB_RATE_ADAPTIVE            = BIT(9),
 405        ODM_BB_PATH_DIV                 = BIT(10),
 406        ODM_BB_PSD                      = BIT(11),
 407        ODM_BB_RXHP                     = BIT(12),
 408
 409        /*  MAC DM section BIT 16-23 */
 410        ODM_MAC_EDCA_TURBO              = BIT(16),
 411        ODM_MAC_EARLY_MODE              = BIT(17),
 412
 413        /*  RF ODM section BIT 24-31 */
 414        ODM_RF_TX_PWR_TRACK             = BIT(24),
 415        ODM_RF_RX_GAIN_TRACK            = BIT(25),
 416        ODM_RF_CALIBRATION              = BIT(26),
 417};
 418
 419#define ODM_RTL8188E            BIT(4)
 420
 421/* ODM_CMNINFO_CUT_VER */
 422enum odm_cut_version {
 423        ODM_CUT_A       =       1,
 424        ODM_CUT_B       =       2,
 425        ODM_CUT_C       =       3,
 426        ODM_CUT_D       =       4,
 427        ODM_CUT_E       =       5,
 428        ODM_CUT_F       =       6,
 429        ODM_CUT_TEST    =       7,
 430};
 431
 432/*  ODM_CMNINFO_RF_TYPE */
 433/*  For example 1T2R (A+AB = BIT0|BIT4|BIT5) */
 434enum odm_rf_path {
 435        ODM_RF_TX_A     =       BIT(0),
 436        ODM_RF_TX_B     =       BIT(1),
 437        ODM_RF_TX_C     =       BIT(2),
 438        ODM_RF_TX_D     =       BIT(3),
 439        ODM_RF_RX_A     =       BIT(4),
 440        ODM_RF_RX_B     =       BIT(5),
 441        ODM_RF_RX_C     =       BIT(6),
 442        ODM_RF_RX_D     =       BIT(7),
 443};
 444
 445enum odm_rf_type {
 446        ODM_1T1R        =       0,
 447        ODM_1T2R        =       1,
 448        ODM_2T2R        =       2,
 449        ODM_2T3R        =       3,
 450        ODM_2T4R        =       4,
 451        ODM_3T3R        =       5,
 452        ODM_3T4R        =       6,
 453        ODM_4T4R        =       7,
 454};
 455
 456/*  ODM Dynamic common info value definition */
 457
 458enum odm_mac_phy_mode {
 459        ODM_SMSP        = 0,
 460        ODM_DMSP        = 1,
 461        ODM_DMDP        = 2,
 462};
 463
 464enum odm_bt_coexist {
 465        ODM_BT_BUSY             = 1,
 466        ODM_BT_ON               = 2,
 467        ODM_BT_OFF              = 3,
 468        ODM_BT_NONE             = 4,
 469};
 470
 471/*  ODM_CMNINFO_OP_MODE */
 472enum odm_operation_mode {
 473        ODM_NO_LINK             = BIT(0),
 474        ODM_LINK                = BIT(1),
 475        ODM_SCAN                = BIT(2),
 476        ODM_POWERSAVE           = BIT(3),
 477        ODM_AP_MODE             = BIT(4),
 478        ODM_CLIENT_MODE         = BIT(5),
 479        ODM_AD_HOC              = BIT(6),
 480        ODM_WIFI_DIRECT         = BIT(7),
 481        ODM_WIFI_DISPLAY        = BIT(8),
 482};
 483
 484/*  ODM_CMNINFO_WM_MODE */
 485enum odm_wireless_mode {
 486        ODM_WM_UNKNOW   = 0x0,
 487        ODM_WM_B        = BIT(0),
 488        ODM_WM_G        = BIT(1),
 489        ODM_WM_A        = BIT(2),
 490        ODM_WM_N24G     = BIT(3),
 491        ODM_WM_N5G      = BIT(4),
 492        ODM_WM_AUTO     = BIT(5),
 493        ODM_WM_AC       = BIT(6),
 494};
 495
 496/*  ODM_CMNINFO_BAND */
 497enum odm_band_type {
 498        ODM_BAND_2_4G   = BIT(0),
 499        ODM_BAND_5G     = BIT(1),
 500};
 501
 502/*  ODM_CMNINFO_SEC_CHNL_OFFSET */
 503enum odm_sec_chnl_offset {
 504        ODM_DONT_CARE   = 0,
 505        ODM_BELOW       = 1,
 506        ODM_ABOVE       = 2
 507};
 508
 509/*  ODM_CMNINFO_SEC_MODE */
 510enum odm_security {
 511        ODM_SEC_OPEN            = 0,
 512        ODM_SEC_WEP40           = 1,
 513        ODM_SEC_TKIP            = 2,
 514        ODM_SEC_RESERVE         = 3,
 515        ODM_SEC_AESCCMP         = 4,
 516        ODM_SEC_WEP104          = 5,
 517        ODM_WEP_WPA_MIXED       = 6, /*  WEP + WPA */
 518        ODM_SEC_SMS4            = 7,
 519};
 520
 521/*  ODM_CMNINFO_BW */
 522enum odm_bw {
 523        ODM_BW20M               = 0,
 524        ODM_BW40M               = 1,
 525        ODM_BW80M               = 2,
 526        ODM_BW160M              = 3,
 527        ODM_BW10M               = 4,
 528};
 529
 530/*  ODM_CMNINFO_BOARD_TYPE */
 531enum odm_board_type {
 532        ODM_BOARD_NORMAL        = 0,
 533        ODM_BOARD_HIGHPWR       = 1,
 534        ODM_BOARD_MINICARD      = 2,
 535        ODM_BOARD_SLIM          = 3,
 536        ODM_BOARD_COMBO         = 4,
 537};
 538
 539/*  ODM_CMNINFO_ONE_PATH_CCA */
 540enum odm_cca_path {
 541        ODM_CCA_2R              = 0,
 542        ODM_CCA_1R_A            = 1,
 543        ODM_CCA_1R_B            = 2,
 544};
 545
 546struct odm_ra_info {
 547        u8 RateID;
 548        u32 RateMask;
 549        u32 RAUseRate;
 550        u8 RateSGI;
 551        u8 RssiStaRA;
 552        u8 PreRssiStaRA;
 553        u8 SGIEnable;
 554        u8 DecisionRate;
 555        u8 PreRate;
 556        u8 HighestRate;
 557        u8 LowestRate;
 558        u32 NscUp;
 559        u32 NscDown;
 560        u16 RTY[5];
 561        u32 TOTAL;
 562        u16 DROP;
 563        u8 Active;
 564        u16 RptTime;
 565        u8 RAWaitingCounter;
 566        u8 RAPendingCounter;
 567        u8 PTActive;    /*  on or off */
 568        u8 PTTryState;  /*  0 trying state, 1 for decision state */
 569        u8 PTStage;     /*  0~6 */
 570        u8 PTStopCount; /* Stop PT counter */
 571        u8 PTPreRate;   /*  if rate change do PT */
 572        u8 PTPreRssi;   /*  if RSSI change 5% do PT */
 573        u8 PTModeSS;    /*  decide whitch rate should do PT */
 574        u8 RAstage;     /*  StageRA, decide how many times RA will be done
 575                         * between PT */
 576        u8 PTSmoothFactor;
 577};
 578
 579struct ijk_matrix_regs_set {
 580        bool    bIQKDone;
 581        s32     Value[1][IQK_Matrix_REG_NUM];
 582};
 583
 584struct odm_rf_cal {
 585        /* for tx power tracking */
 586        u32     RegA24; /*  for TempCCK */
 587        s32     RegE94;
 588        s32     RegE9C;
 589        s32     RegEB4;
 590        s32     RegEBC;
 591
 592        u8      TXPowercount;
 593        bool    bTXPowerTrackingInit;
 594        bool    bTXPowerTracking;
 595        u8      TxPowerTrackControl; /* for mp mode, turn off txpwrtracking
 596                                      * as default */
 597        u8      TM_Trigger;
 598        u8      InternalPA5G[2];        /* pathA / pathB */
 599
 600        u8      ThermalMeter[2];    /* ThermalMeter, index 0 for RFIC0,
 601                                     * and 1 for RFIC1 */
 602        u8      ThermalValue;
 603        u8      ThermalValue_LCK;
 604        u8      ThermalValue_IQK;
 605        u8      ThermalValue_DPK;
 606        u8      ThermalValue_AVG[AVG_THERMAL_NUM];
 607        u8      ThermalValue_AVG_index;
 608        u8      ThermalValue_RxGain;
 609        u8      ThermalValue_Crystal;
 610        u8      ThermalValue_DPKstore;
 611        u8      ThermalValue_DPKtrack;
 612        bool    TxPowerTrackingInProgress;
 613        bool    bDPKenable;
 614
 615        bool    bReloadtxpowerindex;
 616        u8      bRfPiEnable;
 617        u32     TXPowerTrackingCallbackCnt; /* cosa add for debug */
 618
 619        u8      bCCKinCH14;
 620        u8      CCK_index;
 621        u8      OFDM_index[2];
 622        bool bDoneTxpower;
 623
 624        u8      ThermalValue_HP[HP_THERMAL_NUM];
 625        u8      ThermalValue_HP_index;
 626        struct ijk_matrix_regs_set IQKMatrixRegSetting[IQK_Matrix_Settings_NUM];
 627
 628        u8      Delta_IQK;
 629        u8      Delta_LCK;
 630
 631        /* for IQK */
 632        u32     RegC04;
 633        u32     Reg874;
 634        u32     RegC08;
 635        u32     RegB68;
 636        u32     RegB6C;
 637        u32     Reg870;
 638        u32     Reg860;
 639        u32     Reg864;
 640
 641        bool    bIQKInitialized;
 642        bool    bLCKInProgress;
 643        bool    bAntennaDetected;
 644        u32     ADDA_backup[IQK_ADDA_REG_NUM];
 645        u32     IQK_MAC_backup[IQK_MAC_REG_NUM];
 646        u32     IQK_BB_backup_recover[9];
 647        u32     IQK_BB_backup[IQK_BB_REG_NUM];
 648
 649        /* for APK */
 650        u32     APKoutput[2][2]; /* path A/B; output1_1a/output1_2a */
 651        u8      bAPKdone;
 652        u8      bAPKThermalMeterIgnore;
 653        u8      bDPdone;
 654        u8      bDPPathAOK;
 655        u8      bDPPathBOK;
 656};
 657
 658/*  ODM Dynamic common info value definition */
 659
 660struct fast_ant_train {
 661        u8      Bssid[6];
 662        u8      antsel_rx_keep_0;
 663        u8      antsel_rx_keep_1;
 664        u8      antsel_rx_keep_2;
 665        u32     antSumRSSI[7];
 666        u32     antRSSIcnt[7];
 667        u32     antAveRSSI[7];
 668        u8      FAT_State;
 669        u32     TrainIdx;
 670        u8      antsel_a[ODM_ASSOCIATE_ENTRY_NUM];
 671        u8      antsel_b[ODM_ASSOCIATE_ENTRY_NUM];
 672        u8      antsel_c[ODM_ASSOCIATE_ENTRY_NUM];
 673        u32     MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
 674        u32     AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
 675        u32     MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
 676        u32     AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
 677        u8      RxIdleAnt;
 678        bool    bBecomeLinked;
 679};
 680
 681enum fat_state {
 682        FAT_NORMAL_STATE                = 0,
 683        FAT_TRAINING_STATE              = 1,
 684};
 685
 686enum ant_div_type {
 687        NO_ANTDIV                       = 0xFF,
 688        CG_TRX_HW_ANTDIV                = 0x01,
 689        CGCS_RX_HW_ANTDIV               = 0x02,
 690        FIXED_HW_ANTDIV                 = 0x03,
 691        CG_TRX_SMART_ANTDIV             = 0x04,
 692        CGCS_RX_SW_ANTDIV               = 0x05,
 693};
 694
 695/* Copy from SD4 defined structure. We use to support PHY DM integration. */
 696struct odm_dm_struct {
 697        /*      Add for different team use temporarily */
 698        struct adapter *Adapter;        /*  For CE/NIC team */
 699        struct rtl8192cd_priv *priv;    /*  For AP/ADSL team */
 700        /*  WHen you use above pointers, they must be initialized. */
 701        bool    odm_ready;
 702
 703        struct rtl8192cd_priv *fake_priv;
 704        u64     DebugComponents;
 705        u32     DebugLevel;
 706
 707/*  ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */
 708        bool    bCckHighPower;
 709        u8      RFPathRxEnable;         /*  ODM_CMNINFO_RFPATH_ENABLE */
 710        u8      ControlChannel;
 711/*  ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */
 712
 713/* 1  COMMON INFORMATION */
 714        /*  Init Value */
 715/* HOOK BEFORE REG INIT----------- */
 716        /*  ODM Platform info AP/ADSL/CE/MP = 1/2/3/4 */
 717        u8      SupportPlatform;
 718        /*  ODM Support Ability DIG/RATR/TX_PWR_TRACK/ ¡K¡K = 1/2/3/¡K */
 719        u32     SupportAbility;
 720        /*  ODM PCIE/USB/SDIO/GSPI = 0/1/2/3 */
 721        u8      SupportInterface;
 722        /*  ODM composite or independent. Bit oriented/ 92C+92D+ .... or any
 723         *  other type = 1/2/3/... */
 724        u32     SupportICType;
 725        /*  Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/... */
 726        u8      CutVersion;
 727        /*  Board Type Normal/HighPower/MiniCard/SLIM/Combo/. = 0/1/2/3/4/. */
 728        u8      BoardType;
 729        /*  with external LNA  NO/Yes = 0/1 */
 730        u8      ExtLNA;
 731        /*  with external PA  NO/Yes = 0/1 */
 732        u8      ExtPA;
 733        /*  with external TRSW  NO/Yes = 0/1 */
 734        u8      ExtTRSW;
 735        u8      PatchID; /* Customer ID */
 736        bool    bInHctTest;
 737        bool    bWIFITest;
 738
 739        bool    bDualMacSmartConcurrent;
 740        u32     BK_SupportAbility;
 741        u8      AntDivType;
 742/* HOOK BEFORE REG INIT----------- */
 743
 744        /*  Dynamic Value */
 745/*  POINTER REFERENCE----------- */
 746
 747        u8      u8_temp;
 748        bool    bool_temp;
 749        struct adapter *adapter_temp;
 750
 751        /*  MAC PHY Mode SMSP/DMSP/DMDP = 0/1/2 */
 752        u8      *pMacPhyMode;
 753        /* TX Unicast byte count */
 754        u64     *pNumTxBytesUnicast;
 755        /* RX Unicast byte count */
 756        u64     *pNumRxBytesUnicast;
 757        /*  Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3 */
 758        u8      *pWirelessMode; /* ODM_WIRELESS_MODE_E */
 759        /*  Frequence band 2.4G/5G = 0/1 */
 760        u8      *pBandType;
 761        /*  Secondary channel offset don't_care/below/above = 0/1/2 */
 762        u8      *pSecChOffset;
 763        /*  Security mode Open/WEP/AES/TKIP = 0/1/2/3 */
 764        u8      *pSecurity;
 765        /*  BW info 20M/40M/80M = 0/1/2 */
 766        u8      *pBandWidth;
 767        /*  Central channel location Ch1/Ch2/.... */
 768        u8      *pChannel;      /* central channel number */
 769        /*  Common info for 92D DMSP */
 770
 771        bool    *pbGetValueFromOtherMac;
 772        struct adapter **pBuddyAdapter;
 773        bool    *pbMasterOfDMSP; /* MAC0: master, MAC1: slave */
 774        /*  Common info for Status */
 775        bool    *pbScanInProcess;
 776        bool    *pbPowerSaving;
 777        /*  CCA Path 2-path/path-A/path-B = 0/1/2; using ODM_CCA_PATH_E. */
 778        u8      *pOnePathCCA;
 779        /* pMgntInfo->AntennaTest */
 780        u8      *pAntennaTest;
 781        bool    *pbNet_closed;
 782/*  POINTER REFERENCE----------- */
 783        /*  */
 784/* CALL BY VALUE------------- */
 785        bool    bWIFI_Direct;
 786        bool    bWIFI_Display;
 787        bool    bLinked;
 788        u8      RSSI_Min;
 789        u8      InterfaceIndex; /*  Add for 92D  dual MAC: 0--Mac0 1--Mac1 */
 790        bool    bIsMPChip;
 791        bool    bOneEntryOnly;
 792        /*  Common info for BTDM */
 793        bool    bBtDisabled;    /*  BT is disabled */
 794        bool    bBtHsOperation; /*  BT HS mode is under progress */
 795        u8      btHsDigVal;     /*  use BT rssi to decide the DIG value */
 796        bool    bBtDisableEdcaTurbo;/* Under some condition, don't enable the
 797                                     * EDCA Turbo */
 798        bool    bBtBusy;                        /*  BT is busy. */
 799/* CALL BY VALUE------------- */
 800
 801        /* 2 Define STA info. */
 802        /*  _ODM_STA_INFO */
 803        /*  For MP, we need to reduce one array pointer for default port.?? */
 804        struct sta_info *pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM];
 805
 806        u16     CurrminRptTime;
 807        struct odm_ra_info RAInfo[ODM_ASSOCIATE_ENTRY_NUM]; /* Use MacID as
 808                        * array index. STA MacID=0,
 809                        * VWiFi Client MacID={1, ODM_ASSOCIATE_ENTRY_NUM-1} */
 810        /*  */
 811        /*  2012/02/14 MH Add to share 88E ra with other SW team. */
 812        /*  We need to colelct all support abilit to a proper area. */
 813        /*  */
 814        bool    RaSupport88E;
 815
 816        /*  Define ........... */
 817
 818        /*  Latest packet phy info (ODM write) */
 819        struct odm_phy_dbg_info PhyDbgInfo;
 820
 821        /*  Latest packet phy info (ODM write) */
 822        struct odm_mac_status_info *pMacInfo;
 823
 824        /*  Different Team independt structure?? */
 825
 826        /* ODM Structure */
 827        struct fast_ant_train DM_FatTable;
 828        struct rtw_dig  DM_DigTable;
 829        struct rtl_ps   DM_PSTable;
 830        struct rx_hpc   DM_RXHP_Table;
 831        struct false_alarm_stats FalseAlmCnt;
 832        struct false_alarm_stats FlaseAlmCntBuddyAdapter;
 833        struct sw_ant_switch DM_SWAT_Table;
 834        bool            RSSI_test;
 835
 836        struct edca_turbo DM_EDCA_Table;
 837        u32             WMMEDCA_BE;
 838        /*  Copy from SD4 structure */
 839        /*  */
 840        /*  ================================================== */
 841        /*  */
 842
 843        bool    *pbDriverStopped;
 844        bool    *pbDriverIsGoingToPnpSetPowerSleep;
 845        bool    *pinit_adpt_in_progress;
 846
 847        /* PSD */
 848        bool    bUserAssignLevel;
 849        struct timer_list PSDTimer;
 850        u8      RSSI_BT;                        /* come from BT */
 851        bool    bPSDinProcess;
 852        bool    bDMInitialGainEnable;
 853
 854        /* for rate adaptive, in fact,  88c/92c fw will handle this */
 855        u8      bUseRAMask;
 856
 857        struct odm_rate_adapt RateAdaptive;
 858
 859        struct odm_rf_cal RFCalibrateInfo;
 860
 861        /*  TX power tracking */
 862        u8      BbSwingIdxOfdm;
 863        u8      BbSwingIdxOfdmCurrent;
 864        u8      BbSwingIdxOfdmBase;
 865        bool    BbSwingFlagOfdm;
 866        u8      BbSwingIdxCck;
 867        u8      BbSwingIdxCckCurrent;
 868        u8      BbSwingIdxCckBase;
 869        bool    BbSwingFlagCck;
 870        u8      *mp_mode;
 871        /*  ODM system resource. */
 872
 873        /*  ODM relative time. */
 874        struct timer_list PathDivSwitchTimer;
 875        /* 2011.09.27 add for Path Diversity */
 876        struct timer_list CCKPathDiversityTimer;
 877        struct timer_list FastAntTrainingTimer;
 878};              /*  DM_Dynamic_Mechanism_Structure */
 879
 880#define ODM_RF_PATH_MAX 3
 881
 882enum ODM_RF_CONTENT {
 883        odm_radioa_txt = 0x1000,
 884        odm_radiob_txt = 0x1001,
 885        odm_radioc_txt = 0x1002,
 886        odm_radiod_txt = 0x1003
 887};
 888
 889/*  Status code */
 890enum rt_status {
 891        RT_STATUS_SUCCESS,
 892        RT_STATUS_FAILURE,
 893        RT_STATUS_PENDING,
 894        RT_STATUS_RESOURCE,
 895        RT_STATUS_INVALID_CONTEXT,
 896        RT_STATUS_INVALID_PARAMETER,
 897        RT_STATUS_NOT_SUPPORT,
 898        RT_STATUS_OS_API_FAILED,
 899};
 900
 901/* 3=========================================================== */
 902/* 3 DIG */
 903/* 3=========================================================== */
 904
 905enum dm_dig_op {
 906        RT_TYPE_THRESH_HIGH     = 0,
 907        RT_TYPE_THRESH_LOW      = 1,
 908        RT_TYPE_BACKOFF         = 2,
 909        RT_TYPE_RX_GAIN_MIN     = 3,
 910        RT_TYPE_RX_GAIN_MAX     = 4,
 911        RT_TYPE_ENABLE          = 5,
 912        RT_TYPE_DISABLE         = 6,
 913        DIG_OP_TYPE_MAX
 914};
 915
 916#define         DM_DIG_THRESH_HIGH      40
 917#define         DM_DIG_THRESH_LOW       35
 918
 919#define         DM_SCAN_RSSI_TH         0x14 /* scan return issue for LC */
 920
 921
 922#define         DM_false_ALARM_THRESH_LOW       400
 923#define         DM_false_ALARM_THRESH_HIGH      1000
 924
 925#define         DM_DIG_MAX_NIC                  0x4e
 926#define         DM_DIG_MIN_NIC                  0x1e /* 0x22/0x1c */
 927
 928#define         DM_DIG_MAX_AP                   0x32
 929#define         DM_DIG_MIN_AP                   0x20
 930
 931#define         DM_DIG_MAX_NIC_HP               0x46
 932#define         DM_DIG_MIN_NIC_HP               0x2e
 933
 934#define         DM_DIG_MAX_AP_HP                0x42
 935#define         DM_DIG_MIN_AP_HP                0x30
 936
 937/* vivi 92c&92d has different definition, 20110504 */
 938/* this is for 92c */
 939#define         DM_DIG_FA_TH0                   0x200/* 0x20 */
 940#define         DM_DIG_FA_TH1                   0x300/* 0x100 */
 941#define         DM_DIG_FA_TH2                   0x400/* 0x200 */
 942/* this is for 92d */
 943#define         DM_DIG_FA_TH0_92D               0x100
 944#define         DM_DIG_FA_TH1_92D               0x400
 945#define         DM_DIG_FA_TH2_92D               0x600
 946
 947#define         DM_DIG_BACKOFF_MAX              12
 948#define         DM_DIG_BACKOFF_MIN              -4
 949#define         DM_DIG_BACKOFF_DEFAULT          10
 950
 951/* 3=========================================================== */
 952/* 3 AGC RX High Power Mode */
 953/* 3=========================================================== */
 954#define   LNA_Low_Gain_1                0x64
 955#define   LNA_Low_Gain_2                0x5A
 956#define   LNA_Low_Gain_3                0x58
 957
 958#define   FA_RXHP_TH1                   5000
 959#define   FA_RXHP_TH2                   1500
 960#define   FA_RXHP_TH3                   800
 961#define   FA_RXHP_TH4                   600
 962#define   FA_RXHP_TH5                   500
 963
 964/* 3=========================================================== */
 965/* 3 EDCA */
 966/* 3=========================================================== */
 967
 968/* 3=========================================================== */
 969/* 3 Dynamic Tx Power */
 970/* 3=========================================================== */
 971/* Dynamic Tx Power Control Threshold */
 972#define         TX_POWER_NEAR_FIELD_THRESH_LVL2 74
 973#define         TX_POWER_NEAR_FIELD_THRESH_LVL1 67
 974#define         TX_POWER_NEAR_FIELD_THRESH_AP           0x3F
 975
 976#define         TxHighPwrLevel_Normal           0
 977#define         TxHighPwrLevel_Level1           1
 978#define         TxHighPwrLevel_Level2           2
 979#define         TxHighPwrLevel_BT1              3
 980#define         TxHighPwrLevel_BT2              4
 981#define         TxHighPwrLevel_15               5
 982#define         TxHighPwrLevel_35               6
 983#define         TxHighPwrLevel_50               7
 984#define         TxHighPwrLevel_70               8
 985#define         TxHighPwrLevel_100              9
 986
 987/* 3=========================================================== */
 988/* 3 Rate Adaptive */
 989/* 3=========================================================== */
 990#define         DM_RATR_STA_INIT                0
 991#define         DM_RATR_STA_HIGH                1
 992#define         DM_RATR_STA_MIDDLE              2
 993#define         DM_RATR_STA_LOW                 3
 994
 995/* 3=========================================================== */
 996/* 3 BB Power Save */
 997/* 3=========================================================== */
 998
 999
1000enum dm_1r_cca {

1001        CCA_1R = 0,
1002        CCA_2R = 1,
1003        CCA_MAX = 2,
1004};
1005
1006enum dm_rf {
1007        RF_Save = 0,
1008        RF_Normal = 1,
1009        RF_MAX = 2,
1010};
1011
1012/* 3=========================================================== */
1013/* 3 Antenna Diversity */
1014/* 3=========================================================== */
1015enum dm_swas {
1016        Antenna_A = 1,
1017        Antenna_B = 2,
1018        Antenna_MAX = 3,
1019};
1020
1021/*  Maximal number of antenna detection mechanism needs to perform. */
1022#define MAX_ANTENNA_DETECTION_CNT       10
1023
1024/*  Extern Global Variables. */
1025#define OFDM_TABLE_SIZE_92C     37
1026#define OFDM_TABLE_SIZE_92D     43
1027#define CCK_TABLE_SIZE          33
1028
1029extern  u32 OFDMSwingTable[OFDM_TABLE_SIZE_92D];
1030extern  u8 CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8];
1031extern  u8 CCKSwingTable_Ch14[CCK_TABLE_SIZE][8];
1032
1033/*  check Sta pointer valid or not */
1034#define IS_STA_VALID(pSta)              (pSta)
1035/*  20100514 Joseph: Add definition for antenna switching test after link. */
1036/*  This indicates two different the steps. */
1037/*  In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the
1038 *  signal on the air. */
1039/*  In SWAW_STEP_DETERMINE, driver just compares the signal captured in
1040 *  SWAW_STEP_PEAK */
1041/*  with original RSSI to determine if it is necessary to switch antenna. */
1042#define SWAW_STEP_PEAK          0
1043#define SWAW_STEP_DETERMINE     1
1044
1045#define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck
1046#define dm_RF_Saving    ODM_RF_Saving
1047
1048void ODM_RF_Saving(struct odm_dm_struct *pDM_Odm, u8 bForceInNormal);
1049void ODM_TXPowerTrackingCheck(struct odm_dm_struct *pDM_Odm);
1050void odm_DIGbyRSSI_LPS(struct odm_dm_struct *pDM_Odm);
1051void ODM_Write_CCK_CCA_Thres(struct odm_dm_struct *pDM_Odm, u8 CurCCK_CCAThres);
1052bool ODM_RAStateCheck(struct odm_dm_struct *pDM_Odm, s32 RSSI,
1053                      bool bForceUpdate, u8 *pRATRState);
1054u32 ConvertTo_dB(u32 Value);
1055u32 ODM_Get_Rate_Bitmap(struct odm_dm_struct *pDM_Odm, u32 macid,
1056                        u32 ra_mask, u8 rssi_level);
1057void ODM_CmnInfoInit(struct odm_dm_struct *pDM_Odm,
1058                     enum odm_common_info_def CmnInfo, u32 Value);
1059void ODM_CmnInfoUpdate(struct odm_dm_struct *pDM_Odm, u32 CmnInfo, u64 Value);
1060void ODM_CmnInfoHook(struct odm_dm_struct *pDM_Odm,
1061                     enum odm_common_info_def CmnInfo, void *pValue);
1062void ODM_CmnInfoPtrArrayHook(struct odm_dm_struct *pDM_Odm,
1063                             enum odm_common_info_def CmnInfo,
1064                             u16 Index, void *pValue);
1065void ODM_DMInit(struct odm_dm_struct *pDM_Odm);
1066void ODM_DMWatchdog(struct odm_dm_struct *pDM_Odm);
1067void ODM_Write_DIG(struct odm_dm_struct *pDM_Odm, u8 CurrentIGI);
1068
1069#endif
1070