linux/drivers/tty/synclink.c
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   1/*
   2 * $Id: synclink.c,v 4.38 2005/11/07 16:30:34 paulkf Exp $
   3 *
   4 * Device driver for Microgate SyncLink ISA and PCI
   5 * high speed multiprotocol serial adapters.
   6 *
   7 * written by Paul Fulghum for Microgate Corporation
   8 * paulkf@microgate.com
   9 *
  10 * Microgate and SyncLink are trademarks of Microgate Corporation
  11 *
  12 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
  13 *
  14 * Original release 01/11/99
  15 *
  16 * This code is released under the GNU General Public License (GPL)
  17 *
  18 * This driver is primarily intended for use in synchronous
  19 * HDLC mode. Asynchronous mode is also provided.
  20 *
  21 * When operating in synchronous mode, each call to mgsl_write()
  22 * contains exactly one complete HDLC frame. Calling mgsl_put_char
  23 * will start assembling an HDLC frame that will not be sent until
  24 * mgsl_flush_chars or mgsl_write is called.
  25 * 
  26 * Synchronous receive data is reported as complete frames. To accomplish
  27 * this, the TTY flip buffer is bypassed (too small to hold largest
  28 * frame and may fragment frames) and the line discipline
  29 * receive entry point is called directly.
  30 *
  31 * This driver has been tested with a slightly modified ppp.c driver
  32 * for synchronous PPP.
  33 *
  34 * 2000/02/16
  35 * Added interface for syncppp.c driver (an alternate synchronous PPP
  36 * implementation that also supports Cisco HDLC). Each device instance
  37 * registers as a tty device AND a network device (if dosyncppp option
  38 * is set for the device). The functionality is determined by which
  39 * device interface is opened.
  40 *
  41 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  42 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  43 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  44 * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  45 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  46 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  47 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  48 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  49 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  50 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  51 * OF THE POSSIBILITY OF SUCH DAMAGE.
  52 */
  53
  54#if defined(__i386__)
  55#  define BREAKPOINT() asm("   int $3");
  56#else
  57#  define BREAKPOINT() { }
  58#endif
  59
  60#define MAX_ISA_DEVICES 10
  61#define MAX_PCI_DEVICES 10
  62#define MAX_TOTAL_DEVICES 20
  63
  64#include <linux/module.h>
  65#include <linux/errno.h>
  66#include <linux/signal.h>
  67#include <linux/sched.h>
  68#include <linux/timer.h>
  69#include <linux/interrupt.h>
  70#include <linux/pci.h>
  71#include <linux/tty.h>
  72#include <linux/tty_flip.h>
  73#include <linux/serial.h>
  74#include <linux/major.h>
  75#include <linux/string.h>
  76#include <linux/fcntl.h>
  77#include <linux/ptrace.h>
  78#include <linux/ioport.h>
  79#include <linux/mm.h>
  80#include <linux/seq_file.h>
  81#include <linux/slab.h>
  82#include <linux/delay.h>
  83#include <linux/netdevice.h>
  84#include <linux/vmalloc.h>
  85#include <linux/init.h>
  86#include <linux/ioctl.h>
  87#include <linux/synclink.h>
  88
  89#include <asm/io.h>
  90#include <asm/irq.h>
  91#include <asm/dma.h>
  92#include <linux/bitops.h>
  93#include <asm/types.h>
  94#include <linux/termios.h>
  95#include <linux/workqueue.h>
  96#include <linux/hdlc.h>
  97#include <linux/dma-mapping.h>
  98
  99#if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_MODULE))
 100#define SYNCLINK_GENERIC_HDLC 1
 101#else
 102#define SYNCLINK_GENERIC_HDLC 0
 103#endif
 104
 105#define GET_USER(error,value,addr) error = get_user(value,addr)
 106#define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
 107#define PUT_USER(error,value,addr) error = put_user(value,addr)
 108#define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
 109
 110#include <asm/uaccess.h>
 111
 112#define RCLRVALUE 0xffff
 113
 114static MGSL_PARAMS default_params = {
 115        MGSL_MODE_HDLC,                 /* unsigned long mode */
 116        0,                              /* unsigned char loopback; */
 117        HDLC_FLAG_UNDERRUN_ABORT15,     /* unsigned short flags; */
 118        HDLC_ENCODING_NRZI_SPACE,       /* unsigned char encoding; */
 119        0,                              /* unsigned long clock_speed; */
 120        0xff,                           /* unsigned char addr_filter; */
 121        HDLC_CRC_16_CCITT,              /* unsigned short crc_type; */
 122        HDLC_PREAMBLE_LENGTH_8BITS,     /* unsigned char preamble_length; */
 123        HDLC_PREAMBLE_PATTERN_NONE,     /* unsigned char preamble; */
 124        9600,                           /* unsigned long data_rate; */
 125        8,                              /* unsigned char data_bits; */
 126        1,                              /* unsigned char stop_bits; */
 127        ASYNC_PARITY_NONE               /* unsigned char parity; */
 128};
 129
 130#define SHARED_MEM_ADDRESS_SIZE 0x40000
 131#define BUFFERLISTSIZE 4096
 132#define DMABUFFERSIZE 4096
 133#define MAXRXFRAMES 7
 134
 135typedef struct _DMABUFFERENTRY
 136{
 137        u32 phys_addr;  /* 32-bit flat physical address of data buffer */
 138        volatile u16 count;     /* buffer size/data count */
 139        volatile u16 status;    /* Control/status field */
 140        volatile u16 rcc;       /* character count field */
 141        u16 reserved;   /* padding required by 16C32 */
 142        u32 link;       /* 32-bit flat link to next buffer entry */
 143        char *virt_addr;        /* virtual address of data buffer */
 144        u32 phys_entry; /* physical address of this buffer entry */
 145        dma_addr_t dma_addr;
 146} DMABUFFERENTRY, *DMAPBUFFERENTRY;
 147
 148/* The queue of BH actions to be performed */
 149
 150#define BH_RECEIVE  1
 151#define BH_TRANSMIT 2
 152#define BH_STATUS   4
 153
 154#define IO_PIN_SHUTDOWN_LIMIT 100
 155
 156struct  _input_signal_events {
 157        int     ri_up;  
 158        int     ri_down;
 159        int     dsr_up;
 160        int     dsr_down;
 161        int     dcd_up;
 162        int     dcd_down;
 163        int     cts_up;
 164        int     cts_down;
 165};
 166
 167/* transmit holding buffer definitions*/
 168#define MAX_TX_HOLDING_BUFFERS 5
 169struct tx_holding_buffer {
 170        int     buffer_size;
 171        unsigned char * buffer;
 172};
 173
 174
 175/*
 176 * Device instance data structure
 177 */
 178 
 179struct mgsl_struct {
 180        int                     magic;
 181        struct tty_port         port;
 182        int                     line;
 183        int                     hw_version;
 184        
 185        struct mgsl_icount      icount;
 186        
 187        int                     timeout;
 188        int                     x_char;         /* xon/xoff character */
 189        u16                     read_status_mask;
 190        u16                     ignore_status_mask;     
 191        unsigned char           *xmit_buf;
 192        int                     xmit_head;
 193        int                     xmit_tail;
 194        int                     xmit_cnt;
 195        
 196        wait_queue_head_t       status_event_wait_q;
 197        wait_queue_head_t       event_wait_q;
 198        struct timer_list       tx_timer;       /* HDLC transmit timeout timer */
 199        struct mgsl_struct      *next_device;   /* device list link */
 200        
 201        spinlock_t irq_spinlock;                /* spinlock for synchronizing with ISR */
 202        struct work_struct task;                /* task structure for scheduling bh */
 203
 204        u32 EventMask;                  /* event trigger mask */
 205        u32 RecordedEvents;             /* pending events */
 206
 207        u32 max_frame_size;             /* as set by device config */
 208
 209        u32 pending_bh;
 210
 211        bool bh_running;                /* Protection from multiple */
 212        int isr_overflow;
 213        bool bh_requested;
 214        
 215        int dcd_chkcount;               /* check counts to prevent */
 216        int cts_chkcount;               /* too many IRQs if a signal */
 217        int dsr_chkcount;               /* is floating */
 218        int ri_chkcount;
 219
 220        char *buffer_list;              /* virtual address of Rx & Tx buffer lists */
 221        u32 buffer_list_phys;
 222        dma_addr_t buffer_list_dma_addr;
 223
 224        unsigned int rx_buffer_count;   /* count of total allocated Rx buffers */
 225        DMABUFFERENTRY *rx_buffer_list; /* list of receive buffer entries */
 226        unsigned int current_rx_buffer;
 227
 228        int num_tx_dma_buffers;         /* number of tx dma frames required */
 229        int tx_dma_buffers_used;
 230        unsigned int tx_buffer_count;   /* count of total allocated Tx buffers */
 231        DMABUFFERENTRY *tx_buffer_list; /* list of transmit buffer entries */
 232        int start_tx_dma_buffer;        /* tx dma buffer to start tx dma operation */
 233        int current_tx_buffer;          /* next tx dma buffer to be loaded */
 234        
 235        unsigned char *intermediate_rxbuffer;
 236
 237        int num_tx_holding_buffers;     /* number of tx holding buffer allocated */
 238        int get_tx_holding_index;       /* next tx holding buffer for adapter to load */
 239        int put_tx_holding_index;       /* next tx holding buffer to store user request */
 240        int tx_holding_count;           /* number of tx holding buffers waiting */
 241        struct tx_holding_buffer tx_holding_buffers[MAX_TX_HOLDING_BUFFERS];
 242
 243        bool rx_enabled;
 244        bool rx_overflow;
 245        bool rx_rcc_underrun;
 246
 247        bool tx_enabled;
 248        bool tx_active;
 249        u32 idle_mode;
 250
 251        u16 cmr_value;
 252        u16 tcsr_value;
 253
 254        char device_name[25];           /* device instance name */
 255
 256        unsigned int bus_type;  /* expansion bus type (ISA,EISA,PCI) */
 257        unsigned char bus;              /* expansion bus number (zero based) */
 258        unsigned char function;         /* PCI device number */
 259
 260        unsigned int io_base;           /* base I/O address of adapter */
 261        unsigned int io_addr_size;      /* size of the I/O address range */
 262        bool io_addr_requested;         /* true if I/O address requested */
 263        
 264        unsigned int irq_level;         /* interrupt level */
 265        unsigned long irq_flags;
 266        bool irq_requested;             /* true if IRQ requested */
 267        
 268        unsigned int dma_level;         /* DMA channel */
 269        bool dma_requested;             /* true if dma channel requested */
 270
 271        u16 mbre_bit;
 272        u16 loopback_bits;
 273        u16 usc_idle_mode;
 274
 275        MGSL_PARAMS params;             /* communications parameters */
 276
 277        unsigned char serial_signals;   /* current serial signal states */
 278
 279        bool irq_occurred;              /* for diagnostics use */
 280        unsigned int init_error;        /* Initialization startup error                 (DIAGS) */
 281        int     fDiagnosticsmode;       /* Driver in Diagnostic mode?                   (DIAGS) */
 282
 283        u32 last_mem_alloc;
 284        unsigned char* memory_base;     /* shared memory address (PCI only) */
 285        u32 phys_memory_base;
 286        bool shared_mem_requested;
 287
 288        unsigned char* lcr_base;        /* local config registers (PCI only) */
 289        u32 phys_lcr_base;
 290        u32 lcr_offset;
 291        bool lcr_mem_requested;
 292
 293        u32 misc_ctrl_value;
 294        char *flag_buf;
 295        bool drop_rts_on_tx_done;
 296
 297        bool loopmode_insert_requested;
 298        bool loopmode_send_done_requested;
 299        
 300        struct  _input_signal_events    input_signal_events;
 301
 302        /* generic HDLC device parts */
 303        int netcount;
 304        spinlock_t netlock;
 305
 306#if SYNCLINK_GENERIC_HDLC
 307        struct net_device *netdev;
 308#endif
 309};
 310
 311#define MGSL_MAGIC 0x5401
 312
 313/*
 314 * The size of the serial xmit buffer is 1 page, or 4096 bytes
 315 */
 316#ifndef SERIAL_XMIT_SIZE
 317#define SERIAL_XMIT_SIZE 4096
 318#endif
 319
 320/*
 321 * These macros define the offsets used in calculating the
 322 * I/O address of the specified USC registers.
 323 */
 324
 325
 326#define DCPIN 2         /* Bit 1 of I/O address */
 327#define SDPIN 4         /* Bit 2 of I/O address */
 328
 329#define DCAR 0          /* DMA command/address register */
 330#define CCAR SDPIN              /* channel command/address register */
 331#define DATAREG DCPIN + SDPIN   /* serial data register */
 332#define MSBONLY 0x41
 333#define LSBONLY 0x40
 334
 335/*
 336 * These macros define the register address (ordinal number)
 337 * used for writing address/value pairs to the USC.
 338 */
 339
 340#define CMR     0x02    /* Channel mode Register */
 341#define CCSR    0x04    /* Channel Command/status Register */
 342#define CCR     0x06    /* Channel Control Register */
 343#define PSR     0x08    /* Port status Register */
 344#define PCR     0x0a    /* Port Control Register */
 345#define TMDR    0x0c    /* Test mode Data Register */
 346#define TMCR    0x0e    /* Test mode Control Register */
 347#define CMCR    0x10    /* Clock mode Control Register */
 348#define HCR     0x12    /* Hardware Configuration Register */
 349#define IVR     0x14    /* Interrupt Vector Register */
 350#define IOCR    0x16    /* Input/Output Control Register */
 351#define ICR     0x18    /* Interrupt Control Register */
 352#define DCCR    0x1a    /* Daisy Chain Control Register */
 353#define MISR    0x1c    /* Misc Interrupt status Register */
 354#define SICR    0x1e    /* status Interrupt Control Register */
 355#define RDR     0x20    /* Receive Data Register */
 356#define RMR     0x22    /* Receive mode Register */
 357#define RCSR    0x24    /* Receive Command/status Register */
 358#define RICR    0x26    /* Receive Interrupt Control Register */
 359#define RSR     0x28    /* Receive Sync Register */
 360#define RCLR    0x2a    /* Receive count Limit Register */
 361#define RCCR    0x2c    /* Receive Character count Register */
 362#define TC0R    0x2e    /* Time Constant 0 Register */
 363#define TDR     0x30    /* Transmit Data Register */
 364#define TMR     0x32    /* Transmit mode Register */
 365#define TCSR    0x34    /* Transmit Command/status Register */
 366#define TICR    0x36    /* Transmit Interrupt Control Register */
 367#define TSR     0x38    /* Transmit Sync Register */
 368#define TCLR    0x3a    /* Transmit count Limit Register */
 369#define TCCR    0x3c    /* Transmit Character count Register */
 370#define TC1R    0x3e    /* Time Constant 1 Register */
 371
 372
 373/*
 374 * MACRO DEFINITIONS FOR DMA REGISTERS
 375 */
 376
 377#define DCR     0x06    /* DMA Control Register (shared) */
 378#define DACR    0x08    /* DMA Array count Register (shared) */
 379#define BDCR    0x12    /* Burst/Dwell Control Register (shared) */
 380#define DIVR    0x14    /* DMA Interrupt Vector Register (shared) */    
 381#define DICR    0x18    /* DMA Interrupt Control Register (shared) */
 382#define CDIR    0x1a    /* Clear DMA Interrupt Register (shared) */
 383#define SDIR    0x1c    /* Set DMA Interrupt Register (shared) */
 384
 385#define TDMR    0x02    /* Transmit DMA mode Register */
 386#define TDIAR   0x1e    /* Transmit DMA Interrupt Arm Register */
 387#define TBCR    0x2a    /* Transmit Byte count Register */
 388#define TARL    0x2c    /* Transmit Address Register (low) */
 389#define TARU    0x2e    /* Transmit Address Register (high) */
 390#define NTBCR   0x3a    /* Next Transmit Byte count Register */
 391#define NTARL   0x3c    /* Next Transmit Address Register (low) */
 392#define NTARU   0x3e    /* Next Transmit Address Register (high) */
 393
 394#define RDMR    0x82    /* Receive DMA mode Register (non-shared) */
 395#define RDIAR   0x9e    /* Receive DMA Interrupt Arm Register */
 396#define RBCR    0xaa    /* Receive Byte count Register */
 397#define RARL    0xac    /* Receive Address Register (low) */
 398#define RARU    0xae    /* Receive Address Register (high) */
 399#define NRBCR   0xba    /* Next Receive Byte count Register */
 400#define NRARL   0xbc    /* Next Receive Address Register (low) */
 401#define NRARU   0xbe    /* Next Receive Address Register (high) */
 402
 403
 404/*
 405 * MACRO DEFINITIONS FOR MODEM STATUS BITS
 406 */
 407
 408#define MODEMSTATUS_DTR 0x80
 409#define MODEMSTATUS_DSR 0x40
 410#define MODEMSTATUS_RTS 0x20
 411#define MODEMSTATUS_CTS 0x10
 412#define MODEMSTATUS_RI  0x04
 413#define MODEMSTATUS_DCD 0x01
 414
 415
 416/*
 417 * Channel Command/Address Register (CCAR) Command Codes
 418 */
 419
 420#define RTCmd_Null                      0x0000
 421#define RTCmd_ResetHighestIus           0x1000
 422#define RTCmd_TriggerChannelLoadDma     0x2000
 423#define RTCmd_TriggerRxDma              0x2800
 424#define RTCmd_TriggerTxDma              0x3000
 425#define RTCmd_TriggerRxAndTxDma         0x3800
 426#define RTCmd_PurgeRxFifo               0x4800
 427#define RTCmd_PurgeTxFifo               0x5000
 428#define RTCmd_PurgeRxAndTxFifo          0x5800
 429#define RTCmd_LoadRcc                   0x6800
 430#define RTCmd_LoadTcc                   0x7000
 431#define RTCmd_LoadRccAndTcc             0x7800
 432#define RTCmd_LoadTC0                   0x8800
 433#define RTCmd_LoadTC1                   0x9000
 434#define RTCmd_LoadTC0AndTC1             0x9800
 435#define RTCmd_SerialDataLSBFirst        0xa000
 436#define RTCmd_SerialDataMSBFirst        0xa800
 437#define RTCmd_SelectBigEndian           0xb000
 438#define RTCmd_SelectLittleEndian        0xb800
 439
 440
 441/*
 442 * DMA Command/Address Register (DCAR) Command Codes
 443 */
 444
 445#define DmaCmd_Null                     0x0000
 446#define DmaCmd_ResetTxChannel           0x1000
 447#define DmaCmd_ResetRxChannel           0x1200
 448#define DmaCmd_StartTxChannel           0x2000
 449#define DmaCmd_StartRxChannel           0x2200
 450#define DmaCmd_ContinueTxChannel        0x3000
 451#define DmaCmd_ContinueRxChannel        0x3200
 452#define DmaCmd_PauseTxChannel           0x4000
 453#define DmaCmd_PauseRxChannel           0x4200
 454#define DmaCmd_AbortTxChannel           0x5000
 455#define DmaCmd_AbortRxChannel           0x5200
 456#define DmaCmd_InitTxChannel            0x7000
 457#define DmaCmd_InitRxChannel            0x7200
 458#define DmaCmd_ResetHighestDmaIus       0x8000
 459#define DmaCmd_ResetAllChannels         0x9000
 460#define DmaCmd_StartAllChannels         0xa000
 461#define DmaCmd_ContinueAllChannels      0xb000
 462#define DmaCmd_PauseAllChannels         0xc000
 463#define DmaCmd_AbortAllChannels         0xd000
 464#define DmaCmd_InitAllChannels          0xf000
 465
 466#define TCmd_Null                       0x0000
 467#define TCmd_ClearTxCRC                 0x2000
 468#define TCmd_SelectTicrTtsaData         0x4000
 469#define TCmd_SelectTicrTxFifostatus     0x5000
 470#define TCmd_SelectTicrIntLevel         0x6000
 471#define TCmd_SelectTicrdma_level                0x7000
 472#define TCmd_SendFrame                  0x8000
 473#define TCmd_SendAbort                  0x9000
 474#define TCmd_EnableDleInsertion         0xc000
 475#define TCmd_DisableDleInsertion        0xd000
 476#define TCmd_ClearEofEom                0xe000
 477#define TCmd_SetEofEom                  0xf000
 478
 479#define RCmd_Null                       0x0000
 480#define RCmd_ClearRxCRC                 0x2000
 481#define RCmd_EnterHuntmode              0x3000
 482#define RCmd_SelectRicrRtsaData         0x4000
 483#define RCmd_SelectRicrRxFifostatus     0x5000
 484#define RCmd_SelectRicrIntLevel         0x6000
 485#define RCmd_SelectRicrdma_level                0x7000
 486
 487/*
 488 * Bits for enabling and disabling IRQs in Interrupt Control Register (ICR)
 489 */
 490 
 491#define RECEIVE_STATUS          BIT5
 492#define RECEIVE_DATA            BIT4
 493#define TRANSMIT_STATUS         BIT3
 494#define TRANSMIT_DATA           BIT2
 495#define IO_PIN                  BIT1
 496#define MISC                    BIT0
 497
 498
 499/*
 500 * Receive status Bits in Receive Command/status Register RCSR
 501 */
 502
 503#define RXSTATUS_SHORT_FRAME            BIT8
 504#define RXSTATUS_CODE_VIOLATION         BIT8
 505#define RXSTATUS_EXITED_HUNT            BIT7
 506#define RXSTATUS_IDLE_RECEIVED          BIT6
 507#define RXSTATUS_BREAK_RECEIVED         BIT5
 508#define RXSTATUS_ABORT_RECEIVED         BIT5
 509#define RXSTATUS_RXBOUND                BIT4
 510#define RXSTATUS_CRC_ERROR              BIT3
 511#define RXSTATUS_FRAMING_ERROR          BIT3
 512#define RXSTATUS_ABORT                  BIT2
 513#define RXSTATUS_PARITY_ERROR           BIT2
 514#define RXSTATUS_OVERRUN                BIT1
 515#define RXSTATUS_DATA_AVAILABLE         BIT0
 516#define RXSTATUS_ALL                    0x01f6
 517#define usc_UnlatchRxstatusBits(a,b) usc_OutReg( (a), RCSR, (u16)((b) & RXSTATUS_ALL) )
 518
 519/*
 520 * Values for setting transmit idle mode in 
 521 * Transmit Control/status Register (TCSR)
 522 */
 523#define IDLEMODE_FLAGS                  0x0000
 524#define IDLEMODE_ALT_ONE_ZERO           0x0100
 525#define IDLEMODE_ZERO                   0x0200
 526#define IDLEMODE_ONE                    0x0300
 527#define IDLEMODE_ALT_MARK_SPACE         0x0500
 528#define IDLEMODE_SPACE                  0x0600
 529#define IDLEMODE_MARK                   0x0700
 530#define IDLEMODE_MASK                   0x0700
 531
 532/*
 533 * IUSC revision identifiers
 534 */
 535#define IUSC_SL1660                     0x4d44
 536#define IUSC_PRE_SL1660                 0x4553
 537
 538/*
 539 * Transmit status Bits in Transmit Command/status Register (TCSR)
 540 */
 541
 542#define TCSR_PRESERVE                   0x0F00
 543
 544#define TCSR_UNDERWAIT                  BIT11
 545#define TXSTATUS_PREAMBLE_SENT          BIT7
 546#define TXSTATUS_IDLE_SENT              BIT6
 547#define TXSTATUS_ABORT_SENT             BIT5
 548#define TXSTATUS_EOF_SENT               BIT4
 549#define TXSTATUS_EOM_SENT               BIT4
 550#define TXSTATUS_CRC_SENT               BIT3
 551#define TXSTATUS_ALL_SENT               BIT2
 552#define TXSTATUS_UNDERRUN               BIT1
 553#define TXSTATUS_FIFO_EMPTY             BIT0
 554#define TXSTATUS_ALL                    0x00fa
 555#define usc_UnlatchTxstatusBits(a,b) usc_OutReg( (a), TCSR, (u16)((a)->tcsr_value + ((b) & 0x00FF)) )
 556                                
 557
 558#define MISCSTATUS_RXC_LATCHED          BIT15
 559#define MISCSTATUS_RXC                  BIT14
 560#define MISCSTATUS_TXC_LATCHED          BIT13
 561#define MISCSTATUS_TXC                  BIT12
 562#define MISCSTATUS_RI_LATCHED           BIT11
 563#define MISCSTATUS_RI                   BIT10
 564#define MISCSTATUS_DSR_LATCHED          BIT9
 565#define MISCSTATUS_DSR                  BIT8
 566#define MISCSTATUS_DCD_LATCHED          BIT7
 567#define MISCSTATUS_DCD                  BIT6
 568#define MISCSTATUS_CTS_LATCHED          BIT5
 569#define MISCSTATUS_CTS                  BIT4
 570#define MISCSTATUS_RCC_UNDERRUN         BIT3
 571#define MISCSTATUS_DPLL_NO_SYNC         BIT2
 572#define MISCSTATUS_BRG1_ZERO            BIT1
 573#define MISCSTATUS_BRG0_ZERO            BIT0
 574
 575#define usc_UnlatchIostatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0xaaa0))
 576#define usc_UnlatchMiscstatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0x000f))
 577
 578#define SICR_RXC_ACTIVE                 BIT15
 579#define SICR_RXC_INACTIVE               BIT14
 580#define SICR_RXC                        (BIT15|BIT14)
 581#define SICR_TXC_ACTIVE                 BIT13
 582#define SICR_TXC_INACTIVE               BIT12
 583#define SICR_TXC                        (BIT13|BIT12)
 584#define SICR_RI_ACTIVE                  BIT11
 585#define SICR_RI_INACTIVE                BIT10
 586#define SICR_RI                         (BIT11|BIT10)
 587#define SICR_DSR_ACTIVE                 BIT9
 588#define SICR_DSR_INACTIVE               BIT8
 589#define SICR_DSR                        (BIT9|BIT8)
 590#define SICR_DCD_ACTIVE                 BIT7
 591#define SICR_DCD_INACTIVE               BIT6
 592#define SICR_DCD                        (BIT7|BIT6)
 593#define SICR_CTS_ACTIVE                 BIT5
 594#define SICR_CTS_INACTIVE               BIT4
 595#define SICR_CTS                        (BIT5|BIT4)
 596#define SICR_RCC_UNDERFLOW              BIT3
 597#define SICR_DPLL_NO_SYNC               BIT2
 598#define SICR_BRG1_ZERO                  BIT1
 599#define SICR_BRG0_ZERO                  BIT0
 600
 601void usc_DisableMasterIrqBit( struct mgsl_struct *info );
 602void usc_EnableMasterIrqBit( struct mgsl_struct *info );
 603void usc_EnableInterrupts( struct mgsl_struct *info, u16 IrqMask );
 604void usc_DisableInterrupts( struct mgsl_struct *info, u16 IrqMask );
 605void usc_ClearIrqPendingBits( struct mgsl_struct *info, u16 IrqMask );
 606
 607#define usc_EnableInterrupts( a, b ) \
 608        usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0xc0 + (b)) )
 609
 610#define usc_DisableInterrupts( a, b ) \
 611        usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0x80 + (b)) )
 612
 613#define usc_EnableMasterIrqBit(a) \
 614        usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0x0f00) + 0xb000) )
 615
 616#define usc_DisableMasterIrqBit(a) \
 617        usc_OutReg( (a), ICR, (u16)(usc_InReg((a),ICR) & 0x7f00) )
 618
 619#define usc_ClearIrqPendingBits( a, b ) usc_OutReg( (a), DCCR, 0x40 + (b) )
 620
 621/*
 622 * Transmit status Bits in Transmit Control status Register (TCSR)
 623 * and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0)
 624 */
 625
 626#define TXSTATUS_PREAMBLE_SENT  BIT7
 627#define TXSTATUS_IDLE_SENT      BIT6
 628#define TXSTATUS_ABORT_SENT     BIT5
 629#define TXSTATUS_EOF            BIT4
 630#define TXSTATUS_CRC_SENT       BIT3
 631#define TXSTATUS_ALL_SENT       BIT2
 632#define TXSTATUS_UNDERRUN       BIT1
 633#define TXSTATUS_FIFO_EMPTY     BIT0
 634
 635#define DICR_MASTER             BIT15
 636#define DICR_TRANSMIT           BIT0
 637#define DICR_RECEIVE            BIT1
 638
 639#define usc_EnableDmaInterrupts(a,b) \
 640        usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) | (b)) )
 641
 642#define usc_DisableDmaInterrupts(a,b) \
 643        usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) & ~(b)) )
 644
 645#define usc_EnableStatusIrqs(a,b) \
 646        usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) | (b)) )
 647
 648#define usc_DisablestatusIrqs(a,b) \
 649        usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) & ~(b)) )
 650
 651/* Transmit status Bits in Transmit Control status Register (TCSR) */
 652/* and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0) */
 653
 654
 655#define DISABLE_UNCONDITIONAL    0
 656#define DISABLE_END_OF_FRAME     1
 657#define ENABLE_UNCONDITIONAL     2
 658#define ENABLE_AUTO_CTS          3
 659#define ENABLE_AUTO_DCD          3
 660#define usc_EnableTransmitter(a,b) \
 661        usc_OutReg( (a), TMR, (u16)((usc_InReg((a),TMR) & 0xfffc) | (b)) )
 662#define usc_EnableReceiver(a,b) \
 663        usc_OutReg( (a), RMR, (u16)((usc_InReg((a),RMR) & 0xfffc) | (b)) )
 664
 665static u16  usc_InDmaReg( struct mgsl_struct *info, u16 Port );
 666static void usc_OutDmaReg( struct mgsl_struct *info, u16 Port, u16 Value );
 667static void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd );
 668
 669static u16  usc_InReg( struct mgsl_struct *info, u16 Port );
 670static void usc_OutReg( struct mgsl_struct *info, u16 Port, u16 Value );
 671static void usc_RTCmd( struct mgsl_struct *info, u16 Cmd );
 672void usc_RCmd( struct mgsl_struct *info, u16 Cmd );
 673void usc_TCmd( struct mgsl_struct *info, u16 Cmd );
 674
 675#define usc_TCmd(a,b) usc_OutReg((a), TCSR, (u16)((a)->tcsr_value + (b)))
 676#define usc_RCmd(a,b) usc_OutReg((a), RCSR, (b))
 677
 678#define usc_SetTransmitSyncChars(a,s0,s1) usc_OutReg((a), TSR, (u16)(((u16)s0<<8)|(u16)s1))
 679
 680static void usc_process_rxoverrun_sync( struct mgsl_struct *info );
 681static void usc_start_receiver( struct mgsl_struct *info );
 682static void usc_stop_receiver( struct mgsl_struct *info );
 683
 684static void usc_start_transmitter( struct mgsl_struct *info );
 685static void usc_stop_transmitter( struct mgsl_struct *info );
 686static void usc_set_txidle( struct mgsl_struct *info );
 687static void usc_load_txfifo( struct mgsl_struct *info );
 688
 689static void usc_enable_aux_clock( struct mgsl_struct *info, u32 DataRate );
 690static void usc_enable_loopback( struct mgsl_struct *info, int enable );
 691
 692static void usc_get_serial_signals( struct mgsl_struct *info );
 693static void usc_set_serial_signals( struct mgsl_struct *info );
 694
 695static void usc_reset( struct mgsl_struct *info );
 696
 697static void usc_set_sync_mode( struct mgsl_struct *info );
 698static void usc_set_sdlc_mode( struct mgsl_struct *info );
 699static void usc_set_async_mode( struct mgsl_struct *info );
 700static void usc_enable_async_clock( struct mgsl_struct *info, u32 DataRate );
 701
 702static void usc_loopback_frame( struct mgsl_struct *info );
 703
 704static void mgsl_tx_timeout(unsigned long context);
 705
 706
 707static void usc_loopmode_cancel_transmit( struct mgsl_struct * info );
 708static void usc_loopmode_insert_request( struct mgsl_struct * info );
 709static int usc_loopmode_active( struct mgsl_struct * info);
 710static void usc_loopmode_send_done( struct mgsl_struct * info );
 711
 712static int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg);
 713
 714#if SYNCLINK_GENERIC_HDLC
 715#define dev_to_port(D) (dev_to_hdlc(D)->priv)
 716static void hdlcdev_tx_done(struct mgsl_struct *info);
 717static void hdlcdev_rx(struct mgsl_struct *info, char *buf, int size);
 718static int  hdlcdev_init(struct mgsl_struct *info);
 719static void hdlcdev_exit(struct mgsl_struct *info);
 720#endif
 721
 722/*
 723 * Defines a BUS descriptor value for the PCI adapter
 724 * local bus address ranges.
 725 */
 726
 727#define BUS_DESCRIPTOR( WrHold, WrDly, RdDly, Nwdd, Nwad, Nxda, Nrdd, Nrad ) \
 728(0x00400020 + \
 729((WrHold) << 30) + \
 730((WrDly)  << 28) + \
 731((RdDly)  << 26) + \
 732((Nwdd)   << 20) + \
 733((Nwad)   << 15) + \
 734((Nxda)   << 13) + \
 735((Nrdd)   << 11) + \
 736((Nrad)   <<  6) )
 737
 738static void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit);
 739
 740/*
 741 * Adapter diagnostic routines
 742 */
 743static bool mgsl_register_test( struct mgsl_struct *info );
 744static bool mgsl_irq_test( struct mgsl_struct *info );
 745static bool mgsl_dma_test( struct mgsl_struct *info );
 746static bool mgsl_memory_test( struct mgsl_struct *info );
 747static int mgsl_adapter_test( struct mgsl_struct *info );
 748
 749/*
 750 * device and resource management routines
 751 */
 752static int mgsl_claim_resources(struct mgsl_struct *info);
 753static void mgsl_release_resources(struct mgsl_struct *info);
 754static void mgsl_add_device(struct mgsl_struct *info);
 755static struct mgsl_struct* mgsl_allocate_device(void);
 756
 757/*
 758 * DMA buffer manupulation functions.
 759 */
 760static void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex );
 761static bool mgsl_get_rx_frame( struct mgsl_struct *info );
 762static bool mgsl_get_raw_rx_frame( struct mgsl_struct *info );
 763static void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info );
 764static void mgsl_reset_tx_dma_buffers( struct mgsl_struct *info );
 765static int num_free_tx_dma_buffers(struct mgsl_struct *info);
 766static void mgsl_load_tx_dma_buffer( struct mgsl_struct *info, const char *Buffer, unsigned int BufferSize);
 767static void mgsl_load_pci_memory(char* TargetPtr, const char* SourcePtr, unsigned short count);
 768
 769/*
 770 * DMA and Shared Memory buffer allocation and formatting
 771 */
 772static int  mgsl_allocate_dma_buffers(struct mgsl_struct *info);
 773static void mgsl_free_dma_buffers(struct mgsl_struct *info);
 774static int  mgsl_alloc_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
 775static void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
 776static int  mgsl_alloc_buffer_list_memory(struct mgsl_struct *info);
 777static void mgsl_free_buffer_list_memory(struct mgsl_struct *info);
 778static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info);
 779static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info);
 780static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info);
 781static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info);
 782static bool load_next_tx_holding_buffer(struct mgsl_struct *info);
 783static int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize);
 784
 785/*
 786 * Bottom half interrupt handlers
 787 */
 788static void mgsl_bh_handler(struct work_struct *work);
 789static void mgsl_bh_receive(struct mgsl_struct *info);
 790static void mgsl_bh_transmit(struct mgsl_struct *info);
 791static void mgsl_bh_status(struct mgsl_struct *info);
 792
 793/*
 794 * Interrupt handler routines and dispatch table.
 795 */
 796static void mgsl_isr_null( struct mgsl_struct *info );
 797static void mgsl_isr_transmit_data( struct mgsl_struct *info );
 798static void mgsl_isr_receive_data( struct mgsl_struct *info );
 799static void mgsl_isr_receive_status( struct mgsl_struct *info );
 800static void mgsl_isr_transmit_status( struct mgsl_struct *info );
 801static void mgsl_isr_io_pin( struct mgsl_struct *info );
 802static void mgsl_isr_misc( struct mgsl_struct *info );
 803static void mgsl_isr_receive_dma( struct mgsl_struct *info );
 804static void mgsl_isr_transmit_dma( struct mgsl_struct *info );
 805
 806typedef void (*isr_dispatch_func)(struct mgsl_struct *);
 807
 808static isr_dispatch_func UscIsrTable[7] =
 809{
 810        mgsl_isr_null,
 811        mgsl_isr_misc,
 812        mgsl_isr_io_pin,
 813        mgsl_isr_transmit_data,
 814        mgsl_isr_transmit_status,
 815        mgsl_isr_receive_data,
 816        mgsl_isr_receive_status
 817};
 818
 819/*
 820 * ioctl call handlers
 821 */
 822static int tiocmget(struct tty_struct *tty);
 823static int tiocmset(struct tty_struct *tty,
 824                    unsigned int set, unsigned int clear);
 825static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount
 826        __user *user_icount);
 827static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS  __user *user_params);
 828static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS  __user *new_params);
 829static int mgsl_get_txidle(struct mgsl_struct * info, int __user *idle_mode);
 830static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode);
 831static int mgsl_txenable(struct mgsl_struct * info, int enable);
 832static int mgsl_txabort(struct mgsl_struct * info);
 833static int mgsl_rxenable(struct mgsl_struct * info, int enable);
 834static int mgsl_wait_event(struct mgsl_struct * info, int __user *mask);
 835static int mgsl_loopmode_send_done( struct mgsl_struct * info );
 836
 837/* set non-zero on successful registration with PCI subsystem */
 838static bool pci_registered;
 839
 840/*
 841 * Global linked list of SyncLink devices
 842 */
 843static struct mgsl_struct *mgsl_device_list;
 844static int mgsl_device_count;
 845
 846/*
 847 * Set this param to non-zero to load eax with the
 848 * .text section address and breakpoint on module load.
 849 * This is useful for use with gdb and add-symbol-file command.
 850 */
 851static bool break_on_load;
 852
 853/*
 854 * Driver major number, defaults to zero to get auto
 855 * assigned major number. May be forced as module parameter.
 856 */
 857static int ttymajor;
 858
 859/*
 860 * Array of user specified options for ISA adapters.
 861 */
 862static int io[MAX_ISA_DEVICES];
 863static int irq[MAX_ISA_DEVICES];
 864static int dma[MAX_ISA_DEVICES];
 865static int debug_level;
 866static int maxframe[MAX_TOTAL_DEVICES];
 867static int txdmabufs[MAX_TOTAL_DEVICES];
 868static int txholdbufs[MAX_TOTAL_DEVICES];
 869        
 870module_param(break_on_load, bool, 0);
 871module_param(ttymajor, int, 0);
 872module_param_array(io, int, NULL, 0);
 873module_param_array(irq, int, NULL, 0);
 874module_param_array(dma, int, NULL, 0);
 875module_param(debug_level, int, 0);
 876module_param_array(maxframe, int, NULL, 0);
 877module_param_array(txdmabufs, int, NULL, 0);
 878module_param_array(txholdbufs, int, NULL, 0);
 879
 880static char *driver_name = "SyncLink serial driver";
 881static char *driver_version = "$Revision: 4.38 $";
 882
 883static int synclink_init_one (struct pci_dev *dev,
 884                                     const struct pci_device_id *ent);
 885static void synclink_remove_one (struct pci_dev *dev);
 886
 887static struct pci_device_id synclink_pci_tbl[] = {
 888        { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_USC, PCI_ANY_ID, PCI_ANY_ID, },
 889        { PCI_VENDOR_ID_MICROGATE, 0x0210, PCI_ANY_ID, PCI_ANY_ID, },
 890        { 0, }, /* terminate list */
 891};
 892MODULE_DEVICE_TABLE(pci, synclink_pci_tbl);
 893
 894MODULE_LICENSE("GPL");
 895
 896static struct pci_driver synclink_pci_driver = {
 897        .name           = "synclink",
 898        .id_table       = synclink_pci_tbl,
 899        .probe          = synclink_init_one,
 900        .remove         = synclink_remove_one,
 901};
 902
 903static struct tty_driver *serial_driver;
 904
 905/* number of characters left in xmit buffer before we ask for more */
 906#define WAKEUP_CHARS 256
 907
 908
 909static void mgsl_change_params(struct mgsl_struct *info);
 910static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout);
 911
 912/*
 913 * 1st function defined in .text section. Calling this function in
 914 * init_module() followed by a breakpoint allows a remote debugger
 915 * (gdb) to get the .text address for the add-symbol-file command.
 916 * This allows remote debugging of dynamically loadable modules.
 917 */
 918static void* mgsl_get_text_ptr(void)
 919{
 920        return mgsl_get_text_ptr;
 921}
 922
 923static inline int mgsl_paranoia_check(struct mgsl_struct *info,
 924                                        char *name, const char *routine)
 925{
 926#ifdef MGSL_PARANOIA_CHECK
 927        static const char *badmagic =
 928                "Warning: bad magic number for mgsl struct (%s) in %s\n";
 929        static const char *badinfo =
 930                "Warning: null mgsl_struct for (%s) in %s\n";
 931
 932        if (!info) {
 933                printk(badinfo, name, routine);
 934                return 1;
 935        }
 936        if (info->magic != MGSL_MAGIC) {
 937                printk(badmagic, name, routine);
 938                return 1;
 939        }
 940#else
 941        if (!info)
 942                return 1;
 943#endif
 944        return 0;
 945}
 946
 947/**
 948 * line discipline callback wrappers
 949 *
 950 * The wrappers maintain line discipline references
 951 * while calling into the line discipline.
 952 *
 953 * ldisc_receive_buf  - pass receive data to line discipline
 954 */
 955
 956static void ldisc_receive_buf(struct tty_struct *tty,
 957                              const __u8 *data, char *flags, int count)
 958{
 959        struct tty_ldisc *ld;
 960        if (!tty)
 961                return;
 962        ld = tty_ldisc_ref(tty);
 963        if (ld) {
 964                if (ld->ops->receive_buf)
 965                        ld->ops->receive_buf(tty, data, flags, count);
 966                tty_ldisc_deref(ld);
 967        }
 968}
 969
 970/* mgsl_stop()          throttle (stop) transmitter
 971 *      
 972 * Arguments:           tty     pointer to tty info structure
 973 * Return Value:        None
 974 */
 975static void mgsl_stop(struct tty_struct *tty)
 976{
 977        struct mgsl_struct *info = tty->driver_data;
 978        unsigned long flags;
 979        
 980        if (mgsl_paranoia_check(info, tty->name, "mgsl_stop"))
 981                return;
 982        
 983        if ( debug_level >= DEBUG_LEVEL_INFO )
 984                printk("mgsl_stop(%s)\n",info->device_name);    
 985                
 986        spin_lock_irqsave(&info->irq_spinlock,flags);
 987        if (info->tx_enabled)
 988                usc_stop_transmitter(info);
 989        spin_unlock_irqrestore(&info->irq_spinlock,flags);
 990        
 991}       /* end of mgsl_stop() */
 992
 993/* mgsl_start()         release (start) transmitter
 994 *      
 995 * Arguments:           tty     pointer to tty info structure
 996 * Return Value:        None
 997 */
 998static void mgsl_start(struct tty_struct *tty)
 999{
1000        struct mgsl_struct *info = tty->driver_data;
1001        unsigned long flags;
1002        
1003        if (mgsl_paranoia_check(info, tty->name, "mgsl_start"))
1004                return;
1005        
1006        if ( debug_level >= DEBUG_LEVEL_INFO )
1007                printk("mgsl_start(%s)\n",info->device_name);   
1008                
1009        spin_lock_irqsave(&info->irq_spinlock,flags);
1010        if (!info->tx_enabled)
1011                usc_start_transmitter(info);
1012        spin_unlock_irqrestore(&info->irq_spinlock,flags);
1013        
1014}       /* end of mgsl_start() */
1015
1016/*
1017 * Bottom half work queue access functions
1018 */
1019
1020/* mgsl_bh_action()     Return next bottom half action to perform.
1021 * Return Value:        BH action code or 0 if nothing to do.
1022 */
1023static int mgsl_bh_action(struct mgsl_struct *info)
1024{
1025        unsigned long flags;
1026        int rc = 0;
1027        
1028        spin_lock_irqsave(&info->irq_spinlock,flags);
1029
1030        if (info->pending_bh & BH_RECEIVE) {
1031                info->pending_bh &= ~BH_RECEIVE;
1032                rc = BH_RECEIVE;
1033        } else if (info->pending_bh & BH_TRANSMIT) {
1034                info->pending_bh &= ~BH_TRANSMIT;
1035                rc = BH_TRANSMIT;
1036        } else if (info->pending_bh & BH_STATUS) {
1037                info->pending_bh &= ~BH_STATUS;
1038                rc = BH_STATUS;
1039        }
1040
1041        if (!rc) {
1042                /* Mark BH routine as complete */
1043                info->bh_running = false;
1044                info->bh_requested = false;
1045        }
1046        
1047        spin_unlock_irqrestore(&info->irq_spinlock,flags);
1048        
1049        return rc;
1050}
1051
1052/*
1053 *      Perform bottom half processing of work items queued by ISR.
1054 */
1055static void mgsl_bh_handler(struct work_struct *work)
1056{
1057        struct mgsl_struct *info =
1058                container_of(work, struct mgsl_struct, task);
1059        int action;
1060
1061        if ( debug_level >= DEBUG_LEVEL_BH )
1062                printk( "%s(%d):mgsl_bh_handler(%s) entry\n",
1063                        __FILE__,__LINE__,info->device_name);
1064        
1065        info->bh_running = true;
1066
1067        while((action = mgsl_bh_action(info)) != 0) {
1068        
1069                /* Process work item */
1070                if ( debug_level >= DEBUG_LEVEL_BH )
1071                        printk( "%s(%d):mgsl_bh_handler() work item action=%d\n",
1072                                __FILE__,__LINE__,action);
1073
1074                switch (action) {
1075                
1076                case BH_RECEIVE:
1077                        mgsl_bh_receive(info);
1078                        break;
1079                case BH_TRANSMIT:
1080                        mgsl_bh_transmit(info);
1081                        break;
1082                case BH_STATUS:
1083                        mgsl_bh_status(info);
1084                        break;
1085                default:
1086                        /* unknown work item ID */
1087                        printk("Unknown work item ID=%08X!\n", action);
1088                        break;
1089                }
1090        }
1091
1092        if ( debug_level >= DEBUG_LEVEL_BH )
1093                printk( "%s(%d):mgsl_bh_handler(%s) exit\n",
1094                        __FILE__,__LINE__,info->device_name);
1095}
1096
1097static void mgsl_bh_receive(struct mgsl_struct *info)
1098{
1099        bool (*get_rx_frame)(struct mgsl_struct *info) =
1100                (info->params.mode == MGSL_MODE_HDLC ? mgsl_get_rx_frame : mgsl_get_raw_rx_frame);
1101
1102        if ( debug_level >= DEBUG_LEVEL_BH )
1103                printk( "%s(%d):mgsl_bh_receive(%s)\n",
1104                        __FILE__,__LINE__,info->device_name);
1105        
1106        do
1107        {
1108                if (info->rx_rcc_underrun) {
1109                        unsigned long flags;
1110                        spin_lock_irqsave(&info->irq_spinlock,flags);
1111                        usc_start_receiver(info);
1112                        spin_unlock_irqrestore(&info->irq_spinlock,flags);
1113                        return;
1114                }
1115        } while(get_rx_frame(info));
1116}
1117
1118static void mgsl_bh_transmit(struct mgsl_struct *info)
1119{
1120        struct tty_struct *tty = info->port.tty;
1121        unsigned long flags;
1122        
1123        if ( debug_level >= DEBUG_LEVEL_BH )
1124                printk( "%s(%d):mgsl_bh_transmit() entry on %s\n",
1125                        __FILE__,__LINE__,info->device_name);
1126
1127        if (tty)
1128                tty_wakeup(tty);
1129
1130        /* if transmitter idle and loopmode_send_done_requested
1131         * then start echoing RxD to TxD
1132         */
1133        spin_lock_irqsave(&info->irq_spinlock,flags);
1134        if ( !info->tx_active && info->loopmode_send_done_requested )
1135                usc_loopmode_send_done( info );
1136        spin_unlock_irqrestore(&info->irq_spinlock,flags);
1137}
1138
1139static void mgsl_bh_status(struct mgsl_struct *info)
1140{
1141        if ( debug_level >= DEBUG_LEVEL_BH )
1142                printk( "%s(%d):mgsl_bh_status() entry on %s\n",
1143                        __FILE__,__LINE__,info->device_name);
1144
1145        info->ri_chkcount = 0;
1146        info->dsr_chkcount = 0;
1147        info->dcd_chkcount = 0;
1148        info->cts_chkcount = 0;
1149}
1150
1151/* mgsl_isr_receive_status()
1152 * 
1153 *      Service a receive status interrupt. The type of status
1154 *      interrupt is indicated by the state of the RCSR.
1155 *      This is only used for HDLC mode.
1156 *
1157 * Arguments:           info    pointer to device instance data
1158 * Return Value:        None
1159 */
1160static void mgsl_isr_receive_status( struct mgsl_struct *info )
1161{
1162        u16 status = usc_InReg( info, RCSR );
1163
1164        if ( debug_level >= DEBUG_LEVEL_ISR )
1165                printk("%s(%d):mgsl_isr_receive_status status=%04X\n",
1166                        __FILE__,__LINE__,status);
1167                        
1168        if ( (status & RXSTATUS_ABORT_RECEIVED) && 
1169                info->loopmode_insert_requested &&
1170                usc_loopmode_active(info) )
1171        {
1172                ++info->icount.rxabort;
1173                info->loopmode_insert_requested = false;
1174 
1175                /* clear CMR:13 to start echoing RxD to TxD */
1176                info->cmr_value &= ~BIT13;
1177                usc_OutReg(info, CMR, info->cmr_value);
1178 
1179                /* disable received abort irq (no longer required) */
1180                usc_OutReg(info, RICR,
1181                        (usc_InReg(info, RICR) & ~RXSTATUS_ABORT_RECEIVED));
1182        }
1183
1184        if (status & (RXSTATUS_EXITED_HUNT | RXSTATUS_IDLE_RECEIVED)) {
1185                if (status & RXSTATUS_EXITED_HUNT)
1186                        info->icount.exithunt++;
1187                if (status & RXSTATUS_IDLE_RECEIVED)
1188                        info->icount.rxidle++;
1189                wake_up_interruptible(&info->event_wait_q);
1190        }
1191
1192        if (status & RXSTATUS_OVERRUN){
1193                info->icount.rxover++;
1194                usc_process_rxoverrun_sync( info );
1195        }
1196
1197        usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
1198        usc_UnlatchRxstatusBits( info, status );
1199
1200}       /* end of mgsl_isr_receive_status() */
1201
1202/* mgsl_isr_transmit_status()
1203 * 
1204 *      Service a transmit status interrupt
1205 *      HDLC mode :end of transmit frame
1206 *      Async mode:all data is sent
1207 *      transmit status is indicated by bits in the TCSR.
1208 * 
1209 * Arguments:           info           pointer to device instance data
1210 * Return Value:        None
1211 */
1212static void mgsl_isr_transmit_status( struct mgsl_struct *info )
1213{
1214        u16 status = usc_InReg( info, TCSR );
1215
1216        if ( debug_level >= DEBUG_LEVEL_ISR )   
1217                printk("%s(%d):mgsl_isr_transmit_status status=%04X\n",
1218                        __FILE__,__LINE__,status);
1219        
1220        usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
1221        usc_UnlatchTxstatusBits( info, status );
1222        
1223        if ( status & (TXSTATUS_UNDERRUN | TXSTATUS_ABORT_SENT) )
1224        {
1225                /* finished sending HDLC abort. This may leave  */
1226                /* the TxFifo with data from the aborted frame  */
1227                /* so purge the TxFifo. Also shutdown the DMA   */
1228                /* channel in case there is data remaining in   */
1229                /* the DMA buffer                               */
1230                usc_DmaCmd( info, DmaCmd_ResetTxChannel );
1231                usc_RTCmd( info, RTCmd_PurgeTxFifo );
1232        }
1233 
1234        if ( status & TXSTATUS_EOF_SENT )
1235                info->icount.txok++;
1236        else if ( status & TXSTATUS_UNDERRUN )
1237                info->icount.txunder++;
1238        else if ( status & TXSTATUS_ABORT_SENT )
1239                info->icount.txabort++;
1240        else
1241                info->icount.txunder++;
1242                        
1243        info->tx_active = false;
1244        info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1245        del_timer(&info->tx_timer);     
1246        
1247        if ( info->drop_rts_on_tx_done ) {
1248                usc_get_serial_signals( info );
1249                if ( info->serial_signals & SerialSignal_RTS ) {
1250                        info->serial_signals &= ~SerialSignal_RTS;
1251                        usc_set_serial_signals( info );
1252                }
1253                info->drop_rts_on_tx_done = false;
1254        }
1255
1256#if SYNCLINK_GENERIC_HDLC
1257        if (info->netcount)
1258                hdlcdev_tx_done(info);
1259        else 
1260#endif
1261        {
1262                if (info->port.tty->stopped || info->port.tty->hw_stopped) {
1263                        usc_stop_transmitter(info);
1264                        return;
1265                }
1266                info->pending_bh |= BH_TRANSMIT;
1267        }
1268
1269}       /* end of mgsl_isr_transmit_status() */
1270
1271/* mgsl_isr_io_pin()
1272 * 
1273 *      Service an Input/Output pin interrupt. The type of
1274 *      interrupt is indicated by bits in the MISR
1275 *      
1276 * Arguments:           info           pointer to device instance data
1277 * Return Value:        None
1278 */
1279static void mgsl_isr_io_pin( struct mgsl_struct *info )
1280{
1281        struct  mgsl_icount *icount;
1282        u16 status = usc_InReg( info, MISR );
1283
1284        if ( debug_level >= DEBUG_LEVEL_ISR )   
1285                printk("%s(%d):mgsl_isr_io_pin status=%04X\n",
1286                        __FILE__,__LINE__,status);
1287                        
1288        usc_ClearIrqPendingBits( info, IO_PIN );
1289        usc_UnlatchIostatusBits( info, status );
1290
1291        if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
1292                      MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
1293                icount = &info->icount;
1294                /* update input line counters */
1295                if (status & MISCSTATUS_RI_LATCHED) {
1296                        if ((info->ri_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1297                                usc_DisablestatusIrqs(info,SICR_RI);
1298                        icount->rng++;
1299                        if ( status & MISCSTATUS_RI )
1300                                info->input_signal_events.ri_up++;      
1301                        else
1302                                info->input_signal_events.ri_down++;    
1303                }
1304                if (status & MISCSTATUS_DSR_LATCHED) {
1305                        if ((info->dsr_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1306                                usc_DisablestatusIrqs(info,SICR_DSR);
1307                        icount->dsr++;
1308                        if ( status & MISCSTATUS_DSR )
1309                                info->input_signal_events.dsr_up++;
1310                        else
1311                                info->input_signal_events.dsr_down++;
1312                }
1313                if (status & MISCSTATUS_DCD_LATCHED) {
1314                        if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1315                                usc_DisablestatusIrqs(info,SICR_DCD);
1316                        icount->dcd++;
1317                        if (status & MISCSTATUS_DCD) {
1318                                info->input_signal_events.dcd_up++;
1319                        } else
1320                                info->input_signal_events.dcd_down++;
1321#if SYNCLINK_GENERIC_HDLC
1322                        if (info->netcount) {
1323                                if (status & MISCSTATUS_DCD)
1324                                        netif_carrier_on(info->netdev);
1325                                else
1326                                        netif_carrier_off(info->netdev);
1327                        }
1328#endif
1329                }
1330                if (status & MISCSTATUS_CTS_LATCHED)
1331                {
1332                        if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1333                                usc_DisablestatusIrqs(info,SICR_CTS);
1334                        icount->cts++;
1335                        if ( status & MISCSTATUS_CTS )
1336                                info->input_signal_events.cts_up++;
1337                        else
1338                                info->input_signal_events.cts_down++;
1339                }
1340                wake_up_interruptible(&info->status_event_wait_q);
1341                wake_up_interruptible(&info->event_wait_q);
1342
1343                if (tty_port_check_carrier(&info->port) &&
1344                     (status & MISCSTATUS_DCD_LATCHED) ) {
1345                        if ( debug_level >= DEBUG_LEVEL_ISR )
1346                                printk("%s CD now %s...", info->device_name,
1347                                       (status & MISCSTATUS_DCD) ? "on" : "off");
1348                        if (status & MISCSTATUS_DCD)
1349                                wake_up_interruptible(&info->port.open_wait);
1350                        else {
1351                                if ( debug_level >= DEBUG_LEVEL_ISR )
1352                                        printk("doing serial hangup...");
1353                                if (info->port.tty)
1354                                        tty_hangup(info->port.tty);
1355                        }
1356                }
1357        
1358                if (tty_port_cts_enabled(&info->port) &&
1359                     (status & MISCSTATUS_CTS_LATCHED) ) {
1360                        if (info->port.tty->hw_stopped) {
1361                                if (status & MISCSTATUS_CTS) {
1362                                        if ( debug_level >= DEBUG_LEVEL_ISR )
1363                                                printk("CTS tx start...");
1364                                        info->port.tty->hw_stopped = 0;
1365                                        usc_start_transmitter(info);
1366                                        info->pending_bh |= BH_TRANSMIT;
1367                                        return;
1368                                }
1369                        } else {
1370                                if (!(status & MISCSTATUS_CTS)) {
1371                                        if ( debug_level >= DEBUG_LEVEL_ISR )
1372                                                printk("CTS tx stop...");
1373                                        if (info->port.tty)
1374                                                info->port.tty->hw_stopped = 1;
1375                                        usc_stop_transmitter(info);
1376                                }
1377                        }
1378                }
1379        }
1380
1381        info->pending_bh |= BH_STATUS;
1382        
1383        /* for diagnostics set IRQ flag */
1384        if ( status & MISCSTATUS_TXC_LATCHED ){
1385                usc_OutReg( info, SICR,
1386                        (unsigned short)(usc_InReg(info,SICR) & ~(SICR_TXC_ACTIVE+SICR_TXC_INACTIVE)) );
1387                usc_UnlatchIostatusBits( info, MISCSTATUS_TXC_LATCHED );
1388                info->irq_occurred = true;
1389        }
1390
1391}       /* end of mgsl_isr_io_pin() */
1392
1393/* mgsl_isr_transmit_data()
1394 * 
1395 *      Service a transmit data interrupt (async mode only).
1396 * 
1397 * Arguments:           info    pointer to device instance data
1398 * Return Value:        None
1399 */
1400static void mgsl_isr_transmit_data( struct mgsl_struct *info )
1401{
1402        if ( debug_level >= DEBUG_LEVEL_ISR )   
1403                printk("%s(%d):mgsl_isr_transmit_data xmit_cnt=%d\n",
1404                        __FILE__,__LINE__,info->xmit_cnt);
1405                        
1406        usc_ClearIrqPendingBits( info, TRANSMIT_DATA );
1407        
1408        if (info->port.tty->stopped || info->port.tty->hw_stopped) {
1409                usc_stop_transmitter(info);
1410                return;
1411        }
1412        
1413        if ( info->xmit_cnt )
1414                usc_load_txfifo( info );
1415        else
1416                info->tx_active = false;
1417                
1418        if (info->xmit_cnt < WAKEUP_CHARS)
1419                info->pending_bh |= BH_TRANSMIT;
1420
1421}       /* end of mgsl_isr_transmit_data() */
1422
1423/* mgsl_isr_receive_data()
1424 * 
1425 *      Service a receive data interrupt. This occurs
1426 *      when operating in asynchronous interrupt transfer mode.
1427 *      The receive data FIFO is flushed to the receive data buffers. 
1428 * 
1429 * Arguments:           info            pointer to device instance data
1430 * Return Value:        None
1431 */
1432static void mgsl_isr_receive_data( struct mgsl_struct *info )
1433{
1434        int Fifocount;
1435        u16 status;
1436        int work = 0;
1437        unsigned char DataByte;
1438        struct  mgsl_icount *icount = &info->icount;
1439        
1440        if ( debug_level >= DEBUG_LEVEL_ISR )   
1441                printk("%s(%d):mgsl_isr_receive_data\n",
1442                        __FILE__,__LINE__);
1443
1444        usc_ClearIrqPendingBits( info, RECEIVE_DATA );
1445        
1446        /* select FIFO status for RICR readback */
1447        usc_RCmd( info, RCmd_SelectRicrRxFifostatus );
1448
1449        /* clear the Wordstatus bit so that status readback */
1450        /* only reflects the status of this byte */
1451        usc_OutReg( info, RICR+LSBONLY, (u16)(usc_InReg(info, RICR+LSBONLY) & ~BIT3 ));
1452
1453        /* flush the receive FIFO */
1454
1455        while( (Fifocount = (usc_InReg(info,RICR) >> 8)) ) {
1456                int flag;
1457
1458                /* read one byte from RxFIFO */
1459                outw( (inw(info->io_base + CCAR) & 0x0780) | (RDR+LSBONLY),
1460                      info->io_base + CCAR );
1461                DataByte = inb( info->io_base + CCAR );
1462
1463                /* get the status of the received byte */
1464                status = usc_InReg(info, RCSR);
1465                if ( status & (RXSTATUS_FRAMING_ERROR | RXSTATUS_PARITY_ERROR |
1466                                RXSTATUS_OVERRUN | RXSTATUS_BREAK_RECEIVED) )
1467                        usc_UnlatchRxstatusBits(info,RXSTATUS_ALL);
1468                
1469                icount->rx++;
1470                
1471                flag = 0;
1472                if ( status & (RXSTATUS_FRAMING_ERROR | RXSTATUS_PARITY_ERROR |
1473                                RXSTATUS_OVERRUN | RXSTATUS_BREAK_RECEIVED) ) {
1474                        printk("rxerr=%04X\n",status);
1475                        /* update error statistics */
1476                        if ( status & RXSTATUS_BREAK_RECEIVED ) {
1477                                status &= ~(RXSTATUS_FRAMING_ERROR | RXSTATUS_PARITY_ERROR);
1478                                icount->brk++;
1479                        } else if (status & RXSTATUS_PARITY_ERROR)
1480                                icount->parity++;
1481                        else if (status & RXSTATUS_FRAMING_ERROR)
1482                                icount->frame++;
1483                        else if (status & RXSTATUS_OVERRUN) {
1484                                /* must issue purge fifo cmd before */
1485                                /* 16C32 accepts more receive chars */
1486                                usc_RTCmd(info,RTCmd_PurgeRxFifo);
1487                                icount->overrun++;
1488                        }
1489
1490                        /* discard char if tty control flags say so */
1491                        if (status & info->ignore_status_mask)
1492                                continue;
1493                                
1494                        status &= info->read_status_mask;
1495                
1496                        if (status & RXSTATUS_BREAK_RECEIVED) {
1497                                flag = TTY_BREAK;
1498                                if (info->port.flags & ASYNC_SAK)
1499                                        do_SAK(info->port.tty);
1500                        } else if (status & RXSTATUS_PARITY_ERROR)
1501                                flag = TTY_PARITY;
1502                        else if (status & RXSTATUS_FRAMING_ERROR)
1503                                flag = TTY_FRAME;
1504                }       /* end of if (error) */
1505                tty_insert_flip_char(&info->port, DataByte, flag);
1506                if (status & RXSTATUS_OVERRUN) {
1507                        /* Overrun is special, since it's
1508                         * reported immediately, and doesn't
1509                         * affect the current character
1510                         */
1511                        work += tty_insert_flip_char(&info->port, 0, TTY_OVERRUN);
1512                }
1513        }
1514
1515        if ( debug_level >= DEBUG_LEVEL_ISR ) {
1516                printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
1517                        __FILE__,__LINE__,icount->rx,icount->brk,
1518                        icount->parity,icount->frame,icount->overrun);
1519        }
1520                        
1521        if(work)
1522                tty_flip_buffer_push(&info->port);
1523}
1524
1525/* mgsl_isr_misc()
1526 * 
1527 *      Service a miscellaneous interrupt source.
1528 *      
1529 * Arguments:           info            pointer to device extension (instance data)
1530 * Return Value:        None
1531 */
1532static void mgsl_isr_misc( struct mgsl_struct *info )
1533{
1534        u16 status = usc_InReg( info, MISR );
1535
1536        if ( debug_level >= DEBUG_LEVEL_ISR )   
1537                printk("%s(%d):mgsl_isr_misc status=%04X\n",
1538                        __FILE__,__LINE__,status);
1539                        
1540        if ((status & MISCSTATUS_RCC_UNDERRUN) &&
1541            (info->params.mode == MGSL_MODE_HDLC)) {
1542
1543                /* turn off receiver and rx DMA */
1544                usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
1545                usc_DmaCmd(info, DmaCmd_ResetRxChannel);
1546                usc_UnlatchRxstatusBits(info, RXSTATUS_ALL);
1547                usc_ClearIrqPendingBits(info, RECEIVE_DATA | RECEIVE_STATUS);
1548                usc_DisableInterrupts(info, RECEIVE_DATA | RECEIVE_STATUS);
1549
1550                /* schedule BH handler to restart receiver */
1551                info->pending_bh |= BH_RECEIVE;
1552                info->rx_rcc_underrun = true;
1553        }
1554
1555        usc_ClearIrqPendingBits( info, MISC );
1556        usc_UnlatchMiscstatusBits( info, status );
1557
1558}       /* end of mgsl_isr_misc() */
1559
1560/* mgsl_isr_null()
1561 *
1562 *      Services undefined interrupt vectors from the
1563 *      USC. (hence this function SHOULD never be called)
1564 * 
1565 * Arguments:           info            pointer to device extension (instance data)
1566 * Return Value:        None
1567 */
1568static void mgsl_isr_null( struct mgsl_struct *info )
1569{
1570
1571}       /* end of mgsl_isr_null() */
1572
1573/* mgsl_isr_receive_dma()
1574 * 
1575 *      Service a receive DMA channel interrupt.
1576 *      For this driver there are two sources of receive DMA interrupts
1577 *      as identified in the Receive DMA mode Register (RDMR):
1578 * 
1579 *      BIT3    EOA/EOL         End of List, all receive buffers in receive
1580 *                              buffer list have been filled (no more free buffers
1581 *                              available). The DMA controller has shut down.
1582 * 
1583 *      BIT2    EOB             End of Buffer. This interrupt occurs when a receive
1584 *                              DMA buffer is terminated in response to completion
1585 *                              of a good frame or a frame with errors. The status
1586 *                              of the frame is stored in the buffer entry in the
1587 *                              list of receive buffer entries.
1588 * 
1589 * Arguments:           info            pointer to device instance data
1590 * Return Value:        None
1591 */
1592static void mgsl_isr_receive_dma( struct mgsl_struct *info )
1593{
1594        u16 status;
1595        
1596        /* clear interrupt pending and IUS bit for Rx DMA IRQ */
1597        usc_OutDmaReg( info, CDIR, BIT9 | BIT1 );
1598
1599        /* Read the receive DMA status to identify interrupt type. */
1600        /* This also clears the status bits. */
1601        status = usc_InDmaReg( info, RDMR );
1602
1603        if ( debug_level >= DEBUG_LEVEL_ISR )   
1604                printk("%s(%d):mgsl_isr_receive_dma(%s) status=%04X\n",
1605                        __FILE__,__LINE__,info->device_name,status);
1606                        
1607        info->pending_bh |= BH_RECEIVE;
1608        
1609        if ( status & BIT3 ) {
1610                info->rx_overflow = true;
1611                info->icount.buf_overrun++;
1612        }
1613
1614}       /* end of mgsl_isr_receive_dma() */
1615
1616/* mgsl_isr_transmit_dma()
1617 *
1618 *      This function services a transmit DMA channel interrupt.
1619 *
1620 *      For this driver there is one source of transmit DMA interrupts
1621 *      as identified in the Transmit DMA Mode Register (TDMR):
1622 *
1623 *      BIT2  EOB       End of Buffer. This interrupt occurs when a
1624 *                      transmit DMA buffer has been emptied.
1625 *
1626 *      The driver maintains enough transmit DMA buffers to hold at least
1627 *      one max frame size transmit frame. When operating in a buffered
1628 *      transmit mode, there may be enough transmit DMA buffers to hold at
1629 *      least two or more max frame size frames. On an EOB condition,
1630 *      determine if there are any queued transmit buffers and copy into
1631 *      transmit DMA buffers if we have room.
1632 *
1633 * Arguments:           info            pointer to device instance data
1634 * Return Value:        None
1635 */
1636static void mgsl_isr_transmit_dma( struct mgsl_struct *info )
1637{
1638        u16 status;
1639
1640        /* clear interrupt pending and IUS bit for Tx DMA IRQ */
1641        usc_OutDmaReg(info, CDIR, BIT8 | BIT0 );
1642
1643        /* Read the transmit DMA status to identify interrupt type. */
1644        /* This also clears the status bits. */
1645
1646        status = usc_InDmaReg( info, TDMR );
1647
1648        if ( debug_level >= DEBUG_LEVEL_ISR )
1649                printk("%s(%d):mgsl_isr_transmit_dma(%s) status=%04X\n",
1650                        __FILE__,__LINE__,info->device_name,status);
1651
1652        if ( status & BIT2 ) {
1653                --info->tx_dma_buffers_used;
1654
1655                /* if there are transmit frames queued,
1656                 *  try to load the next one
1657                 */
1658                if ( load_next_tx_holding_buffer(info) ) {
1659                        /* if call returns non-zero value, we have
1660                         * at least one free tx holding buffer
1661                         */
1662                        info->pending_bh |= BH_TRANSMIT;
1663                }
1664        }
1665
1666}       /* end of mgsl_isr_transmit_dma() */
1667
1668/* mgsl_interrupt()
1669 * 
1670 *      Interrupt service routine entry point.
1671 *      
1672 * Arguments:
1673 * 
1674 *      irq             interrupt number that caused interrupt
1675 *      dev_id          device ID supplied during interrupt registration
1676 *      
1677 * Return Value: None
1678 */
1679static irqreturn_t mgsl_interrupt(int dummy, void *dev_id)
1680{
1681        struct mgsl_struct *info = dev_id;
1682        u16 UscVector;
1683        u16 DmaVector;
1684
1685        if ( debug_level >= DEBUG_LEVEL_ISR )   
1686                printk(KERN_DEBUG "%s(%d):mgsl_interrupt(%d)entry.\n",
1687                        __FILE__, __LINE__, info->irq_level);
1688
1689        spin_lock(&info->irq_spinlock);
1690
1691        for(;;) {
1692                /* Read the interrupt vectors from hardware. */
1693                UscVector = usc_InReg(info, IVR) >> 9;
1694                DmaVector = usc_InDmaReg(info, DIVR);
1695                
1696                if ( debug_level >= DEBUG_LEVEL_ISR )   
1697                        printk("%s(%d):%s UscVector=%08X DmaVector=%08X\n",
1698                                __FILE__,__LINE__,info->device_name,UscVector,DmaVector);
1699                        
1700                if ( !UscVector && !DmaVector )
1701                        break;
1702                        
1703                /* Dispatch interrupt vector */
1704                if ( UscVector )
1705                        (*UscIsrTable[UscVector])(info);
1706                else if ( (DmaVector&(BIT10|BIT9)) == BIT10)
1707                        mgsl_isr_transmit_dma(info);
1708                else
1709                        mgsl_isr_receive_dma(info);
1710
1711                if ( info->isr_overflow ) {
1712                        printk(KERN_ERR "%s(%d):%s isr overflow irq=%d\n",
1713                                __FILE__, __LINE__, info->device_name, info->irq_level);
1714                        usc_DisableMasterIrqBit(info);
1715                        usc_DisableDmaInterrupts(info,DICR_MASTER);
1716                        break;
1717                }
1718        }
1719        
1720        /* Request bottom half processing if there's something 
1721         * for it to do and the bh is not already running
1722         */
1723
1724        if ( info->pending_bh && !info->bh_running && !info->bh_requested ) {
1725                if ( debug_level >= DEBUG_LEVEL_ISR )   
1726                        printk("%s(%d):%s queueing bh task.\n",
1727                                __FILE__,__LINE__,info->device_name);
1728                schedule_work(&info->task);
1729                info->bh_requested = true;
1730        }
1731
1732        spin_unlock(&info->irq_spinlock);
1733        
1734        if ( debug_level >= DEBUG_LEVEL_ISR )   
1735                printk(KERN_DEBUG "%s(%d):mgsl_interrupt(%d)exit.\n",
1736                        __FILE__, __LINE__, info->irq_level);
1737
1738        return IRQ_HANDLED;
1739}       /* end of mgsl_interrupt() */
1740
1741/* startup()
1742 * 
1743 *      Initialize and start device.
1744 *      
1745 * Arguments:           info    pointer to device instance data
1746 * Return Value:        0 if success, otherwise error code
1747 */
1748static int startup(struct mgsl_struct * info)
1749{
1750        int retval = 0;
1751
1752        if ( debug_level >= DEBUG_LEVEL_INFO )
1753                printk("%s(%d):mgsl_startup(%s)\n",__FILE__,__LINE__,info->device_name);
1754
1755        if (tty_port_initialized(&info->port))
1756                return 0;
1757
1758        if (!info->xmit_buf) {
1759                /* allocate a page of memory for a transmit buffer */
1760                info->xmit_buf = (unsigned char *)get_zeroed_page(GFP_KERNEL);
1761                if (!info->xmit_buf) {
1762                        printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
1763                                __FILE__,__LINE__,info->device_name);
1764                        return -ENOMEM;
1765                }
1766        }
1767
1768        info->pending_bh = 0;
1769        
1770        memset(&info->icount, 0, sizeof(info->icount));
1771
1772        setup_timer(&info->tx_timer, mgsl_tx_timeout, (unsigned long)info);
1773        
1774        /* Allocate and claim adapter resources */
1775        retval = mgsl_claim_resources(info);
1776        
1777        /* perform existence check and diagnostics */
1778        if ( !retval )
1779                retval = mgsl_adapter_test(info);
1780                
1781        if ( retval ) {
1782                if (capable(CAP_SYS_ADMIN) && info->port.tty)
1783                        set_bit(TTY_IO_ERROR, &info->port.tty->flags);
1784                mgsl_release_resources(info);
1785                return retval;
1786        }
1787
1788        /* program hardware for current parameters */
1789        mgsl_change_params(info);
1790
1791        if (info->port.tty)
1792                clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
1793
1794        tty_port_set_initialized(&info->port, 1);
1795
1796        return 0;
1797}       /* end of startup() */
1798
1799/* shutdown()
1800 *
1801 * Called by mgsl_close() and mgsl_hangup() to shutdown hardware
1802 *
1803 * Arguments:           info    pointer to device instance data
1804 * Return Value:        None
1805 */
1806static void shutdown(struct mgsl_struct * info)
1807{
1808        unsigned long flags;
1809
1810        if (!tty_port_initialized(&info->port))
1811                return;
1812
1813        if (debug_level >= DEBUG_LEVEL_INFO)
1814                printk("%s(%d):mgsl_shutdown(%s)\n",
1815                         __FILE__,__LINE__, info->device_name );
1816
1817        /* clear status wait queue because status changes */
1818        /* can't happen after shutting down the hardware */
1819        wake_up_interruptible(&info->status_event_wait_q);
1820        wake_up_interruptible(&info->event_wait_q);
1821
1822        del_timer_sync(&info->tx_timer);
1823
1824        if (info->xmit_buf) {
1825                free_page((unsigned long) info->xmit_buf);
1826                info->xmit_buf = NULL;
1827        }
1828
1829        spin_lock_irqsave(&info->irq_spinlock,flags);
1830        usc_DisableMasterIrqBit(info);
1831        usc_stop_receiver(info);
1832        usc_stop_transmitter(info);
1833        usc_DisableInterrupts(info,RECEIVE_DATA | RECEIVE_STATUS |
1834                TRANSMIT_DATA | TRANSMIT_STATUS | IO_PIN | MISC );
1835        usc_DisableDmaInterrupts(info,DICR_MASTER + DICR_TRANSMIT + DICR_RECEIVE);
1836
1837        /* Disable DMAEN (Port 7, Bit 14) */
1838        /* This disconnects the DMA request signal from the ISA bus */
1839        /* on the ISA adapter. This has no effect for the PCI adapter */
1840        usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) | BIT14));
1841
1842        /* Disable INTEN (Port 6, Bit12) */
1843        /* This disconnects the IRQ request signal to the ISA bus */
1844        /* on the ISA adapter. This has no effect for the PCI adapter */
1845        usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) | BIT12));
1846
1847        if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
1848                info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
1849                usc_set_serial_signals(info);
1850        }
1851
1852        spin_unlock_irqrestore(&info->irq_spinlock,flags);
1853
1854        mgsl_release_resources(info);
1855
1856        if (info->port.tty)
1857                set_bit(TTY_IO_ERROR, &info->port.tty->flags);
1858
1859        tty_port_set_initialized(&info->port, 0);
1860}       /* end of shutdown() */
1861
1862static void mgsl_program_hw(struct mgsl_struct *info)
1863{
1864        unsigned long flags;
1865
1866        spin_lock_irqsave(&info->irq_spinlock,flags);
1867        
1868        usc_stop_receiver(info);
1869        usc_stop_transmitter(info);
1870        info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1871        
1872        if (info->params.mode == MGSL_MODE_HDLC ||
1873            info->params.mode == MGSL_MODE_RAW ||
1874            info->netcount)
1875                usc_set_sync_mode(info);
1876        else
1877                usc_set_async_mode(info);
1878                
1879        usc_set_serial_signals(info);
1880        
1881        info->dcd_chkcount = 0;
1882        info->cts_chkcount = 0;
1883        info->ri_chkcount = 0;
1884        info->dsr_chkcount = 0;
1885
1886        usc_EnableStatusIrqs(info,SICR_CTS+SICR_DSR+SICR_DCD+SICR_RI);
1887        usc_EnableInterrupts(info, IO_PIN);
1888        usc_get_serial_signals(info);
1889                
1890        if (info->netcount || info->port.tty->termios.c_cflag & CREAD)
1891                usc_start_receiver(info);
1892                
1893        spin_unlock_irqrestore(&info->irq_spinlock,flags);
1894}
1895
1896/* Reconfigure adapter based on new parameters
1897 */
1898static void mgsl_change_params(struct mgsl_struct *info)
1899{
1900        unsigned cflag;
1901        int bits_per_char;
1902
1903        if (!info->port.tty)
1904                return;
1905                
1906        if (debug_level >= DEBUG_LEVEL_INFO)
1907                printk("%s(%d):mgsl_change_params(%s)\n",
1908                         __FILE__,__LINE__, info->device_name );
1909                         
1910        cflag = info->port.tty->termios.c_cflag;
1911
1912        /* if B0 rate (hangup) specified then negate RTS and DTR */
1913        /* otherwise assert RTS and DTR */
1914        if (cflag & CBAUD)
1915                info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
1916        else
1917                info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
1918        
1919        /* byte size and parity */
1920        
1921        switch (cflag & CSIZE) {
1922              case CS5: info->params.data_bits = 5; break;
1923              case CS6: info->params.data_bits = 6; break;
1924              case CS7: info->params.data_bits = 7; break;
1925              case CS8: info->params.data_bits = 8; break;
1926              /* Never happens, but GCC is too dumb to figure it out */
1927              default:  info->params.data_bits = 7; break;
1928              }
1929              
1930        if (cflag & CSTOPB)
1931                info->params.stop_bits = 2;
1932        else
1933                info->params.stop_bits = 1;
1934
1935        info->params.parity = ASYNC_PARITY_NONE;
1936        if (cflag & PARENB) {
1937                if (cflag & PARODD)
1938                        info->params.parity = ASYNC_PARITY_ODD;
1939                else
1940                        info->params.parity = ASYNC_PARITY_EVEN;
1941#ifdef CMSPAR
1942                if (cflag & CMSPAR)
1943                        info->params.parity = ASYNC_PARITY_SPACE;
1944#endif
1945        }
1946
1947        /* calculate number of jiffies to transmit a full
1948         * FIFO (32 bytes) at specified data rate
1949         */
1950        bits_per_char = info->params.data_bits + 
1951                        info->params.stop_bits + 1;
1952
1953        /* if port data rate is set to 460800 or less then
1954         * allow tty settings to override, otherwise keep the
1955         * current data rate.
1956         */
1957        if (info->params.data_rate <= 460800)
1958                info->params.data_rate = tty_get_baud_rate(info->port.tty);
1959        
1960        if ( info->params.data_rate ) {
1961                info->timeout = (32*HZ*bits_per_char) / 
1962                                info->params.data_rate;
1963        }
1964        info->timeout += HZ/50;         /* Add .02 seconds of slop */
1965
1966        tty_port_set_cts_flow(&info->port, cflag & CRTSCTS);
1967        tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL);
1968
1969        /* process tty input control flags */
1970        
1971        info->read_status_mask = RXSTATUS_OVERRUN;
1972        if (I_INPCK(info->port.tty))
1973                info->read_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR;
1974        if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
1975                info->read_status_mask |= RXSTATUS_BREAK_RECEIVED;
1976        
1977        if (I_IGNPAR(info->port.tty))
1978                info->ignore_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR;
1979        if (I_IGNBRK(info->port.tty)) {
1980                info->ignore_status_mask |= RXSTATUS_BREAK_RECEIVED;
1981                /* If ignoring parity and break indicators, ignore 
1982                 * overruns too.  (For real raw support).
1983                 */
1984                if (I_IGNPAR(info->port.tty))
1985                        info->ignore_status_mask |= RXSTATUS_OVERRUN;
1986        }
1987
1988        mgsl_program_hw(info);
1989
1990}       /* end of mgsl_change_params() */
1991
1992/* mgsl_put_char()
1993 * 
1994 *      Add a character to the transmit buffer.
1995 *      
1996 * Arguments:           tty     pointer to tty information structure
1997 *                      ch      character to add to transmit buffer
1998 *              
1999 * Return Value:        None
2000 */
2001static int mgsl_put_char(struct tty_struct *tty, unsigned char ch)
2002{
2003        struct mgsl_struct *info = tty->driver_data;
2004        unsigned long flags;
2005        int ret = 0;
2006
2007        if (debug_level >= DEBUG_LEVEL_INFO) {
2008                printk(KERN_DEBUG "%s(%d):mgsl_put_char(%d) on %s\n",
2009                        __FILE__, __LINE__, ch, info->device_name);
2010        }               
2011        
2012        if (mgsl_paranoia_check(info, tty->name, "mgsl_put_char"))
2013                return 0;
2014
2015        if (!info->xmit_buf)
2016                return 0;
2017
2018        spin_lock_irqsave(&info->irq_spinlock, flags);
2019        
2020        if ((info->params.mode == MGSL_MODE_ASYNC ) || !info->tx_active) {
2021                if (info->xmit_cnt < SERIAL_XMIT_SIZE - 1) {
2022                        info->xmit_buf[info->xmit_head++] = ch;
2023                        info->xmit_head &= SERIAL_XMIT_SIZE-1;
2024                        info->xmit_cnt++;
2025                        ret = 1;
2026                }
2027        }
2028        spin_unlock_irqrestore(&info->irq_spinlock, flags);
2029        return ret;
2030        
2031}       /* end of mgsl_put_char() */
2032
2033/* mgsl_flush_chars()
2034 * 
2035 *      Enable transmitter so remaining characters in the
2036 *      transmit buffer are sent.
2037 *      
2038 * Arguments:           tty     pointer to tty information structure
2039 * Return Value:        None
2040 */
2041static void mgsl_flush_chars(struct tty_struct *tty)
2042{
2043        struct mgsl_struct *info = tty->driver_data;
2044        unsigned long flags;
2045                                
2046        if ( debug_level >= DEBUG_LEVEL_INFO )
2047                printk( "%s(%d):mgsl_flush_chars() entry on %s xmit_cnt=%d\n",
2048                        __FILE__,__LINE__,info->device_name,info->xmit_cnt);
2049        
2050        if (mgsl_paranoia_check(info, tty->name, "mgsl_flush_chars"))
2051                return;
2052
2053        if (info->xmit_cnt <= 0 || tty->stopped || tty->hw_stopped ||
2054            !info->xmit_buf)
2055                return;
2056
2057        if ( debug_level >= DEBUG_LEVEL_INFO )
2058                printk( "%s(%d):mgsl_flush_chars() entry on %s starting transmitter\n",
2059                        __FILE__,__LINE__,info->device_name );
2060
2061        spin_lock_irqsave(&info->irq_spinlock,flags);
2062        
2063        if (!info->tx_active) {
2064                if ( (info->params.mode == MGSL_MODE_HDLC ||
2065                        info->params.mode == MGSL_MODE_RAW) && info->xmit_cnt ) {
2066                        /* operating in synchronous (frame oriented) mode */
2067                        /* copy data from circular xmit_buf to */
2068                        /* transmit DMA buffer. */
2069                        mgsl_load_tx_dma_buffer(info,
2070                                 info->xmit_buf,info->xmit_cnt);
2071                }
2072                usc_start_transmitter(info);
2073        }
2074        
2075        spin_unlock_irqrestore(&info->irq_spinlock,flags);
2076        
2077}       /* end of mgsl_flush_chars() */
2078
2079/* mgsl_write()
2080 * 
2081 *      Send a block of data
2082 *      
2083 * Arguments:
2084 * 
2085 *      tty             pointer to tty information structure
2086 *      buf             pointer to buffer containing send data
2087 *      count           size of send data in bytes
2088 *      
2089 * Return Value:        number of characters written
2090 */
2091static int mgsl_write(struct tty_struct * tty,
2092                    const unsigned char *buf, int count)
2093{
2094        int     c, ret = 0;
2095        struct mgsl_struct *info = tty->driver_data;
2096        unsigned long flags;
2097        
2098        if ( debug_level >= DEBUG_LEVEL_INFO )
2099                printk( "%s(%d):mgsl_write(%s) count=%d\n",
2100                        __FILE__,__LINE__,info->device_name,count);
2101        
2102        if (mgsl_paranoia_check(info, tty->name, "mgsl_write"))
2103                goto cleanup;
2104
2105        if (!info->xmit_buf)
2106                goto cleanup;
2107
2108        if ( info->params.mode == MGSL_MODE_HDLC ||
2109                        info->params.mode == MGSL_MODE_RAW ) {
2110                /* operating in synchronous (frame oriented) mode */
2111                if (info->tx_active) {
2112
2113                        if ( info->params.mode == MGSL_MODE_HDLC ) {
2114                                ret = 0;
2115                                goto cleanup;
2116                        }
2117                        /* transmitter is actively sending data -
2118                         * if we have multiple transmit dma and
2119                         * holding buffers, attempt to queue this
2120                         * frame for transmission at a later time.
2121                         */
2122                        if (info->tx_holding_count >= info->num_tx_holding_buffers ) {
2123                                /* no tx holding buffers available */
2124                                ret = 0;
2125                                goto cleanup;
2126                        }
2127
2128                        /* queue transmit frame request */
2129                        ret = count;
2130                        save_tx_buffer_request(info,buf,count);
2131
2132                        /* if we have sufficient tx dma buffers,
2133                         * load the next buffered tx request
2134                         */
2135                        spin_lock_irqsave(&info->irq_spinlock,flags);
2136                        load_next_tx_holding_buffer(info);
2137                        spin_unlock_irqrestore(&info->irq_spinlock,flags);
2138                        goto cleanup;
2139                }
2140        
2141                /* if operating in HDLC LoopMode and the adapter  */
2142                /* has yet to be inserted into the loop, we can't */
2143                /* transmit                                       */
2144
2145                if ( (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) &&
2146                        !usc_loopmode_active(info) )
2147                {
2148                        ret = 0;
2149                        goto cleanup;
2150                }
2151
2152                if ( info->xmit_cnt ) {
2153                        /* Send accumulated from send_char() calls */
2154                        /* as frame and wait before accepting more data. */
2155                        ret = 0;
2156                        
2157                        /* copy data from circular xmit_buf to */
2158                        /* transmit DMA buffer. */
2159                        mgsl_load_tx_dma_buffer(info,
2160                                info->xmit_buf,info->xmit_cnt);
2161                        if ( debug_level >= DEBUG_LEVEL_INFO )
2162                                printk( "%s(%d):mgsl_write(%s) sync xmit_cnt flushing\n",
2163                                        __FILE__,__LINE__,info->device_name);
2164                } else {
2165                        if ( debug_level >= DEBUG_LEVEL_INFO )
2166                                printk( "%s(%d):mgsl_write(%s) sync transmit accepted\n",
2167                                        __FILE__,__LINE__,info->device_name);
2168                        ret = count;
2169                        info->xmit_cnt = count;
2170                        mgsl_load_tx_dma_buffer(info,buf,count);
2171                }
2172        } else {
2173                while (1) {
2174                        spin_lock_irqsave(&info->irq_spinlock,flags);
2175                        c = min_t(int, count,
2176                                min(SERIAL_XMIT_SIZE - info->xmit_cnt - 1,
2177                                    SERIAL_XMIT_SIZE - info->xmit_head));
2178                        if (c <= 0) {
2179                                spin_unlock_irqrestore(&info->irq_spinlock,flags);
2180                                break;
2181                        }
2182                        memcpy(info->xmit_buf + info->xmit_head, buf, c);
2183                        info->xmit_head = ((info->xmit_head + c) &
2184                                           (SERIAL_XMIT_SIZE-1));
2185                        info->xmit_cnt += c;
2186                        spin_unlock_irqrestore(&info->irq_spinlock,flags);
2187                        buf += c;
2188                        count -= c;
2189                        ret += c;
2190                }
2191        }       
2192        
2193        if (info->xmit_cnt && !tty->stopped && !tty->hw_stopped) {
2194                spin_lock_irqsave(&info->irq_spinlock,flags);
2195                if (!info->tx_active)
2196                        usc_start_transmitter(info);
2197                spin_unlock_irqrestore(&info->irq_spinlock,flags);
2198        }
2199cleanup:        
2200        if ( debug_level >= DEBUG_LEVEL_INFO )
2201                printk( "%s(%d):mgsl_write(%s) returning=%d\n",
2202                        __FILE__,__LINE__,info->device_name,ret);
2203                        
2204        return ret;
2205        
2206}       /* end of mgsl_write() */
2207
2208/* mgsl_write_room()
2209 *
2210 *      Return the count of free bytes in transmit buffer
2211 *      
2212 * Arguments:           tty     pointer to tty info structure
2213 * Return Value:        None
2214 */
2215static int mgsl_write_room(struct tty_struct *tty)
2216{
2217        struct mgsl_struct *info = tty->driver_data;
2218        int     ret;
2219                                
2220        if (mgsl_paranoia_check(info, tty->name, "mgsl_write_room"))
2221                return 0;
2222        ret = SERIAL_XMIT_SIZE - info->xmit_cnt - 1;
2223        if (ret < 0)
2224                ret = 0;
2225                
2226        if (debug_level >= DEBUG_LEVEL_INFO)
2227                printk("%s(%d):mgsl_write_room(%s)=%d\n",
2228                         __FILE__,__LINE__, info->device_name,ret );
2229                         
2230        if ( info->params.mode == MGSL_MODE_HDLC ||
2231                info->params.mode == MGSL_MODE_RAW ) {
2232                /* operating in synchronous (frame oriented) mode */
2233                if ( info->tx_active )
2234                        return 0;
2235                else
2236                        return HDLC_MAX_FRAME_SIZE;
2237        }
2238        
2239        return ret;
2240        
2241}       /* end of mgsl_write_room() */
2242
2243/* mgsl_chars_in_buffer()
2244 *
2245 *      Return the count of bytes in transmit buffer
2246 *      
2247 * Arguments:           tty     pointer to tty info structure
2248 * Return Value:        None
2249 */
2250static int mgsl_chars_in_buffer(struct tty_struct *tty)
2251{
2252        struct mgsl_struct *info = tty->driver_data;
2253                         
2254        if (debug_level >= DEBUG_LEVEL_INFO)
2255                printk("%s(%d):mgsl_chars_in_buffer(%s)\n",
2256                         __FILE__,__LINE__, info->device_name );
2257                         
2258        if (mgsl_paranoia_check(info, tty->name, "mgsl_chars_in_buffer"))
2259                return 0;
2260                
2261        if (debug_level >= DEBUG_LEVEL_INFO)
2262                printk("%s(%d):mgsl_chars_in_buffer(%s)=%d\n",
2263                         __FILE__,__LINE__, info->device_name,info->xmit_cnt );
2264                         
2265        if ( info->params.mode == MGSL_MODE_HDLC ||
2266                info->params.mode == MGSL_MODE_RAW ) {
2267                /* operating in synchronous (frame oriented) mode */
2268                if ( info->tx_active )
2269                        return info->max_frame_size;
2270                else
2271                        return 0;
2272        }
2273                         
2274        return info->xmit_cnt;
2275}       /* end of mgsl_chars_in_buffer() */
2276
2277/* mgsl_flush_buffer()
2278 *
2279 *      Discard all data in the send buffer
2280 *      
2281 * Arguments:           tty     pointer to tty info structure
2282 * Return Value:        None
2283 */
2284static void mgsl_flush_buffer(struct tty_struct *tty)
2285{
2286        struct mgsl_struct *info = tty->driver_data;
2287        unsigned long flags;
2288        
2289        if (debug_level >= DEBUG_LEVEL_INFO)
2290                printk("%s(%d):mgsl_flush_buffer(%s) entry\n",
2291                         __FILE__,__LINE__, info->device_name );
2292        
2293        if (mgsl_paranoia_check(info, tty->name, "mgsl_flush_buffer"))
2294                return;
2295                
2296        spin_lock_irqsave(&info->irq_spinlock,flags); 
2297        info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
2298        del_timer(&info->tx_timer);     
2299        spin_unlock_irqrestore(&info->irq_spinlock,flags);
2300        
2301        tty_wakeup(tty);
2302}
2303
2304/* mgsl_send_xchar()
2305 *
2306 *      Send a high-priority XON/XOFF character
2307 *      
2308 * Arguments:           tty     pointer to tty info structure
2309 *                      ch      character to send
2310 * Return Value:        None
2311 */
2312static void mgsl_send_xchar(struct tty_struct *tty, char ch)
2313{
2314        struct mgsl_struct *info = tty->driver_data;
2315        unsigned long flags;
2316
2317        if (debug_level >= DEBUG_LEVEL_INFO)
2318                printk("%s(%d):mgsl_send_xchar(%s,%d)\n",
2319                         __FILE__,__LINE__, info->device_name, ch );
2320                         
2321        if (mgsl_paranoia_check(info, tty->name, "mgsl_send_xchar"))
2322                return;
2323
2324        info->x_char = ch;
2325        if (ch) {
2326                /* Make sure transmit interrupts are on */
2327                spin_lock_irqsave(&info->irq_spinlock,flags);
2328                if (!info->tx_enabled)
2329                        usc_start_transmitter(info);
2330                spin_unlock_irqrestore(&info->irq_spinlock,flags);
2331        }
2332}       /* end of mgsl_send_xchar() */
2333
2334/* mgsl_throttle()
2335 * 
2336 *      Signal remote device to throttle send data (our receive data)
2337 *      
2338 * Arguments:           tty     pointer to tty info structure
2339 * Return Value:        None
2340 */
2341static void mgsl_throttle(struct tty_struct * tty)
2342{
2343        struct mgsl_struct *info = tty->driver_data;
2344        unsigned long flags;
2345        
2346        if (debug_level >= DEBUG_LEVEL_INFO)
2347                printk("%s(%d):mgsl_throttle(%s) entry\n",
2348                         __FILE__,__LINE__, info->device_name );
2349
2350        if (mgsl_paranoia_check(info, tty->name, "mgsl_throttle"))
2351                return;
2352        
2353        if (I_IXOFF(tty))
2354                mgsl_send_xchar(tty, STOP_CHAR(tty));
2355
2356        if (C_CRTSCTS(tty)) {
2357                spin_lock_irqsave(&info->irq_spinlock,flags);
2358                info->serial_signals &= ~SerialSignal_RTS;
2359                usc_set_serial_signals(info);
2360                spin_unlock_irqrestore(&info->irq_spinlock,flags);
2361        }
2362}       /* end of mgsl_throttle() */
2363
2364/* mgsl_unthrottle()
2365 * 
2366 *      Signal remote device to stop throttling send data (our receive data)
2367 *      
2368 * Arguments:           tty     pointer to tty info structure
2369 * Return Value:        None
2370 */
2371static void mgsl_unthrottle(struct tty_struct * tty)
2372{
2373        struct mgsl_struct *info = tty->driver_data;
2374        unsigned long flags;
2375        
2376        if (debug_level >= DEBUG_LEVEL_INFO)
2377                printk("%s(%d):mgsl_unthrottle(%s) entry\n",
2378                         __FILE__,__LINE__, info->device_name );
2379
2380        if (mgsl_paranoia_check(info, tty->name, "mgsl_unthrottle"))
2381                return;
2382        
2383        if (I_IXOFF(tty)) {
2384                if (info->x_char)
2385                        info->x_char = 0;
2386                else
2387                        mgsl_send_xchar(tty, START_CHAR(tty));
2388        }
2389
2390        if (C_CRTSCTS(tty)) {
2391                spin_lock_irqsave(&info->irq_spinlock,flags);
2392                info->serial_signals |= SerialSignal_RTS;
2393                usc_set_serial_signals(info);
2394                spin_unlock_irqrestore(&info->irq_spinlock,flags);
2395        }
2396        
2397}       /* end of mgsl_unthrottle() */
2398
2399/* mgsl_get_stats()
2400 * 
2401 *      get the current serial parameters information
2402 *
2403 * Arguments:   info            pointer to device instance data
2404 *              user_icount     pointer to buffer to hold returned stats
2405 *      
2406 * Return Value:        0 if success, otherwise error code
2407 */
2408static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount __user *user_icount)
2409{
2410        int err;
2411        
2412        if (debug_level >= DEBUG_LEVEL_INFO)
2413                printk("%s(%d):mgsl_get_params(%s)\n",
2414                         __FILE__,__LINE__, info->device_name);
2415                        
2416        if (!user_icount) {
2417                memset(&info->icount, 0, sizeof(info->icount));
2418        } else {
2419                mutex_lock(&info->port.mutex);
2420                COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
2421                mutex_unlock(&info->port.mutex);
2422                if (err)
2423                        return -EFAULT;
2424        }
2425        
2426        return 0;
2427        
2428}       /* end of mgsl_get_stats() */
2429
2430/* mgsl_get_params()
2431 * 
2432 *      get the current serial parameters information
2433 *
2434 * Arguments:   info            pointer to device instance data
2435 *              user_params     pointer to buffer to hold returned params
2436 *      
2437 * Return Value:        0 if success, otherwise error code
2438 */
2439static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS __user *user_params)
2440{
2441        int err;
2442        if (debug_level >= DEBUG_LEVEL_INFO)
2443                printk("%s(%d):mgsl_get_params(%s)\n",
2444                         __FILE__,__LINE__, info->device_name);
2445                        
2446        mutex_lock(&info->port.mutex);
2447        COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2448        mutex_unlock(&info->port.mutex);
2449        if (err) {
2450                if ( debug_level >= DEBUG_LEVEL_INFO )
2451                        printk( "%s(%d):mgsl_get_params(%s) user buffer copy failed\n",
2452                                __FILE__,__LINE__,info->device_name);
2453                return -EFAULT;
2454        }
2455        
2456        return 0;
2457        
2458}       /* end of mgsl_get_params() */
2459
2460/* mgsl_set_params()
2461 * 
2462 *      set the serial parameters
2463 *      
2464 * Arguments:
2465 * 
2466 *      info            pointer to device instance data
2467 *      new_params      user buffer containing new serial params
2468 *
2469 * Return Value:        0 if success, otherwise error code
2470 */
2471static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS __user *new_params)
2472{
2473        unsigned long flags;
2474        MGSL_PARAMS tmp_params;
2475        int err;
2476 
2477        if (debug_level >= DEBUG_LEVEL_INFO)
2478                printk("%s(%d):mgsl_set_params %s\n", __FILE__,__LINE__,
2479                        info->device_name );
2480        COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2481        if (err) {
2482                if ( debug_level >= DEBUG_LEVEL_INFO )
2483                        printk( "%s(%d):mgsl_set_params(%s) user buffer copy failed\n",
2484                                __FILE__,__LINE__,info->device_name);
2485                return -EFAULT;
2486        }
2487        
2488        mutex_lock(&info->port.mutex);
2489        spin_lock_irqsave(&info->irq_spinlock,flags);
2490        memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2491        spin_unlock_irqrestore(&info->irq_spinlock,flags);
2492        
2493        mgsl_change_params(info);
2494        mutex_unlock(&info->port.mutex);
2495        
2496        return 0;
2497        
2498}       /* end of mgsl_set_params() */
2499
2500/* mgsl_get_txidle()
2501 * 
2502 *      get the current transmit idle mode
2503 *
2504 * Arguments:   info            pointer to device instance data
2505 *              idle_mode       pointer to buffer to hold returned idle mode
2506 *      
2507 * Return Value:        0 if success, otherwise error code
2508 */
2509static int mgsl_get_txidle(struct mgsl_struct * info, int __user *idle_mode)
2510{
2511        int err;
2512        
2513        if (debug_level >= DEBUG_LEVEL_INFO)
2514                printk("%s(%d):mgsl_get_txidle(%s)=%d\n",
2515                         __FILE__,__LINE__, info->device_name, info->idle_mode);
2516                        
2517        COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
2518        if (err) {
2519                if ( debug_level >= DEBUG_LEVEL_INFO )
2520                        printk( "%s(%d):mgsl_get_txidle(%s) user buffer copy failed\n",
2521                                __FILE__,__LINE__,info->device_name);
2522                return -EFAULT;
2523        }
2524        
2525        return 0;
2526        
2527}       /* end of mgsl_get_txidle() */
2528
2529/* mgsl_set_txidle()    service ioctl to set transmit idle mode
2530 *      
2531 * Arguments:           info            pointer to device instance data
2532 *                      idle_mode       new idle mode
2533 *
2534 * Return Value:        0 if success, otherwise error code
2535 */
2536static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode)
2537{
2538        unsigned long flags;
2539 
2540        if (debug_level >= DEBUG_LEVEL_INFO)
2541                printk("%s(%d):mgsl_set_txidle(%s,%d)\n", __FILE__,__LINE__,
2542                        info->device_name, idle_mode );
2543                        
2544        spin_lock_irqsave(&info->irq_spinlock,flags);
2545        info->idle_mode = idle_mode;
2546        usc_set_txidle( info );
2547        spin_unlock_irqrestore(&info->irq_spinlock,flags);
2548        return 0;
2549        
2550}       /* end of mgsl_set_txidle() */
2551
2552/* mgsl_txenable()
2553 * 
2554 *      enable or disable the transmitter
2555 *      
2556 * Arguments:
2557 * 
2558 *      info            pointer to device instance data
2559 *      enable          1 = enable, 0 = disable
2560 *
2561 * Return Value:        0 if success, otherwise error code
2562 */
2563static int mgsl_txenable(struct mgsl_struct * info, int enable)
2564{
2565        unsigned long flags;
2566 
2567        if (debug_level >= DEBUG_LEVEL_INFO)
2568                printk("%s(%d):mgsl_txenable(%s,%d)\n", __FILE__,__LINE__,
2569                        info->device_name, enable);
2570                        
2571        spin_lock_irqsave(&info->irq_spinlock,flags);
2572        if ( enable ) {
2573                if ( !info->tx_enabled ) {
2574
2575                        usc_start_transmitter(info);
2576                        /*--------------------------------------------------
2577                         * if HDLC/SDLC Loop mode, attempt to insert the
2578                         * station in the 'loop' by setting CMR:13. Upon
2579                         * receipt of the next GoAhead (RxAbort) sequence,
2580                         * the OnLoop indicator (CCSR:7) should go active
2581                         * to indicate that we are on the loop
2582                         *--------------------------------------------------*/
2583                        if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
2584                                usc_loopmode_insert_request( info );
2585                }
2586        } else {
2587                if ( info->tx_enabled )
2588                        usc_stop_transmitter(info);
2589        }
2590        spin_unlock_irqrestore(&info->irq_spinlock,flags);
2591        return 0;
2592        
2593}       /* end of mgsl_txenable() */
2594
2595/* mgsl_txabort()       abort send HDLC frame
2596 *      
2597 * Arguments:           info            pointer to device instance data
2598 * Return Value:        0 if success, otherwise error code
2599 */
2600static int mgsl_txabort(struct mgsl_struct * info)
2601{
2602        unsigned long flags;
2603 
2604        if (debug_level >= DEBUG_LEVEL_INFO)
2605                printk("%s(%d):mgsl_txabort(%s)\n", __FILE__,__LINE__,
2606                        info->device_name);
2607                        
2608        spin_lock_irqsave(&info->irq_spinlock,flags);
2609        if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC )
2610        {
2611                if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
2612                        usc_loopmode_cancel_transmit( info );
2613                else
2614                        usc_TCmd(info,TCmd_SendAbort);
2615        }
2616        spin_unlock_irqrestore(&info->irq_spinlock,flags);
2617        return 0;
2618        
2619}       /* end of mgsl_txabort() */
2620
2621/* mgsl_rxenable()      enable or disable the receiver
2622 *      
2623 * Arguments:           info            pointer to device instance data
2624 *                      enable          1 = enable, 0 = disable
2625 * Return Value:        0 if success, otherwise error code
2626 */
2627static int mgsl_rxenable(struct mgsl_struct * info, int enable)
2628{
2629        unsigned long flags;
2630 
2631        if (debug_level >= DEBUG_LEVEL_INFO)
2632                printk("%s(%d):mgsl_rxenable(%s,%d)\n", __FILE__,__LINE__,
2633                        info->device_name, enable);
2634                        
2635        spin_lock_irqsave(&info->irq_spinlock,flags);
2636        if ( enable ) {
2637                if ( !info->rx_enabled )
2638                        usc_start_receiver(info);
2639        } else {
2640                if ( info->rx_enabled )
2641                        usc_stop_receiver(info);
2642        }
2643        spin_unlock_irqrestore(&info->irq_spinlock,flags);
2644        return 0;
2645        
2646}       /* end of mgsl_rxenable() */
2647
2648/* mgsl_wait_event()    wait for specified event to occur
2649 *      
2650 * Arguments:           info    pointer to device instance data
2651 *                      mask    pointer to bitmask of events to wait for
2652 * Return Value:        0       if successful and bit mask updated with
2653 *                              of events triggerred,
2654 *                      otherwise error code
2655 */
2656static int mgsl_wait_event(struct mgsl_struct * info, int __user * mask_ptr)
2657{
2658        unsigned long flags;
2659        int s;
2660        int rc=0;
2661        struct mgsl_icount cprev, cnow;
2662        int events;
2663        int mask;
2664        struct  _input_signal_events oldsigs, newsigs;
2665        DECLARE_WAITQUEUE(wait, current);
2666
2667        COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
2668        if (rc) {
2669                return  -EFAULT;
2670        }
2671                 
2672        if (debug_level >= DEBUG_LEVEL_INFO)
2673                printk("%s(%d):mgsl_wait_event(%s,%d)\n", __FILE__,__LINE__,
2674                        info->device_name, mask);
2675
2676        spin_lock_irqsave(&info->irq_spinlock,flags);
2677
2678        /* return immediately if state matches requested events */
2679        usc_get_serial_signals(info);
2680        s = info->serial_signals;
2681        events = mask &
2682                ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2683                  ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2684                  ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2685                  ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2686        if (events) {
2687                spin_unlock_irqrestore(&info->irq_spinlock,flags);
2688                goto exit;
2689        }
2690
2691        /* save current irq counts */
2692        cprev = info->icount;
2693        oldsigs = info->input_signal_events;
2694        
2695        /* enable hunt and idle irqs if needed */
2696        if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2697                u16 oldreg = usc_InReg(info,RICR);
2698                u16 newreg = oldreg +
2699                         (mask & MgslEvent_ExitHuntMode ? RXSTATUS_EXITED_HUNT:0) +
2700                         (mask & MgslEvent_IdleReceived ? RXSTATUS_IDLE_RECEIVED:0);
2701                if (oldreg != newreg)
2702                        usc_OutReg(info, RICR, newreg);
2703        }
2704        
2705        set_current_state(TASK_INTERRUPTIBLE);
2706        add_wait_queue(&info->event_wait_q, &wait);
2707        
2708        spin_unlock_irqrestore(&info->irq_spinlock,flags);
2709        
2710
2711        for(;;) {
2712                schedule();
2713                if (signal_pending(current)) {
2714                        rc = -ERESTARTSYS;
2715                        break;
2716                }
2717                        
2718                /* get current irq counts */
2719                spin_lock_irqsave(&info->irq_spinlock,flags);
2720                cnow = info->icount;
2721                newsigs = info->input_signal_events;
2722                set_current_state(TASK_INTERRUPTIBLE);
2723                spin_unlock_irqrestore(&info->irq_spinlock,flags);
2724
2725                /* if no change, wait aborted for some reason */
2726                if (newsigs.dsr_up   == oldsigs.dsr_up   &&
2727                    newsigs.dsr_down == oldsigs.dsr_down &&
2728                    newsigs.dcd_up   == oldsigs.dcd_up   &&
2729                    newsigs.dcd_down == oldsigs.dcd_down &&
2730                    newsigs.cts_up   == oldsigs.cts_up   &&
2731                    newsigs.cts_down == oldsigs.cts_down &&
2732                    newsigs.ri_up    == oldsigs.ri_up    &&
2733                    newsigs.ri_down  == oldsigs.ri_down  &&
2734                    cnow.exithunt    == cprev.exithunt   &&
2735                    cnow.rxidle      == cprev.rxidle) {
2736                        rc = -EIO;
2737                        break;
2738                }
2739
2740                events = mask &
2741                        ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
2742                        (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2743                        (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
2744                        (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2745                        (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
2746                        (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2747                        (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
2748                        (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
2749                        (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
2750                          (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
2751                if (events)
2752                        break;
2753                
2754                cprev = cnow;
2755                oldsigs = newsigs;
2756        }
2757        
2758        remove_wait_queue(&info->event_wait_q, &wait);
2759        set_current_state(TASK_RUNNING);
2760
2761        if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2762                spin_lock_irqsave(&info->irq_spinlock,flags);
2763                if (!waitqueue_active(&info->event_wait_q)) {
2764                        /* disable enable exit hunt mode/idle rcvd IRQs */
2765                        usc_OutReg(info, RICR, usc_InReg(info,RICR) &
2766                                ~(RXSTATUS_EXITED_HUNT | RXSTATUS_IDLE_RECEIVED));
2767                }
2768                spin_unlock_irqrestore(&info->irq_spinlock,flags);
2769        }
2770exit:
2771        if ( rc == 0 )
2772                PUT_USER(rc, events, mask_ptr);
2773                
2774        return rc;
2775        
2776}       /* end of mgsl_wait_event() */
2777
2778static int modem_input_wait(struct mgsl_struct *info,int arg)
2779{
2780        unsigned long flags;
2781        int rc;
2782        struct mgsl_icount cprev, cnow;
2783        DECLARE_WAITQUEUE(wait, current);
2784
2785        /* save current irq counts */
2786        spin_lock_irqsave(&info->irq_spinlock,flags);
2787        cprev = info->icount;
2788        add_wait_queue(&info->status_event_wait_q, &wait);
2789        set_current_state(TASK_INTERRUPTIBLE);
2790        spin_unlock_irqrestore(&info->irq_spinlock,flags);
2791
2792        for(;;) {
2793                schedule();
2794                if (signal_pending(current)) {
2795                        rc = -ERESTARTSYS;
2796                        break;
2797                }
2798
2799                /* get new irq counts */
2800                spin_lock_irqsave(&info->irq_spinlock,flags);
2801                cnow = info->icount;
2802                set_current_state(TASK_INTERRUPTIBLE);
2803                spin_unlock_irqrestore(&info->irq_spinlock,flags);
2804
2805                /* if no change, wait aborted for some reason */
2806                if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
2807                    cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
2808                        rc = -EIO;
2809                        break;
2810                }
2811
2812                /* check for change in caller specified modem input */
2813                if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
2814                    (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
2815                    (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
2816                    (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
2817                        rc = 0;
2818                        break;
2819                }
2820
2821                cprev = cnow;
2822        }
2823        remove_wait_queue(&info->status_event_wait_q, &wait);
2824        set_current_state(TASK_RUNNING);
2825        return rc;
2826}
2827
2828/* return the state of the serial control and status signals
2829 */
2830static int tiocmget(struct tty_struct *tty)
2831{
2832        struct mgsl_struct *info = tty->driver_data;
2833        unsigned int result;
2834        unsigned long flags;
2835
2836        spin_lock_irqsave(&info->irq_spinlock,flags);
2837        usc_get_serial_signals(info);
2838        spin_unlock_irqrestore(&info->irq_spinlock,flags);
2839
2840        result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
2841                ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
2842                ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
2843                ((info->serial_signals & SerialSignal_RI)  ? TIOCM_RNG:0) +
2844                ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
2845                ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
2846
2847        if (debug_level >= DEBUG_LEVEL_INFO)
2848                printk("%s(%d):%s tiocmget() value=%08X\n",
2849                         __FILE__,__LINE__, info->device_name, result );
2850        return result;
2851}
2852
2853/* set modem control signals (DTR/RTS)
2854 */
2855static int tiocmset(struct tty_struct *tty,
2856                                    unsigned int set, unsigned int clear)
2857{
2858        struct mgsl_struct *info = tty->driver_data;
2859        unsigned long flags;
2860
2861        if (debug_level >= DEBUG_LEVEL_INFO)
2862                printk("%s(%d):%s tiocmset(%x,%x)\n",
2863                        __FILE__,__LINE__,info->device_name, set, clear);
2864
2865        if (set & TIOCM_RTS)
2866                info->serial_signals |= SerialSignal_RTS;
2867        if (set & TIOCM_DTR)
2868                info->serial_signals |= SerialSignal_DTR;
2869        if (clear & TIOCM_RTS)
2870                info->serial_signals &= ~SerialSignal_RTS;
2871        if (clear & TIOCM_DTR)
2872                info->serial_signals &= ~SerialSignal_DTR;
2873
2874        spin_lock_irqsave(&info->irq_spinlock,flags);
2875        usc_set_serial_signals(info);
2876        spin_unlock_irqrestore(&info->irq_spinlock,flags);
2877
2878        return 0;
2879}
2880
2881/* mgsl_break()         Set or clear transmit break condition
2882 *
2883 * Arguments:           tty             pointer to tty instance data
2884 *                      break_state     -1=set break condition, 0=clear
2885 * Return Value:        error code
2886 */
2887static int mgsl_break(struct tty_struct *tty, int break_state)
2888{
2889        struct mgsl_struct * info = tty->driver_data;
2890        unsigned long flags;
2891        
2892        if (debug_level >= DEBUG_LEVEL_INFO)
2893                printk("%s(%d):mgsl_break(%s,%d)\n",
2894                         __FILE__,__LINE__, info->device_name, break_state);
2895                         
2896        if (mgsl_paranoia_check(info, tty->name, "mgsl_break"))
2897                return -EINVAL;
2898
2899        spin_lock_irqsave(&info->irq_spinlock,flags);
2900        if (break_state == -1)
2901                usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) | BIT7));
2902        else 
2903                usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) & ~BIT7));
2904        spin_unlock_irqrestore(&info->irq_spinlock,flags);
2905        return 0;
2906        
2907}       /* end of mgsl_break() */
2908
2909/*
2910 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
2911 * Return: write counters to the user passed counter struct
2912 * NB: both 1->0 and 0->1 transitions are counted except for
2913 *     RI where only 0->1 is counted.
2914 */
2915static int msgl_get_icount(struct tty_struct *tty,
2916                                struct serial_icounter_struct *icount)
2917
2918{
2919        struct mgsl_struct * info = tty->driver_data;
2920        struct mgsl_icount cnow;        /* kernel counter temps */
2921        unsigned long flags;
2922
2923        spin_lock_irqsave(&info->irq_spinlock,flags);
2924        cnow = info->icount;
2925        spin_unlock_irqrestore(&info->irq_spinlock,flags);
2926
2927        icount->cts = cnow.cts;
2928        icount->dsr = cnow.dsr;
2929        icount->rng = cnow.rng;
2930        icount->dcd = cnow.dcd;
2931        icount->rx = cnow.rx;
2932        icount->tx = cnow.tx;
2933        icount->frame = cnow.frame;
2934        icount->overrun = cnow.overrun;
2935        icount->parity = cnow.parity;
2936        icount->brk = cnow.brk;
2937        icount->buf_overrun = cnow.buf_overrun;
2938        return 0;
2939}
2940
2941/* mgsl_ioctl() Service an IOCTL request
2942 *      
2943 * Arguments:
2944 * 
2945 *      tty     pointer to tty instance data
2946 *      cmd     IOCTL command code
2947 *      arg     command argument/context
2948 *      
2949 * Return Value:        0 if success, otherwise error code
2950 */
2951static int mgsl_ioctl(struct tty_struct *tty,
2952                    unsigned int cmd, unsigned long arg)
2953{
2954        struct mgsl_struct * info = tty->driver_data;
2955        
2956        if (debug_level >= DEBUG_LEVEL_INFO)
2957                printk("%s(%d):mgsl_ioctl %s cmd=%08X\n", __FILE__,__LINE__,
2958                        info->device_name, cmd );
2959        
2960        if (mgsl_paranoia_check(info, tty->name, "mgsl_ioctl"))
2961                return -ENODEV;
2962
2963        if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
2964            (cmd != TIOCMIWAIT)) {
2965                if (tty_io_error(tty))
2966                    return -EIO;
2967        }
2968
2969        return mgsl_ioctl_common(info, cmd, arg);
2970}
2971
2972static int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg)
2973{
2974        void __user *argp = (void __user *)arg;
2975        
2976        switch (cmd) {
2977                case MGSL_IOCGPARAMS:
2978                        return mgsl_get_params(info, argp);
2979                case MGSL_IOCSPARAMS:
2980                        return mgsl_set_params(info, argp);
2981                case MGSL_IOCGTXIDLE:
2982                        return mgsl_get_txidle(info, argp);
2983                case MGSL_IOCSTXIDLE:
2984                        return mgsl_set_txidle(info,(int)arg);
2985                case MGSL_IOCTXENABLE:
2986                        return mgsl_txenable(info,(int)arg);
2987                case MGSL_IOCRXENABLE:
2988                        return mgsl_rxenable(info,(int)arg);
2989                case MGSL_IOCTXABORT:
2990                        return mgsl_txabort(info);
2991                case MGSL_IOCGSTATS:
2992                        return mgsl_get_stats(info, argp);
2993                case MGSL_IOCWAITEVENT:
2994                        return mgsl_wait_event(info, argp);
2995                case MGSL_IOCLOOPTXDONE:
2996                        return mgsl_loopmode_send_done(info);
2997                /* Wait for modem input (DCD,RI,DSR,CTS) change
2998                 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
2999                 */
3000                case TIOCMIWAIT:
3001                        return modem_input_wait(info,(int)arg);
3002
3003                default:
3004                        return -ENOIOCTLCMD;
3005        }
3006        return 0;
3007}
3008
3009/* mgsl_set_termios()
3010 * 
3011 *      Set new termios settings
3012 *      
3013 * Arguments:
3014 * 
3015 *      tty             pointer to tty structure
3016 *      termios         pointer to buffer to hold returned old termios
3017 *      
3018 * Return Value:                None
3019 */
3020static void mgsl_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
3021{
3022        struct mgsl_struct *info = tty->driver_data;
3023        unsigned long flags;
3024        
3025        if (debug_level >= DEBUG_LEVEL_INFO)
3026                printk("%s(%d):mgsl_set_termios %s\n", __FILE__,__LINE__,
3027                        tty->driver->name );
3028        
3029        mgsl_change_params(info);
3030
3031        /* Handle transition to B0 status */
3032        if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) {
3033                info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
3034                spin_lock_irqsave(&info->irq_spinlock,flags);
3035                usc_set_serial_signals(info);
3036                spin_unlock_irqrestore(&info->irq_spinlock,flags);
3037        }
3038
3039        /* Handle transition away from B0 status */
3040        if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) {
3041                info->serial_signals |= SerialSignal_DTR;
3042                if (!C_CRTSCTS(tty) || !tty_throttled(tty))
3043                        info->serial_signals |= SerialSignal_RTS;
3044                spin_lock_irqsave(&info->irq_spinlock,flags);
3045                usc_set_serial_signals(info);
3046                spin_unlock_irqrestore(&info->irq_spinlock,flags);
3047        }
3048
3049        /* Handle turning off CRTSCTS */
3050        if (old_termios->c_cflag & CRTSCTS && !C_CRTSCTS(tty)) {
3051                tty->hw_stopped = 0;
3052                mgsl_start(tty);
3053        }
3054
3055}       /* end of mgsl_set_termios() */
3056
3057/* mgsl_close()
3058 * 
3059 *      Called when port is closed. Wait for remaining data to be
3060 *      sent. Disable port and free resources.
3061 *      
3062 * Arguments:
3063 * 
3064 *      tty     pointer to open tty structure
3065 *      filp    pointer to open file object
3066 *      
3067 * Return Value:        None
3068 */
3069static void mgsl_close(struct tty_struct *tty, struct file * filp)
3070{
3071        struct mgsl_struct * info = tty->driver_data;
3072
3073        if (mgsl_paranoia_check(info, tty->name, "mgsl_close"))
3074                return;
3075        
3076        if (debug_level >= DEBUG_LEVEL_INFO)
3077                printk("%s(%d):mgsl_close(%s) entry, count=%d\n",
3078                         __FILE__,__LINE__, info->device_name, info->port.count);
3079
3080        if (tty_port_close_start(&info->port, tty, filp) == 0)
3081                goto cleanup;
3082
3083        mutex_lock(&info->port.mutex);
3084        if (tty_port_initialized(&info->port))
3085                mgsl_wait_until_sent(tty, info->timeout);
3086        mgsl_flush_buffer(tty);
3087        tty_ldisc_flush(tty);
3088        shutdown(info);
3089        mutex_unlock(&info->port.mutex);
3090
3091        tty_port_close_end(&info->port, tty);   
3092        info->port.tty = NULL;
3093cleanup:                        
3094        if (debug_level >= DEBUG_LEVEL_INFO)
3095                printk("%s(%d):mgsl_close(%s) exit, count=%d\n", __FILE__,__LINE__,
3096                        tty->driver->name, info->port.count);
3097                        
3098}       /* end of mgsl_close() */
3099
3100/* mgsl_wait_until_sent()
3101 *
3102 *      Wait until the transmitter is empty.
3103 *
3104 * Arguments:
3105 *
3106 *      tty             pointer to tty info structure
3107 *      timeout         time to wait for send completion
3108 *
3109 * Return Value:        None
3110 */
3111static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout)
3112{
3113        struct mgsl_struct * info = tty->driver_data;
3114        unsigned long orig_jiffies, char_time;
3115
3116        if (!info )
3117                return;
3118
3119        if (debug_level >= DEBUG_LEVEL_INFO)
3120                printk("%s(%d):mgsl_wait_until_sent(%s) entry\n",
3121                         __FILE__,__LINE__, info->device_name );
3122
3123        if (mgsl_paranoia_check(info, tty->name, "mgsl_wait_until_sent"))
3124                return;
3125
3126        if (!tty_port_initialized(&info->port))
3127                goto exit;
3128
3129        orig_jiffies = jiffies;
3130
3131        /* Set check interval to 1/5 of estimated time to
3132         * send a character, and make it at least 1. The check
3133         * interval should also be less than the timeout.
3134         * Note: use tight timings here to satisfy the NIST-PCTS.
3135         */ 
3136
3137        if ( info->params.data_rate ) {
3138                char_time = info->timeout/(32 * 5);
3139                if (!char_time)
3140                        char_time++;
3141        } else
3142                char_time = 1;
3143                
3144        if (timeout)
3145                char_time = min_t(unsigned long, char_time, timeout);
3146                
3147        if ( info->params.mode == MGSL_MODE_HDLC ||
3148                info->params.mode == MGSL_MODE_RAW ) {
3149                while (info->tx_active) {
3150                        msleep_interruptible(jiffies_to_msecs(char_time));
3151                        if (signal_pending(current))
3152                                break;
3153                        if (timeout && time_after(jiffies, orig_jiffies + timeout))
3154                                break;
3155                }
3156        } else {
3157                while (!(usc_InReg(info,TCSR) & TXSTATUS_ALL_SENT) &&
3158                        info->tx_enabled) {
3159                        msleep_interruptible(jiffies_to_msecs(char_time));
3160                        if (signal_pending(current))
3161                                break;
3162                        if (timeout && time_after(jiffies, orig_jiffies + timeout))
3163                                break;
3164                }
3165        }
3166      
3167exit:
3168        if (debug_level >= DEBUG_LEVEL_INFO)
3169                printk("%s(%d):mgsl_wait_until_sent(%s) exit\n",
3170                         __FILE__,__LINE__, info->device_name );
3171                         
3172}       /* end of mgsl_wait_until_sent() */
3173
3174/* mgsl_hangup()
3175 *
3176 *      Called by tty_hangup() when a hangup is signaled.
3177 *      This is the same as to closing all open files for the port.
3178 *
3179 * Arguments:           tty     pointer to associated tty object
3180 * Return Value:        None
3181 */
3182static void mgsl_hangup(struct tty_struct *tty)
3183{
3184        struct mgsl_struct * info = tty->driver_data;
3185        
3186        if (debug_level >= DEBUG_LEVEL_INFO)
3187                printk("%s(%d):mgsl_hangup(%s)\n",
3188                         __FILE__,__LINE__, info->device_name );
3189                         
3190        if (mgsl_paranoia_check(info, tty->name, "mgsl_hangup"))
3191                return;
3192
3193        mgsl_flush_buffer(tty);
3194        shutdown(info);
3195        
3196        info->port.count = 0;   
3197        tty_port_set_active(&info->port, 0);
3198        info->port.tty = NULL;
3199
3200        wake_up_interruptible(&info->port.open_wait);
3201        
3202}       /* end of mgsl_hangup() */
3203
3204/*
3205 * carrier_raised()
3206 *
3207 *      Return true if carrier is raised
3208 */
3209
3210static int carrier_raised(struct tty_port *port)
3211{
3212        unsigned long flags;
3213        struct mgsl_struct *info = container_of(port, struct mgsl_struct, port);
3214        
3215        spin_lock_irqsave(&info->irq_spinlock, flags);
3216        usc_get_serial_signals(info);
3217        spin_unlock_irqrestore(&info->irq_spinlock, flags);
3218        return (info->serial_signals & SerialSignal_DCD) ? 1 : 0;
3219}
3220
3221static void dtr_rts(struct tty_port *port, int on)
3222{
3223        struct mgsl_struct *info = container_of(port, struct mgsl_struct, port);
3224        unsigned long flags;
3225
3226        spin_lock_irqsave(&info->irq_spinlock,flags);
3227        if (on)
3228                info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
3229        else
3230                info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
3231        usc_set_serial_signals(info);
3232        spin_unlock_irqrestore(&info->irq_spinlock,flags);
3233}
3234
3235
3236/* block_til_ready()
3237 * 
3238 *      Block the current process until the specified port
3239 *      is ready to be opened.
3240 *      
3241 * Arguments:
3242 * 
3243 *      tty             pointer to tty info structure
3244 *      filp            pointer to open file object
3245 *      info            pointer to device instance data
3246 *      
3247 * Return Value:        0 if success, otherwise error code
3248 */
3249static int block_til_ready(struct tty_struct *tty, struct file * filp,
3250                           struct mgsl_struct *info)
3251{
3252        DECLARE_WAITQUEUE(wait, current);
3253        int             retval;
3254        bool            do_clocal = false;
3255        unsigned long   flags;
3256        int             dcd;
3257        struct tty_port *port = &info->port;
3258        
3259        if (debug_level >= DEBUG_LEVEL_INFO)
3260                printk("%s(%d):block_til_ready on %s\n",
3261                         __FILE__,__LINE__, tty->driver->name );
3262
3263        if (filp->f_flags & O_NONBLOCK || tty_io_error(tty)) {
3264                /* nonblock mode is set or port is not enabled */
3265                tty_port_set_active(port, 1);
3266                return 0;
3267        }
3268
3269        if (C_CLOCAL(tty))
3270                do_clocal = true;
3271
3272        /* Wait for carrier detect and the line to become
3273         * free (i.e., not in use by the callout).  While we are in
3274         * this loop, port->count is dropped by one, so that
3275         * mgsl_close() knows when to free things.  We restore it upon
3276         * exit, either normal or abnormal.
3277         */
3278         
3279        retval = 0;
3280        add_wait_queue(&port->open_wait, &wait);
3281        
3282        if (debug_level >= DEBUG_LEVEL_INFO)
3283                printk("%s(%d):block_til_ready before block on %s count=%d\n",
3284                         __FILE__,__LINE__, tty->driver->name, port->count );
3285
3286        spin_lock_irqsave(&info->irq_spinlock, flags);
3287        port->count--;
3288        spin_unlock_irqrestore(&info->irq_spinlock, flags);
3289        port->blocked_open++;
3290
3291        while (1) {
3292                if (C_BAUD(tty) && tty_port_initialized(port))
3293                        tty_port_raise_dtr_rts(port);
3294
3295                set_current_state(TASK_INTERRUPTIBLE);
3296
3297                if (tty_hung_up_p(filp) || !tty_port_initialized(port)) {
3298                        retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3299                                        -EAGAIN : -ERESTARTSYS;
3300                        break;
3301                }
3302
3303                dcd = tty_port_carrier_raised(&info->port);
3304                if (do_clocal || dcd)
3305                        break;
3306
3307                if (signal_pending(current)) {
3308                        retval = -ERESTARTSYS;
3309                        break;
3310                }
3311                
3312                if (debug_level >= DEBUG_LEVEL_INFO)
3313                        printk("%s(%d):block_til_ready blocking on %s count=%d\n",
3314                                 __FILE__,__LINE__, tty->driver->name, port->count );
3315                                 
3316                tty_unlock(tty);
3317                schedule();
3318                tty_lock(tty);
3319        }
3320        
3321        set_current_state(TASK_RUNNING);
3322        remove_wait_queue(&port->open_wait, &wait);
3323        
3324        /* FIXME: Racy on hangup during close wait */
3325        if (!tty_hung_up_p(filp))
3326                port->count++;
3327        port->blocked_open--;
3328        
3329        if (debug_level >= DEBUG_LEVEL_INFO)
3330                printk("%s(%d):block_til_ready after blocking on %s count=%d\n",
3331                         __FILE__,__LINE__, tty->driver->name, port->count );
3332                         
3333        if (!retval)
3334                tty_port_set_active(port, 1);
3335                
3336        return retval;
3337        
3338}       /* end of block_til_ready() */
3339
3340static int mgsl_install(struct tty_driver *driver, struct tty_struct *tty)
3341{
3342        struct mgsl_struct *info;
3343        int line = tty->index;
3344
3345        /* verify range of specified line number */
3346        if (line >= mgsl_device_count) {
3347                printk("%s(%d):mgsl_open with invalid line #%d.\n",
3348                        __FILE__, __LINE__, line);
3349                return -ENODEV;
3350        }
3351
3352        /* find the info structure for the specified line */
3353        info = mgsl_device_list;
3354        while (info && info->line != line)
3355                info = info->next_device;
3356        if (mgsl_paranoia_check(info, tty->name, "mgsl_open"))
3357                return -ENODEV;
3358        tty->driver_data = info;
3359
3360        return tty_port_install(&info->port, driver, tty);
3361}
3362
3363/* mgsl_open()
3364 *
3365 *      Called when a port is opened.  Init and enable port.
3366 *      Perform serial-specific initialization for the tty structure.
3367 *
3368 * Arguments:           tty     pointer to tty info structure
3369 *                      filp    associated file pointer
3370 *
3371 * Return Value:        0 if success, otherwise error code
3372 */
3373static int mgsl_open(struct tty_struct *tty, struct file * filp)
3374{
3375        struct mgsl_struct *info = tty->driver_data;
3376        unsigned long flags;
3377        int retval;
3378
3379        info->port.tty = tty;
3380                
3381        if (debug_level >= DEBUG_LEVEL_INFO)
3382                printk("%s(%d):mgsl_open(%s), old ref count = %d\n",
3383                         __FILE__,__LINE__,tty->driver->name, info->port.count);
3384
3385        info->port.low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
3386
3387        spin_lock_irqsave(&info->netlock, flags);
3388        if (info->netcount) {
3389                retval = -EBUSY;
3390                spin_unlock_irqrestore(&info->netlock, flags);
3391                goto cleanup;
3392        }
3393        info->port.count++;
3394        spin_unlock_irqrestore(&info->netlock, flags);
3395
3396        if (info->port.count == 1) {
3397                /* 1st open on this device, init hardware */
3398                retval = startup(info);
3399                if (retval < 0)
3400                        goto cleanup;
3401        }
3402
3403        retval = block_til_ready(tty, filp, info);
3404        if (retval) {
3405                if (debug_level >= DEBUG_LEVEL_INFO)
3406                        printk("%s(%d):block_til_ready(%s) returned %d\n",
3407                                 __FILE__,__LINE__, info->device_name, retval);
3408                goto cleanup;
3409        }
3410
3411        if (debug_level >= DEBUG_LEVEL_INFO)
3412                printk("%s(%d):mgsl_open(%s) success\n",
3413                         __FILE__,__LINE__, info->device_name);
3414        retval = 0;
3415        
3416cleanup:                        
3417        if (retval) {
3418                if (tty->count == 1)
3419                        info->port.tty = NULL; /* tty layer will release tty struct */
3420                if(info->port.count)
3421                        info->port.count--;
3422        }
3423        
3424        return retval;
3425        
3426}       /* end of mgsl_open() */
3427
3428/*
3429 * /proc fs routines....
3430 */
3431
3432static inline void line_info(struct seq_file *m, struct mgsl_struct *info)
3433{
3434        char    stat_buf[30];
3435        unsigned long flags;
3436
3437        if (info->bus_type == MGSL_BUS_TYPE_PCI) {
3438                seq_printf(m, "%s:PCI io:%04X irq:%d mem:%08X lcr:%08X",
3439                        info->device_name, info->io_base, info->irq_level,
3440                        info->phys_memory_base, info->phys_lcr_base);
3441        } else {
3442                seq_printf(m, "%s:(E)ISA io:%04X irq:%d dma:%d",
3443                        info->device_name, info->io_base, 
3444                        info->irq_level, info->dma_level);
3445        }
3446
3447        /* output current serial signal states */
3448        spin_lock_irqsave(&info->irq_spinlock,flags);
3449        usc_get_serial_signals(info);
3450        spin_unlock_irqrestore(&info->irq_spinlock,flags);
3451        
3452        stat_buf[0] = 0;
3453        stat_buf[1] = 0;
3454        if (info->serial_signals & SerialSignal_RTS)
3455                strcat(stat_buf, "|RTS");
3456        if (info->serial_signals & SerialSignal_CTS)
3457                strcat(stat_buf, "|CTS");
3458        if (info->serial_signals & SerialSignal_DTR)
3459                strcat(stat_buf, "|DTR");
3460        if (info->serial_signals & SerialSignal_DSR)
3461                strcat(stat_buf, "|DSR");
3462        if (info->serial_signals & SerialSignal_DCD)
3463                strcat(stat_buf, "|CD");
3464        if (info->serial_signals & SerialSignal_RI)
3465                strcat(stat_buf, "|RI");
3466
3467        if (info->params.mode == MGSL_MODE_HDLC ||
3468            info->params.mode == MGSL_MODE_RAW ) {
3469                seq_printf(m, " HDLC txok:%d rxok:%d",
3470                              info->icount.txok, info->icount.rxok);
3471                if (info->icount.txunder)
3472                        seq_printf(m, " txunder:%d", info->icount.txunder);
3473                if (info->icount.txabort)
3474                        seq_printf(m, " txabort:%d", info->icount.txabort);
3475                if (info->icount.rxshort)
3476                        seq_printf(m, " rxshort:%d", info->icount.rxshort);
3477                if (info->icount.rxlong)
3478                        seq_printf(m, " rxlong:%d", info->icount.rxlong);
3479                if (info->icount.rxover)
3480                        seq_printf(m, " rxover:%d", info->icount.rxover);
3481                if (info->icount.rxcrc)
3482                        seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
3483        } else {
3484                seq_printf(m, " ASYNC tx:%d rx:%d",
3485                              info->icount.tx, info->icount.rx);
3486                if (info->icount.frame)
3487                        seq_printf(m, " fe:%d", info->icount.frame);
3488                if (info->icount.parity)
3489                        seq_printf(m, " pe:%d", info->icount.parity);
3490                if (info->icount.brk)
3491                        seq_printf(m, " brk:%d", info->icount.brk);
3492                if (info->icount.overrun)
3493                        seq_printf(m, " oe:%d", info->icount.overrun);
3494        }
3495        
3496        /* Append serial signal status to end */
3497        seq_printf(m, " %s\n", stat_buf+1);
3498        
3499        seq_printf(m, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
3500         info->tx_active,info->bh_requested,info->bh_running,
3501         info->pending_bh);
3502         
3503        spin_lock_irqsave(&info->irq_spinlock,flags);
3504        {       
3505        u16 Tcsr = usc_InReg( info, TCSR );
3506        u16 Tdmr = usc_InDmaReg( info, TDMR );
3507        u16 Ticr = usc_InReg( info, TICR );
3508        u16 Rscr = usc_InReg( info, RCSR );
3509        u16 Rdmr = usc_InDmaReg( info, RDMR );
3510        u16 Ricr = usc_InReg( info, RICR );
3511        u16 Icr = usc_InReg( info, ICR );
3512        u16 Dccr = usc_InReg( info, DCCR );
3513        u16 Tmr = usc_InReg( info, TMR );
3514        u16 Tccr = usc_InReg( info, TCCR );
3515        u16 Ccar = inw( info->io_base + CCAR );
3516        seq_printf(m, "tcsr=%04X tdmr=%04X ticr=%04X rcsr=%04X rdmr=%04X\n"
3517                        "ricr=%04X icr =%04X dccr=%04X tmr=%04X tccr=%04X ccar=%04X\n",
3518                        Tcsr,Tdmr,Ticr,Rscr,Rdmr,Ricr,Icr,Dccr,Tmr,Tccr,Ccar );
3519        }
3520        spin_unlock_irqrestore(&info->irq_spinlock,flags);
3521}
3522
3523/* Called to print information about devices */
3524static int mgsl_proc_show(struct seq_file *m, void *v)
3525{
3526        struct mgsl_struct *info;
3527        
3528        seq_printf(m, "synclink driver:%s\n", driver_version);
3529        
3530        info = mgsl_device_list;
3531        while( info ) {
3532                line_info(m, info);
3533                info = info->next_device;
3534        }
3535        return 0;
3536}
3537
3538static int mgsl_proc_open(struct inode *inode, struct file *file)
3539{
3540        return single_open(file, mgsl_proc_show, NULL);
3541}
3542
3543static const struct file_operations mgsl_proc_fops = {
3544        .owner          = THIS_MODULE,
3545        .open           = mgsl_proc_open,
3546        .read           = seq_read,
3547        .llseek         = seq_lseek,
3548        .release        = single_release,
3549};
3550
3551/* mgsl_allocate_dma_buffers()
3552 * 
3553 *      Allocate and format DMA buffers (ISA adapter)
3554 *      or format shared memory buffers (PCI adapter).
3555 * 
3556 * Arguments:           info    pointer to device instance data
3557 * Return Value:        0 if success, otherwise error
3558 */
3559static int mgsl_allocate_dma_buffers(struct mgsl_struct *info)
3560{
3561        unsigned short BuffersPerFrame;
3562
3563        info->last_mem_alloc = 0;
3564
3565        /* Calculate the number of DMA buffers necessary to hold the */
3566        /* largest allowable frame size. Note: If the max frame size is */
3567        /* not an even multiple of the DMA buffer size then we need to */
3568        /* round the buffer count per frame up one. */
3569
3570        BuffersPerFrame = (unsigned short)(info->max_frame_size/DMABUFFERSIZE);
3571        if ( info->max_frame_size % DMABUFFERSIZE )
3572                BuffersPerFrame++;
3573
3574        if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3575                /*
3576                 * The PCI adapter has 256KBytes of shared memory to use.
3577                 * This is 64 PAGE_SIZE buffers.
3578                 *
3579                 * The first page is used for padding at this time so the
3580                 * buffer list does not begin at offset 0 of the PCI
3581                 * adapter's shared memory.
3582                 *
3583                 * The 2nd page is used for the buffer list. A 4K buffer
3584                 * list can hold 128 DMA_BUFFER structures at 32 bytes
3585                 * each.
3586                 *
3587                 * This leaves 62 4K pages.
3588                 *
3589                 * The next N pages are used for transmit frame(s). We
3590                 * reserve enough 4K page blocks to hold the required
3591                 * number of transmit dma buffers (num_tx_dma_buffers),
3592                 * each of MaxFrameSize size.
3593                 *
3594                 * Of the remaining pages (62-N), determine how many can
3595                 * be used to receive full MaxFrameSize inbound frames
3596                 */
3597                info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame;
3598                info->rx_buffer_count = 62 - info->tx_buffer_count;
3599        } else {
3600                /* Calculate the number of PAGE_SIZE buffers needed for */
3601                /* receive and transmit DMA buffers. */
3602
3603
3604                /* Calculate the number of DMA buffers necessary to */
3605                /* hold 7 max size receive frames and one max size transmit frame. */
3606                /* The receive buffer count is bumped by one so we avoid an */
3607                /* End of List condition if all receive buffers are used when */
3608                /* using linked list DMA buffers. */
3609
3610                info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame;
3611                info->rx_buffer_count = (BuffersPerFrame * MAXRXFRAMES) + 6;
3612                
3613                /* 
3614                 * limit total TxBuffers & RxBuffers to 62 4K total 
3615                 * (ala PCI Allocation) 
3616                 */
3617                
3618                if ( (info->tx_buffer_count + info->rx_buffer_count) > 62 )
3619                        info->rx_buffer_count = 62 - info->tx_buffer_count;
3620
3621        }
3622
3623        if ( debug_level >= DEBUG_LEVEL_INFO )
3624                printk("%s(%d):Allocating %d TX and %d RX DMA buffers.\n",
3625                        __FILE__,__LINE__, info->tx_buffer_count,info->rx_buffer_count);
3626        
3627        if ( mgsl_alloc_buffer_list_memory( info ) < 0 ||
3628                  mgsl_alloc_frame_memory(info, info->rx_buffer_list, info->rx_buffer_count) < 0 || 
3629                  mgsl_alloc_frame_memory(info, info->tx_buffer_list, info->tx_buffer_count) < 0 || 
3630                  mgsl_alloc_intermediate_rxbuffer_memory(info) < 0  ||
3631                  mgsl_alloc_intermediate_txbuffer_memory(info) < 0 ) {
3632                printk("%s(%d):Can't allocate DMA buffer memory\n",__FILE__,__LINE__);
3633                return -ENOMEM;
3634        }
3635        
3636        mgsl_reset_rx_dma_buffers( info );
3637        mgsl_reset_tx_dma_buffers( info );
3638
3639        return 0;
3640
3641}       /* end of mgsl_allocate_dma_buffers() */
3642
3643/*
3644 * mgsl_alloc_buffer_list_memory()
3645 * 
3646 * Allocate a common DMA buffer for use as the
3647 * receive and transmit buffer lists.
3648 * 
3649 * A buffer list is a set of buffer entries where each entry contains
3650 * a pointer to an actual buffer and a pointer to the next buffer entry
3651 * (plus some other info about the buffer).
3652 * 
3653 * The buffer entries for a list are built to form a circular list so
3654 * that when the entire list has been traversed you start back at the
3655 * beginning.
3656 * 
3657 * This function allocates memory for just the buffer entries.
3658 * The links (pointer to next entry) are filled in with the physical
3659 * address of the next entry so the adapter can navigate the list
3660 * using bus master DMA. The pointers to the actual buffers are filled
3661 * out later when the actual buffers are allocated.
3662 * 
3663 * Arguments:           info    pointer to device instance data
3664 * Return Value:        0 if success, otherwise error
3665 */
3666static int mgsl_alloc_buffer_list_memory( struct mgsl_struct *info )
3667{
3668        unsigned int i;
3669
3670        if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3671                /* PCI adapter uses shared memory. */
3672                info->buffer_list = info->memory_base + info->last_mem_alloc;
3673                info->buffer_list_phys = info->last_mem_alloc;
3674                info->last_mem_alloc += BUFFERLISTSIZE;
3675        } else {
3676                /* ISA adapter uses system memory. */
3677                /* The buffer lists are allocated as a common buffer that both */
3678                /* the processor and adapter can access. This allows the driver to */
3679                /* inspect portions of the buffer while other portions are being */
3680                /* updated by the adapter using Bus Master DMA. */
3681
3682                info->buffer_list = dma_alloc_coherent(NULL, BUFFERLISTSIZE, &info->buffer_list_dma_addr, GFP_KERNEL);
3683                if (info->buffer_list == NULL)
3684                        return -ENOMEM;
3685                info->buffer_list_phys = (u32)(info->buffer_list_dma_addr);
3686        }
3687
3688        /* We got the memory for the buffer entry lists. */
3689        /* Initialize the memory block to all zeros. */
3690        memset( info->buffer_list, 0, BUFFERLISTSIZE );
3691
3692        /* Save virtual address pointers to the receive and */
3693        /* transmit buffer lists. (Receive 1st). These pointers will */
3694        /* be used by the processor to access the lists. */
3695        info->rx_buffer_list = (DMABUFFERENTRY *)info->buffer_list;
3696        info->tx_buffer_list = (DMABUFFERENTRY *)info->buffer_list;
3697        info->tx_buffer_list += info->rx_buffer_count;
3698
3699        /*
3700         * Build the links for the buffer entry lists such that
3701         * two circular lists are built. (Transmit and Receive).
3702         *
3703         * Note: the links are physical addresses
3704         * which are read by the adapter to determine the next
3705         * buffer entry to use.
3706         */
3707
3708        for ( i = 0; i < info->rx_buffer_count; i++ ) {
3709                /* calculate and store physical address of this buffer entry */
3710                info->rx_buffer_list[i].phys_entry =
3711                        info->buffer_list_phys + (i * sizeof(DMABUFFERENTRY));
3712
3713                /* calculate and store physical address of */
3714                /* next entry in cirular list of entries */
3715
3716                info->rx_buffer_list[i].link = info->buffer_list_phys;
3717
3718                if ( i < info->rx_buffer_count - 1 )
3719                        info->rx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY);
3720        }
3721
3722        for ( i = 0; i < info->tx_buffer_count; i++ ) {
3723                /* calculate and store physical address of this buffer entry */
3724                info->tx_buffer_list[i].phys_entry = info->buffer_list_phys +
3725                        ((info->rx_buffer_count + i) * sizeof(DMABUFFERENTRY));
3726
3727                /* calculate and store physical address of */
3728                /* next entry in cirular list of entries */
3729
3730                info->tx_buffer_list[i].link = info->buffer_list_phys +
3731                        info->rx_buffer_count * sizeof(DMABUFFERENTRY);
3732
3733                if ( i < info->tx_buffer_count - 1 )
3734                        info->tx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY);
3735        }
3736
3737        return 0;
3738
3739}       /* end of mgsl_alloc_buffer_list_memory() */
3740
3741/* Free DMA buffers allocated for use as the
3742 * receive and transmit buffer lists.
3743 * Warning:
3744 * 
3745 *      The data transfer buffers associated with the buffer list
3746 *      MUST be freed before freeing the buffer list itself because
3747 *      the buffer list contains the information necessary to free
3748 *      the individual buffers!
3749 */
3750static void mgsl_free_buffer_list_memory( struct mgsl_struct *info )
3751{
3752        if (info->buffer_list && info->bus_type != MGSL_BUS_TYPE_PCI)
3753                dma_free_coherent(NULL, BUFFERLISTSIZE, info->buffer_list, info->buffer_list_dma_addr);
3754                
3755        info->buffer_list = NULL;
3756        info->rx_buffer_list = NULL;
3757        info->tx_buffer_list = NULL;
3758
3759}       /* end of mgsl_free_buffer_list_memory() */
3760
3761/*
3762 * mgsl_alloc_frame_memory()
3763 * 
3764 *      Allocate the frame DMA buffers used by the specified buffer list.
3765 *      Each DMA buffer will be one memory page in size. This is necessary
3766 *      because memory can fragment enough that it may be impossible
3767 *      contiguous pages.
3768 * 
3769 * Arguments:
3770 * 
3771 *      info            pointer to device instance data
3772 *      BufferList      pointer to list of buffer entries
3773 *      Buffercount     count of buffer entries in buffer list
3774 * 
3775 * Return Value:        0 if success, otherwise -ENOMEM
3776 */
3777static int mgsl_alloc_frame_memory(struct mgsl_struct *info,DMABUFFERENTRY *BufferList,int Buffercount)
3778{
3779        int i;
3780        u32 phys_addr;
3781
3782        /* Allocate page sized buffers for the receive buffer list */
3783
3784        for ( i = 0; i < Buffercount; i++ ) {
3785                if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3786                        /* PCI adapter uses shared memory buffers. */
3787                        BufferList[i].virt_addr = info->memory_base + info->last_mem_alloc;
3788                        phys_addr = info->last_mem_alloc;
3789                        info->last_mem_alloc += DMABUFFERSIZE;
3790                } else {
3791                        /* ISA adapter uses system memory. */
3792                        BufferList[i].virt_addr = dma_alloc_coherent(NULL, DMABUFFERSIZE, &BufferList[i].dma_addr, GFP_KERNEL);
3793                        if (BufferList[i].virt_addr == NULL)
3794                                return -ENOMEM;
3795                        phys_addr = (u32)(BufferList[i].dma_addr);
3796                }
3797                BufferList[i].phys_addr = phys_addr;
3798        }
3799
3800        return 0;
3801
3802}       /* end of mgsl_alloc_frame_memory() */
3803
3804/*
3805 * mgsl_free_frame_memory()
3806 * 
3807 *      Free the buffers associated with
3808 *      each buffer entry of a buffer list.
3809 * 
3810 * Arguments:
3811 * 
3812 *      info            pointer to device instance data
3813 *      BufferList      pointer to list of buffer entries
3814 *      Buffercount     count of buffer entries in buffer list
3815 * 
3816 * Return Value:        None
3817 */
3818static void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList, int Buffercount)
3819{
3820        int i;
3821
3822        if ( BufferList ) {
3823                for ( i = 0 ; i < Buffercount ; i++ ) {
3824                        if ( BufferList[i].virt_addr ) {
3825                                if ( info->bus_type != MGSL_BUS_TYPE_PCI )
3826                                        dma_free_coherent(NULL, DMABUFFERSIZE, BufferList[i].virt_addr, BufferList[i].dma_addr);
3827                                BufferList[i].virt_addr = NULL;
3828                        }
3829                }
3830        }
3831
3832}       /* end of mgsl_free_frame_memory() */
3833
3834/* mgsl_free_dma_buffers()
3835 * 
3836 *      Free DMA buffers
3837 *      
3838 * Arguments:           info    pointer to device instance data
3839 * Return Value:        None
3840 */
3841static void mgsl_free_dma_buffers( struct mgsl_struct *info )
3842{
3843        mgsl_free_frame_memory( info, info->rx_buffer_list, info->rx_buffer_count );
3844        mgsl_free_frame_memory( info, info->tx_buffer_list, info->tx_buffer_count );
3845        mgsl_free_buffer_list_memory( info );
3846
3847}       /* end of mgsl_free_dma_buffers() */
3848
3849
3850/*
3851 * mgsl_alloc_intermediate_rxbuffer_memory()
3852 * 
3853 *      Allocate a buffer large enough to hold max_frame_size. This buffer
3854 *      is used to pass an assembled frame to the line discipline.
3855 * 
3856 * Arguments:
3857 * 
3858 *      info            pointer to device instance data
3859 * 
3860 * Return Value:        0 if success, otherwise -ENOMEM
3861 */
3862static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info)
3863{
3864        info->intermediate_rxbuffer = kmalloc(info->max_frame_size, GFP_KERNEL | GFP_DMA);
3865        if ( info->intermediate_rxbuffer == NULL )
3866                return -ENOMEM;
3867        /* unused flag buffer to satisfy receive_buf calling interface */
3868        info->flag_buf = kzalloc(info->max_frame_size, GFP_KERNEL);
3869        if (!info->flag_buf) {
3870                kfree(info->intermediate_rxbuffer);
3871                info->intermediate_rxbuffer = NULL;
3872                return -ENOMEM;
3873        }
3874        return 0;
3875
3876}       /* end of mgsl_alloc_intermediate_rxbuffer_memory() */
3877
3878/*
3879 * mgsl_free_intermediate_rxbuffer_memory()
3880 * 
3881 * 
3882 * Arguments:
3883 * 
3884 *      info            pointer to device instance data
3885 * 
3886 * Return Value:        None
3887 */
3888static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info)
3889{
3890        kfree(info->intermediate_rxbuffer);
3891        info->intermediate_rxbuffer = NULL;
3892        kfree(info->flag_buf);
3893        info->flag_buf = NULL;
3894
3895}       /* end of mgsl_free_intermediate_rxbuffer_memory() */
3896
3897/*
3898 * mgsl_alloc_intermediate_txbuffer_memory()
3899 *
3900 *      Allocate intermdiate transmit buffer(s) large enough to hold max_frame_size.
3901 *      This buffer is used to load transmit frames into the adapter's dma transfer
3902 *      buffers when there is sufficient space.
3903 *
3904 * Arguments:
3905 *
3906 *      info            pointer to device instance data
3907 *
3908 * Return Value:        0 if success, otherwise -ENOMEM
3909 */
3910static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info)
3911{
3912        int i;
3913
3914        if ( debug_level >= DEBUG_LEVEL_INFO )
3915                printk("%s %s(%d)  allocating %d tx holding buffers\n",
3916                                info->device_name, __FILE__,__LINE__,info->num_tx_holding_buffers);
3917
3918        memset(info->tx_holding_buffers,0,sizeof(info->tx_holding_buffers));
3919
3920        for ( i=0; i<info->num_tx_holding_buffers; ++i) {
3921                info->tx_holding_buffers[i].buffer =
3922                        kmalloc(info->max_frame_size, GFP_KERNEL);
3923                if (info->tx_holding_buffers[i].buffer == NULL) {
3924                        for (--i; i >= 0; i--) {
3925                                kfree(info->tx_holding_buffers[i].buffer);
3926                                info->tx_holding_buffers[i].buffer = NULL;
3927                        }
3928                        return -ENOMEM;
3929                }
3930        }
3931
3932        return 0;
3933
3934}       /* end of mgsl_alloc_intermediate_txbuffer_memory() */
3935
3936/*
3937 * mgsl_free_intermediate_txbuffer_memory()
3938 *
3939 *
3940 * Arguments:
3941 *
3942 *      info            pointer to device instance data
3943 *
3944 * Return Value:        None
3945 */
3946static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info)
3947{
3948        int i;
3949
3950        for ( i=0; i<info->num_tx_holding_buffers; ++i ) {
3951                kfree(info->tx_holding_buffers[i].buffer);
3952                info->tx_holding_buffers[i].buffer = NULL;
3953        }
3954
3955        info->get_tx_holding_index = 0;
3956        info->put_tx_holding_index = 0;
3957        info->tx_holding_count = 0;
3958
3959}       /* end of mgsl_free_intermediate_txbuffer_memory() */
3960
3961
3962/*
3963 * load_next_tx_holding_buffer()
3964 *
3965 * attempts to load the next buffered tx request into the
3966 * tx dma buffers
3967 *
3968 * Arguments:
3969 *
3970 *      info            pointer to device instance data
3971 *
3972 * Return Value:        true if next buffered tx request loaded
3973 *                      into adapter's tx dma buffer,
3974 *                      false otherwise
3975 */
3976static bool load_next_tx_holding_buffer(struct mgsl_struct *info)
3977{
3978        bool ret = false;
3979
3980        if ( info->tx_holding_count ) {
3981                /* determine if we have enough tx dma buffers
3982                 * to accommodate the next tx frame
3983                 */
3984                struct tx_holding_buffer *ptx =
3985                        &info->tx_holding_buffers[info->get_tx_holding_index];
3986                int num_free = num_free_tx_dma_buffers(info);
3987                int num_needed = ptx->buffer_size / DMABUFFERSIZE;
3988                if ( ptx->buffer_size % DMABUFFERSIZE )
3989                        ++num_needed;
3990
3991                if (num_needed <= num_free) {
3992                        info->xmit_cnt = ptx->buffer_size;
3993                        mgsl_load_tx_dma_buffer(info,ptx->buffer,ptx->buffer_size);
3994
3995                        --info->tx_holding_count;
3996                        if ( ++info->get_tx_holding_index >= info->num_tx_holding_buffers)
3997                                info->get_tx_holding_index=0;
3998
3999                        /* restart transmit timer */
4000                        mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(5000));
4001
4002                        ret = true;
4003                }
4004        }
4005
4006        return ret;
4007}
4008
4009/*
4010 * save_tx_buffer_request()
4011 *
4012 * attempt to store transmit frame request for later transmission
4013 *
4014 * Arguments:
4015 *
4016 *      info            pointer to device instance data
4017 *      Buffer          pointer to buffer containing frame to load
4018 *      BufferSize      size in bytes of frame in Buffer
4019 *
4020 * Return Value:        1 if able to store, 0 otherwise
4021 */
4022static int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize)
4023{
4024        struct tx_holding_buffer *ptx;
4025
4026        if ( info->tx_holding_count >= info->num_tx_holding_buffers ) {
4027                return 0;               /* all buffers in use */
4028        }
4029
4030        ptx = &info->tx_holding_buffers[info->put_tx_holding_index];
4031        ptx->buffer_size = BufferSize;
4032        memcpy( ptx->buffer, Buffer, BufferSize);
4033
4034        ++info->tx_holding_count;
4035        if ( ++info->put_tx_holding_index >= info->num_tx_holding_buffers)
4036                info->put_tx_holding_index=0;
4037
4038        return 1;
4039}
4040
4041static int mgsl_claim_resources(struct mgsl_struct *info)
4042{
4043        if (request_region(info->io_base,info->io_addr_size,"synclink") == NULL) {
4044                printk( "%s(%d):I/O address conflict on device %s Addr=%08X\n",
4045                        __FILE__,__LINE__,info->device_name, info->io_base);
4046                return -ENODEV;
4047        }
4048        info->io_addr_requested = true;
4049        
4050        if ( request_irq(info->irq_level,mgsl_interrupt,info->irq_flags,
4051                info->device_name, info ) < 0 ) {
4052                printk( "%s(%d):Can't request interrupt on device %s IRQ=%d\n",
4053                        __FILE__,__LINE__,info->device_name, info->irq_level );
4054                goto errout;
4055        }
4056        info->irq_requested = true;
4057        
4058        if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
4059                if (request_mem_region(info->phys_memory_base,0x40000,"synclink") == NULL) {
4060                        printk( "%s(%d):mem addr conflict device %s Addr=%08X\n",
4061                                __FILE__,__LINE__,info->device_name, info->phys_memory_base);
4062                        goto errout;
4063                }
4064                info->shared_mem_requested = true;
4065                if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclink") == NULL) {
4066                        printk( "%s(%d):lcr mem addr conflict device %s Addr=%08X\n",
4067                                __FILE__,__LINE__,info->device_name, info->phys_lcr_base + info->lcr_offset);
4068                        goto errout;
4069                }
4070                info->lcr_mem_requested = true;
4071
4072                info->memory_base = ioremap_nocache(info->phys_memory_base,
4073                                                                0x40000);
4074                if (!info->memory_base) {
4075                        printk( "%s(%d):Can't map shared memory on device %s MemAddr=%08X\n",
4076                                __FILE__,__LINE__,info->device_name, info->phys_memory_base );
4077                        goto errout;
4078                }
4079                
4080                if ( !mgsl_memory_test(info) ) {
4081                        printk( "%s(%d):Failed shared memory test %s MemAddr=%08X\n",
4082                                __FILE__,__LINE__,info->device_name, info->phys_memory_base );
4083                        goto errout;
4084                }
4085                
4086                info->lcr_base = ioremap_nocache(info->phys_lcr_base,
4087                                                                PAGE_SIZE);
4088                if (!info->lcr_base) {
4089                        printk( "%s(%d):Can't map LCR memory on device %s MemAddr=%08X\n",
4090                                __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
4091                        goto errout;
4092                }
4093                info->lcr_base += info->lcr_offset;
4094                
4095        } else {
4096                /* claim DMA channel */
4097                
4098                if (request_dma(info->dma_level,info->device_name) < 0){
4099                        printk( "%s(%d):Can't request DMA channel on device %s DMA=%d\n",
4100                                __FILE__,__LINE__,info->device_name, info->dma_level );
4101                        mgsl_release_resources( info );
4102                        return -ENODEV;
4103                }
4104                info->dma_requested = true;
4105
4106                /* ISA adapter uses bus master DMA */           
4107                set_dma_mode(info->dma_level,DMA_MODE_CASCADE);
4108                enable_dma(info->dma_level);
4109        }
4110        
4111        if ( mgsl_allocate_dma_buffers(info) < 0 ) {
4112                printk( "%s(%d):Can't allocate DMA buffers on device %s DMA=%d\n",
4113                        __FILE__,__LINE__,info->device_name, info->dma_level );
4114                goto errout;
4115        }       
4116        
4117        return 0;
4118errout:
4119        mgsl_release_resources(info);
4120        return -ENODEV;
4121
4122}       /* end of mgsl_claim_resources() */
4123
4124static void mgsl_release_resources(struct mgsl_struct *info)
4125{
4126        if ( debug_level >= DEBUG_LEVEL_INFO )
4127                printk( "%s(%d):mgsl_release_resources(%s) entry\n",
4128                        __FILE__,__LINE__,info->device_name );
4129                        
4130        if ( info->irq_requested ) {
4131                free_irq(info->irq_level, info);
4132                info->irq_requested = false;
4133        }
4134        if ( info->dma_requested ) {
4135                disable_dma(info->dma_level);
4136                free_dma(info->dma_level);
4137                info->dma_requested = false;
4138        }
4139        mgsl_free_dma_buffers(info);
4140        mgsl_free_intermediate_rxbuffer_memory(info);
4141        mgsl_free_intermediate_txbuffer_memory(info);
4142        
4143        if ( info->io_addr_requested ) {
4144                release_region(info->io_base,info->io_addr_size);
4145                info->io_addr_requested = false;
4146        }
4147        if ( info->shared_mem_requested ) {
4148                release_mem_region(info->phys_memory_base,0x40000);
4149                info->shared_mem_requested = false;
4150        }
4151        if ( info->lcr_mem_requested ) {
4152                release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
4153                info->lcr_mem_requested = false;
4154        }
4155        if (info->memory_base){
4156                iounmap(info->memory_base);
4157                info->memory_base = NULL;
4158        }
4159        if (info->lcr_base){
4160                iounmap(info->lcr_base - info->lcr_offset);
4161                info->lcr_base = NULL;
4162        }
4163        
4164        if ( debug_level >= DEBUG_LEVEL_INFO )
4165                printk( "%s(%d):mgsl_release_resources(%s) exit\n",
4166                        __FILE__,__LINE__,info->device_name );
4167                        
4168}       /* end of mgsl_release_resources() */
4169
4170/* mgsl_add_device()
4171 * 
4172 *      Add the specified device instance data structure to the
4173 *      global linked list of devices and increment the device count.
4174 *      
4175 * Arguments:           info    pointer to device instance data
4176 * Return Value:        None
4177 */
4178static void mgsl_add_device( struct mgsl_struct *info )
4179{
4180        info->next_device = NULL;
4181        info->line = mgsl_device_count;
4182        sprintf(info->device_name,"ttySL%d",info->line);
4183        
4184        if (info->line < MAX_TOTAL_DEVICES) {
4185                if (maxframe[info->line])
4186                        info->max_frame_size = maxframe[info->line];
4187
4188                if (txdmabufs[info->line]) {
4189                        info->num_tx_dma_buffers = txdmabufs[info->line];
4190                        if (info->num_tx_dma_buffers < 1)
4191                                info->num_tx_dma_buffers = 1;
4192                }
4193
4194                if (txholdbufs[info->line]) {
4195                        info->num_tx_holding_buffers = txholdbufs[info->line];
4196                        if (info->num_tx_holding_buffers < 1)
4197                                info->num_tx_holding_buffers = 1;
4198                        else if (info->num_tx_holding_buffers > MAX_TX_HOLDING_BUFFERS)
4199                                info->num_tx_holding_buffers = MAX_TX_HOLDING_BUFFERS;
4200                }
4201        }
4202
4203        mgsl_device_count++;
4204        
4205        if ( !mgsl_device_list )
4206                mgsl_device_list = info;
4207        else {  
4208                struct mgsl_struct *current_dev = mgsl_device_list;
4209                while( current_dev->next_device )
4210                        current_dev = current_dev->next_device;
4211                current_dev->next_device = info;
4212        }
4213        
4214        if ( info->max_frame_size < 4096 )
4215                info->max_frame_size = 4096;
4216        else if ( info->max_frame_size > 65535 )
4217                info->max_frame_size = 65535;
4218        
4219        if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
4220                printk( "SyncLink PCI v%d %s: IO=%04X IRQ=%d Mem=%08X,%08X MaxFrameSize=%u\n",
4221                        info->hw_version + 1, info->device_name, info->io_base, info->irq_level,
4222                        info->phys_memory_base, info->phys_lcr_base,
4223                        info->max_frame_size );
4224        } else {
4225                printk( "SyncLink ISA %s: IO=%04X IRQ=%d DMA=%d MaxFrameSize=%u\n",
4226                        info->device_name, info->io_base, info->irq_level, info->dma_level,
4227                        info->max_frame_size );
4228        }
4229
4230#if SYNCLINK_GENERIC_HDLC
4231        hdlcdev_init(info);
4232#endif
4233
4234}       /* end of mgsl_add_device() */
4235
4236static const struct tty_port_operations mgsl_port_ops = {
4237        .carrier_raised = carrier_raised,
4238        .dtr_rts = dtr_rts,
4239};
4240
4241
4242/* mgsl_allocate_device()
4243 * 
4244 *      Allocate and initialize a device instance structure
4245 *      
4246 * Arguments:           none
4247 * Return Value:        pointer to mgsl_struct if success, otherwise NULL
4248 */
4249static struct mgsl_struct* mgsl_allocate_device(void)
4250{
4251        struct mgsl_struct *info;
4252        
4253        info = kzalloc(sizeof(struct mgsl_struct),
4254                 GFP_KERNEL);
4255                 
4256        if (!info) {
4257                printk("Error can't allocate device instance data\n");
4258        } else {
4259                tty_port_init(&info->port);
4260                info->port.ops = &mgsl_port_ops;
4261                info->magic = MGSL_MAGIC;
4262                INIT_WORK(&info->task, mgsl_bh_handler);
4263                info->max_frame_size = 4096;
4264                info->port.close_delay = 5*HZ/10;
4265                info->port.closing_wait = 30*HZ;
4266                init_waitqueue_head(&info->status_event_wait_q);
4267                init_waitqueue_head(&info->event_wait_q);
4268                spin_lock_init(&info->irq_spinlock);
4269                spin_lock_init(&info->netlock);
4270                memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
4271                info->idle_mode = HDLC_TXIDLE_FLAGS;
4272                info->num_tx_dma_buffers = 1;
4273                info->num_tx_holding_buffers = 0;
4274        }
4275        
4276        return info;
4277
4278}       /* end of mgsl_allocate_device()*/
4279
4280static const struct tty_operations mgsl_ops = {
4281        .install = mgsl_install,
4282        .open = mgsl_open,
4283        .close = mgsl_close,
4284        .write = mgsl_write,
4285        .put_char = mgsl_put_char,
4286        .flush_chars = mgsl_flush_chars,
4287        .write_room = mgsl_write_room,
4288        .chars_in_buffer = mgsl_chars_in_buffer,
4289        .flush_buffer = mgsl_flush_buffer,
4290        .ioctl = mgsl_ioctl,
4291        .throttle = mgsl_throttle,
4292        .unthrottle = mgsl_unthrottle,
4293        .send_xchar = mgsl_send_xchar,
4294        .break_ctl = mgsl_break,
4295        .wait_until_sent = mgsl_wait_until_sent,
4296        .set_termios = mgsl_set_termios,
4297        .stop = mgsl_stop,
4298        .start = mgsl_start,
4299        .hangup = mgsl_hangup,
4300        .tiocmget = tiocmget,
4301        .tiocmset = tiocmset,
4302        .get_icount = msgl_get_icount,
4303        .proc_fops = &mgsl_proc_fops,
4304};
4305
4306/*
4307 * perform tty device initialization
4308 */
4309static int mgsl_init_tty(void)
4310{
4311        int rc;
4312
4313        serial_driver = alloc_tty_driver(128);
4314        if (!serial_driver)
4315                return -ENOMEM;
4316        
4317        serial_driver->driver_name = "synclink";
4318        serial_driver->name = "ttySL";
4319        serial_driver->major = ttymajor;
4320        serial_driver->minor_start = 64;
4321        serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
4322        serial_driver->subtype = SERIAL_TYPE_NORMAL;
4323        serial_driver->init_termios = tty_std_termios;
4324        serial_driver->init_termios.c_cflag =
4325                B9600 | CS8 | CREAD | HUPCL | CLOCAL;
4326        serial_driver->init_termios.c_ispeed = 9600;
4327        serial_driver->init_termios.c_ospeed = 9600;
4328        serial_driver->flags = TTY_DRIVER_REAL_RAW;
4329        tty_set_operations(serial_driver, &mgsl_ops);
4330        if ((rc = tty_register_driver(serial_driver)) < 0) {
4331                printk("%s(%d):Couldn't register serial driver\n",
4332                        __FILE__,__LINE__);
4333                put_tty_driver(serial_driver);
4334                serial_driver = NULL;
4335                return rc;
4336        }
4337                        
4338        printk("%s %s, tty major#%d\n",
4339                driver_name, driver_version,
4340                serial_driver->major);
4341        return 0;
4342}
4343
4344/* enumerate user specified ISA adapters
4345 */
4346static void mgsl_enum_isa_devices(void)
4347{
4348        struct mgsl_struct *info;
4349        int i;
4350                
4351        /* Check for user specified ISA devices */
4352        
4353        for (i=0 ;(i < MAX_ISA_DEVICES) && io[i] && irq[i]; i++){
4354                if ( debug_level >= DEBUG_LEVEL_INFO )
4355                        printk("ISA device specified io=%04X,irq=%d,dma=%d\n",
4356                                io[i], irq[i], dma[i] );
4357                
4358                info = mgsl_allocate_device();
4359                if ( !info ) {
4360                        /* error allocating device instance data */
4361                        if ( debug_level >= DEBUG_LEVEL_ERROR )
4362                                printk( "can't allocate device instance data.\n");
4363                        continue;
4364                }
4365                
4366                /* Copy user configuration info to device instance data */
4367                info->io_base = (unsigned int)io[i];
4368                info->irq_level = (unsigned int)irq[i];
4369                info->irq_level = irq_canonicalize(info->irq_level);
4370                info->dma_level = (unsigned int)dma[i];
4371                info->bus_type = MGSL_BUS_TYPE_ISA;
4372                info->io_addr_size = 16;
4373                info->irq_flags = 0;
4374                
4375                mgsl_add_device( info );
4376        }
4377}
4378
4379static void synclink_cleanup(void)
4380{
4381        int rc;
4382        struct mgsl_struct *info;
4383        struct mgsl_struct *tmp;
4384
4385        printk("Unloading %s: %s\n", driver_name, driver_version);
4386
4387        if (serial_driver) {
4388                rc = tty_unregister_driver(serial_driver);
4389                if (rc)
4390                        printk("%s(%d) failed to unregister tty driver err=%d\n",
4391                               __FILE__,__LINE__,rc);
4392                put_tty_driver(serial_driver);
4393        }
4394
4395        info = mgsl_device_list;
4396        while(info) {
4397#if SYNCLINK_GENERIC_HDLC
4398                hdlcdev_exit(info);
4399#endif
4400                mgsl_release_resources(info);
4401                tmp = info;
4402                info = info->next_device;
4403                tty_port_destroy(&tmp->port);
4404                kfree(tmp);
4405        }
4406        
4407        if (pci_registered)
4408                pci_unregister_driver(&synclink_pci_driver);
4409}
4410
4411static int __init synclink_init(void)
4412{
4413        int rc;
4414
4415        if (break_on_load) {
4416                mgsl_get_text_ptr();
4417                BREAKPOINT();
4418        }
4419
4420        printk("%s %s\n", driver_name, driver_version);
4421
4422        mgsl_enum_isa_devices();
4423        if ((rc = pci_register_driver(&synclink_pci_driver)) < 0)
4424                printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
4425        else
4426                pci_registered = true;
4427
4428        if ((rc = mgsl_init_tty()) < 0)
4429                goto error;
4430
4431        return 0;
4432
4433error:
4434        synclink_cleanup();
4435        return rc;
4436}
4437
4438static void __exit synclink_exit(void)
4439{
4440        synclink_cleanup();
4441}
4442
4443module_init(synclink_init);
4444module_exit(synclink_exit);
4445
4446/*
4447 * usc_RTCmd()
4448 *
4449 * Issue a USC Receive/Transmit command to the
4450 * Channel Command/Address Register (CCAR).
4451 *
4452 * Notes:
4453 *
4454 *    The command is encoded in the most significant 5 bits <15..11>
4455 *    of the CCAR value. Bits <10..7> of the CCAR must be preserved
4456 *    and Bits <6..0> must be written as zeros.
4457 *
4458 * Arguments:
4459 *
4460 *    info   pointer to device information structure
4461 *    Cmd    command mask (use symbolic macros)
4462 *
4463 * Return Value:
4464 *
4465 *    None
4466 */
4467static void usc_RTCmd( struct mgsl_struct *info, u16 Cmd )
4468{
4469        /* output command to CCAR in bits <15..11> */
4470        /* preserve bits <10..7>, bits <6..0> must be zero */
4471
4472        outw( Cmd + info->loopback_bits, info->io_base + CCAR );
4473
4474        /* Read to flush write to CCAR */
4475        if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4476                inw( info->io_base + CCAR );
4477
4478}       /* end of usc_RTCmd() */
4479
4480/*
4481 * usc_DmaCmd()
4482 *
4483 *    Issue a DMA command to the DMA Command/Address Register (DCAR).
4484 *
4485 * Arguments:
4486 *
4487 *    info   pointer to device information structure
4488 *    Cmd    DMA command mask (usc_DmaCmd_XX Macros)
4489 *
4490 * Return Value:
4491 *
4492 *       None
4493 */
4494static void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd )
4495{
4496        /* write command mask to DCAR */
4497        outw( Cmd + info->mbre_bit, info->io_base );
4498
4499        /* Read to flush write to DCAR */
4500        if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4501                inw( info->io_base );
4502
4503}       /* end of usc_DmaCmd() */
4504
4505/*
4506 * usc_OutDmaReg()
4507 *
4508 *    Write a 16-bit value to a USC DMA register
4509 *
4510 * Arguments:
4511 *
4512 *    info      pointer to device info structure
4513 *    RegAddr   register address (number) for write
4514 *    RegValue  16-bit value to write to register
4515 *
4516 * Return Value:
4517 *
4518 *    None
4519 *
4520 */
4521static void usc_OutDmaReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue )
4522{
4523        /* Note: The DCAR is located at the adapter base address */
4524        /* Note: must preserve state of BIT8 in DCAR */
4525
4526        outw( RegAddr + info->mbre_bit, info->io_base );
4527        outw( RegValue, info->io_base );
4528
4529        /* Read to flush write to DCAR */
4530        if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4531                inw( info->io_base );
4532
4533}       /* end of usc_OutDmaReg() */
4534 
4535/*
4536 * usc_InDmaReg()
4537 *
4538 *    Read a 16-bit value from a DMA register
4539 *
4540 * Arguments:
4541 *
4542 *    info     pointer to device info structure
4543 *    RegAddr  register address (number) to read from
4544 *
4545 * Return Value:
4546 *
4547 *    The 16-bit value read from register
4548 *
4549 */
4550static u16 usc_InDmaReg( struct mgsl_struct *info, u16 RegAddr )
4551{
4552        /* Note: The DCAR is located at the adapter base address */
4553        /* Note: must preserve state of BIT8 in DCAR */
4554
4555        outw( RegAddr + info->mbre_bit, info->io_base );
4556        return inw( info->io_base );
4557
4558}       /* end of usc_InDmaReg() */
4559
4560/*
4561 *
4562 * usc_OutReg()
4563 *
4564 *    Write a 16-bit value to a USC serial channel register 
4565 *
4566 * Arguments:
4567 *
4568 *    info      pointer to device info structure
4569 *    RegAddr   register address (number) to write to
4570 *    RegValue  16-bit value to write to register
4571 *
4572 * Return Value:
4573 *
4574 *    None
4575 *
4576 */
4577static void usc_OutReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue )
4578{
4579        outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
4580        outw( RegValue, info->io_base + CCAR );
4581
4582        /* Read to flush write to CCAR */
4583        if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4584                inw( info->io_base + CCAR );
4585
4586}       /* end of usc_OutReg() */
4587
4588/*
4589 * usc_InReg()
4590 *
4591 *    Reads a 16-bit value from a USC serial channel register
4592 *
4593 * Arguments:
4594 *
4595 *    info       pointer to device extension
4596 *    RegAddr    register address (number) to read from
4597 *
4598 * Return Value:
4599 *
4600 *    16-bit value read from register
4601 */
4602static u16 usc_InReg( struct mgsl_struct *info, u16 RegAddr )
4603{
4604        outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
4605        return inw( info->io_base + CCAR );
4606
4607}       /* end of usc_InReg() */
4608
4609/* usc_set_sdlc_mode()
4610 *
4611 *    Set up the adapter for SDLC DMA communications.
4612 *
4613 * Arguments:           info    pointer to device instance data
4614 * Return Value:        NONE
4615 */
4616static void usc_set_sdlc_mode( struct mgsl_struct *info )
4617{
4618        u16 RegValue;
4619        bool PreSL1660;
4620        
4621        /*
4622         * determine if the IUSC on the adapter is pre-SL1660. If
4623         * not, take advantage of the UnderWait feature of more
4624         * modern chips. If an underrun occurs and this bit is set,
4625         * the transmitter will idle the programmed idle pattern
4626         * until the driver has time to service the underrun. Otherwise,
4627         * the dma controller may get the cycles previously requested
4628         * and begin transmitting queued tx data.
4629         */
4630        usc_OutReg(info,TMCR,0x1f);
4631        RegValue=usc_InReg(info,TMDR);
4632        PreSL1660 = (RegValue == IUSC_PRE_SL1660);
4633
4634        if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
4635        {
4636           /*
4637           ** Channel Mode Register (CMR)
4638           **
4639           ** <15..14>    10    Tx Sub Modes, Send Flag on Underrun
4640           ** <13>        0     0 = Transmit Disabled (initially)
4641           ** <12>        0     1 = Consecutive Idles share common 0
4642           ** <11..8>     1110  Transmitter Mode = HDLC/SDLC Loop
4643           ** <7..4>      0000  Rx Sub Modes, addr/ctrl field handling
4644           ** <3..0>      0110  Receiver Mode = HDLC/SDLC
4645           **
4646           ** 1000 1110 0000 0110 = 0x8e06
4647           */
4648           RegValue = 0x8e06;
4649 
4650           /*--------------------------------------------------
4651            * ignore user options for UnderRun Actions and
4652            * preambles
4653            *--------------------------------------------------*/
4654        }
4655        else
4656        {       
4657                /* Channel mode Register (CMR)
4658                 *
4659                 * <15..14>  00    Tx Sub modes, Underrun Action
4660                 * <13>      0     1 = Send Preamble before opening flag
4661                 * <12>      0     1 = Consecutive Idles share common 0
4662                 * <11..8>   0110  Transmitter mode = HDLC/SDLC
4663                 * <7..4>    0000  Rx Sub modes, addr/ctrl field handling
4664                 * <3..0>    0110  Receiver mode = HDLC/SDLC
4665                 *
4666                 * 0000 0110 0000 0110 = 0x0606
4667                 */
4668                if (info->params.mode == MGSL_MODE_RAW) {
4669                        RegValue = 0x0001;              /* Set Receive mode = external sync */
4670
4671                        usc_OutReg( info, IOCR,         /* Set IOCR DCD is RxSync Detect Input */
4672                                (unsigned short)((usc_InReg(info, IOCR) & ~(BIT13|BIT12)) | BIT12));
4673
4674                        /*
4675                         * TxSubMode:
4676                         *      CMR <15>                0       Don't send CRC on Tx Underrun
4677                         *      CMR <14>                x       undefined
4678                         *      CMR <13>                0       Send preamble before openning sync
4679                         *      CMR <12>                0       Send 8-bit syncs, 1=send Syncs per TxLength
4680                         *
4681                         * TxMode:
4682                         *      CMR <11-8)      0100    MonoSync
4683                         *
4684                         *      0x00 0100 xxxx xxxx  04xx
4685                         */
4686                        RegValue |= 0x0400;
4687                }
4688                else {
4689
4690                RegValue = 0x0606;
4691
4692                if ( info->params.flags & HDLC_FLAG_UNDERRUN_ABORT15 )
4693                        RegValue |= BIT14;
4694                else if ( info->params.flags & HDLC_FLAG_UNDERRUN_FLAG )
4695                        RegValue |= BIT15;
4696                else if ( info->params.flags & HDLC_FLAG_UNDERRUN_CRC )
4697                        RegValue |= BIT15 | BIT14;
4698                }
4699
4700                if ( info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE )
4701                        RegValue |= BIT13;
4702        }
4703
4704        if ( info->params.mode == MGSL_MODE_HDLC &&
4705                (info->params.flags & HDLC_FLAG_SHARE_ZERO) )
4706                RegValue |= BIT12;
4707
4708        if ( info->params.addr_filter != 0xff )
4709        {
4710                /* set up receive address filtering */
4711                usc_OutReg( info, RSR, info->params.addr_filter );
4712                RegValue |= BIT4;
4713        }
4714
4715        usc_OutReg( info, CMR, RegValue );
4716        info->cmr_value = RegValue;
4717
4718        /* Receiver mode Register (RMR)
4719         *
4720         * <15..13>  000    encoding
4721         * <12..11>  00     FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4722         * <10>      1      1 = Set CRC to all 1s (use for SDLC/HDLC)
4723         * <9>       0      1 = Include Receive chars in CRC
4724         * <8>       1      1 = Use Abort/PE bit as abort indicator
4725         * <7..6>    00     Even parity
4726         * <5>       0      parity disabled
4727         * <4..2>    000    Receive Char Length = 8 bits
4728         * <1..0>    00     Disable Receiver
4729         *
4730         * 0000 0101 0000 0000 = 0x0500
4731         */
4732
4733        RegValue = 0x0500;
4734
4735        switch ( info->params.encoding ) {
4736        case HDLC_ENCODING_NRZB:               RegValue |= BIT13; break;
4737        case HDLC_ENCODING_NRZI_MARK:          RegValue |= BIT14; break;
4738        case HDLC_ENCODING_NRZI_SPACE:         RegValue |= BIT14 | BIT13; break;
4739        case HDLC_ENCODING_BIPHASE_MARK:       RegValue |= BIT15; break;
4740        case HDLC_ENCODING_BIPHASE_SPACE:      RegValue |= BIT15 | BIT13; break;
4741        case HDLC_ENCODING_BIPHASE_LEVEL:      RegValue |= BIT15 | BIT14; break;
4742        case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 | BIT14 | BIT13; break;
4743        }
4744
4745        if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_16_CCITT )
4746                RegValue |= BIT9;
4747        else if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_32_CCITT )
4748                RegValue |= ( BIT12 | BIT10 | BIT9 );
4749
4750        usc_OutReg( info, RMR, RegValue );
4751
4752        /* Set the Receive count Limit Register (RCLR) to 0xffff. */
4753        /* When an opening flag of an SDLC frame is recognized the */
4754        /* Receive Character count (RCC) is loaded with the value in */
4755        /* RCLR. The RCC is decremented for each received byte.  The */
4756        /* value of RCC is stored after the closing flag of the frame */
4757        /* allowing the frame size to be computed. */
4758
4759        usc_OutReg( info, RCLR, RCLRVALUE );
4760
4761        usc_RCmd( info, RCmd_SelectRicrdma_level );
4762
4763        /* Receive Interrupt Control Register (RICR)
4764         *
4765         * <15..8>      ?       RxFIFO DMA Request Level
4766         * <7>          0       Exited Hunt IA (Interrupt Arm)
4767         * <6>          0       Idle Received IA
4768         * <5>          0       Break/Abort IA
4769         * <4>          0       Rx Bound IA
4770         * <3>          1       Queued status reflects oldest 2 bytes in FIFO
4771         * <2>          0       Abort/PE IA
4772         * <1>          1       Rx Overrun IA
4773         * <0>          0       Select TC0 value for readback
4774         *
4775         *      0000 0000 0000 1000 = 0x000a
4776         */
4777
4778        /* Carry over the Exit Hunt and Idle Received bits */
4779        /* in case they have been armed by usc_ArmEvents.   */
4780
4781        RegValue = usc_InReg( info, RICR ) & 0xc0;
4782
4783        if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4784                usc_OutReg( info, RICR, (u16)(0x030a | RegValue) );
4785        else
4786                usc_OutReg( info, RICR, (u16)(0x140a | RegValue) );
4787
4788        /* Unlatch all Rx status bits and clear Rx status IRQ Pending */
4789
4790        usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
4791        usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
4792
4793        /* Transmit mode Register (TMR)
4794         *      
4795         * <15..13>     000     encoding
4796         * <12..11>     00      FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4797         * <10>         1       1 = Start CRC as all 1s (use for SDLC/HDLC)
4798         * <9>          0       1 = Tx CRC Enabled
4799         * <8>          0       1 = Append CRC to end of transmit frame
4800         * <7..6>       00      Transmit parity Even
4801         * <5>          0       Transmit parity Disabled
4802         * <4..2>       000     Tx Char Length = 8 bits
4803         * <1..0>       00      Disable Transmitter
4804         *
4805         *      0000 0100 0000 0000 = 0x0400
4806         */
4807
4808        RegValue = 0x0400;
4809
4810        switch ( info->params.encoding ) {
4811        case HDLC_ENCODING_NRZB:               RegValue |= BIT13; break;
4812        case HDLC_ENCODING_NRZI_MARK:          RegValue |= BIT14; break;
4813        case HDLC_ENCODING_NRZI_SPACE:         RegValue |= BIT14 | BIT13; break;
4814        case HDLC_ENCODING_BIPHASE_MARK:       RegValue |= BIT15; break;
4815        case HDLC_ENCODING_BIPHASE_SPACE:      RegValue |= BIT15 | BIT13; break;
4816        case HDLC_ENCODING_BIPHASE_LEVEL:      RegValue |= BIT15 | BIT14; break;
4817        case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 | BIT14 | BIT13; break;
4818        }
4819
4820        if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_16_CCITT )
4821                RegValue |= BIT9 | BIT8;
4822        else if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_32_CCITT )
4823                RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8);
4824
4825        usc_OutReg( info, TMR, RegValue );
4826
4827        usc_set_txidle( info );
4828
4829
4830        usc_TCmd( info, TCmd_SelectTicrdma_level );
4831
4832        /* Transmit Interrupt Control Register (TICR)
4833         *
4834         * <15..8>      ?       Transmit FIFO DMA Level
4835         * <7>          0       Present IA (Interrupt Arm)
4836         * <6>          0       Idle Sent IA
4837         * <5>          1       Abort Sent IA
4838         * <4>          1       EOF/EOM Sent IA
4839         * <3>          0       CRC Sent IA
4840         * <2>          1       1 = Wait for SW Trigger to Start Frame
4841         * <1>          1       Tx Underrun IA
4842         * <0>          0       TC0 constant on read back
4843         *
4844         *      0000 0000 0011 0110 = 0x0036
4845         */
4846
4847        if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4848                usc_OutReg( info, TICR, 0x0736 );
4849        else                                                            
4850                usc_OutReg( info, TICR, 0x1436 );
4851
4852        usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
4853        usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
4854
4855        /*
4856        ** Transmit Command/Status Register (TCSR)
4857        **
4858        ** <15..12>     0000    TCmd
4859        ** <11>         0/1     UnderWait
4860        ** <10..08>     000     TxIdle
4861        ** <7>          x       PreSent
4862        ** <6>          x       IdleSent
4863        ** <5>          x       AbortSent
4864        ** <4>          x       EOF/EOM Sent
4865        ** <3>          x       CRC Sent
4866        ** <2>          x       All Sent
4867        ** <1>          x       TxUnder
4868        ** <0>          x       TxEmpty
4869        ** 
4870        ** 0000 0000 0000 0000 = 0x0000
4871        */
4872        info->tcsr_value = 0;
4873
4874        if ( !PreSL1660 )
4875                info->tcsr_value |= TCSR_UNDERWAIT;
4876                
4877        usc_OutReg( info, TCSR, info->tcsr_value );
4878
4879        /* Clock mode Control Register (CMCR)
4880         *
4881         * <15..14>     00      counter 1 Source = Disabled
4882         * <13..12>     00      counter 0 Source = Disabled
4883         * <11..10>     11      BRG1 Input is TxC Pin
4884         * <9..8>       11      BRG0 Input is TxC Pin
4885         * <7..6>       01      DPLL Input is BRG1 Output
4886         * <5..3>       XXX     TxCLK comes from Port 0
4887         * <2..0>       XXX     RxCLK comes from Port 1
4888         *
4889         *      0000 1111 0111 0111 = 0x0f77
4890         */
4891
4892        RegValue = 0x0f40;
4893
4894        if ( info->params.flags & HDLC_FLAG_RXC_DPLL )
4895                RegValue |= 0x0003;     /* RxCLK from DPLL */
4896        else if ( info->params.flags & HDLC_FLAG_RXC_BRG )
4897                RegValue |= 0x0004;     /* RxCLK from BRG0 */
4898        else if ( info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4899                RegValue |= 0x0006;     /* RxCLK from TXC Input */
4900        else
4901                RegValue |= 0x0007;     /* RxCLK from Port1 */
4902
4903        if ( info->params.flags & HDLC_FLAG_TXC_DPLL )
4904                RegValue |= 0x0018;     /* TxCLK from DPLL */
4905        else if ( info->params.flags & HDLC_FLAG_TXC_BRG )
4906                RegValue |= 0x0020;     /* TxCLK from BRG0 */
4907        else if ( info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4908                RegValue |= 0x0038;     /* RxCLK from TXC Input */
4909        else
4910                RegValue |= 0x0030;     /* TxCLK from Port0 */
4911
4912        usc_OutReg( info, CMCR, RegValue );
4913
4914
4915        /* Hardware Configuration Register (HCR)
4916         *
4917         * <15..14>     00      CTR0 Divisor:00=32,01=16,10=8,11=4
4918         * <13>         0       CTR1DSel:0=CTR0Div determines CTR0Div
4919         * <12>         0       CVOK:0=report code violation in biphase
4920         * <11..10>     00      DPLL Divisor:00=32,01=16,10=8,11=4
4921         * <9..8>       XX      DPLL mode:00=disable,01=NRZ,10=Biphase,11=Biphase Level
4922         * <7..6>       00      reserved
4923         * <5>          0       BRG1 mode:0=continuous,1=single cycle
4924         * <4>          X       BRG1 Enable
4925         * <3..2>       00      reserved
4926         * <1>          0       BRG0 mode:0=continuous,1=single cycle
4927         * <0>          0       BRG0 Enable
4928         */
4929
4930        RegValue = 0x0000;
4931
4932        if ( info->params.flags & (HDLC_FLAG_RXC_DPLL | HDLC_FLAG_TXC_DPLL) ) {
4933                u32 XtalSpeed;
4934                u32 DpllDivisor;
4935                u16 Tc;
4936
4937                /*  DPLL is enabled. Use BRG1 to provide continuous reference clock  */
4938                /*  for DPLL. DPLL mode in HCR is dependent on the encoding used. */
4939
4940                if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4941                        XtalSpeed = 11059200;
4942                else
4943                        XtalSpeed = 14745600;
4944
4945                if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4946                        DpllDivisor = 16;
4947                        RegValue |= BIT10;
4948                }
4949                else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4950                        DpllDivisor = 8;
4951                        RegValue |= BIT11;
4952                }
4953                else
4954                        DpllDivisor = 32;
4955
4956                /*  Tc = (Xtal/Speed) - 1 */
4957                /*  If twice the remainder of (Xtal/Speed) is greater than Speed */
4958                /*  then rounding up gives a more precise time constant. Instead */
4959                /*  of rounding up and then subtracting 1 we just don't subtract */
4960                /*  the one in this case. */
4961
4962                /*--------------------------------------------------
4963                 * ejz: for DPLL mode, application should use the
4964                 * same clock speed as the partner system, even 
4965                 * though clocking is derived from the input RxData.
4966                 * In case the user uses a 0 for the clock speed,
4967                 * default to 0xffffffff and don't try to divide by
4968                 * zero
4969                 *--------------------------------------------------*/
4970                if ( info->params.clock_speed )
4971                {
4972                        Tc = (u16)((XtalSpeed/DpllDivisor)/info->params.clock_speed);
4973                        if ( !((((XtalSpeed/DpllDivisor) % info->params.clock_speed) * 2)
4974                               / info->params.clock_speed) )
4975                                Tc--;
4976                }
4977                else
4978                        Tc = -1;
4979                                  
4980
4981                /* Write 16-bit Time Constant for BRG1 */
4982                usc_OutReg( info, TC1R, Tc );
4983
4984                RegValue |= BIT4;               /* enable BRG1 */
4985
4986                switch ( info->params.encoding ) {
4987                case HDLC_ENCODING_NRZ:
4988                case HDLC_ENCODING_NRZB:
4989                case HDLC_ENCODING_NRZI_MARK:
4990                case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT8; break;
4991                case HDLC_ENCODING_BIPHASE_MARK:
4992                case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT9; break;
4993                case HDLC_ENCODING_BIPHASE_LEVEL:
4994                case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT9 | BIT8; break;
4995                }
4996        }
4997
4998        usc_OutReg( info, HCR, RegValue );
4999
5000
5001        /* Channel Control/status Register (CCSR)
5002         *
5003         * <15>         X       RCC FIFO Overflow status (RO)
5004         * <14>         X       RCC FIFO Not Empty status (RO)
5005         * <13>         0       1 = Clear RCC FIFO (WO)
5006         * <12>         X       DPLL Sync (RW)
5007         * <11>         X       DPLL 2 Missed Clocks status (RO)
5008         * <10>         X       DPLL 1 Missed Clock status (RO)
5009         * <9..8>       00      DPLL Resync on rising and falling edges (RW)
5010         * <7>          X       SDLC Loop On status (RO)
5011         * <6>          X       SDLC Loop Send status (RO)
5012         * <5>          1       Bypass counters for TxClk and RxClk (RW)
5013         * <4..2>       000     Last Char of SDLC frame has 8 bits (RW)
5014         * <1..0>       00      reserved
5015         *
5016         *      0000 0000 0010 0000 = 0x0020
5017         */
5018
5019        usc_OutReg( info, CCSR, 0x1020 );
5020
5021
5022        if ( info->params.flags & HDLC_FLAG_AUTO_CTS ) {
5023                usc_OutReg( info, SICR,
5024                            (u16)(usc_InReg(info,SICR) | SICR_CTS_INACTIVE) );
5025        }
5026        
5027
5028        /* enable Master Interrupt Enable bit (MIE) */
5029        usc_EnableMasterIrqBit( info );
5030
5031        usc_ClearIrqPendingBits( info, RECEIVE_STATUS | RECEIVE_DATA |
5032                                TRANSMIT_STATUS | TRANSMIT_DATA | MISC);
5033
5034        /* arm RCC underflow interrupt */
5035        usc_OutReg(info, SICR, (u16)(usc_InReg(info,SICR) | BIT3));
5036        usc_EnableInterrupts(info, MISC);
5037
5038        info->mbre_bit = 0;
5039        outw( 0, info->io_base );                       /* clear Master Bus Enable (DCAR) */
5040        usc_DmaCmd( info, DmaCmd_ResetAllChannels );    /* disable both DMA channels */
5041        info->mbre_bit = BIT8;
5042        outw( BIT8, info->io_base );                    /* set Master Bus Enable (DCAR) */
5043
5044        if (info->bus_type == MGSL_BUS_TYPE_ISA) {
5045                /* Enable DMAEN (Port 7, Bit 14) */
5046                /* This connects the DMA request signal to the ISA bus */
5047                usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) & ~BIT14));
5048        }
5049
5050        /* DMA Control Register (DCR)
5051         *
5052         * <15..14>     10      Priority mode = Alternating Tx/Rx
5053         *              01      Rx has priority
5054         *              00      Tx has priority
5055         *
5056         * <13>         1       Enable Priority Preempt per DCR<15..14>
5057         *                      (WARNING DCR<11..10> must be 00 when this is 1)
5058         *              0       Choose activate channel per DCR<11..10>
5059         *
5060         * <12>         0       Little Endian for Array/List
5061         * <11..10>     00      Both Channels can use each bus grant
5062         * <9..6>       0000    reserved
5063         * <5>          0       7 CLK - Minimum Bus Re-request Interval
5064         * <4>          0       1 = drive D/C and S/D pins
5065         * <3>          1       1 = Add one wait state to all DMA cycles.
5066         * <2>          0       1 = Strobe /UAS on every transfer.
5067         * <1..0>       11      Addr incrementing only affects LS24 bits
5068         *
5069         *      0110 0000 0000 1011 = 0x600b
5070         */
5071
5072        if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5073                /* PCI adapter does not need DMA wait state */
5074                usc_OutDmaReg( info, DCR, 0xa00b );
5075        }
5076        else
5077                usc_OutDmaReg( info, DCR, 0x800b );
5078
5079
5080        /* Receive DMA mode Register (RDMR)
5081         *
5082         * <15..14>     11      DMA mode = Linked List Buffer mode
5083         * <13>         1       RSBinA/L = store Rx status Block in Arrary/List entry
5084         * <12>         1       Clear count of List Entry after fetching
5085         * <11..10>     00      Address mode = Increment
5086         * <9>          1       Terminate Buffer on RxBound
5087         * <8>          0       Bus Width = 16bits
5088         * <7..0>       ?       status Bits (write as 0s)
5089         *
5090         * 1111 0010 0000 0000 = 0xf200
5091         */
5092
5093        usc_OutDmaReg( info, RDMR, 0xf200 );
5094
5095
5096        /* Transmit DMA mode Register (TDMR)
5097         *
5098         * <15..14>     11      DMA mode = Linked List Buffer mode
5099         * <13>         1       TCBinA/L = fetch Tx Control Block from List entry
5100         * <12>         1       Clear count of List Entry after fetching
5101         * <11..10>     00      Address mode = Increment
5102         * <9>          1       Terminate Buffer on end of frame
5103         * <8>          0       Bus Width = 16bits
5104         * <7..0>       ?       status Bits (Read Only so write as 0)
5105         *
5106         *      1111 0010 0000 0000 = 0xf200
5107         */
5108
5109        usc_OutDmaReg( info, TDMR, 0xf200 );
5110
5111
5112        /* DMA Interrupt Control Register (DICR)
5113         *
5114         * <15>         1       DMA Interrupt Enable
5115         * <14>         0       1 = Disable IEO from USC
5116         * <13>         0       1 = Don't provide vector during IntAck
5117         * <12>         1       1 = Include status in Vector
5118         * <10..2>      0       reserved, Must be 0s
5119         * <1>          0       1 = Rx DMA Interrupt Enabled
5120         * <0>          0       1 = Tx DMA Interrupt Enabled
5121         *
5122         *      1001 0000 0000 0000 = 0x9000
5123         */
5124
5125        usc_OutDmaReg( info, DICR, 0x9000 );
5126
5127        usc_InDmaReg( info, RDMR );             /* clear pending receive DMA IRQ bits */
5128        usc_InDmaReg( info, TDMR );             /* clear pending transmit DMA IRQ bits */
5129        usc_OutDmaReg( info, CDIR, 0x0303 );    /* clear IUS and Pending for Tx and Rx */
5130
5131        /* Channel Control Register (CCR)
5132         *
5133         * <15..14>     10      Use 32-bit Tx Control Blocks (TCBs)
5134         * <13>         0       Trigger Tx on SW Command Disabled
5135         * <12>         0       Flag Preamble Disabled
5136         * <11..10>     00      Preamble Length
5137         * <9..8>       00      Preamble Pattern
5138         * <7..6>       10      Use 32-bit Rx status Blocks (RSBs)
5139         * <5>          0       Trigger Rx on SW Command Disabled
5140         * <4..0>       0       reserved
5141         *
5142         *      1000 0000 1000 0000 = 0x8080
5143         */
5144
5145        RegValue = 0x8080;
5146
5147        switch ( info->params.preamble_length ) {
5148        case HDLC_PREAMBLE_LENGTH_16BITS: RegValue |= BIT10; break;
5149        case HDLC_PREAMBLE_LENGTH_32BITS: RegValue |= BIT11; break;
5150        case HDLC_PREAMBLE_LENGTH_64BITS: RegValue |= BIT11 | BIT10; break;
5151        }
5152
5153        switch ( info->params.preamble ) {
5154        case HDLC_PREAMBLE_PATTERN_FLAGS: RegValue |= BIT8 | BIT12; break;
5155        case HDLC_PREAMBLE_PATTERN_ONES:  RegValue |= BIT8; break;
5156        case HDLC_PREAMBLE_PATTERN_10:    RegValue |= BIT9; break;
5157        case HDLC_PREAMBLE_PATTERN_01:    RegValue |= BIT9 | BIT8; break;
5158        }
5159
5160        usc_OutReg( info, CCR, RegValue );
5161
5162
5163        /*
5164         * Burst/Dwell Control Register
5165         *
5166         * <15..8>      0x20    Maximum number of transfers per bus grant
5167         * <7..0>       0x00    Maximum number of clock cycles per bus grant
5168         */
5169
5170        if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5171                /* don't limit bus occupancy on PCI adapter */
5172                usc_OutDmaReg( info, BDCR, 0x0000 );
5173        }
5174        else
5175                usc_OutDmaReg( info, BDCR, 0x2000 );
5176
5177        usc_stop_transmitter(info);
5178        usc_stop_receiver(info);
5179        
5180}       /* end of usc_set_sdlc_mode() */
5181
5182/* usc_enable_loopback()
5183 *
5184 * Set the 16C32 for internal loopback mode.
5185 * The TxCLK and RxCLK signals are generated from the BRG0 and
5186 * the TxD is looped back to the RxD internally.
5187 *
5188 * Arguments:           info    pointer to device instance data
5189 *                      enable  1 = enable loopback, 0 = disable
5190 * Return Value:        None
5191 */
5192static void usc_enable_loopback(struct mgsl_struct *info, int enable)
5193{
5194        if (enable) {
5195                /* blank external TXD output */
5196                usc_OutReg(info,IOCR,usc_InReg(info,IOCR) | (BIT7 | BIT6));
5197        
5198                /* Clock mode Control Register (CMCR)
5199                 *
5200                 * <15..14>     00      counter 1 Disabled
5201                 * <13..12>     00      counter 0 Disabled
5202                 * <11..10>     11      BRG1 Input is TxC Pin
5203                 * <9..8>       11      BRG0 Input is TxC Pin
5204                 * <7..6>       01      DPLL Input is BRG1 Output
5205                 * <5..3>       100     TxCLK comes from BRG0
5206                 * <2..0>       100     RxCLK comes from BRG0
5207                 *
5208                 * 0000 1111 0110 0100 = 0x0f64
5209                 */
5210
5211                usc_OutReg( info, CMCR, 0x0f64 );
5212
5213                /* Write 16-bit Time Constant for BRG0 */
5214                /* use clock speed if available, otherwise use 8 for diagnostics */
5215                if (info->params.clock_speed) {
5216                        if (info->bus_type == MGSL_BUS_TYPE_PCI)
5217                                usc_OutReg(info, TC0R, (u16)((11059200/info->params.clock_speed)-1));
5218                        else
5219                                usc_OutReg(info, TC0R, (u16)((14745600/info->params.clock_speed)-1));
5220                } else
5221                        usc_OutReg(info, TC0R, (u16)8);
5222
5223                /* Hardware Configuration Register (HCR) Clear Bit 1, BRG0
5224                   mode = Continuous Set Bit 0 to enable BRG0.  */
5225                usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
5226
5227                /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5228                usc_OutReg(info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004));
5229
5230                /* set Internal Data loopback mode */
5231                info->loopback_bits = 0x300;
5232                outw( 0x0300, info->io_base + CCAR );
5233        } else {
5234                /* enable external TXD output */
5235                usc_OutReg(info,IOCR,usc_InReg(info,IOCR) & ~(BIT7 | BIT6));
5236        
5237                /* clear Internal Data loopback mode */
5238                info->loopback_bits = 0;
5239                outw( 0,info->io_base + CCAR );
5240        }
5241        
5242}       /* end of usc_enable_loopback() */
5243
5244/* usc_enable_aux_clock()
5245 *
5246 * Enabled the AUX clock output at the specified frequency.
5247 *
5248 * Arguments:
5249 *
5250 *      info            pointer to device extension
5251 *      data_rate       data rate of clock in bits per second
5252 *                      A data rate of 0 disables the AUX clock.
5253 *
5254 * Return Value:        None
5255 */
5256static void usc_enable_aux_clock( struct mgsl_struct *info, u32 data_rate )
5257{
5258        u32 XtalSpeed;
5259        u16 Tc;
5260
5261        if ( data_rate ) {
5262                if ( info->bus_type == MGSL_BUS_TYPE_PCI )
5263                        XtalSpeed = 11059200;
5264                else
5265                        XtalSpeed = 14745600;
5266
5267
5268                /* Tc = (Xtal/Speed) - 1 */
5269                /* If twice the remainder of (Xtal/Speed) is greater than Speed */
5270                /* then rounding up gives a more precise time constant. Instead */
5271                /* of rounding up and then subtracting 1 we just don't subtract */
5272                /* the one in this case. */
5273
5274
5275                Tc = (u16)(XtalSpeed/data_rate);
5276                if ( !(((XtalSpeed % data_rate) * 2) / data_rate) )
5277                        Tc--;
5278
5279                /* Write 16-bit Time Constant for BRG0 */
5280                usc_OutReg( info, TC0R, Tc );
5281
5282                /*
5283                 * Hardware Configuration Register (HCR)
5284                 * Clear Bit 1, BRG0 mode = Continuous
5285                 * Set Bit 0 to enable BRG0.
5286                 */
5287
5288                usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
5289
5290                /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5291                usc_OutReg( info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) );
5292        } else {
5293                /* data rate == 0 so turn off BRG0 */
5294                usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) );
5295        }
5296
5297}       /* end of usc_enable_aux_clock() */
5298
5299/*
5300 *
5301 * usc_process_rxoverrun_sync()
5302 *
5303 *              This function processes a receive overrun by resetting the
5304 *              receive DMA buffers and issuing a Purge Rx FIFO command
5305 *              to allow the receiver to continue receiving.
5306 *
5307 * Arguments:
5308 *
5309 *      info            pointer to device extension
5310 *
5311 * Return Value: None
5312 */
5313static void usc_process_rxoverrun_sync( struct mgsl_struct *info )
5314{
5315        int start_index;
5316        int end_index;
5317        int frame_start_index;
5318        bool start_of_frame_found = false;
5319        bool end_of_frame_found = false;
5320        bool reprogram_dma = false;
5321
5322        DMABUFFERENTRY *buffer_list = info->rx_buffer_list;
5323        u32 phys_addr;
5324
5325        usc_DmaCmd( info, DmaCmd_PauseRxChannel );
5326        usc_RCmd( info, RCmd_EnterHuntmode );
5327        usc_RTCmd( info, RTCmd_PurgeRxFifo );
5328
5329        /* CurrentRxBuffer points to the 1st buffer of the next */
5330        /* possibly available receive frame. */
5331        
5332        frame_start_index = start_index = end_index = info->current_rx_buffer;
5333
5334        /* Search for an unfinished string of buffers. This means */
5335        /* that a receive frame started (at least one buffer with */
5336        /* count set to zero) but there is no terminiting buffer */
5337        /* (status set to non-zero). */
5338
5339        while( !buffer_list[end_index].count )
5340        {
5341                /* Count field has been reset to zero by 16C32. */
5342                /* This buffer is currently in use. */
5343
5344                if ( !start_of_frame_found )
5345                {
5346                        start_of_frame_found = true;
5347                        frame_start_index = end_index;
5348                        end_of_frame_found = false;
5349                }
5350
5351                if ( buffer_list[end_index].status )
5352                {
5353                        /* Status field has been set by 16C32. */
5354                        /* This is the last buffer of a received frame. */
5355
5356                        /* We want to leave the buffers for this frame intact. */
5357                        /* Move on to next possible frame. */
5358
5359                        start_of_frame_found = false;
5360                        end_of_frame_found = true;
5361                }
5362
5363                /* advance to next buffer entry in linked list */
5364                end_index++;
5365                if ( end_index == info->rx_buffer_count )
5366                        end_index = 0;
5367
5368                if ( start_index == end_index )
5369                {
5370                        /* The entire list has been searched with all Counts == 0 and */
5371                        /* all Status == 0. The receive buffers are */
5372                        /* completely screwed, reset all receive buffers! */
5373                        mgsl_reset_rx_dma_buffers( info );
5374                        frame_start_index = 0;
5375                        start_of_frame_found = false;
5376                        reprogram_dma = true;
5377                        break;
5378                }
5379        }
5380
5381        if ( start_of_frame_found && !end_of_frame_found )
5382        {
5383                /* There is an unfinished string of receive DMA buffers */
5384                /* as a result of the receiver overrun. */
5385
5386                /* Reset the buffers for the unfinished frame */
5387                /* and reprogram the receive DMA controller to start */
5388                /* at the 1st buffer of unfinished frame. */
5389
5390                start_index = frame_start_index;
5391
5392                do
5393                {
5394                        *((unsigned long *)&(info->rx_buffer_list[start_index++].count)) = DMABUFFERSIZE;
5395
5396                        /* Adjust index for wrap around. */
5397                        if ( start_index == info->rx_buffer_count )
5398                                start_index = 0;
5399
5400                } while( start_index != end_index );
5401
5402                reprogram_dma = true;
5403        }
5404
5405        if ( reprogram_dma )
5406        {
5407                usc_UnlatchRxstatusBits(info,RXSTATUS_ALL);
5408                usc_ClearIrqPendingBits(info, RECEIVE_DATA|RECEIVE_STATUS);
5409                usc_UnlatchRxstatusBits(info, RECEIVE_DATA|RECEIVE_STATUS);
5410                
5411                usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
5412                
5413                /* This empties the receive FIFO and loads the RCC with RCLR */
5414                usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5415
5416                /* program 16C32 with physical address of 1st DMA buffer entry */
5417                phys_addr = info->rx_buffer_list[frame_start_index].phys_entry;
5418                usc_OutDmaReg( info, NRARL, (u16)phys_addr );
5419                usc_OutDmaReg( info, NRARU, (u16)(phys_addr >> 16) );
5420
5421                usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5422                usc_ClearIrqPendingBits( info, RECEIVE_DATA | RECEIVE_STATUS );
5423                usc_EnableInterrupts( info, RECEIVE_STATUS );
5424
5425                /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5426                /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5427
5428                usc_OutDmaReg( info, RDIAR, BIT3 | BIT2 );
5429                usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) );
5430                usc_DmaCmd( info, DmaCmd_InitRxChannel );
5431                if ( info->params.flags & HDLC_FLAG_AUTO_DCD )
5432                        usc_EnableReceiver(info,ENABLE_AUTO_DCD);
5433                else
5434                        usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5435        }
5436        else
5437        {
5438                /* This empties the receive FIFO and loads the RCC with RCLR */
5439                usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5440                usc_RTCmd( info, RTCmd_PurgeRxFifo );
5441        }
5442
5443}       /* end of usc_process_rxoverrun_sync() */
5444
5445/* usc_stop_receiver()
5446 *
5447 *      Disable USC receiver
5448 *
5449 * Arguments:           info    pointer to device instance data
5450 * Return Value:        None
5451 */
5452static void usc_stop_receiver( struct mgsl_struct *info )
5453{
5454        if (debug_level >= DEBUG_LEVEL_ISR)
5455                printk("%s(%d):usc_stop_receiver(%s)\n",
5456                         __FILE__,__LINE__, info->device_name );
5457                         
5458        /* Disable receive DMA channel. */
5459        /* This also disables receive DMA channel interrupts */
5460        usc_DmaCmd( info, DmaCmd_ResetRxChannel );
5461
5462        usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5463        usc_ClearIrqPendingBits( info, RECEIVE_DATA | RECEIVE_STATUS );
5464        usc_DisableInterrupts( info, RECEIVE_DATA | RECEIVE_STATUS );
5465
5466        usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
5467
5468        /* This empties the receive FIFO and loads the RCC with RCLR */
5469        usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5470        usc_RTCmd( info, RTCmd_PurgeRxFifo );
5471
5472        info->rx_enabled = false;
5473        info->rx_overflow = false;
5474        info->rx_rcc_underrun = false;
5475        
5476}       /* end of stop_receiver() */
5477
5478/* usc_start_receiver()
5479 *
5480 *      Enable the USC receiver 
5481 *
5482 * Arguments:           info    pointer to device instance data
5483 * Return Value:        None
5484 */
5485static void usc_start_receiver( struct mgsl_struct *info )
5486{
5487        u32 phys_addr;
5488        
5489        if (debug_level >= DEBUG_LEVEL_ISR)
5490                printk("%s(%d):usc_start_receiver(%s)\n",
5491                         __FILE__,__LINE__, info->device_name );
5492
5493        mgsl_reset_rx_dma_buffers( info );
5494        usc_stop_receiver( info );
5495
5496        usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5497        usc_RTCmd( info, RTCmd_PurgeRxFifo );
5498
5499        if ( info->params.mode == MGSL_MODE_HDLC ||
5500                info->params.mode == MGSL_MODE_RAW ) {
5501                /* DMA mode Transfers */
5502                /* Program the DMA controller. */
5503                /* Enable the DMA controller end of buffer interrupt. */
5504
5505                /* program 16C32 with physical address of 1st DMA buffer entry */
5506                phys_addr = info->rx_buffer_list[0].phys_entry;
5507                usc_OutDmaReg( info, NRARL, (u16)phys_addr );
5508                usc_OutDmaReg( info, NRARU, (u16)(phys_addr >> 16) );
5509
5510                usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5511                usc_ClearIrqPendingBits( info, RECEIVE_DATA | RECEIVE_STATUS );
5512                usc_EnableInterrupts( info, RECEIVE_STATUS );
5513
5514                /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5515                /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5516
5517                usc_OutDmaReg( info, RDIAR, BIT3 | BIT2 );
5518                usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) );
5519                usc_DmaCmd( info, DmaCmd_InitRxChannel );
5520                if ( info->params.flags & HDLC_FLAG_AUTO_DCD )
5521                        usc_EnableReceiver(info,ENABLE_AUTO_DCD);
5522                else
5523                        usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5524        } else {
5525                usc_UnlatchRxstatusBits(info, RXSTATUS_ALL);
5526                usc_ClearIrqPendingBits(info, RECEIVE_DATA | RECEIVE_STATUS);
5527                usc_EnableInterrupts(info, RECEIVE_DATA);
5528
5529                usc_RTCmd( info, RTCmd_PurgeRxFifo );
5530                usc_RCmd( info, RCmd_EnterHuntmode );
5531
5532                usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5533        }
5534
5535        usc_OutReg( info, CCSR, 0x1020 );
5536
5537        info->rx_enabled = true;
5538
5539}       /* end of usc_start_receiver() */
5540
5541/* usc_start_transmitter()
5542 *
5543 *      Enable the USC transmitter and send a transmit frame if
5544 *      one is loaded in the DMA buffers.
5545 *
5546 * Arguments:           info    pointer to device instance data
5547 * Return Value:        None
5548 */
5549static void usc_start_transmitter( struct mgsl_struct *info )
5550{
5551        u32 phys_addr;
5552        unsigned int FrameSize;
5553
5554        if (debug_level >= DEBUG_LEVEL_ISR)
5555                printk("%s(%d):usc_start_transmitter(%s)\n",
5556                         __FILE__,__LINE__, info->device_name );
5557                         
5558        if ( info->xmit_cnt ) {
5559
5560                /* If auto RTS enabled and RTS is inactive, then assert */
5561                /* RTS and set a flag indicating that the driver should */
5562                /* negate RTS when the transmission completes. */
5563
5564                info->drop_rts_on_tx_done = false;
5565
5566                if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
5567                        usc_get_serial_signals( info );
5568                        if ( !(info->serial_signals & SerialSignal_RTS) ) {
5569                                info->serial_signals |= SerialSignal_RTS;
5570                                usc_set_serial_signals( info );
5571                                info->drop_rts_on_tx_done = true;
5572                        }
5573                }
5574
5575
5576                if ( info->params.mode == MGSL_MODE_ASYNC ) {
5577                        if ( !info->tx_active ) {
5578                                usc_UnlatchTxstatusBits(info, TXSTATUS_ALL);
5579                                usc_ClearIrqPendingBits(info, TRANSMIT_STATUS + TRANSMIT_DATA);
5580                                usc_EnableInterrupts(info, TRANSMIT_DATA);
5581                                usc_load_txfifo(info);
5582                        }
5583                } else {
5584                        /* Disable transmit DMA controller while programming. */
5585                        usc_DmaCmd( info, DmaCmd_ResetTxChannel );
5586                        
5587                        /* Transmit DMA buffer is loaded, so program USC */
5588                        /* to send the frame contained in the buffers.   */
5589
5590                        FrameSize = info->tx_buffer_list[info->start_tx_dma_buffer].rcc;
5591
5592                        /* if operating in Raw sync mode, reset the rcc component
5593                         * of the tx dma buffer entry, otherwise, the serial controller
5594                         * will send a closing sync char after this count.
5595                         */
5596                        if ( info->params.mode == MGSL_MODE_RAW )
5597                                info->tx_buffer_list[info->start_tx_dma_buffer].rcc = 0;
5598
5599                        /* Program the Transmit Character Length Register (TCLR) */
5600                        /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
5601                        usc_OutReg( info, TCLR, (u16)FrameSize );
5602
5603                        usc_RTCmd( info, RTCmd_PurgeTxFifo );
5604
5605                        /* Program the address of the 1st DMA Buffer Entry in linked list */
5606                        phys_addr = info->tx_buffer_list[info->start_tx_dma_buffer].phys_entry;
5607                        usc_OutDmaReg( info, NTARL, (u16)phys_addr );
5608                        usc_OutDmaReg( info, NTARU, (u16)(phys_addr >> 16) );
5609
5610                        usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
5611                        usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
5612                        usc_EnableInterrupts( info, TRANSMIT_STATUS );
5613
5614                        if ( info->params.mode == MGSL_MODE_RAW &&
5615                                        info->num_tx_dma_buffers > 1 ) {
5616                           /* When running external sync mode, attempt to 'stream' transmit  */
5617                           /* by filling tx dma buffers as they become available. To do this */
5618                           /* we need to enable Tx DMA EOB Status interrupts :               */
5619                           /*                                                                */
5620                           /* 1. Arm End of Buffer (EOB) Transmit DMA Interrupt (BIT2 of TDIAR) */
5621                           /* 2. Enable Transmit DMA Interrupts (BIT0 of DICR) */
5622
5623                           usc_OutDmaReg( info, TDIAR, BIT2|BIT3 );
5624                           usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT0) );
5625                        }
5626
5627                        /* Initialize Transmit DMA Channel */
5628                        usc_DmaCmd( info, DmaCmd_InitTxChannel );
5629                        
5630                        usc_TCmd( info, TCmd_SendFrame );
5631                        
5632                        mod_timer(&info->tx_timer, jiffies +
5633                                        msecs_to_jiffies(5000));
5634                }
5635                info->tx_active = true;
5636        }
5637
5638        if ( !info->tx_enabled ) {
5639                info->tx_enabled = true;
5640                if ( info->params.flags & HDLC_FLAG_AUTO_CTS )
5641                        usc_EnableTransmitter(info,ENABLE_AUTO_CTS);
5642                else
5643                        usc_EnableTransmitter(info,ENABLE_UNCONDITIONAL);
5644        }
5645
5646}       /* end of usc_start_transmitter() */
5647
5648/* usc_stop_transmitter()
5649 *
5650 *      Stops the transmitter and DMA
5651 *
5652 * Arguments:           info    pointer to device isntance data
5653 * Return Value:        None
5654 */
5655static void usc_stop_transmitter( struct mgsl_struct *info )
5656{
5657        if (debug_level >= DEBUG_LEVEL_ISR)
5658                printk("%s(%d):usc_stop_transmitter(%s)\n",
5659                         __FILE__,__LINE__, info->device_name );
5660                         
5661        del_timer(&info->tx_timer);     
5662                         
5663        usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
5664        usc_ClearIrqPendingBits( info, TRANSMIT_STATUS + TRANSMIT_DATA );
5665        usc_DisableInterrupts( info, TRANSMIT_STATUS + TRANSMIT_DATA );
5666
5667        usc_EnableTransmitter(info,DISABLE_UNCONDITIONAL);
5668        usc_DmaCmd( info, DmaCmd_ResetTxChannel );
5669        usc_RTCmd( info, RTCmd_PurgeTxFifo );
5670
5671        info->tx_enabled = false;
5672        info->tx_active = false;
5673
5674}       /* end of usc_stop_transmitter() */
5675
5676/* usc_load_txfifo()
5677 *
5678 *      Fill the transmit FIFO until the FIFO is full or
5679 *      there is no more data to load.
5680 *
5681 * Arguments:           info    pointer to device extension (instance data)
5682 * Return Value:        None
5683 */
5684static void usc_load_txfifo( struct mgsl_struct *info )
5685{
5686        int Fifocount;
5687        u8 TwoBytes[2];
5688        
5689        if ( !info->xmit_cnt && !info->x_char )
5690                return; 
5691                
5692        /* Select transmit FIFO status readback in TICR */
5693        usc_TCmd( info, TCmd_SelectTicrTxFifostatus );
5694
5695        /* load the Transmit FIFO until FIFOs full or all data sent */
5696
5697        while( (Fifocount = usc_InReg(info, TICR) >> 8) && info->xmit_cnt ) {
5698                /* there is more space in the transmit FIFO and */
5699                /* there is more data in transmit buffer */
5700
5701                if ( (info->xmit_cnt > 1) && (Fifocount > 1) && !info->x_char ) {
5702                        /* write a 16-bit word from transmit buffer to 16C32 */
5703                                
5704                        TwoBytes[0] = info->xmit_buf[info->xmit_tail++];
5705                        info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5706                        TwoBytes[1] = info->xmit_buf[info->xmit_tail++];
5707                        info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5708                        
5709                        outw( *((u16 *)TwoBytes), info->io_base + DATAREG);
5710                                
5711                        info->xmit_cnt -= 2;
5712                        info->icount.tx += 2;
5713                } else {
5714                        /* only 1 byte left to transmit or 1 FIFO slot left */
5715                        
5716                        outw( (inw( info->io_base + CCAR) & 0x0780) | (TDR+LSBONLY),
5717                                info->io_base + CCAR );
5718                        
5719                        if (info->x_char) {
5720                                /* transmit pending high priority char */
5721                                outw( info->x_char,info->io_base + CCAR );
5722                                info->x_char = 0;
5723                        } else {
5724                                outw( info->xmit_buf[info->xmit_tail++],info->io_base + CCAR );
5725                                info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5726                                info->xmit_cnt--;
5727                        }
5728                        info->icount.tx++;
5729                }
5730        }
5731
5732}       /* end of usc_load_txfifo() */
5733
5734/* usc_reset()
5735 *
5736 *      Reset the adapter to a known state and prepare it for further use.
5737 *
5738 * Arguments:           info    pointer to device instance data
5739 * Return Value:        None
5740 */
5741static void usc_reset( struct mgsl_struct *info )
5742{
5743        if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5744                int i;
5745                u32 readval;
5746
5747                /* Set BIT30 of Misc Control Register */
5748                /* (Local Control Register 0x50) to force reset of USC. */
5749
5750                volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5751                u32 *LCR0BRDR = (u32 *)(info->lcr_base + 0x28);
5752
5753                info->misc_ctrl_value |= BIT30;
5754                *MiscCtrl = info->misc_ctrl_value;
5755
5756                /*
5757                 * Force at least 170ns delay before clearing 
5758                 * reset bit. Each read from LCR takes at least 
5759                 * 30ns so 10 times for 300ns to be safe.
5760                 */
5761                for(i=0;i<10;i++)
5762                        readval = *MiscCtrl;
5763
5764                info->misc_ctrl_value &= ~BIT30;
5765                *MiscCtrl = info->misc_ctrl_value;
5766
5767                *LCR0BRDR = BUS_DESCRIPTOR(
5768                        1,              // Write Strobe Hold (0-3)
5769                        2,              // Write Strobe Delay (0-3)
5770                        2,              // Read Strobe Delay  (0-3)
5771                        0,              // NWDD (Write data-data) (0-3)
5772                        4,              // NWAD (Write Addr-data) (0-31)
5773                        0,              // NXDA (Read/Write Data-Addr) (0-3)
5774                        0,              // NRDD (Read Data-Data) (0-3)
5775                        5               // NRAD (Read Addr-Data) (0-31)
5776                        );
5777        } else {
5778                /* do HW reset */
5779                outb( 0,info->io_base + 8 );
5780        }
5781
5782        info->mbre_bit = 0;
5783        info->loopback_bits = 0;
5784        info->usc_idle_mode = 0;
5785
5786        /*
5787         * Program the Bus Configuration Register (BCR)
5788         *
5789         * <15>         0       Don't use separate address
5790         * <14..6>      0       reserved
5791         * <5..4>       00      IAckmode = Default, don't care
5792         * <3>          1       Bus Request Totem Pole output
5793         * <2>          1       Use 16 Bit data bus
5794         * <1>          0       IRQ Totem Pole output
5795         * <0>          0       Don't Shift Right Addr
5796         *
5797         * 0000 0000 0000 1100 = 0x000c
5798         *
5799         * By writing to io_base + SDPIN the Wait/Ack pin is
5800         * programmed to work as a Wait pin.
5801         */
5802        
5803        outw( 0x000c,info->io_base + SDPIN );
5804
5805
5806        outw( 0,info->io_base );
5807        outw( 0,info->io_base + CCAR );
5808
5809        /* select little endian byte ordering */
5810        usc_RTCmd( info, RTCmd_SelectLittleEndian );
5811
5812
5813        /* Port Control Register (PCR)
5814         *
5815         * <15..14>     11      Port 7 is Output (~DMAEN, Bit 14 : 0 = Enabled)
5816         * <13..12>     11      Port 6 is Output (~INTEN, Bit 12 : 0 = Enabled)
5817         * <11..10>     00      Port 5 is Input (No Connect, Don't Care)
5818         * <9..8>       00      Port 4 is Input (No Connect, Don't Care)
5819         * <7..6>       11      Port 3 is Output (~RTS, Bit 6 : 0 = Enabled )
5820         * <5..4>       11      Port 2 is Output (~DTR, Bit 4 : 0 = Enabled )
5821         * <3..2>       01      Port 1 is Input (Dedicated RxC)
5822         * <1..0>       01      Port 0 is Input (Dedicated TxC)
5823         *
5824         *      1111 0000 1111 0101 = 0xf0f5
5825         */
5826
5827        usc_OutReg( info, PCR, 0xf0f5 );
5828
5829
5830        /*
5831         * Input/Output Control Register
5832         *
5833         * <15..14>     00      CTS is active low input
5834         * <13..12>     00      DCD is active low input
5835         * <11..10>     00      TxREQ pin is input (DSR)
5836         * <9..8>       00      RxREQ pin is input (RI)
5837         * <7..6>       00      TxD is output (Transmit Data)
5838         * <5..3>       000     TxC Pin in Input (14.7456MHz Clock)
5839         * <2..0>       100     RxC is Output (drive with BRG0)
5840         *
5841         *      0000 0000 0000 0100 = 0x0004
5842         */
5843
5844        usc_OutReg( info, IOCR, 0x0004 );
5845
5846}       /* end of usc_reset() */
5847
5848/* usc_set_async_mode()
5849 *
5850 *      Program adapter for asynchronous communications.
5851 *
5852 * Arguments:           info            pointer to device instance data
5853 * Return Value:        None
5854 */
5855static void usc_set_async_mode( struct mgsl_struct *info )
5856{
5857        u16 RegValue;
5858
5859        /* disable interrupts while programming USC */
5860        usc_DisableMasterIrqBit( info );
5861
5862        outw( 0, info->io_base );                       /* clear Master Bus Enable (DCAR) */
5863        usc_DmaCmd( info, DmaCmd_ResetAllChannels );    /* disable both DMA channels */
5864
5865        usc_loopback_frame( info );
5866
5867        /* Channel mode Register (CMR)
5868         *
5869         * <15..14>     00      Tx Sub modes, 00 = 1 Stop Bit
5870         * <13..12>     00                    00 = 16X Clock
5871         * <11..8>      0000    Transmitter mode = Asynchronous
5872         * <7..6>       00      reserved?
5873         * <5..4>       00      Rx Sub modes, 00 = 16X Clock
5874         * <3..0>       0000    Receiver mode = Asynchronous
5875         *
5876         * 0000 0000 0000 0000 = 0x0
5877         */
5878
5879        RegValue = 0;
5880        if ( info->params.stop_bits != 1 )
5881                RegValue |= BIT14;
5882        usc_OutReg( info, CMR, RegValue );
5883
5884        
5885        /* Receiver mode Register (RMR)
5886         *
5887         * <15..13>     000     encoding = None
5888         * <12..08>     00000   reserved (Sync Only)
5889         * <7..6>       00      Even parity
5890         * <5>          0       parity disabled
5891         * <4..2>       000     Receive Char Length = 8 bits
5892         * <1..0>       00      Disable Receiver
5893         *
5894         * 0000 0000 0000 0000 = 0x0
5895         */
5896
5897        RegValue = 0;
5898
5899        if ( info->params.data_bits != 8 )
5900                RegValue |= BIT4 | BIT3 | BIT2;
5901
5902        if ( info->params.parity != ASYNC_PARITY_NONE ) {
5903                RegValue |= BIT5;
5904                if ( info->params.parity != ASYNC_PARITY_ODD )
5905                        RegValue |= BIT6;
5906        }
5907
5908        usc_OutReg( info, RMR, RegValue );
5909
5910
5911        /* Set IRQ trigger level */
5912
5913        usc_RCmd( info, RCmd_SelectRicrIntLevel );
5914
5915        
5916        /* Receive Interrupt Control Register (RICR)
5917         *
5918         * <15..8>      ?               RxFIFO IRQ Request Level
5919         *
5920         * Note: For async mode the receive FIFO level must be set
5921         * to 0 to avoid the situation where the FIFO contains fewer bytes
5922         * than the trigger level and no more data is expected.
5923         *
5924         * <7>          0               Exited Hunt IA (Interrupt Arm)
5925         * <6>          0               Idle Received IA
5926         * <5>          0               Break/Abort IA
5927         * <4>          0               Rx Bound IA
5928         * <3>          0               Queued status reflects oldest byte in FIFO
5929         * <2>          0               Abort/PE IA
5930         * <1>          0               Rx Overrun IA
5931         * <0>          0               Select TC0 value for readback
5932         *
5933         * 0000 0000 0100 0000 = 0x0000 + (FIFOLEVEL in MSB)
5934         */
5935        
5936        usc_OutReg( info, RICR, 0x0000 );
5937
5938        usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5939        usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
5940
5941        
5942        /* Transmit mode Register (TMR)
5943         *
5944         * <15..13>     000     encoding = None
5945         * <12..08>     00000   reserved (Sync Only)
5946         * <7..6>       00      Transmit parity Even
5947         * <5>          0       Transmit parity Disabled
5948         * <4..2>       000     Tx Char Length = 8 bits
5949         * <1..0>       00      Disable Transmitter
5950         *
5951         * 0000 0000 0000 0000 = 0x0
5952         */
5953
5954        RegValue = 0;
5955
5956        if ( info->params.data_bits != 8 )
5957                RegValue |= BIT4 | BIT3 | BIT2;
5958
5959        if ( info->params.parity != ASYNC_PARITY_NONE ) {
5960                RegValue |= BIT5;
5961                if ( info->params.parity != ASYNC_PARITY_ODD )
5962                        RegValue |= BIT6;
5963        }
5964
5965        usc_OutReg( info, TMR, RegValue );
5966
5967        usc_set_txidle( info );
5968
5969
5970        /* Set IRQ trigger level */
5971
5972        usc_TCmd( info, TCmd_SelectTicrIntLevel );
5973
5974        
5975        /* Transmit Interrupt Control Register (TICR)
5976         *
5977         * <15..8>      ?       Transmit FIFO IRQ Level
5978         * <7>          0       Present IA (Interrupt Arm)
5979         * <6>          1       Idle Sent IA
5980         * <5>          0       Abort Sent IA
5981         * <4>          0       EOF/EOM Sent IA
5982         * <3>          0       CRC Sent IA
5983         * <2>          0       1 = Wait for SW Trigger to Start Frame
5984         * <1>          0       Tx Underrun IA
5985         * <0>          0       TC0 constant on read back
5986         *
5987         *      0000 0000 0100 0000 = 0x0040
5988         */
5989
5990        usc_OutReg( info, TICR, 0x1f40 );
5991
5992        usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
5993        usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
5994
5995        usc_enable_async_clock( info, info->params.data_rate );
5996
5997        
5998        /* Channel Control/status Register (CCSR)
5999         *
6000         * <15>         X       RCC FIFO Overflow status (RO)
6001         * <14>         X       RCC FIFO Not Empty status (RO)
6002         * <13>         0       1 = Clear RCC FIFO (WO)
6003         * <12>         X       DPLL in Sync status (RO)
6004         * <11>         X       DPLL 2 Missed Clocks status (RO)
6005         * <10>         X       DPLL 1 Missed Clock status (RO)
6006         * <9..8>       00      DPLL Resync on rising and falling edges (RW)
6007         * <7>          X       SDLC Loop On status (RO)
6008         * <6>          X       SDLC Loop Send status (RO)
6009         * <5>          1       Bypass counters for TxClk and RxClk (RW)
6010         * <4..2>       000     Last Char of SDLC frame has 8 bits (RW)
6011         * <1..0>       00      reserved
6012         *
6013         *      0000 0000 0010 0000 = 0x0020
6014         */
6015        
6016        usc_OutReg( info, CCSR, 0x0020 );
6017
6018        usc_DisableInterrupts( info, TRANSMIT_STATUS + TRANSMIT_DATA +
6019                              RECEIVE_DATA + RECEIVE_STATUS );
6020
6021        usc_ClearIrqPendingBits( info, TRANSMIT_STATUS + TRANSMIT_DATA +
6022                                RECEIVE_DATA + RECEIVE_STATUS );
6023
6024        usc_EnableMasterIrqBit( info );
6025
6026        if (info->bus_type == MGSL_BUS_TYPE_ISA) {
6027                /* Enable INTEN (Port 6, Bit12) */
6028                /* This connects the IRQ request signal to the ISA bus */
6029                usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12));
6030        }
6031
6032        if (info->params.loopback) {
6033                info->loopback_bits = 0x300;
6034                outw(0x0300, info->io_base + CCAR);
6035        }
6036
6037}       /* end of usc_set_async_mode() */
6038
6039/* usc_loopback_frame()
6040 *
6041 *      Loop back a small (2 byte) dummy SDLC frame.
6042 *      Interrupts and DMA are NOT used. The purpose of this is to
6043 *      clear any 'stale' status info left over from running in async mode.
6044 *
6045 *      The 16C32 shows the strange behaviour of marking the 1st
6046 *      received SDLC frame with a CRC error even when there is no
6047 *      CRC error. To get around this a small dummy from of 2 bytes
6048 *      is looped back when switching from async to sync mode.
6049 *
6050 * Arguments:           info            pointer to device instance data
6051 * Return Value:        None
6052 */
6053static void usc_loopback_frame( struct mgsl_struct *info )
6054{
6055        int i;
6056        unsigned long oldmode = info->params.mode;
6057
6058        info->params.mode = MGSL_MODE_HDLC;
6059        
6060        usc_DisableMasterIrqBit( info );
6061
6062        usc_set_sdlc_mode( info );
6063        usc_enable_loopback( info, 1 );
6064
6065        /* Write 16-bit Time Constant for BRG0 */
6066        usc_OutReg( info, TC0R, 0 );
6067        
6068        /* Channel Control Register (CCR)
6069         *
6070         * <15..14>     00      Don't use 32-bit Tx Control Blocks (TCBs)
6071         * <13>         0       Trigger Tx on SW Command Disabled
6072         * <12>         0       Flag Preamble Disabled
6073         * <11..10>     00      Preamble Length = 8-Bits
6074         * <9..8>       01      Preamble Pattern = flags
6075         * <7..6>       10      Don't use 32-bit Rx status Blocks (RSBs)
6076         * <5>          0       Trigger Rx on SW Command Disabled
6077         * <4..0>       0       reserved
6078         *
6079         *      0000 0001 0000 0000 = 0x0100
6080         */
6081
6082        usc_OutReg( info, CCR, 0x0100 );
6083
6084        /* SETUP RECEIVER */
6085        usc_RTCmd( info, RTCmd_PurgeRxFifo );
6086        usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
6087
6088        /* SETUP TRANSMITTER */
6089        /* Program the Transmit Character Length Register (TCLR) */
6090        /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
6091        usc_OutReg( info, TCLR, 2 );
6092        usc_RTCmd( info, RTCmd_PurgeTxFifo );
6093
6094        /* unlatch Tx status bits, and start transmit channel. */
6095        usc_UnlatchTxstatusBits(info,TXSTATUS_ALL);
6096        outw(0,info->io_base + DATAREG);
6097
6098        /* ENABLE TRANSMITTER */
6099        usc_TCmd( info, TCmd_SendFrame );
6100        usc_EnableTransmitter(info,ENABLE_UNCONDITIONAL);
6101                                                        
6102        /* WAIT FOR RECEIVE COMPLETE */
6103        for (i=0 ; i<1000 ; i++)
6104                if (usc_InReg( info, RCSR ) & (BIT8 | BIT4 | BIT3 | BIT1))
6105                        break;
6106
6107        /* clear Internal Data loopback mode */
6108        usc_enable_loopback(info, 0);
6109
6110        usc_EnableMasterIrqBit(info);
6111
6112        info->params.mode = oldmode;
6113
6114}       /* end of usc_loopback_frame() */
6115
6116/* usc_set_sync_mode()  Programs the USC for SDLC communications.
6117 *
6118 * Arguments:           info    pointer to adapter info structure
6119 * Return Value:        None
6120 */
6121static void usc_set_sync_mode( struct mgsl_struct *info )
6122{
6123        usc_loopback_frame( info );
6124        usc_set_sdlc_mode( info );
6125
6126        if (info->bus_type == MGSL_BUS_TYPE_ISA) {
6127                /* Enable INTEN (Port 6, Bit12) */
6128                /* This connects the IRQ request signal to the ISA bus */
6129                usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12));
6130        }
6131
6132        usc_enable_aux_clock(info, info->params.clock_speed);
6133
6134        if (info->params.loopback)
6135                usc_enable_loopback(info,1);
6136
6137}       /* end of mgsl_set_sync_mode() */
6138
6139/* usc_set_txidle()     Set the HDLC idle mode for the transmitter.
6140 *
6141 * Arguments:           info    pointer to device instance data
6142 * Return Value:        None
6143 */
6144static void usc_set_txidle( struct mgsl_struct *info )
6145{
6146        u16 usc_idle_mode = IDLEMODE_FLAGS;
6147
6148        /* Map API idle mode to USC register bits */
6149
6150        switch( info->idle_mode ){
6151        case HDLC_TXIDLE_FLAGS:                 usc_idle_mode = IDLEMODE_FLAGS; break;
6152        case HDLC_TXIDLE_ALT_ZEROS_ONES:        usc_idle_mode = IDLEMODE_ALT_ONE_ZERO; break;
6153        case HDLC_TXIDLE_ZEROS:                 usc_idle_mode = IDLEMODE_ZERO; break;
6154        case HDLC_TXIDLE_ONES:                  usc_idle_mode = IDLEMODE_ONE; break;
6155        case HDLC_TXIDLE_ALT_MARK_SPACE:        usc_idle_mode = IDLEMODE_ALT_MARK_SPACE; break;
6156        case HDLC_TXIDLE_SPACE:                 usc_idle_mode = IDLEMODE_SPACE; break;
6157        case HDLC_TXIDLE_MARK:                  usc_idle_mode = IDLEMODE_MARK; break;
6158        }
6159
6160        info->usc_idle_mode = usc_idle_mode;
6161        //usc_OutReg(info, TCSR, usc_idle_mode);
6162        info->tcsr_value &= ~IDLEMODE_MASK;     /* clear idle mode bits */
6163        info->tcsr_value += usc_idle_mode;
6164        usc_OutReg(info, TCSR, info->tcsr_value);
6165
6166        /*
6167         * if SyncLink WAN adapter is running in external sync mode, the
6168         * transmitter has been set to Monosync in order to try to mimic
6169         * a true raw outbound bit stream. Monosync still sends an open/close
6170         * sync char at the start/end of a frame. Try to match those sync
6171         * patterns to the idle mode set here
6172         */
6173        if ( info->params.mode == MGSL_MODE_RAW ) {
6174                unsigned char syncpat = 0;
6175                switch( info->idle_mode ) {
6176                case HDLC_TXIDLE_FLAGS:
6177                        syncpat = 0x7e;
6178                        break;
6179                case HDLC_TXIDLE_ALT_ZEROS_ONES:
6180                        syncpat = 0x55;
6181                        break;
6182                case HDLC_TXIDLE_ZEROS:
6183                case HDLC_TXIDLE_SPACE:
6184                        syncpat = 0x00;
6185                        break;
6186                case HDLC_TXIDLE_ONES:
6187                case HDLC_TXIDLE_MARK:
6188                        syncpat = 0xff;
6189                        break;
6190                case HDLC_TXIDLE_ALT_MARK_SPACE:
6191                        syncpat = 0xaa;
6192                        break;
6193                }
6194
6195                usc_SetTransmitSyncChars(info,syncpat,syncpat);
6196        }
6197
6198}       /* end of usc_set_txidle() */
6199
6200/* usc_get_serial_signals()
6201 *
6202 *      Query the adapter for the state of the V24 status (input) signals.
6203 *
6204 * Arguments:           info    pointer to device instance data
6205 * Return Value:        None
6206 */
6207static void usc_get_serial_signals( struct mgsl_struct *info )
6208{
6209        u16 status;
6210
6211        /* clear all serial signals except RTS and DTR */
6212        info->serial_signals &= SerialSignal_RTS | SerialSignal_DTR;
6213
6214        /* Read the Misc Interrupt status Register (MISR) to get */
6215        /* the V24 status signals. */
6216
6217        status = usc_InReg( info, MISR );
6218
6219        /* set serial signal bits to reflect MISR */
6220
6221        if ( status & MISCSTATUS_CTS )
6222                info->serial_signals |= SerialSignal_CTS;
6223
6224        if ( status & MISCSTATUS_DCD )
6225                info->serial_signals |= SerialSignal_DCD;
6226
6227        if ( status & MISCSTATUS_RI )
6228                info->serial_signals |= SerialSignal_RI;
6229
6230        if ( status & MISCSTATUS_DSR )
6231                info->serial_signals |= SerialSignal_DSR;
6232
6233}       /* end of usc_get_serial_signals() */
6234
6235/* usc_set_serial_signals()
6236 *
6237 *      Set the state of RTS and DTR based on contents of
6238 *      serial_signals member of device extension.
6239 *      
6240 * Arguments:           info    pointer to device instance data
6241 * Return Value:        None
6242 */
6243static void usc_set_serial_signals( struct mgsl_struct *info )
6244{
6245        u16 Control;
6246        unsigned char V24Out = info->serial_signals;
6247
6248        /* get the current value of the Port Control Register (PCR) */
6249
6250        Control = usc_InReg( info, PCR );
6251
6252        if ( V24Out & SerialSignal_RTS )
6253                Control &= ~(BIT6);
6254        else
6255                Control |= BIT6;
6256
6257        if ( V24Out & SerialSignal_DTR )
6258                Control &= ~(BIT4);
6259        else
6260                Control |= BIT4;
6261
6262        usc_OutReg( info, PCR, Control );
6263
6264}       /* end of usc_set_serial_signals() */
6265
6266/* usc_enable_async_clock()
6267 *
6268 *      Enable the async clock at the specified frequency.
6269 *
6270 * Arguments:           info            pointer to device instance data
6271 *                      data_rate       data rate of clock in bps
6272 *                                      0 disables the AUX clock.
6273 * Return Value:        None
6274 */
6275static void usc_enable_async_clock( struct mgsl_struct *info, u32 data_rate )
6276{
6277        if ( data_rate )        {
6278                /*
6279                 * Clock mode Control Register (CMCR)
6280                 * 
6281                 * <15..14>     00      counter 1 Disabled
6282                 * <13..12>     00      counter 0 Disabled
6283                 * <11..10>     11      BRG1 Input is TxC Pin
6284                 * <9..8>       11      BRG0 Input is TxC Pin
6285                 * <7..6>       01      DPLL Input is BRG1 Output
6286                 * <5..3>       100     TxCLK comes from BRG0
6287                 * <2..0>       100     RxCLK comes from BRG0
6288                 *
6289                 * 0000 1111 0110 0100 = 0x0f64
6290                 */
6291                
6292                usc_OutReg( info, CMCR, 0x0f64 );
6293
6294
6295                /*
6296                 * Write 16-bit Time Constant for BRG0
6297                 * Time Constant = (ClkSpeed / data_rate) - 1
6298                 * ClkSpeed = 921600 (ISA), 691200 (PCI)
6299                 */
6300
6301                if ( info->bus_type == MGSL_BUS_TYPE_PCI )
6302                        usc_OutReg( info, TC0R, (u16)((691200/data_rate) - 1) );
6303                else
6304                        usc_OutReg( info, TC0R, (u16)((921600/data_rate) - 1) );
6305
6306                
6307                /*
6308                 * Hardware Configuration Register (HCR)
6309                 * Clear Bit 1, BRG0 mode = Continuous
6310                 * Set Bit 0 to enable BRG0.
6311                 */
6312
6313                usc_OutReg( info, HCR,
6314                            (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
6315
6316
6317                /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
6318
6319                usc_OutReg( info, IOCR,
6320                            (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) );
6321        } else {
6322                /* data rate == 0 so turn off BRG0 */
6323                usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) );
6324        }
6325
6326}       /* end of usc_enable_async_clock() */
6327
6328/*
6329 * Buffer Structures:
6330 *
6331 * Normal memory access uses virtual addresses that can make discontiguous
6332 * physical memory pages appear to be contiguous in the virtual address
6333 * space (the processors memory mapping handles the conversions).
6334 *
6335 * DMA transfers require physically contiguous memory. This is because
6336 * the DMA system controller and DMA bus masters deal with memory using
6337 * only physical addresses.
6338 *
6339 * This causes a problem under Windows NT when large DMA buffers are
6340 * needed. Fragmentation of the nonpaged pool prevents allocations of
6341 * physically contiguous buffers larger than the PAGE_SIZE.
6342 *
6343 * However the 16C32 supports Bus Master Scatter/Gather DMA which
6344 * allows DMA transfers to physically discontiguous buffers. Information
6345 * about each data transfer buffer is contained in a memory structure
6346 * called a 'buffer entry'. A list of buffer entries is maintained
6347 * to track and control the use of the data transfer buffers.
6348 *
6349 * To support this strategy we will allocate sufficient PAGE_SIZE
6350 * contiguous memory buffers to allow for the total required buffer
6351 * space.
6352 *
6353 * The 16C32 accesses the list of buffer entries using Bus Master
6354 * DMA. Control information is read from the buffer entries by the
6355 * 16C32 to control data transfers. status information is written to
6356 * the buffer entries by the 16C32 to indicate the status of completed
6357 * transfers.
6358 *
6359 * The CPU writes control information to the buffer entries to control
6360 * the 16C32 and reads status information from the buffer entries to
6361 * determine information about received and transmitted frames.
6362 *
6363 * Because the CPU and 16C32 (adapter) both need simultaneous access
6364 * to the buffer entries, the buffer entry memory is allocated with
6365 * HalAllocateCommonBuffer(). This restricts the size of the buffer
6366 * entry list to PAGE_SIZE.
6367 *
6368 * The actual data buffers on the other hand will only be accessed
6369 * by the CPU or the adapter but not by both simultaneously. This allows
6370 * Scatter/Gather packet based DMA procedures for using physically
6371 * discontiguous pages.
6372 */
6373
6374/*
6375 * mgsl_reset_tx_dma_buffers()
6376 *
6377 *      Set the count for all transmit buffers to 0 to indicate the
6378 *      buffer is available for use and set the current buffer to the
6379 *      first buffer. This effectively makes all buffers free and
6380 *      discards any data in buffers.
6381 *
6382 * Arguments:           info    pointer to device instance data
6383 * Return Value:        None
6384 */
6385static void mgsl_reset_tx_dma_buffers( struct mgsl_struct *info )
6386{
6387        unsigned int i;
6388
6389        for ( i = 0; i < info->tx_buffer_count; i++ ) {
6390                *((unsigned long *)&(info->tx_buffer_list[i].count)) = 0;
6391        }
6392
6393        info->current_tx_buffer = 0;
6394        info->start_tx_dma_buffer = 0;
6395        info->tx_dma_buffers_used = 0;
6396
6397        info->get_tx_holding_index = 0;
6398        info->put_tx_holding_index = 0;
6399        info->tx_holding_count = 0;
6400
6401}       /* end of mgsl_reset_tx_dma_buffers() */
6402
6403/*
6404 * num_free_tx_dma_buffers()
6405 *
6406 *      returns the number of free tx dma buffers available
6407 *
6408 * Arguments:           info    pointer to device instance data
6409 * Return Value:        number of free tx dma buffers
6410 */
6411static int num_free_tx_dma_buffers(struct mgsl_struct *info)
6412{
6413        return info->tx_buffer_count - info->tx_dma_buffers_used;
6414}
6415
6416/*
6417 * mgsl_reset_rx_dma_buffers()
6418 * 
6419 *      Set the count for all receive buffers to DMABUFFERSIZE
6420 *      and set the current buffer to the first buffer. This effectively
6421 *      makes all buffers free and discards any data in buffers.
6422 * 
6423 * Arguments:           info    pointer to device instance data
6424 * Return Value:        None
6425 */
6426static void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info )
6427{
6428        unsigned int i;
6429
6430        for ( i = 0; i < info->rx_buffer_count; i++ ) {
6431                *((unsigned long *)&(info->rx_buffer_list[i].count)) = DMABUFFERSIZE;
6432//              info->rx_buffer_list[i].count = DMABUFFERSIZE;
6433//              info->rx_buffer_list[i].status = 0;
6434        }
6435
6436        info->current_rx_buffer = 0;
6437
6438}       /* end of mgsl_reset_rx_dma_buffers() */
6439
6440/*
6441 * mgsl_free_rx_frame_buffers()
6442 * 
6443 *      Free the receive buffers used by a received SDLC
6444 *      frame such that the buffers can be reused.
6445 * 
6446 * Arguments:
6447 * 
6448 *      info                    pointer to device instance data
6449 *      StartIndex              index of 1st receive buffer of frame
6450 *      EndIndex                index of last receive buffer of frame
6451 * 
6452 * Return Value:        None
6453 */
6454static void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex )
6455{
6456        bool Done = false;
6457        DMABUFFERENTRY *pBufEntry;
6458        unsigned int Index;
6459
6460        /* Starting with 1st buffer entry of the frame clear the status */
6461        /* field and set the count field to DMA Buffer Size. */
6462
6463        Index = StartIndex;
6464
6465        while( !Done ) {
6466                pBufEntry = &(info->rx_buffer_list[Index]);
6467
6468                if ( Index == EndIndex ) {
6469                        /* This is the last buffer of the frame! */
6470                        Done = true;
6471                }
6472
6473                /* reset current buffer for reuse */
6474//              pBufEntry->status = 0;
6475//              pBufEntry->count = DMABUFFERSIZE;
6476                *((unsigned long *)&(pBufEntry->count)) = DMABUFFERSIZE;
6477
6478                /* advance to next buffer entry in linked list */
6479                Index++;
6480                if ( Index == info->rx_buffer_count )
6481                        Index = 0;
6482        }
6483
6484        /* set current buffer to next buffer after last buffer of frame */
6485        info->current_rx_buffer = Index;
6486
6487}       /* end of free_rx_frame_buffers() */
6488
6489/* mgsl_get_rx_frame()
6490 * 
6491 *      This function attempts to return a received SDLC frame from the
6492 *      receive DMA buffers. Only frames received without errors are returned.
6493 *
6494 * Arguments:           info    pointer to device extension
6495 * Return Value:        true if frame returned, otherwise false
6496 */
6497static bool mgsl_get_rx_frame(struct mgsl_struct *info)
6498{
6499        unsigned int StartIndex, EndIndex;      /* index of 1st and last buffers of Rx frame */
6500        unsigned short status;
6501        DMABUFFERENTRY *pBufEntry;
6502        unsigned int framesize = 0;
6503        bool ReturnCode = false;
6504        unsigned long flags;
6505        struct tty_struct *tty = info->port.tty;
6506        bool return_frame = false;
6507        
6508        /*
6509         * current_rx_buffer points to the 1st buffer of the next available
6510         * receive frame. To find the last buffer of the frame look for
6511         * a non-zero status field in the buffer entries. (The status
6512         * field is set by the 16C32 after completing a receive frame.
6513         */
6514
6515        StartIndex = EndIndex = info->current_rx_buffer;
6516
6517        while( !info->rx_buffer_list[EndIndex].status ) {
6518                /*
6519                 * If the count field of the buffer entry is non-zero then
6520                 * this buffer has not been used. (The 16C32 clears the count
6521                 * field when it starts using the buffer.) If an unused buffer
6522                 * is encountered then there are no frames available.
6523                 */
6524
6525                if ( info->rx_buffer_list[EndIndex].count )
6526                        goto Cleanup;
6527
6528                /* advance to next buffer entry in linked list */
6529                EndIndex++;
6530                if ( EndIndex == info->rx_buffer_count )
6531                        EndIndex = 0;
6532
6533                /* if entire list searched then no frame available */
6534                if ( EndIndex == StartIndex ) {
6535                        /* If this occurs then something bad happened,
6536                         * all buffers have been 'used' but none mark
6537                         * the end of a frame. Reset buffers and receiver.
6538                         */
6539
6540                        if ( info->rx_enabled ){
6541                                spin_lock_irqsave(&info->irq_spinlock,flags);
6542                                usc_start_receiver(info);
6543                                spin_unlock_irqrestore(&info->irq_spinlock,flags);
6544                        }
6545                        goto Cleanup;
6546                }
6547        }
6548
6549
6550        /* check status of receive frame */
6551        
6552        status = info->rx_buffer_list[EndIndex].status;
6553
6554        if ( status & (RXSTATUS_SHORT_FRAME | RXSTATUS_OVERRUN |
6555                        RXSTATUS_CRC_ERROR | RXSTATUS_ABORT) ) {
6556                if ( status & RXSTATUS_SHORT_FRAME )
6557                        info->icount.rxshort++;
6558                else if ( status & RXSTATUS_ABORT )
6559                        info->icount.rxabort++;
6560                else if ( status & RXSTATUS_OVERRUN )
6561                        info->icount.rxover++;
6562                else {
6563                        info->icount.rxcrc++;
6564                        if ( info->params.crc_type & HDLC_CRC_RETURN_EX )
6565                                return_frame = true;
6566                }
6567                framesize = 0;
6568#if SYNCLINK_GENERIC_HDLC
6569                {
6570                        info->netdev->stats.rx_errors++;
6571                        info->netdev->stats.rx_frame_errors++;
6572                }
6573#endif
6574        } else
6575                return_frame = true;
6576
6577        if ( return_frame ) {
6578                /* receive frame has no errors, get frame size.
6579                 * The frame size is the starting value of the RCC (which was
6580                 * set to 0xffff) minus the ending value of the RCC (decremented
6581                 * once for each receive character) minus 2 for the 16-bit CRC.
6582                 */
6583
6584                framesize = RCLRVALUE - info->rx_buffer_list[EndIndex].rcc;
6585
6586                /* adjust frame size for CRC if any */
6587                if ( info->params.crc_type == HDLC_CRC_16_CCITT )
6588                        framesize -= 2;
6589                else if ( info->params.crc_type == HDLC_CRC_32_CCITT )
6590                        framesize -= 4;         
6591        }
6592
6593        if ( debug_level >= DEBUG_LEVEL_BH )
6594                printk("%s(%d):mgsl_get_rx_frame(%s) status=%04X size=%d\n",
6595                        __FILE__,__LINE__,info->device_name,status,framesize);
6596                        
6597        if ( debug_level >= DEBUG_LEVEL_DATA )
6598                mgsl_trace_block(info,info->rx_buffer_list[StartIndex].virt_addr,
6599                        min_t(int, framesize, DMABUFFERSIZE),0);
6600                
6601        if (framesize) {
6602                if ( ( (info->params.crc_type & HDLC_CRC_RETURN_EX) &&
6603                                ((framesize+1) > info->max_frame_size) ) ||
6604                        (framesize > info->max_frame_size) )
6605                        info->icount.rxlong++;
6606                else {
6607                        /* copy dma buffer(s) to contiguous intermediate buffer */
6608                        int copy_count = framesize;
6609                        int index = StartIndex;
6610                        unsigned char *ptmp = info->intermediate_rxbuffer;
6611
6612                        if ( !(status & RXSTATUS_CRC_ERROR))
6613                                info->icount.rxok++;
6614                        
6615                        while(copy_count) {
6616                                int partial_count;
6617                                if ( copy_count > DMABUFFERSIZE )
6618                                        partial_count = DMABUFFERSIZE;
6619                                else
6620                                        partial_count = copy_count;
6621                        
6622                                pBufEntry = &(info->rx_buffer_list[index]);
6623                                memcpy( ptmp, pBufEntry->virt_addr, partial_count );
6624                                ptmp += partial_count;
6625                                copy_count -= partial_count;
6626                                
6627                                if ( ++index == info->rx_buffer_count )
6628                                        index = 0;
6629                        }
6630
6631                        if ( info->params.crc_type & HDLC_CRC_RETURN_EX ) {
6632                                ++framesize;
6633                                *ptmp = (status & RXSTATUS_CRC_ERROR ?
6634                                                RX_CRC_ERROR :
6635                                                RX_OK);
6636
6637                                if ( debug_level >= DEBUG_LEVEL_DATA )
6638                                        printk("%s(%d):mgsl_get_rx_frame(%s) rx frame status=%d\n",
6639                                                __FILE__,__LINE__,info->device_name,
6640                                                *ptmp);
6641                        }
6642
6643#if SYNCLINK_GENERIC_HDLC
6644                        if (info->netcount)
6645                                hdlcdev_rx(info,info->intermediate_rxbuffer,framesize);
6646                        else
6647#endif
6648                                ldisc_receive_buf(tty, info->intermediate_rxbuffer, info->flag_buf, framesize);
6649                }
6650        }
6651        /* Free the buffers used by this frame. */
6652        mgsl_free_rx_frame_buffers( info, StartIndex, EndIndex );
6653
6654        ReturnCode = true;
6655
6656Cleanup:
6657
6658        if ( info->rx_enabled && info->rx_overflow ) {
6659                /* The receiver needs to restarted because of 
6660                 * a receive overflow (buffer or FIFO). If the 
6661                 * receive buffers are now empty, then restart receiver.
6662                 */
6663
6664                if ( !info->rx_buffer_list[EndIndex].status &&
6665                        info->rx_buffer_list[EndIndex].count ) {
6666                        spin_lock_irqsave(&info->irq_spinlock,flags);
6667                        usc_start_receiver(info);
6668                        spin_unlock_irqrestore(&info->irq_spinlock,flags);
6669                }
6670        }
6671
6672        return ReturnCode;
6673
6674}       /* end of mgsl_get_rx_frame() */
6675
6676/* mgsl_get_raw_rx_frame()
6677 *
6678 *      This function attempts to return a received frame from the
6679 *      receive DMA buffers when running in external loop mode. In this mode,
6680 *      we will return at most one DMABUFFERSIZE frame to the application.
6681 *      The USC receiver is triggering off of DCD going active to start a new
6682 *      frame, and DCD going inactive to terminate the frame (similar to
6683 *      processing a closing flag character).
6684 *
6685 *      In this routine, we will return DMABUFFERSIZE "chunks" at a time.
6686 *      If DCD goes inactive, the last Rx DMA Buffer will have a non-zero
6687 *      status field and the RCC field will indicate the length of the
6688 *      entire received frame. We take this RCC field and get the modulus
6689 *      of RCC and DMABUFFERSIZE to determine if number of bytes in the
6690 *      last Rx DMA buffer and return that last portion of the frame.
6691 *
6692 * Arguments:           info    pointer to device extension
6693 * Return Value:        true if frame returned, otherwise false
6694 */
6695static bool mgsl_get_raw_rx_frame(struct mgsl_struct *info)
6696{
6697        unsigned int CurrentIndex, NextIndex;
6698        unsigned short status;
6699        DMABUFFERENTRY *pBufEntry;
6700        unsigned int framesize = 0;
6701        bool ReturnCode = false;
6702        unsigned long flags;
6703        struct tty_struct *tty = info->port.tty;
6704
6705        /*
6706         * current_rx_buffer points to the 1st buffer of the next available
6707         * receive frame. The status field is set by the 16C32 after
6708         * completing a receive frame. If the status field of this buffer
6709         * is zero, either the USC is still filling this buffer or this
6710         * is one of a series of buffers making up a received frame.
6711         *
6712         * If the count field of this buffer is zero, the USC is either
6713         * using this buffer or has used this buffer. Look at the count
6714         * field of the next buffer. If that next buffer's count is
6715         * non-zero, the USC is still actively using the current buffer.
6716         * Otherwise, if the next buffer's count field is zero, the
6717         * current buffer is complete and the USC is using the next
6718         * buffer.
6719         */
6720        CurrentIndex = NextIndex = info->current_rx_buffer;
6721        ++NextIndex;
6722        if ( NextIndex == info->rx_buffer_count )
6723                NextIndex = 0;
6724
6725        if ( info->rx_buffer_list[CurrentIndex].status != 0 ||
6726                (info->rx_buffer_list[CurrentIndex].count == 0 &&
6727                        info->rx_buffer_list[NextIndex].count == 0)) {
6728                /*
6729                 * Either the status field of this dma buffer is non-zero
6730                 * (indicating the last buffer of a receive frame) or the next
6731                 * buffer is marked as in use -- implying this buffer is complete
6732                 * and an intermediate buffer for this received frame.
6733                 */
6734
6735                status = info->rx_buffer_list[CurrentIndex].status;
6736
6737                if ( status & (RXSTATUS_SHORT_FRAME | RXSTATUS_OVERRUN |
6738                                RXSTATUS_CRC_ERROR | RXSTATUS_ABORT) ) {
6739                        if ( status & RXSTATUS_SHORT_FRAME )
6740                                info->icount.rxshort++;
6741                        else if ( status & RXSTATUS_ABORT )
6742                                info->icount.rxabort++;
6743                        else if ( status & RXSTATUS_OVERRUN )
6744                                info->icount.rxover++;
6745                        else
6746                                info->icount.rxcrc++;
6747                        framesize = 0;
6748                } else {
6749                        /*
6750                         * A receive frame is available, get frame size and status.
6751                         *
6752                         * The frame size is the starting value of the RCC (which was
6753                         * set to 0xffff) minus the ending value of the RCC (decremented
6754                         * once for each receive character) minus 2 or 4 for the 16-bit
6755                         * or 32-bit CRC.
6756                         *
6757                         * If the status field is zero, this is an intermediate buffer.
6758                         * It's size is 4K.
6759                         *
6760                         * If the DMA Buffer Entry's Status field is non-zero, the
6761                         * receive operation completed normally (ie: DCD dropped). The
6762                         * RCC field is valid and holds the received frame size.
6763                         * It is possible that the RCC field will be zero on a DMA buffer
6764                         * entry with a non-zero status. This can occur if the total
6765                         * frame size (number of bytes between the time DCD goes active
6766                         * to the time DCD goes inactive) exceeds 65535 bytes. In this
6767                         * case the 16C32 has underrun on the RCC count and appears to
6768                         * stop updating this counter to let us know the actual received
6769                         * frame size. If this happens (non-zero status and zero RCC),
6770                         * simply return the entire RxDMA Buffer
6771                         */
6772                        if ( status ) {
6773                                /*
6774                                 * In the event that the final RxDMA Buffer is
6775                                 * terminated with a non-zero status and the RCC
6776                                 * field is zero, we interpret this as the RCC
6777                                 * having underflowed (received frame > 65535 bytes).
6778                                 *
6779                                 * Signal the event to the user by passing back
6780                                 * a status of RxStatus_CrcError returning the full
6781                                 * buffer and let the app figure out what data is
6782                                 * actually valid
6783                                 */
6784                                if ( info->rx_buffer_list[CurrentIndex].rcc )
6785                                        framesize = RCLRVALUE - info->rx_buffer_list[CurrentIndex].rcc;
6786                                else
6787                                        framesize = DMABUFFERSIZE;
6788                        }
6789                        else
6790                                framesize = DMABUFFERSIZE;
6791                }
6792
6793                if ( framesize > DMABUFFERSIZE ) {
6794                        /*
6795                         * if running in raw sync mode, ISR handler for
6796                         * End Of Buffer events terminates all buffers at 4K.
6797                         * If this frame size is said to be >4K, get the
6798                         * actual number of bytes of the frame in this buffer.
6799                         */
6800                        framesize = framesize % DMABUFFERSIZE;
6801                }
6802
6803
6804                if ( debug_level >= DEBUG_LEVEL_BH )
6805                        printk("%s(%d):mgsl_get_raw_rx_frame(%s) status=%04X size=%d\n",
6806                                __FILE__,__LINE__,info->device_name,status,framesize);
6807
6808                if ( debug_level >= DEBUG_LEVEL_DATA )
6809                        mgsl_trace_block(info,info->rx_buffer_list[CurrentIndex].virt_addr,
6810                                min_t(int, framesize, DMABUFFERSIZE),0);
6811
6812                if (framesize) {
6813                        /* copy dma buffer(s) to contiguous intermediate buffer */
6814                        /* NOTE: we never copy more than DMABUFFERSIZE bytes    */
6815
6816                        pBufEntry = &(info->rx_buffer_list[CurrentIndex]);
6817                        memcpy( info->intermediate_rxbuffer, pBufEntry->virt_addr, framesize);
6818                        info->icount.rxok++;
6819
6820                        ldisc_receive_buf(tty, info->intermediate_rxbuffer, info->flag_buf, framesize);
6821                }
6822
6823                /* Free the buffers used by this frame. */
6824                mgsl_free_rx_frame_buffers( info, CurrentIndex, CurrentIndex );
6825
6826                ReturnCode = true;
6827        }
6828
6829
6830        if ( info->rx_enabled && info->rx_overflow ) {
6831                /* The receiver needs to restarted because of
6832                 * a receive overflow (buffer or FIFO). If the
6833                 * receive buffers are now empty, then restart receiver.
6834                 */
6835
6836                if ( !info->rx_buffer_list[CurrentIndex].status &&
6837                        info->rx_buffer_list[CurrentIndex].count ) {
6838                        spin_lock_irqsave(&info->irq_spinlock,flags);
6839                        usc_start_receiver(info);
6840                        spin_unlock_irqrestore(&info->irq_spinlock,flags);
6841                }
6842        }
6843
6844        return ReturnCode;
6845
6846}       /* end of mgsl_get_raw_rx_frame() */
6847
6848/* mgsl_load_tx_dma_buffer()
6849 * 
6850 *      Load the transmit DMA buffer with the specified data.
6851 * 
6852 * Arguments:
6853 * 
6854 *      info            pointer to device extension
6855 *      Buffer          pointer to buffer containing frame to load
6856 *      BufferSize      size in bytes of frame in Buffer
6857 * 
6858 * Return Value:        None
6859 */
6860static void mgsl_load_tx_dma_buffer(struct mgsl_struct *info,
6861                const char *Buffer, unsigned int BufferSize)
6862{
6863        unsigned short Copycount;
6864        unsigned int i = 0;
6865        DMABUFFERENTRY *pBufEntry;
6866        
6867        if ( debug_level >= DEBUG_LEVEL_DATA )
6868                mgsl_trace_block(info,Buffer, min_t(int, BufferSize, DMABUFFERSIZE), 1);
6869
6870        if (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) {
6871                /* set CMR:13 to start transmit when
6872                 * next GoAhead (abort) is received
6873                 */
6874                info->cmr_value |= BIT13;
6875        }
6876                
6877        /* begin loading the frame in the next available tx dma
6878         * buffer, remember it's starting location for setting
6879         * up tx dma operation
6880         */
6881        i = info->current_tx_buffer;
6882        info->start_tx_dma_buffer = i;
6883
6884        /* Setup the status and RCC (Frame Size) fields of the 1st */
6885        /* buffer entry in the transmit DMA buffer list. */
6886
6887        info->tx_buffer_list[i].status = info->cmr_value & 0xf000;
6888        info->tx_buffer_list[i].rcc    = BufferSize;
6889        info->tx_buffer_list[i].count  = BufferSize;
6890
6891        /* Copy frame data from 1st source buffer to the DMA buffers. */
6892        /* The frame data may span multiple DMA buffers. */
6893
6894        while( BufferSize ){
6895                /* Get a pointer to next DMA buffer entry. */
6896                pBufEntry = &info->tx_buffer_list[i++];
6897                        
6898                if ( i == info->tx_buffer_count )
6899                        i=0;
6900
6901                /* Calculate the number of bytes that can be copied from */
6902                /* the source buffer to this DMA buffer. */
6903                if ( BufferSize > DMABUFFERSIZE )
6904                        Copycount = DMABUFFERSIZE;
6905                else
6906                        Copycount = BufferSize;
6907
6908                /* Actually copy data from source buffer to DMA buffer. */
6909                /* Also set the data count for this individual DMA buffer. */
6910                if ( info->bus_type == MGSL_BUS_TYPE_PCI )
6911                        mgsl_load_pci_memory(pBufEntry->virt_addr, Buffer,Copycount);
6912                else
6913                        memcpy(pBufEntry->virt_addr, Buffer, Copycount);
6914
6915                pBufEntry->count = Copycount;
6916
6917                /* Advance source pointer and reduce remaining data count. */
6918                Buffer += Copycount;
6919                BufferSize -= Copycount;
6920
6921                ++info->tx_dma_buffers_used;
6922        }
6923
6924        /* remember next available tx dma buffer */
6925        info->current_tx_buffer = i;
6926
6927}       /* end of mgsl_load_tx_dma_buffer() */
6928
6929/*
6930 * mgsl_register_test()
6931 * 
6932 *      Performs a register test of the 16C32.
6933 *      
6934 * Arguments:           info    pointer to device instance data
6935 * Return Value:                true if test passed, otherwise false
6936 */
6937static bool mgsl_register_test( struct mgsl_struct *info )
6938{
6939        static unsigned short BitPatterns[] =
6940                { 0x0000, 0xffff, 0xaaaa, 0x5555, 0x1234, 0x6969, 0x9696, 0x0f0f };
6941        static unsigned int Patterncount = ARRAY_SIZE(BitPatterns);
6942        unsigned int i;
6943        bool rc = true;
6944        unsigned long flags;
6945
6946        spin_lock_irqsave(&info->irq_spinlock,flags);
6947        usc_reset(info);
6948
6949        /* Verify the reset state of some registers. */
6950
6951        if ( (usc_InReg( info, SICR ) != 0) ||
6952                  (usc_InReg( info, IVR  ) != 0) ||
6953                  (usc_InDmaReg( info, DIVR ) != 0) ){
6954                rc = false;
6955        }
6956
6957        if ( rc ){
6958                /* Write bit patterns to various registers but do it out of */
6959                /* sync, then read back and verify values. */
6960
6961                for ( i = 0 ; i < Patterncount ; i++ ) {
6962                        usc_OutReg( info, TC0R, BitPatterns[i] );
6963                        usc_OutReg( info, TC1R, BitPatterns[(i+1)%Patterncount] );
6964                        usc_OutReg( info, TCLR, BitPatterns[(i+2)%Patterncount] );
6965                        usc_OutReg( info, RCLR, BitPatterns[(i+3)%Patterncount] );
6966                        usc_OutReg( info, RSR,  BitPatterns[(i+4)%Patterncount] );
6967                        usc_OutDmaReg( info, TBCR, BitPatterns[(i+5)%Patterncount] );
6968
6969                        if ( (usc_InReg( info, TC0R ) != BitPatterns[i]) ||
6970                                  (usc_InReg( info, TC1R ) != BitPatterns[(i+1)%Patterncount]) ||
6971                                  (usc_InReg( info, TCLR ) != BitPatterns[(i+2)%Patterncount]) ||
6972                                  (usc_InReg( info, RCLR ) != BitPatterns[(i+3)%Patterncount]) ||
6973                                  (usc_InReg( info, RSR )  != BitPatterns[(i+4)%Patterncount]) ||
6974                                  (usc_InDmaReg( info, TBCR ) != BitPatterns[(i+5)%Patterncount]) ){
6975                                rc = false;
6976                                break;
6977                        }
6978                }
6979        }
6980
6981        usc_reset(info);
6982        spin_unlock_irqrestore(&info->irq_spinlock,flags);
6983
6984        return rc;
6985
6986}       /* end of mgsl_register_test() */
6987
6988/* mgsl_irq_test()      Perform interrupt test of the 16C32.
6989 * 
6990 * Arguments:           info    pointer to device instance data
6991 * Return Value:        true if test passed, otherwise false
6992 */
6993static bool mgsl_irq_test( struct mgsl_struct *info )
6994{
6995        unsigned long EndTime;
6996        unsigned long flags;
6997
6998        spin_lock_irqsave(&info->irq_spinlock,flags);
6999        usc_reset(info);
7000
7001        /*
7002         * Setup 16C32 to interrupt on TxC pin (14MHz clock) transition. 
7003         * The ISR sets irq_occurred to true.
7004         */
7005
7006        info->irq_occurred = false;
7007
7008        /* Enable INTEN gate for ISA adapter (Port 6, Bit12) */
7009        /* Enable INTEN (Port 6, Bit12) */
7010        /* This connects the IRQ request signal to the ISA bus */
7011        /* on the ISA adapter. This has no effect for the PCI adapter */
7012        usc_OutReg( info, PCR, (unsigned short)((usc_InReg(info, PCR) | BIT13) & ~BIT12) );
7013
7014        usc_EnableMasterIrqBit(info);
7015        usc_EnableInterrupts(info, IO_PIN);
7016        usc_ClearIrqPendingBits(info, IO_PIN);
7017        
7018        usc_UnlatchIostatusBits(info, MISCSTATUS_TXC_LATCHED);
7019        usc_EnableStatusIrqs(info, SICR_TXC_ACTIVE + SICR_TXC_INACTIVE);
7020
7021        spin_unlock_irqrestore(&info->irq_spinlock,flags);
7022
7023        EndTime=100;
7024        while( EndTime-- && !info->irq_occurred ) {
7025                msleep_interruptible(10);
7026        }
7027        
7028        spin_lock_irqsave(&info->irq_spinlock,flags);
7029        usc_reset(info);
7030        spin_unlock_irqrestore(&info->irq_spinlock,flags);
7031        
7032        return info->irq_occurred;
7033
7034}       /* end of mgsl_irq_test() */
7035
7036/* mgsl_dma_test()
7037 * 
7038 *      Perform a DMA test of the 16C32. A small frame is
7039 *      transmitted via DMA from a transmit buffer to a receive buffer
7040 *      using single buffer DMA mode.
7041 *      
7042 * Arguments:           info    pointer to device instance data
7043 * Return Value:        true if test passed, otherwise false
7044 */
7045static bool mgsl_dma_test( struct mgsl_struct *info )
7046{
7047        unsigned short FifoLevel;
7048        unsigned long phys_addr;
7049        unsigned int FrameSize;
7050        unsigned int i;
7051        char *TmpPtr;
7052        bool rc = true;
7053        unsigned short status=0;
7054        unsigned long EndTime;
7055        unsigned long flags;
7056        MGSL_PARAMS tmp_params;
7057
7058        /* save current port options */
7059        memcpy(&tmp_params,&info->params,sizeof(MGSL_PARAMS));
7060        /* load default port options */
7061        memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
7062        
7063#define TESTFRAMESIZE 40
7064
7065        spin_lock_irqsave(&info->irq_spinlock,flags);
7066        
7067        /* setup 16C32 for SDLC DMA transfer mode */
7068
7069        usc_reset(info);
7070        usc_set_sdlc_mode(info);
7071        usc_enable_loopback(info,1);
7072        
7073        /* Reprogram the RDMR so that the 16C32 does NOT clear the count
7074         * field of the buffer entry after fetching buffer address. This
7075         * way we can detect a DMA failure for a DMA read (which should be
7076         * non-destructive to system memory) before we try and write to
7077         * memory (where a failure could corrupt system memory).
7078         */
7079
7080        /* Receive DMA mode Register (RDMR)
7081         * 
7082         * <15..14>     11      DMA mode = Linked List Buffer mode
7083         * <13>         1       RSBinA/L = store Rx status Block in List entry
7084         * <12>         0       1 = Clear count of List Entry after fetching
7085         * <11..10>     00      Address mode = Increment
7086         * <9>          1       Terminate Buffer on RxBound
7087         * <8>          0       Bus Width = 16bits
7088         * <7..0>               ?       status Bits (write as 0s)
7089         * 
7090         * 1110 0010 0000 0000 = 0xe200
7091         */
7092
7093        usc_OutDmaReg( info, RDMR, 0xe200 );
7094        
7095        spin_unlock_irqrestore(&info->irq_spinlock,flags);
7096
7097
7098        /* SETUP TRANSMIT AND RECEIVE DMA BUFFERS */
7099
7100        FrameSize = TESTFRAMESIZE;
7101
7102        /* setup 1st transmit buffer entry: */
7103        /* with frame size and transmit control word */
7104
7105        info->tx_buffer_list[0].count  = FrameSize;
7106        info->tx_buffer_list[0].rcc    = FrameSize;
7107        info->tx_buffer_list[0].status = 0x4000;
7108
7109        /* build a transmit frame in 1st transmit DMA buffer */
7110
7111        TmpPtr = info->tx_buffer_list[0].virt_addr;
7112        for (i = 0; i < FrameSize; i++ )
7113                *TmpPtr++ = i;
7114
7115        /* setup 1st receive buffer entry: */
7116        /* clear status, set max receive buffer size */
7117
7118        info->rx_buffer_list[0].status = 0;
7119        info->rx_buffer_list[0].count = FrameSize + 4;
7120
7121        /* zero out the 1st receive buffer */
7122
7123        memset( info->rx_buffer_list[0].virt_addr, 0, FrameSize + 4 );
7124
7125        /* Set count field of next buffer entries to prevent */
7126        /* 16C32 from using buffers after the 1st one. */
7127
7128        info->tx_buffer_list[1].count = 0;
7129        info->rx_buffer_list[1].count = 0;
7130        
7131
7132        /***************************/
7133        /* Program 16C32 receiver. */
7134        /***************************/
7135        
7136        spin_lock_irqsave(&info->irq_spinlock,flags);
7137
7138        /* setup DMA transfers */
7139        usc_RTCmd( info, RTCmd_PurgeRxFifo );
7140
7141        /* program 16C32 receiver with physical address of 1st DMA buffer entry */
7142        phys_addr = info->rx_buffer_list[0].phys_entry;
7143        usc_OutDmaReg( info, NRARL, (unsigned short)phys_addr );
7144        usc_OutDmaReg( info, NRARU, (unsigned short)(phys_addr >> 16) );
7145
7146        /* Clear the Rx DMA status bits (read RDMR) and start channel */
7147        usc_InDmaReg( info, RDMR );
7148        usc_DmaCmd( info, DmaCmd_InitRxChannel );
7149
7150        /* Enable Receiver (RMR <1..0> = 10) */
7151        usc_OutReg( info, RMR, (unsigned short)((usc_InReg(info, RMR) & 0xfffc) | 0x0002) );
7152        
7153        spin_unlock_irqrestore(&info->irq_spinlock,flags);
7154
7155
7156        /*************************************************************/
7157        /* WAIT FOR RECEIVER TO DMA ALL PARAMETERS FROM BUFFER ENTRY */
7158        /*************************************************************/
7159
7160        /* Wait 100ms for interrupt. */
7161        EndTime = jiffies + msecs_to_jiffies(100);
7162
7163        for(;;) {
7164                if (time_after(jiffies, EndTime)) {
7165                        rc = false;
7166                        break;
7167                }
7168
7169                spin_lock_irqsave(&info->irq_spinlock,flags);
7170                status = usc_InDmaReg( info, RDMR );
7171                spin_unlock_irqrestore(&info->irq_spinlock,flags);
7172
7173                if ( !(status & BIT4) && (status & BIT5) ) {
7174                        /* INITG (BIT 4) is inactive (no entry read in progress) AND */
7175                        /* BUSY  (BIT 5) is active (channel still active). */
7176                        /* This means the buffer entry read has completed. */
7177                        break;
7178                }
7179        }
7180
7181
7182        /******************************/
7183        /* Program 16C32 transmitter. */
7184        /******************************/
7185        
7186        spin_lock_irqsave(&info->irq_spinlock,flags);
7187
7188        /* Program the Transmit Character Length Register (TCLR) */
7189        /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
7190
7191        usc_OutReg( info, TCLR, (unsigned short)info->tx_buffer_list[0].count );
7192        usc_RTCmd( info, RTCmd_PurgeTxFifo );
7193
7194        /* Program the address of the 1st DMA Buffer Entry in linked list */
7195
7196        phys_addr = info->tx_buffer_list[0].phys_entry;
7197        usc_OutDmaReg( info, NTARL, (unsigned short)phys_addr );
7198        usc_OutDmaReg( info, NTARU, (unsigned short)(phys_addr >> 16) );
7199
7200        /* unlatch Tx status bits, and start transmit channel. */
7201
7202        usc_OutReg( info, TCSR, (unsigned short)(( usc_InReg(info, TCSR) & 0x0f00) | 0xfa) );
7203        usc_DmaCmd( info, DmaCmd_InitTxChannel );
7204
7205        /* wait for DMA controller to fill transmit FIFO */
7206
7207        usc_TCmd( info, TCmd_SelectTicrTxFifostatus );
7208        
7209        spin_unlock_irqrestore(&info->irq_spinlock,flags);
7210
7211
7212        /**********************************/
7213        /* WAIT FOR TRANSMIT FIFO TO FILL */
7214        /**********************************/
7215        
7216        /* Wait 100ms */
7217        EndTime = jiffies + msecs_to_jiffies(100);
7218
7219        for(;;) {
7220                if (time_after(jiffies, EndTime)) {
7221                        rc = false;
7222                        break;
7223                }
7224
7225                spin_lock_irqsave(&info->irq_spinlock,flags);
7226                FifoLevel = usc_InReg(info, TICR) >> 8;
7227                spin_unlock_irqrestore(&info->irq_spinlock,flags);
7228                        
7229                if ( FifoLevel < 16 )
7230                        break;
7231                else
7232                        if ( FrameSize < 32 ) {
7233                                /* This frame is smaller than the entire transmit FIFO */
7234                                /* so wait for the entire frame to be loaded. */
7235                                if ( FifoLevel <= (32 - FrameSize) )
7236                                        break;
7237                        }
7238        }
7239
7240
7241        if ( rc )
7242        {
7243                /* Enable 16C32 transmitter. */
7244
7245                spin_lock_irqsave(&info->irq_spinlock,flags);
7246                
7247                /* Transmit mode Register (TMR), <1..0> = 10, Enable Transmitter */
7248                usc_TCmd( info, TCmd_SendFrame );
7249                usc_OutReg( info, TMR, (unsigned short)((usc_InReg(info, TMR) & 0xfffc) | 0x0002) );
7250                
7251                spin_unlock_irqrestore(&info->irq_spinlock,flags);
7252
7253
7254                /******************************/
7255                /* WAIT FOR TRANSMIT COMPLETE */
7256                /******************************/
7257
7258                /* Wait 100ms */
7259                EndTime = jiffies + msecs_to_jiffies(100);
7260
7261                /* While timer not expired wait for transmit complete */
7262
7263                spin_lock_irqsave(&info->irq_spinlock,flags);
7264                status = usc_InReg( info, TCSR );
7265                spin_unlock_irqrestore(&info->irq_spinlock,flags);
7266
7267                while ( !(status & (BIT6 | BIT5 | BIT4 | BIT2 | BIT1)) ) {
7268                        if (time_after(jiffies, EndTime)) {
7269                                rc = false;
7270                                break;
7271                        }
7272
7273                        spin_lock_irqsave(&info->irq_spinlock,flags);
7274                        status = usc_InReg( info, TCSR );
7275                        spin_unlock_irqrestore(&info->irq_spinlock,flags);
7276                }
7277        }
7278
7279
7280        if ( rc ){
7281                /* CHECK FOR TRANSMIT ERRORS */
7282                if ( status & (BIT5 | BIT1) )
7283                        rc = false;
7284        }
7285
7286        if ( rc ) {
7287                /* WAIT FOR RECEIVE COMPLETE */
7288
7289                /* Wait 100ms */
7290                EndTime = jiffies + msecs_to_jiffies(100);
7291
7292                /* Wait for 16C32 to write receive status to buffer entry. */
7293                status=info->rx_buffer_list[0].status;
7294                while ( status == 0 ) {
7295                        if (time_after(jiffies, EndTime)) {
7296                                rc = false;
7297                                break;
7298                        }
7299                        status=info->rx_buffer_list[0].status;
7300                }
7301        }
7302
7303
7304        if ( rc ) {
7305                /* CHECK FOR RECEIVE ERRORS */
7306                status = info->rx_buffer_list[0].status;
7307
7308                if ( status & (BIT8 | BIT3 | BIT1) ) {
7309                        /* receive error has occurred */
7310                        rc = false;
7311                } else {
7312                        if ( memcmp( info->tx_buffer_list[0].virt_addr ,
7313                                info->rx_buffer_list[0].virt_addr, FrameSize ) ){
7314                                rc = false;
7315                        }
7316                }
7317        }
7318
7319        spin_lock_irqsave(&info->irq_spinlock,flags);
7320        usc_reset( info );
7321        spin_unlock_irqrestore(&info->irq_spinlock,flags);
7322
7323        /* restore current port options */
7324        memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
7325        
7326        return rc;
7327
7328}       /* end of mgsl_dma_test() */
7329
7330/* mgsl_adapter_test()
7331 * 
7332 *      Perform the register, IRQ, and DMA tests for the 16C32.
7333 *      
7334 * Arguments:           info    pointer to device instance data
7335 * Return Value:        0 if success, otherwise -ENODEV
7336 */
7337static int mgsl_adapter_test( struct mgsl_struct *info )
7338{
7339        if ( debug_level >= DEBUG_LEVEL_INFO )
7340                printk( "%s(%d):Testing device %s\n",
7341                        __FILE__,__LINE__,info->device_name );
7342                        
7343        if ( !mgsl_register_test( info ) ) {
7344                info->init_error = DiagStatus_AddressFailure;
7345                printk( "%s(%d):Register test failure for device %s Addr=%04X\n",
7346                        __FILE__,__LINE__,info->device_name, (unsigned short)(info->io_base) );
7347                return -ENODEV;
7348        }
7349
7350        if ( !mgsl_irq_test( info ) ) {
7351                info->init_error = DiagStatus_IrqFailure;
7352                printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
7353                        __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
7354                return -ENODEV;
7355        }
7356
7357        if ( !mgsl_dma_test( info ) ) {
7358                info->init_error = DiagStatus_DmaFailure;
7359                printk( "%s(%d):DMA test failure for device %s DMA=%d\n",
7360                        __FILE__,__LINE__,info->device_name, (unsigned short)(info->dma_level) );
7361                return -ENODEV;
7362        }
7363
7364        if ( debug_level >= DEBUG_LEVEL_INFO )
7365                printk( "%s(%d):device %s passed diagnostics\n",
7366                        __FILE__,__LINE__,info->device_name );
7367                        
7368        return 0;
7369
7370}       /* end of mgsl_adapter_test() */
7371
7372/* mgsl_memory_test()
7373 * 
7374 *      Test the shared memory on a PCI adapter.
7375 * 
7376 * Arguments:           info    pointer to device instance data
7377 * Return Value:        true if test passed, otherwise false
7378 */
7379static bool mgsl_memory_test( struct mgsl_struct *info )
7380{
7381        static unsigned long BitPatterns[] =
7382                { 0x0, 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
7383        unsigned long Patterncount = ARRAY_SIZE(BitPatterns);
7384        unsigned long i;
7385        unsigned long TestLimit = SHARED_MEM_ADDRESS_SIZE/sizeof(unsigned long);
7386        unsigned long * TestAddr;
7387
7388        if ( info->bus_type != MGSL_BUS_TYPE_PCI )
7389                return true;
7390
7391        TestAddr = (unsigned long *)info->memory_base;
7392
7393        /* Test data lines with test pattern at one location. */
7394
7395        for ( i = 0 ; i < Patterncount ; i++ ) {
7396                *TestAddr = BitPatterns[i];
7397                if ( *TestAddr != BitPatterns[i] )
7398                        return false;
7399        }
7400
7401        /* Test address lines with incrementing pattern over */
7402        /* entire address range. */
7403
7404        for ( i = 0 ; i < TestLimit ; i++ ) {
7405                *TestAddr = i * 4;
7406                TestAddr++;
7407        }
7408
7409        TestAddr = (unsigned long *)info->memory_base;
7410
7411        for ( i = 0 ; i < TestLimit ; i++ ) {
7412                if ( *TestAddr != i * 4 )
7413                        return false;
7414                TestAddr++;
7415        }
7416
7417        memset( info->memory_base, 0, SHARED_MEM_ADDRESS_SIZE );
7418
7419        return true;
7420
7421}       /* End Of mgsl_memory_test() */
7422
7423
7424/* mgsl_load_pci_memory()
7425 * 
7426 *      Load a large block of data into the PCI shared memory.
7427 *      Use this instead of memcpy() or memmove() to move data
7428 *      into the PCI shared memory.
7429 * 
7430 * Notes:
7431 * 
7432 *      This function prevents the PCI9050 interface chip from hogging
7433 *      the adapter local bus, which can starve the 16C32 by preventing
7434 *      16C32 bus master cycles.
7435 * 
7436 *      The PCI9050 documentation says that the 9050 will always release
7437 *      control of the local bus after completing the current read
7438 *      or write operation.
7439 * 
7440 *      It appears that as long as the PCI9050 write FIFO is full, the
7441 *      PCI9050 treats all of the writes as a single burst transaction
7442 *      and will not release the bus. This causes DMA latency problems
7443 *      at high speeds when copying large data blocks to the shared
7444 *      memory.
7445 * 
7446 *      This function in effect, breaks the a large shared memory write
7447 *      into multiple transations by interleaving a shared memory read
7448 *      which will flush the write FIFO and 'complete' the write
7449 *      transation. This allows any pending DMA request to gain control
7450 *      of the local bus in a timely fasion.
7451 * 
7452 * Arguments:
7453 * 
7454 *      TargetPtr       pointer to target address in PCI shared memory
7455 *      SourcePtr       pointer to source buffer for data
7456 *      count           count in bytes of data to copy
7457 *
7458 * Return Value:        None
7459 */
7460static void mgsl_load_pci_memory( char* TargetPtr, const char* SourcePtr,
7461        unsigned short count )
7462{
7463        /* 16 32-bit writes @ 60ns each = 960ns max latency on local bus */
7464#define PCI_LOAD_INTERVAL 64
7465
7466        unsigned short Intervalcount = count / PCI_LOAD_INTERVAL;
7467        unsigned short Index;
7468        unsigned long Dummy;
7469
7470        for ( Index = 0 ; Index < Intervalcount ; Index++ )
7471        {
7472                memcpy(TargetPtr, SourcePtr, PCI_LOAD_INTERVAL);
7473                Dummy = *((volatile unsigned long *)TargetPtr);
7474                TargetPtr += PCI_LOAD_INTERVAL;
7475                SourcePtr += PCI_LOAD_INTERVAL;
7476        }
7477
7478        memcpy( TargetPtr, SourcePtr, count % PCI_LOAD_INTERVAL );
7479
7480}       /* End Of mgsl_load_pci_memory() */
7481
7482static void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit)
7483{
7484        int i;
7485        int linecount;
7486        if (xmit)
7487                printk("%s tx data:\n",info->device_name);
7488        else
7489                printk("%s rx data:\n",info->device_name);
7490                
7491        while(count) {
7492                if (count > 16)
7493                        linecount = 16;
7494                else
7495                        linecount = count;
7496                        
7497                for(i=0;i<linecount;i++)
7498                        printk("%02X ",(unsigned char)data[i]);
7499                for(;i<17;i++)
7500                        printk("   ");
7501                for(i=0;i<linecount;i++) {
7502                        if (data[i]>=040 && data[i]<=0176)
7503                                printk("%c",data[i]);
7504                        else
7505                                printk(".");
7506                }
7507                printk("\n");
7508                
7509                data  += linecount;
7510                count -= linecount;
7511        }
7512}       /* end of mgsl_trace_block() */
7513
7514/* mgsl_tx_timeout()
7515 * 
7516 *      called when HDLC frame times out
7517 *      update stats and do tx completion processing
7518 *      
7519 * Arguments:   context         pointer to device instance data
7520 * Return Value:        None
7521 */
7522static void mgsl_tx_timeout(unsigned long context)
7523{
7524        struct mgsl_struct *info = (struct mgsl_struct*)context;
7525        unsigned long flags;
7526        
7527        if ( debug_level >= DEBUG_LEVEL_INFO )
7528                printk( "%s(%d):mgsl_tx_timeout(%s)\n",
7529                        __FILE__,__LINE__,info->device_name);
7530        if(info->tx_active &&
7531           (info->params.mode == MGSL_MODE_HDLC ||
7532            info->params.mode == MGSL_MODE_RAW) ) {
7533                info->icount.txtimeout++;
7534        }
7535        spin_lock_irqsave(&info->irq_spinlock,flags);
7536        info->tx_active = false;
7537        info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
7538
7539        if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
7540                usc_loopmode_cancel_transmit( info );
7541
7542        spin_unlock_irqrestore(&info->irq_spinlock,flags);
7543        
7544#if SYNCLINK_GENERIC_HDLC
7545        if (info->netcount)
7546                hdlcdev_tx_done(info);
7547        else
7548#endif
7549                mgsl_bh_transmit(info);
7550        
7551}       /* end of mgsl_tx_timeout() */
7552
7553/* signal that there are no more frames to send, so that
7554 * line is 'released' by echoing RxD to TxD when current
7555 * transmission is complete (or immediately if no tx in progress).
7556 */
7557static int mgsl_loopmode_send_done( struct mgsl_struct * info )
7558{
7559        unsigned long flags;
7560        
7561        spin_lock_irqsave(&info->irq_spinlock,flags);
7562        if (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) {
7563                if (info->tx_active)
7564                        info->loopmode_send_done_requested = true;
7565                else
7566                        usc_loopmode_send_done(info);
7567        }
7568        spin_unlock_irqrestore(&info->irq_spinlock,flags);
7569
7570        return 0;
7571}
7572
7573/* release the line by echoing RxD to TxD
7574 * upon completion of a transmit frame
7575 */
7576static void usc_loopmode_send_done( struct mgsl_struct * info )
7577{
7578        info->loopmode_send_done_requested = false;
7579        /* clear CMR:13 to 0 to start echoing RxData to TxData */
7580        info->cmr_value &= ~BIT13;
7581        usc_OutReg(info, CMR, info->cmr_value);
7582}
7583
7584/* abort a transmit in progress while in HDLC LoopMode
7585 */
7586static void usc_loopmode_cancel_transmit( struct mgsl_struct * info )
7587{
7588        /* reset tx dma channel and purge TxFifo */
7589        usc_RTCmd( info, RTCmd_PurgeTxFifo );
7590        usc_DmaCmd( info, DmaCmd_ResetTxChannel );
7591        usc_loopmode_send_done( info );
7592}
7593
7594/* for HDLC/SDLC LoopMode, setting CMR:13 after the transmitter is enabled
7595 * is an Insert Into Loop action. Upon receipt of a GoAhead sequence (RxAbort)
7596 * we must clear CMR:13 to begin repeating TxData to RxData
7597 */
7598static void usc_loopmode_insert_request( struct mgsl_struct * info )
7599{
7600        info->loopmode_insert_requested = true;
7601 
7602        /* enable RxAbort irq. On next RxAbort, clear CMR:13 to
7603         * begin repeating TxData on RxData (complete insertion)
7604         */
7605        usc_OutReg( info, RICR, 
7606                (usc_InReg( info, RICR ) | RXSTATUS_ABORT_RECEIVED ) );
7607                
7608        /* set CMR:13 to insert into loop on next GoAhead (RxAbort) */
7609        info->cmr_value |= BIT13;
7610        usc_OutReg(info, CMR, info->cmr_value);
7611}
7612
7613/* return 1 if station is inserted into the loop, otherwise 0
7614 */
7615static int usc_loopmode_active( struct mgsl_struct * info)
7616{
7617        return usc_InReg( info, CCSR ) & BIT7 ? 1 : 0 ;
7618}
7619
7620#if SYNCLINK_GENERIC_HDLC
7621
7622/**
7623 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
7624 * set encoding and frame check sequence (FCS) options
7625 *
7626 * dev       pointer to network device structure
7627 * encoding  serial encoding setting
7628 * parity    FCS setting
7629 *
7630 * returns 0 if success, otherwise error code
7631 */
7632static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
7633                          unsigned short parity)
7634{
7635        struct mgsl_struct *info = dev_to_port(dev);
7636        unsigned char  new_encoding;
7637        unsigned short new_crctype;
7638
7639        /* return error if TTY interface open */
7640        if (info->port.count)
7641                return -EBUSY;
7642
7643        switch (encoding)
7644        {
7645        case ENCODING_NRZ:        new_encoding = HDLC_ENCODING_NRZ; break;
7646        case ENCODING_NRZI:       new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
7647        case ENCODING_FM_MARK:    new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
7648        case ENCODING_FM_SPACE:   new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
7649        case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
7650        default: return -EINVAL;
7651        }
7652
7653        switch (parity)
7654        {
7655        case PARITY_NONE:            new_crctype = HDLC_CRC_NONE; break;
7656        case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
7657        case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
7658        default: return -EINVAL;
7659        }
7660
7661        info->params.encoding = new_encoding;
7662        info->params.crc_type = new_crctype;
7663
7664        /* if network interface up, reprogram hardware */
7665        if (info->netcount)
7666                mgsl_program_hw(info);
7667
7668        return 0;
7669}
7670
7671/**
7672 * called by generic HDLC layer to send frame
7673 *
7674 * skb  socket buffer containing HDLC frame
7675 * dev  pointer to network device structure
7676 */
7677static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
7678                                      struct net_device *dev)
7679{
7680        struct mgsl_struct *info = dev_to_port(dev);
7681        unsigned long flags;
7682
7683        if (debug_level >= DEBUG_LEVEL_INFO)
7684                printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
7685
7686        /* stop sending until this frame completes */
7687        netif_stop_queue(dev);
7688
7689        /* copy data to device buffers */
7690        info->xmit_cnt = skb->len;
7691        mgsl_load_tx_dma_buffer(info, skb->data, skb->len);
7692
7693        /* update network statistics */
7694        dev->stats.tx_packets++;
7695        dev->stats.tx_bytes += skb->len;
7696
7697        /* done with socket buffer, so free it */
7698        dev_kfree_skb(skb);
7699
7700        /* save start time for transmit timeout detection */
7701        netif_trans_update(dev);
7702
7703        /* start hardware transmitter if necessary */
7704        spin_lock_irqsave(&info->irq_spinlock,flags);
7705        if (!info->tx_active)
7706                usc_start_transmitter(info);
7707        spin_unlock_irqrestore(&info->irq_spinlock,flags);
7708
7709        return NETDEV_TX_OK;
7710}
7711
7712/**
7713 * called by network layer when interface enabled
7714 * claim resources and initialize hardware
7715 *
7716 * dev  pointer to network device structure
7717 *
7718 * returns 0 if success, otherwise error code
7719 */
7720static int hdlcdev_open(struct net_device *dev)
7721{
7722        struct mgsl_struct *info = dev_to_port(dev);
7723        int rc;
7724        unsigned long flags;
7725
7726        if (debug_level >= DEBUG_LEVEL_INFO)
7727                printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
7728
7729        /* generic HDLC layer open processing */
7730        rc = hdlc_open(dev);
7731        if (rc)
7732                return rc;
7733
7734        /* arbitrate between network and tty opens */
7735        spin_lock_irqsave(&info->netlock, flags);
7736        if (info->port.count != 0 || info->netcount != 0) {
7737                printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
7738                spin_unlock_irqrestore(&info->netlock, flags);
7739                return -EBUSY;
7740        }
7741        info->netcount=1;
7742        spin_unlock_irqrestore(&info->netlock, flags);
7743
7744        /* claim resources and init adapter */
7745        if ((rc = startup(info)) != 0) {
7746                spin_lock_irqsave(&info->netlock, flags);
7747                info->netcount=0;
7748                spin_unlock_irqrestore(&info->netlock, flags);
7749                return rc;
7750        }
7751
7752        /* assert RTS and DTR, apply hardware settings */
7753        info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
7754        mgsl_program_hw(info);
7755
7756        /* enable network layer transmit */
7757        netif_trans_update(dev);
7758        netif_start_queue(dev);
7759
7760        /* inform generic HDLC layer of current DCD status */
7761        spin_lock_irqsave(&info->irq_spinlock, flags);
7762        usc_get_serial_signals(info);
7763        spin_unlock_irqrestore(&info->irq_spinlock, flags);
7764        if (info->serial_signals & SerialSignal_DCD)
7765                netif_carrier_on(dev);
7766        else
7767                netif_carrier_off(dev);
7768        return 0;
7769}
7770
7771/**
7772 * called by network layer when interface is disabled
7773 * shutdown hardware and release resources
7774 *
7775 * dev  pointer to network device structure
7776 *
7777 * returns 0 if success, otherwise error code
7778 */
7779static int hdlcdev_close(struct net_device *dev)
7780{
7781        struct mgsl_struct *info = dev_to_port(dev);
7782        unsigned long flags;
7783
7784        if (debug_level >= DEBUG_LEVEL_INFO)
7785                printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
7786
7787        netif_stop_queue(dev);
7788
7789        /* shutdown adapter and release resources */
7790        shutdown(info);
7791
7792        hdlc_close(dev);
7793
7794        spin_lock_irqsave(&info->netlock, flags);
7795        info->netcount=0;
7796        spin_unlock_irqrestore(&info->netlock, flags);
7797
7798        return 0;
7799}
7800
7801/**
7802 * called by network layer to process IOCTL call to network device
7803 *
7804 * dev  pointer to network device structure
7805 * ifr  pointer to network interface request structure
7806 * cmd  IOCTL command code
7807 *
7808 * returns 0 if success, otherwise error code
7809 */
7810static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7811{
7812        const size_t size = sizeof(sync_serial_settings);
7813        sync_serial_settings new_line;
7814        sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
7815        struct mgsl_struct *info = dev_to_port(dev);
7816        unsigned int flags;
7817
7818        if (debug_level >= DEBUG_LEVEL_INFO)
7819                printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
7820
7821        /* return error if TTY interface open */
7822        if (info->port.count)
7823                return -EBUSY;
7824
7825        if (cmd != SIOCWANDEV)
7826                return hdlc_ioctl(dev, ifr, cmd);
7827
7828        switch(ifr->ifr_settings.type) {
7829        case IF_GET_IFACE: /* return current sync_serial_settings */
7830
7831                ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
7832                if (ifr->ifr_settings.size < size) {
7833                        ifr->ifr_settings.size = size; /* data size wanted */
7834                        return -ENOBUFS;
7835                }
7836
7837                flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
7838                                              HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
7839                                              HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
7840                                              HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
7841
7842                memset(&new_line, 0, sizeof(new_line));
7843                switch (flags){
7844                case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
7845                case (HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_INT; break;
7846                case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_TXINT; break;
7847                case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
7848                default: new_line.clock_type = CLOCK_DEFAULT;
7849                }
7850
7851                new_line.clock_rate = info->params.clock_speed;
7852                new_line.loopback   = info->params.loopback ? 1:0;
7853
7854                if (copy_to_user(line, &new_line, size))
7855                        return -EFAULT;
7856                return 0;
7857
7858        case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
7859
7860                if(!capable(CAP_NET_ADMIN))
7861                        return -EPERM;
7862                if (copy_from_user(&new_line, line, size))
7863                        return -EFAULT;
7864
7865                switch (new_line.clock_type)
7866                {
7867                case CLOCK_EXT:      flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
7868                case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
7869                case CLOCK_INT:      flags = HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG;    break;
7870                case CLOCK_TXINT:    flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG;    break;
7871                case CLOCK_DEFAULT:  flags = info->params.flags &
7872                                             (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
7873                                              HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
7874                                              HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
7875                                              HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN); break;
7876                default: return -EINVAL;
7877                }
7878
7879                if (new_line.loopback != 0 && new_line.loopback != 1)
7880                        return -EINVAL;
7881
7882                info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
7883                                        HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
7884                                        HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
7885                                        HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
7886                info->params.flags |= flags;
7887
7888                info->params.loopback = new_line.loopback;
7889
7890                if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
7891                        info->params.clock_speed = new_line.clock_rate;
7892                else
7893                        info->params.clock_speed = 0;
7894
7895                /* if network interface up, reprogram hardware */
7896                if (info->netcount)
7897                        mgsl_program_hw(info);
7898                return 0;
7899
7900        default:
7901                return hdlc_ioctl(dev, ifr, cmd);
7902        }
7903}
7904
7905/**
7906 * called by network layer when transmit timeout is detected
7907 *
7908 * dev  pointer to network device structure
7909 */
7910static void hdlcdev_tx_timeout(struct net_device *dev)
7911{
7912        struct mgsl_struct *info = dev_to_port(dev);
7913        unsigned long flags;
7914
7915        if (debug_level >= DEBUG_LEVEL_INFO)
7916                printk("hdlcdev_tx_timeout(%s)\n",dev->name);
7917
7918        dev->stats.tx_errors++;
7919        dev->stats.tx_aborted_errors++;
7920
7921        spin_lock_irqsave(&info->irq_spinlock,flags);
7922        usc_stop_transmitter(info);
7923        spin_unlock_irqrestore(&info->irq_spinlock,flags);
7924
7925        netif_wake_queue(dev);
7926}
7927
7928/**
7929 * called by device driver when transmit completes
7930 * reenable network layer transmit if stopped
7931 *
7932 * info  pointer to device instance information
7933 */
7934static void hdlcdev_tx_done(struct mgsl_struct *info)
7935{
7936        if (netif_queue_stopped(info->netdev))
7937                netif_wake_queue(info->netdev);
7938}
7939
7940/**
7941 * called by device driver when frame received
7942 * pass frame to network layer
7943 *
7944 * info  pointer to device instance information
7945 * buf   pointer to buffer contianing frame data
7946 * size  count of data bytes in buf
7947 */
7948static void hdlcdev_rx(struct mgsl_struct *info, char *buf, int size)
7949{
7950        struct sk_buff *skb = dev_alloc_skb(size);
7951        struct net_device *dev = info->netdev;
7952
7953        if (debug_level >= DEBUG_LEVEL_INFO)
7954                printk("hdlcdev_rx(%s)\n", dev->name);
7955
7956        if (skb == NULL) {
7957                printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n",
7958                       dev->name);
7959                dev->stats.rx_dropped++;
7960                return;
7961        }
7962
7963        memcpy(skb_put(skb, size), buf, size);
7964
7965        skb->protocol = hdlc_type_trans(skb, dev);
7966
7967        dev->stats.rx_packets++;
7968        dev->stats.rx_bytes += size;
7969
7970        netif_rx(skb);
7971}
7972
7973static const struct net_device_ops hdlcdev_ops = {
7974        .ndo_open       = hdlcdev_open,
7975        .ndo_stop       = hdlcdev_close,
7976        .ndo_change_mtu = hdlc_change_mtu,
7977        .ndo_start_xmit = hdlc_start_xmit,
7978        .ndo_do_ioctl   = hdlcdev_ioctl,
7979        .ndo_tx_timeout = hdlcdev_tx_timeout,
7980};
7981
7982/**
7983 * called by device driver when adding device instance
7984 * do generic HDLC initialization
7985 *
7986 * info  pointer to device instance information
7987 *
7988 * returns 0 if success, otherwise error code
7989 */
7990static int hdlcdev_init(struct mgsl_struct *info)
7991{
7992        int rc;
7993        struct net_device *dev;
7994        hdlc_device *hdlc;
7995
7996        /* allocate and initialize network and HDLC layer objects */
7997
7998        dev = alloc_hdlcdev(info);
7999        if (!dev) {
8000                printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
8001                return -ENOMEM;
8002        }
8003
8004        /* for network layer reporting purposes only */
8005        dev->base_addr = info->io_base;
8006        dev->irq       = info->irq_level;
8007        dev->dma       = info->dma_level;
8008
8009        /* network layer callbacks and settings */
8010        dev->netdev_ops     = &hdlcdev_ops;
8011        dev->watchdog_timeo = 10 * HZ;
8012        dev->tx_queue_len   = 50;
8013
8014        /* generic HDLC layer callbacks and settings */
8015        hdlc         = dev_to_hdlc(dev);
8016        hdlc->attach = hdlcdev_attach;
8017        hdlc->xmit   = hdlcdev_xmit;
8018
8019        /* register objects with HDLC layer */
8020        rc = register_hdlc_device(dev);
8021        if (rc) {
8022                printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
8023                free_netdev(dev);
8024                return rc;
8025        }
8026
8027        info->netdev = dev;
8028        return 0;
8029}
8030
8031/**
8032 * called by device driver when removing device instance
8033 * do generic HDLC cleanup
8034 *
8035 * info  pointer to device instance information
8036 */
8037static void hdlcdev_exit(struct mgsl_struct *info)
8038{
8039        unregister_hdlc_device(info->netdev);
8040        free_netdev(info->netdev);
8041        info->netdev = NULL;
8042}
8043
8044#endif /* CONFIG_HDLC */
8045
8046
8047static int synclink_init_one (struct pci_dev *dev,
8048                                        const struct pci_device_id *ent)
8049{
8050        struct mgsl_struct *info;
8051
8052        if (pci_enable_device(dev)) {
8053                printk("error enabling pci device %p\n", dev);
8054                return -EIO;
8055        }
8056
8057        info = mgsl_allocate_device();
8058        if (!info) {
8059                printk("can't allocate device instance data.\n");
8060                return -EIO;
8061        }
8062
8063        /* Copy user configuration info to device instance data */
8064                
8065        info->io_base = pci_resource_start(dev, 2);
8066        info->irq_level = dev->irq;
8067        info->phys_memory_base = pci_resource_start(dev, 3);
8068                                
8069        /* Because veremap only works on page boundaries we must map
8070         * a larger area than is actually implemented for the LCR
8071         * memory range. We map a full page starting at the page boundary.
8072         */
8073        info->phys_lcr_base = pci_resource_start(dev, 0);
8074        info->lcr_offset    = info->phys_lcr_base & (PAGE_SIZE-1);
8075        info->phys_lcr_base &= ~(PAGE_SIZE-1);
8076                                
8077        info->bus_type = MGSL_BUS_TYPE_PCI;
8078        info->io_addr_size = 8;
8079        info->irq_flags = IRQF_SHARED;
8080
8081        if (dev->device == 0x0210) {
8082                /* Version 1 PCI9030 based universal PCI adapter */
8083                info->misc_ctrl_value = 0x007c4080;
8084                info->hw_version = 1;
8085        } else {
8086                /* Version 0 PCI9050 based 5V PCI adapter
8087                 * A PCI9050 bug prevents reading LCR registers if 
8088                 * LCR base address bit 7 is set. Maintain shadow
8089                 * value so we can write to LCR misc control reg.
8090                 */
8091                info->misc_ctrl_value = 0x087e4546;
8092                info->hw_version = 0;
8093        }
8094                                
8095        mgsl_add_device(info);
8096
8097        return 0;
8098}
8099
8100static void synclink_remove_one (struct pci_dev *dev)
8101{
8102}
8103
8104