linux/sound/soc/codecs/wm8991.c
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   1/*
   2 * wm8991.c  --  WM8991 ALSA Soc Audio driver
   3 *
   4 * Copyright 2007-2010 Wolfson Microelectronics PLC.
   5 * Author: Graeme Gregory
   6 *         Graeme.Gregory@wolfsonmicro.com
   7 *
   8 *  This program is free software; you can redistribute  it and/or modify it
   9 *  under  the terms of  the GNU General  Public License as published by the
  10 *  Free Software Foundation;  either version 2 of the  License, or (at your
  11 *  option) any later version.
  12 */
  13
  14#include <linux/module.h>
  15#include <linux/moduleparam.h>
  16#include <linux/kernel.h>
  17#include <linux/init.h>
  18#include <linux/delay.h>
  19#include <linux/pm.h>
  20#include <linux/i2c.h>
  21#include <linux/regmap.h>
  22#include <linux/slab.h>
  23#include <sound/core.h>
  24#include <sound/pcm.h>
  25#include <sound/pcm_params.h>
  26#include <sound/soc.h>
  27#include <sound/soc-dapm.h>
  28#include <sound/initval.h>
  29#include <sound/tlv.h>
  30#include <asm/div64.h>
  31
  32#include "wm8991.h"
  33
  34struct wm8991_priv {
  35        struct regmap *regmap;
  36        unsigned int pcmclk;
  37};
  38
  39static const struct reg_default wm8991_reg_defaults[] = {
  40        {  1, 0x0000 },     /* R1  - Power Management (1) */
  41        {  2, 0x6000 },     /* R2  - Power Management (2) */
  42        {  3, 0x0000 },     /* R3  - Power Management (3) */
  43        {  4, 0x4050 },     /* R4  - Audio Interface (1) */
  44        {  5, 0x4000 },     /* R5  - Audio Interface (2) */
  45        {  6, 0x01C8 },     /* R6  - Clocking (1) */
  46        {  7, 0x0000 },     /* R7  - Clocking (2) */
  47        {  8, 0x0040 },     /* R8  - Audio Interface (3) */
  48        {  9, 0x0040 },     /* R9  - Audio Interface (4) */
  49        { 10, 0x0004 },     /* R10 - DAC CTRL */
  50        { 11, 0x00C0 },     /* R11 - Left DAC Digital Volume */
  51        { 12, 0x00C0 },     /* R12 - Right DAC Digital Volume */
  52        { 13, 0x0000 },     /* R13 - Digital Side Tone */
  53        { 14, 0x0100 },     /* R14 - ADC CTRL */
  54        { 15, 0x00C0 },     /* R15 - Left ADC Digital Volume */
  55        { 16, 0x00C0 },     /* R16 - Right ADC Digital Volume */
  56
  57        { 18, 0x0000 },     /* R18 - GPIO CTRL 1 */
  58        { 19, 0x1000 },     /* R19 - GPIO1 & GPIO2 */
  59        { 20, 0x1010 },     /* R20 - GPIO3 & GPIO4 */
  60        { 21, 0x1010 },     /* R21 - GPIO5 & GPIO6 */
  61        { 22, 0x8000 },     /* R22 - GPIOCTRL 2 */
  62        { 23, 0x0800 },     /* R23 - GPIO_POL */
  63        { 24, 0x008B },     /* R24 - Left Line Input 1&2 Volume */
  64        { 25, 0x008B },     /* R25 - Left Line Input 3&4 Volume */
  65        { 26, 0x008B },     /* R26 - Right Line Input 1&2 Volume */
  66        { 27, 0x008B },     /* R27 - Right Line Input 3&4 Volume */
  67        { 28, 0x0000 },     /* R28 - Left Output Volume */
  68        { 29, 0x0000 },     /* R29 - Right Output Volume */
  69        { 30, 0x0066 },     /* R30 - Line Outputs Volume */
  70        { 31, 0x0022 },     /* R31 - Out3/4 Volume */
  71        { 32, 0x0079 },     /* R32 - Left OPGA Volume */
  72        { 33, 0x0079 },     /* R33 - Right OPGA Volume */
  73        { 34, 0x0003 },     /* R34 - Speaker Volume */
  74        { 35, 0x0003 },     /* R35 - ClassD1 */
  75
  76        { 37, 0x0100 },     /* R37 - ClassD3 */
  77
  78        { 39, 0x0000 },     /* R39 - Input Mixer1 */
  79        { 40, 0x0000 },     /* R40 - Input Mixer2 */
  80        { 41, 0x0000 },     /* R41 - Input Mixer3 */
  81        { 42, 0x0000 },     /* R42 - Input Mixer4 */
  82        { 43, 0x0000 },     /* R43 - Input Mixer5 */
  83        { 44, 0x0000 },     /* R44 - Input Mixer6 */
  84        { 45, 0x0000 },     /* R45 - Output Mixer1 */
  85        { 46, 0x0000 },     /* R46 - Output Mixer2 */
  86        { 47, 0x0000 },     /* R47 - Output Mixer3 */
  87        { 48, 0x0000 },     /* R48 - Output Mixer4 */
  88        { 49, 0x0000 },     /* R49 - Output Mixer5 */
  89        { 50, 0x0000 },     /* R50 - Output Mixer6 */
  90        { 51, 0x0180 },     /* R51 - Out3/4 Mixer */
  91        { 52, 0x0000 },     /* R52 - Line Mixer1 */
  92        { 53, 0x0000 },     /* R53 - Line Mixer2 */
  93        { 54, 0x0000 },     /* R54 - Speaker Mixer */
  94        { 55, 0x0000 },     /* R55 - Additional Control */
  95        { 56, 0x0000 },     /* R56 - AntiPOP1 */
  96        { 57, 0x0000 },     /* R57 - AntiPOP2 */
  97        { 58, 0x0000 },     /* R58 - MICBIAS */
  98
  99        { 60, 0x0008 },     /* R60 - PLL1 */
 100        { 61, 0x0031 },     /* R61 - PLL2 */
 101        { 62, 0x0026 },     /* R62 - PLL3 */
 102};
 103
 104static bool wm8991_volatile(struct device *dev, unsigned int reg)
 105{
 106        switch (reg) {
 107        case WM8991_RESET:
 108                return true;
 109        default:
 110                return false;
 111        }
 112}
 113
 114static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(in_pga_tlv, -1650, 150, 0);
 115static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(out_mix_tlv, -2100, 300, 0);
 116static const SNDRV_CTL_TLVD_DECLARE_DB_RANGE(out_pga_tlv,
 117        0x00, 0x2f, SNDRV_CTL_TLVD_DB_SCALE_ITEM(SNDRV_CTL_TLVD_DB_GAIN_MUTE, 0, 1),
 118        0x30, 0x7f, SNDRV_CTL_TLVD_DB_SCALE_ITEM(-7300, 100, 0),
 119);
 120static const SNDRV_CTL_TLVD_DECLARE_DB_RANGE(out_dac_tlv,
 121        0x00, 0xbf, SNDRV_CTL_TLVD_DB_SCALE_ITEM(-71625, 375, 1),
 122        0xc0, 0xff, SNDRV_CTL_TLVD_DB_SCALE_ITEM(0, 0, 0),
 123);
 124static const SNDRV_CTL_TLVD_DECLARE_DB_RANGE(in_adc_tlv,
 125        0x00, 0xef, SNDRV_CTL_TLVD_DB_SCALE_ITEM(-71625, 375, 1),
 126        0xf0, 0xff, SNDRV_CTL_TLVD_DB_SCALE_ITEM(17625, 0, 0),
 127);
 128static const SNDRV_CTL_TLVD_DECLARE_DB_RANGE(out_sidetone_tlv,
 129        0x00, 0x0c, SNDRV_CTL_TLVD_DB_SCALE_ITEM(-3600, 300, 0),
 130        0x0d, 0x0f, SNDRV_CTL_TLVD_DB_SCALE_ITEM(0, 0, 0),
 131);
 132
 133static int wm899x_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol,
 134                                      struct snd_ctl_elem_value *ucontrol)
 135{
 136        struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
 137        int reg = kcontrol->private_value & 0xff;
 138        int ret;
 139        u16 val;
 140
 141        ret = snd_soc_put_volsw(kcontrol, ucontrol);
 142        if (ret < 0)
 143                return ret;
 144
 145        /* now hit the volume update bits (always bit 8) */
 146        val = snd_soc_read(codec, reg);
 147        return snd_soc_write(codec, reg, val | 0x0100);
 148}
 149
 150static const char *wm8991_digital_sidetone[] =
 151{"None", "Left ADC", "Right ADC", "Reserved"};
 152
 153static SOC_ENUM_SINGLE_DECL(wm8991_left_digital_sidetone_enum,
 154                            WM8991_DIGITAL_SIDE_TONE,
 155                            WM8991_ADC_TO_DACL_SHIFT,
 156                            wm8991_digital_sidetone);
 157
 158static SOC_ENUM_SINGLE_DECL(wm8991_right_digital_sidetone_enum,
 159                            WM8991_DIGITAL_SIDE_TONE,
 160                            WM8991_ADC_TO_DACR_SHIFT,
 161                            wm8991_digital_sidetone);
 162
 163static const char *wm8991_adcmode[] =
 164{"Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"};
 165
 166static SOC_ENUM_SINGLE_DECL(wm8991_right_adcmode_enum,
 167                            WM8991_ADC_CTRL,
 168                            WM8991_ADC_HPF_CUT_SHIFT,
 169                            wm8991_adcmode);
 170
 171static const struct snd_kcontrol_new wm8991_snd_controls[] = {
 172        /* INMIXL */
 173        SOC_SINGLE("LIN12 PGA Boost", WM8991_INPUT_MIXER3, WM8991_L12MNBST_BIT, 1, 0),
 174        SOC_SINGLE("LIN34 PGA Boost", WM8991_INPUT_MIXER3, WM8991_L34MNBST_BIT, 1, 0),
 175        /* INMIXR */
 176        SOC_SINGLE("RIN12 PGA Boost", WM8991_INPUT_MIXER3, WM8991_R12MNBST_BIT, 1, 0),
 177        SOC_SINGLE("RIN34 PGA Boost", WM8991_INPUT_MIXER3, WM8991_R34MNBST_BIT, 1, 0),
 178
 179        /* LOMIX */
 180        SOC_SINGLE_TLV("LOMIX LIN3 Bypass Volume", WM8991_OUTPUT_MIXER3,
 181                WM8991_LLI3LOVOL_SHIFT, WM8991_LLI3LOVOL_MASK, 1, out_mix_tlv),
 182        SOC_SINGLE_TLV("LOMIX RIN12 PGA Bypass Volume", WM8991_OUTPUT_MIXER3,
 183                WM8991_LR12LOVOL_SHIFT, WM8991_LR12LOVOL_MASK, 1, out_mix_tlv),
 184        SOC_SINGLE_TLV("LOMIX LIN12 PGA Bypass Volume", WM8991_OUTPUT_MIXER3,
 185                WM8991_LL12LOVOL_SHIFT, WM8991_LL12LOVOL_MASK, 1, out_mix_tlv),
 186        SOC_SINGLE_TLV("LOMIX RIN3 Bypass Volume", WM8991_OUTPUT_MIXER5,
 187                WM8991_LRI3LOVOL_SHIFT, WM8991_LRI3LOVOL_MASK, 1, out_mix_tlv),
 188        SOC_SINGLE_TLV("LOMIX AINRMUX Bypass Volume", WM8991_OUTPUT_MIXER5,
 189                WM8991_LRBLOVOL_SHIFT, WM8991_LRBLOVOL_MASK, 1, out_mix_tlv),
 190        SOC_SINGLE_TLV("LOMIX AINLMUX Bypass Volume", WM8991_OUTPUT_MIXER5,
 191                WM8991_LRBLOVOL_SHIFT, WM8991_LRBLOVOL_MASK, 1, out_mix_tlv),
 192
 193        /* ROMIX */
 194        SOC_SINGLE_TLV("ROMIX RIN3 Bypass Volume", WM8991_OUTPUT_MIXER4,
 195                WM8991_RRI3ROVOL_SHIFT, WM8991_RRI3ROVOL_MASK, 1, out_mix_tlv),
 196        SOC_SINGLE_TLV("ROMIX LIN12 PGA Bypass Volume", WM8991_OUTPUT_MIXER4,
 197                WM8991_RL12ROVOL_SHIFT, WM8991_RL12ROVOL_MASK, 1, out_mix_tlv),
 198        SOC_SINGLE_TLV("ROMIX RIN12 PGA Bypass Volume", WM8991_OUTPUT_MIXER4,
 199                WM8991_RR12ROVOL_SHIFT, WM8991_RR12ROVOL_MASK, 1, out_mix_tlv),
 200        SOC_SINGLE_TLV("ROMIX LIN3 Bypass Volume", WM8991_OUTPUT_MIXER6,
 201                WM8991_RLI3ROVOL_SHIFT, WM8991_RLI3ROVOL_MASK, 1, out_mix_tlv),
 202        SOC_SINGLE_TLV("ROMIX AINLMUX Bypass Volume", WM8991_OUTPUT_MIXER6,
 203                WM8991_RLBROVOL_SHIFT, WM8991_RLBROVOL_MASK, 1, out_mix_tlv),
 204        SOC_SINGLE_TLV("ROMIX AINRMUX Bypass Volume", WM8991_OUTPUT_MIXER6,
 205                WM8991_RRBROVOL_SHIFT, WM8991_RRBROVOL_MASK, 1, out_mix_tlv),
 206
 207        /* LOUT */
 208        SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOUT Volume", WM8991_LEFT_OUTPUT_VOLUME,
 209                WM8991_LOUTVOL_SHIFT, WM8991_LOUTVOL_MASK, 0, out_pga_tlv),
 210        SOC_SINGLE("LOUT ZC", WM8991_LEFT_OUTPUT_VOLUME, WM8991_LOZC_BIT, 1, 0),
 211
 212        /* ROUT */
 213        SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROUT Volume", WM8991_RIGHT_OUTPUT_VOLUME,
 214                WM8991_ROUTVOL_SHIFT, WM8991_ROUTVOL_MASK, 0, out_pga_tlv),
 215        SOC_SINGLE("ROUT ZC", WM8991_RIGHT_OUTPUT_VOLUME, WM8991_ROZC_BIT, 1, 0),
 216
 217        /* LOPGA */
 218        SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOPGA Volume", WM8991_LEFT_OPGA_VOLUME,
 219                WM8991_LOPGAVOL_SHIFT, WM8991_LOPGAVOL_MASK, 0, out_pga_tlv),
 220        SOC_SINGLE("LOPGA ZC Switch", WM8991_LEFT_OPGA_VOLUME,
 221                WM8991_LOPGAZC_BIT, 1, 0),
 222
 223        /* ROPGA */
 224        SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROPGA Volume", WM8991_RIGHT_OPGA_VOLUME,
 225                WM8991_ROPGAVOL_SHIFT, WM8991_ROPGAVOL_MASK, 0, out_pga_tlv),
 226        SOC_SINGLE("ROPGA ZC Switch", WM8991_RIGHT_OPGA_VOLUME,
 227                WM8991_ROPGAZC_BIT, 1, 0),
 228
 229        SOC_SINGLE("LON Mute Switch", WM8991_LINE_OUTPUTS_VOLUME,
 230                WM8991_LONMUTE_BIT, 1, 0),
 231        SOC_SINGLE("LOP Mute Switch", WM8991_LINE_OUTPUTS_VOLUME,
 232                WM8991_LOPMUTE_BIT, 1, 0),
 233        SOC_SINGLE("LOP Attenuation Switch", WM8991_LINE_OUTPUTS_VOLUME,
 234                WM8991_LOATTN_BIT, 1, 0),
 235        SOC_SINGLE("RON Mute Switch", WM8991_LINE_OUTPUTS_VOLUME,
 236                WM8991_RONMUTE_BIT, 1, 0),
 237        SOC_SINGLE("ROP Mute Switch", WM8991_LINE_OUTPUTS_VOLUME,
 238                WM8991_ROPMUTE_BIT, 1, 0),
 239        SOC_SINGLE("ROP Attenuation Switch", WM8991_LINE_OUTPUTS_VOLUME,
 240                WM8991_ROATTN_BIT, 1, 0),
 241
 242        SOC_SINGLE("OUT3 Mute Switch", WM8991_OUT3_4_VOLUME,
 243                WM8991_OUT3MUTE_BIT, 1, 0),
 244        SOC_SINGLE("OUT3 Attenuation Switch", WM8991_OUT3_4_VOLUME,
 245                WM8991_OUT3ATTN_BIT, 1, 0),
 246
 247        SOC_SINGLE("OUT4 Mute Switch", WM8991_OUT3_4_VOLUME,
 248                WM8991_OUT4MUTE_BIT, 1, 0),
 249        SOC_SINGLE("OUT4 Attenuation Switch", WM8991_OUT3_4_VOLUME,
 250                WM8991_OUT4ATTN_BIT, 1, 0),
 251
 252        SOC_SINGLE("Speaker Mode Switch", WM8991_CLASSD1,
 253                WM8991_CDMODE_BIT, 1, 0),
 254
 255        SOC_SINGLE("Speaker Output Attenuation Volume", WM8991_SPEAKER_VOLUME,
 256                WM8991_SPKVOL_SHIFT, WM8991_SPKVOL_MASK, 0),
 257        SOC_SINGLE("Speaker DC Boost Volume", WM8991_CLASSD3,
 258                WM8991_DCGAIN_SHIFT, WM8991_DCGAIN_MASK, 0),
 259        SOC_SINGLE("Speaker AC Boost Volume", WM8991_CLASSD3,
 260                WM8991_ACGAIN_SHIFT, WM8991_ACGAIN_MASK, 0),
 261
 262        SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left DAC Digital Volume",
 263                WM8991_LEFT_DAC_DIGITAL_VOLUME,
 264                WM8991_DACL_VOL_SHIFT,
 265                WM8991_DACL_VOL_MASK,
 266                0,
 267                out_dac_tlv),
 268
 269        SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right DAC Digital Volume",
 270                WM8991_RIGHT_DAC_DIGITAL_VOLUME,
 271                WM8991_DACR_VOL_SHIFT,
 272                WM8991_DACR_VOL_MASK,
 273                0,
 274                out_dac_tlv),
 275
 276        SOC_ENUM("Left Digital Sidetone", wm8991_left_digital_sidetone_enum),
 277        SOC_ENUM("Right Digital Sidetone", wm8991_right_digital_sidetone_enum),
 278
 279        SOC_SINGLE_TLV("Left Digital Sidetone Volume", WM8991_DIGITAL_SIDE_TONE,
 280                WM8991_ADCL_DAC_SVOL_SHIFT, WM8991_ADCL_DAC_SVOL_MASK, 0,
 281                out_sidetone_tlv),
 282        SOC_SINGLE_TLV("Right Digital Sidetone Volume", WM8991_DIGITAL_SIDE_TONE,
 283                WM8991_ADCR_DAC_SVOL_SHIFT, WM8991_ADCR_DAC_SVOL_MASK, 0,
 284                out_sidetone_tlv),
 285
 286        SOC_SINGLE("ADC Digital High Pass Filter Switch", WM8991_ADC_CTRL,
 287                WM8991_ADC_HPF_ENA_BIT, 1, 0),
 288
 289        SOC_ENUM("ADC HPF Mode", wm8991_right_adcmode_enum),
 290
 291        SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left ADC Digital Volume",
 292                WM8991_LEFT_ADC_DIGITAL_VOLUME,
 293                WM8991_ADCL_VOL_SHIFT,
 294                WM8991_ADCL_VOL_MASK,
 295                0,
 296                in_adc_tlv),
 297
 298        SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right ADC Digital Volume",
 299                WM8991_RIGHT_ADC_DIGITAL_VOLUME,
 300                WM8991_ADCR_VOL_SHIFT,
 301                WM8991_ADCR_VOL_MASK,
 302                0,
 303                in_adc_tlv),
 304
 305        SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN12 Volume",
 306                WM8991_LEFT_LINE_INPUT_1_2_VOLUME,
 307                WM8991_LIN12VOL_SHIFT,
 308                WM8991_LIN12VOL_MASK,
 309                0,
 310                in_pga_tlv),
 311
 312        SOC_SINGLE("LIN12 ZC Switch", WM8991_LEFT_LINE_INPUT_1_2_VOLUME,
 313                WM8991_LI12ZC_BIT, 1, 0),
 314
 315        SOC_SINGLE("LIN12 Mute Switch", WM8991_LEFT_LINE_INPUT_1_2_VOLUME,
 316                WM8991_LI12MUTE_BIT, 1, 0),
 317
 318        SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN34 Volume",
 319                WM8991_LEFT_LINE_INPUT_3_4_VOLUME,
 320                WM8991_LIN34VOL_SHIFT,
 321                WM8991_LIN34VOL_MASK,
 322                0,
 323                in_pga_tlv),
 324
 325        SOC_SINGLE("LIN34 ZC Switch", WM8991_LEFT_LINE_INPUT_3_4_VOLUME,
 326                WM8991_LI34ZC_BIT, 1, 0),
 327
 328        SOC_SINGLE("LIN34 Mute Switch", WM8991_LEFT_LINE_INPUT_3_4_VOLUME,
 329                WM8991_LI34MUTE_BIT, 1, 0),
 330
 331        SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN12 Volume",
 332                WM8991_RIGHT_LINE_INPUT_1_2_VOLUME,
 333                WM8991_RIN12VOL_SHIFT,
 334                WM8991_RIN12VOL_MASK,
 335                0,
 336                in_pga_tlv),
 337
 338        SOC_SINGLE("RIN12 ZC Switch", WM8991_RIGHT_LINE_INPUT_1_2_VOLUME,
 339                WM8991_RI12ZC_BIT, 1, 0),
 340
 341        SOC_SINGLE("RIN12 Mute Switch", WM8991_RIGHT_LINE_INPUT_1_2_VOLUME,
 342                WM8991_RI12MUTE_BIT, 1, 0),
 343
 344        SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN34 Volume",
 345                WM8991_RIGHT_LINE_INPUT_3_4_VOLUME,
 346                WM8991_RIN34VOL_SHIFT,
 347                WM8991_RIN34VOL_MASK,
 348                0,
 349                in_pga_tlv),
 350
 351        SOC_SINGLE("RIN34 ZC Switch", WM8991_RIGHT_LINE_INPUT_3_4_VOLUME,
 352                WM8991_RI34ZC_BIT, 1, 0),
 353
 354        SOC_SINGLE("RIN34 Mute Switch", WM8991_RIGHT_LINE_INPUT_3_4_VOLUME,
 355                WM8991_RI34MUTE_BIT, 1, 0),
 356};
 357
 358/*
 359 * _DAPM_ Controls
 360 */
 361static int outmixer_event(struct snd_soc_dapm_widget *w,
 362                          struct snd_kcontrol *kcontrol, int event)
 363{
 364        struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
 365        u32 reg_shift = kcontrol->private_value & 0xfff;
 366        int ret = 0;
 367        u16 reg;
 368
 369        switch (reg_shift) {
 370        case WM8991_SPEAKER_MIXER | (WM8991_LDSPK_BIT << 8):
 371                reg = snd_soc_read(codec, WM8991_OUTPUT_MIXER1);
 372                if (reg & WM8991_LDLO) {
 373                        printk(KERN_WARNING
 374                               "Cannot set as Output Mixer 1 LDLO Set\n");
 375                        ret = -1;
 376                }
 377                break;
 378
 379        case WM8991_SPEAKER_MIXER | (WM8991_RDSPK_BIT << 8):
 380                reg = snd_soc_read(codec, WM8991_OUTPUT_MIXER2);
 381                if (reg & WM8991_RDRO) {
 382                        printk(KERN_WARNING
 383                               "Cannot set as Output Mixer 2 RDRO Set\n");
 384                        ret = -1;
 385                }
 386                break;
 387
 388        case WM8991_OUTPUT_MIXER1 | (WM8991_LDLO_BIT << 8):
 389                reg = snd_soc_read(codec, WM8991_SPEAKER_MIXER);
 390                if (reg & WM8991_LDSPK) {
 391                        printk(KERN_WARNING
 392                               "Cannot set as Speaker Mixer LDSPK Set\n");
 393                        ret = -1;
 394                }
 395                break;
 396
 397        case WM8991_OUTPUT_MIXER2 | (WM8991_RDRO_BIT << 8):
 398                reg = snd_soc_read(codec, WM8991_SPEAKER_MIXER);
 399                if (reg & WM8991_RDSPK) {
 400                        printk(KERN_WARNING
 401                               "Cannot set as Speaker Mixer RDSPK Set\n");
 402                        ret = -1;
 403                }
 404                break;
 405        }
 406
 407        return ret;
 408}
 409
 410/* INMIX dB values */
 411static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(in_mix_tlv, -1200, 300, 1);
 412
 413/* Left In PGA Connections */
 414static const struct snd_kcontrol_new wm8991_dapm_lin12_pga_controls[] = {
 415        SOC_DAPM_SINGLE("LIN1 Switch", WM8991_INPUT_MIXER2, WM8991_LMN1_BIT, 1, 0),
 416        SOC_DAPM_SINGLE("LIN2 Switch", WM8991_INPUT_MIXER2, WM8991_LMP2_BIT, 1, 0),
 417};
 418
 419static const struct snd_kcontrol_new wm8991_dapm_lin34_pga_controls[] = {
 420        SOC_DAPM_SINGLE("LIN3 Switch", WM8991_INPUT_MIXER2, WM8991_LMN3_BIT, 1, 0),
 421        SOC_DAPM_SINGLE("LIN4 Switch", WM8991_INPUT_MIXER2, WM8991_LMP4_BIT, 1, 0),
 422};
 423
 424/* Right In PGA Connections */
 425static const struct snd_kcontrol_new wm8991_dapm_rin12_pga_controls[] = {
 426        SOC_DAPM_SINGLE("RIN1 Switch", WM8991_INPUT_MIXER2, WM8991_RMN1_BIT, 1, 0),
 427        SOC_DAPM_SINGLE("RIN2 Switch", WM8991_INPUT_MIXER2, WM8991_RMP2_BIT, 1, 0),
 428};
 429
 430static const struct snd_kcontrol_new wm8991_dapm_rin34_pga_controls[] = {
 431        SOC_DAPM_SINGLE("RIN3 Switch", WM8991_INPUT_MIXER2, WM8991_RMN3_BIT, 1, 0),
 432        SOC_DAPM_SINGLE("RIN4 Switch", WM8991_INPUT_MIXER2, WM8991_RMP4_BIT, 1, 0),
 433};
 434
 435/* INMIXL */
 436static const struct snd_kcontrol_new wm8991_dapm_inmixl_controls[] = {
 437        SOC_DAPM_SINGLE_TLV("Record Left Volume", WM8991_INPUT_MIXER3,
 438                WM8991_LDBVOL_SHIFT, WM8991_LDBVOL_MASK, 0, in_mix_tlv),
 439        SOC_DAPM_SINGLE_TLV("LIN2 Volume", WM8991_INPUT_MIXER5, WM8991_LI2BVOL_SHIFT,
 440                7, 0, in_mix_tlv),
 441        SOC_DAPM_SINGLE("LINPGA12 Switch", WM8991_INPUT_MIXER3, WM8991_L12MNB_BIT,
 442                1, 0),
 443        SOC_DAPM_SINGLE("LINPGA34 Switch", WM8991_INPUT_MIXER3, WM8991_L34MNB_BIT,
 444                1, 0),
 445};
 446
 447/* INMIXR */
 448static const struct snd_kcontrol_new wm8991_dapm_inmixr_controls[] = {
 449        SOC_DAPM_SINGLE_TLV("Record Right Volume", WM8991_INPUT_MIXER4,
 450                WM8991_RDBVOL_SHIFT, WM8991_RDBVOL_MASK, 0, in_mix_tlv),
 451        SOC_DAPM_SINGLE_TLV("RIN2 Volume", WM8991_INPUT_MIXER6, WM8991_RI2BVOL_SHIFT,
 452                7, 0, in_mix_tlv),
 453        SOC_DAPM_SINGLE("RINPGA12 Switch", WM8991_INPUT_MIXER3, WM8991_L12MNB_BIT,
 454                1, 0),
 455        SOC_DAPM_SINGLE("RINPGA34 Switch", WM8991_INPUT_MIXER3, WM8991_L34MNB_BIT,
 456                1, 0),
 457};
 458
 459/* AINLMUX */
 460static const char *wm8991_ainlmux[] =
 461{"INMIXL Mix", "RXVOICE Mix", "DIFFINL Mix"};
 462
 463static SOC_ENUM_SINGLE_DECL(wm8991_ainlmux_enum,
 464                            WM8991_INPUT_MIXER1, WM8991_AINLMODE_SHIFT,
 465                            wm8991_ainlmux);
 466
 467static const struct snd_kcontrol_new wm8991_dapm_ainlmux_controls =
 468        SOC_DAPM_ENUM("Route", wm8991_ainlmux_enum);
 469
 470/* DIFFINL */
 471
 472/* AINRMUX */
 473static const char *wm8991_ainrmux[] =
 474{"INMIXR Mix", "RXVOICE Mix", "DIFFINR Mix"};
 475
 476static SOC_ENUM_SINGLE_DECL(wm8991_ainrmux_enum,
 477                            WM8991_INPUT_MIXER1, WM8991_AINRMODE_SHIFT,
 478                            wm8991_ainrmux);
 479
 480static const struct snd_kcontrol_new wm8991_dapm_ainrmux_controls =
 481        SOC_DAPM_ENUM("Route", wm8991_ainrmux_enum);
 482
 483/* RXVOICE */
 484static const struct snd_kcontrol_new wm8991_dapm_rxvoice_controls[] = {
 485        SOC_DAPM_SINGLE_TLV("LIN4RXN", WM8991_INPUT_MIXER5, WM8991_LR4BVOL_SHIFT,
 486                WM8991_LR4BVOL_MASK, 0, in_mix_tlv),
 487        SOC_DAPM_SINGLE_TLV("RIN4RXP", WM8991_INPUT_MIXER6, WM8991_RL4BVOL_SHIFT,
 488                WM8991_RL4BVOL_MASK, 0, in_mix_tlv),
 489};
 490
 491/* LOMIX */
 492static const struct snd_kcontrol_new wm8991_dapm_lomix_controls[] = {
 493        SOC_DAPM_SINGLE("LOMIX Right ADC Bypass Switch", WM8991_OUTPUT_MIXER1,
 494                WM8991_LRBLO_BIT, 1, 0),
 495        SOC_DAPM_SINGLE("LOMIX Left ADC Bypass Switch", WM8991_OUTPUT_MIXER1,
 496                WM8991_LLBLO_BIT, 1, 0),
 497        SOC_DAPM_SINGLE("LOMIX RIN3 Bypass Switch", WM8991_OUTPUT_MIXER1,
 498                WM8991_LRI3LO_BIT, 1, 0),
 499        SOC_DAPM_SINGLE("LOMIX LIN3 Bypass Switch", WM8991_OUTPUT_MIXER1,
 500                WM8991_LLI3LO_BIT, 1, 0),
 501        SOC_DAPM_SINGLE("LOMIX RIN12 PGA Bypass Switch", WM8991_OUTPUT_MIXER1,
 502                WM8991_LR12LO_BIT, 1, 0),
 503        SOC_DAPM_SINGLE("LOMIX LIN12 PGA Bypass Switch", WM8991_OUTPUT_MIXER1,
 504                WM8991_LL12LO_BIT, 1, 0),
 505        SOC_DAPM_SINGLE("LOMIX Left DAC Switch", WM8991_OUTPUT_MIXER1,
 506                WM8991_LDLO_BIT, 1, 0),
 507};
 508
 509/* ROMIX */
 510static const struct snd_kcontrol_new wm8991_dapm_romix_controls[] = {
 511        SOC_DAPM_SINGLE("ROMIX Left ADC Bypass Switch", WM8991_OUTPUT_MIXER2,
 512                WM8991_RLBRO_BIT, 1, 0),
 513        SOC_DAPM_SINGLE("ROMIX Right ADC Bypass Switch", WM8991_OUTPUT_MIXER2,
 514                WM8991_RRBRO_BIT, 1, 0),
 515        SOC_DAPM_SINGLE("ROMIX LIN3 Bypass Switch", WM8991_OUTPUT_MIXER2,
 516                WM8991_RLI3RO_BIT, 1, 0),
 517        SOC_DAPM_SINGLE("ROMIX RIN3 Bypass Switch", WM8991_OUTPUT_MIXER2,
 518                WM8991_RRI3RO_BIT, 1, 0),
 519        SOC_DAPM_SINGLE("ROMIX LIN12 PGA Bypass Switch", WM8991_OUTPUT_MIXER2,
 520                WM8991_RL12RO_BIT, 1, 0),
 521        SOC_DAPM_SINGLE("ROMIX RIN12 PGA Bypass Switch", WM8991_OUTPUT_MIXER2,
 522                WM8991_RR12RO_BIT, 1, 0),
 523        SOC_DAPM_SINGLE("ROMIX Right DAC Switch", WM8991_OUTPUT_MIXER2,
 524                WM8991_RDRO_BIT, 1, 0),
 525};
 526
 527/* LONMIX */
 528static const struct snd_kcontrol_new wm8991_dapm_lonmix_controls[] = {
 529        SOC_DAPM_SINGLE("LONMIX Left Mixer PGA Switch", WM8991_LINE_MIXER1,
 530                WM8991_LLOPGALON_BIT, 1, 0),
 531        SOC_DAPM_SINGLE("LONMIX Right Mixer PGA Switch", WM8991_LINE_MIXER1,
 532                WM8991_LROPGALON_BIT, 1, 0),
 533        SOC_DAPM_SINGLE("LONMIX Inverted LOP Switch", WM8991_LINE_MIXER1,
 534                WM8991_LOPLON_BIT, 1, 0),
 535};
 536
 537/* LOPMIX */
 538static const struct snd_kcontrol_new wm8991_dapm_lopmix_controls[] = {
 539        SOC_DAPM_SINGLE("LOPMIX Right Mic Bypass Switch", WM8991_LINE_MIXER1,
 540                WM8991_LR12LOP_BIT, 1, 0),
 541        SOC_DAPM_SINGLE("LOPMIX Left Mic Bypass Switch", WM8991_LINE_MIXER1,
 542                WM8991_LL12LOP_BIT, 1, 0),
 543        SOC_DAPM_SINGLE("LOPMIX Left Mixer PGA Switch", WM8991_LINE_MIXER1,
 544                WM8991_LLOPGALOP_BIT, 1, 0),
 545};
 546
 547/* RONMIX */
 548static const struct snd_kcontrol_new wm8991_dapm_ronmix_controls[] = {
 549        SOC_DAPM_SINGLE("RONMIX Right Mixer PGA Switch", WM8991_LINE_MIXER2,
 550                WM8991_RROPGARON_BIT, 1, 0),
 551        SOC_DAPM_SINGLE("RONMIX Left Mixer PGA Switch", WM8991_LINE_MIXER2,
 552                WM8991_RLOPGARON_BIT, 1, 0),
 553        SOC_DAPM_SINGLE("RONMIX Inverted ROP Switch", WM8991_LINE_MIXER2,
 554                WM8991_ROPRON_BIT, 1, 0),
 555};
 556
 557/* ROPMIX */
 558static const struct snd_kcontrol_new wm8991_dapm_ropmix_controls[] = {
 559        SOC_DAPM_SINGLE("ROPMIX Left Mic Bypass Switch", WM8991_LINE_MIXER2,
 560                WM8991_RL12ROP_BIT, 1, 0),
 561        SOC_DAPM_SINGLE("ROPMIX Right Mic Bypass Switch", WM8991_LINE_MIXER2,
 562                WM8991_RR12ROP_BIT, 1, 0),
 563        SOC_DAPM_SINGLE("ROPMIX Right Mixer PGA Switch", WM8991_LINE_MIXER2,
 564                WM8991_RROPGAROP_BIT, 1, 0),
 565};
 566
 567/* OUT3MIX */
 568static const struct snd_kcontrol_new wm8991_dapm_out3mix_controls[] = {
 569        SOC_DAPM_SINGLE("OUT3MIX LIN4RXN Bypass Switch", WM8991_OUT3_4_MIXER,
 570                WM8991_LI4O3_BIT, 1, 0),
 571        SOC_DAPM_SINGLE("OUT3MIX Left Out PGA Switch", WM8991_OUT3_4_MIXER,
 572                WM8991_LPGAO3_BIT, 1, 0),
 573};
 574
 575/* OUT4MIX */
 576static const struct snd_kcontrol_new wm8991_dapm_out4mix_controls[] = {
 577        SOC_DAPM_SINGLE("OUT4MIX Right Out PGA Switch", WM8991_OUT3_4_MIXER,
 578                WM8991_RPGAO4_BIT, 1, 0),
 579        SOC_DAPM_SINGLE("OUT4MIX RIN4RXP Bypass Switch", WM8991_OUT3_4_MIXER,
 580                WM8991_RI4O4_BIT, 1, 0),
 581};
 582
 583/* SPKMIX */
 584static const struct snd_kcontrol_new wm8991_dapm_spkmix_controls[] = {
 585        SOC_DAPM_SINGLE("SPKMIX LIN2 Bypass Switch", WM8991_SPEAKER_MIXER,
 586                WM8991_LI2SPK_BIT, 1, 0),
 587        SOC_DAPM_SINGLE("SPKMIX LADC Bypass Switch", WM8991_SPEAKER_MIXER,
 588                WM8991_LB2SPK_BIT, 1, 0),
 589        SOC_DAPM_SINGLE("SPKMIX Left Mixer PGA Switch", WM8991_SPEAKER_MIXER,
 590                WM8991_LOPGASPK_BIT, 1, 0),
 591        SOC_DAPM_SINGLE("SPKMIX Left DAC Switch", WM8991_SPEAKER_MIXER,
 592                WM8991_LDSPK_BIT, 1, 0),
 593        SOC_DAPM_SINGLE("SPKMIX Right DAC Switch", WM8991_SPEAKER_MIXER,
 594                WM8991_RDSPK_BIT, 1, 0),
 595        SOC_DAPM_SINGLE("SPKMIX Right Mixer PGA Switch", WM8991_SPEAKER_MIXER,
 596                WM8991_ROPGASPK_BIT, 1, 0),
 597        SOC_DAPM_SINGLE("SPKMIX RADC Bypass Switch", WM8991_SPEAKER_MIXER,
 598                WM8991_RL12ROP_BIT, 1, 0),
 599        SOC_DAPM_SINGLE("SPKMIX RIN2 Bypass Switch", WM8991_SPEAKER_MIXER,
 600                WM8991_RI2SPK_BIT, 1, 0),
 601};
 602
 603static const struct snd_soc_dapm_widget wm8991_dapm_widgets[] = {
 604        /* Input Side */
 605        /* Input Lines */
 606        SND_SOC_DAPM_INPUT("LIN1"),
 607        SND_SOC_DAPM_INPUT("LIN2"),
 608        SND_SOC_DAPM_INPUT("LIN3"),
 609        SND_SOC_DAPM_INPUT("LIN4RXN"),
 610        SND_SOC_DAPM_INPUT("RIN3"),
 611        SND_SOC_DAPM_INPUT("RIN4RXP"),
 612        SND_SOC_DAPM_INPUT("RIN1"),
 613        SND_SOC_DAPM_INPUT("RIN2"),
 614        SND_SOC_DAPM_INPUT("Internal ADC Source"),
 615
 616        SND_SOC_DAPM_SUPPLY("INL", WM8991_POWER_MANAGEMENT_2,
 617                            WM8991_AINL_ENA_BIT, 0, NULL, 0),
 618        SND_SOC_DAPM_SUPPLY("INR", WM8991_POWER_MANAGEMENT_2,
 619                            WM8991_AINR_ENA_BIT, 0, NULL, 0),
 620
 621        /* DACs */
 622        SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8991_POWER_MANAGEMENT_2,
 623                WM8991_ADCL_ENA_BIT, 0),
 624        SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8991_POWER_MANAGEMENT_2,
 625                WM8991_ADCR_ENA_BIT, 0),
 626
 627        /* Input PGAs */
 628        SND_SOC_DAPM_MIXER("LIN12 PGA", WM8991_POWER_MANAGEMENT_2, WM8991_LIN12_ENA_BIT,
 629                0, &wm8991_dapm_lin12_pga_controls[0],
 630                ARRAY_SIZE(wm8991_dapm_lin12_pga_controls)),
 631        SND_SOC_DAPM_MIXER("LIN34 PGA", WM8991_POWER_MANAGEMENT_2, WM8991_LIN34_ENA_BIT,
 632                0, &wm8991_dapm_lin34_pga_controls[0],
 633                ARRAY_SIZE(wm8991_dapm_lin34_pga_controls)),
 634        SND_SOC_DAPM_MIXER("RIN12 PGA", WM8991_POWER_MANAGEMENT_2, WM8991_RIN12_ENA_BIT,
 635                0, &wm8991_dapm_rin12_pga_controls[0],
 636                ARRAY_SIZE(wm8991_dapm_rin12_pga_controls)),
 637        SND_SOC_DAPM_MIXER("RIN34 PGA", WM8991_POWER_MANAGEMENT_2, WM8991_RIN34_ENA_BIT,
 638                0, &wm8991_dapm_rin34_pga_controls[0],
 639                ARRAY_SIZE(wm8991_dapm_rin34_pga_controls)),
 640
 641        /* INMIXL */
 642        SND_SOC_DAPM_MIXER("INMIXL", SND_SOC_NOPM, 0, 0,
 643                &wm8991_dapm_inmixl_controls[0],
 644                ARRAY_SIZE(wm8991_dapm_inmixl_controls)),
 645
 646        /* AINLMUX */
 647        SND_SOC_DAPM_MUX("AINLMUX", SND_SOC_NOPM, 0, 0,
 648                &wm8991_dapm_ainlmux_controls),
 649
 650        /* INMIXR */
 651        SND_SOC_DAPM_MIXER("INMIXR", SND_SOC_NOPM, 0, 0,
 652                &wm8991_dapm_inmixr_controls[0],
 653                ARRAY_SIZE(wm8991_dapm_inmixr_controls)),
 654
 655        /* AINRMUX */
 656        SND_SOC_DAPM_MUX("AINRMUX", SND_SOC_NOPM, 0, 0,
 657                &wm8991_dapm_ainrmux_controls),
 658
 659        /* Output Side */
 660        /* DACs */
 661        SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8991_POWER_MANAGEMENT_3,
 662                WM8991_DACL_ENA_BIT, 0),
 663        SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8991_POWER_MANAGEMENT_3,
 664                WM8991_DACR_ENA_BIT, 0),
 665
 666        /* LOMIX */
 667        SND_SOC_DAPM_MIXER_E("LOMIX", WM8991_POWER_MANAGEMENT_3, WM8991_LOMIX_ENA_BIT,
 668                0, &wm8991_dapm_lomix_controls[0],
 669                ARRAY_SIZE(wm8991_dapm_lomix_controls),
 670                outmixer_event, SND_SOC_DAPM_PRE_REG),
 671
 672        /* LONMIX */
 673        SND_SOC_DAPM_MIXER("LONMIX", WM8991_POWER_MANAGEMENT_3, WM8991_LON_ENA_BIT, 0,
 674                &wm8991_dapm_lonmix_controls[0],
 675                ARRAY_SIZE(wm8991_dapm_lonmix_controls)),
 676
 677        /* LOPMIX */
 678        SND_SOC_DAPM_MIXER("LOPMIX", WM8991_POWER_MANAGEMENT_3, WM8991_LOP_ENA_BIT, 0,
 679                &wm8991_dapm_lopmix_controls[0],
 680                ARRAY_SIZE(wm8991_dapm_lopmix_controls)),
 681
 682        /* OUT3MIX */
 683        SND_SOC_DAPM_MIXER("OUT3MIX", WM8991_POWER_MANAGEMENT_1, WM8991_OUT3_ENA_BIT, 0,
 684                &wm8991_dapm_out3mix_controls[0],
 685                ARRAY_SIZE(wm8991_dapm_out3mix_controls)),
 686
 687        /* SPKMIX */
 688        SND_SOC_DAPM_MIXER_E("SPKMIX", WM8991_POWER_MANAGEMENT_1, WM8991_SPK_ENA_BIT, 0,
 689                &wm8991_dapm_spkmix_controls[0],
 690                ARRAY_SIZE(wm8991_dapm_spkmix_controls), outmixer_event,
 691                SND_SOC_DAPM_PRE_REG),
 692
 693        /* OUT4MIX */
 694        SND_SOC_DAPM_MIXER("OUT4MIX", WM8991_POWER_MANAGEMENT_1, WM8991_OUT4_ENA_BIT, 0,
 695                &wm8991_dapm_out4mix_controls[0],
 696                ARRAY_SIZE(wm8991_dapm_out4mix_controls)),
 697
 698        /* ROPMIX */
 699        SND_SOC_DAPM_MIXER("ROPMIX", WM8991_POWER_MANAGEMENT_3, WM8991_ROP_ENA_BIT, 0,
 700                &wm8991_dapm_ropmix_controls[0],
 701                ARRAY_SIZE(wm8991_dapm_ropmix_controls)),
 702
 703        /* RONMIX */
 704        SND_SOC_DAPM_MIXER("RONMIX", WM8991_POWER_MANAGEMENT_3, WM8991_RON_ENA_BIT, 0,
 705                &wm8991_dapm_ronmix_controls[0],
 706                ARRAY_SIZE(wm8991_dapm_ronmix_controls)),
 707
 708        /* ROMIX */
 709        SND_SOC_DAPM_MIXER_E("ROMIX", WM8991_POWER_MANAGEMENT_3, WM8991_ROMIX_ENA_BIT,
 710                0, &wm8991_dapm_romix_controls[0],
 711                ARRAY_SIZE(wm8991_dapm_romix_controls),
 712                outmixer_event, SND_SOC_DAPM_PRE_REG),
 713
 714        /* LOUT PGA */
 715        SND_SOC_DAPM_PGA("LOUT PGA", WM8991_POWER_MANAGEMENT_1, WM8991_LOUT_ENA_BIT, 0,
 716                NULL, 0),
 717
 718        /* ROUT PGA */
 719        SND_SOC_DAPM_PGA("ROUT PGA", WM8991_POWER_MANAGEMENT_1, WM8991_ROUT_ENA_BIT, 0,
 720                NULL, 0),
 721
 722        /* LOPGA */
 723        SND_SOC_DAPM_PGA("LOPGA", WM8991_POWER_MANAGEMENT_3, WM8991_LOPGA_ENA_BIT, 0,
 724                NULL, 0),
 725
 726        /* ROPGA */
 727        SND_SOC_DAPM_PGA("ROPGA", WM8991_POWER_MANAGEMENT_3, WM8991_ROPGA_ENA_BIT, 0,
 728                NULL, 0),
 729
 730        /* MICBIAS */
 731        SND_SOC_DAPM_SUPPLY("MICBIAS", WM8991_POWER_MANAGEMENT_1,
 732                            WM8991_MICBIAS_ENA_BIT, 0, NULL, 0),
 733
 734        SND_SOC_DAPM_OUTPUT("LON"),
 735        SND_SOC_DAPM_OUTPUT("LOP"),
 736        SND_SOC_DAPM_OUTPUT("OUT3"),
 737        SND_SOC_DAPM_OUTPUT("LOUT"),
 738        SND_SOC_DAPM_OUTPUT("SPKN"),
 739        SND_SOC_DAPM_OUTPUT("SPKP"),
 740        SND_SOC_DAPM_OUTPUT("ROUT"),
 741        SND_SOC_DAPM_OUTPUT("OUT4"),
 742        SND_SOC_DAPM_OUTPUT("ROP"),
 743        SND_SOC_DAPM_OUTPUT("RON"),
 744        SND_SOC_DAPM_OUTPUT("OUT"),
 745
 746        SND_SOC_DAPM_OUTPUT("Internal DAC Sink"),
 747};
 748
 749static const struct snd_soc_dapm_route wm8991_dapm_routes[] = {
 750        /* Make DACs turn on when playing even if not mixed into any outputs */
 751        {"Internal DAC Sink", NULL, "Left DAC"},
 752        {"Internal DAC Sink", NULL, "Right DAC"},
 753
 754        /* Make ADCs turn on when recording even if not mixed from any inputs */
 755        {"Left ADC", NULL, "Internal ADC Source"},
 756        {"Right ADC", NULL, "Internal ADC Source"},
 757
 758        /* Input Side */
 759        {"INMIXL", NULL, "INL"},
 760        {"AINLMUX", NULL, "INL"},
 761        {"INMIXR", NULL, "INR"},
 762        {"AINRMUX", NULL, "INR"},
 763        /* LIN12 PGA */
 764        {"LIN12 PGA", "LIN1 Switch", "LIN1"},
 765        {"LIN12 PGA", "LIN2 Switch", "LIN2"},
 766        /* LIN34 PGA */
 767        {"LIN34 PGA", "LIN3 Switch", "LIN3"},
 768        {"LIN34 PGA", "LIN4 Switch", "LIN4RXN"},
 769        /* INMIXL */
 770        {"INMIXL", "Record Left Volume", "LOMIX"},
 771        {"INMIXL", "LIN2 Volume", "LIN2"},
 772        {"INMIXL", "LINPGA12 Switch", "LIN12 PGA"},
 773        {"INMIXL", "LINPGA34 Switch", "LIN34 PGA"},
 774        /* AINLMUX */
 775        {"AINLMUX", "INMIXL Mix", "INMIXL"},
 776        {"AINLMUX", "DIFFINL Mix", "LIN12 PGA"},
 777        {"AINLMUX", "DIFFINL Mix", "LIN34 PGA"},
 778        {"AINLMUX", "RXVOICE Mix", "LIN4RXN"},
 779        {"AINLMUX", "RXVOICE Mix", "RIN4RXP"},
 780        /* ADC */
 781        {"Left ADC", NULL, "AINLMUX"},
 782
 783        /* RIN12 PGA */
 784        {"RIN12 PGA", "RIN1 Switch", "RIN1"},
 785        {"RIN12 PGA", "RIN2 Switch", "RIN2"},
 786        /* RIN34 PGA */
 787        {"RIN34 PGA", "RIN3 Switch", "RIN3"},
 788        {"RIN34 PGA", "RIN4 Switch", "RIN4RXP"},
 789        /* INMIXL */
 790        {"INMIXR", "Record Right Volume", "ROMIX"},
 791        {"INMIXR", "RIN2 Volume", "RIN2"},
 792        {"INMIXR", "RINPGA12 Switch", "RIN12 PGA"},
 793        {"INMIXR", "RINPGA34 Switch", "RIN34 PGA"},
 794        /* AINRMUX */
 795        {"AINRMUX", "INMIXR Mix", "INMIXR"},
 796        {"AINRMUX", "DIFFINR Mix", "RIN12 PGA"},
 797        {"AINRMUX", "DIFFINR Mix", "RIN34 PGA"},
 798        {"AINRMUX", "RXVOICE Mix", "LIN4RXN"},
 799        {"AINRMUX", "RXVOICE Mix", "RIN4RXP"},
 800        /* ADC */
 801        {"Right ADC", NULL, "AINRMUX"},
 802
 803        /* LOMIX */
 804        {"LOMIX", "LOMIX RIN3 Bypass Switch", "RIN3"},
 805        {"LOMIX", "LOMIX LIN3 Bypass Switch", "LIN3"},
 806        {"LOMIX", "LOMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
 807        {"LOMIX", "LOMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
 808        {"LOMIX", "LOMIX Right ADC Bypass Switch", "AINRMUX"},
 809        {"LOMIX", "LOMIX Left ADC Bypass Switch", "AINLMUX"},
 810        {"LOMIX", "LOMIX Left DAC Switch", "Left DAC"},
 811
 812        /* ROMIX */
 813        {"ROMIX", "ROMIX RIN3 Bypass Switch", "RIN3"},
 814        {"ROMIX", "ROMIX LIN3 Bypass Switch", "LIN3"},
 815        {"ROMIX", "ROMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
 816        {"ROMIX", "ROMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
 817        {"ROMIX", "ROMIX Right ADC Bypass Switch", "AINRMUX"},
 818        {"ROMIX", "ROMIX Left ADC Bypass Switch", "AINLMUX"},
 819        {"ROMIX", "ROMIX Right DAC Switch", "Right DAC"},
 820
 821        /* SPKMIX */
 822        {"SPKMIX", "SPKMIX LIN2 Bypass Switch", "LIN2"},
 823        {"SPKMIX", "SPKMIX RIN2 Bypass Switch", "RIN2"},
 824        {"SPKMIX", "SPKMIX LADC Bypass Switch", "AINLMUX"},
 825        {"SPKMIX", "SPKMIX RADC Bypass Switch", "AINRMUX"},
 826        {"SPKMIX", "SPKMIX Left Mixer PGA Switch", "LOPGA"},
 827        {"SPKMIX", "SPKMIX Right Mixer PGA Switch", "ROPGA"},
 828        {"SPKMIX", "SPKMIX Right DAC Switch", "Right DAC"},
 829        {"SPKMIX", "SPKMIX Left DAC Switch", "Right DAC"},
 830
 831        /* LONMIX */
 832        {"LONMIX", "LONMIX Left Mixer PGA Switch", "LOPGA"},
 833        {"LONMIX", "LONMIX Right Mixer PGA Switch", "ROPGA"},
 834        {"LONMIX", "LONMIX Inverted LOP Switch", "LOPMIX"},
 835
 836        /* LOPMIX */
 837        {"LOPMIX", "LOPMIX Right Mic Bypass Switch", "RIN12 PGA"},
 838        {"LOPMIX", "LOPMIX Left Mic Bypass Switch", "LIN12 PGA"},
 839        {"LOPMIX", "LOPMIX Left Mixer PGA Switch", "LOPGA"},
 840
 841        /* OUT3MIX */
 842        {"OUT3MIX", "OUT3MIX LIN4RXN Bypass Switch", "LIN4RXN"},
 843        {"OUT3MIX", "OUT3MIX Left Out PGA Switch", "LOPGA"},
 844
 845        /* OUT4MIX */
 846        {"OUT4MIX", "OUT4MIX Right Out PGA Switch", "ROPGA"},
 847        {"OUT4MIX", "OUT4MIX RIN4RXP Bypass Switch", "RIN4RXP"},
 848
 849        /* RONMIX */
 850        {"RONMIX", "RONMIX Right Mixer PGA Switch", "ROPGA"},
 851        {"RONMIX", "RONMIX Left Mixer PGA Switch", "LOPGA"},
 852        {"RONMIX", "RONMIX Inverted ROP Switch", "ROPMIX"},
 853
 854        /* ROPMIX */
 855        {"ROPMIX", "ROPMIX Left Mic Bypass Switch", "LIN12 PGA"},
 856        {"ROPMIX", "ROPMIX Right Mic Bypass Switch", "RIN12 PGA"},
 857        {"ROPMIX", "ROPMIX Right Mixer PGA Switch", "ROPGA"},
 858
 859        /* Out Mixer PGAs */
 860        {"LOPGA", NULL, "LOMIX"},
 861        {"ROPGA", NULL, "ROMIX"},
 862
 863        {"LOUT PGA", NULL, "LOMIX"},
 864        {"ROUT PGA", NULL, "ROMIX"},
 865
 866        /* Output Pins */
 867        {"LON", NULL, "LONMIX"},
 868        {"LOP", NULL, "LOPMIX"},
 869        {"OUT", NULL, "OUT3MIX"},
 870        {"LOUT", NULL, "LOUT PGA"},
 871        {"SPKN", NULL, "SPKMIX"},
 872        {"ROUT", NULL, "ROUT PGA"},
 873        {"OUT4", NULL, "OUT4MIX"},
 874        {"ROP", NULL, "ROPMIX"},
 875        {"RON", NULL, "RONMIX"},
 876};
 877
 878/* PLL divisors */
 879struct _pll_div {
 880        u32 div2;
 881        u32 n;
 882        u32 k;
 883};
 884
 885/* The size in bits of the pll divide multiplied by 10
 886 * to allow rounding later */
 887#define FIXED_PLL_SIZE ((1 << 16) * 10)
 888
 889static void pll_factors(struct _pll_div *pll_div, unsigned int target,
 890                        unsigned int source)
 891{
 892        u64 Kpart;
 893        unsigned int K, Ndiv, Nmod;
 894
 895
 896        Ndiv = target / source;
 897        if (Ndiv < 6) {
 898                source >>= 1;
 899                pll_div->div2 = 1;
 900                Ndiv = target / source;
 901        } else
 902                pll_div->div2 = 0;
 903
 904        if ((Ndiv < 6) || (Ndiv > 12))
 905                printk(KERN_WARNING
 906                       "WM8991 N value outwith recommended range! N = %d\n", Ndiv);
 907
 908        pll_div->n = Ndiv;
 909        Nmod = target % source;
 910        Kpart = FIXED_PLL_SIZE * (long long)Nmod;
 911
 912        do_div(Kpart, source);
 913
 914        K = Kpart & 0xFFFFFFFF;
 915
 916        /* Check if we need to round */
 917        if ((K % 10) >= 5)
 918                K += 5;
 919
 920        /* Move down to proper range now rounding is done */
 921        K /= 10;
 922
 923        pll_div->k = K;
 924}
 925
 926static int wm8991_set_dai_pll(struct snd_soc_dai *codec_dai,
 927                              int pll_id, int src, unsigned int freq_in, unsigned int freq_out)
 928{
 929        u16 reg;
 930        struct snd_soc_codec *codec = codec_dai->codec;
 931        struct _pll_div pll_div;
 932
 933        if (freq_in && freq_out) {
 934                pll_factors(&pll_div, freq_out * 4, freq_in);
 935
 936                /* Turn on PLL */
 937                reg = snd_soc_read(codec, WM8991_POWER_MANAGEMENT_2);
 938                reg |= WM8991_PLL_ENA;
 939                snd_soc_write(codec, WM8991_POWER_MANAGEMENT_2, reg);
 940
 941                /* sysclk comes from PLL */
 942                reg = snd_soc_read(codec, WM8991_CLOCKING_2);
 943                snd_soc_write(codec, WM8991_CLOCKING_2, reg | WM8991_SYSCLK_SRC);
 944
 945                /* set up N , fractional mode and pre-divisor if necessary */
 946                snd_soc_write(codec, WM8991_PLL1, pll_div.n | WM8991_SDM |
 947                              (pll_div.div2 ? WM8991_PRESCALE : 0));
 948                snd_soc_write(codec, WM8991_PLL2, (u8)(pll_div.k>>8));
 949                snd_soc_write(codec, WM8991_PLL3, (u8)(pll_div.k & 0xFF));
 950        } else {
 951                /* Turn on PLL */
 952                reg = snd_soc_read(codec, WM8991_POWER_MANAGEMENT_2);
 953                reg &= ~WM8991_PLL_ENA;
 954                snd_soc_write(codec, WM8991_POWER_MANAGEMENT_2, reg);
 955        }
 956        return 0;
 957}
 958
 959/*
 960 * Set's ADC and Voice DAC format.
 961 */
 962static int wm8991_set_dai_fmt(struct snd_soc_dai *codec_dai,
 963                              unsigned int fmt)
 964{
 965        struct snd_soc_codec *codec = codec_dai->codec;
 966        u16 audio1, audio3;
 967
 968        audio1 = snd_soc_read(codec, WM8991_AUDIO_INTERFACE_1);
 969        audio3 = snd_soc_read(codec, WM8991_AUDIO_INTERFACE_3);
 970
 971        /* set master/slave audio interface */
 972        switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 973        case SND_SOC_DAIFMT_CBS_CFS:
 974                audio3 &= ~WM8991_AIF_MSTR1;
 975                break;
 976        case SND_SOC_DAIFMT_CBM_CFM:
 977                audio3 |= WM8991_AIF_MSTR1;
 978                break;
 979        default:
 980                return -EINVAL;
 981        }
 982
 983        audio1 &= ~WM8991_AIF_FMT_MASK;
 984
 985        /* interface format */
 986        switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 987        case SND_SOC_DAIFMT_I2S:
 988                audio1 |= WM8991_AIF_TMF_I2S;
 989                audio1 &= ~WM8991_AIF_LRCLK_INV;
 990                break;
 991        case SND_SOC_DAIFMT_RIGHT_J:
 992                audio1 |= WM8991_AIF_TMF_RIGHTJ;
 993                audio1 &= ~WM8991_AIF_LRCLK_INV;
 994                break;
 995        case SND_SOC_DAIFMT_LEFT_J:
 996                audio1 |= WM8991_AIF_TMF_LEFTJ;
 997                audio1 &= ~WM8991_AIF_LRCLK_INV;
 998                break;
 999        case SND_SOC_DAIFMT_DSP_A:
1000                audio1 |= WM8991_AIF_TMF_DSP;
1001                audio1 &= ~WM8991_AIF_LRCLK_INV;
1002                break;
1003        case SND_SOC_DAIFMT_DSP_B:
1004                audio1 |= WM8991_AIF_TMF_DSP | WM8991_AIF_LRCLK_INV;
1005                break;
1006        default:
1007                return -EINVAL;
1008        }
1009
1010        snd_soc_write(codec, WM8991_AUDIO_INTERFACE_1, audio1);
1011        snd_soc_write(codec, WM8991_AUDIO_INTERFACE_3, audio3);
1012        return 0;
1013}
1014
1015static int wm8991_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
1016                                 int div_id, int div)
1017{
1018        struct snd_soc_codec *codec = codec_dai->codec;
1019        u16 reg;
1020
1021        switch (div_id) {
1022        case WM8991_MCLK_DIV:
1023                reg = snd_soc_read(codec, WM8991_CLOCKING_2) &
1024                      ~WM8991_MCLK_DIV_MASK;
1025                snd_soc_write(codec, WM8991_CLOCKING_2, reg | div);
1026                break;
1027        case WM8991_DACCLK_DIV:
1028                reg = snd_soc_read(codec, WM8991_CLOCKING_2) &
1029                      ~WM8991_DAC_CLKDIV_MASK;
1030                snd_soc_write(codec, WM8991_CLOCKING_2, reg | div);
1031                break;
1032        case WM8991_ADCCLK_DIV:
1033                reg = snd_soc_read(codec, WM8991_CLOCKING_2) &
1034                      ~WM8991_ADC_CLKDIV_MASK;
1035                snd_soc_write(codec, WM8991_CLOCKING_2, reg | div);
1036                break;
1037        case WM8991_BCLK_DIV:
1038                reg = snd_soc_read(codec, WM8991_CLOCKING_1) &
1039                      ~WM8991_BCLK_DIV_MASK;
1040                snd_soc_write(codec, WM8991_CLOCKING_1, reg | div);
1041                break;
1042        default:
1043                return -EINVAL;
1044        }
1045
1046        return 0;
1047}
1048
1049/*
1050 * Set PCM DAI bit size and sample rate.
1051 */
1052static int wm8991_hw_params(struct snd_pcm_substream *substream,
1053                            struct snd_pcm_hw_params *params,
1054                            struct snd_soc_dai *dai)
1055{
1056        struct snd_soc_codec *codec = dai->codec;
1057        u16 audio1 = snd_soc_read(codec, WM8991_AUDIO_INTERFACE_1);
1058
1059        audio1 &= ~WM8991_AIF_WL_MASK;
1060        /* bit size */
1061        switch (params_width(params)) {
1062        case 16:
1063                break;
1064        case 20:
1065                audio1 |= WM8991_AIF_WL_20BITS;
1066                break;
1067        case 24:
1068                audio1 |= WM8991_AIF_WL_24BITS;
1069                break;
1070        case 32:
1071                audio1 |= WM8991_AIF_WL_32BITS;
1072                break;
1073        }
1074
1075        snd_soc_write(codec, WM8991_AUDIO_INTERFACE_1, audio1);
1076        return 0;
1077}
1078
1079static int wm8991_mute(struct snd_soc_dai *dai, int mute)
1080{
1081        struct snd_soc_codec *codec = dai->codec;
1082        u16 val;
1083
1084        val  = snd_soc_read(codec, WM8991_DAC_CTRL) & ~WM8991_DAC_MUTE;
1085        if (mute)
1086                snd_soc_write(codec, WM8991_DAC_CTRL, val | WM8991_DAC_MUTE);
1087        else
1088                snd_soc_write(codec, WM8991_DAC_CTRL, val);
1089        return 0;
1090}
1091
1092static int wm8991_set_bias_level(struct snd_soc_codec *codec,
1093                                 enum snd_soc_bias_level level)
1094{
1095        struct wm8991_priv *wm8991 = snd_soc_codec_get_drvdata(codec);
1096        u16 val;
1097
1098        switch (level) {
1099        case SND_SOC_BIAS_ON:
1100                break;
1101
1102        case SND_SOC_BIAS_PREPARE:
1103                /* VMID=2*50k */
1104                val = snd_soc_read(codec, WM8991_POWER_MANAGEMENT_1) &
1105                      ~WM8991_VMID_MODE_MASK;
1106                snd_soc_write(codec, WM8991_POWER_MANAGEMENT_1, val | 0x2);
1107                break;
1108
1109        case SND_SOC_BIAS_STANDBY:
1110                if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
1111                        regcache_sync(wm8991->regmap);
1112                        /* Enable all output discharge bits */
1113                        snd_soc_write(codec, WM8991_ANTIPOP1, WM8991_DIS_LLINE |
1114                                      WM8991_DIS_RLINE | WM8991_DIS_OUT3 |
1115                                      WM8991_DIS_OUT4 | WM8991_DIS_LOUT |
1116                                      WM8991_DIS_ROUT);
1117
1118                        /* Enable POBCTRL, SOFT_ST, VMIDTOG and BUFDCOPEN */
1119                        snd_soc_write(codec, WM8991_ANTIPOP2, WM8991_SOFTST |
1120                                      WM8991_BUFDCOPEN | WM8991_POBCTRL |
1121                                      WM8991_VMIDTOG);
1122
1123                        /* Delay to allow output caps to discharge */
1124                        msleep(300);
1125
1126                        /* Disable VMIDTOG */
1127                        snd_soc_write(codec, WM8991_ANTIPOP2, WM8991_SOFTST |
1128                                      WM8991_BUFDCOPEN | WM8991_POBCTRL);
1129
1130                        /* disable all output discharge bits */
1131                        snd_soc_write(codec, WM8991_ANTIPOP1, 0);
1132
1133                        /* Enable outputs */
1134                        snd_soc_write(codec, WM8991_POWER_MANAGEMENT_1, 0x1b00);
1135
1136                        msleep(50);
1137
1138                        /* Enable VMID at 2x50k */
1139                        snd_soc_write(codec, WM8991_POWER_MANAGEMENT_1, 0x1f02);
1140
1141                        msleep(100);
1142
1143                        /* Enable VREF */
1144                        snd_soc_write(codec, WM8991_POWER_MANAGEMENT_1, 0x1f03);
1145
1146                        msleep(600);
1147
1148                        /* Enable BUFIOEN */
1149                        snd_soc_write(codec, WM8991_ANTIPOP2, WM8991_SOFTST |
1150                                      WM8991_BUFDCOPEN | WM8991_POBCTRL |
1151                                      WM8991_BUFIOEN);
1152
1153                        /* Disable outputs */
1154                        snd_soc_write(codec, WM8991_POWER_MANAGEMENT_1, 0x3);
1155
1156                        /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
1157                        snd_soc_write(codec, WM8991_ANTIPOP2, WM8991_BUFIOEN);
1158                }
1159
1160                /* VMID=2*250k */
1161                val = snd_soc_read(codec, WM8991_POWER_MANAGEMENT_1) &
1162                      ~WM8991_VMID_MODE_MASK;
1163                snd_soc_write(codec, WM8991_POWER_MANAGEMENT_1, val | 0x4);
1164                break;
1165
1166        case SND_SOC_BIAS_OFF:
1167                /* Enable POBCTRL and SOFT_ST */
1168                snd_soc_write(codec, WM8991_ANTIPOP2, WM8991_SOFTST |
1169                              WM8991_POBCTRL | WM8991_BUFIOEN);
1170
1171                /* Enable POBCTRL, SOFT_ST and BUFDCOPEN */
1172                snd_soc_write(codec, WM8991_ANTIPOP2, WM8991_SOFTST |
1173                              WM8991_BUFDCOPEN | WM8991_POBCTRL |
1174                              WM8991_BUFIOEN);
1175
1176                /* mute DAC */
1177                val = snd_soc_read(codec, WM8991_DAC_CTRL);
1178                snd_soc_write(codec, WM8991_DAC_CTRL, val | WM8991_DAC_MUTE);
1179
1180                /* Enable any disabled outputs */
1181                snd_soc_write(codec, WM8991_POWER_MANAGEMENT_1, 0x1f03);
1182
1183                /* Disable VMID */
1184                snd_soc_write(codec, WM8991_POWER_MANAGEMENT_1, 0x1f01);
1185
1186                msleep(300);
1187
1188                /* Enable all output discharge bits */
1189                snd_soc_write(codec, WM8991_ANTIPOP1, WM8991_DIS_LLINE |
1190                              WM8991_DIS_RLINE | WM8991_DIS_OUT3 |
1191                              WM8991_DIS_OUT4 | WM8991_DIS_LOUT |
1192                              WM8991_DIS_ROUT);
1193
1194                /* Disable VREF */
1195                snd_soc_write(codec, WM8991_POWER_MANAGEMENT_1, 0x0);
1196
1197                /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
1198                snd_soc_write(codec, WM8991_ANTIPOP2, 0x0);
1199                regcache_mark_dirty(wm8991->regmap);
1200                break;
1201        }
1202
1203        return 0;
1204}
1205
1206#define WM8991_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1207                        SNDRV_PCM_FMTBIT_S24_LE)
1208
1209static const struct snd_soc_dai_ops wm8991_ops = {
1210        .hw_params = wm8991_hw_params,
1211        .digital_mute = wm8991_mute,
1212        .set_fmt = wm8991_set_dai_fmt,
1213        .set_clkdiv = wm8991_set_dai_clkdiv,
1214        .set_pll = wm8991_set_dai_pll
1215};
1216
1217/*
1218 * The WM8991 supports 2 different and mutually exclusive DAI
1219 * configurations.
1220 *
1221 * 1. ADC/DAC on Primary Interface
1222 * 2. ADC on Primary Interface/DAC on secondary
1223 */
1224static struct snd_soc_dai_driver wm8991_dai = {
1225        /* ADC/DAC on primary */
1226        .name = "wm8991",
1227        .id = 1,
1228        .playback = {
1229                .stream_name = "Playback",
1230                .channels_min = 1,
1231                .channels_max = 2,
1232                .rates = SNDRV_PCM_RATE_8000_96000,
1233                .formats = WM8991_FORMATS
1234        },
1235        .capture = {
1236                .stream_name = "Capture",
1237                .channels_min = 1,
1238                .channels_max = 2,
1239                .rates = SNDRV_PCM_RATE_8000_96000,
1240                .formats = WM8991_FORMATS
1241        },
1242        .ops = &wm8991_ops
1243};
1244
1245static const struct snd_soc_codec_driver soc_codec_dev_wm8991 = {
1246        .set_bias_level = wm8991_set_bias_level,
1247        .suspend_bias_off = true,
1248
1249        .component_driver = {
1250                .controls               = wm8991_snd_controls,
1251                .num_controls           = ARRAY_SIZE(wm8991_snd_controls),
1252                .dapm_widgets           = wm8991_dapm_widgets,
1253                .num_dapm_widgets       = ARRAY_SIZE(wm8991_dapm_widgets),
1254                .dapm_routes            = wm8991_dapm_routes,
1255                .num_dapm_routes        = ARRAY_SIZE(wm8991_dapm_routes),
1256        },
1257};
1258
1259static const struct regmap_config wm8991_regmap = {
1260        .reg_bits = 8,
1261        .val_bits = 16,
1262
1263        .max_register = WM8991_PLL3,
1264        .volatile_reg = wm8991_volatile,
1265        .reg_defaults = wm8991_reg_defaults,
1266        .num_reg_defaults = ARRAY_SIZE(wm8991_reg_defaults),
1267        .cache_type = REGCACHE_RBTREE,
1268};
1269
1270static int wm8991_i2c_probe(struct i2c_client *i2c,
1271                            const struct i2c_device_id *id)
1272{
1273        struct wm8991_priv *wm8991;
1274        unsigned int val;
1275        int ret;
1276
1277        wm8991 = devm_kzalloc(&i2c->dev, sizeof(*wm8991), GFP_KERNEL);
1278        if (!wm8991)
1279                return -ENOMEM;
1280
1281        wm8991->regmap = devm_regmap_init_i2c(i2c, &wm8991_regmap);
1282        if (IS_ERR(wm8991->regmap))
1283                return PTR_ERR(wm8991->regmap);
1284
1285        i2c_set_clientdata(i2c, wm8991);
1286
1287        ret = regmap_read(wm8991->regmap, WM8991_RESET, &val);
1288        if (ret != 0) {
1289                dev_err(&i2c->dev, "Failed to read device ID: %d\n", ret);
1290                return ret;
1291        }
1292        if (val != 0x8991) {
1293                dev_err(&i2c->dev, "Device with ID %x is not a WM8991\n", val);
1294                return -EINVAL;
1295        }
1296
1297        ret = regmap_write(wm8991->regmap, WM8991_RESET, 0);
1298        if (ret < 0) {
1299                dev_err(&i2c->dev, "Failed to issue reset: %d\n", ret);
1300                return ret;
1301        }
1302
1303        regmap_update_bits(wm8991->regmap, WM8991_AUDIO_INTERFACE_4,
1304                           WM8991_ALRCGPIO1, WM8991_ALRCGPIO1);
1305
1306        regmap_update_bits(wm8991->regmap, WM8991_GPIO1_GPIO2,
1307                           WM8991_GPIO1_SEL_MASK, 1);
1308
1309        regmap_update_bits(wm8991->regmap, WM8991_POWER_MANAGEMENT_1,
1310                           WM8991_VREF_ENA | WM8991_VMID_MODE_MASK,
1311                           WM8991_VREF_ENA | WM8991_VMID_MODE_MASK);
1312
1313        regmap_update_bits(wm8991->regmap, WM8991_POWER_MANAGEMENT_2,
1314                           WM8991_OPCLK_ENA, WM8991_OPCLK_ENA);
1315
1316        regmap_write(wm8991->regmap, WM8991_DAC_CTRL, 0);
1317        regmap_write(wm8991->regmap, WM8991_LEFT_OUTPUT_VOLUME,
1318                     0x50 | (1<<8));
1319        regmap_write(wm8991->regmap, WM8991_RIGHT_OUTPUT_VOLUME,
1320                     0x50 | (1<<8));
1321
1322        ret = snd_soc_register_codec(&i2c->dev,
1323                                     &soc_codec_dev_wm8991, &wm8991_dai, 1);
1324
1325        return ret;
1326}
1327
1328static int wm8991_i2c_remove(struct i2c_client *client)
1329{
1330        snd_soc_unregister_codec(&client->dev);
1331
1332        return 0;
1333}
1334
1335static const struct i2c_device_id wm8991_i2c_id[] = {
1336        { "wm8991", 0 },
1337        { }
1338};
1339MODULE_DEVICE_TABLE(i2c, wm8991_i2c_id);
1340
1341static struct i2c_driver wm8991_i2c_driver = {
1342        .driver = {
1343                .name = "wm8991",
1344        },
1345        .probe = wm8991_i2c_probe,
1346        .remove = wm8991_i2c_remove,
1347        .id_table = wm8991_i2c_id,
1348};
1349
1350module_i2c_driver(wm8991_i2c_driver);
1351
1352MODULE_DESCRIPTION("ASoC WM8991 driver");
1353MODULE_AUTHOR("Graeme Gregory");
1354MODULE_LICENSE("GPL");
1355