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21#ifndef __SKL_TOPOLOGY_H__
22#define __SKL_TOPOLOGY_H__
23
24#include <linux/types.h>
25
26#include <sound/hdaudio_ext.h>
27#include <sound/soc.h>
28#include "skl.h"
29#include "skl-tplg-interface.h"
30
31#define BITS_PER_BYTE 8
32#define MAX_TS_GROUPS 8
33#define MAX_DMIC_TS_GROUPS 4
34#define MAX_FIXED_DMIC_PARAMS_SIZE 727
35
36
37#define UP_DOWN_MIXER_MAX_COEFF 6
38
39#define MODULE_MAX_IN_PINS 8
40#define MODULE_MAX_OUT_PINS 8
41
42enum skl_channel_index {
43 SKL_CHANNEL_LEFT = 0,
44 SKL_CHANNEL_RIGHT = 1,
45 SKL_CHANNEL_CENTER = 2,
46 SKL_CHANNEL_LEFT_SURROUND = 3,
47 SKL_CHANNEL_CENTER_SURROUND = 3,
48 SKL_CHANNEL_RIGHT_SURROUND = 4,
49 SKL_CHANNEL_LFE = 7,
50 SKL_CHANNEL_INVALID = 0xF,
51};
52
53enum skl_bitdepth {
54 SKL_DEPTH_8BIT = 8,
55 SKL_DEPTH_16BIT = 16,
56 SKL_DEPTH_24BIT = 24,
57 SKL_DEPTH_32BIT = 32,
58 SKL_DEPTH_INVALID
59};
60
61
62enum skl_s_freq {
63 SKL_FS_8000 = 8000,
64 SKL_FS_11025 = 11025,
65 SKL_FS_12000 = 12000,
66 SKL_FS_16000 = 16000,
67 SKL_FS_22050 = 22050,
68 SKL_FS_24000 = 24000,
69 SKL_FS_32000 = 32000,
70 SKL_FS_44100 = 44100,
71 SKL_FS_48000 = 48000,
72 SKL_FS_64000 = 64000,
73 SKL_FS_88200 = 88200,
74 SKL_FS_96000 = 96000,
75 SKL_FS_128000 = 128000,
76 SKL_FS_176400 = 176400,
77 SKL_FS_192000 = 192000,
78 SKL_FS_INVALID
79};
80
81enum skl_widget_type {
82 SKL_WIDGET_VMIXER = 1,
83 SKL_WIDGET_MIXER = 2,
84 SKL_WIDGET_PGA = 3,
85 SKL_WIDGET_MUX = 4
86};
87
88struct skl_audio_data_format {
89 enum skl_s_freq s_freq;
90 enum skl_bitdepth bit_depth;
91 u32 channel_map;
92 enum skl_ch_cfg ch_cfg;
93 enum skl_interleaving interleaving;
94 u8 number_of_channels;
95 u8 valid_bit_depth;
96 u8 sample_type;
97 u8 reserved[1];
98} __packed;
99
100struct skl_base_cfg {
101 u32 cps;
102 u32 ibs;
103 u32 obs;
104 u32 is_pages;
105 struct skl_audio_data_format audio_fmt;
106};
107
108struct skl_cpr_gtw_cfg {
109 u32 node_id;
110 u32 dma_buffer_size;
111 u32 config_length;
112
113 u32 config_data[1];
114} __packed;
115
116struct skl_i2s_config_blob {
117 u32 gateway_attrib;
118 u32 tdm_ts_group[8];
119 u32 ssc0;
120 u32 ssc1;
121 u32 sscto;
122 u32 sspsp;
123 u32 sstsa;
124 u32 ssrsa;
125 u32 ssc2;
126 u32 sspsp2;
127 u32 ssc3;
128 u32 ssioc;
129 u32 mdivc;
130 u32 mdivr;
131} __packed;
132
133struct skl_dma_control {
134 u32 node_id;
135 u32 config_length;
136 u32 config_data[0];
137} __packed;
138
139struct skl_cpr_cfg {
140 struct skl_base_cfg base_cfg;
141 struct skl_audio_data_format out_fmt;
142 u32 cpr_feature_mask;
143 struct skl_cpr_gtw_cfg gtw_cfg;
144} __packed;
145
146
147struct skl_src_module_cfg {
148 struct skl_base_cfg base_cfg;
149 enum skl_s_freq src_cfg;
150} __packed;
151
152struct notification_mask {
153 u32 notify;
154 u32 enable;
155} __packed;
156
157struct skl_up_down_mixer_cfg {
158 struct skl_base_cfg base_cfg;
159 enum skl_ch_cfg out_ch_cfg;
160
161 u32 coeff_sel;
162
163 s32 coeff[UP_DOWN_MIXER_MAX_COEFF];
164} __packed;
165
166struct skl_algo_cfg {
167 struct skl_base_cfg base_cfg;
168 char params[0];
169} __packed;
170
171struct skl_base_outfmt_cfg {
172 struct skl_base_cfg base_cfg;
173 struct skl_audio_data_format out_fmt;
174} __packed;
175
176enum skl_dma_type {
177 SKL_DMA_HDA_HOST_OUTPUT_CLASS = 0,
178 SKL_DMA_HDA_HOST_INPUT_CLASS = 1,
179 SKL_DMA_HDA_HOST_INOUT_CLASS = 2,
180 SKL_DMA_HDA_LINK_OUTPUT_CLASS = 8,
181 SKL_DMA_HDA_LINK_INPUT_CLASS = 9,
182 SKL_DMA_HDA_LINK_INOUT_CLASS = 0xA,
183 SKL_DMA_DMIC_LINK_INPUT_CLASS = 0xB,
184 SKL_DMA_I2S_LINK_OUTPUT_CLASS = 0xC,
185 SKL_DMA_I2S_LINK_INPUT_CLASS = 0xD,
186};
187
188union skl_ssp_dma_node {
189 u8 val;
190 struct {
191 u8 time_slot_index:4;
192 u8 i2s_instance:4;
193 } dma_node;
194};
195
196union skl_connector_node_id {
197 u32 val;
198 struct {
199 u32 vindex:8;
200 u32 dma_type:4;
201 u32 rsvd:20;
202 } node;
203};
204
205struct skl_module_fmt {
206 u32 channels;
207 u32 s_freq;
208 u32 bit_depth;
209 u32 valid_bit_depth;
210 u32 ch_cfg;
211 u32 interleaving_style;
212 u32 sample_type;
213 u32 ch_map;
214};
215
216struct skl_module_cfg;
217
218struct skl_mod_inst_map {
219 u16 mod_id;
220 u16 inst_id;
221};
222
223struct skl_kpb_params {
224 u32 num_modules;
225 struct skl_mod_inst_map map[0];
226};
227
228struct skl_module_inst_id {
229 int module_id;
230 u32 instance_id;
231 int pvt_id;
232};
233
234enum skl_module_pin_state {
235 SKL_PIN_UNBIND = 0,
236 SKL_PIN_BIND_DONE = 1,
237};
238
239struct skl_module_pin {
240 struct skl_module_inst_id id;
241 bool is_dynamic;
242 bool in_use;
243 enum skl_module_pin_state pin_state;
244 struct skl_module_cfg *tgt_mcfg;
245};
246
247struct skl_specific_cfg {
248 u32 set_params;
249 u32 param_id;
250 u32 caps_size;
251 u32 *caps;
252};
253
254enum skl_pipe_state {
255 SKL_PIPE_INVALID = 0,
256 SKL_PIPE_CREATED = 1,
257 SKL_PIPE_PAUSED = 2,
258 SKL_PIPE_STARTED = 3,
259 SKL_PIPE_RESET = 4
260};
261
262struct skl_pipe_module {
263 struct snd_soc_dapm_widget *w;
264 struct list_head node;
265};
266
267struct skl_pipe_params {
268 u8 host_dma_id;
269 u8 link_dma_id;
270 u32 ch;
271 u32 s_freq;
272 u32 s_fmt;
273 u8 linktype;
274 int stream;
275};
276
277struct skl_pipe {
278 u8 ppl_id;
279 u8 pipe_priority;
280 u16 conn_type;
281 u32 memory_pages;
282 struct skl_pipe_params *p_params;
283 enum skl_pipe_state state;
284 struct list_head w_list;
285 bool passthru;
286};
287
288enum skl_module_state {
289 SKL_MODULE_UNINIT = 0,
290 SKL_MODULE_LOADED = 1,
291 SKL_MODULE_INIT_DONE = 2,
292 SKL_MODULE_BIND_DONE = 3,
293 SKL_MODULE_UNLOADED = 4,
294};
295
296struct skl_module_cfg {
297 u8 guid[16];
298 struct skl_module_inst_id id;
299 u8 domain;
300 bool homogenous_inputs;
301 bool homogenous_outputs;
302 struct skl_module_fmt in_fmt[MODULE_MAX_IN_PINS];
303 struct skl_module_fmt out_fmt[MODULE_MAX_OUT_PINS];
304 u8 max_in_queue;
305 u8 max_out_queue;
306 u8 in_queue_mask;
307 u8 out_queue_mask;
308 u8 in_queue;
309 u8 out_queue;
310 u32 mcps;
311 u32 ibs;
312 u32 obs;
313 u8 is_loadable;
314 u8 core_id;
315 u8 dev_type;
316 u8 dma_id;
317 u8 time_slot;
318 u32 params_fixup;
319 u32 converter;
320 u32 vbus_id;
321 u32 mem_pages;
322 struct skl_module_pin *m_in_pin;
323 struct skl_module_pin *m_out_pin;
324 enum skl_module_type m_type;
325 enum skl_hw_conn_type hw_conn_type;
326 enum skl_module_state m_state;
327 struct skl_pipe *pipe;
328 struct skl_specific_cfg formats_config;
329};
330
331struct skl_algo_data {
332 u32 param_id;
333 u32 set_params;
334 u32 max;
335 u32 size;
336 char *params;
337};
338
339struct skl_pipeline {
340 struct skl_pipe *pipe;
341 struct list_head node;
342};
343
344static inline struct skl *get_skl_ctx(struct device *dev)
345{
346 struct hdac_ext_bus *ebus = dev_get_drvdata(dev);
347
348 return ebus_to_skl(ebus);
349}
350
351int skl_tplg_be_update_params(struct snd_soc_dai *dai,
352 struct skl_pipe_params *params);
353int skl_dsp_set_dma_control(struct skl_sst *ctx,
354 struct skl_module_cfg *mconfig);
355void skl_tplg_set_be_dmic_config(struct snd_soc_dai *dai,
356 struct skl_pipe_params *params, int stream);
357int skl_tplg_init(struct snd_soc_platform *platform,
358 struct hdac_ext_bus *ebus);
359struct skl_module_cfg *skl_tplg_fe_get_cpr_module(
360 struct snd_soc_dai *dai, int stream);
361int skl_tplg_update_pipe_params(struct device *dev,
362 struct skl_module_cfg *mconfig, struct skl_pipe_params *params);
363
364int skl_create_pipeline(struct skl_sst *ctx, struct skl_pipe *pipe);
365
366int skl_run_pipe(struct skl_sst *ctx, struct skl_pipe *pipe);
367
368int skl_pause_pipe(struct skl_sst *ctx, struct skl_pipe *pipe);
369
370int skl_delete_pipe(struct skl_sst *ctx, struct skl_pipe *pipe);
371
372int skl_stop_pipe(struct skl_sst *ctx, struct skl_pipe *pipe);
373
374int skl_reset_pipe(struct skl_sst *ctx, struct skl_pipe *pipe);
375
376int skl_init_module(struct skl_sst *ctx, struct skl_module_cfg *module_config);
377
378int skl_bind_modules(struct skl_sst *ctx, struct skl_module_cfg
379 *src_module, struct skl_module_cfg *dst_module);
380
381int skl_unbind_modules(struct skl_sst *ctx, struct skl_module_cfg
382 *src_module, struct skl_module_cfg *dst_module);
383
384int skl_set_module_params(struct skl_sst *ctx, u32 *params, int size,
385 u32 param_id, struct skl_module_cfg *mcfg);
386int skl_get_module_params(struct skl_sst *ctx, u32 *params, int size,
387 u32 param_id, struct skl_module_cfg *mcfg);
388
389struct skl_module_cfg *skl_tplg_be_get_cpr_module(struct snd_soc_dai *dai,
390 int stream);
391enum skl_bitdepth skl_get_bit_depth(int params);
392#endif
393
