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11#define pr_fmt(fmt) "MityOMAPL138: " fmt
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/console.h>
16#include <linux/platform_device.h>
17#include <linux/mtd/partitions.h>
18#include <linux/nvmem-provider.h>
19#include <linux/regulator/machine.h>
20#include <linux/i2c.h>
21#include <linux/platform_data/at24.h>
22#include <linux/etherdevice.h>
23#include <linux/spi/spi.h>
24#include <linux/spi/flash.h>
25
26#include <asm/io.h>
27#include <asm/mach-types.h>
28#include <asm/mach/arch.h>
29#include <mach/common.h>
30#include "cp_intc.h"
31#include <mach/da8xx.h>
32#include <linux/platform_data/mtd-davinci.h>
33#include <linux/platform_data/mtd-davinci-aemif.h>
34#include <linux/platform_data/ti-aemif.h>
35#include <mach/mux.h>
36#include <linux/platform_data/spi-davinci.h>
37
38#define MITYOMAPL138_PHY_ID ""
39
40#define FACTORY_CONFIG_MAGIC 0x012C0138
41#define FACTORY_CONFIG_VERSION 0x00010001
42
43
44struct factory_config {
45 u32 magic;
46 u32 version;
47 u8 mac[6];
48 u32 fpga_type;
49 u32 spare;
50 u32 serialnumber;
51 char partnum[32];
52};
53
54static struct factory_config factory_config;
55
56#ifdef CONFIG_CPU_FREQ
57struct part_no_info {
58 const char *part_no;
59 int max_freq;
60};
61
62static struct part_no_info mityomapl138_pn_info[] = {
63 {
64 .part_no = "L138-C",
65 .max_freq = 300000,
66 },
67 {
68 .part_no = "L138-D",
69 .max_freq = 375000,
70 },
71 {
72 .part_no = "L138-F",
73 .max_freq = 456000,
74 },
75 {
76 .part_no = "1808-C",
77 .max_freq = 300000,
78 },
79 {
80 .part_no = "1808-D",
81 .max_freq = 375000,
82 },
83 {
84 .part_no = "1808-F",
85 .max_freq = 456000,
86 },
87 {
88 .part_no = "1810-D",
89 .max_freq = 375000,
90 },
91};
92
93static void mityomapl138_cpufreq_init(const char *partnum)
94{
95 int i, ret;
96
97 for (i = 0; partnum && i < ARRAY_SIZE(mityomapl138_pn_info); i++) {
98
99
100
101
102
103
104
105 if (!strncmp(partnum, mityomapl138_pn_info[i].part_no,
106 strlen(mityomapl138_pn_info[i].part_no))) {
107 da850_max_speed = mityomapl138_pn_info[i].max_freq;
108 break;
109 }
110 }
111
112 ret = da850_register_cpufreq("pll0_sysclk3");
113 if (ret)
114 pr_warn("cpufreq registration failed: %d\n", ret);
115}
116#else
117static void mityomapl138_cpufreq_init(const char *partnum) { }
118#endif
119
120static void read_factory_config(struct nvmem_device *nvmem, void *context)
121{
122 int ret;
123 const char *partnum = NULL;
124 struct davinci_soc_info *soc_info = &davinci_soc_info;
125
126 if (!IS_BUILTIN(CONFIG_NVMEM)) {
127 pr_warn("Factory Config not available without CONFIG_NVMEM\n");
128 goto bad_config;
129 }
130
131 ret = nvmem_device_read(nvmem, 0, sizeof(factory_config),
132 &factory_config);
133 if (ret != sizeof(struct factory_config)) {
134 pr_warn("Read Factory Config Failed: %d\n", ret);
135 goto bad_config;
136 }
137
138 if (factory_config.magic != FACTORY_CONFIG_MAGIC) {
139 pr_warn("Factory Config Magic Wrong (%X)\n",
140 factory_config.magic);
141 goto bad_config;
142 }
143
144 if (factory_config.version != FACTORY_CONFIG_VERSION) {
145 pr_warn("Factory Config Version Wrong (%X)\n",
146 factory_config.version);
147 goto bad_config;
148 }
149
150 pr_info("Found MAC = %pM\n", factory_config.mac);
151 if (is_valid_ether_addr(factory_config.mac))
152 memcpy(soc_info->emac_pdata->mac_addr,
153 factory_config.mac, ETH_ALEN);
154 else
155 pr_warn("Invalid MAC found in factory config block\n");
156
157 partnum = factory_config.partnum;
158 pr_info("Part Number = %s\n", partnum);
159
160bad_config:
161
162 mityomapl138_cpufreq_init(partnum);
163}
164
165
166
167
168
169static struct nvmem_cell_info mityomapl138_nvmem_cells[] = {
170 {
171 .name = "macaddr",
172 .offset = 0x64,
173 .bytes = ETH_ALEN,
174 }
175};
176
177static struct nvmem_cell_table mityomapl138_nvmem_cell_table = {
178 .nvmem_name = "1-00500",
179 .cells = mityomapl138_nvmem_cells,
180 .ncells = ARRAY_SIZE(mityomapl138_nvmem_cells),
181};
182
183static struct nvmem_cell_lookup mityomapl138_nvmem_cell_lookup = {
184 .nvmem_name = "1-00500",
185 .cell_name = "macaddr",
186 .dev_id = "davinci_emac.1",
187 .con_id = "mac-address",
188};
189
190static struct at24_platform_data mityomapl138_fd_chip = {
191 .byte_len = 256,
192 .page_size = 8,
193 .flags = AT24_FLAG_READONLY | AT24_FLAG_IRUGO,
194 .setup = read_factory_config,
195 .context = NULL,
196};
197
198static struct davinci_i2c_platform_data mityomap_i2c_0_pdata = {
199 .bus_freq = 100,
200 .bus_delay = 0,
201};
202
203
204
205static struct regulator_consumer_supply tps65023_dcdc1_consumers[] = {
206 {
207 .supply = "cvdd",
208 },
209};
210
211
212static struct regulator_consumer_supply tps65023_dcdc2_consumers[] = {
213 {
214 .supply = "usb0_vdda18",
215 },
216 {
217 .supply = "usb1_vdda18",
218 },
219 {
220 .supply = "ddr_dvdd18",
221 },
222 {
223 .supply = "sata_vddr",
224 },
225};
226
227
228static struct regulator_consumer_supply tps65023_dcdc3_consumers[] = {
229 {
230 .supply = "sata_vdd",
231 },
232 {
233 .supply = "usb_cvdd",
234 },
235 {
236 .supply = "pll0_vdda",
237 },
238 {
239 .supply = "pll1_vdda",
240 },
241};
242
243
244static struct regulator_consumer_supply tps65023_ldo1_consumers[] = {
245 {
246 .supply = "1.8v_aux",
247 },
248};
249
250
251static struct regulator_consumer_supply tps65023_ldo2_consumers[] = {
252 {
253 .supply = "vccaux",
254 },
255};
256
257static struct regulator_init_data tps65023_regulator_data[] = {
258
259 {
260 .constraints = {
261 .min_uV = 1150000,
262 .max_uV = 1350000,
263 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
264 REGULATOR_CHANGE_STATUS,
265 .boot_on = 1,
266 },
267 .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc1_consumers),
268 .consumer_supplies = tps65023_dcdc1_consumers,
269 },
270
271 {
272 .constraints = {
273 .min_uV = 1800000,
274 .max_uV = 1800000,
275 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
276 .boot_on = 1,
277 },
278 .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc2_consumers),
279 .consumer_supplies = tps65023_dcdc2_consumers,
280 },
281
282 {
283 .constraints = {
284 .min_uV = 1200000,
285 .max_uV = 1200000,
286 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
287 .boot_on = 1,
288 },
289 .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc3_consumers),
290 .consumer_supplies = tps65023_dcdc3_consumers,
291 },
292
293 {
294 .constraints = {
295 .min_uV = 1800000,
296 .max_uV = 1800000,
297 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
298 .boot_on = 1,
299 },
300 .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo1_consumers),
301 .consumer_supplies = tps65023_ldo1_consumers,
302 },
303
304 {
305 .constraints = {
306 .min_uV = 2500000,
307 .max_uV = 3300000,
308 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
309 REGULATOR_CHANGE_STATUS,
310 .boot_on = 1,
311 },
312 .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo2_consumers),
313 .consumer_supplies = tps65023_ldo2_consumers,
314 },
315};
316
317static struct i2c_board_info __initdata mityomap_tps65023_info[] = {
318 {
319 I2C_BOARD_INFO("tps65023", 0x48),
320 .platform_data = &tps65023_regulator_data[0],
321 },
322 {
323 I2C_BOARD_INFO("24c02", 0x50),
324 .platform_data = &mityomapl138_fd_chip,
325 },
326};
327
328static int __init pmic_tps65023_init(void)
329{
330 return i2c_register_board_info(1, mityomap_tps65023_info,
331 ARRAY_SIZE(mityomap_tps65023_info));
332}
333
334
335
336
337
338static struct mtd_partition spi_flash_partitions[] = {
339 [0] = {
340 .name = "ubl",
341 .offset = 0,
342 .size = SZ_64K,
343 .mask_flags = MTD_WRITEABLE,
344 },
345 [1] = {
346 .name = "u-boot",
347 .offset = MTDPART_OFS_APPEND,
348 .size = SZ_512K,
349 .mask_flags = MTD_WRITEABLE,
350 },
351 [2] = {
352 .name = "u-boot-env",
353 .offset = MTDPART_OFS_APPEND,
354 .size = SZ_64K,
355 .mask_flags = MTD_WRITEABLE,
356 },
357 [3] = {
358 .name = "periph-config",
359 .offset = MTDPART_OFS_APPEND,
360 .size = SZ_64K,
361 .mask_flags = MTD_WRITEABLE,
362 },
363 [4] = {
364 .name = "reserved",
365 .offset = MTDPART_OFS_APPEND,
366 .size = SZ_256K + SZ_64K,
367 },
368 [5] = {
369 .name = "kernel",
370 .offset = MTDPART_OFS_APPEND,
371 .size = SZ_2M + SZ_1M,
372 },
373 [6] = {
374 .name = "fpga",
375 .offset = MTDPART_OFS_APPEND,
376 .size = SZ_2M,
377 },
378 [7] = {
379 .name = "spare",
380 .offset = MTDPART_OFS_APPEND,
381 .size = MTDPART_SIZ_FULL,
382 },
383};
384
385static struct flash_platform_data mityomapl138_spi_flash_data = {
386 .name = "m25p80",
387 .parts = spi_flash_partitions,
388 .nr_parts = ARRAY_SIZE(spi_flash_partitions),
389 .type = "m24p64",
390};
391
392static struct davinci_spi_config spi_eprom_config = {
393 .io_type = SPI_IO_TYPE_DMA,
394 .c2tdelay = 8,
395 .t2cdelay = 8,
396};
397
398static struct spi_board_info mityomapl138_spi_flash_info[] = {
399 {
400 .modalias = "m25p80",
401 .platform_data = &mityomapl138_spi_flash_data,
402 .controller_data = &spi_eprom_config,
403 .mode = SPI_MODE_0,
404 .max_speed_hz = 30000000,
405 .bus_num = 1,
406 .chip_select = 0,
407 },
408};
409
410
411
412
413
414static struct mtd_partition mityomapl138_nandflash_partition[] = {
415 {
416 .name = "rootfs",
417 .offset = 0,
418 .size = SZ_128M,
419 .mask_flags = 0,
420 },
421 {
422 .name = "homefs",
423 .offset = MTDPART_OFS_APPEND,
424 .size = MTDPART_SIZ_FULL,
425 .mask_flags = 0,
426 },
427};
428
429static struct davinci_nand_pdata mityomapl138_nandflash_data = {
430 .core_chipsel = 1,
431 .parts = mityomapl138_nandflash_partition,
432 .nr_parts = ARRAY_SIZE(mityomapl138_nandflash_partition),
433 .ecc_mode = NAND_ECC_HW,
434 .bbt_options = NAND_BBT_USE_FLASH,
435 .options = NAND_BUSWIDTH_16,
436 .ecc_bits = 1,
437};
438
439static struct resource mityomapl138_nandflash_resource[] = {
440 {
441 .start = DA8XX_AEMIF_CS3_BASE,
442 .end = DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1,
443 .flags = IORESOURCE_MEM,
444 },
445 {
446 .start = DA8XX_AEMIF_CTL_BASE,
447 .end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
448 .flags = IORESOURCE_MEM,
449 },
450};
451
452static struct platform_device mityomapl138_aemif_devices[] = {
453 {
454 .name = "davinci_nand",
455 .id = 1,
456 .dev = {
457 .platform_data = &mityomapl138_nandflash_data,
458 },
459 .num_resources = ARRAY_SIZE(mityomapl138_nandflash_resource),
460 .resource = mityomapl138_nandflash_resource,
461 },
462};
463
464static struct resource mityomapl138_aemif_resources[] = {
465 {
466 .start = DA8XX_AEMIF_CTL_BASE,
467 .end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
468 .flags = IORESOURCE_MEM,
469 },
470};
471
472static struct aemif_abus_data mityomapl138_aemif_abus_data[] = {
473 {
474 .cs = 1,
475 },
476};
477
478static struct aemif_platform_data mityomapl138_aemif_pdata = {
479 .abus_data = mityomapl138_aemif_abus_data,
480 .num_abus_data = ARRAY_SIZE(mityomapl138_aemif_abus_data),
481 .sub_devices = mityomapl138_aemif_devices,
482 .num_sub_devices = ARRAY_SIZE(mityomapl138_aemif_devices),
483};
484
485static struct platform_device mityomapl138_aemif_device = {
486 .name = "ti-aemif",
487 .id = -1,
488 .dev = {
489 .platform_data = &mityomapl138_aemif_pdata,
490 },
491 .resource = mityomapl138_aemif_resources,
492 .num_resources = ARRAY_SIZE(mityomapl138_aemif_resources),
493};
494
495static void __init mityomapl138_setup_nand(void)
496{
497 if (platform_device_register(&mityomapl138_aemif_device))
498 pr_warn("%s: Cannot register AEMIF device\n", __func__);
499}
500
501static const short mityomap_mii_pins[] = {
502 DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
503 DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
504 DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
505 DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
506 DA850_MDIO_D,
507 -1
508};
509
510static const short mityomap_rmii_pins[] = {
511 DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN,
512 DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1,
513 DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK,
514 DA850_MDIO_D,
515 -1
516};
517
518static void __init mityomapl138_config_emac(void)
519{
520 void __iomem *cfg_chip3_base;
521 int ret;
522 u32 val;
523 struct davinci_soc_info *soc_info = &davinci_soc_info;
524
525 soc_info->emac_pdata->rmii_en = 0;
526
527 cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG);
528 val = __raw_readl(cfg_chip3_base);
529
530 if (soc_info->emac_pdata->rmii_en) {
531 val |= BIT(8);
532 ret = davinci_cfg_reg_list(mityomap_rmii_pins);
533 pr_info("RMII PHY configured\n");
534 } else {
535 val &= ~BIT(8);
536 ret = davinci_cfg_reg_list(mityomap_mii_pins);
537 pr_info("MII PHY configured\n");
538 }
539
540 if (ret) {
541 pr_warn("mii/rmii mux setup failed: %d\n", ret);
542 return;
543 }
544
545
546 __raw_writel(val, cfg_chip3_base);
547
548 soc_info->emac_pdata->phy_id = MITYOMAPL138_PHY_ID;
549
550 ret = da8xx_register_emac();
551 if (ret)
552 pr_warn("emac registration failed: %d\n", ret);
553}
554
555static void __init mityomapl138_init(void)
556{
557 int ret;
558
559 da850_register_clocks();
560
561
562 ret = da850_register_edma(NULL);
563 if (ret)
564 pr_warn("edma registration failed: %d\n", ret);
565
566 ret = da8xx_register_watchdog();
567 if (ret)
568 pr_warn("watchdog registration failed: %d\n", ret);
569
570 davinci_serial_init(da8xx_serial_device);
571
572 nvmem_add_cell_table(&mityomapl138_nvmem_cell_table);
573 nvmem_add_cell_lookups(&mityomapl138_nvmem_cell_lookup, 1);
574
575 ret = da8xx_register_i2c(0, &mityomap_i2c_0_pdata);
576 if (ret)
577 pr_warn("i2c0 registration failed: %d\n", ret);
578
579 ret = pmic_tps65023_init();
580 if (ret)
581 pr_warn("TPS65023 PMIC init failed: %d\n", ret);
582
583 mityomapl138_setup_nand();
584
585 ret = spi_register_board_info(mityomapl138_spi_flash_info,
586 ARRAY_SIZE(mityomapl138_spi_flash_info));
587 if (ret)
588 pr_warn("spi info registration failed: %d\n", ret);
589
590 ret = da8xx_register_spi_bus(1,
591 ARRAY_SIZE(mityomapl138_spi_flash_info));
592 if (ret)
593 pr_warn("spi 1 registration failed: %d\n", ret);
594
595 mityomapl138_config_emac();
596
597 ret = da8xx_register_rtc();
598 if (ret)
599 pr_warn("rtc setup failed: %d\n", ret);
600
601 ret = da8xx_register_cpuidle();
602 if (ret)
603 pr_warn("cpuidle registration failed: %d\n", ret);
604
605 davinci_pm_init();
606}
607
608#ifdef CONFIG_SERIAL_8250_CONSOLE
609static int __init mityomapl138_console_init(void)
610{
611 if (!machine_is_mityomapl138())
612 return 0;
613
614 return add_preferred_console("ttyS", 1, "115200");
615}
616console_initcall(mityomapl138_console_init);
617#endif
618
619static void __init mityomapl138_map_io(void)
620{
621 da850_init();
622}
623
624MACHINE_START(MITYOMAPL138, "MityDSP-L138/MityARM-1808")
625 .atag_offset = 0x100,
626 .map_io = mityomapl138_map_io,
627 .init_irq = cp_intc_init,
628 .init_time = da850_init_time,
629 .init_machine = mityomapl138_init,
630 .init_late = davinci_init_late,
631 .dma_zone_size = SZ_128M,
632MACHINE_END
633
