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11
12#undef DEBUG
13
14#include <linux/kernel.h>
15#include <linux/pci.h>
16#include <linux/crash_dump.h>
17#include <linux/delay.h>
18#include <linux/string.h>
19#include <linux/init.h>
20#include <linux/memblock.h>
21#include <linux/irq.h>
22#include <linux/io.h>
23#include <linux/msi.h>
24#include <linux/iommu.h>
25#include <linux/rculist.h>
26#include <linux/sizes.h>
27
28#include <asm/sections.h>
29#include <asm/io.h>
30#include <asm/prom.h>
31#include <asm/pci-bridge.h>
32#include <asm/machdep.h>
33#include <asm/msi_bitmap.h>
34#include <asm/ppc-pci.h>
35#include <asm/opal.h>
36#include <asm/iommu.h>
37#include <asm/tce.h>
38#include <asm/xics.h>
39#include <asm/debugfs.h>
40#include <asm/firmware.h>
41#include <asm/pnv-pci.h>
42#include <asm/mmzone.h>
43
44#include <misc/cxl-base.h>
45
46#include "powernv.h"
47#include "pci.h"
48#include "../../../../drivers/pci/pci.h"
49
50#define PNV_IODA1_M64_NUM 16
51#define PNV_IODA1_M64_SEGS 8
52#define PNV_IODA1_DMA32_SEGSIZE 0x10000000
53
54static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU_NVLINK",
55 "NPU_OCAPI" };
56
57void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
58 const char *fmt, ...)
59{
60 struct va_format vaf;
61 va_list args;
62 char pfix[32];
63
64 va_start(args, fmt);
65
66 vaf.fmt = fmt;
67 vaf.va = &args;
68
69 if (pe->flags & PNV_IODA_PE_DEV)
70 strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix));
71 else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
72 sprintf(pfix, "%04x:%02x ",
73 pci_domain_nr(pe->pbus), pe->pbus->number);
74#ifdef CONFIG_PCI_IOV
75 else if (pe->flags & PNV_IODA_PE_VF)
76 sprintf(pfix, "%04x:%02x:%2x.%d",
77 pci_domain_nr(pe->parent_dev->bus),
78 (pe->rid & 0xff00) >> 8,
79 PCI_SLOT(pe->rid), PCI_FUNC(pe->rid));
80#endif
81
82 printk("%spci %s: [PE# %.2x] %pV",
83 level, pfix, pe->pe_number, &vaf);
84
85 va_end(args);
86}
87
88static bool pnv_iommu_bypass_disabled __read_mostly;
89static bool pci_reset_phbs __read_mostly;
90
91static int __init iommu_setup(char *str)
92{
93 if (!str)
94 return -EINVAL;
95
96 while (*str) {
97 if (!strncmp(str, "nobypass", 8)) {
98 pnv_iommu_bypass_disabled = true;
99 pr_info("PowerNV: IOMMU bypass window disabled.\n");
100 break;
101 }
102 str += strcspn(str, ",");
103 if (*str == ',')
104 str++;
105 }
106
107 return 0;
108}
109early_param("iommu", iommu_setup);
110
111static int __init pci_reset_phbs_setup(char *str)
112{
113 pci_reset_phbs = true;
114 return 0;
115}
116
117early_param("ppc_pci_reset_phbs", pci_reset_phbs_setup);
118
119static inline bool pnv_pci_is_m64(struct pnv_phb *phb, struct resource *r)
120{
121
122
123
124
125
126
127
128 return (r->start >= phb->ioda.m64_base &&
129 r->start < (phb->ioda.m64_base + phb->ioda.m64_size));
130}
131
132static inline bool pnv_pci_is_m64_flags(unsigned long resource_flags)
133{
134 unsigned long flags = (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
135
136 return (resource_flags & flags) == flags;
137}
138
139static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no)
140{
141 s64 rc;
142
143 phb->ioda.pe_array[pe_no].phb = phb;
144 phb->ioda.pe_array[pe_no].pe_number = pe_no;
145
146
147
148
149
150
151 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
152 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
153 if (rc != OPAL_SUCCESS && rc != OPAL_UNSUPPORTED)
154 pr_warn("%s: Error %lld unfreezing PHB#%x-PE#%x\n",
155 __func__, rc, phb->hose->global_number, pe_no);
156
157 return &phb->ioda.pe_array[pe_no];
158}
159
160static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no)
161{
162 if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) {
163 pr_warn("%s: Invalid PE %x on PHB#%x\n",
164 __func__, pe_no, phb->hose->global_number);
165 return;
166 }
167
168 if (test_and_set_bit(pe_no, phb->ioda.pe_alloc))
169 pr_debug("%s: PE %x was reserved on PHB#%x\n",
170 __func__, pe_no, phb->hose->global_number);
171
172 pnv_ioda_init_pe(phb, pe_no);
173}
174
175static struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb)
176{
177 long pe;
178
179 for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) {
180 if (!test_and_set_bit(pe, phb->ioda.pe_alloc))
181 return pnv_ioda_init_pe(phb, pe);
182 }
183
184 return NULL;
185}
186
187static void pnv_ioda_free_pe(struct pnv_ioda_pe *pe)
188{
189 struct pnv_phb *phb = pe->phb;
190 unsigned int pe_num = pe->pe_number;
191
192 WARN_ON(pe->pdev);
193 WARN_ON(pe->npucomp);
194 kfree(pe->npucomp);
195 memset(pe, 0, sizeof(struct pnv_ioda_pe));
196 clear_bit(pe_num, phb->ioda.pe_alloc);
197}
198
199
200static int pnv_ioda2_init_m64(struct pnv_phb *phb)
201{
202 const char *desc;
203 struct resource *r;
204 s64 rc;
205
206
207 rc = opal_pci_set_phb_mem_window(phb->opal_id,
208 OPAL_M64_WINDOW_TYPE,
209 phb->ioda.m64_bar_idx,
210 phb->ioda.m64_base,
211 0,
212 phb->ioda.m64_size);
213 if (rc != OPAL_SUCCESS) {
214 desc = "configuring";
215 goto fail;
216 }
217
218
219 rc = opal_pci_phb_mmio_enable(phb->opal_id,
220 OPAL_M64_WINDOW_TYPE,
221 phb->ioda.m64_bar_idx,
222 OPAL_ENABLE_M64_SPLIT);
223 if (rc != OPAL_SUCCESS) {
224 desc = "enabling";
225 goto fail;
226 }
227
228
229
230
231
232 r = &phb->hose->mem_resources[1];
233 if (phb->ioda.reserved_pe_idx == 0)
234 r->start += (2 * phb->ioda.m64_segsize);
235 else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
236 r->end -= (2 * phb->ioda.m64_segsize);
237 else
238 pr_warn(" Cannot strip M64 segment for reserved PE#%x\n",
239 phb->ioda.reserved_pe_idx);
240
241 return 0;
242
243fail:
244 pr_warn(" Failure %lld %s M64 BAR#%d\n",
245 rc, desc, phb->ioda.m64_bar_idx);
246 opal_pci_phb_mmio_enable(phb->opal_id,
247 OPAL_M64_WINDOW_TYPE,
248 phb->ioda.m64_bar_idx,
249 OPAL_DISABLE_M64);
250 return -EIO;
251}
252
253static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev,
254 unsigned long *pe_bitmap)
255{
256 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
257 struct pnv_phb *phb = hose->private_data;
258 struct resource *r;
259 resource_size_t base, sgsz, start, end;
260 int segno, i;
261
262 base = phb->ioda.m64_base;
263 sgsz = phb->ioda.m64_segsize;
264 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
265 r = &pdev->resource[i];
266 if (!r->parent || !pnv_pci_is_m64(phb, r))
267 continue;
268
269 start = _ALIGN_DOWN(r->start - base, sgsz);
270 end = _ALIGN_UP(r->end - base, sgsz);
271 for (segno = start / sgsz; segno < end / sgsz; segno++) {
272 if (pe_bitmap)
273 set_bit(segno, pe_bitmap);
274 else
275 pnv_ioda_reserve_pe(phb, segno);
276 }
277 }
278}
279
280static int pnv_ioda1_init_m64(struct pnv_phb *phb)
281{
282 struct resource *r;
283 int index;
284
285
286
287
288
289
290 for (index = 0; index < PNV_IODA1_M64_NUM; index++) {
291 unsigned long base, segsz = phb->ioda.m64_segsize;
292 int64_t rc;
293
294 base = phb->ioda.m64_base +
295 index * PNV_IODA1_M64_SEGS * segsz;
296 rc = opal_pci_set_phb_mem_window(phb->opal_id,
297 OPAL_M64_WINDOW_TYPE, index, base, 0,
298 PNV_IODA1_M64_SEGS * segsz);
299 if (rc != OPAL_SUCCESS) {
300 pr_warn(" Error %lld setting M64 PHB#%x-BAR#%d\n",
301 rc, phb->hose->global_number, index);
302 goto fail;
303 }
304
305 rc = opal_pci_phb_mmio_enable(phb->opal_id,
306 OPAL_M64_WINDOW_TYPE, index,
307 OPAL_ENABLE_M64_SPLIT);
308 if (rc != OPAL_SUCCESS) {
309 pr_warn(" Error %lld enabling M64 PHB#%x-BAR#%d\n",
310 rc, phb->hose->global_number, index);
311 goto fail;
312 }
313 }
314
315
316
317
318
319 r = &phb->hose->mem_resources[1];
320 if (phb->ioda.reserved_pe_idx == 0)
321 r->start += (2 * phb->ioda.m64_segsize);
322 else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
323 r->end -= (2 * phb->ioda.m64_segsize);
324 else
325 WARN(1, "Wrong reserved PE#%x on PHB#%x\n",
326 phb->ioda.reserved_pe_idx, phb->hose->global_number);
327
328 return 0;
329
330fail:
331 for ( ; index >= 0; index--)
332 opal_pci_phb_mmio_enable(phb->opal_id,
333 OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64);
334
335 return -EIO;
336}
337
338static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus,
339 unsigned long *pe_bitmap,
340 bool all)
341{
342 struct pci_dev *pdev;
343
344 list_for_each_entry(pdev, &bus->devices, bus_list) {
345 pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap);
346
347 if (all && pdev->subordinate)
348 pnv_ioda_reserve_m64_pe(pdev->subordinate,
349 pe_bitmap, all);
350 }
351}
352
353static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all)
354{
355 struct pci_controller *hose = pci_bus_to_host(bus);
356 struct pnv_phb *phb = hose->private_data;
357 struct pnv_ioda_pe *master_pe, *pe;
358 unsigned long size, *pe_alloc;
359 int i;
360
361
362 if (pci_is_root_bus(bus))
363 return NULL;
364
365
366 size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long));
367 pe_alloc = kzalloc(size, GFP_KERNEL);
368 if (!pe_alloc) {
369 pr_warn("%s: Out of memory !\n",
370 __func__);
371 return NULL;
372 }
373
374
375 pnv_ioda_reserve_m64_pe(bus, pe_alloc, all);
376
377
378
379
380
381
382 if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) {
383 kfree(pe_alloc);
384 return NULL;
385 }
386
387
388
389
390
391 master_pe = NULL;
392 i = -1;
393 while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) <
394 phb->ioda.total_pe_num) {
395 pe = &phb->ioda.pe_array[i];
396
397 phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number;
398 if (!master_pe) {
399 pe->flags |= PNV_IODA_PE_MASTER;
400 INIT_LIST_HEAD(&pe->slaves);
401 master_pe = pe;
402 } else {
403 pe->flags |= PNV_IODA_PE_SLAVE;
404 pe->master = master_pe;
405 list_add_tail(&pe->list, &master_pe->slaves);
406 }
407
408
409
410
411
412
413
414
415 if (phb->type == PNV_PHB_IODA1) {
416 int64_t rc;
417
418 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
419 pe->pe_number, OPAL_M64_WINDOW_TYPE,
420 pe->pe_number / PNV_IODA1_M64_SEGS,
421 pe->pe_number % PNV_IODA1_M64_SEGS);
422 if (rc != OPAL_SUCCESS)
423 pr_warn("%s: Error %lld mapping M64 for PHB#%x-PE#%x\n",
424 __func__, rc, phb->hose->global_number,
425 pe->pe_number);
426 }
427 }
428
429 kfree(pe_alloc);
430 return master_pe;
431}
432
433static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb)
434{
435 struct pci_controller *hose = phb->hose;
436 struct device_node *dn = hose->dn;
437 struct resource *res;
438 u32 m64_range[2], i;
439 const __be32 *r;
440 u64 pci_addr;
441
442 if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) {
443 pr_info(" Not support M64 window\n");
444 return;
445 }
446
447 if (!firmware_has_feature(FW_FEATURE_OPAL)) {
448 pr_info(" Firmware too old to support M64 window\n");
449 return;
450 }
451
452 r = of_get_property(dn, "ibm,opal-m64-window", NULL);
453 if (!r) {
454 pr_info(" No <ibm,opal-m64-window> on %pOF\n",
455 dn);
456 return;
457 }
458
459
460
461
462
463 if (of_property_read_u32_array(dn, "ibm,opal-available-m64-ranges",
464 m64_range, 2)) {
465
466 m64_range[0] = 0;
467 m64_range[1] = 16;
468 }
469
470 if (m64_range[1] > 63) {
471 pr_warn("%s: Limiting M64 range to 63 (from %d) on PHB#%x\n",
472 __func__, m64_range[1], phb->hose->global_number);
473 m64_range[1] = 63;
474 }
475
476 if (m64_range[1] <= m64_range[0]) {
477 pr_warn("%s: M64 empty, disabling M64 usage on PHB#%x\n",
478 __func__, phb->hose->global_number);
479 return;
480 }
481
482
483 res = &hose->mem_resources[1];
484 res->name = dn->full_name;
485 res->start = of_translate_address(dn, r + 2);
486 res->end = res->start + of_read_number(r + 4, 2) - 1;
487 res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
488 pci_addr = of_read_number(r, 2);
489 hose->mem_offset[1] = res->start - pci_addr;
490
491 phb->ioda.m64_size = resource_size(res);
492 phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num;
493 phb->ioda.m64_base = pci_addr;
494
495
496 pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n",
497 res->start, res->end, pci_addr, m64_range[0],
498 m64_range[0] + m64_range[1] - 1);
499
500
501 phb->ioda.m64_bar_alloc = (unsigned long)-1;
502
503
504 m64_range[1]--;
505 phb->ioda.m64_bar_idx = m64_range[0] + m64_range[1];
506
507 pr_info(" Using M64 #%d as default window\n", phb->ioda.m64_bar_idx);
508
509
510 for (i = m64_range[0]; i < m64_range[1]; i++)
511 clear_bit(i, &phb->ioda.m64_bar_alloc);
512
513
514
515
516
517 if (phb->type == PNV_PHB_IODA1)
518 phb->init_m64 = pnv_ioda1_init_m64;
519 else
520 phb->init_m64 = pnv_ioda2_init_m64;
521}
522
523static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no)
524{
525 struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no];
526 struct pnv_ioda_pe *slave;
527 s64 rc;
528
529
530 if (pe->flags & PNV_IODA_PE_SLAVE) {
531 pe = pe->master;
532 if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)))
533 return;
534
535 pe_no = pe->pe_number;
536 }
537
538
539 rc = opal_pci_eeh_freeze_set(phb->opal_id,
540 pe_no,
541 OPAL_EEH_ACTION_SET_FREEZE_ALL);
542 if (rc != OPAL_SUCCESS) {
543 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
544 __func__, rc, phb->hose->global_number, pe_no);
545 return;
546 }
547
548
549 if (!(pe->flags & PNV_IODA_PE_MASTER))
550 return;
551
552 list_for_each_entry(slave, &pe->slaves, list) {
553 rc = opal_pci_eeh_freeze_set(phb->opal_id,
554 slave->pe_number,
555 OPAL_EEH_ACTION_SET_FREEZE_ALL);
556 if (rc != OPAL_SUCCESS)
557 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
558 __func__, rc, phb->hose->global_number,
559 slave->pe_number);
560 }
561}
562
563static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt)
564{
565 struct pnv_ioda_pe *pe, *slave;
566 s64 rc;
567
568
569 pe = &phb->ioda.pe_array[pe_no];
570 if (pe->flags & PNV_IODA_PE_SLAVE) {
571 pe = pe->master;
572 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
573 pe_no = pe->pe_number;
574 }
575
576
577 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt);
578 if (rc != OPAL_SUCCESS) {
579 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
580 __func__, rc, opt, phb->hose->global_number, pe_no);
581 return -EIO;
582 }
583
584 if (!(pe->flags & PNV_IODA_PE_MASTER))
585 return 0;
586
587
588 list_for_each_entry(slave, &pe->slaves, list) {
589 rc = opal_pci_eeh_freeze_clear(phb->opal_id,
590 slave->pe_number,
591 opt);
592 if (rc != OPAL_SUCCESS) {
593 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
594 __func__, rc, opt, phb->hose->global_number,
595 slave->pe_number);
596 return -EIO;
597 }
598 }
599
600 return 0;
601}
602
603static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no)
604{
605 struct pnv_ioda_pe *slave, *pe;
606 u8 fstate = 0, state;
607 __be16 pcierr = 0;
608 s64 rc;
609
610
611 if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num)
612 return OPAL_EEH_STOPPED_PERM_UNAVAIL;
613
614
615
616
617
618 pe = &phb->ioda.pe_array[pe_no];
619 if (pe->flags & PNV_IODA_PE_SLAVE) {
620 pe = pe->master;
621 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
622 pe_no = pe->pe_number;
623 }
624
625
626 rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
627 &state, &pcierr, NULL);
628 if (rc != OPAL_SUCCESS) {
629 pr_warn("%s: Failure %lld getting "
630 "PHB#%x-PE#%x state\n",
631 __func__, rc,
632 phb->hose->global_number, pe_no);
633 return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
634 }
635
636
637 if (!(pe->flags & PNV_IODA_PE_MASTER))
638 return state;
639
640 list_for_each_entry(slave, &pe->slaves, list) {
641 rc = opal_pci_eeh_freeze_status(phb->opal_id,
642 slave->pe_number,
643 &fstate,
644 &pcierr,
645 NULL);
646 if (rc != OPAL_SUCCESS) {
647 pr_warn("%s: Failure %lld getting "
648 "PHB#%x-PE#%x state\n",
649 __func__, rc,
650 phb->hose->global_number, slave->pe_number);
651 return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
652 }
653
654
655
656
657
658 if (fstate > state)
659 state = fstate;
660 }
661
662 return state;
663}
664
665struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev)
666{
667 struct pci_controller *hose = pci_bus_to_host(dev->bus);
668 struct pnv_phb *phb = hose->private_data;
669 struct pci_dn *pdn = pci_get_pdn(dev);
670
671 if (!pdn)
672 return NULL;
673 if (pdn->pe_number == IODA_INVALID_PE)
674 return NULL;
675 return &phb->ioda.pe_array[pdn->pe_number];
676}
677
678static int pnv_ioda_set_one_peltv(struct pnv_phb *phb,
679 struct pnv_ioda_pe *parent,
680 struct pnv_ioda_pe *child,
681 bool is_add)
682{
683 const char *desc = is_add ? "adding" : "removing";
684 uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN :
685 OPAL_REMOVE_PE_FROM_DOMAIN;
686 struct pnv_ioda_pe *slave;
687 long rc;
688
689
690 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
691 child->pe_number, op);
692 if (rc != OPAL_SUCCESS) {
693 pe_warn(child, "OPAL error %ld %s to parent PELTV\n",
694 rc, desc);
695 return -ENXIO;
696 }
697
698 if (!(child->flags & PNV_IODA_PE_MASTER))
699 return 0;
700
701
702 list_for_each_entry(slave, &child->slaves, list) {
703 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
704 slave->pe_number, op);
705 if (rc != OPAL_SUCCESS) {
706 pe_warn(slave, "OPAL error %ld %s to parent PELTV\n",
707 rc, desc);
708 return -ENXIO;
709 }
710 }
711
712 return 0;
713}
714
715static int pnv_ioda_set_peltv(struct pnv_phb *phb,
716 struct pnv_ioda_pe *pe,
717 bool is_add)
718{
719 struct pnv_ioda_pe *slave;
720 struct pci_dev *pdev = NULL;
721 int ret;
722
723
724
725
726
727 if (is_add) {
728 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
729 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
730 if (pe->flags & PNV_IODA_PE_MASTER) {
731 list_for_each_entry(slave, &pe->slaves, list)
732 opal_pci_eeh_freeze_clear(phb->opal_id,
733 slave->pe_number,
734 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
735 }
736 }
737
738
739
740
741
742
743
744 ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add);
745 if (ret)
746 return ret;
747
748
749 if (pe->flags & PNV_IODA_PE_MASTER) {
750 list_for_each_entry(slave, &pe->slaves, list) {
751 ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add);
752 if (ret)
753 return ret;
754 }
755 }
756
757 if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS))
758 pdev = pe->pbus->self;
759 else if (pe->flags & PNV_IODA_PE_DEV)
760 pdev = pe->pdev->bus->self;
761#ifdef CONFIG_PCI_IOV
762 else if (pe->flags & PNV_IODA_PE_VF)
763 pdev = pe->parent_dev;
764#endif
765 while (pdev) {
766 struct pci_dn *pdn = pci_get_pdn(pdev);
767 struct pnv_ioda_pe *parent;
768
769 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
770 parent = &phb->ioda.pe_array[pdn->pe_number];
771 ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add);
772 if (ret)
773 return ret;
774 }
775
776 pdev = pdev->bus->self;
777 }
778
779 return 0;
780}
781
782static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
783{
784 struct pci_dev *parent;
785 uint8_t bcomp, dcomp, fcomp;
786 int64_t rc;
787 long rid_end, rid;
788
789
790 if (pe->pbus) {
791 int count;
792
793 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
794 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
795 parent = pe->pbus->self;
796 if (pe->flags & PNV_IODA_PE_BUS_ALL)
797 count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
798 else
799 count = 1;
800
801 switch(count) {
802 case 1: bcomp = OpalPciBusAll; break;
803 case 2: bcomp = OpalPciBus7Bits; break;
804 case 4: bcomp = OpalPciBus6Bits; break;
805 case 8: bcomp = OpalPciBus5Bits; break;
806 case 16: bcomp = OpalPciBus4Bits; break;
807 case 32: bcomp = OpalPciBus3Bits; break;
808 default:
809 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
810 count);
811
812 bcomp = OpalPciBusAll;
813 }
814 rid_end = pe->rid + (count << 8);
815 } else {
816#ifdef CONFIG_PCI_IOV
817 if (pe->flags & PNV_IODA_PE_VF)
818 parent = pe->parent_dev;
819 else
820#endif
821 parent = pe->pdev->bus->self;
822 bcomp = OpalPciBusAll;
823 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
824 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
825 rid_end = pe->rid + 1;
826 }
827
828
829 for (rid = pe->rid; rid < rid_end; rid++)
830 phb->ioda.pe_rmap[rid] = IODA_INVALID_PE;
831
832
833 while (parent) {
834 struct pci_dn *pdn = pci_get_pdn(parent);
835 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
836 rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number,
837 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
838
839 }
840 parent = parent->bus->self;
841 }
842
843 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
844 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
845
846
847 rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number,
848 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
849 if (rc)
850 pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc);
851 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
852 bcomp, dcomp, fcomp, OPAL_UNMAP_PE);
853 if (rc)
854 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
855
856 pe->pbus = NULL;
857 pe->pdev = NULL;
858#ifdef CONFIG_PCI_IOV
859 pe->parent_dev = NULL;
860#endif
861
862 return 0;
863}
864
865static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
866{
867 struct pci_dev *parent;
868 uint8_t bcomp, dcomp, fcomp;
869 long rc, rid_end, rid;
870
871
872 if (pe->pbus) {
873 int count;
874
875 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
876 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
877 parent = pe->pbus->self;
878 if (pe->flags & PNV_IODA_PE_BUS_ALL)
879 count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
880 else
881 count = 1;
882
883 switch(count) {
884 case 1: bcomp = OpalPciBusAll; break;
885 case 2: bcomp = OpalPciBus7Bits; break;
886 case 4: bcomp = OpalPciBus6Bits; break;
887 case 8: bcomp = OpalPciBus5Bits; break;
888 case 16: bcomp = OpalPciBus4Bits; break;
889 case 32: bcomp = OpalPciBus3Bits; break;
890 default:
891 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
892 count);
893
894 bcomp = OpalPciBusAll;
895 }
896 rid_end = pe->rid + (count << 8);
897 } else {
898#ifdef CONFIG_PCI_IOV
899 if (pe->flags & PNV_IODA_PE_VF)
900 parent = pe->parent_dev;
901 else
902#endif
903 parent = pe->pdev->bus->self;
904 bcomp = OpalPciBusAll;
905 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
906 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
907 rid_end = pe->rid + 1;
908 }
909
910
911
912
913
914
915
916 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
917 bcomp, dcomp, fcomp, OPAL_MAP_PE);
918 if (rc) {
919 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
920 return -ENXIO;
921 }
922
923
924
925
926
927 if (phb->type != PNV_PHB_NPU_NVLINK && phb->type != PNV_PHB_NPU_OCAPI)
928 pnv_ioda_set_peltv(phb, pe, true);
929
930
931 for (rid = pe->rid; rid < rid_end; rid++)
932 phb->ioda.pe_rmap[rid] = pe->pe_number;
933
934
935 if (phb->type != PNV_PHB_IODA1) {
936 pe->mve_number = 0;
937 goto out;
938 }
939
940 pe->mve_number = pe->pe_number;
941 rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number);
942 if (rc != OPAL_SUCCESS) {
943 pe_err(pe, "OPAL error %ld setting up MVE %x\n",
944 rc, pe->mve_number);
945 pe->mve_number = -1;
946 } else {
947 rc = opal_pci_set_mve_enable(phb->opal_id,
948 pe->mve_number, OPAL_ENABLE_MVE);
949 if (rc) {
950 pe_err(pe, "OPAL error %ld enabling MVE %x\n",
951 rc, pe->mve_number);
952 pe->mve_number = -1;
953 }
954 }
955
956out:
957 return 0;
958}
959
960#ifdef CONFIG_PCI_IOV
961static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset)
962{
963 struct pci_dn *pdn = pci_get_pdn(dev);
964 int i;
965 struct resource *res, res2;
966 resource_size_t size;
967 u16 num_vfs;
968
969 if (!dev->is_physfn)
970 return -EINVAL;
971
972
973
974
975
976
977
978
979
980 num_vfs = pdn->num_vfs;
981 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
982 res = &dev->resource[i + PCI_IOV_RESOURCES];
983 if (!res->flags || !res->parent)
984 continue;
985
986
987
988
989
990
991
992 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
993 res2.flags = res->flags;
994 res2.start = res->start + (size * offset);
995 res2.end = res2.start + (size * num_vfs) - 1;
996
997 if (res2.end > res->end) {
998 dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n",
999 i, &res2, res, num_vfs, offset);
1000 return -EBUSY;
1001 }
1002 }
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1013 res = &dev->resource[i + PCI_IOV_RESOURCES];
1014 if (!res->flags || !res->parent)
1015 continue;
1016
1017 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
1018 res2 = *res;
1019 res->start += size * offset;
1020
1021 dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n",
1022 i, &res2, res, (offset > 0) ? "En" : "Dis",
1023 num_vfs, offset);
1024
1025 if (offset < 0) {
1026 devm_release_resource(&dev->dev, &pdn->holes[i]);
1027 memset(&pdn->holes[i], 0, sizeof(pdn->holes[i]));
1028 }
1029
1030 pci_update_resource(dev, i + PCI_IOV_RESOURCES);
1031
1032 if (offset > 0) {
1033 pdn->holes[i].start = res2.start;
1034 pdn->holes[i].end = res2.start + size * offset - 1;
1035 pdn->holes[i].flags = IORESOURCE_BUS;
1036 pdn->holes[i].name = "pnv_iov_reserved";
1037 devm_request_resource(&dev->dev, res->parent,
1038 &pdn->holes[i]);
1039 }
1040 }
1041 return 0;
1042}
1043#endif
1044
1045static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev)
1046{
1047 struct pci_controller *hose = pci_bus_to_host(dev->bus);
1048 struct pnv_phb *phb = hose->private_data;
1049 struct pci_dn *pdn = pci_get_pdn(dev);
1050 struct pnv_ioda_pe *pe;
1051
1052 if (!pdn) {
1053 pr_err("%s: Device tree node not associated properly\n",
1054 pci_name(dev));
1055 return NULL;
1056 }
1057 if (pdn->pe_number != IODA_INVALID_PE)
1058 return NULL;
1059
1060 pe = pnv_ioda_alloc_pe(phb);
1061 if (!pe) {
1062 pr_warn("%s: Not enough PE# available, disabling device\n",
1063 pci_name(dev));
1064 return NULL;
1065 }
1066
1067
1068
1069
1070
1071
1072
1073
1074 pci_dev_get(dev);
1075 pdn->pe_number = pe->pe_number;
1076 pe->flags = PNV_IODA_PE_DEV;
1077 pe->pdev = dev;
1078 pe->pbus = NULL;
1079 pe->mve_number = -1;
1080 pe->rid = dev->bus->number << 8 | pdn->devfn;
1081
1082 pe_info(pe, "Associated device to PE\n");
1083
1084 if (pnv_ioda_configure_pe(phb, pe)) {
1085
1086 pnv_ioda_free_pe(pe);
1087 pdn->pe_number = IODA_INVALID_PE;
1088 pe->pdev = NULL;
1089 pci_dev_put(dev);
1090 return NULL;
1091 }
1092
1093
1094 list_add_tail(&pe->list, &phb->ioda.pe_list);
1095
1096 return pe;
1097}
1098
1099static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe)
1100{
1101 struct pci_dev *dev;
1102
1103 list_for_each_entry(dev, &bus->devices, bus_list) {
1104 struct pci_dn *pdn = pci_get_pdn(dev);
1105
1106 if (pdn == NULL) {
1107 pr_warn("%s: No device node associated with device !\n",
1108 pci_name(dev));
1109 continue;
1110 }
1111
1112
1113
1114
1115
1116
1117 if (pdn->pe_number != IODA_INVALID_PE)
1118 continue;
1119
1120 pe->device_count++;
1121 pdn->pe_number = pe->pe_number;
1122 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1123 pnv_ioda_setup_same_PE(dev->subordinate, pe);
1124 }
1125}
1126
1127
1128
1129
1130
1131
1132
1133static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all)
1134{
1135 struct pci_controller *hose = pci_bus_to_host(bus);
1136 struct pnv_phb *phb = hose->private_data;
1137 struct pnv_ioda_pe *pe = NULL;
1138 unsigned int pe_num;
1139
1140
1141
1142
1143
1144 pe_num = phb->ioda.pe_rmap[bus->number << 8];
1145 if (pe_num != IODA_INVALID_PE) {
1146 pe = &phb->ioda.pe_array[pe_num];
1147 pnv_ioda_setup_same_PE(bus, pe);
1148 return NULL;
1149 }
1150
1151
1152 if (pci_is_root_bus(bus) &&
1153 phb->ioda.root_pe_idx != IODA_INVALID_PE)
1154 pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx];
1155
1156
1157 if (!pe)
1158 pe = pnv_ioda_pick_m64_pe(bus, all);
1159
1160
1161 if (!pe)
1162 pe = pnv_ioda_alloc_pe(phb);
1163
1164 if (!pe) {
1165 pr_warn("%s: Not enough PE# available for PCI bus %04x:%02x\n",
1166 __func__, pci_domain_nr(bus), bus->number);
1167 return NULL;
1168 }
1169
1170 pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS);
1171 pe->pbus = bus;
1172 pe->pdev = NULL;
1173 pe->mve_number = -1;
1174 pe->rid = bus->busn_res.start << 8;
1175
1176 if (all)
1177 pe_info(pe, "Secondary bus %d..%d associated with PE#%x\n",
1178 bus->busn_res.start, bus->busn_res.end, pe->pe_number);
1179 else
1180 pe_info(pe, "Secondary bus %d associated with PE#%x\n",
1181 bus->busn_res.start, pe->pe_number);
1182
1183 if (pnv_ioda_configure_pe(phb, pe)) {
1184
1185 pnv_ioda_free_pe(pe);
1186 pe->pbus = NULL;
1187 return NULL;
1188 }
1189
1190
1191 pnv_ioda_setup_same_PE(bus, pe);
1192
1193
1194 list_add_tail(&pe->list, &phb->ioda.pe_list);
1195
1196 return pe;
1197}
1198
1199static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev)
1200{
1201 int pe_num, found_pe = false, rc;
1202 long rid;
1203 struct pnv_ioda_pe *pe;
1204 struct pci_dev *gpu_pdev;
1205 struct pci_dn *npu_pdn;
1206 struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus);
1207 struct pnv_phb *phb = hose->private_data;
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218 gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev);
1219 for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) {
1220 pe = &phb->ioda.pe_array[pe_num];
1221 if (!pe->pdev)
1222 continue;
1223
1224 if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) {
1225
1226
1227
1228
1229
1230 dev_info(&npu_pdev->dev,
1231 "Associating to existing PE %x\n", pe_num);
1232 pci_dev_get(npu_pdev);
1233 npu_pdn = pci_get_pdn(npu_pdev);
1234 rid = npu_pdev->bus->number << 8 | npu_pdn->devfn;
1235 npu_pdn->pe_number = pe_num;
1236 phb->ioda.pe_rmap[rid] = pe->pe_number;
1237
1238
1239 rc = opal_pci_set_pe(phb->opal_id, pe_num, rid,
1240 OpalPciBusAll,
1241 OPAL_COMPARE_RID_DEVICE_NUMBER,
1242 OPAL_COMPARE_RID_FUNCTION_NUMBER,
1243 OPAL_MAP_PE);
1244 WARN_ON(rc != OPAL_SUCCESS);
1245 found_pe = true;
1246 break;
1247 }
1248 }
1249
1250 if (!found_pe)
1251
1252
1253
1254
1255 return pnv_ioda_setup_dev_PE(npu_pdev);
1256 else
1257 return pe;
1258}
1259
1260static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus)
1261{
1262 struct pci_dev *pdev;
1263
1264 list_for_each_entry(pdev, &bus->devices, bus_list)
1265 pnv_ioda_setup_npu_PE(pdev);
1266}
1267
1268static void pnv_pci_ioda_setup_PEs(void)
1269{
1270 struct pci_controller *hose;
1271 struct pnv_phb *phb;
1272 struct pci_bus *bus;
1273 struct pci_dev *pdev;
1274 struct pnv_ioda_pe *pe;
1275
1276 list_for_each_entry(hose, &hose_list, list_node) {
1277 phb = hose->private_data;
1278 if (phb->type == PNV_PHB_NPU_NVLINK) {
1279
1280 pnv_ioda_reserve_pe(phb, 0);
1281 pnv_ioda_setup_npu_PEs(hose->bus);
1282 if (phb->model == PNV_PHB_MODEL_NPU2)
1283 WARN_ON_ONCE(pnv_npu2_init(hose));
1284 }
1285 if (phb->type == PNV_PHB_NPU_OCAPI) {
1286 bus = hose->bus;
1287 list_for_each_entry(pdev, &bus->devices, bus_list)
1288 pnv_ioda_setup_dev_PE(pdev);
1289 }
1290 }
1291 list_for_each_entry(hose, &hose_list, list_node) {
1292 phb = hose->private_data;
1293 if (phb->type != PNV_PHB_IODA2)
1294 continue;
1295
1296 list_for_each_entry(pe, &phb->ioda.pe_list, list)
1297 pnv_npu2_map_lpar(pe, MSR_DR | MSR_PR | MSR_HV);
1298 }
1299}
1300
1301#ifdef CONFIG_PCI_IOV
1302static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs)
1303{
1304 struct pci_bus *bus;
1305 struct pci_controller *hose;
1306 struct pnv_phb *phb;
1307 struct pci_dn *pdn;
1308 int i, j;
1309 int m64_bars;
1310
1311 bus = pdev->bus;
1312 hose = pci_bus_to_host(bus);
1313 phb = hose->private_data;
1314 pdn = pci_get_pdn(pdev);
1315
1316 if (pdn->m64_single_mode)
1317 m64_bars = num_vfs;
1318 else
1319 m64_bars = 1;
1320
1321 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++)
1322 for (j = 0; j < m64_bars; j++) {
1323 if (pdn->m64_map[j][i] == IODA_INVALID_M64)
1324 continue;
1325 opal_pci_phb_mmio_enable(phb->opal_id,
1326 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0);
1327 clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc);
1328 pdn->m64_map[j][i] = IODA_INVALID_M64;
1329 }
1330
1331 kfree(pdn->m64_map);
1332 return 0;
1333}
1334
1335static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs)
1336{
1337 struct pci_bus *bus;
1338 struct pci_controller *hose;
1339 struct pnv_phb *phb;
1340 struct pci_dn *pdn;
1341 unsigned int win;
1342 struct resource *res;
1343 int i, j;
1344 int64_t rc;
1345 int total_vfs;
1346 resource_size_t size, start;
1347 int pe_num;
1348 int m64_bars;
1349
1350 bus = pdev->bus;
1351 hose = pci_bus_to_host(bus);
1352 phb = hose->private_data;
1353 pdn = pci_get_pdn(pdev);
1354 total_vfs = pci_sriov_get_totalvfs(pdev);
1355
1356 if (pdn->m64_single_mode)
1357 m64_bars = num_vfs;
1358 else
1359 m64_bars = 1;
1360
1361 pdn->m64_map = kmalloc_array(m64_bars,
1362 sizeof(*pdn->m64_map),
1363 GFP_KERNEL);
1364 if (!pdn->m64_map)
1365 return -ENOMEM;
1366
1367 for (i = 0; i < m64_bars ; i++)
1368 for (j = 0; j < PCI_SRIOV_NUM_BARS; j++)
1369 pdn->m64_map[i][j] = IODA_INVALID_M64;
1370
1371
1372 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1373 res = &pdev->resource[i + PCI_IOV_RESOURCES];
1374 if (!res->flags || !res->parent)
1375 continue;
1376
1377 for (j = 0; j < m64_bars; j++) {
1378 do {
1379 win = find_next_zero_bit(&phb->ioda.m64_bar_alloc,
1380 phb->ioda.m64_bar_idx + 1, 0);
1381
1382 if (win >= phb->ioda.m64_bar_idx + 1)
1383 goto m64_failed;
1384 } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc));
1385
1386 pdn->m64_map[j][i] = win;
1387
1388 if (pdn->m64_single_mode) {
1389 size = pci_iov_resource_size(pdev,
1390 PCI_IOV_RESOURCES + i);
1391 start = res->start + size * j;
1392 } else {
1393 size = resource_size(res);
1394 start = res->start;
1395 }
1396
1397
1398 if (pdn->m64_single_mode) {
1399 pe_num = pdn->pe_num_map[j];
1400 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
1401 pe_num, OPAL_M64_WINDOW_TYPE,
1402 pdn->m64_map[j][i], 0);
1403 }
1404
1405 rc = opal_pci_set_phb_mem_window(phb->opal_id,
1406 OPAL_M64_WINDOW_TYPE,
1407 pdn->m64_map[j][i],
1408 start,
1409 0,
1410 size);
1411
1412
1413 if (rc != OPAL_SUCCESS) {
1414 dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n",
1415 win, rc);
1416 goto m64_failed;
1417 }
1418
1419 if (pdn->m64_single_mode)
1420 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1421 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2);
1422 else
1423 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1424 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1);
1425
1426 if (rc != OPAL_SUCCESS) {
1427 dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n",
1428 win, rc);
1429 goto m64_failed;
1430 }
1431 }
1432 }
1433 return 0;
1434
1435m64_failed:
1436 pnv_pci_vf_release_m64(pdev, num_vfs);
1437 return -EBUSY;
1438}
1439
1440static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
1441 int num);
1442
1443static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe)
1444{
1445 struct iommu_table *tbl;
1446 int64_t rc;
1447
1448 tbl = pe->table_group.tables[0];
1449 rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
1450 if (rc)
1451 pe_warn(pe, "OPAL error %ld release DMA window\n", rc);
1452
1453 pnv_pci_ioda2_set_bypass(pe, false);
1454 if (pe->table_group.group) {
1455 iommu_group_put(pe->table_group.group);
1456 BUG_ON(pe->table_group.group);
1457 }
1458 iommu_tce_table_put(tbl);
1459}
1460
1461static void pnv_ioda_release_vf_PE(struct pci_dev *pdev)
1462{
1463 struct pci_bus *bus;
1464 struct pci_controller *hose;
1465 struct pnv_phb *phb;
1466 struct pnv_ioda_pe *pe, *pe_n;
1467 struct pci_dn *pdn;
1468
1469 bus = pdev->bus;
1470 hose = pci_bus_to_host(bus);
1471 phb = hose->private_data;
1472 pdn = pci_get_pdn(pdev);
1473
1474 if (!pdev->is_physfn)
1475 return;
1476
1477 list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) {
1478 if (pe->parent_dev != pdev)
1479 continue;
1480
1481 pnv_pci_ioda2_release_dma_pe(pdev, pe);
1482
1483
1484 mutex_lock(&phb->ioda.pe_list_mutex);
1485 list_del(&pe->list);
1486 mutex_unlock(&phb->ioda.pe_list_mutex);
1487
1488 pnv_ioda_deconfigure_pe(phb, pe);
1489
1490 pnv_ioda_free_pe(pe);
1491 }
1492}
1493
1494void pnv_pci_sriov_disable(struct pci_dev *pdev)
1495{
1496 struct pci_bus *bus;
1497 struct pci_controller *hose;
1498 struct pnv_phb *phb;
1499 struct pnv_ioda_pe *pe;
1500 struct pci_dn *pdn;
1501 u16 num_vfs, i;
1502
1503 bus = pdev->bus;
1504 hose = pci_bus_to_host(bus);
1505 phb = hose->private_data;
1506 pdn = pci_get_pdn(pdev);
1507 num_vfs = pdn->num_vfs;
1508
1509
1510 pnv_ioda_release_vf_PE(pdev);
1511
1512 if (phb->type == PNV_PHB_IODA2) {
1513 if (!pdn->m64_single_mode)
1514 pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map);
1515
1516
1517 pnv_pci_vf_release_m64(pdev, num_vfs);
1518
1519
1520 if (pdn->m64_single_mode) {
1521 for (i = 0; i < num_vfs; i++) {
1522 if (pdn->pe_num_map[i] == IODA_INVALID_PE)
1523 continue;
1524
1525 pe = &phb->ioda.pe_array[pdn->pe_num_map[i]];
1526 pnv_ioda_free_pe(pe);
1527 }
1528 } else
1529 bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1530
1531 kfree(pdn->pe_num_map);
1532 }
1533}
1534
1535static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
1536 struct pnv_ioda_pe *pe);
1537#ifdef CONFIG_IOMMU_API
1538static void pnv_ioda_setup_bus_iommu_group(struct pnv_ioda_pe *pe,
1539 struct iommu_table_group *table_group, struct pci_bus *bus);
1540
1541#endif
1542static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs)
1543{
1544 struct pci_bus *bus;
1545 struct pci_controller *hose;
1546 struct pnv_phb *phb;
1547 struct pnv_ioda_pe *pe;
1548 int pe_num;
1549 u16 vf_index;
1550 struct pci_dn *pdn;
1551
1552 bus = pdev->bus;
1553 hose = pci_bus_to_host(bus);
1554 phb = hose->private_data;
1555 pdn = pci_get_pdn(pdev);
1556
1557 if (!pdev->is_physfn)
1558 return;
1559
1560
1561 for (vf_index = 0; vf_index < num_vfs; vf_index++) {
1562 if (pdn->m64_single_mode)
1563 pe_num = pdn->pe_num_map[vf_index];
1564 else
1565 pe_num = *pdn->pe_num_map + vf_index;
1566
1567 pe = &phb->ioda.pe_array[pe_num];
1568 pe->pe_number = pe_num;
1569 pe->phb = phb;
1570 pe->flags = PNV_IODA_PE_VF;
1571 pe->pbus = NULL;
1572 pe->parent_dev = pdev;
1573 pe->mve_number = -1;
1574 pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) |
1575 pci_iov_virtfn_devfn(pdev, vf_index);
1576
1577 pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%x\n",
1578 hose->global_number, pdev->bus->number,
1579 PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)),
1580 PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num);
1581
1582 if (pnv_ioda_configure_pe(phb, pe)) {
1583
1584 pnv_ioda_free_pe(pe);
1585 pe->pdev = NULL;
1586 continue;
1587 }
1588
1589
1590 mutex_lock(&phb->ioda.pe_list_mutex);
1591 list_add_tail(&pe->list, &phb->ioda.pe_list);
1592 mutex_unlock(&phb->ioda.pe_list_mutex);
1593
1594 pnv_pci_ioda2_setup_dma_pe(phb, pe);
1595#ifdef CONFIG_IOMMU_API
1596 iommu_register_group(&pe->table_group,
1597 pe->phb->hose->global_number, pe->pe_number);
1598 pnv_ioda_setup_bus_iommu_group(pe, &pe->table_group, NULL);
1599#endif
1600 }
1601}
1602
1603int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1604{
1605 struct pci_bus *bus;
1606 struct pci_controller *hose;
1607 struct pnv_phb *phb;
1608 struct pnv_ioda_pe *pe;
1609 struct pci_dn *pdn;
1610 int ret;
1611 u16 i;
1612
1613 bus = pdev->bus;
1614 hose = pci_bus_to_host(bus);
1615 phb = hose->private_data;
1616 pdn = pci_get_pdn(pdev);
1617
1618 if (phb->type == PNV_PHB_IODA2) {
1619 if (!pdn->vfs_expanded) {
1620 dev_info(&pdev->dev, "don't support this SRIOV device"
1621 " with non 64bit-prefetchable IOV BAR\n");
1622 return -ENOSPC;
1623 }
1624
1625
1626
1627
1628
1629 if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) {
1630 dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n");
1631 return -EBUSY;
1632 }
1633
1634
1635 if (pdn->m64_single_mode)
1636 pdn->pe_num_map = kmalloc_array(num_vfs,
1637 sizeof(*pdn->pe_num_map),
1638 GFP_KERNEL);
1639 else
1640 pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL);
1641
1642 if (!pdn->pe_num_map)
1643 return -ENOMEM;
1644
1645 if (pdn->m64_single_mode)
1646 for (i = 0; i < num_vfs; i++)
1647 pdn->pe_num_map[i] = IODA_INVALID_PE;
1648
1649
1650 if (pdn->m64_single_mode) {
1651 for (i = 0; i < num_vfs; i++) {
1652 pe = pnv_ioda_alloc_pe(phb);
1653 if (!pe) {
1654 ret = -EBUSY;
1655 goto m64_failed;
1656 }
1657
1658 pdn->pe_num_map[i] = pe->pe_number;
1659 }
1660 } else {
1661 mutex_lock(&phb->ioda.pe_alloc_mutex);
1662 *pdn->pe_num_map = bitmap_find_next_zero_area(
1663 phb->ioda.pe_alloc, phb->ioda.total_pe_num,
1664 0, num_vfs, 0);
1665 if (*pdn->pe_num_map >= phb->ioda.total_pe_num) {
1666 mutex_unlock(&phb->ioda.pe_alloc_mutex);
1667 dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs);
1668 kfree(pdn->pe_num_map);
1669 return -EBUSY;
1670 }
1671 bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1672 mutex_unlock(&phb->ioda.pe_alloc_mutex);
1673 }
1674 pdn->num_vfs = num_vfs;
1675
1676
1677 ret = pnv_pci_vf_assign_m64(pdev, num_vfs);
1678 if (ret) {
1679 dev_info(&pdev->dev, "Not enough M64 window resources\n");
1680 goto m64_failed;
1681 }
1682
1683
1684
1685
1686
1687
1688 if (!pdn->m64_single_mode) {
1689 ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map);
1690 if (ret)
1691 goto m64_failed;
1692 }
1693 }
1694
1695
1696 pnv_ioda_setup_vf_PE(pdev, num_vfs);
1697
1698 return 0;
1699
1700m64_failed:
1701 if (pdn->m64_single_mode) {
1702 for (i = 0; i < num_vfs; i++) {
1703 if (pdn->pe_num_map[i] == IODA_INVALID_PE)
1704 continue;
1705
1706 pe = &phb->ioda.pe_array[pdn->pe_num_map[i]];
1707 pnv_ioda_free_pe(pe);
1708 }
1709 } else
1710 bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1711
1712
1713 kfree(pdn->pe_num_map);
1714
1715 return ret;
1716}
1717
1718int pnv_pcibios_sriov_disable(struct pci_dev *pdev)
1719{
1720 pnv_pci_sriov_disable(pdev);
1721
1722
1723 remove_dev_pci_data(pdev);
1724 return 0;
1725}
1726
1727int pnv_pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1728{
1729
1730 add_dev_pci_data(pdev);
1731
1732 return pnv_pci_sriov_enable(pdev, num_vfs);
1733}
1734#endif
1735
1736static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev)
1737{
1738 struct pci_dn *pdn = pci_get_pdn(pdev);
1739 struct pnv_ioda_pe *pe;
1740
1741
1742
1743
1744
1745
1746 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
1747 return;
1748
1749 pe = &phb->ioda.pe_array[pdn->pe_number];
1750 WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops);
1751 set_dma_offset(&pdev->dev, pe->tce_bypass_base);
1752 set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]);
1753
1754
1755
1756
1757
1758
1759}
1760
1761static bool pnv_pci_ioda_pe_single_vendor(struct pnv_ioda_pe *pe)
1762{
1763 unsigned short vendor = 0;
1764 struct pci_dev *pdev;
1765
1766 if (pe->device_count == 1)
1767 return true;
1768
1769
1770 if (!pe->pbus)
1771 return true;
1772
1773 list_for_each_entry(pdev, &pe->pbus->devices, bus_list) {
1774 if (!vendor) {
1775 vendor = pdev->vendor;
1776 continue;
1777 }
1778
1779 if (pdev->vendor != vendor)
1780 return false;
1781 }
1782
1783 return true;
1784}
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803static int pnv_pci_ioda_dma_64bit_bypass(struct pnv_ioda_pe *pe)
1804{
1805 u64 window_size, table_size, tce_count, addr;
1806 struct page *table_pages;
1807 u64 tce_order = 28;
1808 __be64 *tces;
1809 s64 rc;
1810
1811
1812
1813
1814
1815 window_size = roundup_pow_of_two(memory_hotplug_max() + (1ULL << 32));
1816 tce_count = window_size >> tce_order;
1817 table_size = tce_count << 3;
1818
1819 if (table_size < PAGE_SIZE)
1820 table_size = PAGE_SIZE;
1821
1822 table_pages = alloc_pages_node(pe->phb->hose->node, GFP_KERNEL,
1823 get_order(table_size));
1824 if (!table_pages)
1825 goto err;
1826
1827 tces = page_address(table_pages);
1828 if (!tces)
1829 goto err;
1830
1831 memset(tces, 0, table_size);
1832
1833 for (addr = 0; addr < memory_hotplug_max(); addr += (1 << tce_order)) {
1834 tces[(addr + (1ULL << 32)) >> tce_order] =
1835 cpu_to_be64(addr | TCE_PCI_READ | TCE_PCI_WRITE);
1836 }
1837
1838 rc = opal_pci_map_pe_dma_window(pe->phb->opal_id,
1839 pe->pe_number,
1840
1841 (pe->pe_number << 1) + 0,
1842 1,
1843 __pa(tces),
1844 table_size,
1845 1 << tce_order);
1846 if (rc == OPAL_SUCCESS) {
1847 pe_info(pe, "Using 64-bit DMA iommu bypass (through TVE#0)\n");
1848 return 0;
1849 }
1850err:
1851 pe_err(pe, "Error configuring 64-bit DMA bypass\n");
1852 return -EIO;
1853}
1854
1855static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask)
1856{
1857 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1858 struct pnv_phb *phb = hose->private_data;
1859 struct pci_dn *pdn = pci_get_pdn(pdev);
1860 struct pnv_ioda_pe *pe;
1861 uint64_t top;
1862 bool bypass = false;
1863 s64 rc;
1864
1865 if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1866 return -ENODEV;
1867
1868 pe = &phb->ioda.pe_array[pdn->pe_number];
1869 if (pe->tce_bypass_enabled) {
1870 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1;
1871 bypass = (dma_mask >= top);
1872 }
1873
1874 if (bypass) {
1875 dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n");
1876 set_dma_ops(&pdev->dev, &dma_nommu_ops);
1877 } else {
1878
1879
1880
1881
1882
1883
1884 if (dma_mask >> 32 &&
1885 dma_mask > (memory_hotplug_max() + (1ULL << 32)) &&
1886 pnv_pci_ioda_pe_single_vendor(pe) &&
1887 phb->model == PNV_PHB_MODEL_PHB3) {
1888
1889 rc = pnv_pci_ioda_dma_64bit_bypass(pe);
1890 if (rc)
1891 return rc;
1892
1893 set_dma_offset(&pdev->dev, (1ULL << 32));
1894 set_dma_ops(&pdev->dev, &dma_nommu_ops);
1895 } else if (dma_mask >> 32 && dma_mask != DMA_BIT_MASK(64)) {
1896
1897
1898
1899
1900
1901
1902 return -ENOMEM;
1903 } else {
1904 dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n");
1905 set_dma_ops(&pdev->dev, &dma_iommu_ops);
1906 }
1907 }
1908 *pdev->dev.dma_mask = dma_mask;
1909
1910
1911 pnv_npu_try_dma_set_bypass(pdev, bypass);
1912
1913 return 0;
1914}
1915
1916static u64 pnv_pci_ioda_dma_get_required_mask(struct pci_dev *pdev)
1917{
1918 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1919 struct pnv_phb *phb = hose->private_data;
1920 struct pci_dn *pdn = pci_get_pdn(pdev);
1921 struct pnv_ioda_pe *pe;
1922 u64 end, mask;
1923
1924 if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1925 return 0;
1926
1927 pe = &phb->ioda.pe_array[pdn->pe_number];
1928 if (!pe->tce_bypass_enabled)
1929 return __dma_get_required_mask(&pdev->dev);
1930
1931
1932 end = pe->tce_bypass_base + memblock_end_of_DRAM();
1933 mask = 1ULL << (fls64(end) - 1);
1934 mask += mask - 1;
1935
1936 return mask;
1937}
1938
1939static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, struct pci_bus *bus)
1940{
1941 struct pci_dev *dev;
1942
1943 list_for_each_entry(dev, &bus->devices, bus_list) {
1944 set_iommu_table_base(&dev->dev, pe->table_group.tables[0]);
1945 set_dma_offset(&dev->dev, pe->tce_bypass_base);
1946
1947 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1948 pnv_ioda_setup_bus_dma(pe, dev->subordinate);
1949 }
1950}
1951
1952static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb,
1953 bool real_mode)
1954{
1955 return real_mode ? (__be64 __iomem *)(phb->regs_phys + 0x210) :
1956 (phb->regs + 0x210);
1957}
1958
1959static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl,
1960 unsigned long index, unsigned long npages, bool rm)
1961{
1962 struct iommu_table_group_link *tgl = list_first_entry_or_null(
1963 &tbl->it_group_list, struct iommu_table_group_link,
1964 next);
1965 struct pnv_ioda_pe *pe = container_of(tgl->table_group,
1966 struct pnv_ioda_pe, table_group);
1967 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm);
1968 unsigned long start, end, inc;
1969
1970 start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset);
1971 end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset +
1972 npages - 1);
1973
1974
1975 start |= (1ull << 63);
1976 end |= (1ull << 63);
1977 inc = 16;
1978 end |= inc - 1;
1979
1980 mb();
1981 while (start <= end) {
1982 if (rm)
1983 __raw_rm_writeq_be(start, invalidate);
1984 else
1985 __raw_writeq_be(start, invalidate);
1986
1987 start += inc;
1988 }
1989
1990
1991
1992
1993
1994}
1995
1996static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index,
1997 long npages, unsigned long uaddr,
1998 enum dma_data_direction direction,
1999 unsigned long attrs)
2000{
2001 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
2002 attrs);
2003
2004 if (!ret)
2005 pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false);
2006
2007 return ret;
2008}
2009
2010#ifdef CONFIG_IOMMU_API
2011static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index,
2012 unsigned long *hpa, enum dma_data_direction *direction)
2013{
2014 long ret = pnv_tce_xchg(tbl, index, hpa, direction, true);
2015
2016 if (!ret)
2017 pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, false);
2018
2019 return ret;
2020}
2021
2022static int pnv_ioda1_tce_xchg_rm(struct iommu_table *tbl, long index,
2023 unsigned long *hpa, enum dma_data_direction *direction)
2024{
2025 long ret = pnv_tce_xchg(tbl, index, hpa, direction, false);
2026
2027 if (!ret)
2028 pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, true);
2029
2030 return ret;
2031}
2032#endif
2033
2034static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index,
2035 long npages)
2036{
2037 pnv_tce_free(tbl, index, npages);
2038
2039 pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false);
2040}
2041
2042static struct iommu_table_ops pnv_ioda1_iommu_ops = {
2043 .set = pnv_ioda1_tce_build,
2044#ifdef CONFIG_IOMMU_API
2045 .exchange = pnv_ioda1_tce_xchg,
2046 .exchange_rm = pnv_ioda1_tce_xchg_rm,
2047 .useraddrptr = pnv_tce_useraddrptr,
2048#endif
2049 .clear = pnv_ioda1_tce_free,
2050 .get = pnv_tce_get,
2051};
2052
2053#define PHB3_TCE_KILL_INVAL_ALL PPC_BIT(0)
2054#define PHB3_TCE_KILL_INVAL_PE PPC_BIT(1)
2055#define PHB3_TCE_KILL_INVAL_ONE PPC_BIT(2)
2056
2057static void pnv_pci_phb3_tce_invalidate_entire(struct pnv_phb *phb, bool rm)
2058{
2059 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(phb, rm);
2060 const unsigned long val = PHB3_TCE_KILL_INVAL_ALL;
2061
2062 mb();
2063 if (rm)
2064 __raw_rm_writeq_be(val, invalidate);
2065 else
2066 __raw_writeq_be(val, invalidate);
2067}
2068
2069static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe)
2070{
2071
2072 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false);
2073 unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF);
2074
2075 mb();
2076 __raw_writeq_be(val, invalidate);
2077}
2078
2079static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, bool rm,
2080 unsigned shift, unsigned long index,
2081 unsigned long npages)
2082{
2083 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm);
2084 unsigned long start, end, inc;
2085
2086
2087 start = PHB3_TCE_KILL_INVAL_ONE;
2088 start |= (pe->pe_number & 0xFF);
2089 end = start;
2090
2091
2092 start |= (index << shift);
2093 end |= ((index + npages - 1) << shift);
2094 inc = (0x1ull << shift);
2095 mb();
2096
2097 while (start <= end) {
2098 if (rm)
2099 __raw_rm_writeq_be(start, invalidate);
2100 else
2101 __raw_writeq_be(start, invalidate);
2102 start += inc;
2103 }
2104}
2105
2106static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe)
2107{
2108 struct pnv_phb *phb = pe->phb;
2109
2110 if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs)
2111 pnv_pci_phb3_tce_invalidate_pe(pe);
2112 else
2113 opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL_PE,
2114 pe->pe_number, 0, 0, 0);
2115}
2116
2117static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl,
2118 unsigned long index, unsigned long npages, bool rm)
2119{
2120 struct iommu_table_group_link *tgl;
2121
2122 list_for_each_entry_lockless(tgl, &tbl->it_group_list, next) {
2123 struct pnv_ioda_pe *pe = container_of(tgl->table_group,
2124 struct pnv_ioda_pe, table_group);
2125 struct pnv_phb *phb = pe->phb;
2126 unsigned int shift = tbl->it_page_shift;
2127
2128
2129
2130
2131
2132
2133 if (phb->model == PNV_PHB_MODEL_NPU) {
2134
2135
2136
2137
2138
2139 pnv_pci_phb3_tce_invalidate_entire(phb, rm);
2140 continue;
2141 }
2142 if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs)
2143 pnv_pci_phb3_tce_invalidate(pe, rm, shift,
2144 index, npages);
2145 else
2146 opal_pci_tce_kill(phb->opal_id,
2147 OPAL_PCI_TCE_KILL_PAGES,
2148 pe->pe_number, 1u << shift,
2149 index << shift, npages);
2150 }
2151}
2152
2153void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm)
2154{
2155 if (phb->model == PNV_PHB_MODEL_NPU || phb->model == PNV_PHB_MODEL_PHB3)
2156 pnv_pci_phb3_tce_invalidate_entire(phb, rm);
2157 else
2158 opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL, 0, 0, 0, 0);
2159}
2160
2161static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index,
2162 long npages, unsigned long uaddr,
2163 enum dma_data_direction direction,
2164 unsigned long attrs)
2165{
2166 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
2167 attrs);
2168
2169 if (!ret)
2170 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
2171
2172 return ret;
2173}
2174
2175#ifdef CONFIG_IOMMU_API
2176static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index,
2177 unsigned long *hpa, enum dma_data_direction *direction)
2178{
2179 long ret = pnv_tce_xchg(tbl, index, hpa, direction, true);
2180
2181 if (!ret)
2182 pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false);
2183
2184 return ret;
2185}
2186
2187static int pnv_ioda2_tce_xchg_rm(struct iommu_table *tbl, long index,
2188 unsigned long *hpa, enum dma_data_direction *direction)
2189{
2190 long ret = pnv_tce_xchg(tbl, index, hpa, direction, false);
2191
2192 if (!ret)
2193 pnv_pci_ioda2_tce_invalidate(tbl, index, 1, true);
2194
2195 return ret;
2196}
2197#endif
2198
2199static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index,
2200 long npages)
2201{
2202 pnv_tce_free(tbl, index, npages);
2203
2204 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
2205}
2206
2207static struct iommu_table_ops pnv_ioda2_iommu_ops = {
2208 .set = pnv_ioda2_tce_build,
2209#ifdef CONFIG_IOMMU_API
2210 .exchange = pnv_ioda2_tce_xchg,
2211 .exchange_rm = pnv_ioda2_tce_xchg_rm,
2212 .useraddrptr = pnv_tce_useraddrptr,
2213#endif
2214 .clear = pnv_ioda2_tce_free,
2215 .get = pnv_tce_get,
2216 .free = pnv_pci_ioda2_table_free_pages,
2217};
2218
2219static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data)
2220{
2221 unsigned int *weight = (unsigned int *)data;
2222
2223
2224
2225
2226 if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL)
2227 return 0;
2228
2229 if (dev->class == PCI_CLASS_SERIAL_USB_UHCI ||
2230 dev->class == PCI_CLASS_SERIAL_USB_OHCI ||
2231 dev->class == PCI_CLASS_SERIAL_USB_EHCI)
2232 *weight += 3;
2233 else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID)
2234 *weight += 15;
2235 else
2236 *weight += 10;
2237
2238 return 0;
2239}
2240
2241static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe)
2242{
2243 unsigned int weight = 0;
2244
2245
2246#ifdef CONFIG_PCI_IOV
2247 if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) {
2248 pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight);
2249 return weight;
2250 }
2251#endif
2252
2253 if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) {
2254 pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight);
2255 } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) {
2256 struct pci_dev *pdev;
2257
2258 list_for_each_entry(pdev, &pe->pbus->devices, bus_list)
2259 pnv_pci_ioda_dev_dma_weight(pdev, &weight);
2260 } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) {
2261 pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight);
2262 }
2263
2264 return weight;
2265}
2266
2267static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb,
2268 struct pnv_ioda_pe *pe)
2269{
2270
2271 struct page *tce_mem = NULL;
2272 struct iommu_table *tbl;
2273 unsigned int weight, total_weight = 0;
2274 unsigned int tce32_segsz, base, segs, avail, i;
2275 int64_t rc;
2276 void *addr;
2277
2278
2279
2280
2281 weight = pnv_pci_ioda_pe_dma_weight(pe);
2282 if (!weight)
2283 return;
2284
2285 pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight,
2286 &total_weight);
2287 segs = (weight * phb->ioda.dma32_count) / total_weight;
2288 if (!segs)
2289 segs = 1;
2290
2291
2292
2293
2294
2295
2296
2297 do {
2298 for (base = 0; base <= phb->ioda.dma32_count - segs; base++) {
2299 for (avail = 0, i = base; i < base + segs; i++) {
2300 if (phb->ioda.dma32_segmap[i] ==
2301 IODA_INVALID_PE)
2302 avail++;
2303 }
2304
2305 if (avail == segs)
2306 goto found;
2307 }
2308 } while (--segs);
2309
2310 if (!segs) {
2311 pe_warn(pe, "No available DMA32 segments\n");
2312 return;
2313 }
2314
2315found:
2316 tbl = pnv_pci_table_alloc(phb->hose->node);
2317 if (WARN_ON(!tbl))
2318 return;
2319
2320 iommu_register_group(&pe->table_group, phb->hose->global_number,
2321 pe->pe_number);
2322 pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group);
2323
2324
2325 pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n",
2326 weight, total_weight, base, segs);
2327 pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n",
2328 base * PNV_IODA1_DMA32_SEGSIZE,
2329 (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1);
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339 tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3);
2340 tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL,
2341 get_order(tce32_segsz * segs));
2342 if (!tce_mem) {
2343 pe_err(pe, " Failed to allocate a 32-bit TCE memory\n");
2344 goto fail;
2345 }
2346 addr = page_address(tce_mem);
2347 memset(addr, 0, tce32_segsz * segs);
2348
2349
2350 for (i = 0; i < segs; i++) {
2351 rc = opal_pci_map_pe_dma_window(phb->opal_id,
2352 pe->pe_number,
2353 base + i, 1,
2354 __pa(addr) + tce32_segsz * i,
2355 tce32_segsz, IOMMU_PAGE_SIZE_4K);
2356 if (rc) {
2357 pe_err(pe, " Failed to configure 32-bit TCE table,"
2358 " err %ld\n", rc);
2359 goto fail;
2360 }
2361 }
2362
2363
2364 for (i = base; i < base + segs; i++)
2365 phb->ioda.dma32_segmap[i] = pe->pe_number;
2366
2367
2368 pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs,
2369 base * PNV_IODA1_DMA32_SEGSIZE,
2370 IOMMU_PAGE_SHIFT_4K);
2371
2372 tbl->it_ops = &pnv_ioda1_iommu_ops;
2373 pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift;
2374 pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift;
2375 iommu_init_table(tbl, phb->hose->node);
2376
2377 if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2378 pnv_ioda_setup_bus_dma(pe, pe->pbus);
2379
2380 return;
2381 fail:
2382
2383 if (tce_mem)
2384 __free_pages(tce_mem, get_order(tce32_segsz * segs));
2385 if (tbl) {
2386 pnv_pci_unlink_table_and_group(tbl, &pe->table_group);
2387 iommu_tce_table_put(tbl);
2388 }
2389}
2390
2391static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group,
2392 int num, struct iommu_table *tbl)
2393{
2394 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2395 table_group);
2396 struct pnv_phb *phb = pe->phb;
2397 int64_t rc;
2398 const unsigned long size = tbl->it_indirect_levels ?
2399 tbl->it_level_size : tbl->it_size;
2400 const __u64 start_addr = tbl->it_offset << tbl->it_page_shift;
2401 const __u64 win_size = tbl->it_size << tbl->it_page_shift;
2402
2403 pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num,
2404 start_addr, start_addr + win_size - 1,
2405 IOMMU_PAGE_SIZE(tbl));
2406
2407
2408
2409
2410
2411 rc = opal_pci_map_pe_dma_window(phb->opal_id,
2412 pe->pe_number,
2413 (pe->pe_number << 1) + num,
2414 tbl->it_indirect_levels + 1,
2415 __pa(tbl->it_base),
2416 size << 3,
2417 IOMMU_PAGE_SIZE(tbl));
2418 if (rc) {
2419 pe_err(pe, "Failed to configure TCE table, err %ld\n", rc);
2420 return rc;
2421 }
2422
2423 pnv_pci_link_table_and_group(phb->hose->node, num,
2424 tbl, &pe->table_group);
2425 pnv_pci_ioda2_tce_invalidate_pe(pe);
2426
2427 return 0;
2428}
2429
2430void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable)
2431{
2432 uint16_t window_id = (pe->pe_number << 1 ) + 1;
2433 int64_t rc;
2434
2435 pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis");
2436 if (enable) {
2437 phys_addr_t top = memblock_end_of_DRAM();
2438
2439 top = roundup_pow_of_two(top);
2440 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2441 pe->pe_number,
2442 window_id,
2443 pe->tce_bypass_base,
2444 top);
2445 } else {
2446 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2447 pe->pe_number,
2448 window_id,
2449 pe->tce_bypass_base,
2450 0);
2451 }
2452 if (rc)
2453 pe_err(pe, "OPAL error %lld configuring bypass window\n", rc);
2454 else
2455 pe->tce_bypass_enabled = enable;
2456}
2457
2458static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group,
2459 int num, __u32 page_shift, __u64 window_size, __u32 levels,
2460 bool alloc_userspace_copy, struct iommu_table **ptbl)
2461{
2462 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2463 table_group);
2464 int nid = pe->phb->hose->node;
2465 __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start;
2466 long ret;
2467 struct iommu_table *tbl;
2468
2469 tbl = pnv_pci_table_alloc(nid);
2470 if (!tbl)
2471 return -ENOMEM;
2472
2473 tbl->it_ops = &pnv_ioda2_iommu_ops;
2474
2475 ret = pnv_pci_ioda2_table_alloc_pages(nid,
2476 bus_offset, page_shift, window_size,
2477 levels, alloc_userspace_copy, tbl);
2478 if (ret) {
2479 iommu_tce_table_put(tbl);
2480 return ret;
2481 }
2482
2483 *ptbl = tbl;
2484
2485 return 0;
2486}
2487
2488static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe)
2489{
2490 struct iommu_table *tbl = NULL;
2491 long rc;
2492
2493
2494
2495
2496
2497
2498 const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max());
2499
2500
2501
2502
2503
2504
2505 const u64 window_size = min((u64)pe->table_group.tce32_size, max_memory);
2506
2507 rc = pnv_pci_ioda2_create_table(&pe->table_group, 0,
2508 IOMMU_PAGE_SHIFT_4K,
2509 window_size,
2510 POWERNV_IOMMU_DEFAULT_LEVELS, false, &tbl);
2511 if (rc) {
2512 pe_err(pe, "Failed to create 32-bit TCE table, err %ld",
2513 rc);
2514 return rc;
2515 }
2516
2517 iommu_init_table(tbl, pe->phb->hose->node);
2518
2519 rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl);
2520 if (rc) {
2521 pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n",
2522 rc);
2523 iommu_tce_table_put(tbl);
2524 return rc;
2525 }
2526
2527 if (!pnv_iommu_bypass_disabled)
2528 pnv_pci_ioda2_set_bypass(pe, true);
2529
2530 return 0;
2531}
2532
2533#if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV)
2534static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
2535 int num)
2536{
2537 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2538 table_group);
2539 struct pnv_phb *phb = pe->phb;
2540 long ret;
2541
2542 pe_info(pe, "Removing DMA window #%d\n", num);
2543
2544 ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
2545 (pe->pe_number << 1) + num,
2546 0, 0,
2547 0, 0);
2548 if (ret)
2549 pe_warn(pe, "Unmapping failed, ret = %ld\n", ret);
2550 else
2551 pnv_pci_ioda2_tce_invalidate_pe(pe);
2552
2553 pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
2554
2555 return ret;
2556}
2557#endif
2558
2559#ifdef CONFIG_IOMMU_API
2560unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift,
2561 __u64 window_size, __u32 levels)
2562{
2563 unsigned long bytes = 0;
2564 const unsigned window_shift = ilog2(window_size);
2565 unsigned entries_shift = window_shift - page_shift;
2566 unsigned table_shift = entries_shift + 3;
2567 unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift);
2568 unsigned long direct_table_size;
2569
2570 if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) ||
2571 !is_power_of_2(window_size))
2572 return 0;
2573
2574
2575 entries_shift = (entries_shift + levels - 1) / levels;
2576 table_shift = entries_shift + 3;
2577 table_shift = max_t(unsigned, table_shift, PAGE_SHIFT);
2578 direct_table_size = 1UL << table_shift;
2579
2580 for ( ; levels; --levels) {
2581 bytes += _ALIGN_UP(tce_table_size, direct_table_size);
2582
2583 tce_table_size /= direct_table_size;
2584 tce_table_size <<= 3;
2585 tce_table_size = max_t(unsigned long,
2586 tce_table_size, direct_table_size);
2587 }
2588
2589 return bytes + bytes;
2590}
2591
2592static long pnv_pci_ioda2_create_table_userspace(
2593 struct iommu_table_group *table_group,
2594 int num, __u32 page_shift, __u64 window_size, __u32 levels,
2595 struct iommu_table **ptbl)
2596{
2597 return pnv_pci_ioda2_create_table(table_group,
2598 num, page_shift, window_size, levels, true, ptbl);
2599}
2600
2601static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group)
2602{
2603 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2604 table_group);
2605
2606 struct iommu_table *tbl = pe->table_group.tables[0];
2607
2608 pnv_pci_ioda2_set_bypass(pe, false);
2609 pnv_pci_ioda2_unset_window(&pe->table_group, 0);
2610 if (pe->pbus)
2611 pnv_ioda_setup_bus_dma(pe, pe->pbus);
2612 iommu_tce_table_put(tbl);
2613}
2614
2615static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group)
2616{
2617 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2618 table_group);
2619
2620 pnv_pci_ioda2_setup_default_config(pe);
2621 if (pe->pbus)
2622 pnv_ioda_setup_bus_dma(pe, pe->pbus);
2623}
2624
2625static struct iommu_table_group_ops pnv_pci_ioda2_ops = {
2626 .get_table_size = pnv_pci_ioda2_get_table_size,
2627 .create_table = pnv_pci_ioda2_create_table_userspace,
2628 .set_window = pnv_pci_ioda2_set_window,
2629 .unset_window = pnv_pci_ioda2_unset_window,
2630 .take_ownership = pnv_ioda2_take_ownership,
2631 .release_ownership = pnv_ioda2_release_ownership,
2632};
2633
2634static void pnv_ioda_setup_bus_iommu_group_add_devices(struct pnv_ioda_pe *pe,
2635 struct iommu_table_group *table_group,
2636 struct pci_bus *bus)
2637{
2638 struct pci_dev *dev;
2639
2640 list_for_each_entry(dev, &bus->devices, bus_list) {
2641 iommu_add_device(table_group, &dev->dev);
2642
2643 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
2644 pnv_ioda_setup_bus_iommu_group_add_devices(pe,
2645 table_group, dev->subordinate);
2646 }
2647}
2648
2649static void pnv_ioda_setup_bus_iommu_group(struct pnv_ioda_pe *pe,
2650 struct iommu_table_group *table_group, struct pci_bus *bus)
2651{
2652
2653 if (pe->flags & PNV_IODA_PE_DEV)
2654 iommu_add_device(table_group, &pe->pdev->dev);
2655
2656 if ((pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) || bus)
2657 pnv_ioda_setup_bus_iommu_group_add_devices(pe, table_group,
2658 bus);
2659}
2660
2661static unsigned long pnv_ioda_parse_tce_sizes(struct pnv_phb *phb);
2662
2663static void pnv_pci_ioda_setup_iommu_api(void)
2664{
2665 struct pci_controller *hose;
2666 struct pnv_phb *phb;
2667 struct pnv_ioda_pe *pe;
2668
2669
2670
2671
2672
2673
2674
2675
2676
2677
2678
2679
2680
2681
2682
2683 list_for_each_entry(hose, &hose_list, list_node) {
2684 phb = hose->private_data;
2685
2686 if (phb->type == PNV_PHB_NPU_NVLINK ||
2687 phb->type == PNV_PHB_NPU_OCAPI)
2688 continue;
2689
2690 list_for_each_entry(pe, &phb->ioda.pe_list, list) {
2691 struct iommu_table_group *table_group;
2692
2693 table_group = pnv_try_setup_npu_table_group(pe);
2694 if (!table_group) {
2695 if (!pnv_pci_ioda_pe_dma_weight(pe))
2696 continue;
2697
2698 table_group = &pe->table_group;
2699 iommu_register_group(&pe->table_group,
2700 pe->phb->hose->global_number,
2701 pe->pe_number);
2702 }
2703 pnv_ioda_setup_bus_iommu_group(pe, table_group,
2704 pe->pbus);
2705 }
2706 }
2707
2708
2709
2710
2711
2712 list_for_each_entry(hose, &hose_list, list_node) {
2713 unsigned long pgsizes;
2714
2715 phb = hose->private_data;
2716
2717 if (phb->type != PNV_PHB_NPU_NVLINK)
2718 continue;
2719
2720 pgsizes = pnv_ioda_parse_tce_sizes(phb);
2721 list_for_each_entry(pe, &phb->ioda.pe_list, list) {
2722
2723
2724
2725
2726
2727 pe->table_group.pgsizes = pgsizes;
2728 pnv_npu_compound_attach(pe);
2729 }
2730 }
2731}
2732#else
2733static void pnv_pci_ioda_setup_iommu_api(void) { };
2734#endif
2735
2736static unsigned long pnv_ioda_parse_tce_sizes(struct pnv_phb *phb)
2737{
2738 struct pci_controller *hose = phb->hose;
2739 struct device_node *dn = hose->dn;
2740 unsigned long mask = 0;
2741 int i, rc, count;
2742 u32 val;
2743
2744 count = of_property_count_u32_elems(dn, "ibm,supported-tce-sizes");
2745 if (count <= 0) {
2746 mask = SZ_4K | SZ_64K;
2747
2748 if (cpu_has_feature(CPU_FTR_ARCH_207S) &&
2749 !cpu_has_feature(CPU_FTR_ARCH_300))
2750 mask |= SZ_16M | SZ_256M;
2751 return mask;
2752 }
2753
2754 for (i = 0; i < count; i++) {
2755 rc = of_property_read_u32_index(dn, "ibm,supported-tce-sizes",
2756 i, &val);
2757 if (rc == 0)
2758 mask |= 1ULL << val;
2759 }
2760
2761 return mask;
2762}
2763
2764static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
2765 struct pnv_ioda_pe *pe)
2766{
2767 int64_t rc;
2768
2769 if (!pnv_pci_ioda_pe_dma_weight(pe))
2770 return;
2771
2772
2773 pe->tce_bypass_base = 1ull << 59;
2774
2775
2776 pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n",
2777 phb->ioda.m32_pci_base);
2778
2779
2780 pe->table_group.tce32_start = 0;
2781 pe->table_group.tce32_size = phb->ioda.m32_pci_base;
2782 pe->table_group.max_dynamic_windows_supported =
2783 IOMMU_TABLE_GROUP_MAX_TABLES;
2784 pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS;
2785 pe->table_group.pgsizes = pnv_ioda_parse_tce_sizes(phb);
2786#ifdef CONFIG_IOMMU_API
2787 pe->table_group.ops = &pnv_pci_ioda2_ops;
2788#endif
2789
2790 rc = pnv_pci_ioda2_setup_default_config(pe);
2791 if (rc)
2792 return;
2793
2794 if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2795 pnv_ioda_setup_bus_dma(pe, pe->pbus);
2796}
2797
2798int64_t pnv_opal_pci_msi_eoi(struct irq_chip *chip, unsigned int hw_irq)
2799{
2800 struct pnv_phb *phb = container_of(chip, struct pnv_phb,
2801 ioda.irq_chip);
2802
2803 return opal_pci_msi_eoi(phb->opal_id, hw_irq);
2804}
2805
2806static void pnv_ioda2_msi_eoi(struct irq_data *d)
2807{
2808 int64_t rc;
2809 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
2810 struct irq_chip *chip = irq_data_get_irq_chip(d);
2811
2812 rc = pnv_opal_pci_msi_eoi(chip, hw_irq);
2813 WARN_ON_ONCE(rc);
2814
2815 icp_native_eoi(d);
2816}
2817
2818
2819void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq)
2820{
2821 struct irq_data *idata;
2822 struct irq_chip *ichip;
2823
2824
2825 if (phb->model != PNV_PHB_MODEL_PHB3)
2826 return;
2827
2828 if (!phb->ioda.irq_chip_init) {
2829
2830
2831
2832
2833 idata = irq_get_irq_data(virq);
2834 ichip = irq_data_get_irq_chip(idata);
2835 phb->ioda.irq_chip_init = 1;
2836 phb->ioda.irq_chip = *ichip;
2837 phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi;
2838 }
2839 irq_set_chip(virq, &phb->ioda.irq_chip);
2840}
2841
2842
2843
2844
2845
2846bool is_pnv_opal_msi(struct irq_chip *chip)
2847{
2848 return chip->irq_eoi == pnv_ioda2_msi_eoi;
2849}
2850EXPORT_SYMBOL_GPL(is_pnv_opal_msi);
2851
2852static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
2853 unsigned int hwirq, unsigned int virq,
2854 unsigned int is_64, struct msi_msg *msg)
2855{
2856 struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev);
2857 unsigned int xive_num = hwirq - phb->msi_base;
2858 __be32 data;
2859 int rc;
2860
2861
2862 if (pe == NULL)
2863 return -ENXIO;
2864
2865
2866 if (pe->mve_number < 0)
2867 return -ENXIO;
2868
2869
2870 if (dev->no_64bit_msi)
2871 is_64 = 0;
2872
2873
2874 rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
2875 if (rc) {
2876 pr_warn("%s: OPAL error %d setting XIVE %d PE\n",
2877 pci_name(dev), rc, xive_num);
2878 return -EIO;
2879 }
2880
2881 if (is_64) {
2882 __be64 addr64;
2883
2884 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1,
2885 &addr64, &data);
2886 if (rc) {
2887 pr_warn("%s: OPAL error %d getting 64-bit MSI data\n",
2888 pci_name(dev), rc);
2889 return -EIO;
2890 }
2891 msg->address_hi = be64_to_cpu(addr64) >> 32;
2892 msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful;
2893 } else {
2894 __be32 addr32;
2895
2896 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1,
2897 &addr32, &data);
2898 if (rc) {
2899 pr_warn("%s: OPAL error %d getting 32-bit MSI data\n",
2900 pci_name(dev), rc);
2901 return -EIO;
2902 }
2903 msg->address_hi = 0;
2904 msg->address_lo = be32_to_cpu(addr32);
2905 }
2906 msg->data = be32_to_cpu(data);
2907
2908 pnv_set_msi_irq_chip(phb, virq);
2909
2910 pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d),"
2911 " address=%x_%08x data=%x PE# %x\n",
2912 pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num,
2913 msg->address_hi, msg->address_lo, data, pe->pe_number);
2914
2915 return 0;
2916}
2917
2918static void pnv_pci_init_ioda_msis(struct pnv_phb *phb)
2919{
2920 unsigned int count;
2921 const __be32 *prop = of_get_property(phb->hose->dn,
2922 "ibm,opal-msi-ranges", NULL);
2923 if (!prop) {
2924
2925 prop = of_get_property(phb->hose->dn, "msi-ranges", NULL);
2926 }
2927 if (!prop)
2928 return;
2929
2930 phb->msi_base = be32_to_cpup(prop);
2931 count = be32_to_cpup(prop + 1);
2932 if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) {
2933 pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
2934 phb->hose->global_number);
2935 return;
2936 }
2937
2938 phb->msi_setup = pnv_pci_ioda_msi_setup;
2939 phb->msi32_support = 1;
2940 pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
2941 count, phb->msi_base);
2942}
2943
2944#ifdef CONFIG_PCI_IOV
2945static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev)
2946{
2947 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
2948 struct pnv_phb *phb = hose->private_data;
2949 const resource_size_t gate = phb->ioda.m64_segsize >> 2;
2950 struct resource *res;
2951 int i;
2952 resource_size_t size, total_vf_bar_sz;
2953 struct pci_dn *pdn;
2954 int mul, total_vfs;
2955
2956 if (!pdev->is_physfn || pci_dev_is_added(pdev))
2957 return;
2958
2959 pdn = pci_get_pdn(pdev);
2960 pdn->vfs_expanded = 0;
2961 pdn->m64_single_mode = false;
2962
2963 total_vfs = pci_sriov_get_totalvfs(pdev);
2964 mul = phb->ioda.total_pe_num;
2965 total_vf_bar_sz = 0;
2966
2967 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2968 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2969 if (!res->flags || res->parent)
2970 continue;
2971 if (!pnv_pci_is_m64_flags(res->flags)) {
2972 dev_warn(&pdev->dev, "Don't support SR-IOV with"
2973 " non M64 VF BAR%d: %pR. \n",
2974 i, res);
2975 goto truncate_iov;
2976 }
2977
2978 total_vf_bar_sz += pci_iov_resource_size(pdev,
2979 i + PCI_IOV_RESOURCES);
2980
2981
2982
2983
2984
2985
2986
2987
2988
2989
2990
2991
2992
2993 if (total_vf_bar_sz > gate) {
2994 mul = roundup_pow_of_two(total_vfs);
2995 dev_info(&pdev->dev,
2996 "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n",
2997 total_vf_bar_sz, gate, mul);
2998 pdn->m64_single_mode = true;
2999 break;
3000 }
3001 }
3002
3003 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
3004 res = &pdev->resource[i + PCI_IOV_RESOURCES];
3005 if (!res->flags || res->parent)
3006 continue;
3007
3008 size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES);
3009
3010
3011
3012
3013 if (pdn->m64_single_mode && (size < SZ_32M))
3014 goto truncate_iov;
3015 dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res);
3016 res->end = res->start + size * mul - 1;
3017 dev_dbg(&pdev->dev, " %pR\n", res);
3018 dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)",
3019 i, res, mul);
3020 }
3021 pdn->vfs_expanded = mul;
3022
3023 return;
3024
3025truncate_iov:
3026
3027 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
3028 res = &pdev->resource[i + PCI_IOV_RESOURCES];
3029 res->flags = 0;
3030 res->end = res->start - 1;
3031 }
3032}
3033#endif
3034
3035static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe,
3036 struct resource *res)
3037{
3038 struct pnv_phb *phb = pe->phb;
3039 struct pci_bus_region region;
3040 int index;
3041 int64_t rc;
3042
3043 if (!res || !res->flags || res->start > res->end)
3044 return;
3045
3046 if (res->flags & IORESOURCE_IO) {
3047 region.start = res->start - phb->ioda.io_pci_base;
3048 region.end = res->end - phb->ioda.io_pci_base;
3049 index = region.start / phb->ioda.io_segsize;
3050
3051 while (index < phb->ioda.total_pe_num &&
3052 region.start <= region.end) {
3053 phb->ioda.io_segmap[index] = pe->pe_number;
3054 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3055 pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index);
3056 if (rc != OPAL_SUCCESS) {
3057 pr_err("%s: Error %lld mapping IO segment#%d to PE#%x\n",
3058 __func__, rc, index, pe->pe_number);
3059 break;
3060 }
3061
3062 region.start += phb->ioda.io_segsize;
3063 index++;
3064 }
3065 } else if ((res->flags & IORESOURCE_MEM) &&
3066 !pnv_pci_is_m64(phb, res)) {
3067 region.start = res->start -
3068 phb->hose->mem_offset[0] -
3069 phb->ioda.m32_pci_base;
3070 region.end = res->end -
3071 phb->hose->mem_offset[0] -
3072 phb->ioda.m32_pci_base;
3073 index = region.start / phb->ioda.m32_segsize;
3074
3075 while (index < phb->ioda.total_pe_num &&
3076 region.start <= region.end) {
3077 phb->ioda.m32_segmap[index] = pe->pe_number;
3078 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3079 pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index);
3080 if (rc != OPAL_SUCCESS) {
3081 pr_err("%s: Error %lld mapping M32 segment#%d to PE#%x",
3082 __func__, rc, index, pe->pe_number);
3083 break;
3084 }
3085
3086 region.start += phb->ioda.m32_segsize;
3087 index++;
3088 }
3089 }
3090}
3091
3092
3093
3094
3095
3096
3097static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe)
3098{
3099 struct pci_dev *pdev;
3100 int i;
3101
3102
3103
3104
3105
3106
3107 BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)));
3108
3109 list_for_each_entry(pdev, &pe->pbus->devices, bus_list) {
3110 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
3111 pnv_ioda_setup_pe_res(pe, &pdev->resource[i]);
3112
3113
3114
3115
3116
3117
3118 if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev))
3119 continue;
3120 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
3121 pnv_ioda_setup_pe_res(pe,
3122 &pdev->resource[PCI_BRIDGE_RESOURCES + i]);
3123 }
3124}
3125
3126#ifdef CONFIG_DEBUG_FS
3127static int pnv_pci_diag_data_set(void *data, u64 val)
3128{
3129 struct pci_controller *hose;
3130 struct pnv_phb *phb;
3131 s64 ret;
3132
3133 if (val != 1ULL)
3134 return -EINVAL;
3135
3136 hose = (struct pci_controller *)data;
3137 if (!hose || !hose->private_data)
3138 return -ENODEV;
3139
3140 phb = hose->private_data;
3141
3142
3143 ret = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag_data,
3144 phb->diag_data_size);
3145 if (ret != OPAL_SUCCESS)
3146 return -EIO;
3147
3148
3149 pnv_pci_dump_phb_diag_data(phb->hose, phb->diag_data);
3150 return 0;
3151}
3152
3153DEFINE_SIMPLE_ATTRIBUTE(pnv_pci_diag_data_fops, NULL,
3154 pnv_pci_diag_data_set, "%llu\n");
3155
3156#endif
3157
3158static void pnv_pci_ioda_create_dbgfs(void)
3159{
3160#ifdef CONFIG_DEBUG_FS
3161 struct pci_controller *hose, *tmp;
3162 struct pnv_phb *phb;
3163 char name[16];
3164
3165 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
3166 phb = hose->private_data;
3167
3168
3169 phb->initialized = 1;
3170
3171 sprintf(name, "PCI%04x", hose->global_number);
3172 phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root);
3173 if (!phb->dbgfs) {
3174 pr_warn("%s: Error on creating debugfs on PHB#%x\n",
3175 __func__, hose->global_number);
3176 continue;
3177 }
3178
3179 debugfs_create_file("dump_diag_regs", 0200, phb->dbgfs, hose,
3180 &pnv_pci_diag_data_fops);
3181 }
3182#endif
3183}
3184
3185static void pnv_pci_enable_bridge(struct pci_bus *bus)
3186{
3187 struct pci_dev *dev = bus->self;
3188 struct pci_bus *child;
3189
3190
3191 if (list_empty(&bus->devices))
3192 return;
3193
3194
3195
3196
3197
3198
3199
3200 if (dev) {
3201 int rc = pci_enable_device(dev);
3202 if (rc)
3203 pci_err(dev, "Error enabling bridge (%d)\n", rc);
3204 pci_set_master(dev);
3205 }
3206
3207
3208 list_for_each_entry(child, &bus->children, node)
3209 pnv_pci_enable_bridge(child);
3210}
3211
3212static void pnv_pci_enable_bridges(void)
3213{
3214 struct pci_controller *hose;
3215
3216 list_for_each_entry(hose, &hose_list, list_node)
3217 pnv_pci_enable_bridge(hose->bus);
3218}
3219
3220static void pnv_pci_ioda_fixup(void)
3221{
3222 pnv_pci_ioda_setup_PEs();
3223 pnv_pci_ioda_setup_iommu_api();
3224 pnv_pci_ioda_create_dbgfs();
3225
3226 pnv_pci_enable_bridges();
3227
3228#ifdef CONFIG_EEH
3229 pnv_eeh_post_init();
3230#endif
3231}
3232
3233
3234
3235
3236
3237
3238
3239
3240
3241
3242
3243
3244
3245static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus,
3246 unsigned long type)
3247{
3248 struct pci_dev *bridge;
3249 struct pci_controller *hose = pci_bus_to_host(bus);
3250 struct pnv_phb *phb = hose->private_data;
3251 int num_pci_bridges = 0;
3252
3253 bridge = bus->self;
3254 while (bridge) {
3255 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) {
3256 num_pci_bridges++;
3257 if (num_pci_bridges >= 2)
3258 return 1;
3259 }
3260
3261 bridge = bridge->bus->self;
3262 }
3263
3264
3265
3266
3267
3268
3269 if (phb->ioda.m64_segsize && pnv_pci_is_m64_flags(type))
3270 return phb->ioda.m64_segsize;
3271 if (type & IORESOURCE_MEM)
3272 return phb->ioda.m32_segsize;
3273
3274 return phb->ioda.io_segsize;
3275}
3276
3277
3278
3279
3280
3281
3282
3283
3284
3285static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus,
3286 unsigned long type)
3287{
3288 struct pci_controller *hose = pci_bus_to_host(bus);
3289 struct pnv_phb *phb = hose->private_data;
3290 struct pci_dev *bridge = bus->self;
3291 struct resource *r, *w;
3292 bool msi_region = false;
3293 int i;
3294
3295
3296 if (!pci_is_root_bus(bridge->bus) &&
3297 !pci_is_root_bus(bridge->bus->self->bus))
3298 return;
3299
3300
3301 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
3302 r = &bridge->resource[PCI_BRIDGE_RESOURCES + i];
3303 if (!r->flags || !r->parent)
3304 continue;
3305
3306 w = NULL;
3307 if (r->flags & type & IORESOURCE_IO)
3308 w = &hose->io_resource;
3309 else if (pnv_pci_is_m64(phb, r) &&
3310 (type & IORESOURCE_PREFETCH) &&
3311 phb->ioda.m64_segsize)
3312 w = &hose->mem_resources[1];
3313 else if (r->flags & type & IORESOURCE_MEM) {
3314 w = &hose->mem_resources[0];
3315 msi_region = true;
3316 }
3317
3318 r->start = w->start;
3319 r->end = w->end;
3320
3321
3322
3323
3324
3325
3326
3327
3328 if (msi_region) {
3329 r->end += 0x10000;
3330 r->end -= 0x100000;
3331 }
3332 }
3333}
3334
3335static void pnv_pci_setup_bridge(struct pci_bus *bus, unsigned long type)
3336{
3337 struct pci_controller *hose = pci_bus_to_host(bus);
3338 struct pnv_phb *phb = hose->private_data;
3339 struct pci_dev *bridge = bus->self;
3340 struct pnv_ioda_pe *pe;
3341 bool all = (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE);
3342
3343
3344 pnv_pci_fixup_bridge_resources(bus, type);
3345
3346
3347 if (!phb->ioda.root_pe_populated) {
3348 pe = pnv_ioda_setup_bus_PE(phb->hose->bus, false);
3349 if (pe) {
3350 phb->ioda.root_pe_idx = pe->pe_number;
3351 phb->ioda.root_pe_populated = true;
3352 }
3353 }
3354
3355
3356 if (list_empty(&bus->devices))
3357 return;
3358
3359
3360 pnv_ioda_reserve_m64_pe(bus, NULL, all);
3361
3362
3363
3364
3365
3366
3367 pe = pnv_ioda_setup_bus_PE(bus, all);
3368 if (!pe)
3369 return;
3370
3371 pnv_ioda_setup_pe_seg(pe);
3372 switch (phb->type) {
3373 case PNV_PHB_IODA1:
3374 pnv_pci_ioda1_setup_dma_pe(phb, pe);
3375 break;
3376 case PNV_PHB_IODA2:
3377 pnv_pci_ioda2_setup_dma_pe(phb, pe);
3378 break;
3379 default:
3380 pr_warn("%s: No DMA for PHB#%x (type %d)\n",
3381 __func__, phb->hose->global_number, phb->type);
3382 }
3383}
3384
3385static resource_size_t pnv_pci_default_alignment(void)
3386{
3387 return PAGE_SIZE;
3388}
3389
3390#ifdef CONFIG_PCI_IOV
3391static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev,
3392 int resno)
3393{
3394 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
3395 struct pnv_phb *phb = hose->private_data;
3396 struct pci_dn *pdn = pci_get_pdn(pdev);
3397 resource_size_t align;
3398
3399
3400
3401
3402
3403
3404
3405
3406
3407
3408
3409
3410
3411
3412
3413
3414
3415
3416 align = pci_iov_resource_size(pdev, resno);
3417 if (!pdn->vfs_expanded)
3418 return align;
3419 if (pdn->m64_single_mode)
3420 return max(align, (resource_size_t)phb->ioda.m64_segsize);
3421
3422 return pdn->vfs_expanded * align;
3423}
3424#endif
3425
3426
3427
3428
3429static bool pnv_pci_enable_device_hook(struct pci_dev *dev)
3430{
3431 struct pci_controller *hose = pci_bus_to_host(dev->bus);
3432 struct pnv_phb *phb = hose->private_data;
3433 struct pci_dn *pdn;
3434
3435
3436
3437
3438
3439
3440 if (!phb->initialized)
3441 return true;
3442
3443 pdn = pci_get_pdn(dev);
3444 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
3445 return false;
3446
3447 return true;
3448}
3449
3450static long pnv_pci_ioda1_unset_window(struct iommu_table_group *table_group,
3451 int num)
3452{
3453 struct pnv_ioda_pe *pe = container_of(table_group,
3454 struct pnv_ioda_pe, table_group);
3455 struct pnv_phb *phb = pe->phb;
3456 unsigned int idx;
3457 long rc;
3458
3459 pe_info(pe, "Removing DMA window #%d\n", num);
3460 for (idx = 0; idx < phb->ioda.dma32_count; idx++) {
3461 if (phb->ioda.dma32_segmap[idx] != pe->pe_number)
3462 continue;
3463
3464 rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
3465 idx, 0, 0ul, 0ul, 0ul);
3466 if (rc != OPAL_SUCCESS) {
3467 pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n",
3468 rc, idx);
3469 return rc;
3470 }
3471
3472 phb->ioda.dma32_segmap[idx] = IODA_INVALID_PE;
3473 }
3474
3475 pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
3476 return OPAL_SUCCESS;
3477}
3478
3479static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe)
3480{
3481 unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe);
3482 struct iommu_table *tbl = pe->table_group.tables[0];
3483 int64_t rc;
3484
3485 if (!weight)
3486 return;
3487
3488 rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0);
3489 if (rc != OPAL_SUCCESS)
3490 return;
3491
3492 pnv_pci_p7ioc_tce_invalidate(tbl, tbl->it_offset, tbl->it_size, false);
3493 if (pe->table_group.group) {
3494 iommu_group_put(pe->table_group.group);
3495 WARN_ON(pe->table_group.group);
3496 }
3497
3498 free_pages(tbl->it_base, get_order(tbl->it_size << 3));
3499 iommu_tce_table_put(tbl);
3500}
3501
3502static void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe)
3503{
3504 struct iommu_table *tbl = pe->table_group.tables[0];
3505 unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe);
3506#ifdef CONFIG_IOMMU_API
3507 int64_t rc;
3508#endif
3509
3510 if (!weight)
3511 return;
3512
3513#ifdef CONFIG_IOMMU_API
3514 rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
3515 if (rc)
3516 pe_warn(pe, "OPAL error %ld release DMA window\n", rc);
3517#endif
3518
3519 pnv_pci_ioda2_set_bypass(pe, false);
3520 if (pe->table_group.group) {
3521 iommu_group_put(pe->table_group.group);
3522 WARN_ON(pe->table_group.group);
3523 }
3524
3525 iommu_tce_table_put(tbl);
3526}
3527
3528static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe,
3529 unsigned short win,
3530 unsigned int *map)
3531{
3532 struct pnv_phb *phb = pe->phb;
3533 int idx;
3534 int64_t rc;
3535
3536 for (idx = 0; idx < phb->ioda.total_pe_num; idx++) {
3537 if (map[idx] != pe->pe_number)
3538 continue;
3539
3540 if (win == OPAL_M64_WINDOW_TYPE)
3541 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3542 phb->ioda.reserved_pe_idx, win,
3543 idx / PNV_IODA1_M64_SEGS,
3544 idx % PNV_IODA1_M64_SEGS);
3545 else
3546 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3547 phb->ioda.reserved_pe_idx, win, 0, idx);
3548
3549 if (rc != OPAL_SUCCESS)
3550 pe_warn(pe, "Error %ld unmapping (%d) segment#%d\n",
3551 rc, win, idx);
3552
3553 map[idx] = IODA_INVALID_PE;
3554 }
3555}
3556
3557static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe)
3558{
3559 struct pnv_phb *phb = pe->phb;
3560
3561 if (phb->type == PNV_PHB_IODA1) {
3562 pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE,
3563 phb->ioda.io_segmap);
3564 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,
3565 phb->ioda.m32_segmap);
3566 pnv_ioda_free_pe_seg(pe, OPAL_M64_WINDOW_TYPE,
3567 phb->ioda.m64_segmap);
3568 } else if (phb->type == PNV_PHB_IODA2) {
3569 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,
3570 phb->ioda.m32_segmap);
3571 }
3572}
3573
3574static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe)
3575{
3576 struct pnv_phb *phb = pe->phb;
3577 struct pnv_ioda_pe *slave, *tmp;
3578
3579 list_del(&pe->list);
3580 switch (phb->type) {
3581 case PNV_PHB_IODA1:
3582 pnv_pci_ioda1_release_pe_dma(pe);
3583 break;
3584 case PNV_PHB_IODA2:
3585 pnv_pci_ioda2_release_pe_dma(pe);
3586 break;
3587 default:
3588 WARN_ON(1);
3589 }
3590
3591 pnv_ioda_release_pe_seg(pe);
3592 pnv_ioda_deconfigure_pe(pe->phb, pe);
3593
3594
3595 if (pe->flags & PNV_IODA_PE_MASTER) {
3596 list_for_each_entry_safe(slave, tmp, &pe->slaves, list) {
3597 list_del(&slave->list);
3598 pnv_ioda_free_pe(slave);
3599 }
3600 }
3601
3602
3603
3604
3605
3606
3607
3608 if (phb->ioda.root_pe_populated &&
3609 phb->ioda.root_pe_idx == pe->pe_number)
3610 phb->ioda.root_pe_populated = false;
3611 else
3612 pnv_ioda_free_pe(pe);
3613}
3614
3615static void pnv_pci_release_device(struct pci_dev *pdev)
3616{
3617 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
3618 struct pnv_phb *phb = hose->private_data;
3619 struct pci_dn *pdn = pci_get_pdn(pdev);
3620 struct pnv_ioda_pe *pe;
3621
3622 if (pdev->is_virtfn)
3623 return;
3624
3625 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
3626 return;
3627
3628
3629
3630
3631
3632
3633
3634
3635
3636 pe = &phb->ioda.pe_array[pdn->pe_number];
3637 pdn->pe_number = IODA_INVALID_PE;
3638
3639 WARN_ON(--pe->device_count < 0);
3640 if (pe->device_count == 0)
3641 pnv_ioda_release_pe(pe);
3642}
3643
3644static void pnv_npu_disable_device(struct pci_dev *pdev)
3645{
3646 struct eeh_dev *edev = pci_dev_to_eeh_dev(pdev);
3647 struct eeh_pe *eehpe = edev ? edev->pe : NULL;
3648
3649 if (eehpe && eeh_ops && eeh_ops->reset)
3650 eeh_ops->reset(eehpe, EEH_RESET_HOT);
3651}
3652
3653static void pnv_pci_ioda_shutdown(struct pci_controller *hose)
3654{
3655 struct pnv_phb *phb = hose->private_data;
3656
3657 opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE,
3658 OPAL_ASSERT_RESET);
3659}
3660
3661static const struct pci_controller_ops pnv_pci_ioda_controller_ops = {
3662 .dma_dev_setup = pnv_pci_dma_dev_setup,
3663 .dma_bus_setup = pnv_pci_dma_bus_setup,
3664 .setup_msi_irqs = pnv_setup_msi_irqs,
3665 .teardown_msi_irqs = pnv_teardown_msi_irqs,
3666 .enable_device_hook = pnv_pci_enable_device_hook,
3667 .release_device = pnv_pci_release_device,
3668 .window_alignment = pnv_pci_window_alignment,
3669 .setup_bridge = pnv_pci_setup_bridge,
3670 .reset_secondary_bus = pnv_pci_reset_secondary_bus,
3671 .dma_set_mask = pnv_pci_ioda_dma_set_mask,
3672 .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask,
3673 .shutdown = pnv_pci_ioda_shutdown,
3674};
3675
3676static int pnv_npu_dma_set_mask(struct pci_dev *npdev, u64 dma_mask)
3677{
3678 dev_err_once(&npdev->dev,
3679 "%s operation unsupported for NVLink devices\n",
3680 __func__);
3681 return -EPERM;
3682}
3683
3684static const struct pci_controller_ops pnv_npu_ioda_controller_ops = {
3685 .dma_dev_setup = pnv_pci_dma_dev_setup,
3686 .setup_msi_irqs = pnv_setup_msi_irqs,
3687 .teardown_msi_irqs = pnv_teardown_msi_irqs,
3688 .enable_device_hook = pnv_pci_enable_device_hook,
3689 .window_alignment = pnv_pci_window_alignment,
3690 .reset_secondary_bus = pnv_pci_reset_secondary_bus,
3691 .dma_set_mask = pnv_npu_dma_set_mask,
3692 .shutdown = pnv_pci_ioda_shutdown,
3693 .disable_device = pnv_npu_disable_device,
3694};
3695
3696static const struct pci_controller_ops pnv_npu_ocapi_ioda_controller_ops = {
3697 .enable_device_hook = pnv_pci_enable_device_hook,
3698 .window_alignment = pnv_pci_window_alignment,
3699 .reset_secondary_bus = pnv_pci_reset_secondary_bus,
3700 .shutdown = pnv_pci_ioda_shutdown,
3701};
3702
3703static void __init pnv_pci_init_ioda_phb(struct device_node *np,
3704 u64 hub_id, int ioda_type)
3705{
3706 struct pci_controller *hose;
3707 struct pnv_phb *phb;
3708 unsigned long size, m64map_off, m32map_off, pemap_off;
3709 unsigned long iomap_off = 0, dma32map_off = 0;
3710 struct resource r;
3711 const __be64 *prop64;
3712 const __be32 *prop32;
3713 int len;
3714 unsigned int segno;
3715 u64 phb_id;
3716 void *aux;
3717 long rc;
3718
3719 if (!of_device_is_available(np))
3720 return;
3721
3722 pr_info("Initializing %s PHB (%pOF)\n", pnv_phb_names[ioda_type], np);
3723
3724 prop64 = of_get_property(np, "ibm,opal-phbid", NULL);
3725 if (!prop64) {
3726 pr_err(" Missing \"ibm,opal-phbid\" property !\n");
3727 return;
3728 }
3729 phb_id = be64_to_cpup(prop64);
3730 pr_debug(" PHB-ID : 0x%016llx\n", phb_id);
3731
3732 phb = memblock_alloc(sizeof(*phb), SMP_CACHE_BYTES);
3733
3734
3735 phb->hose = hose = pcibios_alloc_controller(np);
3736 if (!phb->hose) {
3737 pr_err(" Can't allocate PCI controller for %pOF\n",
3738 np);
3739 memblock_free(__pa(phb), sizeof(struct pnv_phb));
3740 return;
3741 }
3742
3743 spin_lock_init(&phb->lock);
3744 prop32 = of_get_property(np, "bus-range", &len);
3745 if (prop32 && len == 8) {
3746 hose->first_busno = be32_to_cpu(prop32[0]);
3747 hose->last_busno = be32_to_cpu(prop32[1]);
3748 } else {
3749 pr_warn(" Broken <bus-range> on %pOF\n", np);
3750 hose->first_busno = 0;
3751 hose->last_busno = 0xff;
3752 }
3753 hose->private_data = phb;
3754 phb->hub_id = hub_id;
3755 phb->opal_id = phb_id;
3756 phb->type = ioda_type;
3757 mutex_init(&phb->ioda.pe_alloc_mutex);
3758
3759
3760 if (of_device_is_compatible(np, "ibm,p7ioc-pciex"))
3761 phb->model = PNV_PHB_MODEL_P7IOC;
3762 else if (of_device_is_compatible(np, "ibm,power8-pciex"))
3763 phb->model = PNV_PHB_MODEL_PHB3;
3764 else if (of_device_is_compatible(np, "ibm,power8-npu-pciex"))
3765 phb->model = PNV_PHB_MODEL_NPU;
3766 else if (of_device_is_compatible(np, "ibm,power9-npu-pciex"))
3767 phb->model = PNV_PHB_MODEL_NPU2;
3768 else
3769 phb->model = PNV_PHB_MODEL_UNKNOWN;
3770
3771
3772 prop32 = of_get_property(np, "ibm,phb-diag-data-size", NULL);
3773 if (prop32)
3774 phb->diag_data_size = be32_to_cpup(prop32);
3775 else
3776 phb->diag_data_size = PNV_PCI_DIAG_BUF_SIZE;
3777
3778 phb->diag_data = memblock_alloc(phb->diag_data_size, SMP_CACHE_BYTES);
3779
3780
3781 pci_process_bridge_OF_ranges(hose, np, !hose->global_number);
3782
3783
3784 if (!of_address_to_resource(np, 0, &r)) {
3785 phb->regs_phys = r.start;
3786 phb->regs = ioremap(r.start, resource_size(&r));
3787 if (phb->regs == NULL)
3788 pr_err(" Failed to map registers !\n");
3789 }
3790
3791
3792 phb->ioda.total_pe_num = 1;
3793 prop32 = of_get_property(np, "ibm,opal-num-pes", NULL);
3794 if (prop32)
3795 phb->ioda.total_pe_num = be32_to_cpup(prop32);
3796 prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL);
3797 if (prop32)
3798 phb->ioda.reserved_pe_idx = be32_to_cpup(prop32);
3799
3800
3801 for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++)
3802 phb->ioda.pe_rmap[segno] = IODA_INVALID_PE;
3803
3804
3805 pnv_ioda_parse_m64_window(phb);
3806
3807 phb->ioda.m32_size = resource_size(&hose->mem_resources[0]);
3808
3809 phb->ioda.m32_size += 0x10000;
3810
3811 phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num;
3812 phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0];
3813 phb->ioda.io_size = hose->pci_io_size;
3814 phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num;
3815 phb->ioda.io_pci_base = 0;
3816
3817
3818 phb->ioda.dma32_count = phb->ioda.m32_pci_base /
3819 PNV_IODA1_DMA32_SEGSIZE;
3820
3821
3822 size = _ALIGN_UP(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8,
3823 sizeof(unsigned long));
3824 m64map_off = size;
3825 size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]);
3826 m32map_off = size;
3827 size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]);
3828 if (phb->type == PNV_PHB_IODA1) {
3829 iomap_off = size;
3830 size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]);
3831 dma32map_off = size;
3832 size += phb->ioda.dma32_count *
3833 sizeof(phb->ioda.dma32_segmap[0]);
3834 }
3835 pemap_off = size;
3836 size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe);
3837 aux = memblock_alloc(size, SMP_CACHE_BYTES);
3838 phb->ioda.pe_alloc = aux;
3839 phb->ioda.m64_segmap = aux + m64map_off;
3840 phb->ioda.m32_segmap = aux + m32map_off;
3841 for (segno = 0; segno < phb->ioda.total_pe_num; segno++) {
3842 phb->ioda.m64_segmap[segno] = IODA_INVALID_PE;
3843 phb->ioda.m32_segmap[segno] = IODA_INVALID_PE;
3844 }
3845 if (phb->type == PNV_PHB_IODA1) {
3846 phb->ioda.io_segmap = aux + iomap_off;
3847 for (segno = 0; segno < phb->ioda.total_pe_num; segno++)
3848 phb->ioda.io_segmap[segno] = IODA_INVALID_PE;
3849
3850 phb->ioda.dma32_segmap = aux + dma32map_off;
3851 for (segno = 0; segno < phb->ioda.dma32_count; segno++)
3852 phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE;
3853 }
3854 phb->ioda.pe_array = aux + pemap_off;
3855
3856
3857
3858
3859
3860
3861 pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx);
3862 if (phb->ioda.reserved_pe_idx == 0) {
3863 phb->ioda.root_pe_idx = 1;
3864 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx);
3865 } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) {
3866 phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1;
3867 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx);
3868 } else {
3869 phb->ioda.root_pe_idx = IODA_INVALID_PE;
3870 }
3871
3872 INIT_LIST_HEAD(&phb->ioda.pe_list);
3873 mutex_init(&phb->ioda.pe_list_mutex);
3874
3875
3876 phb->ioda.dma32_count = phb->ioda.m32_pci_base /
3877 PNV_IODA1_DMA32_SEGSIZE;
3878
3879#if 0
3880 rc = opal_pci_set_phb_mem_window(opal->phb_id,
3881 window_type,
3882 window_num,
3883 starting_real_address,
3884 starting_pci_address,
3885 segment_size);
3886#endif
3887
3888 pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n",
3889 phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx,
3890 phb->ioda.m32_size, phb->ioda.m32_segsize);
3891 if (phb->ioda.m64_size)
3892 pr_info(" M64: 0x%lx [segment=0x%lx]\n",
3893 phb->ioda.m64_size, phb->ioda.m64_segsize);
3894 if (phb->ioda.io_size)
3895 pr_info(" IO: 0x%x [segment=0x%x]\n",
3896 phb->ioda.io_size, phb->ioda.io_segsize);
3897
3898
3899 phb->hose->ops = &pnv_pci_ops;
3900 phb->get_pe_state = pnv_ioda_get_pe_state;
3901 phb->freeze_pe = pnv_ioda_freeze_pe;
3902 phb->unfreeze_pe = pnv_ioda_unfreeze_pe;
3903
3904
3905 pnv_pci_init_ioda_msis(phb);
3906
3907
3908
3909
3910
3911
3912
3913
3914 ppc_md.pcibios_fixup = pnv_pci_ioda_fixup;
3915
3916 switch (phb->type) {
3917 case PNV_PHB_NPU_NVLINK:
3918 hose->controller_ops = pnv_npu_ioda_controller_ops;
3919 break;
3920 case PNV_PHB_NPU_OCAPI:
3921 hose->controller_ops = pnv_npu_ocapi_ioda_controller_ops;
3922 break;
3923 default:
3924 phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup;
3925 hose->controller_ops = pnv_pci_ioda_controller_ops;
3926 }
3927
3928 ppc_md.pcibios_default_alignment = pnv_pci_default_alignment;
3929
3930#ifdef CONFIG_PCI_IOV
3931 ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources;
3932 ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment;
3933 ppc_md.pcibios_sriov_enable = pnv_pcibios_sriov_enable;
3934 ppc_md.pcibios_sriov_disable = pnv_pcibios_sriov_disable;
3935#endif
3936
3937 pci_add_flags(PCI_REASSIGN_ALL_RSRC);
3938
3939
3940 rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET);
3941 if (rc)
3942 pr_warn(" OPAL Error %ld performing IODA table reset !\n", rc);
3943
3944
3945
3946
3947
3948
3949
3950
3951 if (is_kdump_kernel() || pci_reset_phbs) {
3952 pr_info(" Issue PHB reset ...\n");
3953 pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL);
3954 pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE);
3955 }
3956
3957
3958 if (!phb->init_m64 || phb->init_m64(phb))
3959 hose->mem_resources[1].flags = 0;
3960}
3961
3962void __init pnv_pci_init_ioda2_phb(struct device_node *np)
3963{
3964 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2);
3965}
3966
3967void __init pnv_pci_init_npu_phb(struct device_node *np)
3968{
3969 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_NVLINK);
3970}
3971
3972void __init pnv_pci_init_npu2_opencapi_phb(struct device_node *np)
3973{
3974 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_OCAPI);
3975}
3976
3977static void pnv_npu2_opencapi_cfg_size_fixup(struct pci_dev *dev)
3978{
3979 struct pci_controller *hose = pci_bus_to_host(dev->bus);
3980 struct pnv_phb *phb = hose->private_data;
3981
3982 if (!machine_is(powernv))
3983 return;
3984
3985 if (phb->type == PNV_PHB_NPU_OCAPI)
3986 dev->cfg_size = PCI_CFG_SPACE_EXP_SIZE;
3987}
3988DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, pnv_npu2_opencapi_cfg_size_fixup);
3989
3990void __init pnv_pci_init_ioda_hub(struct device_node *np)
3991{
3992 struct device_node *phbn;
3993 const __be64 *prop64;
3994 u64 hub_id;
3995
3996 pr_info("Probing IODA IO-Hub %pOF\n", np);
3997
3998 prop64 = of_get_property(np, "ibm,opal-hubid", NULL);
3999 if (!prop64) {
4000 pr_err(" Missing \"ibm,opal-hubid\" property !\n");
4001 return;
4002 }
4003 hub_id = be64_to_cpup(prop64);
4004 pr_devel(" HUB-ID : 0x%016llx\n", hub_id);
4005
4006
4007 for_each_child_of_node(np, phbn) {
4008
4009 if (of_device_is_compatible(phbn, "ibm,ioda-phb"))
4010 pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1);
4011 }
4012}
4013