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10#include <linux/cpumask.h>
11#include <linux/hardirq.h>
12#include <linux/proc_fs.h>
13#include <linux/threads.h>
14#include <linux/kernel.h>
15#include <linux/export.h>
16#include <linux/string.h>
17#include <linux/ctype.h>
18#include <linux/sched.h>
19#include <linux/timer.h>
20#include <linux/slab.h>
21#include <linux/cpu.h>
22#include <linux/init.h>
23#include <linux/io.h>
24#include <linux/pci.h>
25#include <linux/kdebug.h>
26#include <linux/delay.h>
27#include <linux/crash_dump.h>
28#include <linux/reboot.h>
29#include <linux/memory.h>
30
31#include <asm/uv/uv_mmrs.h>
32#include <asm/uv/uv_hub.h>
33#include <asm/current.h>
34#include <asm/pgtable.h>
35#include <asm/uv/bios.h>
36#include <asm/uv/uv.h>
37#include <asm/apic.h>
38#include <asm/e820/api.h>
39#include <asm/ipi.h>
40#include <asm/smp.h>
41#include <asm/x86_init.h>
42#include <asm/nmi.h>
43
44DEFINE_PER_CPU(int, x2apic_extra_bits);
45
46static enum uv_system_type uv_system_type;
47static bool uv_hubless_system;
48static u64 gru_start_paddr, gru_end_paddr;
49static u64 gru_dist_base, gru_first_node_paddr = -1LL, gru_last_node_paddr;
50static u64 gru_dist_lmask, gru_dist_umask;
51static union uvh_apicid uvh_apicid;
52
53
54static struct {
55 unsigned int apicid_shift;
56 unsigned int apicid_mask;
57 unsigned int socketid_shift;
58 unsigned int pnode_mask;
59 unsigned int gpa_shift;
60 unsigned int gnode_shift;
61} uv_cpuid;
62
63int uv_min_hub_revision_id;
64EXPORT_SYMBOL_GPL(uv_min_hub_revision_id);
65
66unsigned int uv_apicid_hibits;
67EXPORT_SYMBOL_GPL(uv_apicid_hibits);
68
69static struct apic apic_x2apic_uv_x;
70static struct uv_hub_info_s uv_hub_info_node0;
71
72
73static int disable_uv_undefined_panic = 1;
74
75unsigned long uv_undefined(char *str)
76{
77 if (likely(!disable_uv_undefined_panic))
78 panic("UV: error: undefined MMR: %s\n", str);
79 else
80 pr_crit("UV: error: undefined MMR: %s\n", str);
81
82
83 return ~0ul;
84}
85EXPORT_SYMBOL(uv_undefined);
86
87static unsigned long __init uv_early_read_mmr(unsigned long addr)
88{
89 unsigned long val, *mmr;
90
91 mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, sizeof(*mmr));
92 val = *mmr;
93 early_iounmap(mmr, sizeof(*mmr));
94
95 return val;
96}
97
98static inline bool is_GRU_range(u64 start, u64 end)
99{
100 if (gru_dist_base) {
101 u64 su = start & gru_dist_umask;
102 u64 sl = start & gru_dist_lmask;
103 u64 eu = end & gru_dist_umask;
104 u64 el = end & gru_dist_lmask;
105
106
107 return (sl == gru_dist_base && el == gru_dist_base &&
108 su >= gru_first_node_paddr &&
109 su <= gru_last_node_paddr &&
110 eu == su);
111 } else {
112 return start >= gru_start_paddr && end <= gru_end_paddr;
113 }
114}
115
116static bool uv_is_untracked_pat_range(u64 start, u64 end)
117{
118 return is_ISA_range(start, end) || is_GRU_range(start, end);
119}
120
121static int __init early_get_pnodeid(void)
122{
123 union uvh_node_id_u node_id;
124 union uvh_rh_gam_config_mmr_u m_n_config;
125 int pnode;
126
127
128 node_id.v = uv_early_read_mmr(UVH_NODE_ID);
129 m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_CONFIG_MMR);
130 uv_min_hub_revision_id = node_id.s.revision;
131
132 switch (node_id.s.part_number) {
133 case UV2_HUB_PART_NUMBER:
134 case UV2_HUB_PART_NUMBER_X:
135 uv_min_hub_revision_id += UV2_HUB_REVISION_BASE - 1;
136 break;
137 case UV3_HUB_PART_NUMBER:
138 case UV3_HUB_PART_NUMBER_X:
139 uv_min_hub_revision_id += UV3_HUB_REVISION_BASE;
140 break;
141
142
143 case UV4_HUB_PART_NUMBER:
144 uv_min_hub_revision_id += UV4_HUB_REVISION_BASE - 1;
145 uv_cpuid.gnode_shift = 2;
146 break;
147 }
148
149 uv_hub_info->hub_revision = uv_min_hub_revision_id;
150 uv_cpuid.pnode_mask = (1 << m_n_config.s.n_skt) - 1;
151 pnode = (node_id.s.node_id >> 1) & uv_cpuid.pnode_mask;
152 uv_cpuid.gpa_shift = 46;
153
154 pr_info("UV: rev:%d part#:%x nodeid:%04x n_skt:%d pnmsk:%x pn:%x\n",
155 node_id.s.revision, node_id.s.part_number, node_id.s.node_id,
156 m_n_config.s.n_skt, uv_cpuid.pnode_mask, pnode);
157 return pnode;
158}
159
160static void __init uv_tsc_check_sync(void)
161{
162 u64 mmr;
163 int sync_state;
164 int mmr_shift;
165 char *state;
166 bool valid;
167
168
169 mmr = uv_early_read_mmr(UVH_TSC_SYNC_MMR);
170 mmr_shift =
171 is_uv1_hub() ? 0 :
172 is_uv2_hub() ? UVH_TSC_SYNC_SHIFT_UV2K : UVH_TSC_SYNC_SHIFT;
173 if (mmr_shift)
174 sync_state = (mmr >> mmr_shift) & UVH_TSC_SYNC_MASK;
175 else
176 sync_state = 0;
177
178 switch (sync_state) {
179 case UVH_TSC_SYNC_VALID:
180 state = "in sync";
181 valid = true;
182 break;
183
184 case UVH_TSC_SYNC_INVALID:
185 state = "unstable";
186 valid = false;
187 break;
188 default:
189 state = "unknown: assuming valid";
190 valid = true;
191 break;
192 }
193 pr_info("UV: TSC sync state from BIOS:0%d(%s)\n", sync_state, state);
194
195
196 if (valid)
197 mark_tsc_async_resets("UV BIOS");
198 else
199 mark_tsc_unstable("UV BIOS");
200}
201
202
203
204#define SMT_LEVEL 0
205#define INVALID_TYPE 0
206#define SMT_TYPE 1
207#define CORE_TYPE 2
208#define LEAFB_SUBTYPE(ecx) (((ecx) >> 8) & 0xff)
209#define BITS_SHIFT_NEXT_LEVEL(eax) ((eax) & 0x1f)
210
211static void set_x2apic_bits(void)
212{
213 unsigned int eax, ebx, ecx, edx, sub_index;
214 unsigned int sid_shift;
215
216 cpuid(0, &eax, &ebx, &ecx, &edx);
217 if (eax < 0xb) {
218 pr_info("UV: CPU does not have CPUID.11\n");
219 return;
220 }
221
222 cpuid_count(0xb, SMT_LEVEL, &eax, &ebx, &ecx, &edx);
223 if (ebx == 0 || (LEAFB_SUBTYPE(ecx) != SMT_TYPE)) {
224 pr_info("UV: CPUID.11 not implemented\n");
225 return;
226 }
227
228 sid_shift = BITS_SHIFT_NEXT_LEVEL(eax);
229 sub_index = 1;
230 do {
231 cpuid_count(0xb, sub_index, &eax, &ebx, &ecx, &edx);
232 if (LEAFB_SUBTYPE(ecx) == CORE_TYPE) {
233 sid_shift = BITS_SHIFT_NEXT_LEVEL(eax);
234 break;
235 }
236 sub_index++;
237 } while (LEAFB_SUBTYPE(ecx) != INVALID_TYPE);
238
239 uv_cpuid.apicid_shift = 0;
240 uv_cpuid.apicid_mask = (~(-1 << sid_shift));
241 uv_cpuid.socketid_shift = sid_shift;
242}
243
244static void __init early_get_apic_socketid_shift(void)
245{
246 if (is_uv2_hub() || is_uv3_hub())
247 uvh_apicid.v = uv_early_read_mmr(UVH_APICID);
248
249 set_x2apic_bits();
250
251 pr_info("UV: apicid_shift:%d apicid_mask:0x%x\n", uv_cpuid.apicid_shift, uv_cpuid.apicid_mask);
252 pr_info("UV: socketid_shift:%d pnode_mask:0x%x\n", uv_cpuid.socketid_shift, uv_cpuid.pnode_mask);
253}
254
255
256
257
258
259
260static void __init uv_set_apicid_hibit(void)
261{
262 union uv1h_lb_target_physical_apic_id_mask_u apicid_mask;
263
264 if (is_uv1_hub()) {
265 apicid_mask.v = uv_early_read_mmr(UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK);
266 uv_apicid_hibits = apicid_mask.s1.bit_enables & UV_APICID_HIBIT_MASK;
267 }
268}
269
270static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
271{
272 int pnodeid;
273 int uv_apic;
274
275 if (strncmp(oem_id, "SGI", 3) != 0) {
276 if (strncmp(oem_id, "NSGI", 4) == 0) {
277 uv_hubless_system = true;
278 pr_info("UV: OEM IDs %s/%s, HUBLESS\n",
279 oem_id, oem_table_id);
280 }
281 return 0;
282 }
283
284 if (numa_off) {
285 pr_err("UV: NUMA is off, disabling UV support\n");
286 return 0;
287 }
288
289
290 uv_cpu_info->p_uv_hub_info = &uv_hub_info_node0;
291
292
293
294
295
296
297
298
299 uv_hub_info->hub_revision =
300 !strncmp(oem_id, "SGI4", 4) ? UV4_HUB_REVISION_BASE :
301 !strncmp(oem_id, "SGI3", 4) ? UV3_HUB_REVISION_BASE :
302 !strcmp(oem_id, "SGI2") ? UV2_HUB_REVISION_BASE :
303 !strcmp(oem_id, "SGI") ? UV1_HUB_REVISION_BASE : 0;
304
305 if (uv_hub_info->hub_revision == 0)
306 goto badbios;
307
308 pnodeid = early_get_pnodeid();
309 early_get_apic_socketid_shift();
310
311 x86_platform.is_untracked_pat_range = uv_is_untracked_pat_range;
312 x86_platform.nmi_init = uv_nmi_init;
313
314 if (!strcmp(oem_table_id, "UVX")) {
315
316 uv_system_type = UV_X2APIC;
317 uv_apic = 0;
318
319 } else if (!strcmp(oem_table_id, "UVH")) {
320
321 uv_system_type = UV_NON_UNIQUE_APIC;
322 x86_platform.legacy.warm_reset = 0;
323 __this_cpu_write(x2apic_extra_bits, pnodeid << uvh_apicid.s.pnode_shift);
324 uv_set_apicid_hibit();
325 uv_apic = 1;
326
327 } else if (!strcmp(oem_table_id, "UVL")) {
328
329 uv_system_type = UV_LEGACY_APIC;
330 uv_apic = 0;
331
332 } else {
333 goto badbios;
334 }
335
336 pr_info("UV: OEM IDs %s/%s, System/HUB Types %d/%d, uv_apic %d\n", oem_id, oem_table_id, uv_system_type, uv_min_hub_revision_id, uv_apic);
337 uv_tsc_check_sync();
338
339 return uv_apic;
340
341badbios:
342 pr_err("UV: OEM_ID:%s OEM_TABLE_ID:%s\n", oem_id, oem_table_id);
343 pr_err("Current BIOS not supported, update kernel and/or BIOS\n");
344 BUG();
345}
346
347enum uv_system_type get_uv_system_type(void)
348{
349 return uv_system_type;
350}
351
352int is_uv_system(void)
353{
354 return uv_system_type != UV_NONE;
355}
356EXPORT_SYMBOL_GPL(is_uv_system);
357
358int is_uv_hubless(void)
359{
360 return uv_hubless_system;
361}
362EXPORT_SYMBOL_GPL(is_uv_hubless);
363
364void **__uv_hub_info_list;
365EXPORT_SYMBOL_GPL(__uv_hub_info_list);
366
367DEFINE_PER_CPU(struct uv_cpu_info_s, __uv_cpu_info);
368EXPORT_PER_CPU_SYMBOL_GPL(__uv_cpu_info);
369
370short uv_possible_blades;
371EXPORT_SYMBOL_GPL(uv_possible_blades);
372
373unsigned long sn_rtc_cycles_per_second;
374EXPORT_SYMBOL(sn_rtc_cycles_per_second);
375
376
377static __initdata unsigned short *_node_to_pnode;
378static __initdata unsigned short _min_socket, _max_socket;
379static __initdata unsigned short _min_pnode, _max_pnode, _gr_table_len;
380static __initdata struct uv_gam_range_entry *uv_gre_table;
381static __initdata struct uv_gam_parameters *uv_gp_table;
382static __initdata unsigned short *_socket_to_node;
383static __initdata unsigned short *_socket_to_pnode;
384static __initdata unsigned short *_pnode_to_socket;
385
386static __initdata struct uv_gam_range_s *_gr_table;
387
388#define SOCK_EMPTY ((unsigned short)~0)
389
390extern int uv_hub_info_version(void)
391{
392 return UV_HUB_INFO_VERSION;
393}
394EXPORT_SYMBOL(uv_hub_info_version);
395
396
397static unsigned long mem_block_size __initdata = (2UL << 30);
398
399
400static int __init parse_mem_block_size(char *ptr)
401{
402 unsigned long size = memparse(ptr, NULL);
403
404
405 mem_block_size = size;
406 return 0;
407}
408early_param("uv_memblksize", parse_mem_block_size);
409
410static __init int adj_blksize(u32 lgre)
411{
412 unsigned long base = (unsigned long)lgre << UV_GAM_RANGE_SHFT;
413 unsigned long size;
414
415 for (size = mem_block_size; size > MIN_MEMORY_BLOCK_SIZE; size >>= 1)
416 if (IS_ALIGNED(base, size))
417 break;
418
419 if (size >= mem_block_size)
420 return 0;
421
422 mem_block_size = size;
423 return 1;
424}
425
426static __init void set_block_size(void)
427{
428 unsigned int order = ffs(mem_block_size);
429
430 if (order) {
431
432 set_memory_block_size_order(order - 1);
433 pr_info("UV: mem_block_size set to 0x%lx\n", mem_block_size);
434 } else {
435
436 pr_err("UV: mem_block_size error with 0x%lx\n", mem_block_size);
437 set_memory_block_size_order(31);
438 }
439}
440
441
442static __init void build_uv_gr_table(void)
443{
444 struct uv_gam_range_entry *gre = uv_gre_table;
445 struct uv_gam_range_s *grt;
446 unsigned long last_limit = 0, ram_limit = 0;
447 int bytes, i, sid, lsid = -1, indx = 0, lindx = -1;
448
449 if (!gre)
450 return;
451
452 bytes = _gr_table_len * sizeof(struct uv_gam_range_s);
453 grt = kzalloc(bytes, GFP_KERNEL);
454 BUG_ON(!grt);
455 _gr_table = grt;
456
457 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
458 if (gre->type == UV_GAM_RANGE_TYPE_HOLE) {
459 if (!ram_limit) {
460
461 ram_limit = last_limit;
462 last_limit = gre->limit;
463 lsid++;
464 continue;
465 }
466 last_limit = gre->limit;
467 pr_info("UV: extra hole in GAM RE table @%d\n", (int)(gre - uv_gre_table));
468 continue;
469 }
470 if (_max_socket < gre->sockid) {
471 pr_err("UV: GAM table sockid(%d) too large(>%d) @%d\n", gre->sockid, _max_socket, (int)(gre - uv_gre_table));
472 continue;
473 }
474 sid = gre->sockid - _min_socket;
475 if (lsid < sid) {
476
477 grt = &_gr_table[indx];
478 grt->base = lindx;
479 grt->nasid = gre->nasid;
480 grt->limit = last_limit = gre->limit;
481 lsid = sid;
482 lindx = indx++;
483 continue;
484 }
485
486 if (lsid == sid && !ram_limit) {
487
488 if (grt->limit == last_limit) {
489 grt->limit = last_limit = gre->limit;
490 continue;
491 }
492 }
493
494 if (!ram_limit) {
495 grt++;
496 grt->base = lindx;
497 grt->nasid = gre->nasid;
498 grt->limit = last_limit = gre->limit;
499 continue;
500 }
501
502 grt++;
503
504 grt->base = grt - _gr_table;
505 grt->nasid = gre->nasid;
506 grt->limit = last_limit = gre->limit;
507 lsid++;
508 }
509
510
511 grt++;
512 i = grt - _gr_table;
513 if (i < _gr_table_len) {
514 void *ret;
515
516 bytes = i * sizeof(struct uv_gam_range_s);
517 ret = krealloc(_gr_table, bytes, GFP_KERNEL);
518 if (ret) {
519 _gr_table = ret;
520 _gr_table_len = i;
521 }
522 }
523
524
525 for (i = 0, grt = _gr_table; i < _gr_table_len; i++, grt++) {
526 unsigned long start, end;
527 int gb = grt->base;
528
529 start = gb < 0 ? 0 : (unsigned long)_gr_table[gb].limit << UV_GAM_RANGE_SHFT;
530 end = (unsigned long)grt->limit << UV_GAM_RANGE_SHFT;
531
532 pr_info("UV: GAM Range %2d %04x 0x%013lx-0x%013lx (%d)\n", i, grt->nasid, start, end, gb);
533 }
534}
535
536static int uv_wakeup_secondary(int phys_apicid, unsigned long start_rip)
537{
538 unsigned long val;
539 int pnode;
540
541 pnode = uv_apicid_to_pnode(phys_apicid);
542 phys_apicid |= uv_apicid_hibits;
543
544 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
545 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
546 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
547 APIC_DM_INIT;
548
549 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
550
551 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
552 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
553 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
554 APIC_DM_STARTUP;
555
556 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
557
558 return 0;
559}
560
561static void uv_send_IPI_one(int cpu, int vector)
562{
563 unsigned long apicid;
564 int pnode;
565
566 apicid = per_cpu(x86_cpu_to_apicid, cpu);
567 pnode = uv_apicid_to_pnode(apicid);
568 uv_hub_send_ipi(pnode, apicid, vector);
569}
570
571static void uv_send_IPI_mask(const struct cpumask *mask, int vector)
572{
573 unsigned int cpu;
574
575 for_each_cpu(cpu, mask)
576 uv_send_IPI_one(cpu, vector);
577}
578
579static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
580{
581 unsigned int this_cpu = smp_processor_id();
582 unsigned int cpu;
583
584 for_each_cpu(cpu, mask) {
585 if (cpu != this_cpu)
586 uv_send_IPI_one(cpu, vector);
587 }
588}
589
590static void uv_send_IPI_allbutself(int vector)
591{
592 unsigned int this_cpu = smp_processor_id();
593 unsigned int cpu;
594
595 for_each_online_cpu(cpu) {
596 if (cpu != this_cpu)
597 uv_send_IPI_one(cpu, vector);
598 }
599}
600
601static void uv_send_IPI_all(int vector)
602{
603 uv_send_IPI_mask(cpu_online_mask, vector);
604}
605
606static int uv_apic_id_valid(u32 apicid)
607{
608 return 1;
609}
610
611static int uv_apic_id_registered(void)
612{
613 return 1;
614}
615
616static void uv_init_apic_ldr(void)
617{
618}
619
620static u32 apic_uv_calc_apicid(unsigned int cpu)
621{
622 return apic_default_calc_apicid(cpu) | uv_apicid_hibits;
623}
624
625static unsigned int x2apic_get_apic_id(unsigned long x)
626{
627 unsigned int id;
628
629 WARN_ON(preemptible() && num_online_cpus() > 1);
630 id = x | __this_cpu_read(x2apic_extra_bits);
631
632 return id;
633}
634
635static u32 set_apic_id(unsigned int id)
636{
637
638 return id;
639}
640
641static unsigned int uv_read_apic_id(void)
642{
643 return x2apic_get_apic_id(apic_read(APIC_ID));
644}
645
646static int uv_phys_pkg_id(int initial_apicid, int index_msb)
647{
648 return uv_read_apic_id() >> index_msb;
649}
650
651static void uv_send_IPI_self(int vector)
652{
653 apic_write(APIC_SELF_IPI, vector);
654}
655
656static int uv_probe(void)
657{
658 return apic == &apic_x2apic_uv_x;
659}
660
661static struct apic apic_x2apic_uv_x __ro_after_init = {
662
663 .name = "UV large system",
664 .probe = uv_probe,
665 .acpi_madt_oem_check = uv_acpi_madt_oem_check,
666 .apic_id_valid = uv_apic_id_valid,
667 .apic_id_registered = uv_apic_id_registered,
668
669 .irq_delivery_mode = dest_Fixed,
670 .irq_dest_mode = 0,
671
672 .disable_esr = 0,
673 .dest_logical = APIC_DEST_LOGICAL,
674 .check_apicid_used = NULL,
675
676 .init_apic_ldr = uv_init_apic_ldr,
677
678 .ioapic_phys_id_map = NULL,
679 .setup_apic_routing = NULL,
680 .cpu_present_to_apicid = default_cpu_present_to_apicid,
681 .apicid_to_cpu_present = NULL,
682 .check_phys_apicid_present = default_check_phys_apicid_present,
683 .phys_pkg_id = uv_phys_pkg_id,
684
685 .get_apic_id = x2apic_get_apic_id,
686 .set_apic_id = set_apic_id,
687
688 .calc_dest_apicid = apic_uv_calc_apicid,
689
690 .send_IPI = uv_send_IPI_one,
691 .send_IPI_mask = uv_send_IPI_mask,
692 .send_IPI_mask_allbutself = uv_send_IPI_mask_allbutself,
693 .send_IPI_allbutself = uv_send_IPI_allbutself,
694 .send_IPI_all = uv_send_IPI_all,
695 .send_IPI_self = uv_send_IPI_self,
696
697 .wakeup_secondary_cpu = uv_wakeup_secondary,
698 .inquire_remote_apic = NULL,
699
700 .read = native_apic_msr_read,
701 .write = native_apic_msr_write,
702 .eoi_write = native_apic_msr_eoi_write,
703 .icr_read = native_x2apic_icr_read,
704 .icr_write = native_x2apic_icr_write,
705 .wait_icr_idle = native_x2apic_wait_icr_idle,
706 .safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle,
707};
708
709static void set_x2apic_extra_bits(int pnode)
710{
711 __this_cpu_write(x2apic_extra_bits, pnode << uvh_apicid.s.pnode_shift);
712}
713
714#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH 3
715#define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
716
717static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
718{
719 union uvh_rh_gam_alias210_overlay_config_2_mmr_u alias;
720 union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
721 unsigned long m_redirect;
722 unsigned long m_overlay;
723 int i;
724
725 for (i = 0; i < UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH; i++) {
726 switch (i) {
727 case 0:
728 m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR;
729 m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR;
730 break;
731 case 1:
732 m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR;
733 m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR;
734 break;
735 case 2:
736 m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR;
737 m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR;
738 break;
739 }
740 alias.v = uv_read_local_mmr(m_overlay);
741 if (alias.s.enable && alias.s.base == 0) {
742 *size = (1UL << alias.s.m_alias);
743 redirect.v = uv_read_local_mmr(m_redirect);
744 *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
745 return;
746 }
747 }
748 *base = *size = 0;
749}
750
751enum map_type {map_wb, map_uc};
752
753static __init void map_high(char *id, unsigned long base, int pshift, int bshift, int max_pnode, enum map_type map_type)
754{
755 unsigned long bytes, paddr;
756
757 paddr = base << pshift;
758 bytes = (1UL << bshift) * (max_pnode + 1);
759 if (!paddr) {
760 pr_info("UV: Map %s_HI base address NULL\n", id);
761 return;
762 }
763 pr_debug("UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr, paddr + bytes);
764 if (map_type == map_uc)
765 init_extra_mapping_uc(paddr, bytes);
766 else
767 init_extra_mapping_wb(paddr, bytes);
768}
769
770static __init void map_gru_distributed(unsigned long c)
771{
772 union uvh_rh_gam_gru_overlay_config_mmr_u gru;
773 u64 paddr;
774 unsigned long bytes;
775 int nid;
776
777 gru.v = c;
778
779
780 gru_dist_base = gru.v & 0x000007fff0000000UL;
781 if (!gru_dist_base) {
782 pr_info("UV: Map GRU_DIST base address NULL\n");
783 return;
784 }
785
786 bytes = 1UL << UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
787 gru_dist_lmask = ((1UL << uv_hub_info->m_val) - 1) & ~(bytes - 1);
788 gru_dist_umask = ~((1UL << uv_hub_info->m_val) - 1);
789 gru_dist_base &= gru_dist_lmask;
790
791 for_each_online_node(nid) {
792 paddr = ((u64)uv_node_to_pnode(nid) << uv_hub_info->m_val) |
793 gru_dist_base;
794 init_extra_mapping_wb(paddr, bytes);
795 gru_first_node_paddr = min(paddr, gru_first_node_paddr);
796 gru_last_node_paddr = max(paddr, gru_last_node_paddr);
797 }
798
799
800 gru_first_node_paddr &= gru_dist_umask;
801 gru_last_node_paddr &= gru_dist_umask;
802
803 pr_debug("UV: Map GRU_DIST base 0x%016llx 0x%016llx - 0x%016llx\n", gru_dist_base, gru_first_node_paddr, gru_last_node_paddr);
804}
805
806static __init void map_gru_high(int max_pnode)
807{
808 union uvh_rh_gam_gru_overlay_config_mmr_u gru;
809 int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
810 unsigned long mask = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK;
811 unsigned long base;
812
813 gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
814 if (!gru.s.enable) {
815 pr_info("UV: GRU disabled\n");
816 return;
817 }
818
819
820 if (is_uv3_hub() && gru.s3.mode) {
821 map_gru_distributed(gru.v);
822 return;
823 }
824
825 base = (gru.v & mask) >> shift;
826 map_high("GRU", base, shift, shift, max_pnode, map_wb);
827 gru_start_paddr = ((u64)base << shift);
828 gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1);
829}
830
831static __init void map_mmr_high(int max_pnode)
832{
833 union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
834 int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
835
836 mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
837 if (mmr.s.enable)
838 map_high("MMR", mmr.s.base, shift, shift, max_pnode, map_uc);
839 else
840 pr_info("UV: MMR disabled\n");
841}
842
843
844static __init void map_mmioh_high_uv34(int index, int min_pnode, int max_pnode)
845{
846 unsigned long overlay;
847 unsigned long mmr;
848 unsigned long base;
849 unsigned long nasid_mask;
850 unsigned long m_overlay;
851 int i, n, shift, m_io, max_io;
852 int nasid, lnasid, fi, li;
853 char *id;
854
855 if (index == 0) {
856 id = "MMIOH0";
857 m_overlay = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR;
858 overlay = uv_read_local_mmr(m_overlay);
859 base = overlay & UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_MASK;
860 mmr = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR;
861 m_io = (overlay & UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_MASK)
862 >> UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_SHFT;
863 shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_SHFT;
864 n = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH;
865 nasid_mask = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_MASK;
866 } else {
867 id = "MMIOH1";
868 m_overlay = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR;
869 overlay = uv_read_local_mmr(m_overlay);
870 base = overlay & UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_MASK;
871 mmr = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR;
872 m_io = (overlay & UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_MASK)
873 >> UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_SHFT;
874 shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_SHFT;
875 n = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH;
876 nasid_mask = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_MASK;
877 }
878 pr_info("UV: %s overlay 0x%lx base:0x%lx m_io:%d\n", id, overlay, base, m_io);
879 if (!(overlay & UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_MASK)) {
880 pr_info("UV: %s disabled\n", id);
881 return;
882 }
883
884
885 min_pnode *= 2;
886 max_pnode *= 2;
887 max_io = lnasid = fi = li = -1;
888
889 for (i = 0; i < n; i++) {
890 unsigned long m_redirect = mmr + i * 8;
891 unsigned long redirect = uv_read_local_mmr(m_redirect);
892
893 nasid = redirect & nasid_mask;
894 if (i == 0)
895 pr_info("UV: %s redirect base 0x%lx(@0x%lx) 0x%04x\n",
896 id, redirect, m_redirect, nasid);
897
898
899 if (nasid < min_pnode || max_pnode < nasid)
900 nasid = -1;
901
902 if (nasid == lnasid) {
903 li = i;
904
905 if (i != n-1)
906 continue;
907 }
908
909
910 if (lnasid != -1 || (i == n-1 && nasid != -1)) {
911 unsigned long addr1, addr2;
912 int f, l;
913
914 if (lnasid == -1) {
915 f = l = i;
916 lnasid = nasid;
917 } else {
918 f = fi;
919 l = li;
920 }
921 addr1 = (base << shift) + f * (1ULL << m_io);
922 addr2 = (base << shift) + (l + 1) * (1ULL << m_io);
923 pr_info("UV: %s[%03d..%03d] NASID 0x%04x ADDR 0x%016lx - 0x%016lx\n", id, fi, li, lnasid, addr1, addr2);
924 if (max_io < l)
925 max_io = l;
926 }
927 fi = li = i;
928 lnasid = nasid;
929 }
930
931 pr_info("UV: %s base:0x%lx shift:%d M_IO:%d MAX_IO:%d\n", id, base, shift, m_io, max_io);
932
933 if (max_io >= 0)
934 map_high(id, base, shift, m_io, max_io, map_uc);
935}
936
937static __init void map_mmioh_high(int min_pnode, int max_pnode)
938{
939 union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
940 unsigned long mmr, base;
941 int shift, enable, m_io, n_io;
942
943 if (is_uv3_hub() || is_uv4_hub()) {
944
945 map_mmioh_high_uv34(0, min_pnode, max_pnode);
946 map_mmioh_high_uv34(1, min_pnode, max_pnode);
947 return;
948 }
949
950 if (is_uv1_hub()) {
951 mmr = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR;
952 shift = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
953 mmioh.v = uv_read_local_mmr(mmr);
954 enable = !!mmioh.s1.enable;
955 base = mmioh.s1.base;
956 m_io = mmioh.s1.m_io;
957 n_io = mmioh.s1.n_io;
958 } else if (is_uv2_hub()) {
959 mmr = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR;
960 shift = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
961 mmioh.v = uv_read_local_mmr(mmr);
962 enable = !!mmioh.s2.enable;
963 base = mmioh.s2.base;
964 m_io = mmioh.s2.m_io;
965 n_io = mmioh.s2.n_io;
966 } else {
967 return;
968 }
969
970 if (enable) {
971 max_pnode &= (1 << n_io) - 1;
972 pr_info("UV: base:0x%lx shift:%d N_IO:%d M_IO:%d max_pnode:0x%x\n", base, shift, m_io, n_io, max_pnode);
973 map_high("MMIOH", base, shift, m_io, max_pnode, map_uc);
974 } else {
975 pr_info("UV: MMIOH disabled\n");
976 }
977}
978
979static __init void map_low_mmrs(void)
980{
981 init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
982 init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
983}
984
985static __init void uv_rtc_init(void)
986{
987 long status;
988 u64 ticks_per_sec;
989
990 status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK, &ticks_per_sec);
991
992 if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
993 pr_warn("UV: unable to determine platform RTC clock frequency, guessing.\n");
994
995
996 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
997 } else {
998 sn_rtc_cycles_per_second = ticks_per_sec;
999 }
1000}
1001
1002
1003
1004
1005static void uv_heartbeat(struct timer_list *timer)
1006{
1007 unsigned char bits = uv_scir_info->state;
1008
1009
1010 bits ^= SCIR_CPU_HEARTBEAT;
1011
1012
1013 if (idle_cpu(raw_smp_processor_id()))
1014 bits &= ~SCIR_CPU_ACTIVITY;
1015 else
1016 bits |= SCIR_CPU_ACTIVITY;
1017
1018
1019 uv_set_scir_bits(bits);
1020
1021
1022 mod_timer(timer, jiffies + SCIR_CPU_HB_INTERVAL);
1023}
1024
1025static int uv_heartbeat_enable(unsigned int cpu)
1026{
1027 while (!uv_cpu_scir_info(cpu)->enabled) {
1028 struct timer_list *timer = &uv_cpu_scir_info(cpu)->timer;
1029
1030 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY);
1031 timer_setup(timer, uv_heartbeat, TIMER_PINNED);
1032 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL;
1033 add_timer_on(timer, cpu);
1034 uv_cpu_scir_info(cpu)->enabled = 1;
1035
1036
1037 cpu = 0;
1038 }
1039 return 0;
1040}
1041
1042#ifdef CONFIG_HOTPLUG_CPU
1043static int uv_heartbeat_disable(unsigned int cpu)
1044{
1045 if (uv_cpu_scir_info(cpu)->enabled) {
1046 uv_cpu_scir_info(cpu)->enabled = 0;
1047 del_timer(&uv_cpu_scir_info(cpu)->timer);
1048 }
1049 uv_set_cpu_scir_bits(cpu, 0xff);
1050 return 0;
1051}
1052
1053static __init void uv_scir_register_cpu_notifier(void)
1054{
1055 cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "x86/x2apic-uvx:online",
1056 uv_heartbeat_enable, uv_heartbeat_disable);
1057}
1058
1059#else
1060
1061static __init void uv_scir_register_cpu_notifier(void)
1062{
1063}
1064
1065static __init int uv_init_heartbeat(void)
1066{
1067 int cpu;
1068
1069 if (is_uv_system()) {
1070 for_each_online_cpu(cpu)
1071 uv_heartbeat_enable(cpu);
1072 }
1073
1074 return 0;
1075}
1076
1077late_initcall(uv_init_heartbeat);
1078
1079#endif
1080
1081
1082static int uv_set_vga_state(struct pci_dev *pdev, bool decode, unsigned int command_bits, u32 flags)
1083{
1084 int domain, bus, rc;
1085
1086 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
1087 return 0;
1088
1089 if ((command_bits & PCI_COMMAND_IO) == 0)
1090 return 0;
1091
1092 domain = pci_domain_nr(pdev->bus);
1093 bus = pdev->bus->number;
1094
1095 rc = uv_bios_set_legacy_vga_target(decode, domain, bus);
1096
1097 return rc;
1098}
1099
1100
1101
1102
1103
1104void uv_cpu_init(void)
1105{
1106
1107 if (smp_processor_id() == 0)
1108 return;
1109
1110 uv_hub_info->nr_online_cpus++;
1111
1112 if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
1113 set_x2apic_extra_bits(uv_hub_info->pnode);
1114}
1115
1116struct mn {
1117 unsigned char m_val;
1118 unsigned char n_val;
1119 unsigned char m_shift;
1120 unsigned char n_lshift;
1121};
1122
1123static void get_mn(struct mn *mnp)
1124{
1125 union uvh_rh_gam_config_mmr_u m_n_config;
1126 union uv3h_gr0_gam_gr_config_u m_gr_config;
1127
1128
1129 memset(mnp, 0, sizeof(*mnp));
1130
1131 m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR);
1132 mnp->n_val = m_n_config.s.n_skt;
1133
1134 if (is_uv4_hub()) {
1135 mnp->m_val = 0;
1136 mnp->n_lshift = 0;
1137 } else if (is_uv3_hub()) {
1138 mnp->m_val = m_n_config.s3.m_skt;
1139 m_gr_config.v = uv_read_local_mmr(UV3H_GR0_GAM_GR_CONFIG);
1140 mnp->n_lshift = m_gr_config.s3.m_skt;
1141 } else if (is_uv2_hub()) {
1142 mnp->m_val = m_n_config.s2.m_skt;
1143 mnp->n_lshift = mnp->m_val == 40 ? 40 : 39;
1144 } else if (is_uv1_hub()) {
1145 mnp->m_val = m_n_config.s1.m_skt;
1146 mnp->n_lshift = mnp->m_val;
1147 }
1148 mnp->m_shift = mnp->m_val ? 64 - mnp->m_val : 0;
1149}
1150
1151static void __init uv_init_hub_info(struct uv_hub_info_s *hi)
1152{
1153 union uvh_node_id_u node_id;
1154 struct mn mn;
1155
1156 get_mn(&mn);
1157 hi->gpa_mask = mn.m_val ?
1158 (1UL << (mn.m_val + mn.n_val)) - 1 :
1159 (1UL << uv_cpuid.gpa_shift) - 1;
1160
1161 hi->m_val = mn.m_val;
1162 hi->n_val = mn.n_val;
1163 hi->m_shift = mn.m_shift;
1164 hi->n_lshift = mn.n_lshift ? mn.n_lshift : 0;
1165 hi->hub_revision = uv_hub_info->hub_revision;
1166 hi->pnode_mask = uv_cpuid.pnode_mask;
1167 hi->min_pnode = _min_pnode;
1168 hi->min_socket = _min_socket;
1169 hi->pnode_to_socket = _pnode_to_socket;
1170 hi->socket_to_node = _socket_to_node;
1171 hi->socket_to_pnode = _socket_to_pnode;
1172 hi->gr_table_len = _gr_table_len;
1173 hi->gr_table = _gr_table;
1174
1175 node_id.v = uv_read_local_mmr(UVH_NODE_ID);
1176 uv_cpuid.gnode_shift = max_t(unsigned int, uv_cpuid.gnode_shift, mn.n_val);
1177 hi->gnode_extra = (node_id.s.node_id & ~((1 << uv_cpuid.gnode_shift) - 1)) >> 1;
1178 if (mn.m_val)
1179 hi->gnode_upper = (u64)hi->gnode_extra << mn.m_val;
1180
1181 if (uv_gp_table) {
1182 hi->global_mmr_base = uv_gp_table->mmr_base;
1183 hi->global_mmr_shift = uv_gp_table->mmr_shift;
1184 hi->global_gru_base = uv_gp_table->gru_base;
1185 hi->global_gru_shift = uv_gp_table->gru_shift;
1186 hi->gpa_shift = uv_gp_table->gpa_shift;
1187 hi->gpa_mask = (1UL << hi->gpa_shift) - 1;
1188 } else {
1189 hi->global_mmr_base = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) & ~UV_MMR_ENABLE;
1190 hi->global_mmr_shift = _UV_GLOBAL_MMR64_PNODE_SHIFT;
1191 }
1192
1193 get_lowmem_redirect(&hi->lowmem_remap_base, &hi->lowmem_remap_top);
1194
1195 hi->apic_pnode_shift = uv_cpuid.socketid_shift;
1196
1197
1198 pr_info("UV: N:%d M:%d m_shift:%d n_lshift:%d\n", hi->n_val, hi->m_val, hi->m_shift, hi->n_lshift);
1199 pr_info("UV: gpa_mask/shift:0x%lx/%d pnode_mask:0x%x apic_pns:%d\n", hi->gpa_mask, hi->gpa_shift, hi->pnode_mask, hi->apic_pnode_shift);
1200 pr_info("UV: mmr_base/shift:0x%lx/%ld gru_base/shift:0x%lx/%ld\n", hi->global_mmr_base, hi->global_mmr_shift, hi->global_gru_base, hi->global_gru_shift);
1201 pr_info("UV: gnode_upper:0x%lx gnode_extra:0x%x\n", hi->gnode_upper, hi->gnode_extra);
1202}
1203
1204static void __init decode_gam_params(unsigned long ptr)
1205{
1206 uv_gp_table = (struct uv_gam_parameters *)ptr;
1207
1208 pr_info("UV: GAM Params...\n");
1209 pr_info("UV: mmr_base/shift:0x%llx/%d gru_base/shift:0x%llx/%d gpa_shift:%d\n",
1210 uv_gp_table->mmr_base, uv_gp_table->mmr_shift,
1211 uv_gp_table->gru_base, uv_gp_table->gru_shift,
1212 uv_gp_table->gpa_shift);
1213}
1214
1215static void __init decode_gam_rng_tbl(unsigned long ptr)
1216{
1217 struct uv_gam_range_entry *gre = (struct uv_gam_range_entry *)ptr;
1218 unsigned long lgre = 0;
1219 int index = 0;
1220 int sock_min = 999999, pnode_min = 99999;
1221 int sock_max = -1, pnode_max = -1;
1222
1223 uv_gre_table = gre;
1224 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
1225 unsigned long size = ((unsigned long)(gre->limit - lgre)
1226 << UV_GAM_RANGE_SHFT);
1227 int order = 0;
1228 char suffix[] = " KMGTPE";
1229 int flag = ' ';
1230
1231 while (size > 9999 && order < sizeof(suffix)) {
1232 size /= 1024;
1233 order++;
1234 }
1235
1236
1237 if (gre->type == 1 || gre->type == 2)
1238 if (adj_blksize(lgre))
1239 flag = '*';
1240
1241 if (!index) {
1242 pr_info("UV: GAM Range Table...\n");
1243 pr_info("UV: # %20s %14s %6s %4s %5s %3s %2s\n", "Range", "", "Size", "Type", "NASID", "SID", "PN");
1244 }
1245 pr_info("UV: %2d: 0x%014lx-0x%014lx%c %5lu%c %3d %04x %02x %02x\n",
1246 index++,
1247 (unsigned long)lgre << UV_GAM_RANGE_SHFT,
1248 (unsigned long)gre->limit << UV_GAM_RANGE_SHFT,
1249 flag, size, suffix[order],
1250 gre->type, gre->nasid, gre->sockid, gre->pnode);
1251
1252
1253 lgre = gre->limit;
1254 if (sock_min > gre->sockid)
1255 sock_min = gre->sockid;
1256 if (sock_max < gre->sockid)
1257 sock_max = gre->sockid;
1258 if (pnode_min > gre->pnode)
1259 pnode_min = gre->pnode;
1260 if (pnode_max < gre->pnode)
1261 pnode_max = gre->pnode;
1262 }
1263 _min_socket = sock_min;
1264 _max_socket = sock_max;
1265 _min_pnode = pnode_min;
1266 _max_pnode = pnode_max;
1267 _gr_table_len = index;
1268
1269 pr_info("UV: GRT: %d entries, sockets(min:%x,max:%x) pnodes(min:%x,max:%x)\n", index, _min_socket, _max_socket, _min_pnode, _max_pnode);
1270}
1271
1272static int __init decode_uv_systab(void)
1273{
1274 struct uv_systab *st;
1275 int i;
1276
1277 if (uv_hub_info->hub_revision < UV4_HUB_REVISION_BASE)
1278 return 0;
1279
1280 st = uv_systab;
1281 if ((!st) || (st->revision < UV_SYSTAB_VERSION_UV4_LATEST)) {
1282 int rev = st ? st->revision : 0;
1283
1284 pr_err("UV: BIOS UVsystab version(%x) mismatch, expecting(%x)\n", rev, UV_SYSTAB_VERSION_UV4_LATEST);
1285 pr_err("UV: Cannot support UV operations, switching to generic PC\n");
1286 uv_system_type = UV_NONE;
1287
1288 return -EINVAL;
1289 }
1290
1291 for (i = 0; st->entry[i].type != UV_SYSTAB_TYPE_UNUSED; i++) {
1292 unsigned long ptr = st->entry[i].offset;
1293
1294 if (!ptr)
1295 continue;
1296
1297 ptr = ptr + (unsigned long)st;
1298
1299 switch (st->entry[i].type) {
1300 case UV_SYSTAB_TYPE_GAM_PARAMS:
1301 decode_gam_params(ptr);
1302 break;
1303
1304 case UV_SYSTAB_TYPE_GAM_RNG_TBL:
1305 decode_gam_rng_tbl(ptr);
1306 break;
1307 }
1308 }
1309 return 0;
1310}
1311
1312
1313
1314
1315
1316
1317static __init void boot_init_possible_blades(struct uv_hub_info_s *hub_info)
1318{
1319 int i, uv_pb = 0;
1320
1321 pr_info("UV: NODE_PRESENT_DEPTH = %d\n", UVH_NODE_PRESENT_TABLE_DEPTH);
1322 for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
1323 unsigned long np;
1324
1325 np = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
1326 if (np)
1327 pr_info("UV: NODE_PRESENT(%d) = 0x%016lx\n", i, np);
1328
1329 uv_pb += hweight64(np);
1330 }
1331 if (uv_possible_blades != uv_pb)
1332 uv_possible_blades = uv_pb;
1333}
1334
1335static void __init build_socket_tables(void)
1336{
1337 struct uv_gam_range_entry *gre = uv_gre_table;
1338 int num, nump;
1339 int cpu, i, lnid;
1340 int minsock = _min_socket;
1341 int maxsock = _max_socket;
1342 int minpnode = _min_pnode;
1343 int maxpnode = _max_pnode;
1344 size_t bytes;
1345
1346 if (!gre) {
1347 if (is_uv1_hub() || is_uv2_hub() || is_uv3_hub()) {
1348 pr_info("UV: No UVsystab socket table, ignoring\n");
1349 return;
1350 }
1351 pr_crit("UV: Error: UVsystab address translations not available!\n");
1352 BUG();
1353 }
1354
1355
1356 num = maxsock - minsock + 1;
1357 bytes = num * sizeof(_socket_to_node[0]);
1358 _socket_to_node = kmalloc(bytes, GFP_KERNEL);
1359 _socket_to_pnode = kmalloc(bytes, GFP_KERNEL);
1360
1361 nump = maxpnode - minpnode + 1;
1362 bytes = nump * sizeof(_pnode_to_socket[0]);
1363 _pnode_to_socket = kmalloc(bytes, GFP_KERNEL);
1364 BUG_ON(!_socket_to_node || !_socket_to_pnode || !_pnode_to_socket);
1365
1366 for (i = 0; i < num; i++)
1367 _socket_to_node[i] = _socket_to_pnode[i] = SOCK_EMPTY;
1368
1369 for (i = 0; i < nump; i++)
1370 _pnode_to_socket[i] = SOCK_EMPTY;
1371
1372
1373 pr_info("UV: GAM Building socket/pnode conversion tables\n");
1374 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
1375 if (gre->type == UV_GAM_RANGE_TYPE_HOLE)
1376 continue;
1377 i = gre->sockid - minsock;
1378
1379 if (_socket_to_pnode[i] != SOCK_EMPTY)
1380 continue;
1381 _socket_to_pnode[i] = gre->pnode;
1382
1383 i = gre->pnode - minpnode;
1384 _pnode_to_socket[i] = gre->sockid;
1385
1386 pr_info("UV: sid:%02x type:%d nasid:%04x pn:%02x pn2s:%2x\n",
1387 gre->sockid, gre->type, gre->nasid,
1388 _socket_to_pnode[gre->sockid - minsock],
1389 _pnode_to_socket[gre->pnode - minpnode]);
1390 }
1391
1392
1393 lnid = -1;
1394 for_each_present_cpu(cpu) {
1395 int nid = cpu_to_node(cpu);
1396 int apicid, sockid;
1397
1398 if (lnid == nid)
1399 continue;
1400 lnid = nid;
1401 apicid = per_cpu(x86_cpu_to_apicid, cpu);
1402 sockid = apicid >> uv_cpuid.socketid_shift;
1403 _socket_to_node[sockid - minsock] = nid;
1404 pr_info("UV: sid:%02x: apicid:%04x node:%2d\n",
1405 sockid, apicid, nid);
1406 }
1407
1408
1409 bytes = num_possible_nodes() * sizeof(_node_to_pnode[0]);
1410 _node_to_pnode = kmalloc(bytes, GFP_KERNEL);
1411 BUG_ON(!_node_to_pnode);
1412
1413 for (lnid = 0; lnid < num_possible_nodes(); lnid++) {
1414 unsigned short sockid;
1415
1416 for (sockid = minsock; sockid <= maxsock; sockid++) {
1417 if (lnid == _socket_to_node[sockid - minsock]) {
1418 _node_to_pnode[lnid] = _socket_to_pnode[sockid - minsock];
1419 break;
1420 }
1421 }
1422 if (sockid > maxsock) {
1423 pr_err("UV: socket for node %d not found!\n", lnid);
1424 BUG();
1425 }
1426 }
1427
1428
1429
1430
1431
1432 pr_info("UV: Checking socket->node/pnode for identity maps\n");
1433 if (minsock == 0) {
1434 for (i = 0; i < num; i++)
1435 if (_socket_to_node[i] == SOCK_EMPTY || i != _socket_to_node[i])
1436 break;
1437 if (i >= num) {
1438 kfree(_socket_to_node);
1439 _socket_to_node = NULL;
1440 pr_info("UV: 1:1 socket_to_node table removed\n");
1441 }
1442 }
1443 if (minsock == minpnode) {
1444 for (i = 0; i < num; i++)
1445 if (_socket_to_pnode[i] != SOCK_EMPTY &&
1446 _socket_to_pnode[i] != i + minpnode)
1447 break;
1448 if (i >= num) {
1449 kfree(_socket_to_pnode);
1450 _socket_to_pnode = NULL;
1451 pr_info("UV: 1:1 socket_to_pnode table removed\n");
1452 }
1453 }
1454}
1455
1456static void __init uv_system_init_hub(void)
1457{
1458 struct uv_hub_info_s hub_info = {0};
1459 int bytes, cpu, nodeid;
1460 unsigned short min_pnode = 9999, max_pnode = 0;
1461 char *hub = is_uv4_hub() ? "UV400" :
1462 is_uv3_hub() ? "UV300" :
1463 is_uv2_hub() ? "UV2000/3000" :
1464 is_uv1_hub() ? "UV100/1000" : NULL;
1465
1466 if (!hub) {
1467 pr_err("UV: Unknown/unsupported UV hub\n");
1468 return;
1469 }
1470 pr_info("UV: Found %s hub\n", hub);
1471
1472 map_low_mmrs();
1473
1474
1475 uv_bios_init();
1476
1477
1478 if (decode_uv_systab() < 0)
1479 return;
1480
1481 build_socket_tables();
1482 build_uv_gr_table();
1483 set_block_size();
1484 uv_init_hub_info(&hub_info);
1485 uv_possible_blades = num_possible_nodes();
1486 if (!_node_to_pnode)
1487 boot_init_possible_blades(&hub_info);
1488
1489
1490 pr_info("UV: Found %d hubs, %d nodes, %d CPUs\n", uv_num_possible_blades(), num_possible_nodes(), num_possible_cpus());
1491
1492 uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id, &sn_region_size, &system_serial_number);
1493 hub_info.coherency_domain_number = sn_coherency_id;
1494 uv_rtc_init();
1495
1496 bytes = sizeof(void *) * uv_num_possible_blades();
1497 __uv_hub_info_list = kzalloc(bytes, GFP_KERNEL);
1498 BUG_ON(!__uv_hub_info_list);
1499
1500 bytes = sizeof(struct uv_hub_info_s);
1501 for_each_node(nodeid) {
1502 struct uv_hub_info_s *new_hub;
1503
1504 if (__uv_hub_info_list[nodeid]) {
1505 pr_err("UV: Node %d UV HUB already initialized!?\n", nodeid);
1506 BUG();
1507 }
1508
1509
1510 new_hub = (nodeid == 0) ? &uv_hub_info_node0 : kzalloc_node(bytes, GFP_KERNEL, nodeid);
1511 BUG_ON(!new_hub);
1512 __uv_hub_info_list[nodeid] = new_hub;
1513 new_hub = uv_hub_info_list(nodeid);
1514 BUG_ON(!new_hub);
1515 *new_hub = hub_info;
1516
1517
1518 if (_node_to_pnode)
1519 new_hub->pnode = _node_to_pnode[nodeid];
1520 else
1521 new_hub->pnode = 0xffff;
1522
1523 new_hub->numa_blade_id = uv_node_to_blade_id(nodeid);
1524 new_hub->memory_nid = -1;
1525 new_hub->nr_possible_cpus = 0;
1526 new_hub->nr_online_cpus = 0;
1527 }
1528
1529
1530 for_each_possible_cpu(cpu) {
1531 int apicid = per_cpu(x86_cpu_to_apicid, cpu);
1532 int numa_node_id;
1533 unsigned short pnode;
1534
1535 nodeid = cpu_to_node(cpu);
1536 numa_node_id = numa_cpu_node(cpu);
1537 pnode = uv_apicid_to_pnode(apicid);
1538
1539 uv_cpu_info_per(cpu)->p_uv_hub_info = uv_hub_info_list(nodeid);
1540 uv_cpu_info_per(cpu)->blade_cpu_id = uv_cpu_hub_info(cpu)->nr_possible_cpus++;
1541 if (uv_cpu_hub_info(cpu)->memory_nid == -1)
1542 uv_cpu_hub_info(cpu)->memory_nid = cpu_to_node(cpu);
1543
1544
1545 if (nodeid != numa_node_id &&
1546 uv_hub_info_list(numa_node_id)->pnode == 0xffff)
1547 uv_hub_info_list(numa_node_id)->pnode = pnode;
1548 else if (uv_cpu_hub_info(cpu)->pnode == 0xffff)
1549 uv_cpu_hub_info(cpu)->pnode = pnode;
1550
1551 uv_cpu_scir_info(cpu)->offset = uv_scir_offset(apicid);
1552 }
1553
1554 for_each_node(nodeid) {
1555 unsigned short pnode = uv_hub_info_list(nodeid)->pnode;
1556
1557
1558 if (pnode == 0xffff) {
1559 unsigned long paddr;
1560
1561 paddr = node_start_pfn(nodeid) << PAGE_SHIFT;
1562 pnode = uv_gpa_to_pnode(uv_soc_phys_ram_to_gpa(paddr));
1563 uv_hub_info_list(nodeid)->pnode = pnode;
1564 }
1565 min_pnode = min(pnode, min_pnode);
1566 max_pnode = max(pnode, max_pnode);
1567 pr_info("UV: UVHUB node:%2d pn:%02x nrcpus:%d\n",
1568 nodeid,
1569 uv_hub_info_list(nodeid)->pnode,
1570 uv_hub_info_list(nodeid)->nr_possible_cpus);
1571 }
1572
1573 pr_info("UV: min_pnode:%02x max_pnode:%02x\n", min_pnode, max_pnode);
1574 map_gru_high(max_pnode);
1575 map_mmr_high(max_pnode);
1576 map_mmioh_high(min_pnode, max_pnode);
1577
1578 uv_nmi_setup();
1579 uv_cpu_init();
1580 uv_scir_register_cpu_notifier();
1581 proc_mkdir("sgi_uv", NULL);
1582
1583
1584 pci_register_set_vga_state(uv_set_vga_state);
1585
1586
1587
1588
1589
1590 if (is_kdump_kernel())
1591 reboot_type = BOOT_ACPI;
1592}
1593
1594
1595
1596
1597
1598void __init uv_system_init(void)
1599{
1600 if (likely(!is_uv_system() && !is_uv_hubless()))
1601 return;
1602
1603 if (is_uv_system())
1604 uv_system_init_hub();
1605 else
1606 uv_nmi_setup_hubless();
1607}
1608
1609apic_driver(apic_x2apic_uv_x);
1610
