1
2#include <linux/clk-provider.h>
3#include <linux/mfd/syscon.h>
4#include <linux/slab.h>
5
6#include <dt-bindings/clock/at91.h>
7
8#include "pmc.h"
9
10static const struct clk_master_characteristics mck_characteristics = {
11 .output = { .min = 0, .max = 133333333 },
12 .divisors = { 1, 2, 4, 3 },
13 .have_div3_pres = 1,
14};
15
16static u8 plla_out[] = { 0, 1, 2, 3, 0, 1, 2, 3 };
17
18static u16 plla_icpll[] = { 0, 0, 0, 0, 1, 1, 1, 1 };
19
20static struct clk_range plla_outputs[] = {
21 { .min = 745000000, .max = 800000000 },
22 { .min = 695000000, .max = 750000000 },
23 { .min = 645000000, .max = 700000000 },
24 { .min = 595000000, .max = 650000000 },
25 { .min = 545000000, .max = 600000000 },
26 { .min = 495000000, .max = 555000000 },
27 { .min = 445000000, .max = 500000000 },
28 { .min = 400000000, .max = 450000000 },
29};
30
31static const struct clk_pll_characteristics plla_characteristics = {
32 .input = { .min = 2000000, .max = 32000000 },
33 .num_output = ARRAY_SIZE(plla_outputs),
34 .output = plla_outputs,
35 .icpll = plla_icpll,
36 .out = plla_out,
37};
38
39static const struct {
40 char *n;
41 char *p;
42 u8 id;
43} at91sam9x5_systemck[] = {
44 { .n = "ddrck", .p = "masterck", .id = 2 },
45 { .n = "smdck", .p = "smdclk", .id = 4 },
46 { .n = "uhpck", .p = "usbck", .id = 6 },
47 { .n = "udpck", .p = "usbck", .id = 7 },
48 { .n = "pck0", .p = "prog0", .id = 8 },
49 { .n = "pck1", .p = "prog1", .id = 9 },
50};
51
52struct pck {
53 char *n;
54 u8 id;
55};
56
57static const struct pck at91sam9x5_periphck[] = {
58 { .n = "pioAB_clk", .id = 2, },
59 { .n = "pioCD_clk", .id = 3, },
60 { .n = "smd_clk", .id = 4, },
61 { .n = "usart0_clk", .id = 5, },
62 { .n = "usart1_clk", .id = 6, },
63 { .n = "usart2_clk", .id = 7, },
64 { .n = "twi0_clk", .id = 9, },
65 { .n = "twi1_clk", .id = 10, },
66 { .n = "twi2_clk", .id = 11, },
67 { .n = "mci0_clk", .id = 12, },
68 { .n = "spi0_clk", .id = 13, },
69 { .n = "spi1_clk", .id = 14, },
70 { .n = "uart0_clk", .id = 15, },
71 { .n = "uart1_clk", .id = 16, },
72 { .n = "tcb0_clk", .id = 17, },
73 { .n = "pwm_clk", .id = 18, },
74 { .n = "adc_clk", .id = 19, },
75 { .n = "dma0_clk", .id = 20, },
76 { .n = "dma1_clk", .id = 21, },
77 { .n = "uhphs_clk", .id = 22, },
78 { .n = "udphs_clk", .id = 23, },
79 { .n = "mci1_clk", .id = 26, },
80 { .n = "ssc0_clk", .id = 28, },
81};
82
83static const struct pck at91sam9g15_periphck[] = {
84 { .n = "lcdc_clk", .id = 25, },
85 { }
86};
87
88static const struct pck at91sam9g25_periphck[] = {
89 { .n = "usart3_clk", .id = 8, },
90 { .n = "macb0_clk", .id = 24, },
91 { .n = "isi_clk", .id = 25, },
92 { }
93};
94
95static const struct pck at91sam9g35_periphck[] = {
96 { .n = "macb0_clk", .id = 24, },
97 { .n = "lcdc_clk", .id = 25, },
98 { }
99};
100
101static const struct pck at91sam9x25_periphck[] = {
102 { .n = "usart3_clk", .id = 8, },
103 { .n = "macb0_clk", .id = 24, },
104 { .n = "macb1_clk", .id = 27, },
105 { .n = "can0_clk", .id = 29, },
106 { .n = "can1_clk", .id = 30, },
107 { }
108};
109
110static const struct pck at91sam9x35_periphck[] = {
111 { .n = "macb0_clk", .id = 24, },
112 { .n = "lcdc_clk", .id = 25, },
113 { .n = "can0_clk", .id = 29, },
114 { .n = "can1_clk", .id = 30, },
115 { }
116};
117
118static void __init at91sam9x5_pmc_setup(struct device_node *np,
119 const struct pck *extra_pcks,
120 bool has_lcdck)
121{
122 struct clk_range range = CLK_RANGE(0, 0);
123 const char *slck_name, *mainxtal_name;
124 struct pmc_data *at91sam9x5_pmc;
125 const char *parent_names[6];
126 struct regmap *regmap;
127 struct clk_hw *hw;
128 int i;
129 bool bypass;
130
131 i = of_property_match_string(np, "clock-names", "slow_clk");
132 if (i < 0)
133 return;
134
135 slck_name = of_clk_get_parent_name(np, i);
136
137 i = of_property_match_string(np, "clock-names", "main_xtal");
138 if (i < 0)
139 return;
140 mainxtal_name = of_clk_get_parent_name(np, i);
141
142 regmap = syscon_node_to_regmap(np);
143 if (IS_ERR(regmap))
144 return;
145
146 at91sam9x5_pmc = pmc_data_allocate(PMC_MAIN + 1,
147 nck(at91sam9x5_systemck), 31, 0);
148 if (!at91sam9x5_pmc)
149 return;
150
151 hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000,
152 50000000);
153 if (IS_ERR(hw))
154 goto err_free;
155
156 bypass = of_property_read_bool(np, "atmel,osc-bypass");
157
158 hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
159 bypass);
160 if (IS_ERR(hw))
161 goto err_free;
162
163 parent_names[0] = "main_rc_osc";
164 parent_names[1] = "main_osc";
165 hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2);
166 if (IS_ERR(hw))
167 goto err_free;
168
169 at91sam9x5_pmc->chws[PMC_MAIN] = hw;
170
171 hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0,
172 &at91rm9200_pll_layout, &plla_characteristics);
173 if (IS_ERR(hw))
174 goto err_free;
175
176 hw = at91_clk_register_plldiv(regmap, "plladivck", "pllack");
177 if (IS_ERR(hw))
178 goto err_free;
179
180 hw = at91_clk_register_utmi(regmap, NULL, "utmick", "mainck");
181 if (IS_ERR(hw))
182 goto err_free;
183
184 at91sam9x5_pmc->chws[PMC_UTMI] = hw;
185
186 parent_names[0] = slck_name;
187 parent_names[1] = "mainck";
188 parent_names[2] = "plladivck";
189 parent_names[3] = "utmick";
190 hw = at91_clk_register_master(regmap, "masterck", 4, parent_names,
191 &at91sam9x5_master_layout,
192 &mck_characteristics);
193 if (IS_ERR(hw))
194 goto err_free;
195
196 at91sam9x5_pmc->chws[PMC_MCK] = hw;
197
198 parent_names[0] = "plladivck";
199 parent_names[1] = "utmick";
200 hw = at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, 2);
201 if (IS_ERR(hw))
202 goto err_free;
203
204 hw = at91sam9x5_clk_register_smd(regmap, "smdclk", parent_names, 2);
205 if (IS_ERR(hw))
206 goto err_free;
207
208 parent_names[0] = slck_name;
209 parent_names[1] = "mainck";
210 parent_names[2] = "plladivck";
211 parent_names[3] = "utmick";
212 parent_names[4] = "masterck";
213 for (i = 0; i < 2; i++) {
214 char name[6];
215
216 snprintf(name, sizeof(name), "prog%d", i);
217
218 hw = at91_clk_register_programmable(regmap, name,
219 parent_names, 5, i,
220 &at91sam9x5_programmable_layout);
221 if (IS_ERR(hw))
222 goto err_free;
223 }
224
225 for (i = 0; i < ARRAY_SIZE(at91sam9x5_systemck); i++) {
226 hw = at91_clk_register_system(regmap, at91sam9x5_systemck[i].n,
227 at91sam9x5_systemck[i].p,
228 at91sam9x5_systemck[i].id);
229 if (IS_ERR(hw))
230 goto err_free;
231
232 at91sam9x5_pmc->shws[at91sam9x5_systemck[i].id] = hw;
233 }
234
235 if (has_lcdck) {
236 hw = at91_clk_register_system(regmap, "lcdck", "masterck", 3);
237 if (IS_ERR(hw))
238 goto err_free;
239
240 at91sam9x5_pmc->shws[3] = hw;
241 }
242
243 for (i = 0; i < ARRAY_SIZE(at91sam9x5_periphck); i++) {
244 hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
245 at91sam9x5_periphck[i].n,
246 "masterck",
247 at91sam9x5_periphck[i].id,
248 &range);
249 if (IS_ERR(hw))
250 goto err_free;
251
252 at91sam9x5_pmc->phws[at91sam9x5_periphck[i].id] = hw;
253 }
254
255 for (i = 0; extra_pcks[i].id; i++) {
256 hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
257 extra_pcks[i].n,
258 "masterck",
259 extra_pcks[i].id,
260 &range);
261 if (IS_ERR(hw))
262 goto err_free;
263
264 at91sam9x5_pmc->phws[extra_pcks[i].id] = hw;
265 }
266
267 of_clk_add_hw_provider(np, of_clk_hw_pmc_get, at91sam9x5_pmc);
268
269 return;
270
271err_free:
272 pmc_data_free(at91sam9x5_pmc);
273}
274
275static void __init at91sam9g15_pmc_setup(struct device_node *np)
276{
277 at91sam9x5_pmc_setup(np, at91sam9g15_periphck, true);
278}
279CLK_OF_DECLARE_DRIVER(at91sam9g15_pmc, "atmel,at91sam9g15-pmc",
280 at91sam9g15_pmc_setup);
281
282static void __init at91sam9g25_pmc_setup(struct device_node *np)
283{
284 at91sam9x5_pmc_setup(np, at91sam9g25_periphck, false);
285}
286CLK_OF_DECLARE_DRIVER(at91sam9g25_pmc, "atmel,at91sam9g25-pmc",
287 at91sam9g25_pmc_setup);
288
289static void __init at91sam9g35_pmc_setup(struct device_node *np)
290{
291 at91sam9x5_pmc_setup(np, at91sam9g35_periphck, true);
292}
293CLK_OF_DECLARE_DRIVER(at91sam9g35_pmc, "atmel,at91sam9g35-pmc",
294 at91sam9g35_pmc_setup);
295
296static void __init at91sam9x25_pmc_setup(struct device_node *np)
297{
298 at91sam9x5_pmc_setup(np, at91sam9x25_periphck, false);
299}
300CLK_OF_DECLARE_DRIVER(at91sam9x25_pmc, "atmel,at91sam9x25-pmc",
301 at91sam9x25_pmc_setup);
302
303static void __init at91sam9x35_pmc_setup(struct device_node *np)
304{
305 at91sam9x5_pmc_setup(np, at91sam9x35_periphck, true);
306}
307CLK_OF_DECLARE_DRIVER(at91sam9x35_pmc, "atmel,at91sam9x35-pmc",
308 at91sam9x35_pmc_setup);
309
