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13#include <linux/kernel.h>
14#include <linux/clk-provider.h>
15#include <linux/io.h>
16#include <linux/of.h>
17#include "common.h"
18
19
20
21
22
23
24
25
26#define SARL 0
27#define SARL_AXP_PCLK_FREQ_OPT 21
28#define SARL_AXP_PCLK_FREQ_OPT_MASK 0x7
29#define SARL_AXP_FAB_FREQ_OPT 24
30#define SARL_AXP_FAB_FREQ_OPT_MASK 0xF
31#define SARH 4
32#define SARH_AXP_PCLK_FREQ_OPT (52-32)
33#define SARH_AXP_PCLK_FREQ_OPT_MASK 0x1
34#define SARH_AXP_PCLK_FREQ_OPT_SHIFT 3
35#define SARH_AXP_FAB_FREQ_OPT (51-32)
36#define SARH_AXP_FAB_FREQ_OPT_MASK 0x1
37#define SARH_AXP_FAB_FREQ_OPT_SHIFT 4
38
39enum { AXP_CPU_TO_NBCLK, AXP_CPU_TO_HCLK, AXP_CPU_TO_DRAMCLK };
40
41static const struct coreclk_ratio axp_coreclk_ratios[] __initconst = {
42 { .id = AXP_CPU_TO_NBCLK, .name = "nbclk" },
43 { .id = AXP_CPU_TO_HCLK, .name = "hclk" },
44 { .id = AXP_CPU_TO_DRAMCLK, .name = "dramclk" },
45};
46
47
48static u32 __init axp_get_tclk_freq(void __iomem *sar)
49{
50 return 250000000;
51}
52
53
54static u32 __init mv98dx3236_get_tclk_freq(void __iomem *sar)
55{
56 return 200000000;
57}
58
59static const u32 axp_cpu_freqs[] __initconst = {
60 1000000000,
61 1066000000,
62 1200000000,
63 1333000000,
64 1500000000,
65 1666000000,
66 1800000000,
67 2000000000,
68 667000000,
69 0,
70 800000000,
71 1600000000,
72};
73
74static u32 __init axp_get_cpu_freq(void __iomem *sar)
75{
76 u32 cpu_freq;
77 u8 cpu_freq_select = 0;
78
79 cpu_freq_select = ((readl(sar + SARL) >> SARL_AXP_PCLK_FREQ_OPT) &
80 SARL_AXP_PCLK_FREQ_OPT_MASK);
81
82
83
84
85 cpu_freq_select |= (((readl(sar + SARH) >> SARH_AXP_PCLK_FREQ_OPT) &
86 SARH_AXP_PCLK_FREQ_OPT_MASK) << SARH_AXP_PCLK_FREQ_OPT_SHIFT);
87 if (cpu_freq_select >= ARRAY_SIZE(axp_cpu_freqs)) {
88 pr_err("CPU freq select unsupported: %d\n", cpu_freq_select);
89 cpu_freq = 0;
90 } else
91 cpu_freq = axp_cpu_freqs[cpu_freq_select];
92
93 return cpu_freq;
94}
95
96
97static u32 __init mv98dx3236_get_cpu_freq(void __iomem *sar)
98{
99 return 800000000;
100}
101
102static const int axp_nbclk_ratios[32][2] __initconst = {
103 {0, 1}, {1, 2}, {2, 2}, {2, 2},
104 {1, 2}, {1, 2}, {1, 1}, {2, 3},
105 {0, 1}, {1, 2}, {2, 4}, {0, 1},
106 {1, 2}, {0, 1}, {0, 1}, {2, 2},
107 {0, 1}, {0, 1}, {0, 1}, {1, 1},
108 {2, 3}, {0, 1}, {0, 1}, {0, 1},
109 {0, 1}, {0, 1}, {0, 1}, {1, 1},
110 {0, 1}, {0, 1}, {0, 1}, {0, 1},
111};
112
113static const int axp_hclk_ratios[32][2] __initconst = {
114 {0, 1}, {1, 2}, {2, 6}, {2, 3},
115 {1, 3}, {1, 4}, {1, 2}, {2, 6},
116 {0, 1}, {1, 6}, {2, 10}, {0, 1},
117 {1, 4}, {0, 1}, {0, 1}, {2, 5},
118 {0, 1}, {0, 1}, {0, 1}, {1, 2},
119 {2, 6}, {0, 1}, {0, 1}, {0, 1},
120 {0, 1}, {0, 1}, {0, 1}, {1, 1},
121 {0, 1}, {0, 1}, {0, 1}, {0, 1},
122};
123
124static const int axp_dramclk_ratios[32][2] __initconst = {
125 {0, 1}, {1, 2}, {2, 3}, {2, 3},
126 {1, 3}, {1, 2}, {1, 2}, {2, 6},
127 {0, 1}, {1, 3}, {2, 5}, {0, 1},
128 {1, 4}, {0, 1}, {0, 1}, {2, 5},
129 {0, 1}, {0, 1}, {0, 1}, {1, 1},
130 {2, 3}, {0, 1}, {0, 1}, {0, 1},
131 {0, 1}, {0, 1}, {0, 1}, {1, 1},
132 {0, 1}, {0, 1}, {0, 1}, {0, 1},
133};
134
135static void __init axp_get_clk_ratio(
136 void __iomem *sar, int id, int *mult, int *div)
137{
138 u32 opt = ((readl(sar + SARL) >> SARL_AXP_FAB_FREQ_OPT) &
139 SARL_AXP_FAB_FREQ_OPT_MASK);
140
141
142
143
144 opt |= (((readl(sar + SARH) >> SARH_AXP_FAB_FREQ_OPT) &
145 SARH_AXP_FAB_FREQ_OPT_MASK) << SARH_AXP_FAB_FREQ_OPT_SHIFT);
146
147 switch (id) {
148 case AXP_CPU_TO_NBCLK:
149 *mult = axp_nbclk_ratios[opt][0];
150 *div = axp_nbclk_ratios[opt][1];
151 break;
152 case AXP_CPU_TO_HCLK:
153 *mult = axp_hclk_ratios[opt][0];
154 *div = axp_hclk_ratios[opt][1];
155 break;
156 case AXP_CPU_TO_DRAMCLK:
157 *mult = axp_dramclk_ratios[opt][0];
158 *div = axp_dramclk_ratios[opt][1];
159 break;
160 }
161}
162
163static const struct coreclk_soc_desc axp_coreclks = {
164 .get_tclk_freq = axp_get_tclk_freq,
165 .get_cpu_freq = axp_get_cpu_freq,
166 .get_clk_ratio = axp_get_clk_ratio,
167 .ratios = axp_coreclk_ratios,
168 .num_ratios = ARRAY_SIZE(axp_coreclk_ratios),
169};
170
171static const struct coreclk_soc_desc mv98dx3236_coreclks = {
172 .get_tclk_freq = mv98dx3236_get_tclk_freq,
173 .get_cpu_freq = mv98dx3236_get_cpu_freq,
174};
175
176
177
178
179
180static const struct clk_gating_soc_desc axp_gating_desc[] __initconst = {
181 { "audio", NULL, 0, 0 },
182 { "ge3", NULL, 1, 0 },
183 { "ge2", NULL, 2, 0 },
184 { "ge1", NULL, 3, 0 },
185 { "ge0", NULL, 4, 0 },
186 { "pex00", NULL, 5, 0 },
187 { "pex01", NULL, 6, 0 },
188 { "pex02", NULL, 7, 0 },
189 { "pex03", NULL, 8, 0 },
190 { "pex10", NULL, 9, 0 },
191 { "pex11", NULL, 10, 0 },
192 { "pex12", NULL, 11, 0 },
193 { "pex13", NULL, 12, 0 },
194 { "bp", NULL, 13, 0 },
195 { "sata0lnk", NULL, 14, 0 },
196 { "sata0", "sata0lnk", 15, 0 },
197 { "lcd", NULL, 16, 0 },
198 { "sdio", NULL, 17, 0 },
199 { "usb0", NULL, 18, 0 },
200 { "usb1", NULL, 19, 0 },
201 { "usb2", NULL, 20, 0 },
202 { "xor0", NULL, 22, 0 },
203 { "crypto", NULL, 23, 0 },
204 { "tdm", NULL, 25, 0 },
205 { "pex20", NULL, 26, 0 },
206 { "pex30", NULL, 27, 0 },
207 { "xor1", NULL, 28, 0 },
208 { "sata1lnk", NULL, 29, 0 },
209 { "sata1", "sata1lnk", 30, 0 },
210 { }
211};
212
213static const struct clk_gating_soc_desc mv98dx3236_gating_desc[] __initconst = {
214 { "ge1", NULL, 3, 0 },
215 { "ge0", NULL, 4, 0 },
216 { "pex00", NULL, 5, 0 },
217 { "sdio", NULL, 17, 0 },
218 { "xor0", NULL, 22, 0 },
219 { }
220};
221
222static void __init axp_clk_init(struct device_node *np)
223{
224 struct device_node *cgnp =
225 of_find_compatible_node(NULL, NULL, "marvell,armada-xp-gating-clock");
226
227 mvebu_coreclk_setup(np, &axp_coreclks);
228
229 if (cgnp)
230 mvebu_clk_gating_setup(cgnp, axp_gating_desc);
231}
232CLK_OF_DECLARE(axp_clk, "marvell,armada-xp-core-clock", axp_clk_init);
233
