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11#include <linux/module.h>
12#include <linux/ctype.h>
13#include <linux/init.h>
14#include <linux/pci.h>
15#include <linux/pci_ids.h>
16#include <linux/slab.h>
17#include <linux/mmzone.h>
18#include <linux/edac.h>
19#include <asm/cpu_device_id.h>
20#include <asm/msr.h>
21#include "edac_module.h"
22#include "mce_amd.h"
23
24#define amd64_info(fmt, arg...) \
25 edac_printk(KERN_INFO, "amd64", fmt, ##arg)
26
27#define amd64_warn(fmt, arg...) \
28 edac_printk(KERN_WARNING, "amd64", "Warning: " fmt, ##arg)
29
30#define amd64_err(fmt, arg...) \
31 edac_printk(KERN_ERR, "amd64", "Error: " fmt, ##arg)
32
33#define amd64_mc_warn(mci, fmt, arg...) \
34 edac_mc_chipset_printk(mci, KERN_WARNING, "amd64", fmt, ##arg)
35
36#define amd64_mc_err(mci, fmt, arg...) \
37 edac_mc_chipset_printk(mci, KERN_ERR, "amd64", fmt, ##arg)
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87
88#define EDAC_AMD64_VERSION "3.5.0"
89#define EDAC_MOD_STR "amd64_edac"
90
91
92#define K8_REV_D 1
93#define K8_REV_E 2
94#define K8_REV_F 4
95
96
97#define NUM_CHIPSELECTS 8
98#define DRAM_RANGES 8
99
100#define ON true
101#define OFF false
102
103
104
105
106#define PCI_DEVICE_ID_AMD_15H_NB_F1 0x1601
107#define PCI_DEVICE_ID_AMD_15H_NB_F2 0x1602
108#define PCI_DEVICE_ID_AMD_15H_M30H_NB_F1 0x141b
109#define PCI_DEVICE_ID_AMD_15H_M30H_NB_F2 0x141c
110#define PCI_DEVICE_ID_AMD_15H_M60H_NB_F1 0x1571
111#define PCI_DEVICE_ID_AMD_15H_M60H_NB_F2 0x1572
112#define PCI_DEVICE_ID_AMD_16H_NB_F1 0x1531
113#define PCI_DEVICE_ID_AMD_16H_NB_F2 0x1532
114#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F1 0x1581
115#define PCI_DEVICE_ID_AMD_16H_M30H_NB_F2 0x1582
116#define PCI_DEVICE_ID_AMD_17H_DF_F0 0x1460
117#define PCI_DEVICE_ID_AMD_17H_DF_F6 0x1466
118#define PCI_DEVICE_ID_AMD_17H_M10H_DF_F0 0x15e8
119#define PCI_DEVICE_ID_AMD_17H_M10H_DF_F6 0x15ee
120
121
122
123
124#define DRAM_BASE_LO 0x40
125#define DRAM_LIMIT_LO 0x44
126
127
128
129
130#define DRAM_CONT_BASE 0x200
131#define DRAM_CONT_LIMIT 0x204
132
133
134
135
136#define DRAM_CONT_HIGH_OFF 0x240
137
138#define dram_rw(pvt, i) ((u8)(pvt->ranges[i].base.lo & 0x3))
139#define dram_intlv_sel(pvt, i) ((u8)((pvt->ranges[i].lim.lo >> 8) & 0x7))
140#define dram_dst_node(pvt, i) ((u8)(pvt->ranges[i].lim.lo & 0x7))
141
142#define DHAR 0xf0
143#define dhar_mem_hoist_valid(pvt) ((pvt)->dhar & BIT(1))
144#define dhar_base(pvt) ((pvt)->dhar & 0xff000000)
145#define k8_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff00) << 16)
146
147
148#define f10_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff80) << 16)
149
150#define DCT_CFG_SEL 0x10C
151
152#define DRAM_LOCAL_NODE_BASE 0x120
153#define DRAM_LOCAL_NODE_LIM 0x124
154
155#define DRAM_BASE_HI 0x140
156#define DRAM_LIMIT_HI 0x144
157
158
159
160
161
162#define DCSB0 0x40
163#define DCSB1 0x140
164#define DCSB_CS_ENABLE BIT(0)
165
166#define DCSM0 0x60
167#define DCSM1 0x160
168
169#define csrow_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases[(i)] & DCSB_CS_ENABLE)
170
171#define DRAM_CONTROL 0x78
172
173#define DBAM0 0x80
174#define DBAM1 0x180
175
176
177#define DBAM_DIMM(i, reg) ((((reg) >> (4*(i)))) & 0xF)
178
179#define DBAM_MAX_VALUE 11
180
181#define DCLR0 0x90
182#define DCLR1 0x190
183#define REVE_WIDTH_128 BIT(16)
184#define WIDTH_128 BIT(11)
185
186#define DCHR0 0x94
187#define DCHR1 0x194
188#define DDR3_MODE BIT(8)
189
190#define DCT_SEL_LO 0x110
191#define dct_high_range_enabled(pvt) ((pvt)->dct_sel_lo & BIT(0))
192#define dct_interleave_enabled(pvt) ((pvt)->dct_sel_lo & BIT(2))
193
194#define dct_ganging_enabled(pvt) ((boot_cpu_data.x86 == 0x10) && ((pvt)->dct_sel_lo & BIT(4)))
195
196#define dct_data_intlv_enabled(pvt) ((pvt)->dct_sel_lo & BIT(5))
197#define dct_memory_cleared(pvt) ((pvt)->dct_sel_lo & BIT(10))
198
199#define SWAP_INTLV_REG 0x10c
200
201#define DCT_SEL_HI 0x114
202
203#define F15H_M60H_SCRCTRL 0x1C8
204#define F17H_SCR_BASE_ADDR 0x48
205#define F17H_SCR_LIMIT_ADDR 0x4C
206
207
208
209
210#define NBCTL 0x40
211
212#define NBCFG 0x44
213#define NBCFG_CHIPKILL BIT(23)
214#define NBCFG_ECC_ENABLE BIT(22)
215
216
217#define F10_NBSL_EXT_ERR_ECC 0x8
218#define NBSL_PP_OBS 0x2
219
220#define SCRCTRL 0x58
221
222#define F10_ONLINE_SPARE 0xB0
223#define online_spare_swap_done(pvt, c) (((pvt)->online_spare >> (1 + 2 * (c))) & 0x1)
224#define online_spare_bad_dramcs(pvt, c) (((pvt)->online_spare >> (4 + 4 * (c))) & 0x7)
225
226#define F10_NB_ARRAY_ADDR 0xB8
227#define F10_NB_ARRAY_DRAM BIT(31)
228
229
230#define SET_NB_ARRAY_ADDR(section) (((section) & 0x3) << 1)
231
232#define F10_NB_ARRAY_DATA 0xBC
233#define F10_NB_ARR_ECC_WR_REQ BIT(17)
234#define SET_NB_DRAM_INJECTION_WRITE(inj) \
235 (BIT(((inj.word) & 0xF) + 20) | \
236 F10_NB_ARR_ECC_WR_REQ | inj.bit_map)
237#define SET_NB_DRAM_INJECTION_READ(inj) \
238 (BIT(((inj.word) & 0xF) + 20) | \
239 BIT(16) | inj.bit_map)
240
241
242#define NBCAP 0xE8
243#define NBCAP_CHIPKILL BIT(4)
244#define NBCAP_SECDED BIT(3)
245#define NBCAP_DCT_DUAL BIT(0)
246
247#define EXT_NB_MCA_CFG 0x180
248
249
250#define MSR_MCGCTL_NBE BIT(4)
251
252
253
254
255#define DF_DHAR 0x104
256
257
258#define UMCCH_BASE_ADDR 0x0
259#define UMCCH_ADDR_MASK 0x20
260#define UMCCH_ADDR_CFG 0x30
261#define UMCCH_DIMM_CFG 0x80
262#define UMCCH_UMC_CFG 0x100
263#define UMCCH_SDP_CTRL 0x104
264#define UMCCH_ECC_CTRL 0x14C
265#define UMCCH_ECC_BAD_SYMBOL 0xD90
266#define UMCCH_UMC_CAP 0xDF0
267#define UMCCH_UMC_CAP_HI 0xDF4
268
269
270#define UMC_ECC_CHIPKILL_CAP BIT(31)
271#define UMC_ECC_ENABLED BIT(30)
272
273#define UMC_SDP_INIT BIT(31)
274
275#define NUM_UMCS 2
276
277enum amd_families {
278 K8_CPUS = 0,
279 F10_CPUS,
280 F15_CPUS,
281 F15_M30H_CPUS,
282 F15_M60H_CPUS,
283 F16_CPUS,
284 F16_M30H_CPUS,
285 F17_CPUS,
286 F17_M10H_CPUS,
287 NUM_FAMILIES,
288};
289
290
291struct error_injection {
292 u32 section;
293 u32 word;
294 u32 bit_map;
295};
296
297
298struct reg_pair {
299 u32 lo, hi;
300};
301
302
303
304
305struct dram_range {
306 struct reg_pair base;
307 struct reg_pair lim;
308};
309
310
311struct chip_select {
312 u32 csbases[NUM_CHIPSELECTS];
313 u8 b_cnt;
314
315 u32 csmasks[NUM_CHIPSELECTS];
316 u8 m_cnt;
317};
318
319struct amd64_umc {
320 u32 dimm_cfg;
321 u32 umc_cfg;
322 u32 sdp_ctrl;
323 u32 ecc_ctrl;
324 u32 umc_cap_hi;
325};
326
327struct amd64_pvt {
328 struct low_ops *ops;
329
330
331 struct pci_dev *F0, *F1, *F2, *F3, *F6;
332
333 u16 mc_node_id;
334 u8 fam;
335 u8 model;
336 u8 stepping;
337
338 int ext_model;
339 int channel_count;
340
341
342 u32 dclr0;
343 u32 dclr1;
344 u32 dchr0;
345 u32 dchr1;
346 u32 nbcap;
347 u32 nbcfg;
348 u32 ext_nbcfg;
349 u32 dhar;
350 u32 dbam0;
351 u32 dbam1;
352
353
354 struct chip_select csels[2];
355
356
357 struct dram_range ranges[DRAM_RANGES];
358
359 u64 top_mem;
360 u64 top_mem2;
361
362 u32 dct_sel_lo;
363 u32 dct_sel_hi;
364 u32 online_spare;
365
366
367 u8 ecc_sym_sz;
368
369
370 struct error_injection injection;
371
372
373 enum mem_type dram_type;
374
375 struct amd64_umc *umc;
376};
377
378enum err_codes {
379 DECODE_OK = 0,
380 ERR_NODE = -1,
381 ERR_CSROW = -2,
382 ERR_CHANNEL = -3,
383 ERR_SYND = -4,
384 ERR_NORM_ADDR = -5,
385};
386
387struct err_info {
388 int err_code;
389 struct mem_ctl_info *src_mci;
390 int csrow;
391 int channel;
392 u16 syndrome;
393 u32 page;
394 u32 offset;
395};
396
397static inline u32 get_umc_base(u8 channel)
398{
399
400 return 0x50000 + (!!channel << 20);
401}
402
403static inline u64 get_dram_base(struct amd64_pvt *pvt, u8 i)
404{
405 u64 addr = ((u64)pvt->ranges[i].base.lo & 0xffff0000) << 8;
406
407 if (boot_cpu_data.x86 == 0xf)
408 return addr;
409
410 return (((u64)pvt->ranges[i].base.hi & 0x000000ff) << 40) | addr;
411}
412
413static inline u64 get_dram_limit(struct amd64_pvt *pvt, u8 i)
414{
415 u64 lim = (((u64)pvt->ranges[i].lim.lo & 0xffff0000) << 8) | 0x00ffffff;
416
417 if (boot_cpu_data.x86 == 0xf)
418 return lim;
419
420 return (((u64)pvt->ranges[i].lim.hi & 0x000000ff) << 40) | lim;
421}
422
423static inline u16 extract_syndrome(u64 status)
424{
425 return ((status >> 47) & 0xff) | ((status >> 16) & 0xff00);
426}
427
428static inline u8 dct_sel_interleave_addr(struct amd64_pvt *pvt)
429{
430 if (pvt->fam == 0x15 && pvt->model >= 0x30)
431 return (((pvt->dct_sel_hi >> 9) & 0x1) << 2) |
432 ((pvt->dct_sel_lo >> 6) & 0x3);
433
434 return ((pvt)->dct_sel_lo >> 6) & 0x3;
435}
436
437
438
439struct ecc_settings {
440 u32 old_nbctl;
441 bool nbctl_valid;
442
443 struct flags {
444 unsigned long nb_mce_enable:1;
445 unsigned long nb_ecc_prev:1;
446 } flags;
447};
448
449#ifdef CONFIG_EDAC_DEBUG
450extern const struct attribute_group amd64_edac_dbg_group;
451#endif
452
453#ifdef CONFIG_EDAC_AMD64_ERROR_INJECTION
454extern const struct attribute_group amd64_edac_inj_group;
455#endif
456
457
458
459
460
461struct low_ops {
462 int (*early_channel_count) (struct amd64_pvt *pvt);
463 void (*map_sysaddr_to_csrow) (struct mem_ctl_info *mci, u64 sys_addr,
464 struct err_info *);
465 int (*dbam_to_cs) (struct amd64_pvt *pvt, u8 dct,
466 unsigned cs_mode, int cs_mask_nr);
467};
468
469struct amd64_family_type {
470 const char *ctl_name;
471 u16 f0_id, f1_id, f2_id, f6_id;
472 struct low_ops ops;
473};
474
475int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,
476 u32 *val, const char *func);
477int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset,
478 u32 val, const char *func);
479
480#define amd64_read_pci_cfg(pdev, offset, val) \
481 __amd64_read_pci_cfg_dword(pdev, offset, val, __func__)
482
483#define amd64_write_pci_cfg(pdev, offset, val) \
484 __amd64_write_pci_cfg_dword(pdev, offset, val, __func__)
485
486int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base,
487 u64 *hole_offset, u64 *hole_size);
488
489#define to_mci(k) container_of(k, struct mem_ctl_info, dev)
490
491
492static inline void disable_caches(void *dummy)
493{
494 write_cr0(read_cr0() | X86_CR0_CD);
495 wbinvd();
496}
497
498static inline void enable_caches(void *dummy)
499{
500 write_cr0(read_cr0() & ~X86_CR0_CD);
501}
502
503static inline u8 dram_intlv_en(struct amd64_pvt *pvt, unsigned int i)
504{
505 if (pvt->fam == 0x15 && pvt->model >= 0x30) {
506 u32 tmp;
507 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_LIMIT, &tmp);
508 return (u8) tmp & 0xF;
509 }
510 return (u8) (pvt->ranges[i].base.lo >> 8) & 0x7;
511}
512
513static inline u8 dhar_valid(struct amd64_pvt *pvt)
514{
515 if (pvt->fam == 0x15 && pvt->model >= 0x30) {
516 u32 tmp;
517 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp);
518 return (tmp >> 1) & BIT(0);
519 }
520 return (pvt)->dhar & BIT(0);
521}
522
523static inline u32 dct_sel_baseaddr(struct amd64_pvt *pvt)
524{
525 if (pvt->fam == 0x15 && pvt->model >= 0x30) {
526 u32 tmp;
527 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp);
528 return (tmp >> 11) & 0x1FFF;
529 }
530 return (pvt)->dct_sel_lo & 0xFFFFF800;
531}
532