1/* 2 * Copyright (C) 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21#ifndef _gc_9_1_SH_MASK_HEADER 22#define _gc_9_1_SH_MASK_HEADER 23 24 25// addressBlock: gc_grbmdec 26//GRBM_CNTL 27#define GRBM_CNTL__READ_TIMEOUT__SHIFT 0x0 28#define GRBM_CNTL__REPORT_LAST_RDERR__SHIFT 0x1f 29#define GRBM_CNTL__READ_TIMEOUT_MASK 0x000000FFL 30#define GRBM_CNTL__REPORT_LAST_RDERR_MASK 0x80000000L 31//GRBM_SKEW_CNTL 32#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x0 33#define GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT 0x6 34#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK 0x0000003FL 35#define GRBM_SKEW_CNTL__SKEW_COUNT_MASK 0x00000FC0L 36//GRBM_STATUS2 37#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT 0x0 38#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT 0x4 39#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT 0x5 40#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT 0x6 41#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT 0x7 42#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT 0x8 43#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT 0x9 44#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT 0xa 45#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING__SHIFT 0xb 46#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING__SHIFT 0xc 47#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING__SHIFT 0xd 48#define GRBM_STATUS2__RLC_RQ_PENDING__SHIFT 0xe 49#define GRBM_STATUS2__UTCL2_BUSY__SHIFT 0xf 50#define GRBM_STATUS2__EA_BUSY__SHIFT 0x10 51#define GRBM_STATUS2__RMI_BUSY__SHIFT 0x11 52#define GRBM_STATUS2__UTCL2_RQ_PENDING__SHIFT 0x12 53#define GRBM_STATUS2__CPF_RQ_PENDING__SHIFT 0x13 54#define GRBM_STATUS2__EA_LINK_BUSY__SHIFT 0x14 55#define GRBM_STATUS2__RLC_BUSY__SHIFT 0x18 56#define GRBM_STATUS2__TC_BUSY__SHIFT 0x19 57#define GRBM_STATUS2__TCC_CC_RESIDENT__SHIFT 0x1a 58#define GRBM_STATUS2__CPF_BUSY__SHIFT 0x1c 59#define GRBM_STATUS2__CPC_BUSY__SHIFT 0x1d 60#define GRBM_STATUS2__CPG_BUSY__SHIFT 0x1e 61#define GRBM_STATUS2__CPAXI_BUSY__SHIFT 0x1f 62#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK 0x0000000FL 63#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK 0x00000010L 64#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK 0x00000020L 65#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK 0x00000040L 66#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK 0x00000080L 67#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK 0x00000100L 68#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK 0x00000200L 69#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING_MASK 0x00000400L 70#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING_MASK 0x00000800L 71#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING_MASK 0x00001000L 72#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING_MASK 0x00002000L 73#define GRBM_STATUS2__RLC_RQ_PENDING_MASK 0x00004000L 74#define GRBM_STATUS2__UTCL2_BUSY_MASK 0x00008000L 75#define GRBM_STATUS2__EA_BUSY_MASK 0x00010000L 76#define GRBM_STATUS2__RMI_BUSY_MASK 0x00020000L 77#define GRBM_STATUS2__UTCL2_RQ_PENDING_MASK 0x00040000L 78#define GRBM_STATUS2__CPF_RQ_PENDING_MASK 0x00080000L 79#define GRBM_STATUS2__EA_LINK_BUSY_MASK 0x00100000L 80#define GRBM_STATUS2__RLC_BUSY_MASK 0x01000000L 81#define GRBM_STATUS2__TC_BUSY_MASK 0x02000000L 82#define GRBM_STATUS2__TCC_CC_RESIDENT_MASK 0x04000000L 83#define GRBM_STATUS2__CPF_BUSY_MASK 0x10000000L 84#define GRBM_STATUS2__CPC_BUSY_MASK 0x20000000L 85#define GRBM_STATUS2__CPG_BUSY_MASK 0x40000000L 86#define GRBM_STATUS2__CPAXI_BUSY_MASK 0x80000000L 87//GRBM_PWR_CNTL 88#define GRBM_PWR_CNTL__ALL_REQ_TYPE__SHIFT 0x0 89#define GRBM_PWR_CNTL__GFX_REQ_TYPE__SHIFT 0x2 90#define GRBM_PWR_CNTL__ALL_RSP_TYPE__SHIFT 0x4 91#define GRBM_PWR_CNTL__GFX_RSP_TYPE__SHIFT 0x6 92#define GRBM_PWR_CNTL__GFX_REQ_EN__SHIFT 0xe 93#define GRBM_PWR_CNTL__ALL_REQ_EN__SHIFT 0xf 94#define GRBM_PWR_CNTL__ALL_REQ_TYPE_MASK 0x00000003L 95#define GRBM_PWR_CNTL__GFX_REQ_TYPE_MASK 0x0000000CL 96#define GRBM_PWR_CNTL__ALL_RSP_TYPE_MASK 0x00000030L 97#define GRBM_PWR_CNTL__GFX_RSP_TYPE_MASK 0x000000C0L 98#define GRBM_PWR_CNTL__GFX_REQ_EN_MASK 0x00004000L 99#define GRBM_PWR_CNTL__ALL_REQ_EN_MASK 0x00008000L 100//GRBM_STATUS 101#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT 0x0 102#define GRBM_STATUS__RSMU_RQ_PENDING__SHIFT 0x5 103#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT 0x7 104#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT 0x8 105#define GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT 0x9 106#define GRBM_STATUS__DB_CLEAN__SHIFT 0xc 107#define GRBM_STATUS__CB_CLEAN__SHIFT 0xd 108#define GRBM_STATUS__TA_BUSY__SHIFT 0xe 109#define GRBM_STATUS__GDS_BUSY__SHIFT 0xf 110#define GRBM_STATUS__WD_BUSY_NO_DMA__SHIFT 0x10 111#define GRBM_STATUS__VGT_BUSY__SHIFT 0x11 112#define GRBM_STATUS__IA_BUSY_NO_DMA__SHIFT 0x12 113#define GRBM_STATUS__IA_BUSY__SHIFT 0x13 114#define GRBM_STATUS__SX_BUSY__SHIFT 0x14 115#define GRBM_STATUS__WD_BUSY__SHIFT 0x15 116#define GRBM_STATUS__SPI_BUSY__SHIFT 0x16 117#define GRBM_STATUS__BCI_BUSY__SHIFT 0x17 118#define GRBM_STATUS__SC_BUSY__SHIFT 0x18 119#define GRBM_STATUS__PA_BUSY__SHIFT 0x19 120#define GRBM_STATUS__DB_BUSY__SHIFT 0x1a 121#define GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT 0x1c 122#define GRBM_STATUS__CP_BUSY__SHIFT 0x1d 123#define GRBM_STATUS__CB_BUSY__SHIFT 0x1e 124#define GRBM_STATUS__GUI_ACTIVE__SHIFT 0x1f 125#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK 0x0000000FL 126#define GRBM_STATUS__RSMU_RQ_PENDING_MASK 0x00000020L 127#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK 0x00000080L 128#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK 0x00000100L 129#define GRBM_STATUS__GDS_DMA_RQ_PENDING_MASK 0x00000200L 130#define GRBM_STATUS__DB_CLEAN_MASK 0x00001000L 131#define GRBM_STATUS__CB_CLEAN_MASK 0x00002000L 132#define GRBM_STATUS__TA_BUSY_MASK 0x00004000L 133#define GRBM_STATUS__GDS_BUSY_MASK 0x00008000L 134#define GRBM_STATUS__WD_BUSY_NO_DMA_MASK 0x00010000L 135#define GRBM_STATUS__VGT_BUSY_MASK 0x00020000L 136#define GRBM_STATUS__IA_BUSY_NO_DMA_MASK 0x00040000L 137#define GRBM_STATUS__IA_BUSY_MASK 0x00080000L 138#define GRBM_STATUS__SX_BUSY_MASK 0x00100000L 139#define GRBM_STATUS__WD_BUSY_MASK 0x00200000L 140#define GRBM_STATUS__SPI_BUSY_MASK 0x00400000L 141#define GRBM_STATUS__BCI_BUSY_MASK 0x00800000L 142#define GRBM_STATUS__SC_BUSY_MASK 0x01000000L 143#define GRBM_STATUS__PA_BUSY_MASK 0x02000000L 144#define GRBM_STATUS__DB_BUSY_MASK 0x04000000L 145#define GRBM_STATUS__CP_COHERENCY_BUSY_MASK 0x10000000L 146#define GRBM_STATUS__CP_BUSY_MASK 0x20000000L 147#define GRBM_STATUS__CB_BUSY_MASK 0x40000000L 148#define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000L 149//GRBM_STATUS_SE0 150#define GRBM_STATUS_SE0__DB_CLEAN__SHIFT 0x1 151#define GRBM_STATUS_SE0__CB_CLEAN__SHIFT 0x2 152#define GRBM_STATUS_SE0__RMI_BUSY__SHIFT 0x15 153#define GRBM_STATUS_SE0__BCI_BUSY__SHIFT 0x16 154#define GRBM_STATUS_SE0__VGT_BUSY__SHIFT 0x17 155#define GRBM_STATUS_SE0__PA_BUSY__SHIFT 0x18 156#define GRBM_STATUS_SE0__TA_BUSY__SHIFT 0x19 157#define GRBM_STATUS_SE0__SX_BUSY__SHIFT 0x1a 158#define GRBM_STATUS_SE0__SPI_BUSY__SHIFT 0x1b 159#define GRBM_STATUS_SE0__SC_BUSY__SHIFT 0x1d 160#define GRBM_STATUS_SE0__DB_BUSY__SHIFT 0x1e 161#define GRBM_STATUS_SE0__CB_BUSY__SHIFT 0x1f 162#define GRBM_STATUS_SE0__DB_CLEAN_MASK 0x00000002L 163#define GRBM_STATUS_SE0__CB_CLEAN_MASK 0x00000004L 164#define GRBM_STATUS_SE0__RMI_BUSY_MASK 0x00200000L 165#define GRBM_STATUS_SE0__BCI_BUSY_MASK 0x00400000L 166#define GRBM_STATUS_SE0__VGT_BUSY_MASK 0x00800000L 167#define GRBM_STATUS_SE0__PA_BUSY_MASK 0x01000000L 168#define GRBM_STATUS_SE0__TA_BUSY_MASK 0x02000000L 169#define GRBM_STATUS_SE0__SX_BUSY_MASK 0x04000000L 170#define GRBM_STATUS_SE0__SPI_BUSY_MASK 0x08000000L 171#define GRBM_STATUS_SE0__SC_BUSY_MASK 0x20000000L 172#define GRBM_STATUS_SE0__DB_BUSY_MASK 0x40000000L 173#define GRBM_STATUS_SE0__CB_BUSY_MASK 0x80000000L 174//GRBM_STATUS_SE1 175#define GRBM_STATUS_SE1__DB_CLEAN__SHIFT 0x1 176#define GRBM_STATUS_SE1__CB_CLEAN__SHIFT 0x2 177#define GRBM_STATUS_SE1__RMI_BUSY__SHIFT 0x15 178#define GRBM_STATUS_SE1__BCI_BUSY__SHIFT 0x16 179#define GRBM_STATUS_SE1__VGT_BUSY__SHIFT 0x17 180#define GRBM_STATUS_SE1__PA_BUSY__SHIFT 0x18 181#define GRBM_STATUS_SE1__TA_BUSY__SHIFT 0x19 182#define GRBM_STATUS_SE1__SX_BUSY__SHIFT 0x1a 183#define GRBM_STATUS_SE1__SPI_BUSY__SHIFT 0x1b 184#define GRBM_STATUS_SE1__SC_BUSY__SHIFT 0x1d 185#define GRBM_STATUS_SE1__DB_BUSY__SHIFT 0x1e 186#define GRBM_STATUS_SE1__CB_BUSY__SHIFT 0x1f 187#define GRBM_STATUS_SE1__DB_CLEAN_MASK 0x00000002L 188#define GRBM_STATUS_SE1__CB_CLEAN_MASK 0x00000004L 189#define GRBM_STATUS_SE1__RMI_BUSY_MASK 0x00200000L 190#define GRBM_STATUS_SE1__BCI_BUSY_MASK 0x00400000L 191#define GRBM_STATUS_SE1__VGT_BUSY_MASK 0x00800000L 192#define GRBM_STATUS_SE1__PA_BUSY_MASK 0x01000000L 193#define GRBM_STATUS_SE1__TA_BUSY_MASK 0x02000000L 194#define GRBM_STATUS_SE1__SX_BUSY_MASK 0x04000000L 195#define GRBM_STATUS_SE1__SPI_BUSY_MASK 0x08000000L 196#define GRBM_STATUS_SE1__SC_BUSY_MASK 0x20000000L 197#define GRBM_STATUS_SE1__DB_BUSY_MASK 0x40000000L 198#define GRBM_STATUS_SE1__CB_BUSY_MASK 0x80000000L 199//GRBM_SOFT_RESET 200#define GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT 0x0 201#define GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT 0x2 202#define GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT 0x10 203#define GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT 0x11 204#define GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT 0x12 205#define GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT 0x13 206#define GRBM_SOFT_RESET__SOFT_RESET_CAC__SHIFT 0x14 207#define GRBM_SOFT_RESET__SOFT_RESET_CPAXI__SHIFT 0x15 208#define GRBM_SOFT_RESET__SOFT_RESET_EA__SHIFT 0x16 209#define GRBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x00000001L 210#define GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK 0x00000004L 211#define GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK 0x00010000L 212#define GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK 0x00020000L 213#define GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK 0x00040000L 214#define GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK 0x00080000L 215#define GRBM_SOFT_RESET__SOFT_RESET_CAC_MASK 0x00100000L 216#define GRBM_SOFT_RESET__SOFT_RESET_CPAXI_MASK 0x00200000L 217#define GRBM_SOFT_RESET__SOFT_RESET_EA_MASK 0x00400000L 218//GRBM_CGTT_CLK_CNTL 219#define GRBM_CGTT_CLK_CNTL__ON_DELAY__SHIFT 0x0 220#define GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS__SHIFT 0x4 221#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 222#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 223#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 224#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 225#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 226#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 227#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 228#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 229#define GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN__SHIFT 0x1e 230#define GRBM_CGTT_CLK_CNTL__ON_DELAY_MASK 0x0000000FL 231#define GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS_MASK 0x00000FF0L 232#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L 233#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L 234#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L 235#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L 236#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L 237#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L 238#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L 239#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L 240#define GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN_MASK 0x40000000L 241//GRBM_GFX_CLKEN_CNTL 242#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 243#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 244#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000FL 245#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001F00L 246//GRBM_WAIT_IDLE_CLOCKS 247#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT 0x0 248#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK 0x000000FFL 249//GRBM_STATUS_SE2 250#define GRBM_STATUS_SE2__DB_CLEAN__SHIFT 0x1 251#define GRBM_STATUS_SE2__CB_CLEAN__SHIFT 0x2 252#define GRBM_STATUS_SE2__RMI_BUSY__SHIFT 0x15 253#define GRBM_STATUS_SE2__BCI_BUSY__SHIFT 0x16 254#define GRBM_STATUS_SE2__VGT_BUSY__SHIFT 0x17 255#define GRBM_STATUS_SE2__PA_BUSY__SHIFT 0x18 256#define GRBM_STATUS_SE2__TA_BUSY__SHIFT 0x19 257#define GRBM_STATUS_SE2__SX_BUSY__SHIFT 0x1a 258#define GRBM_STATUS_SE2__SPI_BUSY__SHIFT 0x1b 259#define GRBM_STATUS_SE2__SC_BUSY__SHIFT 0x1d 260#define GRBM_STATUS_SE2__DB_BUSY__SHIFT 0x1e 261#define GRBM_STATUS_SE2__CB_BUSY__SHIFT 0x1f 262#define GRBM_STATUS_SE2__DB_CLEAN_MASK 0x00000002L 263#define GRBM_STATUS_SE2__CB_CLEAN_MASK 0x00000004L 264#define GRBM_STATUS_SE2__RMI_BUSY_MASK 0x00200000L 265#define GRBM_STATUS_SE2__BCI_BUSY_MASK 0x00400000L 266#define GRBM_STATUS_SE2__VGT_BUSY_MASK 0x00800000L 267#define GRBM_STATUS_SE2__PA_BUSY_MASK 0x01000000L 268#define GRBM_STATUS_SE2__TA_BUSY_MASK 0x02000000L 269#define GRBM_STATUS_SE2__SX_BUSY_MASK 0x04000000L 270#define GRBM_STATUS_SE2__SPI_BUSY_MASK 0x08000000L 271#define GRBM_STATUS_SE2__SC_BUSY_MASK 0x20000000L 272#define GRBM_STATUS_SE2__DB_BUSY_MASK 0x40000000L 273#define GRBM_STATUS_SE2__CB_BUSY_MASK 0x80000000L 274//GRBM_STATUS_SE3 275#define GRBM_STATUS_SE3__DB_CLEAN__SHIFT 0x1 276#define GRBM_STATUS_SE3__CB_CLEAN__SHIFT 0x2 277#define GRBM_STATUS_SE3__RMI_BUSY__SHIFT 0x15 278#define GRBM_STATUS_SE3__BCI_BUSY__SHIFT 0x16 279#define GRBM_STATUS_SE3__VGT_BUSY__SHIFT 0x17 280#define GRBM_STATUS_SE3__PA_BUSY__SHIFT 0x18 281#define GRBM_STATUS_SE3__TA_BUSY__SHIFT 0x19 282#define GRBM_STATUS_SE3__SX_BUSY__SHIFT 0x1a 283#define GRBM_STATUS_SE3__SPI_BUSY__SHIFT 0x1b 284#define GRBM_STATUS_SE3__SC_BUSY__SHIFT 0x1d 285#define GRBM_STATUS_SE3__DB_BUSY__SHIFT 0x1e 286#define GRBM_STATUS_SE3__CB_BUSY__SHIFT 0x1f 287#define GRBM_STATUS_SE3__DB_CLEAN_MASK 0x00000002L 288#define GRBM_STATUS_SE3__CB_CLEAN_MASK 0x00000004L 289#define GRBM_STATUS_SE3__RMI_BUSY_MASK 0x00200000L 290#define GRBM_STATUS_SE3__BCI_BUSY_MASK 0x00400000L 291#define GRBM_STATUS_SE3__VGT_BUSY_MASK 0x00800000L 292#define GRBM_STATUS_SE3__PA_BUSY_MASK 0x01000000L 293#define GRBM_STATUS_SE3__TA_BUSY_MASK 0x02000000L 294#define GRBM_STATUS_SE3__SX_BUSY_MASK 0x04000000L 295#define GRBM_STATUS_SE3__SPI_BUSY_MASK 0x08000000L 296#define GRBM_STATUS_SE3__SC_BUSY_MASK 0x20000000L 297#define GRBM_STATUS_SE3__DB_BUSY_MASK 0x40000000L 298#define GRBM_STATUS_SE3__CB_BUSY_MASK 0x80000000L 299//GRBM_READ_ERROR 300#define GRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2 301#define GRBM_READ_ERROR__READ_PIPEID__SHIFT 0x14 302#define GRBM_READ_ERROR__READ_MEID__SHIFT 0x16 303#define GRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f 304#define GRBM_READ_ERROR__READ_ADDRESS_MASK 0x0003FFFCL 305#define GRBM_READ_ERROR__READ_PIPEID_MASK 0x00300000L 306#define GRBM_READ_ERROR__READ_MEID_MASK 0x00C00000L 307#define GRBM_READ_ERROR__READ_ERROR_MASK 0x80000000L 308//GRBM_READ_ERROR2 309#define GRBM_READ_ERROR2__READ_REQUESTER_CPF__SHIFT 0x10 310#define GRBM_READ_ERROR2__READ_REQUESTER_RSMU__SHIFT 0x11 311#define GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT 0x12 312#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT 0x13 313#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT 0x14 314#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT 0x15 315#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT 0x16 316#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT 0x17 317#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT 0x18 318#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT 0x19 319#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT 0x1a 320#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT 0x1b 321#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT 0x1c 322#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT 0x1d 323#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT 0x1e 324#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT 0x1f 325#define GRBM_READ_ERROR2__READ_REQUESTER_CPF_MASK 0x00010000L 326#define GRBM_READ_ERROR2__READ_REQUESTER_RSMU_MASK 0x00020000L 327#define GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK 0x00040000L 328#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK 0x00080000L 329#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK 0x00100000L 330#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK 0x00200000L 331#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK 0x00400000L 332#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK 0x00800000L 333#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK 0x01000000L 334#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK 0x02000000L 335#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK 0x04000000L 336#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK 0x08000000L 337#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK 0x10000000L 338#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK 0x20000000L 339#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK 0x40000000L 340#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK 0x80000000L 341//GRBM_INT_CNTL 342#define GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT 0x0 343#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT 0x13 344#define GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK 0x00000001L 345#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK 0x00080000L 346//GRBM_TRAP_OP 347#define GRBM_TRAP_OP__RW__SHIFT 0x0 348#define GRBM_TRAP_OP__RW_MASK 0x00000001L 349//GRBM_TRAP_ADDR 350#define GRBM_TRAP_ADDR__DATA__SHIFT 0x0 351#define GRBM_TRAP_ADDR__DATA_MASK 0x0003FFFFL 352//GRBM_TRAP_ADDR_MSK 353#define GRBM_TRAP_ADDR_MSK__DATA__SHIFT 0x0 354#define GRBM_TRAP_ADDR_MSK__DATA_MASK 0x0003FFFFL 355//GRBM_TRAP_WD 356#define GRBM_TRAP_WD__DATA__SHIFT 0x0 357#define GRBM_TRAP_WD__DATA_MASK 0xFFFFFFFFL 358//GRBM_TRAP_WD_MSK 359#define GRBM_TRAP_WD_MSK__DATA__SHIFT 0x0 360#define GRBM_TRAP_WD_MSK__DATA_MASK 0xFFFFFFFFL 361//GRBM_DSM_BYPASS 362#define GRBM_DSM_BYPASS__BYPASS_BITS__SHIFT 0x0 363#define GRBM_DSM_BYPASS__BYPASS_EN__SHIFT 0x2 364#define GRBM_DSM_BYPASS__BYPASS_BITS_MASK 0x00000003L 365#define GRBM_DSM_BYPASS__BYPASS_EN_MASK 0x00000004L 366//GRBM_WRITE_ERROR 367#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC__SHIFT 0x0 368#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RSMU__SHIFT 0x1 369#define GRBM_WRITE_ERROR__WRITE_SSRCID__SHIFT 0x2 370#define GRBM_WRITE_ERROR__WRITE_VFID__SHIFT 0x5 371#define GRBM_WRITE_ERROR__WRITE_VF__SHIFT 0xc 372#define GRBM_WRITE_ERROR__WRITE_VMID__SHIFT 0xd 373#define GRBM_WRITE_ERROR__WRITE_PIPEID__SHIFT 0x14 374#define GRBM_WRITE_ERROR__WRITE_MEID__SHIFT 0x16 375#define GRBM_WRITE_ERROR__WRITE_ERROR__SHIFT 0x1f 376#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC_MASK 0x00000001L 377#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RSMU_MASK 0x00000002L 378#define GRBM_WRITE_ERROR__WRITE_SSRCID_MASK 0x0000001CL 379#define GRBM_WRITE_ERROR__WRITE_VFID_MASK 0x000001E0L 380#define GRBM_WRITE_ERROR__WRITE_VF_MASK 0x00001000L 381#define GRBM_WRITE_ERROR__WRITE_VMID_MASK 0x0001E000L 382#define GRBM_WRITE_ERROR__WRITE_PIPEID_MASK 0x00300000L 383#define GRBM_WRITE_ERROR__WRITE_MEID_MASK 0x00C00000L 384#define GRBM_WRITE_ERROR__WRITE_ERROR_MASK 0x80000000L 385//GRBM_IOV_ERROR 386#define GRBM_IOV_ERROR__IOV_ADDR__SHIFT 0x2 387#define GRBM_IOV_ERROR__IOV_VFID__SHIFT 0x14 388#define GRBM_IOV_ERROR__IOV_VF__SHIFT 0x1a 389#define GRBM_IOV_ERROR__IOV_OP__SHIFT 0x1b 390#define GRBM_IOV_ERROR__IOV_ERROR__SHIFT 0x1f 391#define GRBM_IOV_ERROR__IOV_ADDR_MASK 0x000FFFFCL 392#define GRBM_IOV_ERROR__IOV_VFID_MASK 0x03F00000L 393#define GRBM_IOV_ERROR__IOV_VF_MASK 0x04000000L 394#define GRBM_IOV_ERROR__IOV_OP_MASK 0x08000000L 395#define GRBM_IOV_ERROR__IOV_ERROR_MASK 0x80000000L 396//GRBM_CHIP_REVISION 397#define GRBM_CHIP_REVISION__CHIP_REVISION__SHIFT 0x0 398#define GRBM_CHIP_REVISION__CHIP_REVISION_MASK 0x000000FFL 399//GRBM_GFX_CNTL 400#define GRBM_GFX_CNTL__PIPEID__SHIFT 0x0 401#define GRBM_GFX_CNTL__MEID__SHIFT 0x2 402#define GRBM_GFX_CNTL__VMID__SHIFT 0x4 403#define GRBM_GFX_CNTL__QUEUEID__SHIFT 0x8 404#define GRBM_GFX_CNTL__PIPEID_MASK 0x00000003L 405#define GRBM_GFX_CNTL__MEID_MASK 0x0000000CL 406#define GRBM_GFX_CNTL__VMID_MASK 0x000000F0L 407#define GRBM_GFX_CNTL__QUEUEID_MASK 0x00000700L 408//GRBM_RSMU_CFG 409#define GRBM_RSMU_CFG__APERTURE_ID__SHIFT 0x0 410#define GRBM_RSMU_CFG__QOS__SHIFT 0xc 411#define GRBM_RSMU_CFG__POSTED_WR__SHIFT 0x10 412#define GRBM_RSMU_CFG__APERTURE_ID_MASK 0x00000FFFL 413#define GRBM_RSMU_CFG__QOS_MASK 0x0000F000L 414#define GRBM_RSMU_CFG__POSTED_WR_MASK 0x00010000L 415//GRBM_IH_CREDIT 416#define GRBM_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 417#define GRBM_IH_CREDIT__IH_CLIENT_ID__SHIFT 0x10 418#define GRBM_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L 419#define GRBM_IH_CREDIT__IH_CLIENT_ID_MASK 0x00FF0000L 420//GRBM_PWR_CNTL2 421#define GRBM_PWR_CNTL2__PWR_REQUEST_HALT__SHIFT 0x10 422#define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT__SHIFT 0x14 423#define GRBM_PWR_CNTL2__PWR_REQUEST_HALT_MASK 0x00010000L 424#define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT_MASK 0x00100000L 425//GRBM_UTCL2_INVAL_RANGE_START 426#define GRBM_UTCL2_INVAL_RANGE_START__DATA__SHIFT 0x0 427#define GRBM_UTCL2_INVAL_RANGE_START__DATA_MASK 0x0003FFFFL 428//GRBM_UTCL2_INVAL_RANGE_END 429#define GRBM_UTCL2_INVAL_RANGE_END__DATA__SHIFT 0x0 430#define GRBM_UTCL2_INVAL_RANGE_END__DATA_MASK 0x0003FFFFL 431//GRBM_RSMU_READ_ERROR 432#define GRBM_RSMU_READ_ERROR__RSMU_READ_ADDRESS__SHIFT 0x2 433#define GRBM_RSMU_READ_ERROR__RSMU_READ_VF__SHIFT 0x14 434#define GRBM_RSMU_READ_ERROR__RSMU_READ_VFID__SHIFT 0x15 435#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_TYPE__SHIFT 0x1b 436#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR__SHIFT 0x1f 437#define GRBM_RSMU_READ_ERROR__RSMU_READ_ADDRESS_MASK 0x000FFFFCL 438#define GRBM_RSMU_READ_ERROR__RSMU_READ_VF_MASK 0x00100000L 439#define GRBM_RSMU_READ_ERROR__RSMU_READ_VFID_MASK 0x07E00000L 440#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_TYPE_MASK 0x08000000L 441#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_MASK 0x80000000L 442//GRBM_CHICKEN_BITS 443#define GRBM_CHICKEN_BITS__DISABLE_CP_VMID_RESET_REQ__SHIFT 0x0 444#define GRBM_CHICKEN_BITS__DISABLE_CP_VMID_RESET_REQ_MASK 0x00000001L 445//GRBM_NOWHERE 446#define GRBM_NOWHERE__DATA__SHIFT 0x0 447#define GRBM_NOWHERE__DATA_MASK 0xFFFFFFFFL 448//GRBM_SCRATCH_REG0 449#define GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0 450#define GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK 0xFFFFFFFFL 451//GRBM_SCRATCH_REG1 452#define GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0 453#define GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK 0xFFFFFFFFL 454//GRBM_SCRATCH_REG2 455#define GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0 456#define GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK 0xFFFFFFFFL 457//GRBM_SCRATCH_REG3 458#define GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0 459#define GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK 0xFFFFFFFFL 460//GRBM_SCRATCH_REG4 461#define GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0 462#define GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK 0xFFFFFFFFL 463//GRBM_SCRATCH_REG5 464#define GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0 465#define GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK 0xFFFFFFFFL 466//GRBM_SCRATCH_REG6 467#define GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0 468#define GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK 0xFFFFFFFFL 469//GRBM_SCRATCH_REG7 470#define GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0 471#define GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK 0xFFFFFFFFL 472 473 474// addressBlock: gc_cpdec 475//CP_CPC_STATUS 476#define CP_CPC_STATUS__MEC1_BUSY__SHIFT 0x0 477#define CP_CPC_STATUS__MEC2_BUSY__SHIFT 0x1 478#define CP_CPC_STATUS__DC0_BUSY__SHIFT 0x2 479#define CP_CPC_STATUS__DC1_BUSY__SHIFT 0x3 480#define CP_CPC_STATUS__RCIU1_BUSY__SHIFT 0x4 481#define CP_CPC_STATUS__RCIU2_BUSY__SHIFT 0x5 482#define CP_CPC_STATUS__ROQ1_BUSY__SHIFT 0x6 483#define CP_CPC_STATUS__ROQ2_BUSY__SHIFT 0x7 484#define CP_CPC_STATUS__TCIU_BUSY__SHIFT 0xa 485#define CP_CPC_STATUS__SCRATCH_RAM_BUSY__SHIFT 0xb 486#define CP_CPC_STATUS__QU_BUSY__SHIFT 0xc 487#define CP_CPC_STATUS__UTCL2IU_BUSY__SHIFT 0xd 488#define CP_CPC_STATUS__SAVE_RESTORE_BUSY__SHIFT 0xe 489#define CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT 0x1d 490#define CP_CPC_STATUS__CPF_CPC_BUSY__SHIFT 0x1e 491#define CP_CPC_STATUS__CPC_BUSY__SHIFT 0x1f 492#define CP_CPC_STATUS__MEC1_BUSY_MASK 0x00000001L 493#define CP_CPC_STATUS__MEC2_BUSY_MASK 0x00000002L 494#define CP_CPC_STATUS__DC0_BUSY_MASK 0x00000004L 495#define CP_CPC_STATUS__DC1_BUSY_MASK 0x00000008L 496#define CP_CPC_STATUS__RCIU1_BUSY_MASK 0x00000010L 497#define CP_CPC_STATUS__RCIU2_BUSY_MASK 0x00000020L 498#define CP_CPC_STATUS__ROQ1_BUSY_MASK 0x00000040L 499#define CP_CPC_STATUS__ROQ2_BUSY_MASK 0x00000080L 500#define CP_CPC_STATUS__TCIU_BUSY_MASK 0x00000400L 501#define CP_CPC_STATUS__SCRATCH_RAM_BUSY_MASK 0x00000800L 502#define CP_CPC_STATUS__QU_BUSY_MASK 0x00001000L 503#define CP_CPC_STATUS__UTCL2IU_BUSY_MASK 0x00002000L 504#define CP_CPC_STATUS__SAVE_RESTORE_BUSY_MASK 0x00004000L 505#define CP_CPC_STATUS__CPG_CPC_BUSY_MASK 0x20000000L 506#define CP_CPC_STATUS__CPF_CPC_BUSY_MASK 0x40000000L 507#define CP_CPC_STATUS__CPC_BUSY_MASK 0x80000000L 508//CP_CPC_BUSY_STAT 509#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT 0x0 510#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY__SHIFT 0x1 511#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT 0x2 512#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT 0x3 513#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT 0x4 514#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT 0x5 515#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT 0x6 516#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY__SHIFT 0x7 517#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY__SHIFT 0x8 518#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT 0x9 519#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT 0xa 520#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT 0xb 521#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT 0xc 522#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT 0xd 523#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT 0x10 524#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY__SHIFT 0x11 525#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT 0x12 526#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT 0x13 527#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT 0x14 528#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT 0x15 529#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT 0x16 530#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY__SHIFT 0x17 531#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY__SHIFT 0x18 532#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT 0x19 533#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT 0x1a 534#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT 0x1b 535#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT 0x1c 536#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT 0x1d 537#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY_MASK 0x00000001L 538#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY_MASK 0x00000002L 539#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY_MASK 0x00000004L 540#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK 0x00000008L 541#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK 0x00000010L 542#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK 0x00000020L 543#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK 0x00000040L 544#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY_MASK 0x00000080L 545#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY_MASK 0x00000100L 546#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK 0x00000200L 547#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK 0x00000400L 548#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK 0x00000800L 549#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY_MASK 0x00001000L 550#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY_MASK 0x00002000L 551#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY_MASK 0x00010000L 552#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY_MASK 0x00020000L 553#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY_MASK 0x00040000L 554#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK 0x00080000L 555#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK 0x00100000L 556#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK 0x00200000L 557#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK 0x00400000L 558#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY_MASK 0x00800000L 559#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY_MASK 0x01000000L 560#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK 0x02000000L 561#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY_MASK 0x04000000L 562#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY_MASK 0x08000000L 563#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY_MASK 0x10000000L 564#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY_MASK 0x20000000L 565//CP_CPC_STALLED_STAT1 566#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT 0x3 567#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT 0x4 568#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT 0x6 569#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT 0x8 570#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT 0x9 571#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT 0xa 572#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT 0xd 573#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT 0x10 574#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT 0x11 575#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT 0x12 576#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT 0x15 577#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT 0x16 578#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x17 579#define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS__SHIFT 0x18 580#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK 0x00000008L 581#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK 0x00000010L 582#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK 0x00000040L 583#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET_MASK 0x00000100L 584#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK 0x00000200L 585#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK 0x00000400L 586#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK 0x00002000L 587#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET_MASK 0x00010000L 588#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK 0x00020000L 589#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK 0x00040000L 590#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK 0x00200000L 591#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK 0x00400000L 592#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK 0x00800000L 593#define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS_MASK 0x01000000L 594//CP_CPF_STATUS 595#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY__SHIFT 0x0 596#define CP_CPF_STATUS__CSF_BUSY__SHIFT 0x1 597#define CP_CPF_STATUS__ROQ_ALIGN_BUSY__SHIFT 0x4 598#define CP_CPF_STATUS__ROQ_RING_BUSY__SHIFT 0x5 599#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY__SHIFT 0x6 600#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY__SHIFT 0x7 601#define CP_CPF_STATUS__ROQ_STATE_BUSY__SHIFT 0x8 602#define CP_CPF_STATUS__ROQ_CE_RING_BUSY__SHIFT 0x9 603#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT 0xa 604#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY__SHIFT 0xb 605#define CP_CPF_STATUS__SEMAPHORE_BUSY__SHIFT 0xc 606#define CP_CPF_STATUS__INTERRUPT_BUSY__SHIFT 0xd 607#define CP_CPF_STATUS__TCIU_BUSY__SHIFT 0xe 608#define CP_CPF_STATUS__HQD_BUSY__SHIFT 0xf 609#define CP_CPF_STATUS__PRT_BUSY__SHIFT 0x10 610#define CP_CPF_STATUS__UTCL2IU_BUSY__SHIFT 0x11 611#define CP_CPF_STATUS__CPF_GFX_BUSY__SHIFT 0x1a 612#define CP_CPF_STATUS__CPF_CMP_BUSY__SHIFT 0x1b 613#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY__SHIFT 0x1c 614#define CP_CPF_STATUS__CPC_CPF_BUSY__SHIFT 0x1e 615#define CP_CPF_STATUS__CPF_BUSY__SHIFT 0x1f 616#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY_MASK 0x00000001L 617#define CP_CPF_STATUS__CSF_BUSY_MASK 0x00000002L 618#define CP_CPF_STATUS__ROQ_ALIGN_BUSY_MASK 0x00000010L 619#define CP_CPF_STATUS__ROQ_RING_BUSY_MASK 0x00000020L 620#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY_MASK 0x00000040L 621#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY_MASK 0x00000080L 622#define CP_CPF_STATUS__ROQ_STATE_BUSY_MASK 0x00000100L 623#define CP_CPF_STATUS__ROQ_CE_RING_BUSY_MASK 0x00000200L 624#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY_MASK 0x00000400L 625#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY_MASK 0x00000800L 626#define CP_CPF_STATUS__SEMAPHORE_BUSY_MASK 0x00001000L 627#define CP_CPF_STATUS__INTERRUPT_BUSY_MASK 0x00002000L 628#define CP_CPF_STATUS__TCIU_BUSY_MASK 0x00004000L 629#define CP_CPF_STATUS__HQD_BUSY_MASK 0x00008000L 630#define CP_CPF_STATUS__PRT_BUSY_MASK 0x00010000L 631#define CP_CPF_STATUS__UTCL2IU_BUSY_MASK 0x00020000L 632#define CP_CPF_STATUS__CPF_GFX_BUSY_MASK 0x04000000L 633#define CP_CPF_STATUS__CPF_CMP_BUSY_MASK 0x08000000L 634#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY_MASK 0x30000000L 635#define CP_CPF_STATUS__CPC_CPF_BUSY_MASK 0x40000000L 636#define CP_CPF_STATUS__CPF_BUSY_MASK 0x80000000L 637//CP_CPF_BUSY_STAT 638#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0 639#define CP_CPF_BUSY_STAT__CSF_RING_BUSY__SHIFT 0x1 640#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY__SHIFT 0x2 641#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY__SHIFT 0x3 642#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY__SHIFT 0x4 643#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY__SHIFT 0x5 644#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY__SHIFT 0x6 645#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY__SHIFT 0x7 646#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY__SHIFT 0x8 647#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS__SHIFT 0x9 648#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY__SHIFT 0xb 649#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY__SHIFT 0xc 650#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY__SHIFT 0xd 651#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY__SHIFT 0xe 652#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY__SHIFT 0xf 653#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY__SHIFT 0x10 654#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY__SHIFT 0x11 655#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY__SHIFT 0x12 656#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY__SHIFT 0x13 657#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY__SHIFT 0x14 658#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY__SHIFT 0x15 659#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY__SHIFT 0x16 660#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY__SHIFT 0x17 661#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY__SHIFT 0x18 662#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY__SHIFT 0x19 663#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY__SHIFT 0x1a 664#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY__SHIFT 0x1b 665#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY__SHIFT 0x1c 666#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT 0x1d 667#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY__SHIFT 0x1e 668#define CP_CPF_BUSY_STAT__HQD_IB_BUSY__SHIFT 0x1f 669#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x00000001L 670#define CP_CPF_BUSY_STAT__CSF_RING_BUSY_MASK 0x00000002L 671#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY_MASK 0x00000004L 672#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY_MASK 0x00000008L 673#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY_MASK 0x00000010L 674#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY_MASK 0x00000020L 675#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY_MASK 0x00000040L 676#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY_MASK 0x00000080L 677#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY_MASK 0x00000100L 678#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS_MASK 0x00000200L 679#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY_MASK 0x00000800L 680#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY_MASK 0x00001000L 681#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY_MASK 0x00002000L 682#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY_MASK 0x00004000L 683#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY_MASK 0x00008000L 684#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY_MASK 0x00010000L 685#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY_MASK 0x00020000L 686#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY_MASK 0x00040000L 687#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY_MASK 0x00080000L 688#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY_MASK 0x00100000L 689#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY_MASK 0x00200000L 690#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY_MASK 0x00400000L 691#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY_MASK 0x00800000L 692#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY_MASK 0x01000000L 693#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY_MASK 0x02000000L 694#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY_MASK 0x04000000L 695#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY_MASK 0x08000000L 696#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY_MASK 0x10000000L 697#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY_MASK 0x20000000L 698#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY_MASK 0x40000000L 699#define CP_CPF_BUSY_STAT__HQD_IB_BUSY_MASK 0x80000000L 700//CP_CPF_STALLED_STAT1 701#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA__SHIFT 0x0 702#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA__SHIFT 0x1 703#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA__SHIFT 0x2 704#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA__SHIFT 0x3 705#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE__SHIFT 0x5 706#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT 0x6 707#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT 0x7 708#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x8 709#define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS__SHIFT 0x9 710#define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS__SHIFT 0xa 711#define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE__SHIFT 0xb 712#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA_MASK 0x00000001L 713#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA_MASK 0x00000002L 714#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA_MASK 0x00000004L 715#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA_MASK 0x00000008L 716#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE_MASK 0x00000020L 717#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK 0x00000040L 718#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK 0x00000080L 719#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK 0x00000100L 720#define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS_MASK 0x00000200L 721#define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS_MASK 0x00000400L 722#define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE_MASK 0x00000800L 723//CP_CPC_GRBM_FREE_COUNT 724#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0 725#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x0000003FL 726//CP_MEC_CNTL 727#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE__SHIFT 0x4 728#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET__SHIFT 0x10 729#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET__SHIFT 0x11 730#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET__SHIFT 0x12 731#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET__SHIFT 0x13 732#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET__SHIFT 0x14 733#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET__SHIFT 0x15 734#define CP_MEC_CNTL__MEC_ME2_HALT__SHIFT 0x1c 735#define CP_MEC_CNTL__MEC_ME2_STEP__SHIFT 0x1d 736#define CP_MEC_CNTL__MEC_ME1_HALT__SHIFT 0x1e 737#define CP_MEC_CNTL__MEC_ME1_STEP__SHIFT 0x1f 738#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK 0x00000010L 739#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK 0x00010000L 740#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK 0x00020000L 741#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK 0x00040000L 742#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK 0x00080000L 743#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK 0x00100000L 744#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK 0x00200000L 745#define CP_MEC_CNTL__MEC_ME2_HALT_MASK 0x10000000L 746#define CP_MEC_CNTL__MEC_ME2_STEP_MASK 0x20000000L 747#define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000L 748#define CP_MEC_CNTL__MEC_ME1_STEP_MASK 0x80000000L 749//CP_MEC_ME1_HEADER_DUMP 750#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0 751#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP_MASK 0xFFFFFFFFL 752//CP_MEC_ME2_HEADER_DUMP 753#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0 754#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP_MASK 0xFFFFFFFFL 755//CP_CPC_SCRATCH_INDEX 756#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0 757#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000001FFL 758//CP_CPC_SCRATCH_DATA 759#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0 760#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL 761//CP_CPF_GRBM_FREE_COUNT 762#define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0 763#define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x00000007L 764//CP_CPC_HALT_HYST_COUNT 765#define CP_CPC_HALT_HYST_COUNT__COUNT__SHIFT 0x0 766#define CP_CPC_HALT_HYST_COUNT__COUNT_MASK 0x0000000FL 767//CP_PRT_LOD_STATS_CNTL0 768#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE__SHIFT 0x0 769#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE_MASK 0xFFFFFFFFL 770//CP_PRT_LOD_STATS_CNTL1 771#define CP_PRT_LOD_STATS_CNTL1__BASE_LO__SHIFT 0x0 772#define CP_PRT_LOD_STATS_CNTL1__BASE_LO_MASK 0xFFFFFFFFL 773//CP_PRT_LOD_STATS_CNTL2 774#define CP_PRT_LOD_STATS_CNTL2__BASE_HI__SHIFT 0x0 775#define CP_PRT_LOD_STATS_CNTL2__BASE_HI_MASK 0x000003FFL 776//CP_PRT_LOD_STATS_CNTL3 777#define CP_PRT_LOD_STATS_CNTL3__INTERVAL__SHIFT 0x2 778#define CP_PRT_LOD_STATS_CNTL3__RESET_CNT__SHIFT 0xa 779#define CP_PRT_LOD_STATS_CNTL3__RESET_FORCE__SHIFT 0x12 780#define CP_PRT_LOD_STATS_CNTL3__REPORT_AND_RESET__SHIFT 0x13 781#define CP_PRT_LOD_STATS_CNTL3__MC_VMID__SHIFT 0x17 782#define CP_PRT_LOD_STATS_CNTL3__CACHE_POLICY__SHIFT 0x1c 783#define CP_PRT_LOD_STATS_CNTL3__INTERVAL_MASK 0x000003FCL 784#define CP_PRT_LOD_STATS_CNTL3__RESET_CNT_MASK 0x0003FC00L 785#define CP_PRT_LOD_STATS_CNTL3__RESET_FORCE_MASK 0x00040000L 786#define CP_PRT_LOD_STATS_CNTL3__REPORT_AND_RESET_MASK 0x00080000L 787#define CP_PRT_LOD_STATS_CNTL3__MC_VMID_MASK 0x07800000L 788#define CP_PRT_LOD_STATS_CNTL3__CACHE_POLICY_MASK 0x10000000L 789//CP_CE_COMPARE_COUNT 790#define CP_CE_COMPARE_COUNT__COMPARE_COUNT__SHIFT 0x0 791#define CP_CE_COMPARE_COUNT__COMPARE_COUNT_MASK 0xFFFFFFFFL 792//CP_CE_DE_COUNT 793#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0 794#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xFFFFFFFFL 795//CP_DE_CE_COUNT 796#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT__SHIFT 0x0 797#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT_MASK 0xFFFFFFFFL 798//CP_DE_LAST_INVAL_COUNT 799#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT__SHIFT 0x0 800#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT_MASK 0xFFFFFFFFL 801//CP_DE_DE_COUNT 802#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0 803#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xFFFFFFFFL 804//CP_STALLED_STAT3 805#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0 806#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT 0x1 807#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT 0x2 808#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT 0x3 809#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT 0x4 810#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT 0x5 811#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT 0x6 812#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT 0x7 813#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT 0xa 814#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT 0xb 815#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT 0xc 816#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT 0xd 817#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT 0xe 818#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT 0xf 819#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x10 820#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x11 821#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE__SHIFT 0x12 822#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x13 823#define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS__SHIFT 0x14 824#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L 825#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK 0x00000002L 826#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK 0x00000004L 827#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK 0x00000008L 828#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK 0x00000010L 829#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK 0x00000020L 830#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK 0x00000040L 831#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK 0x00000080L 832#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK 0x00000400L 833#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK 0x00000800L 834#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK 0x00001000L 835#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK 0x00002000L 836#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK 0x00004000L 837#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK 0x00008000L 838#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM_MASK 0x00010000L 839#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00020000L 840#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE_MASK 0x00040000L 841#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS_MASK 0x00080000L 842#define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS_MASK 0x00100000L 843//CP_STALLED_STAT1 844#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT 0x0 845#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV__SHIFT 0x2 846#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV__SHIFT 0x4 847#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT 0xa 848#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT 0xb 849#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT 0xc 850#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0xd 851#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA__SHIFT 0xe 852#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT 0xf 853#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT 0x17 854#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT 0x18 855#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT 0x19 856#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT 0x1a 857#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT 0x1b 858#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT 0x1c 859#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT 0x1d 860#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK 0x00000001L 861#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_MASK 0x00000004L 862#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_MASK 0x00000010L 863#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK 0x00000400L 864#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK 0x00000800L 865#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK 0x00001000L 866#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00002000L 867#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA_MASK 0x00004000L 868#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK 0x00008000L 869#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK 0x00800000L 870#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK 0x01000000L 871#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK 0x02000000L 872#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK 0x04000000L 873#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK 0x08000000L 874#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK 0x10000000L 875#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK 0x20000000L 876//CP_STALLED_STAT2 877#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0 878#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT 0x1 879#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT 0x2 880#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT 0x4 881#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT 0x5 882#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT 0x8 883#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT 0x9 884#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT 0xa 885#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT 0xb 886#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT 0xc 887#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT 0xd 888#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT 0xe 889#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT 0xf 890#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x10 891#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x11 892#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT 0x12 893#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x13 894#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x14 895#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE__SHIFT 0x15 896#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM__SHIFT 0x16 897#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT 0x17 898#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT 0x18 899#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT 0x19 900#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT 0x1a 901#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT 0x1b 902#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT 0x1c 903#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT 0x1d 904#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT 0x1e 905#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT 0x1f 906#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L 907#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK 0x00000002L 908#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK 0x00000004L 909#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK 0x00000010L 910#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK 0x00000020L 911#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK 0x00000100L 912#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK 0x00000200L 913#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK 0x00000400L 914#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK 0x00000800L 915#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK 0x00001000L 916#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK 0x00002000L 917#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK 0x00004000L 918#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK 0x00008000L 919#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00010000L 920#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00020000L 921#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK 0x00040000L 922#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK 0x00080000L 923#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00100000L 924#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE_MASK 0x00200000L 925#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM_MASK 0x00400000L 926#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK 0x00800000L 927#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK 0x01000000L 928#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK 0x02000000L 929#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK 0x04000000L 930#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK 0x08000000L 931#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK 0x10000000L 932#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK 0x20000000L 933#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK 0x40000000L 934#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK 0x80000000L 935//CP_BUSY_STAT 936#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0 937#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT 0x6 938#define CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT 0x7 939#define CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT 0x8 940#define CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT 0x9 941#define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT 0xa 942#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT 0xc 943#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT 0xd 944#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT 0xe 945#define CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT 0xf 946#define CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT 0x11 947#define CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT 0x12 948#define CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT 0x13 949#define CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT 0x14 950#define CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT 0x15 951#define CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT 0x16 952#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x00000001L 953#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK 0x00000040L 954#define CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK 0x00000080L 955#define CP_BUSY_STAT__ME_PARSING_PACKETS_MASK 0x00000100L 956#define CP_BUSY_STAT__RCIU_PFP_BUSY_MASK 0x00000200L 957#define CP_BUSY_STAT__RCIU_ME_BUSY_MASK 0x00000400L 958#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK 0x00001000L 959#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK 0x00002000L 960#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK 0x00004000L 961#define CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK 0x00008000L 962#define CP_BUSY_STAT__ME_PARSER_BUSY_MASK 0x00020000L 963#define CP_BUSY_STAT__EOP_DONE_BUSY_MASK 0x00040000L 964#define CP_BUSY_STAT__STRM_OUT_BUSY_MASK 0x00080000L 965#define CP_BUSY_STAT__PIPE_STATS_BUSY_MASK 0x00100000L 966#define CP_BUSY_STAT__RCIU_CE_BUSY_MASK 0x00200000L 967#define CP_BUSY_STAT__CE_PARSING_PACKETS_MASK 0x00400000L 968//CP_STAT 969#define CP_STAT__ROQ_RING_BUSY__SHIFT 0x9 970#define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT 0xa 971#define CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT 0xb 972#define CP_STAT__ROQ_STATE_BUSY__SHIFT 0xc 973#define CP_STAT__DC_BUSY__SHIFT 0xd 974#define CP_STAT__UTCL2IU_BUSY__SHIFT 0xe 975#define CP_STAT__PFP_BUSY__SHIFT 0xf 976#define CP_STAT__MEQ_BUSY__SHIFT 0x10 977#define CP_STAT__ME_BUSY__SHIFT 0x11 978#define CP_STAT__QUERY_BUSY__SHIFT 0x12 979#define CP_STAT__SEMAPHORE_BUSY__SHIFT 0x13 980#define CP_STAT__INTERRUPT_BUSY__SHIFT 0x14 981#define CP_STAT__SURFACE_SYNC_BUSY__SHIFT 0x15 982#define CP_STAT__DMA_BUSY__SHIFT 0x16 983#define CP_STAT__RCIU_BUSY__SHIFT 0x17 984#define CP_STAT__SCRATCH_RAM_BUSY__SHIFT 0x18 985#define CP_STAT__CE_BUSY__SHIFT 0x1a 986#define CP_STAT__TCIU_BUSY__SHIFT 0x1b 987#define CP_STAT__ROQ_CE_RING_BUSY__SHIFT 0x1c 988#define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT 0x1d 989#define CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT 0x1e 990#define CP_STAT__CP_BUSY__SHIFT 0x1f 991#define CP_STAT__ROQ_RING_BUSY_MASK 0x00000200L 992#define CP_STAT__ROQ_INDIRECT1_BUSY_MASK 0x00000400L 993#define CP_STAT__ROQ_INDIRECT2_BUSY_MASK 0x00000800L 994#define CP_STAT__ROQ_STATE_BUSY_MASK 0x00001000L 995#define CP_STAT__DC_BUSY_MASK 0x00002000L 996#define CP_STAT__UTCL2IU_BUSY_MASK 0x00004000L 997#define CP_STAT__PFP_BUSY_MASK 0x00008000L 998#define CP_STAT__MEQ_BUSY_MASK 0x00010000L 999#define CP_STAT__ME_BUSY_MASK 0x00020000L 1000#define CP_STAT__QUERY_BUSY_MASK 0x00040000L
1001#define CP_STAT__SEMAPHORE_BUSY_MASK 0x00080000L 1002#define CP_STAT__INTERRUPT_BUSY_MASK 0x00100000L 1003#define CP_STAT__SURFACE_SYNC_BUSY_MASK 0x00200000L 1004#define CP_STAT__DMA_BUSY_MASK 0x00400000L 1005#define CP_STAT__RCIU_BUSY_MASK 0x00800000L 1006#define CP_STAT__SCRATCH_RAM_BUSY_MASK 0x01000000L 1007#define CP_STAT__CE_BUSY_MASK 0x04000000L 1008#define CP_STAT__TCIU_BUSY_MASK 0x08000000L 1009#define CP_STAT__ROQ_CE_RING_BUSY_MASK 0x10000000L 1010#define CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK 0x20000000L 1011#define CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK 0x40000000L 1012#define CP_STAT__CP_BUSY_MASK 0x80000000L 1013//CP_ME_HEADER_DUMP 1014#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP__SHIFT 0x0 1015#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP_MASK 0xFFFFFFFFL 1016//CP_PFP_HEADER_DUMP 1017#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP__SHIFT 0x0 1018#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP_MASK 0xFFFFFFFFL 1019//CP_GRBM_FREE_COUNT 1020#define CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0 1021#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT 0x8 1022#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT 0x10 1023#define CP_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x0000003FL 1024#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK 0x00003F00L 1025#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK 0x003F0000L 1026//CP_CE_HEADER_DUMP 1027#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP__SHIFT 0x0 1028#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP_MASK 0xFFFFFFFFL 1029//CP_PFP_INSTR_PNTR 1030#define CP_PFP_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 1031#define CP_PFP_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL 1032//CP_ME_INSTR_PNTR 1033#define CP_ME_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 1034#define CP_ME_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL 1035//CP_CE_INSTR_PNTR 1036#define CP_CE_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 1037#define CP_CE_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL 1038//CP_MEC1_INSTR_PNTR 1039#define CP_MEC1_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 1040#define CP_MEC1_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL 1041//CP_MEC2_INSTR_PNTR 1042#define CP_MEC2_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 1043#define CP_MEC2_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL 1044//CP_CSF_STAT 1045#define CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT 0x8 1046#define CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK 0x0001FF00L 1047//CP_ME_CNTL 1048#define CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT 0x4 1049#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT 0x6 1050#define CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT 0x8 1051#define CP_ME_CNTL__CE_PIPE0_RESET__SHIFT 0x10 1052#define CP_ME_CNTL__CE_PIPE1_RESET__SHIFT 0x11 1053#define CP_ME_CNTL__PFP_PIPE0_RESET__SHIFT 0x12 1054#define CP_ME_CNTL__PFP_PIPE1_RESET__SHIFT 0x13 1055#define CP_ME_CNTL__ME_PIPE0_RESET__SHIFT 0x14 1056#define CP_ME_CNTL__ME_PIPE1_RESET__SHIFT 0x15 1057#define CP_ME_CNTL__CE_HALT__SHIFT 0x18 1058#define CP_ME_CNTL__CE_STEP__SHIFT 0x19 1059#define CP_ME_CNTL__PFP_HALT__SHIFT 0x1a 1060#define CP_ME_CNTL__PFP_STEP__SHIFT 0x1b 1061#define CP_ME_CNTL__ME_HALT__SHIFT 0x1c 1062#define CP_ME_CNTL__ME_STEP__SHIFT 0x1d 1063#define CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK 0x00000010L 1064#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK 0x00000040L 1065#define CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK 0x00000100L 1066#define CP_ME_CNTL__CE_PIPE0_RESET_MASK 0x00010000L 1067#define CP_ME_CNTL__CE_PIPE1_RESET_MASK 0x00020000L 1068#define CP_ME_CNTL__PFP_PIPE0_RESET_MASK 0x00040000L 1069#define CP_ME_CNTL__PFP_PIPE1_RESET_MASK 0x00080000L 1070#define CP_ME_CNTL__ME_PIPE0_RESET_MASK 0x00100000L 1071#define CP_ME_CNTL__ME_PIPE1_RESET_MASK 0x00200000L 1072#define CP_ME_CNTL__CE_HALT_MASK 0x01000000L 1073#define CP_ME_CNTL__CE_STEP_MASK 0x02000000L 1074#define CP_ME_CNTL__PFP_HALT_MASK 0x04000000L 1075#define CP_ME_CNTL__PFP_STEP_MASK 0x08000000L 1076#define CP_ME_CNTL__ME_HALT_MASK 0x10000000L 1077#define CP_ME_CNTL__ME_STEP_MASK 0x20000000L 1078//CP_CNTX_STAT 1079#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT 0x0 1080#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT 0x8 1081#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT 0x14 1082#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT 0x1c 1083#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK 0x000000FFL 1084#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK 0x00000700L 1085#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK 0x0FF00000L 1086#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK 0x70000000L 1087//CP_ME_PREEMPTION 1088#define CP_ME_PREEMPTION__OBSOLETE__SHIFT 0x0 1089#define CP_ME_PREEMPTION__OBSOLETE_MASK 0x00000001L 1090//CP_ROQ_THRESHOLDS 1091#define CP_ROQ_THRESHOLDS__IB1_START__SHIFT 0x0 1092#define CP_ROQ_THRESHOLDS__IB2_START__SHIFT 0x8 1093#define CP_ROQ_THRESHOLDS__IB1_START_MASK 0x000000FFL 1094#define CP_ROQ_THRESHOLDS__IB2_START_MASK 0x0000FF00L 1095//CP_MEQ_STQ_THRESHOLD 1096#define CP_MEQ_STQ_THRESHOLD__STQ_START__SHIFT 0x0 1097#define CP_MEQ_STQ_THRESHOLD__STQ_START_MASK 0x000000FFL 1098//CP_RB2_RPTR 1099#define CP_RB2_RPTR__RB_RPTR__SHIFT 0x0 1100#define CP_RB2_RPTR__RB_RPTR_MASK 0x000FFFFFL 1101//CP_RB1_RPTR 1102#define CP_RB1_RPTR__RB_RPTR__SHIFT 0x0 1103#define CP_RB1_RPTR__RB_RPTR_MASK 0x000FFFFFL 1104//CP_RB0_RPTR 1105#define CP_RB0_RPTR__RB_RPTR__SHIFT 0x0 1106#define CP_RB0_RPTR__RB_RPTR_MASK 0x000FFFFFL 1107//CP_RB_RPTR 1108#define CP_RB_RPTR__RB_RPTR__SHIFT 0x0 1109#define CP_RB_RPTR__RB_RPTR_MASK 0x000FFFFFL 1110//CP_RB_WPTR_DELAY 1111#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x0 1112#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x1c 1113#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0x0FFFFFFFL 1114#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xF0000000L 1115//CP_RB_WPTR_POLL_CNTL 1116#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT 0x0 1117#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1118#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK 0x0000FFFFL 1119#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1120//CP_ROQ1_THRESHOLDS 1121#define CP_ROQ1_THRESHOLDS__RB1_START__SHIFT 0x0 1122#define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT 0x8 1123#define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT 0x10 1124#define CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT 0x18 1125#define CP_ROQ1_THRESHOLDS__RB1_START_MASK 0x000000FFL 1126#define CP_ROQ1_THRESHOLDS__RB2_START_MASK 0x0000FF00L 1127#define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK 0x00FF0000L 1128#define CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK 0xFF000000L 1129//CP_ROQ2_THRESHOLDS 1130#define CP_ROQ2_THRESHOLDS__R2_IB1_START__SHIFT 0x0 1131#define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT 0x8 1132#define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT 0x10 1133#define CP_ROQ2_THRESHOLDS__R2_IB2_START__SHIFT 0x18 1134#define CP_ROQ2_THRESHOLDS__R2_IB1_START_MASK 0x000000FFL 1135#define CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK 0x0000FF00L 1136#define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0x00FF0000L 1137#define CP_ROQ2_THRESHOLDS__R2_IB2_START_MASK 0xFF000000L 1138//CP_STQ_THRESHOLDS 1139#define CP_STQ_THRESHOLDS__STQ0_START__SHIFT 0x0 1140#define CP_STQ_THRESHOLDS__STQ1_START__SHIFT 0x8 1141#define CP_STQ_THRESHOLDS__STQ2_START__SHIFT 0x10 1142#define CP_STQ_THRESHOLDS__STQ0_START_MASK 0x000000FFL 1143#define CP_STQ_THRESHOLDS__STQ1_START_MASK 0x0000FF00L 1144#define CP_STQ_THRESHOLDS__STQ2_START_MASK 0x00FF0000L 1145//CP_QUEUE_THRESHOLDS 1146#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT 0x0 1147#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT 0x8 1148#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK 0x0000003FL 1149#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK 0x00003F00L 1150//CP_MEQ_THRESHOLDS 1151#define CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT 0x0 1152#define CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT 0x8 1153#define CP_MEQ_THRESHOLDS__MEQ1_START_MASK 0x000000FFL 1154#define CP_MEQ_THRESHOLDS__MEQ2_START_MASK 0x0000FF00L 1155//CP_ROQ_AVAIL 1156#define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT 0x0 1157#define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x10 1158#define CP_ROQ_AVAIL__ROQ_CNT_RING_MASK 0x000007FFL 1159#define CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK 0x07FF0000L 1160//CP_STQ_AVAIL 1161#define CP_STQ_AVAIL__STQ_CNT__SHIFT 0x0 1162#define CP_STQ_AVAIL__STQ_CNT_MASK 0x000001FFL 1163//CP_ROQ2_AVAIL 1164#define CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT 0x0 1165#define CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK 0x000007FFL 1166//CP_MEQ_AVAIL 1167#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x0 1168#define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x000003FFL 1169//CP_CMD_INDEX 1170#define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x0 1171#define CP_CMD_INDEX__CMD_ME_SEL__SHIFT 0xc 1172#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x10 1173#define CP_CMD_INDEX__CMD_INDEX_MASK 0x000007FFL 1174#define CP_CMD_INDEX__CMD_ME_SEL_MASK 0x00003000L 1175#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x00070000L 1176//CP_CMD_DATA 1177#define CP_CMD_DATA__CMD_DATA__SHIFT 0x0 1178#define CP_CMD_DATA__CMD_DATA_MASK 0xFFFFFFFFL 1179//CP_ROQ_RB_STAT 1180#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT 0x0 1181#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT 0x10 1182#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK 0x000003FFL 1183#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK 0x03FF0000L 1184//CP_ROQ_IB1_STAT 1185#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT 0x0 1186#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT 0x10 1187#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK 0x000003FFL 1188#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK 0x03FF0000L 1189//CP_ROQ_IB2_STAT 1190#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT 0x0 1191#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT 0x10 1192#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK 0x000003FFL 1193#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK 0x03FF0000L 1194//CP_STQ_STAT 1195#define CP_STQ_STAT__STQ_RPTR__SHIFT 0x0 1196#define CP_STQ_STAT__STQ_RPTR_MASK 0x000003FFL 1197//CP_STQ_WR_STAT 1198#define CP_STQ_WR_STAT__STQ_WPTR__SHIFT 0x0 1199#define CP_STQ_WR_STAT__STQ_WPTR_MASK 0x000003FFL 1200//CP_MEQ_STAT 1201#define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x0 1202#define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x10 1203#define CP_MEQ_STAT__MEQ_RPTR_MASK 0x000003FFL 1204#define CP_MEQ_STAT__MEQ_WPTR_MASK 0x03FF0000L 1205//CP_CEQ1_AVAIL 1206#define CP_CEQ1_AVAIL__CEQ_CNT_RING__SHIFT 0x0 1207#define CP_CEQ1_AVAIL__CEQ_CNT_IB1__SHIFT 0x10 1208#define CP_CEQ1_AVAIL__CEQ_CNT_RING_MASK 0x000007FFL 1209#define CP_CEQ1_AVAIL__CEQ_CNT_IB1_MASK 0x07FF0000L 1210//CP_CEQ2_AVAIL 1211#define CP_CEQ2_AVAIL__CEQ_CNT_IB2__SHIFT 0x0 1212#define CP_CEQ2_AVAIL__CEQ_CNT_IB2_MASK 0x000007FFL 1213//CP_CE_ROQ_RB_STAT 1214#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 0x0 1215#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 0x10 1216#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY_MASK 0x000003FFL 1217#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK 0x03FF0000L 1218//CP_CE_ROQ_IB1_STAT 1219#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1__SHIFT 0x0 1220#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 0x10 1221#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1_MASK 0x000003FFL 1222#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1_MASK 0x03FF0000L 1223//CP_CE_ROQ_IB2_STAT 1224#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2__SHIFT 0x0 1225#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2__SHIFT 0x10 1226#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2_MASK 0x000003FFL 1227#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2_MASK 0x03FF0000L 1228#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT 0x16 1229#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 1230#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK 0x00400000L 1231#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L 1232 1233 1234// addressBlock: gc_padec 1235//VGT_VTX_VECT_EJECT_REG 1236#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT 0x0 1237#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK 0x0000007FL 1238//VGT_DMA_DATA_FIFO_DEPTH 1239#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH__SHIFT 0x0 1240#define VGT_DMA_DATA_FIFO_DEPTH__DMA2DRAW_FIFO_DEPTH__SHIFT 0x9 1241#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH_MASK 0x000001FFL 1242#define VGT_DMA_DATA_FIFO_DEPTH__DMA2DRAW_FIFO_DEPTH_MASK 0x0007FE00L 1243//VGT_DMA_REQ_FIFO_DEPTH 1244#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH__SHIFT 0x0 1245#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH_MASK 0x0000003FL 1246//VGT_DRAW_INIT_FIFO_DEPTH 1247#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH__SHIFT 0x0 1248#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH_MASK 0x0000003FL 1249//VGT_LAST_COPY_STATE 1250#define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT 0x0 1251#define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT 0x10 1252#define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L 1253#define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK 0x00070000L 1254//VGT_CACHE_INVALIDATION 1255#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT 0x0 1256#define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT__SHIFT 0x4 1257#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER__SHIFT 0x5 1258#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT 0x6 1259#define VGT_CACHE_INVALIDATION__USE_GS_DONE__SHIFT 0x9 1260#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD__SHIFT 0xb 1261#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN__SHIFT 0xc 1262#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH__SHIFT 0xd 1263#define VGT_CACHE_INVALIDATION__ES_LIMIT__SHIFT 0x10 1264#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG__SHIFT 0x15 1265#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1__SHIFT 0x16 1266#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2__SHIFT 0x19 1267#define VGT_CACHE_INVALIDATION__EN_WAVE_MERGE__SHIFT 0x1c 1268#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI__SHIFT 0x1d 1269#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_MASK 0x00000003L 1270#define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT_MASK 0x00000010L 1271#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER_MASK 0x00000020L 1272#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN_MASK 0x000000C0L 1273#define VGT_CACHE_INVALIDATION__USE_GS_DONE_MASK 0x00000200L 1274#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD_MASK 0x00000800L 1275#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN_MASK 0x00001000L 1276#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH_MASK 0x00002000L 1277#define VGT_CACHE_INVALIDATION__ES_LIMIT_MASK 0x001F0000L 1278#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_MASK 0x00200000L 1279#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1_MASK 0x01C00000L 1280#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2_MASK 0x0E000000L 1281#define VGT_CACHE_INVALIDATION__EN_WAVE_MERGE_MASK 0x10000000L 1282#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI_MASK 0x20000000L 1283//VGT_STRMOUT_DELAY 1284#define VGT_STRMOUT_DELAY__SKIP_DELAY__SHIFT 0x0 1285#define VGT_STRMOUT_DELAY__SE0_WD_DELAY__SHIFT 0x8 1286#define VGT_STRMOUT_DELAY__SE1_WD_DELAY__SHIFT 0xb 1287#define VGT_STRMOUT_DELAY__SE2_WD_DELAY__SHIFT 0xe 1288#define VGT_STRMOUT_DELAY__SE3_WD_DELAY__SHIFT 0x11 1289#define VGT_STRMOUT_DELAY__SKIP_DELAY_MASK 0x000000FFL 1290#define VGT_STRMOUT_DELAY__SE0_WD_DELAY_MASK 0x00000700L 1291#define VGT_STRMOUT_DELAY__SE1_WD_DELAY_MASK 0x00003800L 1292#define VGT_STRMOUT_DELAY__SE2_WD_DELAY_MASK 0x0001C000L 1293#define VGT_STRMOUT_DELAY__SE3_WD_DELAY_MASK 0x000E0000L 1294//VGT_FIFO_DEPTHS 1295#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH__SHIFT 0x0 1296#define VGT_FIFO_DEPTHS__RESERVED_0__SHIFT 0x7 1297#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH__SHIFT 0x8 1298#define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH__SHIFT 0x16 1299#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH_MASK 0x0000007FL 1300#define VGT_FIFO_DEPTHS__RESERVED_0_MASK 0x00000080L 1301#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH_MASK 0x003FFF00L 1302#define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH_MASK 0x0FC00000L 1303//VGT_GS_VERTEX_REUSE 1304#define VGT_GS_VERTEX_REUSE__VERT_REUSE__SHIFT 0x0 1305#define VGT_GS_VERTEX_REUSE__VERT_REUSE_MASK 0x0000001FL 1306//VGT_MC_LAT_CNTL 1307#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES__SHIFT 0x0 1308#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES_MASK 0x0000000FL 1309//IA_CNTL_STATUS 1310#define IA_CNTL_STATUS__IA_BUSY__SHIFT 0x0 1311#define IA_CNTL_STATUS__IA_DMA_BUSY__SHIFT 0x1 1312#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY__SHIFT 0x2 1313#define IA_CNTL_STATUS__IA_GRP_BUSY__SHIFT 0x3 1314#define IA_CNTL_STATUS__IA_ADC_BUSY__SHIFT 0x4 1315#define IA_CNTL_STATUS__IA_BUSY_MASK 0x00000001L 1316#define IA_CNTL_STATUS__IA_DMA_BUSY_MASK 0x00000002L 1317#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY_MASK 0x00000004L 1318#define IA_CNTL_STATUS__IA_GRP_BUSY_MASK 0x00000008L 1319#define IA_CNTL_STATUS__IA_ADC_BUSY_MASK 0x00000010L 1320//VGT_CNTL_STATUS 1321#define VGT_CNTL_STATUS__VGT_BUSY__SHIFT 0x0 1322#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT 0x1 1323#define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT 0x2 1324#define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT 0x3 1325#define VGT_CNTL_STATUS__VGT_TE_BUSY__SHIFT 0x4 1326#define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT 0x5 1327#define VGT_CNTL_STATUS__VGT_PI_BUSY__SHIFT 0x6 1328#define VGT_CNTL_STATUS__VGT_GS_BUSY__SHIFT 0x7 1329#define VGT_CNTL_STATUS__VGT_HS_BUSY__SHIFT 0x8 1330#define VGT_CNTL_STATUS__VGT_TE11_BUSY__SHIFT 0x9 1331#define VGT_CNTL_STATUS__VGT_PRIMGEN_BUSY__SHIFT 0xa 1332#define VGT_CNTL_STATUS__VGT_BUSY_MASK 0x00000001L 1333#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK 0x00000002L 1334#define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK 0x00000004L 1335#define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK 0x00000008L 1336#define VGT_CNTL_STATUS__VGT_TE_BUSY_MASK 0x00000010L 1337#define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK 0x00000020L 1338#define VGT_CNTL_STATUS__VGT_PI_BUSY_MASK 0x00000040L 1339#define VGT_CNTL_STATUS__VGT_GS_BUSY_MASK 0x00000080L 1340#define VGT_CNTL_STATUS__VGT_HS_BUSY_MASK 0x00000100L 1341#define VGT_CNTL_STATUS__VGT_TE11_BUSY_MASK 0x00000200L 1342#define VGT_CNTL_STATUS__VGT_PRIMGEN_BUSY_MASK 0x00000400L 1343//WD_CNTL_STATUS 1344#define WD_CNTL_STATUS__WD_BUSY__SHIFT 0x0 1345#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY__SHIFT 0x1 1346#define WD_CNTL_STATUS__WD_SPL_DI_BUSY__SHIFT 0x2 1347#define WD_CNTL_STATUS__WD_ADC_BUSY__SHIFT 0x3 1348#define WD_CNTL_STATUS__WD_BUSY_MASK 0x00000001L 1349#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY_MASK 0x00000002L 1350#define WD_CNTL_STATUS__WD_SPL_DI_BUSY_MASK 0x00000004L 1351#define WD_CNTL_STATUS__WD_ADC_BUSY_MASK 0x00000008L 1352//CC_GC_PRIM_CONFIG 1353#define CC_GC_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10 1354#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18 1355#define CC_GC_PRIM_CONFIG__INACTIVE_IA_MASK 0x00030000L 1356#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0x0F000000L 1357//GC_USER_PRIM_CONFIG 1358#define GC_USER_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10 1359#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18 1360#define GC_USER_PRIM_CONFIG__INACTIVE_IA_MASK 0x00030000L 1361#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0x0F000000L 1362//WD_QOS 1363#define WD_QOS__DRAW_STALL__SHIFT 0x0 1364#define WD_QOS__DRAW_STALL_MASK 0x00000001L 1365//WD_UTCL1_CNTL 1366#define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 1367#define WD_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17 1368#define WD_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 1369#define WD_UTCL1_CNTL__BYPASS__SHIFT 0x19 1370#define WD_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a 1371#define WD_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b 1372#define WD_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c 1373#define WD_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d 1374#define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL 1375#define WD_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L 1376#define WD_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L 1377#define WD_UTCL1_CNTL__BYPASS_MASK 0x02000000L 1378#define WD_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L 1379#define WD_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L 1380#define WD_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L 1381#define WD_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L 1382//WD_UTCL1_STATUS 1383#define WD_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 1384#define WD_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 1385#define WD_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 1386#define WD_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 1387#define WD_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 1388#define WD_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 1389#define WD_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L 1390#define WD_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L 1391#define WD_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L 1392#define WD_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L 1393#define WD_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L 1394#define WD_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L 1395//IA_UTCL1_CNTL 1396#define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 1397#define IA_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17 1398#define IA_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 1399#define IA_UTCL1_CNTL__BYPASS__SHIFT 0x19 1400#define IA_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a 1401#define IA_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b 1402#define IA_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c 1403#define IA_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d 1404#define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL 1405#define IA_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L 1406#define IA_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L 1407#define IA_UTCL1_CNTL__BYPASS_MASK 0x02000000L 1408#define IA_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L 1409#define IA_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L 1410#define IA_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L 1411#define IA_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L 1412//IA_UTCL1_STATUS 1413#define IA_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 1414#define IA_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 1415#define IA_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 1416#define IA_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 1417#define IA_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 1418#define IA_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 1419#define IA_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L 1420#define IA_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L 1421#define IA_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L 1422#define IA_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L 1423#define IA_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L 1424#define IA_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L 1425//VGT_SYS_CONFIG 1426#define VGT_SYS_CONFIG__DUAL_CORE_EN__SHIFT 0x0 1427#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP__SHIFT 0x1 1428#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE__SHIFT 0x7 1429#define VGT_SYS_CONFIG__DUAL_CORE_EN_MASK 0x00000001L 1430#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP_MASK 0x0000007EL 1431#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE_MASK 0x00000080L 1432//VGT_VS_MAX_WAVE_ID 1433#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 1434#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL 1435//VGT_GS_MAX_WAVE_ID 1436#define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 1437#define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL 1438//GFX_PIPE_CONTROL 1439#define GFX_PIPE_CONTROL__HYSTERESIS_CNT__SHIFT 0x0 1440#define GFX_PIPE_CONTROL__RESERVED__SHIFT 0xd 1441#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN__SHIFT 0x10 1442#define GFX_PIPE_CONTROL__HYSTERESIS_CNT_MASK 0x00001FFFL 1443#define GFX_PIPE_CONTROL__RESERVED_MASK 0x0000E000L 1444#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN_MASK 0x00010000L 1445//CC_GC_SHADER_ARRAY_CONFIG 1446#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10 1447#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xFFFF0000L 1448//GC_USER_SHADER_ARRAY_CONFIG 1449#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10 1450#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xFFFF0000L 1451//VGT_DMA_PRIMITIVE_TYPE 1452#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0 1453#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x0000003FL 1454//VGT_DMA_CONTROL 1455#define VGT_DMA_CONTROL__PRIMGROUP_SIZE__SHIFT 0x0 1456#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP__SHIFT 0x11 1457#define VGT_DMA_CONTROL__SWITCH_ON_EOI__SHIFT 0x13 1458#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP__SHIFT 0x14 1459#define VGT_DMA_CONTROL__EN_INST_OPT_BASIC__SHIFT 0x15 1460#define VGT_DMA_CONTROL__EN_INST_OPT_ADV__SHIFT 0x16 1461#define VGT_DMA_CONTROL__HW_USE_ONLY__SHIFT 0x17 1462#define VGT_DMA_CONTROL__PRIMGROUP_SIZE_MASK 0x0000FFFFL 1463#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP_MASK 0x00020000L 1464#define VGT_DMA_CONTROL__SWITCH_ON_EOI_MASK 0x00080000L 1465#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP_MASK 0x00100000L 1466#define VGT_DMA_CONTROL__EN_INST_OPT_BASIC_MASK 0x00200000L 1467#define VGT_DMA_CONTROL__EN_INST_OPT_ADV_MASK 0x00400000L 1468#define VGT_DMA_CONTROL__HW_USE_ONLY_MASK 0x00800000L 1469//VGT_DMA_LS_HS_CONFIG 1470#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8 1471#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x00003F00L 1472//WD_BUF_RESOURCE_1 1473#define WD_BUF_RESOURCE_1__POS_BUF_SIZE__SHIFT 0x0 1474#define WD_BUF_RESOURCE_1__INDEX_BUF_SIZE__SHIFT 0x10 1475#define WD_BUF_RESOURCE_1__POS_BUF_SIZE_MASK 0x0000FFFFL 1476#define WD_BUF_RESOURCE_1__INDEX_BUF_SIZE_MASK 0xFFFF0000L 1477//WD_BUF_RESOURCE_2 1478#define WD_BUF_RESOURCE_2__PARAM_BUF_SIZE__SHIFT 0x0 1479#define WD_BUF_RESOURCE_2__ADDR_MODE__SHIFT 0xf 1480#define WD_BUF_RESOURCE_2__CNTL_SB_BUF_SIZE__SHIFT 0x10 1481#define WD_BUF_RESOURCE_2__PARAM_BUF_SIZE_MASK 0x00001FFFL 1482#define WD_BUF_RESOURCE_2__ADDR_MODE_MASK 0x00008000L 1483#define WD_BUF_RESOURCE_2__CNTL_SB_BUF_SIZE_MASK 0xFFFF0000L 1484//PA_CL_CNTL_STATUS 1485#define PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED__SHIFT 0x0 1486#define PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED__SHIFT 0x1 1487#define PA_CL_CNTL_STATUS__UTC_PRT_DETECTED__SHIFT 0x2 1488#define PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED_MASK 0x00000001L 1489#define PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED_MASK 0x00000002L 1490#define PA_CL_CNTL_STATUS__UTC_PRT_DETECTED_MASK 0x00000004L 1491//PA_CL_ENHANCE 1492#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT 0x0 1493#define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT 0x1 1494#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL__SHIFT 0x3 1495#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE__SHIFT 0x4 1496#define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET__SHIFT 0x6 1497#define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS__SHIFT 0x7 1498#define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC__SHIFT 0x8 1499#define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION__SHIFT 0x9 1500#define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER__SHIFT 0xb 1501#define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH__SHIFT 0xc 1502#define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH__SHIFT 0xe 1503#define PA_CL_ENHANCE__ECO_SPARE3__SHIFT 0x1c 1504#define PA_CL_ENHANCE__ECO_SPARE2__SHIFT 0x1d 1505#define PA_CL_ENHANCE__ECO_SPARE1__SHIFT 0x1e 1506#define PA_CL_ENHANCE__ECO_SPARE0__SHIFT 0x1f 1507#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK 0x00000001L 1508#define PA_CL_ENHANCE__NUM_CLIP_SEQ_MASK 0x00000006L 1509#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL_MASK 0x00000008L 1510#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE_MASK 0x00000010L 1511#define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET_MASK 0x00000040L 1512#define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS_MASK 0x00000080L 1513#define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC_MASK 0x00000100L 1514#define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION_MASK 0x00000600L 1515#define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER_MASK 0x00000800L 1516#define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH_MASK 0x00003000L 1517#define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH_MASK 0x0001C000L 1518#define PA_CL_ENHANCE__ECO_SPARE3_MASK 0x10000000L 1519#define PA_CL_ENHANCE__ECO_SPARE2_MASK 0x20000000L 1520#define PA_CL_ENHANCE__ECO_SPARE1_MASK 0x40000000L 1521#define PA_CL_ENHANCE__ECO_SPARE0_MASK 0x80000000L 1522//PA_SU_CNTL_STATUS 1523#define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT 0x1f 1524#define PA_SU_CNTL_STATUS__SU_BUSY_MASK 0x80000000L 1525//PA_SC_FIFO_DEPTH_CNTL 1526#define PA_SC_FIFO_DEPTH_CNTL__DEPTH__SHIFT 0x0 1527#define PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK 0x000003FFL 1528//PA_SC_P3D_TRAP_SCREEN_HV_LOCK 1529#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 1530#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L 1531//PA_SC_HP3D_TRAP_SCREEN_HV_LOCK 1532#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 1533#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L 1534//PA_SC_TRAP_SCREEN_HV_LOCK 1535#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 1536#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L 1537//PA_SC_FORCE_EOV_MAX_CNTS 1538#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT 0x0 1539#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT 0x10 1540#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_MASK 0x0000FFFFL 1541#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_MASK 0xFFFF0000L 1542//PA_SC_BINNER_EVENT_CNTL_0 1543#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0__SHIFT 0x0 1544#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1__SHIFT 0x2 1545#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2__SHIFT 0x4 1546#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3__SHIFT 0x6 1547#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS__SHIFT 0x8 1548#define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE__SHIFT 0xa 1549#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH__SHIFT 0xc 1550#define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH__SHIFT 0xe 1551#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC__SHIFT 0x10 1552#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9__SHIFT 0x12 1553#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET__SHIFT 0x14 1554#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE__SHIFT 0x16 1555#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END__SHIFT 0x18 1556#define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT__SHIFT 0x1a 1557#define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH__SHIFT 0x1c 1558#define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH__SHIFT 0x1e 1559#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0_MASK 0x00000003L 1560#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1_MASK 0x0000000CL 1561#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2_MASK 0x00000030L 1562#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3_MASK 0x000000C0L 1563#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS_MASK 0x00000300L 1564#define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE_MASK 0x00000C00L 1565#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_MASK 0x00003000L 1566#define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH_MASK 0x0000C000L 1567#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC_MASK 0x00030000L 1568#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9_MASK 0x000C0000L 1569#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET_MASK 0x00300000L 1570#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE_MASK 0x00C00000L 1571#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END_MASK 0x03000000L 1572#define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT_MASK 0x0C000000L 1573#define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH_MASK 0x30000000L 1574#define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH_MASK 0xC0000000L 1575//PA_SC_BINNER_EVENT_CNTL_1 1576#define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH__SHIFT 0x0 1577#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT__SHIFT 0x2 1578#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM__SHIFT 0x4 1579#define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT__SHIFT 0x6 1580#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT__SHIFT 0x8 1581#define PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE__SHIFT 0xa 1582#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT__SHIFT 0xc 1583#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START__SHIFT 0xe 1584#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP__SHIFT 0x10 1585#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START__SHIFT 0x12 1586#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP__SHIFT 0x14 1587#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE__SHIFT 0x16 1588#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT__SHIFT 0x18 1589#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_GS_OUTPUT__SHIFT 0x1a 1590#define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT__SHIFT 0x1c 1591#define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH__SHIFT 0x1e 1592#define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH_MASK 0x00000003L 1593#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT_MASK 0x0000000CL 1594#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM_MASK 0x00000030L 1595#define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT_MASK 0x000000C0L 1596#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT_MASK 0x00000300L 1597#define PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE_MASK 0x00000C00L 1598#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT_MASK 0x00003000L 1599#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START_MASK 0x0000C000L 1600#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP_MASK 0x00030000L 1601#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START_MASK 0x000C0000L 1602#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP_MASK 0x00300000L 1603#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE_MASK 0x00C00000L 1604#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT_MASK 0x03000000L 1605#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_GS_OUTPUT_MASK 0x0C000000L 1606#define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT_MASK 0x30000000L 1607#define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH_MASK 0xC0000000L 1608//PA_SC_BINNER_EVENT_CNTL_2 1609#define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS__SHIFT 0x0 1610#define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT__SHIFT 0x2 1611#define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE__SHIFT 0x4 1612#define PA_SC_BINNER_EVENT_CNTL_2__CS_CONTEXT_DONE__SHIFT 0x6 1613#define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH__SHIFT 0x8 1614#define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER__SHIFT 0xa 1615#define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT__SHIFT 0xc 1616#define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ__SHIFT 0xe 1617#define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS__SHIFT 0x10 1618#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_SX_TS__SHIFT 0x12 1619#define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV__SHIFT 0x14 1620#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS__SHIFT 0x16 1621#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META__SHIFT 0x18 1622#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS__SHIFT 0x1a 1623#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META__SHIFT 0x1c 1624#define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE__SHIFT 0x1e 1625#define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS_MASK 0x00000003L 1626#define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT_MASK 0x0000000CL 1627#define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE_MASK 0x00000030L 1628#define PA_SC_BINNER_EVENT_CNTL_2__CS_CONTEXT_DONE_MASK 0x000000C0L 1629#define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH_MASK 0x00000300L 1630#define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER_MASK 0x00000C00L 1631#define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT_MASK 0x00003000L 1632#define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ_MASK 0x0000C000L 1633#define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS_MASK 0x00030000L 1634#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_SX_TS_MASK 0x000C0000L 1635#define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV_MASK 0x00300000L 1636#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS_MASK 0x00C00000L 1637#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META_MASK 0x03000000L 1638#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS_MASK 0x0C000000L 1639#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META_MASK 0x30000000L 1640#define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE_MASK 0xC0000000L 1641//PA_SC_BINNER_EVENT_CNTL_3 1642#define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE__SHIFT 0x0 1643#define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA__SHIFT 0x2 1644#define PA_SC_BINNER_EVENT_CNTL_3__SX_CB_RAT_ACK_REQUEST__SHIFT 0x4 1645#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START__SHIFT 0x6 1646#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP__SHIFT 0x8 1647#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER__SHIFT 0xa 1648#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FLUSH__SHIFT 0xc 1649#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH__SHIFT 0xe 1650#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL__SHIFT 0x10 1651#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP__SHIFT 0x12 1652#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET__SHIFT 0x14 1653#define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND__SHIFT 0x16 1654#define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC__SHIFT 0x18 1655#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE__SHIFT 0x1a 1656#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE__SHIFT 0x1c 1657#define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_63__SHIFT 0x1e 1658#define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE_MASK 0x00000003L 1659#define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA_MASK 0x0000000CL 1660#define PA_SC_BINNER_EVENT_CNTL_3__SX_CB_RAT_ACK_REQUEST_MASK 0x00000030L 1661#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START_MASK 0x000000C0L 1662#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP_MASK 0x00000300L 1663#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER_MASK 0x00000C00L 1664#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FLUSH_MASK 0x00003000L 1665#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH_MASK 0x0000C000L 1666#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL_MASK 0x00030000L 1667#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP_MASK 0x000C0000L 1668#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET_MASK 0x00300000L 1669#define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND_MASK 0x00C00000L 1670#define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC_MASK 0x03000000L 1671#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE_MASK 0x0C000000L 1672#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE_MASK 0x30000000L 1673#define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_63_MASK 0xC0000000L 1674//PA_SC_BINNER_TIMEOUT_COUNTER 1675#define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD__SHIFT 0x0 1676#define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD_MASK 0xFFFFFFFFL 1677//PA_SC_BINNER_PERF_CNTL_0 1678#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD__SHIFT 0x0 1679#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD__SHIFT 0xa 1680#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD__SHIFT 0x14 1681#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD__SHIFT 0x17 1682#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD_MASK 0x000003FFL 1683#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD_MASK 0x000FFC00L 1684#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD_MASK 0x00700000L 1685#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD_MASK 0x03800000L 1686//PA_SC_BINNER_PERF_CNTL_1 1687#define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT 0x0 1688#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT 0x5 1689#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD__SHIFT 0xa 1690#define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK 0x0000001FL 1691#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK 0x000003E0L 1692#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD_MASK 0x03FFFC00L 1693//PA_SC_BINNER_PERF_CNTL_2 1694#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD__SHIFT 0x0 1695#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD__SHIFT 0xb 1696#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD_MASK 0x000007FFL 1697#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD_MASK 0x003FF800L 1698//PA_SC_BINNER_PERF_CNTL_3 1699#define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD__SHIFT 0x0 1700#define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD_MASK 0xFFFFFFFFL 1701//PA_SC_FIFO_SIZE 1702#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT 0x0 1703#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x6 1704#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT 0xf 1705#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT 0x15 1706#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE_MASK 0x0000003FL 1707#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE_MASK 0x00007FC0L 1708#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE_MASK 0x001F8000L 1709#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE_MASK 0xFFE00000L 1710//PA_SC_IF_FIFO_SIZE 1711#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE__SHIFT 0x0 1712#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE__SHIFT 0x6 1713#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE__SHIFT 0xc 1714#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE__SHIFT 0x12 1715#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE_MASK 0x0000003FL 1716#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE_MASK 0x00000FC0L 1717#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE_MASK 0x0003F000L 1718#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE_MASK 0x00FC0000L 1719//PA_SC_PKR_WAVE_TABLE_CNTL 1720#define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE__SHIFT 0x0 1721#define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE_MASK 0x0000003FL 1722//PA_UTCL1_CNTL1 1723#define PA_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 1724#define PA_UTCL1_CNTL1__GPUVM_64K_DEFAULT__SHIFT 0x1 1725#define PA_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 1726#define PA_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3 1727#define PA_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 1728#define PA_UTCL1_CNTL1__CLIENTID__SHIFT 0x7 1729#define PA_UTCL1_CNTL1__SPARE__SHIFT 0x10 1730#define PA_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11 1731#define PA_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12 1732#define PA_UTCL1_CNTL1__REG_INV_VMID__SHIFT 0x13 1733#define PA_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17 1734#define PA_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT 0x18 1735#define PA_UTCL1_CNTL1__INVALIDATE_ALL_VMID__SHIFT 0x19 1736#define PA_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a 1737#define PA_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b 1738#define PA_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c 1739#define PA_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e 1740#define PA_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L 1741#define PA_UTCL1_CNTL1__GPUVM_64K_DEFAULT_MASK 0x00000002L 1742#define PA_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L 1743#define PA_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L 1744#define PA_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L 1745#define PA_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L 1746#define PA_UTCL1_CNTL1__SPARE_MASK 0x00010000L 1747#define PA_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L 1748#define PA_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L 1749#define PA_UTCL1_CNTL1__REG_INV_VMID_MASK 0x00780000L 1750#define PA_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L 1751#define PA_UTCL1_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L 1752#define PA_UTCL1_CNTL1__INVALIDATE_ALL_VMID_MASK 0x02000000L 1753#define PA_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L 1754#define PA_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L 1755#define PA_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L 1756#define PA_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L 1757//PA_UTCL1_CNTL2 1758#define PA_UTCL1_CNTL2__SPARE1__SHIFT 0x0 1759#define PA_UTCL1_CNTL2__SPARE2__SHIFT 0x8 1760#define PA_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 1761#define PA_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa 1762#define PA_UTCL1_CNTL2__SPARE3__SHIFT 0xb 1763#define PA_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc 1764#define PA_UTCL1_CNTL2__ENABLE_SHOOTDOWN_OPT__SHIFT 0xd 1765#define PA_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe 1766#define PA_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf 1767#define PA_UTCL1_CNTL2__SPARE4__SHIFT 0x10 1768#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12 1769#define PA_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13 1770#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14 1771#define PA_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT 0x15 1772#define PA_UTCL1_CNTL2__SPARE5__SHIFT 0x19 1773#define PA_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a 1774#define PA_UTCL1_CNTL2__RESERVED__SHIFT 0x1b 1775#define PA_UTCL1_CNTL2__SPARE1_MASK 0x000000FFL 1776#define PA_UTCL1_CNTL2__SPARE2_MASK 0x00000100L 1777#define PA_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L 1778#define PA_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L 1779#define PA_UTCL1_CNTL2__SPARE3_MASK 0x00000800L 1780#define PA_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L 1781#define PA_UTCL1_CNTL2__ENABLE_SHOOTDOWN_OPT_MASK 0x00002000L 1782#define PA_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L 1783#define PA_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L 1784#define PA_UTCL1_CNTL2__SPARE4_MASK 0x00030000L 1785#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L 1786#define PA_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L 1787#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L 1788#define PA_UTCL1_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L 1789#define PA_UTCL1_CNTL2__SPARE5_MASK 0x02000000L 1790#define PA_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L 1791#define PA_UTCL1_CNTL2__RESERVED_MASK 0xF8000000L 1792//PA_SIDEBAND_REQUEST_DELAYS 1793#define PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY__SHIFT 0x0 1794#define PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY__SHIFT 0x10 1795#define PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY_MASK 0x0000FFFFL 1796#define PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY_MASK 0xFFFF0000L 1797//PA_SC_ENHANCE 1798#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER__SHIFT 0x0 1799#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX__SHIFT 0x1 1800#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX__SHIFT 0x2 1801#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS__SHIFT 0x3 1802#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID__SHIFT 0x4 1803#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX__SHIFT 0x5 1804#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER__SHIFT 0x6 1805#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION__SHIFT 0x7 1806#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT 0x8 1807#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE__SHIFT 0x9 1808#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT 0xa 1809#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE__SHIFT 0xb 1810#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS__SHIFT 0xc 1811#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE__SHIFT 0xd 1812#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE__SHIFT 0xe 1813#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE__SHIFT 0xf 1814#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST__SHIFT 0x10 1815#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING__SHIFT 0x11 1816#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT 0x12 1817#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING__SHIFT 0x13 1818#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING__SHIFT 0x14 1819#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS__SHIFT 0x15 1820#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID__SHIFT 0x16 1821#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO__SHIFT 0x17 1822#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT 0x18 1823#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING__SHIFT 0x19 1824#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET__SHIFT 0x1a 1825#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET__SHIFT 0x1b 1826#define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE__SHIFT 0x1c 1827#define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING__SHIFT 0x1d 1828#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK 0x00000001L 1829#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX_MASK 0x00000002L 1830#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX_MASK 0x00000004L 1831#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS_MASK 0x00000008L 1832#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID_MASK 0x00000010L 1833#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX_MASK 0x00000020L 1834#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER_MASK 0x00000040L 1835#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION_MASK 0x00000080L 1836#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 0x00000100L 1837#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE_MASK 0x00000200L 1838#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK 0x00000400L 1839#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE_MASK 0x00000800L 1840#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS_MASK 0x00001000L 1841#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE_MASK 0x00002000L 1842#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE_MASK 0x00004000L 1843#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE_MASK 0x00008000L 1844#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST_MASK 0x00010000L 1845#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING_MASK 0x00020000L 1846#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY_MASK 0x00040000L 1847#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING_MASK 0x00080000L 1848#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING_MASK 0x00100000L 1849#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS_MASK 0x00200000L 1850#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID_MASK 0x00400000L 1851#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO_MASK 0x00800000L 1852#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK 0x01000000L 1853#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING_MASK 0x02000000L 1854#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET_MASK 0x04000000L 1855#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET_MASK 0x08000000L 1856#define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE_MASK 0x10000000L 1857#define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING_MASK 0x20000000L 1858//PA_SC_ENHANCE_1 1859#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE__SHIFT 0x0 1860#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE__SHIFT 0x1 1861#define PA_SC_ENHANCE_1__DISABLE_SC_BINNING__SHIFT 0x3 1862#define PA_SC_ENHANCE_1__BYPASS_PBB__SHIFT 0x4 1863#define PA_SC_ENHANCE_1__ECO_SPARE0__SHIFT 0x5 1864#define PA_SC_ENHANCE_1__ECO_SPARE1__SHIFT 0x6 1865#define PA_SC_ENHANCE_1__ECO_SPARE2__SHIFT 0x7 1866#define PA_SC_ENHANCE_1__ECO_SPARE3__SHIFT 0x8 1867#define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB__SHIFT 0x9 1868#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT__SHIFT 0xa 1869#define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM__SHIFT 0xb 1870#define PA_SC_ENHANCE_1__DISABLE_PACKER_GRAD_FDCE_ENHANCE__SHIFT 0xd 1871#define PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE__SHIFT 0xe 1872#define PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION__SHIFT 0xf 1873#define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE__SHIFT 0x10 1874#define PA_SC_ENHANCE_1__ALLOW_SCALE_LINE_WIDTH_PAD_WITH_BINNING__SHIFT 0x11 1875#define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION__SHIFT 0x12 1876#define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS__SHIFT 0x13 1877#define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION__SHIFT 0x14 1878#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION__SHIFT 0x15 1879#define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION__SHIFT 0x16 1880#define PA_SC_ENHANCE_1__RSVD__SHIFT 0x17 1881#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE_MASK 0x00000001L 1882#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_MASK 0x00000006L 1883#define PA_SC_ENHANCE_1__DISABLE_SC_BINNING_MASK 0x00000008L 1884#define PA_SC_ENHANCE_1__BYPASS_PBB_MASK 0x00000010L 1885#define PA_SC_ENHANCE_1__ECO_SPARE0_MASK 0x00000020L 1886#define PA_SC_ENHANCE_1__ECO_SPARE1_MASK 0x00000040L 1887#define PA_SC_ENHANCE_1__ECO_SPARE2_MASK 0x00000080L 1888#define PA_SC_ENHANCE_1__ECO_SPARE3_MASK 0x00000100L 1889#define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB_MASK 0x00000200L 1890#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT_MASK 0x00000400L 1891#define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM_MASK 0x00000800L 1892#define PA_SC_ENHANCE_1__DISABLE_PACKER_GRAD_FDCE_ENHANCE_MASK 0x00002000L 1893#define PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE_MASK 0x00004000L 1894#define PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION_MASK 0x00008000L 1895#define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE_MASK 0x00010000L 1896#define PA_SC_ENHANCE_1__ALLOW_SCALE_LINE_WIDTH_PAD_WITH_BINNING_MASK 0x00020000L 1897#define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION_MASK 0x00040000L 1898#define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS_MASK 0x00080000L 1899#define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION_MASK 0x00100000L 1900#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION_MASK 0x00200000L 1901#define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION_MASK 0x00400000L 1902#define PA_SC_ENHANCE_1__RSVD_MASK 0xFF800000L 1903//PA_SC_DSM_CNTL 1904#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT 0x0 1905#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1__SHIFT 0x1 1906#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0_MASK 0x00000001L 1907#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1_MASK 0x00000002L 1908//PA_SC_TILE_STEERING_CREST_OVERRIDE 1909#define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE__SHIFT 0x0 1910#define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT__SHIFT 0x1 1911#define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT__SHIFT 0x5 1912#define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE_MASK 0x00000001L 1913#define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT_MASK 0x00000006L 1914#define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT_MASK 0x00000060L 1915 1916 1917// addressBlock: gc_sqdec 1918//SQ_CONFIG 1919#define SQ_CONFIG__UNUSED__SHIFT 0x0 1920#define SQ_CONFIG__OVERRIDE_ALU_BUSY__SHIFT 0x7 1921#define SQ_CONFIG__OVERRIDE_LDS_IDX_BUSY__SHIFT 0xb 1922#define SQ_CONFIG__EARLY_TA_DONE_DISABLE__SHIFT 0xc 1923#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE__SHIFT 0xd 1924#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE__SHIFT 0xe 1925#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE__SHIFT 0xf 1926#define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE__SHIFT 0x10 1927#define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE__SHIFT 0x11 1928#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS__SHIFT 0x12 1929#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS__SHIFT 0x13 1930#define SQ_CONFIG__REPLAY_SLEEP_CNT__SHIFT 0x15 1931#define SQ_CONFIG__DISABLE_SP_VGPR_WRITE_SKIP__SHIFT 0x1c 1932#define SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING__SHIFT 0x1d 1933#define SQ_CONFIG__DISABLE_FLAT_SOFT_CLAUSE__SHIFT 0x1e 1934#define SQ_CONFIG__DISABLE_MIMG_SOFT_CLAUSE__SHIFT 0x1f 1935#define SQ_CONFIG__UNUSED_MASK 0x0000007FL 1936#define SQ_CONFIG__OVERRIDE_ALU_BUSY_MASK 0x00000080L 1937#define SQ_CONFIG__OVERRIDE_LDS_IDX_BUSY_MASK 0x00000800L 1938#define SQ_CONFIG__EARLY_TA_DONE_DISABLE_MASK 0x00001000L 1939#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE_MASK 0x00002000L 1940#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE_MASK 0x00004000L 1941#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE_MASK 0x00008000L 1942#define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE_MASK 0x00010000L 1943#define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE_MASK 0x00020000L 1944#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS_MASK 0x00040000L 1945#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS_MASK 0x00180000L 1946#define SQ_CONFIG__REPLAY_SLEEP_CNT_MASK 0x0FE00000L 1947#define SQ_CONFIG__DISABLE_SP_VGPR_WRITE_SKIP_MASK 0x10000000L 1948#define SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING_MASK 0x20000000L 1949#define SQ_CONFIG__DISABLE_FLAT_SOFT_CLAUSE_MASK 0x40000000L 1950#define SQ_CONFIG__DISABLE_MIMG_SOFT_CLAUSE_MASK 0x80000000L 1951//SQC_CONFIG 1952#define SQC_CONFIG__INST_CACHE_SIZE__SHIFT 0x0 1953#define SQC_CONFIG__DATA_CACHE_SIZE__SHIFT 0x2 1954#define SQC_CONFIG__MISS_FIFO_DEPTH__SHIFT 0x4 1955#define SQC_CONFIG__HIT_FIFO_DEPTH__SHIFT 0x6 1956#define SQC_CONFIG__FORCE_ALWAYS_MISS__SHIFT 0x7 1957#define SQC_CONFIG__FORCE_IN_ORDER__SHIFT 0x8 1958#define SQC_CONFIG__IDENTITY_HASH_BANK__SHIFT 0x9 1959#define SQC_CONFIG__IDENTITY_HASH_SET__SHIFT 0xa 1960#define SQC_CONFIG__PER_VMID_INV_DISABLE__SHIFT 0xb 1961#define SQC_CONFIG__EVICT_LRU__SHIFT 0xc 1962#define SQC_CONFIG__FORCE_2_BANK__SHIFT 0xe 1963#define SQC_CONFIG__FORCE_1_BANK__SHIFT 0xf 1964#define SQC_CONFIG__LS_DISABLE_CLOCKS__SHIFT 0x10 1965#define SQC_CONFIG__INST_PRF_COUNT__SHIFT 0x18 1966#define SQC_CONFIG__INST_PRF_FILTER_DIS__SHIFT 0x1a 1967#define SQC_CONFIG__INST_CACHE_SIZE_MASK 0x00000003L 1968#define SQC_CONFIG__DATA_CACHE_SIZE_MASK 0x0000000CL 1969#define SQC_CONFIG__MISS_FIFO_DEPTH_MASK 0x00000030L 1970#define SQC_CONFIG__HIT_FIFO_DEPTH_MASK 0x00000040L 1971#define SQC_CONFIG__FORCE_ALWAYS_MISS_MASK 0x00000080L 1972#define SQC_CONFIG__FORCE_IN_ORDER_MASK 0x00000100L 1973#define SQC_CONFIG__IDENTITY_HASH_BANK_MASK 0x00000200L 1974#define SQC_CONFIG__IDENTITY_HASH_SET_MASK 0x00000400L 1975#define SQC_CONFIG__PER_VMID_INV_DISABLE_MASK 0x00000800L 1976#define SQC_CONFIG__EVICT_LRU_MASK 0x00003000L 1977#define SQC_CONFIG__FORCE_2_BANK_MASK 0x00004000L 1978#define SQC_CONFIG__FORCE_1_BANK_MASK 0x00008000L 1979#define SQC_CONFIG__LS_DISABLE_CLOCKS_MASK 0x00FF0000L 1980#define SQC_CONFIG__INST_PRF_COUNT_MASK 0x03000000L 1981#define SQC_CONFIG__INST_PRF_FILTER_DIS_MASK 0x04000000L 1982//LDS_CONFIG 1983#define LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING__SHIFT 0x0 1984#define LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING_MASK 0x00000001L 1985//SQ_RANDOM_WAVE_PRI 1986#define SQ_RANDOM_WAVE_PRI__RET__SHIFT 0x0 1987#define SQ_RANDOM_WAVE_PRI__RUI__SHIFT 0x7 1988#define SQ_RANDOM_WAVE_PRI__RNG__SHIFT 0xa 1989#define SQ_RANDOM_WAVE_PRI__RET_MASK 0x0000007FL 1990#define SQ_RANDOM_WAVE_PRI__RUI_MASK 0x00000380L 1991#define SQ_RANDOM_WAVE_PRI__RNG_MASK 0x007FFC00L 1992//SQ_REG_CREDITS 1993#define SQ_REG_CREDITS__SRBM_CREDITS__SHIFT 0x0 1994#define SQ_REG_CREDITS__CMD_CREDITS__SHIFT 0x8 1995#define SQ_REG_CREDITS__REG_BUSY__SHIFT 0x1c 1996#define SQ_REG_CREDITS__SRBM_OVERFLOW__SHIFT 0x1d 1997#define SQ_REG_CREDITS__IMMED_OVERFLOW__SHIFT 0x1e 1998#define SQ_REG_CREDITS__CMD_OVERFLOW__SHIFT 0x1f 1999#define SQ_REG_CREDITS__SRBM_CREDITS_MASK 0x0000003FL 2000#define SQ_REG_CREDITS__CMD_CREDITS_MASK 0x00000F00L
2001#define SQ_REG_CREDITS__REG_BUSY_MASK 0x10000000L 2002#define SQ_REG_CREDITS__SRBM_OVERFLOW_MASK 0x20000000L 2003#define SQ_REG_CREDITS__IMMED_OVERFLOW_MASK 0x40000000L 2004#define SQ_REG_CREDITS__CMD_OVERFLOW_MASK 0x80000000L 2005//SQ_FIFO_SIZES 2006#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE__SHIFT 0x0 2007#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE__SHIFT 0x8 2008#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE__SHIFT 0x10 2009#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE__SHIFT 0x12 2010#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE_MASK 0x0000000FL 2011#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE_MASK 0x00000F00L 2012#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE_MASK 0x00030000L 2013#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE_MASK 0x000C0000L 2014//SQ_DSM_CNTL 2015#define SQ_DSM_CNTL__WAVEFRONT_STALL_0__SHIFT 0x0 2016#define SQ_DSM_CNTL__WAVEFRONT_STALL_1__SHIFT 0x1 2017#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0__SHIFT 0x2 2018#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1__SHIFT 0x3 2019#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0__SHIFT 0x8 2020#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1__SHIFT 0x9 2021#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT 0xa 2022#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0__SHIFT 0x10 2023#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1__SHIFT 0x11 2024#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01__SHIFT 0x12 2025#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2__SHIFT 0x13 2026#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3__SHIFT 0x14 2027#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23__SHIFT 0x15 2028#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0__SHIFT 0x18 2029#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1__SHIFT 0x19 2030#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE__SHIFT 0x1a 2031#define SQ_DSM_CNTL__WAVEFRONT_STALL_0_MASK 0x00000001L 2032#define SQ_DSM_CNTL__WAVEFRONT_STALL_1_MASK 0x00000002L 2033#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0_MASK 0x00000004L 2034#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1_MASK 0x00000008L 2035#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0_MASK 0x00000100L 2036#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1_MASK 0x00000200L 2037#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE_MASK 0x00000400L 2038#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0_MASK 0x00010000L 2039#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1_MASK 0x00020000L 2040#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01_MASK 0x00040000L 2041#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2_MASK 0x00080000L 2042#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3_MASK 0x00100000L 2043#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23_MASK 0x00200000L 2044#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0_MASK 0x01000000L 2045#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1_MASK 0x02000000L 2046#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE_MASK 0x04000000L 2047//SQ_DSM_CNTL2 2048#define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT__SHIFT 0x0 2049#define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY__SHIFT 0x2 2050#define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT__SHIFT 0x3 2051#define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY__SHIFT 0x5 2052#define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT__SHIFT 0x6 2053#define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY__SHIFT 0x8 2054#define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT__SHIFT 0x9 2055#define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY__SHIFT 0xb 2056#define SQ_DSM_CNTL2__LDS_INJECT_DELAY__SHIFT 0xe 2057#define SQ_DSM_CNTL2__SP_INJECT_DELAY__SHIFT 0x14 2058#define SQ_DSM_CNTL2__SQ_INJECT_DELAY__SHIFT 0x1a 2059#define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT_MASK 0x00000003L 2060#define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY_MASK 0x00000004L 2061#define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT_MASK 0x00000018L 2062#define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY_MASK 0x00000020L 2063#define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT_MASK 0x000000C0L 2064#define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY_MASK 0x00000100L 2065#define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT_MASK 0x00000600L 2066#define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY_MASK 0x00000800L 2067#define SQ_DSM_CNTL2__LDS_INJECT_DELAY_MASK 0x000FC000L 2068#define SQ_DSM_CNTL2__SP_INJECT_DELAY_MASK 0x03F00000L 2069#define SQ_DSM_CNTL2__SQ_INJECT_DELAY_MASK 0xFC000000L 2070//SQ_RUNTIME_CONFIG 2071#define SQ_RUNTIME_CONFIG__ENABLE_TEX_ARB_OLDEST__SHIFT 0x0 2072#define SQ_RUNTIME_CONFIG__ENABLE_TEX_ARB_OLDEST_MASK 0x00000001L 2073//SH_MEM_BASES 2074#define SH_MEM_BASES__PRIVATE_BASE__SHIFT 0x0 2075#define SH_MEM_BASES__SHARED_BASE__SHIFT 0x10 2076#define SH_MEM_BASES__PRIVATE_BASE_MASK 0x0000FFFFL 2077#define SH_MEM_BASES__SHARED_BASE_MASK 0xFFFF0000L 2078//SH_MEM_CONFIG 2079#define SH_MEM_CONFIG__ADDRESS_MODE__SHIFT 0x0 2080#define SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT 0x3 2081#define SH_MEM_CONFIG__RETRY_DISABLE__SHIFT 0xc 2082#define SH_MEM_CONFIG__PRIVATE_NV__SHIFT 0xd 2083#define SH_MEM_CONFIG__ADDRESS_MODE_MASK 0x00000001L 2084#define SH_MEM_CONFIG__ALIGNMENT_MODE_MASK 0x00000018L 2085#define SH_MEM_CONFIG__RETRY_DISABLE_MASK 0x00001000L 2086#define SH_MEM_CONFIG__PRIVATE_NV_MASK 0x00002000L 2087//CC_GC_SHADER_RATE_CONFIG 2088#define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1 2089#define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3 2090#define CC_GC_SHADER_RATE_CONFIG__HALF_LDS__SHIFT 0x4 2091#define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x00000006L 2092#define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x00000008L 2093#define CC_GC_SHADER_RATE_CONFIG__HALF_LDS_MASK 0x00000010L 2094//GC_USER_SHADER_RATE_CONFIG 2095#define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1 2096#define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3 2097#define GC_USER_SHADER_RATE_CONFIG__HALF_LDS__SHIFT 0x4 2098#define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x00000006L 2099#define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x00000008L 2100#define GC_USER_SHADER_RATE_CONFIG__HALF_LDS_MASK 0x00000010L 2101//SQ_INTERRUPT_AUTO_MASK 2102#define SQ_INTERRUPT_AUTO_MASK__MASK__SHIFT 0x0 2103#define SQ_INTERRUPT_AUTO_MASK__MASK_MASK 0x00FFFFFFL 2104//SQ_INTERRUPT_MSG_CTRL 2105#define SQ_INTERRUPT_MSG_CTRL__STALL__SHIFT 0x0 2106#define SQ_INTERRUPT_MSG_CTRL__STALL_MASK 0x00000001L 2107//SQ_UTCL1_CNTL1 2108#define SQ_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 2109#define SQ_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1 2110#define SQ_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 2111#define SQ_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3 2112#define SQ_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 2113#define SQ_UTCL1_CNTL1__CLIENTID__SHIFT 0x7 2114#define SQ_UTCL1_CNTL1__USERVM_DIS__SHIFT 0x10 2115#define SQ_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11 2116#define SQ_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12 2117#define SQ_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT 0x13 2118#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT 0x17 2119#define SQ_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT 0x18 2120#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL__SHIFT 0x19 2121#define SQ_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a 2122#define SQ_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b 2123#define SQ_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c 2124#define SQ_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e 2125#define SQ_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L 2126#define SQ_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L 2127#define SQ_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L 2128#define SQ_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L 2129#define SQ_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L 2130#define SQ_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L 2131#define SQ_UTCL1_CNTL1__USERVM_DIS_MASK 0x00010000L 2132#define SQ_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L 2133#define SQ_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L 2134#define SQ_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK 0x00780000L 2135#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK 0x00800000L 2136#define SQ_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK 0x01000000L 2137#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_MASK 0x02000000L 2138#define SQ_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L 2139#define SQ_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L 2140#define SQ_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L 2141#define SQ_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L 2142//SQ_UTCL1_CNTL2 2143#define SQ_UTCL1_CNTL2__SPARE__SHIFT 0x0 2144#define SQ_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8 2145#define SQ_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 2146#define SQ_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa 2147#define SQ_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb 2148#define SQ_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc 2149#define SQ_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd 2150#define SQ_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe 2151#define SQ_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf 2152#define SQ_UTCL1_CNTL2__RETRY_TIMER__SHIFT 0x10 2153#define SQ_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a 2154#define SQ_UTCL1_CNTL2__PREFETCH_PAGE__SHIFT 0x1c 2155#define SQ_UTCL1_CNTL2__SPARE_MASK 0x000000FFL 2156#define SQ_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L 2157#define SQ_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L 2158#define SQ_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L 2159#define SQ_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L 2160#define SQ_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L 2161#define SQ_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L 2162#define SQ_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L 2163#define SQ_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L 2164#define SQ_UTCL1_CNTL2__RETRY_TIMER_MASK 0x007F0000L 2165#define SQ_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L 2166#define SQ_UTCL1_CNTL2__PREFETCH_PAGE_MASK 0xF0000000L 2167//SQ_UTCL1_STATUS 2168#define SQ_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 2169#define SQ_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 2170#define SQ_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 2171#define SQ_UTCL1_STATUS__RESERVED__SHIFT 0x3 2172#define SQ_UTCL1_STATUS__UNUSED__SHIFT 0x10 2173#define SQ_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L 2174#define SQ_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L 2175#define SQ_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L 2176#define SQ_UTCL1_STATUS__RESERVED_MASK 0x0000FFF8L 2177#define SQ_UTCL1_STATUS__UNUSED_MASK 0xFFFF0000L 2178//SQ_SHADER_TBA_LO 2179#define SQ_SHADER_TBA_LO__ADDR_LO__SHIFT 0x0 2180#define SQ_SHADER_TBA_LO__ADDR_LO_MASK 0xFFFFFFFFL 2181//SQ_SHADER_TBA_HI 2182#define SQ_SHADER_TBA_HI__ADDR_HI__SHIFT 0x0 2183#define SQ_SHADER_TBA_HI__ADDR_HI_MASK 0x000000FFL 2184//SQ_SHADER_TMA_LO 2185#define SQ_SHADER_TMA_LO__ADDR_LO__SHIFT 0x0 2186#define SQ_SHADER_TMA_LO__ADDR_LO_MASK 0xFFFFFFFFL 2187//SQ_SHADER_TMA_HI 2188#define SQ_SHADER_TMA_HI__ADDR_HI__SHIFT 0x0 2189#define SQ_SHADER_TMA_HI__ADDR_HI_MASK 0x000000FFL 2190//SQC_DSM_CNTL 2191#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x0 2192#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x2 2193#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT 0x3 2194#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT 0x5 2195#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x6 2196#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8 2197#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT 0x9 2198#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT 0xb 2199#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0xc 2200#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0xe 2201#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT 0xf 2202#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT 0x11 2203#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x12 2204#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x14 2205#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x00000003L 2206#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00000004L 2207#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK 0x00000018L 2208#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK 0x00000020L 2209#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L 2210#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L 2211#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK 0x00000600L 2212#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK 0x00000800L 2213#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x00003000L 2214#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00004000L 2215#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK 0x00018000L 2216#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK 0x00020000L 2217#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x000C0000L 2218#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00100000L 2219//SQC_DSM_CNTLA 2220#define SQC_DSM_CNTLA__INST_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0x0 2221#define SQC_DSM_CNTLA__INST_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x2 2222#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x3 2223#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x5 2224#define SQC_DSM_CNTLA__INST_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x6 2225#define SQC_DSM_CNTLA__INST_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8 2226#define SQC_DSM_CNTLA__INST_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x9 2227#define SQC_DSM_CNTLA__INST_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xb 2228#define SQC_DSM_CNTLA__DATA_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0xc 2229#define SQC_DSM_CNTLA__DATA_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xe 2230#define SQC_DSM_CNTLA__DATA_HIT_FIFO_DSM_IRRITATOR_DATA__SHIFT 0xf 2231#define SQC_DSM_CNTLA__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x11 2232#define SQC_DSM_CNTLA__DATA_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x12 2233#define SQC_DSM_CNTLA__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x14 2234#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA__SHIFT 0x15 2235#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x17 2236#define SQC_DSM_CNTLA__DATA_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x18 2237#define SQC_DSM_CNTLA__DATA_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x1a 2238#define SQC_DSM_CNTLA__INST_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00000003L 2239#define SQC_DSM_CNTLA__INST_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000004L 2240#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x00000018L 2241#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000020L 2242#define SQC_DSM_CNTLA__INST_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L 2243#define SQC_DSM_CNTLA__INST_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L 2244#define SQC_DSM_CNTLA__INST_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x00000600L 2245#define SQC_DSM_CNTLA__INST_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000800L 2246#define SQC_DSM_CNTLA__DATA_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00003000L 2247#define SQC_DSM_CNTLA__DATA_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00004000L 2248#define SQC_DSM_CNTLA__DATA_HIT_FIFO_DSM_IRRITATOR_DATA_MASK 0x00018000L 2249#define SQC_DSM_CNTLA__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00020000L 2250#define SQC_DSM_CNTLA__DATA_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000C0000L 2251#define SQC_DSM_CNTLA__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00100000L 2252#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA_MASK 0x00600000L 2253#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE_MASK 0x00800000L 2254#define SQC_DSM_CNTLA__DATA_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x03000000L 2255#define SQC_DSM_CNTLA__DATA_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x04000000L 2256//SQC_DSM_CNTLB 2257#define SQC_DSM_CNTLB__INST_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0x0 2258#define SQC_DSM_CNTLB__INST_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x2 2259#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x3 2260#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x5 2261#define SQC_DSM_CNTLB__INST_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x6 2262#define SQC_DSM_CNTLB__INST_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8 2263#define SQC_DSM_CNTLB__INST_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x9 2264#define SQC_DSM_CNTLB__INST_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xb 2265#define SQC_DSM_CNTLB__DATA_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0xc 2266#define SQC_DSM_CNTLB__DATA_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xe 2267#define SQC_DSM_CNTLB__DATA_HIT_FIFO_DSM_IRRITATOR_DATA__SHIFT 0xf 2268#define SQC_DSM_CNTLB__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x11 2269#define SQC_DSM_CNTLB__DATA_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x12 2270#define SQC_DSM_CNTLB__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x14 2271#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA__SHIFT 0x15 2272#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x17 2273#define SQC_DSM_CNTLB__DATA_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x18 2274#define SQC_DSM_CNTLB__DATA_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x1a 2275#define SQC_DSM_CNTLB__INST_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00000003L 2276#define SQC_DSM_CNTLB__INST_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000004L 2277#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x00000018L 2278#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000020L 2279#define SQC_DSM_CNTLB__INST_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L 2280#define SQC_DSM_CNTLB__INST_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L 2281#define SQC_DSM_CNTLB__INST_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x00000600L 2282#define SQC_DSM_CNTLB__INST_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000800L 2283#define SQC_DSM_CNTLB__DATA_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00003000L 2284#define SQC_DSM_CNTLB__DATA_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00004000L 2285#define SQC_DSM_CNTLB__DATA_HIT_FIFO_DSM_IRRITATOR_DATA_MASK 0x00018000L 2286#define SQC_DSM_CNTLB__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00020000L 2287#define SQC_DSM_CNTLB__DATA_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000C0000L 2288#define SQC_DSM_CNTLB__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00100000L 2289#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA_MASK 0x00600000L 2290#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE_MASK 0x00800000L 2291#define SQC_DSM_CNTLB__DATA_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x03000000L 2292#define SQC_DSM_CNTLB__DATA_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x04000000L 2293//SQC_DSM_CNTL2 2294#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x0 2295#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x2 2296#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT 0x3 2297#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT 0x5 2298#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x6 2299#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x8 2300#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT 0x9 2301#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT 0xb 2302#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0xc 2303#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0xe 2304#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT 0xf 2305#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT 0x11 2306#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x12 2307#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x14 2308#define SQC_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a 2309#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x00000003L 2310#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00000004L 2311#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK 0x00000018L 2312#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK 0x00000020L 2313#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L 2314#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00000100L 2315#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK 0x00000600L 2316#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK 0x00000800L 2317#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x00003000L 2318#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00004000L 2319#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK 0x00018000L 2320#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK 0x00020000L 2321#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x000C0000L 2322#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00100000L 2323#define SQC_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L 2324//SQC_DSM_CNTL2A 2325#define SQC_DSM_CNTL2A__INST_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0x0 2326#define SQC_DSM_CNTL2A__INST_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0x2 2327#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x3 2328#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x5 2329#define SQC_DSM_CNTL2A__INST_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x6 2330#define SQC_DSM_CNTL2A__INST_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x8 2331#define SQC_DSM_CNTL2A__INST_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9 2332#define SQC_DSM_CNTL2A__INST_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0xb 2333#define SQC_DSM_CNTL2A__DATA_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0xc 2334#define SQC_DSM_CNTL2A__DATA_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0xe 2335#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_ENABLE_ERROR_INJECT__SHIFT 0xf 2336#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_SELECT_INJECT_DELAY__SHIFT 0x11 2337#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x12 2338#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x14 2339#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x15 2340#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY__SHIFT 0x17 2341#define SQC_DSM_CNTL2A__DATA_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x18 2342#define SQC_DSM_CNTL2A__DATA_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0x1a 2343#define SQC_DSM_CNTL2A__INST_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00000003L 2344#define SQC_DSM_CNTL2A__INST_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00000004L 2345#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x00000018L 2346#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000020L 2347#define SQC_DSM_CNTL2A__INST_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L 2348#define SQC_DSM_CNTL2A__INST_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L 2349#define SQC_DSM_CNTL2A__INST_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L 2350#define SQC_DSM_CNTL2A__INST_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L 2351#define SQC_DSM_CNTL2A__DATA_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00003000L 2352#define SQC_DSM_CNTL2A__DATA_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00004000L 2353#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_ENABLE_ERROR_INJECT_MASK 0x00018000L 2354#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_SELECT_INJECT_DELAY_MASK 0x00020000L 2355#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000C0000L 2356#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00100000L 2357#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT_MASK 0x00600000L 2358#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY_MASK 0x00800000L 2359#define SQC_DSM_CNTL2A__DATA_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x03000000L 2360#define SQC_DSM_CNTL2A__DATA_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x04000000L 2361//SQC_DSM_CNTL2B 2362#define SQC_DSM_CNTL2B__INST_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0x0 2363#define SQC_DSM_CNTL2B__INST_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0x2 2364#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x3 2365#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x5 2366#define SQC_DSM_CNTL2B__INST_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x6 2367#define SQC_DSM_CNTL2B__INST_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x8 2368#define SQC_DSM_CNTL2B__INST_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9 2369#define SQC_DSM_CNTL2B__INST_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0xb 2370#define SQC_DSM_CNTL2B__DATA_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0xc 2371#define SQC_DSM_CNTL2B__DATA_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0xe 2372#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_ENABLE_ERROR_INJECT__SHIFT 0xf 2373#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_SELECT_INJECT_DELAY__SHIFT 0x11 2374#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x12 2375#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x14 2376#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x15 2377#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY__SHIFT 0x17 2378#define SQC_DSM_CNTL2B__DATA_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x18 2379#define SQC_DSM_CNTL2B__DATA_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0x1a 2380#define SQC_DSM_CNTL2B__INST_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00000003L 2381#define SQC_DSM_CNTL2B__INST_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00000004L 2382#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x00000018L 2383#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000020L 2384#define SQC_DSM_CNTL2B__INST_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L 2385#define SQC_DSM_CNTL2B__INST_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L 2386#define SQC_DSM_CNTL2B__INST_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L 2387#define SQC_DSM_CNTL2B__INST_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L 2388#define SQC_DSM_CNTL2B__DATA_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00003000L 2389#define SQC_DSM_CNTL2B__DATA_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00004000L 2390#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_ENABLE_ERROR_INJECT_MASK 0x00018000L 2391#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_SELECT_INJECT_DELAY_MASK 0x00020000L 2392#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000C0000L 2393#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00100000L 2394#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT_MASK 0x00600000L 2395#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY_MASK 0x00800000L 2396#define SQC_DSM_CNTL2B__DATA_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x03000000L 2397#define SQC_DSM_CNTL2B__DATA_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x04000000L 2398//SQC_EDC_FUE_CNTL 2399#define SQC_EDC_FUE_CNTL__BLOCK_FUE_FLAGS__SHIFT 0x0 2400#define SQC_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES__SHIFT 0x10 2401#define SQC_EDC_FUE_CNTL__BLOCK_FUE_FLAGS_MASK 0x0000FFFFL 2402#define SQC_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES_MASK 0xFFFF0000L 2403//SQC_EDC_CNT2 2404#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_SEC_COUNT__SHIFT 0x0 2405#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_DED_COUNT__SHIFT 0x2 2406#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_SEC_COUNT__SHIFT 0x4 2407#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_DED_COUNT__SHIFT 0x6 2408#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_SEC_COUNT__SHIFT 0x8 2409#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_DED_COUNT__SHIFT 0xa 2410#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_SEC_COUNT__SHIFT 0xc 2411#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_DED_COUNT__SHIFT 0xe 2412#define SQC_EDC_CNT2__INST_BANKA_UTCL1_MISS_FIFO_SED_COUNT__SHIFT 0x10 2413#define SQC_EDC_CNT2__INST_BANKA_MISS_FIFO_SED_COUNT__SHIFT 0x12 2414#define SQC_EDC_CNT2__DATA_BANKA_HIT_FIFO_SED_COUNT__SHIFT 0x14 2415#define SQC_EDC_CNT2__DATA_BANKA_MISS_FIFO_SED_COUNT__SHIFT 0x16 2416#define SQC_EDC_CNT2__DATA_BANKA_DIRTY_BIT_RAM_SED_COUNT__SHIFT 0x18 2417#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x1a 2418#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_DED_COUNT__SHIFT 0x1c 2419#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_SEC_COUNT_MASK 0x00000003L 2420#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_DED_COUNT_MASK 0x0000000CL 2421#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_SEC_COUNT_MASK 0x00000030L 2422#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_DED_COUNT_MASK 0x000000C0L 2423#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_SEC_COUNT_MASK 0x00000300L 2424#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_DED_COUNT_MASK 0x00000C00L 2425#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_SEC_COUNT_MASK 0x00003000L 2426#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_DED_COUNT_MASK 0x0000C000L 2427#define SQC_EDC_CNT2__INST_BANKA_UTCL1_MISS_FIFO_SED_COUNT_MASK 0x00030000L 2428#define SQC_EDC_CNT2__INST_BANKA_MISS_FIFO_SED_COUNT_MASK 0x000C0000L 2429#define SQC_EDC_CNT2__DATA_BANKA_HIT_FIFO_SED_COUNT_MASK 0x00300000L 2430#define SQC_EDC_CNT2__DATA_BANKA_MISS_FIFO_SED_COUNT_MASK 0x00C00000L 2431#define SQC_EDC_CNT2__DATA_BANKA_DIRTY_BIT_RAM_SED_COUNT_MASK 0x03000000L 2432#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_SEC_COUNT_MASK 0x0C000000L 2433#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_DED_COUNT_MASK 0x30000000L 2434//SQC_EDC_CNT3 2435#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_SEC_COUNT__SHIFT 0x0 2436#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_DED_COUNT__SHIFT 0x2 2437#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_SEC_COUNT__SHIFT 0x4 2438#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_DED_COUNT__SHIFT 0x6 2439#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_SEC_COUNT__SHIFT 0x8 2440#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_DED_COUNT__SHIFT 0xa 2441#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_SEC_COUNT__SHIFT 0xc 2442#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_DED_COUNT__SHIFT 0xe 2443#define SQC_EDC_CNT3__INST_BANKB_UTCL1_MISS_FIFO_SED_COUNT__SHIFT 0x10 2444#define SQC_EDC_CNT3__INST_BANKB_MISS_FIFO_SED_COUNT__SHIFT 0x12 2445#define SQC_EDC_CNT3__DATA_BANKB_HIT_FIFO_SED_COUNT__SHIFT 0x14 2446#define SQC_EDC_CNT3__DATA_BANKB_MISS_FIFO_SED_COUNT__SHIFT 0x16 2447#define SQC_EDC_CNT3__DATA_BANKB_DIRTY_BIT_RAM_SED_COUNT__SHIFT 0x18 2448#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_SEC_COUNT_MASK 0x00000003L 2449#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_DED_COUNT_MASK 0x0000000CL 2450#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_SEC_COUNT_MASK 0x00000030L 2451#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_DED_COUNT_MASK 0x000000C0L 2452#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_SEC_COUNT_MASK 0x00000300L 2453#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_DED_COUNT_MASK 0x00000C00L 2454#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_SEC_COUNT_MASK 0x00003000L 2455#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_DED_COUNT_MASK 0x0000C000L 2456#define SQC_EDC_CNT3__INST_BANKB_UTCL1_MISS_FIFO_SED_COUNT_MASK 0x00030000L 2457#define SQC_EDC_CNT3__INST_BANKB_MISS_FIFO_SED_COUNT_MASK 0x000C0000L 2458#define SQC_EDC_CNT3__DATA_BANKB_HIT_FIFO_SED_COUNT_MASK 0x00300000L 2459#define SQC_EDC_CNT3__DATA_BANKB_MISS_FIFO_SED_COUNT_MASK 0x00C00000L 2460#define SQC_EDC_CNT3__DATA_BANKB_DIRTY_BIT_RAM_SED_COUNT_MASK 0x03000000L 2461//SQ_REG_TIMESTAMP 2462#define SQ_REG_TIMESTAMP__TIMESTAMP__SHIFT 0x0 2463#define SQ_REG_TIMESTAMP__TIMESTAMP_MASK 0x000000FFL 2464//SQ_CMD_TIMESTAMP 2465#define SQ_CMD_TIMESTAMP__TIMESTAMP__SHIFT 0x0 2466#define SQ_CMD_TIMESTAMP__TIMESTAMP_MASK 0x000000FFL 2467//SQ_IND_INDEX 2468#define SQ_IND_INDEX__WAVE_ID__SHIFT 0x0 2469#define SQ_IND_INDEX__SIMD_ID__SHIFT 0x4 2470#define SQ_IND_INDEX__THREAD_ID__SHIFT 0x6 2471#define SQ_IND_INDEX__AUTO_INCR__SHIFT 0xc 2472#define SQ_IND_INDEX__FORCE_READ__SHIFT 0xd 2473#define SQ_IND_INDEX__READ_TIMEOUT__SHIFT 0xe 2474#define SQ_IND_INDEX__UNINDEXED__SHIFT 0xf 2475#define SQ_IND_INDEX__INDEX__SHIFT 0x10 2476#define SQ_IND_INDEX__WAVE_ID_MASK 0x0000000FL 2477#define SQ_IND_INDEX__SIMD_ID_MASK 0x00000030L 2478#define SQ_IND_INDEX__THREAD_ID_MASK 0x00000FC0L 2479#define SQ_IND_INDEX__AUTO_INCR_MASK 0x00001000L 2480#define SQ_IND_INDEX__FORCE_READ_MASK 0x00002000L 2481#define SQ_IND_INDEX__READ_TIMEOUT_MASK 0x00004000L 2482#define SQ_IND_INDEX__UNINDEXED_MASK 0x00008000L 2483#define SQ_IND_INDEX__INDEX_MASK 0xFFFF0000L 2484//SQ_IND_DATA 2485#define SQ_IND_DATA__DATA__SHIFT 0x0 2486#define SQ_IND_DATA__DATA_MASK 0xFFFFFFFFL 2487//SQ_CMD 2488#define SQ_CMD__CMD__SHIFT 0x0 2489#define SQ_CMD__MODE__SHIFT 0x4 2490#define SQ_CMD__CHECK_VMID__SHIFT 0x7 2491#define SQ_CMD__DATA__SHIFT 0x8 2492#define SQ_CMD__WAVE_ID__SHIFT 0x10 2493#define SQ_CMD__SIMD_ID__SHIFT 0x14 2494#define SQ_CMD__QUEUE_ID__SHIFT 0x18 2495#define SQ_CMD__VM_ID__SHIFT 0x1c 2496#define SQ_CMD__CMD_MASK 0x00000007L 2497#define SQ_CMD__MODE_MASK 0x00000070L 2498#define SQ_CMD__CHECK_VMID_MASK 0x00000080L 2499#define SQ_CMD__DATA_MASK 0x00000F00L 2500#define SQ_CMD__WAVE_ID_MASK 0x000F0000L 2501#define SQ_CMD__SIMD_ID_MASK 0x00300000L 2502#define SQ_CMD__QUEUE_ID_MASK 0x07000000L 2503#define SQ_CMD__VM_ID_MASK 0xF0000000L 2504//SQ_TIME_HI 2505#define SQ_TIME_HI__TIME__SHIFT 0x0 2506#define SQ_TIME_HI__TIME_MASK 0xFFFFFFFFL 2507//SQ_TIME_LO 2508#define SQ_TIME_LO__TIME__SHIFT 0x0 2509#define SQ_TIME_LO__TIME_MASK 0xFFFFFFFFL 2510//SQ_DS_0 2511#define SQ_DS_0__OFFSET0__SHIFT 0x0 2512#define SQ_DS_0__OFFSET1__SHIFT 0x8 2513#define SQ_DS_0__GDS__SHIFT 0x10 2514#define SQ_DS_0__OP__SHIFT 0x11 2515#define SQ_DS_0__ENCODING__SHIFT 0x1a 2516#define SQ_DS_0__OFFSET0_MASK 0x000000FFL 2517#define SQ_DS_0__OFFSET1_MASK 0x0000FF00L 2518#define SQ_DS_0__GDS_MASK 0x00010000L 2519#define SQ_DS_0__OP_MASK 0x01FE0000L 2520#define SQ_DS_0__ENCODING_MASK 0xFC000000L 2521//SQ_DS_1 2522#define SQ_DS_1__ADDR__SHIFT 0x0 2523#define SQ_DS_1__DATA0__SHIFT 0x8 2524#define SQ_DS_1__DATA1__SHIFT 0x10 2525#define SQ_DS_1__VDST__SHIFT 0x18 2526#define SQ_DS_1__ADDR_MASK 0x000000FFL 2527#define SQ_DS_1__DATA0_MASK 0x0000FF00L 2528#define SQ_DS_1__DATA1_MASK 0x00FF0000L 2529#define SQ_DS_1__VDST_MASK 0xFF000000L 2530//SQ_EXP_0 2531#define SQ_EXP_0__EN__SHIFT 0x0 2532#define SQ_EXP_0__TGT__SHIFT 0x4 2533#define SQ_EXP_0__COMPR__SHIFT 0xa 2534#define SQ_EXP_0__DONE__SHIFT 0xb 2535#define SQ_EXP_0__VM__SHIFT 0xc 2536#define SQ_EXP_0__ENCODING__SHIFT 0x1a 2537#define SQ_EXP_0__EN_MASK 0x0000000FL 2538#define SQ_EXP_0__TGT_MASK 0x000003F0L 2539#define SQ_EXP_0__COMPR_MASK 0x00000400L 2540#define SQ_EXP_0__DONE_MASK 0x00000800L 2541#define SQ_EXP_0__VM_MASK 0x00001000L 2542#define SQ_EXP_0__ENCODING_MASK 0xFC000000L 2543//SQ_EXP_1 2544#define SQ_EXP_1__VSRC0__SHIFT 0x0 2545#define SQ_EXP_1__VSRC1__SHIFT 0x8 2546#define SQ_EXP_1__VSRC2__SHIFT 0x10 2547#define SQ_EXP_1__VSRC3__SHIFT 0x18 2548#define SQ_EXP_1__VSRC0_MASK 0x000000FFL 2549#define SQ_EXP_1__VSRC1_MASK 0x0000FF00L 2550#define SQ_EXP_1__VSRC2_MASK 0x00FF0000L 2551#define SQ_EXP_1__VSRC3_MASK 0xFF000000L 2552//SQ_FLAT_0 2553#define SQ_FLAT_0__OFFSET__SHIFT 0x0 2554#define SQ_FLAT_0__LDS__SHIFT 0xd 2555#define SQ_FLAT_0__SEG__SHIFT 0xe 2556#define SQ_FLAT_0__GLC__SHIFT 0x10 2557#define SQ_FLAT_0__SLC__SHIFT 0x11 2558#define SQ_FLAT_0__OP__SHIFT 0x12 2559#define SQ_FLAT_0__ENCODING__SHIFT 0x1a 2560#define SQ_FLAT_0__OFFSET_MASK 0x00000FFFL 2561#define SQ_FLAT_0__LDS_MASK 0x00002000L 2562#define SQ_FLAT_0__SEG_MASK 0x0000C000L 2563#define SQ_FLAT_0__GLC_MASK 0x00010000L 2564#define SQ_FLAT_0__SLC_MASK 0x00020000L 2565#define SQ_FLAT_0__OP_MASK 0x01FC0000L 2566#define SQ_FLAT_0__ENCODING_MASK 0xFC000000L 2567//SQ_FLAT_1 2568#define SQ_FLAT_1__ADDR__SHIFT 0x0 2569#define SQ_FLAT_1__DATA__SHIFT 0x8 2570#define SQ_FLAT_1__SADDR__SHIFT 0x10 2571#define SQ_FLAT_1__NV__SHIFT 0x17 2572#define SQ_FLAT_1__VDST__SHIFT 0x18 2573#define SQ_FLAT_1__ADDR_MASK 0x000000FFL 2574#define SQ_FLAT_1__DATA_MASK 0x0000FF00L 2575#define SQ_FLAT_1__SADDR_MASK 0x007F0000L 2576#define SQ_FLAT_1__NV_MASK 0x00800000L 2577#define SQ_FLAT_1__VDST_MASK 0xFF000000L 2578//SQ_GLBL_0 2579#define SQ_GLBL_0__OFFSET__SHIFT 0x0 2580#define SQ_GLBL_0__LDS__SHIFT 0xd 2581#define SQ_GLBL_0__SEG__SHIFT 0xe 2582#define SQ_GLBL_0__GLC__SHIFT 0x10 2583#define SQ_GLBL_0__SLC__SHIFT 0x11 2584#define SQ_GLBL_0__OP__SHIFT 0x12 2585#define SQ_GLBL_0__ENCODING__SHIFT 0x1a 2586#define SQ_GLBL_0__OFFSET_MASK 0x00001FFFL 2587#define SQ_GLBL_0__LDS_MASK 0x00002000L 2588#define SQ_GLBL_0__SEG_MASK 0x0000C000L 2589#define SQ_GLBL_0__GLC_MASK 0x00010000L 2590#define SQ_GLBL_0__SLC_MASK 0x00020000L 2591#define SQ_GLBL_0__OP_MASK 0x01FC0000L 2592#define SQ_GLBL_0__ENCODING_MASK 0xFC000000L 2593//SQ_GLBL_1 2594#define SQ_GLBL_1__ADDR__SHIFT 0x0 2595#define SQ_GLBL_1__DATA__SHIFT 0x8 2596#define SQ_GLBL_1__SADDR__SHIFT 0x10 2597#define SQ_GLBL_1__NV__SHIFT 0x17 2598#define SQ_GLBL_1__VDST__SHIFT 0x18 2599#define SQ_GLBL_1__ADDR_MASK 0x000000FFL 2600#define SQ_GLBL_1__DATA_MASK 0x0000FF00L 2601#define SQ_GLBL_1__SADDR_MASK 0x007F0000L 2602#define SQ_GLBL_1__NV_MASK 0x00800000L 2603#define SQ_GLBL_1__VDST_MASK 0xFF000000L 2604//SQ_INST 2605#define SQ_INST__ENCODING__SHIFT 0x0 2606#define SQ_INST__ENCODING_MASK 0xFFFFFFFFL 2607//SQ_MIMG_0 2608#define SQ_MIMG_0__OPM__SHIFT 0x0 2609#define SQ_MIMG_0__DMASK__SHIFT 0x8 2610#define SQ_MIMG_0__UNORM__SHIFT 0xc 2611#define SQ_MIMG_0__GLC__SHIFT 0xd 2612#define SQ_MIMG_0__DA__SHIFT 0xe 2613#define SQ_MIMG_0__A16__SHIFT 0xf 2614#define SQ_MIMG_0__TFE__SHIFT 0x10 2615#define SQ_MIMG_0__LWE__SHIFT 0x11 2616#define SQ_MIMG_0__OP__SHIFT 0x12 2617#define SQ_MIMG_0__SLC__SHIFT 0x19 2618#define SQ_MIMG_0__ENCODING__SHIFT 0x1a 2619#define SQ_MIMG_0__OPM_MASK 0x00000001L 2620#define SQ_MIMG_0__DMASK_MASK 0x00000F00L 2621#define SQ_MIMG_0__UNORM_MASK 0x00001000L 2622#define SQ_MIMG_0__GLC_MASK 0x00002000L 2623#define SQ_MIMG_0__DA_MASK 0x00004000L 2624#define SQ_MIMG_0__A16_MASK 0x00008000L 2625#define SQ_MIMG_0__TFE_MASK 0x00010000L 2626#define SQ_MIMG_0__LWE_MASK 0x00020000L 2627#define SQ_MIMG_0__OP_MASK 0x01FC0000L 2628#define SQ_MIMG_0__SLC_MASK 0x02000000L 2629#define SQ_MIMG_0__ENCODING_MASK 0xFC000000L 2630//SQ_MIMG_1 2631#define SQ_MIMG_1__VADDR__SHIFT 0x0 2632#define SQ_MIMG_1__VDATA__SHIFT 0x8 2633#define SQ_MIMG_1__SRSRC__SHIFT 0x10 2634#define SQ_MIMG_1__SSAMP__SHIFT 0x15 2635#define SQ_MIMG_1__D16__SHIFT 0x1f 2636#define SQ_MIMG_1__VADDR_MASK 0x000000FFL 2637#define SQ_MIMG_1__VDATA_MASK 0x0000FF00L 2638#define SQ_MIMG_1__SRSRC_MASK 0x001F0000L 2639#define SQ_MIMG_1__SSAMP_MASK 0x03E00000L 2640#define SQ_MIMG_1__D16_MASK 0x80000000L 2641//SQ_MTBUF_0 2642#define SQ_MTBUF_0__OFFSET__SHIFT 0x0 2643#define SQ_MTBUF_0__OFFEN__SHIFT 0xc 2644#define SQ_MTBUF_0__IDXEN__SHIFT 0xd 2645#define SQ_MTBUF_0__GLC__SHIFT 0xe 2646#define SQ_MTBUF_0__OP__SHIFT 0xf 2647#define SQ_MTBUF_0__DFMT__SHIFT 0x13 2648#define SQ_MTBUF_0__NFMT__SHIFT 0x17 2649#define SQ_MTBUF_0__ENCODING__SHIFT 0x1a 2650#define SQ_MTBUF_0__OFFSET_MASK 0x00000FFFL 2651#define SQ_MTBUF_0__OFFEN_MASK 0x00001000L 2652#define SQ_MTBUF_0__IDXEN_MASK 0x00002000L 2653#define SQ_MTBUF_0__GLC_MASK 0x00004000L 2654#define SQ_MTBUF_0__OP_MASK 0x00078000L 2655#define SQ_MTBUF_0__DFMT_MASK 0x00780000L 2656#define SQ_MTBUF_0__NFMT_MASK 0x03800000L 2657#define SQ_MTBUF_0__ENCODING_MASK 0xFC000000L 2658//SQ_MTBUF_1 2659#define SQ_MTBUF_1__VADDR__SHIFT 0x0 2660#define SQ_MTBUF_1__VDATA__SHIFT 0x8 2661#define SQ_MTBUF_1__SRSRC__SHIFT 0x10 2662#define SQ_MTBUF_1__SLC__SHIFT 0x16 2663#define SQ_MTBUF_1__TFE__SHIFT 0x17 2664#define SQ_MTBUF_1__SOFFSET__SHIFT 0x18 2665#define SQ_MTBUF_1__VADDR_MASK 0x000000FFL 2666#define SQ_MTBUF_1__VDATA_MASK 0x0000FF00L 2667#define SQ_MTBUF_1__SRSRC_MASK 0x001F0000L 2668#define SQ_MTBUF_1__SLC_MASK 0x00400000L 2669#define SQ_MTBUF_1__TFE_MASK 0x00800000L 2670#define SQ_MTBUF_1__SOFFSET_MASK 0xFF000000L 2671//SQ_MUBUF_0 2672#define SQ_MUBUF_0__OFFSET__SHIFT 0x0 2673#define SQ_MUBUF_0__OFFEN__SHIFT 0xc 2674#define SQ_MUBUF_0__IDXEN__SHIFT 0xd 2675#define SQ_MUBUF_0__GLC__SHIFT 0xe 2676#define SQ_MUBUF_0__LDS__SHIFT 0x10 2677#define SQ_MUBUF_0__SLC__SHIFT 0x11 2678#define SQ_MUBUF_0__OP__SHIFT 0x12 2679#define SQ_MUBUF_0__ENCODING__SHIFT 0x1a 2680#define SQ_MUBUF_0__OFFSET_MASK 0x00000FFFL 2681#define SQ_MUBUF_0__OFFEN_MASK 0x00001000L 2682#define SQ_MUBUF_0__IDXEN_MASK 0x00002000L 2683#define SQ_MUBUF_0__GLC_MASK 0x00004000L 2684#define SQ_MUBUF_0__LDS_MASK 0x00010000L 2685#define SQ_MUBUF_0__SLC_MASK 0x00020000L 2686#define SQ_MUBUF_0__OP_MASK 0x01FC0000L 2687#define SQ_MUBUF_0__ENCODING_MASK 0xFC000000L 2688//SQ_MUBUF_1 2689#define SQ_MUBUF_1__VADDR__SHIFT 0x0 2690#define SQ_MUBUF_1__VDATA__SHIFT 0x8 2691#define SQ_MUBUF_1__SRSRC__SHIFT 0x10 2692#define SQ_MUBUF_1__TFE__SHIFT 0x17 2693#define SQ_MUBUF_1__SOFFSET__SHIFT 0x18 2694#define SQ_MUBUF_1__VADDR_MASK 0x000000FFL 2695#define SQ_MUBUF_1__VDATA_MASK 0x0000FF00L 2696#define SQ_MUBUF_1__SRSRC_MASK 0x001F0000L 2697#define SQ_MUBUF_1__TFE_MASK 0x00800000L 2698#define SQ_MUBUF_1__SOFFSET_MASK 0xFF000000L 2699//SQ_SCRATCH_0 2700#define SQ_SCRATCH_0__OFFSET__SHIFT 0x0 2701#define SQ_SCRATCH_0__LDS__SHIFT 0xd 2702#define SQ_SCRATCH_0__SEG__SHIFT 0xe 2703#define SQ_SCRATCH_0__GLC__SHIFT 0x10 2704#define SQ_SCRATCH_0__SLC__SHIFT 0x11 2705#define SQ_SCRATCH_0__OP__SHIFT 0x12 2706#define SQ_SCRATCH_0__ENCODING__SHIFT 0x1a 2707#define SQ_SCRATCH_0__OFFSET_MASK 0x00001FFFL 2708#define SQ_SCRATCH_0__LDS_MASK 0x00002000L 2709#define SQ_SCRATCH_0__SEG_MASK 0x0000C000L 2710#define SQ_SCRATCH_0__GLC_MASK 0x00010000L 2711#define SQ_SCRATCH_0__SLC_MASK 0x00020000L 2712#define SQ_SCRATCH_0__OP_MASK 0x01FC0000L 2713#define SQ_SCRATCH_0__ENCODING_MASK 0xFC000000L 2714//SQ_SCRATCH_1 2715#define SQ_SCRATCH_1__ADDR__SHIFT 0x0 2716#define SQ_SCRATCH_1__DATA__SHIFT 0x8 2717#define SQ_SCRATCH_1__SADDR__SHIFT 0x10 2718#define SQ_SCRATCH_1__NV__SHIFT 0x17 2719#define SQ_SCRATCH_1__VDST__SHIFT 0x18 2720#define SQ_SCRATCH_1__ADDR_MASK 0x000000FFL 2721#define SQ_SCRATCH_1__DATA_MASK 0x0000FF00L 2722#define SQ_SCRATCH_1__SADDR_MASK 0x007F0000L 2723#define SQ_SCRATCH_1__NV_MASK 0x00800000L 2724#define SQ_SCRATCH_1__VDST_MASK 0xFF000000L 2725//SQ_SMEM_0 2726#define SQ_SMEM_0__SBASE__SHIFT 0x0 2727#define SQ_SMEM_0__SDATA__SHIFT 0x6 2728#define SQ_SMEM_0__SOFFSET_EN__SHIFT 0xe 2729#define SQ_SMEM_0__NV__SHIFT 0xf 2730#define SQ_SMEM_0__GLC__SHIFT 0x10 2731#define SQ_SMEM_0__IMM__SHIFT 0x11 2732#define SQ_SMEM_0__OP__SHIFT 0x12 2733#define SQ_SMEM_0__ENCODING__SHIFT 0x1a 2734#define SQ_SMEM_0__SBASE_MASK 0x0000003FL 2735#define SQ_SMEM_0__SDATA_MASK 0x00001FC0L 2736#define SQ_SMEM_0__SOFFSET_EN_MASK 0x00004000L 2737#define SQ_SMEM_0__NV_MASK 0x00008000L 2738#define SQ_SMEM_0__GLC_MASK 0x00010000L 2739#define SQ_SMEM_0__IMM_MASK 0x00020000L 2740#define SQ_SMEM_0__OP_MASK 0x03FC0000L 2741#define SQ_SMEM_0__ENCODING_MASK 0xFC000000L 2742//SQ_SMEM_1 2743#define SQ_SMEM_1__OFFSET__SHIFT 0x0 2744#define SQ_SMEM_1__SOFFSET__SHIFT 0x19 2745#define SQ_SMEM_1__OFFSET_MASK 0x001FFFFFL 2746#define SQ_SMEM_1__SOFFSET_MASK 0xFE000000L 2747//SQ_SOP1 2748#define SQ_SOP1__SSRC0__SHIFT 0x0 2749#define SQ_SOP1__OP__SHIFT 0x8 2750#define SQ_SOP1__SDST__SHIFT 0x10 2751#define SQ_SOP1__ENCODING__SHIFT 0x17 2752#define SQ_SOP1__SSRC0_MASK 0x000000FFL 2753#define SQ_SOP1__OP_MASK 0x0000FF00L 2754#define SQ_SOP1__SDST_MASK 0x007F0000L 2755#define SQ_SOP1__ENCODING_MASK 0xFF800000L 2756//SQ_SOP2 2757#define SQ_SOP2__SSRC0__SHIFT 0x0 2758#define SQ_SOP2__SSRC1__SHIFT 0x8 2759#define SQ_SOP2__SDST__SHIFT 0x10 2760#define SQ_SOP2__OP__SHIFT 0x17 2761#define SQ_SOP2__ENCODING__SHIFT 0x1e 2762#define SQ_SOP2__SSRC0_MASK 0x000000FFL 2763#define SQ_SOP2__SSRC1_MASK 0x0000FF00L 2764#define SQ_SOP2__SDST_MASK 0x007F0000L 2765#define SQ_SOP2__OP_MASK 0x3F800000L 2766#define SQ_SOP2__ENCODING_MASK 0xC0000000L 2767//SQ_SOPC 2768#define SQ_SOPC__SSRC0__SHIFT 0x0 2769#define SQ_SOPC__SSRC1__SHIFT 0x8 2770#define SQ_SOPC__OP__SHIFT 0x10 2771#define SQ_SOPC__ENCODING__SHIFT 0x17 2772#define SQ_SOPC__SSRC0_MASK 0x000000FFL 2773#define SQ_SOPC__SSRC1_MASK 0x0000FF00L 2774#define SQ_SOPC__OP_MASK 0x007F0000L 2775#define SQ_SOPC__ENCODING_MASK 0xFF800000L 2776//SQ_SOPK 2777#define SQ_SOPK__SIMM16__SHIFT 0x0 2778#define SQ_SOPK__SDST__SHIFT 0x10 2779#define SQ_SOPK__OP__SHIFT 0x17 2780#define SQ_SOPK__ENCODING__SHIFT 0x1c 2781#define SQ_SOPK__SIMM16_MASK 0x0000FFFFL 2782#define SQ_SOPK__SDST_MASK 0x007F0000L 2783#define SQ_SOPK__OP_MASK 0x0F800000L 2784#define SQ_SOPK__ENCODING_MASK 0xF0000000L 2785//SQ_SOPP 2786#define SQ_SOPP__SIMM16__SHIFT 0x0 2787#define SQ_SOPP__OP__SHIFT 0x10 2788#define SQ_SOPP__ENCODING__SHIFT 0x17 2789#define SQ_SOPP__SIMM16_MASK 0x0000FFFFL 2790#define SQ_SOPP__OP_MASK 0x007F0000L 2791#define SQ_SOPP__ENCODING_MASK 0xFF800000L 2792//SQ_VINTRP 2793#define SQ_VINTRP__VSRC__SHIFT 0x0 2794#define SQ_VINTRP__ATTRCHAN__SHIFT 0x8 2795#define SQ_VINTRP__ATTR__SHIFT 0xa 2796#define SQ_VINTRP__OP__SHIFT 0x10 2797#define SQ_VINTRP__VDST__SHIFT 0x12 2798#define SQ_VINTRP__ENCODING__SHIFT 0x1a 2799#define SQ_VINTRP__VSRC_MASK 0x000000FFL 2800#define SQ_VINTRP__ATTRCHAN_MASK 0x00000300L 2801#define SQ_VINTRP__ATTR_MASK 0x0000FC00L 2802#define SQ_VINTRP__OP_MASK 0x00030000L 2803#define SQ_VINTRP__VDST_MASK 0x03FC0000L 2804#define SQ_VINTRP__ENCODING_MASK 0xFC000000L 2805//SQ_VOP1 2806#define SQ_VOP1__SRC0__SHIFT 0x0 2807#define SQ_VOP1__OP__SHIFT 0x9 2808#define SQ_VOP1__VDST__SHIFT 0x11 2809#define SQ_VOP1__ENCODING__SHIFT 0x19 2810#define SQ_VOP1__SRC0_MASK 0x000001FFL 2811#define SQ_VOP1__OP_MASK 0x0001FE00L 2812#define SQ_VOP1__VDST_MASK 0x01FE0000L 2813#define SQ_VOP1__ENCODING_MASK 0xFE000000L 2814//SQ_VOP2 2815#define SQ_VOP2__SRC0__SHIFT 0x0 2816#define SQ_VOP2__VSRC1__SHIFT 0x9 2817#define SQ_VOP2__VDST__SHIFT 0x11 2818#define SQ_VOP2__OP__SHIFT 0x19 2819#define SQ_VOP2__ENCODING__SHIFT 0x1f 2820#define SQ_VOP2__SRC0_MASK 0x000001FFL 2821#define SQ_VOP2__VSRC1_MASK 0x0001FE00L 2822#define SQ_VOP2__VDST_MASK 0x01FE0000L 2823#define SQ_VOP2__OP_MASK 0x7E000000L 2824#define SQ_VOP2__ENCODING_MASK 0x80000000L 2825//SQ_VOP3P_0 2826#define SQ_VOP3P_0__VDST__SHIFT 0x0 2827#define SQ_VOP3P_0__NEG_HI__SHIFT 0x8 2828#define SQ_VOP3P_0__OP_SEL__SHIFT 0xb 2829#define SQ_VOP3P_0__OP_SEL_HI_2__SHIFT 0xe 2830#define SQ_VOP3P_0__CLAMP__SHIFT 0xf 2831#define SQ_VOP3P_0__OP__SHIFT 0x10 2832#define SQ_VOP3P_0__ENCODING__SHIFT 0x17 2833#define SQ_VOP3P_0__VDST_MASK 0x000000FFL 2834#define SQ_VOP3P_0__NEG_HI_MASK 0x00000700L 2835#define SQ_VOP3P_0__OP_SEL_MASK 0x00003800L 2836#define SQ_VOP3P_0__OP_SEL_HI_2_MASK 0x00004000L 2837#define SQ_VOP3P_0__CLAMP_MASK 0x00008000L 2838#define SQ_VOP3P_0__OP_MASK 0x007F0000L 2839#define SQ_VOP3P_0__ENCODING_MASK 0xFF800000L 2840//SQ_VOP3P_1 2841#define SQ_VOP3P_1__SRC0__SHIFT 0x0 2842#define SQ_VOP3P_1__SRC1__SHIFT 0x9 2843#define SQ_VOP3P_1__SRC2__SHIFT 0x12 2844#define SQ_VOP3P_1__OP_SEL_HI__SHIFT 0x1b 2845#define SQ_VOP3P_1__NEG__SHIFT 0x1d 2846#define SQ_VOP3P_1__SRC0_MASK 0x000001FFL 2847#define SQ_VOP3P_1__SRC1_MASK 0x0003FE00L 2848#define SQ_VOP3P_1__SRC2_MASK 0x07FC0000L 2849#define SQ_VOP3P_1__OP_SEL_HI_MASK 0x18000000L 2850#define SQ_VOP3P_1__NEG_MASK 0xE0000000L 2851//SQ_VOP3_0 2852#define SQ_VOP3_0__VDST__SHIFT 0x0 2853#define SQ_VOP3_0__ABS__SHIFT 0x8 2854#define SQ_VOP3_0__OP_SEL__SHIFT 0xb 2855#define SQ_VOP3_0__CLAMP__SHIFT 0xf 2856#define SQ_VOP3_0__OP__SHIFT 0x10 2857#define SQ_VOP3_0__ENCODING__SHIFT 0x1a 2858#define SQ_VOP3_0__VDST_MASK 0x000000FFL 2859#define SQ_VOP3_0__ABS_MASK 0x00000700L 2860#define SQ_VOP3_0__OP_SEL_MASK 0x00007800L 2861#define SQ_VOP3_0__CLAMP_MASK 0x00008000L 2862#define SQ_VOP3_0__OP_MASK 0x03FF0000L 2863#define SQ_VOP3_0__ENCODING_MASK 0xFC000000L 2864//SQ_VOP3_0_SDST_ENC 2865#define SQ_VOP3_0_SDST_ENC__VDST__SHIFT 0x0 2866#define SQ_VOP3_0_SDST_ENC__SDST__SHIFT 0x8 2867#define SQ_VOP3_0_SDST_ENC__CLAMP__SHIFT 0xf 2868#define SQ_VOP3_0_SDST_ENC__OP__SHIFT 0x10 2869#define SQ_VOP3_0_SDST_ENC__ENCODING__SHIFT 0x1a 2870#define SQ_VOP3_0_SDST_ENC__VDST_MASK 0x000000FFL 2871#define SQ_VOP3_0_SDST_ENC__SDST_MASK 0x00007F00L 2872#define SQ_VOP3_0_SDST_ENC__CLAMP_MASK 0x00008000L 2873#define SQ_VOP3_0_SDST_ENC__OP_MASK 0x03FF0000L 2874#define SQ_VOP3_0_SDST_ENC__ENCODING_MASK 0xFC000000L 2875//SQ_VOP3_1 2876#define SQ_VOP3_1__SRC0__SHIFT 0x0 2877#define SQ_VOP3_1__SRC1__SHIFT 0x9 2878#define SQ_VOP3_1__SRC2__SHIFT 0x12 2879#define SQ_VOP3_1__OMOD__SHIFT 0x1b 2880#define SQ_VOP3_1__NEG__SHIFT 0x1d 2881#define SQ_VOP3_1__SRC0_MASK 0x000001FFL 2882#define SQ_VOP3_1__SRC1_MASK 0x0003FE00L 2883#define SQ_VOP3_1__SRC2_MASK 0x07FC0000L 2884#define SQ_VOP3_1__OMOD_MASK 0x18000000L 2885#define SQ_VOP3_1__NEG_MASK 0xE0000000L 2886//SQ_VOPC 2887#define SQ_VOPC__SRC0__SHIFT 0x0 2888#define SQ_VOPC__VSRC1__SHIFT 0x9 2889#define SQ_VOPC__OP__SHIFT 0x11 2890#define SQ_VOPC__ENCODING__SHIFT 0x19 2891#define SQ_VOPC__SRC0_MASK 0x000001FFL 2892#define SQ_VOPC__VSRC1_MASK 0x0001FE00L 2893#define SQ_VOPC__OP_MASK 0x01FE0000L 2894#define SQ_VOPC__ENCODING_MASK 0xFE000000L 2895//SQ_VOP_DPP 2896#define SQ_VOP_DPP__SRC0__SHIFT 0x0 2897#define SQ_VOP_DPP__DPP_CTRL__SHIFT 0x8 2898#define SQ_VOP_DPP__BOUND_CTRL__SHIFT 0x13 2899#define SQ_VOP_DPP__SRC0_NEG__SHIFT 0x14 2900#define SQ_VOP_DPP__SRC0_ABS__SHIFT 0x15 2901#define SQ_VOP_DPP__SRC1_NEG__SHIFT 0x16 2902#define SQ_VOP_DPP__SRC1_ABS__SHIFT 0x17 2903#define SQ_VOP_DPP__BANK_MASK__SHIFT 0x18 2904#define SQ_VOP_DPP__ROW_MASK__SHIFT 0x1c 2905#define SQ_VOP_DPP__SRC0_MASK 0x000000FFL 2906#define SQ_VOP_DPP__DPP_CTRL_MASK 0x0001FF00L 2907#define SQ_VOP_DPP__BOUND_CTRL_MASK 0x00080000L 2908#define SQ_VOP_DPP__SRC0_NEG_MASK 0x00100000L 2909#define SQ_VOP_DPP__SRC0_ABS_MASK 0x00200000L 2910#define SQ_VOP_DPP__SRC1_NEG_MASK 0x00400000L 2911#define SQ_VOP_DPP__SRC1_ABS_MASK 0x00800000L 2912#define SQ_VOP_DPP__BANK_MASK_MASK 0x0F000000L 2913#define SQ_VOP_DPP__ROW_MASK_MASK 0xF0000000L 2914//SQ_VOP_SDWA 2915#define SQ_VOP_SDWA__SRC0__SHIFT 0x0 2916#define SQ_VOP_SDWA__DST_SEL__SHIFT 0x8 2917#define SQ_VOP_SDWA__DST_UNUSED__SHIFT 0xb 2918#define SQ_VOP_SDWA__CLAMP__SHIFT 0xd 2919#define SQ_VOP_SDWA__OMOD__SHIFT 0xe 2920#define SQ_VOP_SDWA__SRC0_SEL__SHIFT 0x10 2921#define SQ_VOP_SDWA__SRC0_SEXT__SHIFT 0x13 2922#define SQ_VOP_SDWA__SRC0_NEG__SHIFT 0x14 2923#define SQ_VOP_SDWA__SRC0_ABS__SHIFT 0x15 2924#define SQ_VOP_SDWA__S0__SHIFT 0x17 2925#define SQ_VOP_SDWA__SRC1_SEL__SHIFT 0x18 2926#define SQ_VOP_SDWA__SRC1_SEXT__SHIFT 0x1b 2927#define SQ_VOP_SDWA__SRC1_NEG__SHIFT 0x1c 2928#define SQ_VOP_SDWA__SRC1_ABS__SHIFT 0x1d 2929#define SQ_VOP_SDWA__S1__SHIFT 0x1f 2930#define SQ_VOP_SDWA__SRC0_MASK 0x000000FFL 2931#define SQ_VOP_SDWA__DST_SEL_MASK 0x00000700L 2932#define SQ_VOP_SDWA__DST_UNUSED_MASK 0x00001800L 2933#define SQ_VOP_SDWA__CLAMP_MASK 0x00002000L 2934#define SQ_VOP_SDWA__OMOD_MASK 0x0000C000L 2935#define SQ_VOP_SDWA__SRC0_SEL_MASK 0x00070000L 2936#define SQ_VOP_SDWA__SRC0_SEXT_MASK 0x00080000L 2937#define SQ_VOP_SDWA__SRC0_NEG_MASK 0x00100000L 2938#define SQ_VOP_SDWA__SRC0_ABS_MASK 0x00200000L 2939#define SQ_VOP_SDWA__S0_MASK 0x00800000L 2940#define SQ_VOP_SDWA__SRC1_SEL_MASK 0x07000000L 2941#define SQ_VOP_SDWA__SRC1_SEXT_MASK 0x08000000L 2942#define SQ_VOP_SDWA__SRC1_NEG_MASK 0x10000000L 2943#define SQ_VOP_SDWA__SRC1_ABS_MASK 0x20000000L 2944#define SQ_VOP_SDWA__S1_MASK 0x80000000L 2945//SQ_VOP_SDWA_SDST_ENC 2946#define SQ_VOP_SDWA_SDST_ENC__SRC0__SHIFT 0x0 2947#define SQ_VOP_SDWA_SDST_ENC__SDST__SHIFT 0x8 2948#define SQ_VOP_SDWA_SDST_ENC__SD__SHIFT 0xf 2949#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEL__SHIFT 0x10 2950#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEXT__SHIFT 0x13 2951#define SQ_VOP_SDWA_SDST_ENC__SRC0_NEG__SHIFT 0x14 2952#define SQ_VOP_SDWA_SDST_ENC__SRC0_ABS__SHIFT 0x15 2953#define SQ_VOP_SDWA_SDST_ENC__S0__SHIFT 0x17 2954#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEL__SHIFT 0x18 2955#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEXT__SHIFT 0x1b 2956#define SQ_VOP_SDWA_SDST_ENC__SRC1_NEG__SHIFT 0x1c 2957#define SQ_VOP_SDWA_SDST_ENC__SRC1_ABS__SHIFT 0x1d 2958#define SQ_VOP_SDWA_SDST_ENC__S1__SHIFT 0x1f 2959#define SQ_VOP_SDWA_SDST_ENC__SRC0_MASK 0x000000FFL 2960#define SQ_VOP_SDWA_SDST_ENC__SDST_MASK 0x00007F00L 2961#define SQ_VOP_SDWA_SDST_ENC__SD_MASK 0x00008000L 2962#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEL_MASK 0x00070000L 2963#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEXT_MASK 0x00080000L 2964#define SQ_VOP_SDWA_SDST_ENC__SRC0_NEG_MASK 0x00100000L 2965#define SQ_VOP_SDWA_SDST_ENC__SRC0_ABS_MASK 0x00200000L 2966#define SQ_VOP_SDWA_SDST_ENC__S0_MASK 0x00800000L 2967#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEL_MASK 0x07000000L 2968#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEXT_MASK 0x08000000L 2969#define SQ_VOP_SDWA_SDST_ENC__SRC1_NEG_MASK 0x10000000L 2970#define SQ_VOP_SDWA_SDST_ENC__SRC1_ABS_MASK 0x20000000L 2971#define SQ_VOP_SDWA_SDST_ENC__S1_MASK 0x80000000L 2972//SQ_LB_CTR_CTRL 2973#define SQ_LB_CTR_CTRL__START__SHIFT 0x0 2974#define SQ_LB_CTR_CTRL__LOAD__SHIFT 0x1 2975#define SQ_LB_CTR_CTRL__CLEAR__SHIFT 0x2 2976#define SQ_LB_CTR_CTRL__START_MASK 0x00000001L 2977#define SQ_LB_CTR_CTRL__LOAD_MASK 0x00000002L 2978#define SQ_LB_CTR_CTRL__CLEAR_MASK 0x00000004L 2979//SQ_LB_DATA0 2980#define SQ_LB_DATA0__DATA__SHIFT 0x0 2981#define SQ_LB_DATA0__DATA_MASK 0xFFFFFFFFL 2982//SQ_LB_DATA1 2983#define SQ_LB_DATA1__DATA__SHIFT 0x0 2984#define SQ_LB_DATA1__DATA_MASK 0xFFFFFFFFL 2985//SQ_LB_DATA2 2986#define SQ_LB_DATA2__DATA__SHIFT 0x0 2987#define SQ_LB_DATA2__DATA_MASK 0xFFFFFFFFL 2988//SQ_LB_DATA3 2989#define SQ_LB_DATA3__DATA__SHIFT 0x0 2990#define SQ_LB_DATA3__DATA_MASK 0xFFFFFFFFL 2991//SQ_LB_CTR_SEL 2992#define SQ_LB_CTR_SEL__SEL0__SHIFT 0x0 2993#define SQ_LB_CTR_SEL__SEL1__SHIFT 0x4 2994#define SQ_LB_CTR_SEL__SEL2__SHIFT 0x8 2995#define SQ_LB_CTR_SEL__SEL3__SHIFT 0xc 2996#define SQ_LB_CTR_SEL__SEL0_MASK 0x0000000FL 2997#define SQ_LB_CTR_SEL__SEL1_MASK 0x000000F0L 2998#define SQ_LB_CTR_SEL__SEL2_MASK 0x00000F00L 2999#define SQ_LB_CTR_SEL__SEL3_MASK 0x0000F000L 3000//SQ_LB_CTR0_CU
3001#define SQ_LB_CTR0_CU__SH0_MASK__SHIFT 0x0 3002#define SQ_LB_CTR0_CU__SH1_MASK__SHIFT 0x10 3003#define SQ_LB_CTR0_CU__SH0_MASK_MASK 0x0000FFFFL 3004#define SQ_LB_CTR0_CU__SH1_MASK_MASK 0xFFFF0000L 3005//SQ_LB_CTR1_CU 3006#define SQ_LB_CTR1_CU__SH0_MASK__SHIFT 0x0 3007#define SQ_LB_CTR1_CU__SH1_MASK__SHIFT 0x10 3008#define SQ_LB_CTR1_CU__SH0_MASK_MASK 0x0000FFFFL 3009#define SQ_LB_CTR1_CU__SH1_MASK_MASK 0xFFFF0000L 3010//SQ_LB_CTR2_CU 3011#define SQ_LB_CTR2_CU__SH0_MASK__SHIFT 0x0 3012#define SQ_LB_CTR2_CU__SH1_MASK__SHIFT 0x10 3013#define SQ_LB_CTR2_CU__SH0_MASK_MASK 0x0000FFFFL 3014#define SQ_LB_CTR2_CU__SH1_MASK_MASK 0xFFFF0000L 3015//SQ_LB_CTR3_CU 3016#define SQ_LB_CTR3_CU__SH0_MASK__SHIFT 0x0 3017#define SQ_LB_CTR3_CU__SH1_MASK__SHIFT 0x10 3018#define SQ_LB_CTR3_CU__SH0_MASK_MASK 0x0000FFFFL 3019#define SQ_LB_CTR3_CU__SH1_MASK_MASK 0xFFFF0000L 3020//SQC_EDC_CNT 3021#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x0 3022#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_DED_COUNT__SHIFT 0x2 3023#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x4 3024#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_DED_COUNT__SHIFT 0x6 3025#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x8 3026#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_DED_COUNT__SHIFT 0xa 3027#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_SEC_COUNT__SHIFT 0xc 3028#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_DED_COUNT__SHIFT 0xe 3029#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x10 3030#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_DED_COUNT__SHIFT 0x12 3031#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x14 3032#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_DED_COUNT__SHIFT 0x16 3033#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x18 3034#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_DED_COUNT__SHIFT 0x1a 3035#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x1c 3036#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_DED_COUNT__SHIFT 0x1e 3037#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_SEC_COUNT_MASK 0x00000003L 3038#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_DED_COUNT_MASK 0x0000000CL 3039#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_SEC_COUNT_MASK 0x00000030L 3040#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_DED_COUNT_MASK 0x000000C0L 3041#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_SEC_COUNT_MASK 0x00000300L 3042#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_DED_COUNT_MASK 0x00000C00L 3043#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_SEC_COUNT_MASK 0x00003000L 3044#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_DED_COUNT_MASK 0x0000C000L 3045#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_SEC_COUNT_MASK 0x00030000L 3046#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_DED_COUNT_MASK 0x000C0000L 3047#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_SEC_COUNT_MASK 0x00300000L 3048#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_DED_COUNT_MASK 0x00C00000L 3049#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_SEC_COUNT_MASK 0x03000000L 3050#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_DED_COUNT_MASK 0x0C000000L 3051#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_SEC_COUNT_MASK 0x30000000L 3052#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_DED_COUNT_MASK 0xC0000000L 3053//SQ_EDC_SEC_CNT 3054#define SQ_EDC_SEC_CNT__LDS_SEC__SHIFT 0x0 3055#define SQ_EDC_SEC_CNT__SGPR_SEC__SHIFT 0x8 3056#define SQ_EDC_SEC_CNT__VGPR_SEC__SHIFT 0x10 3057#define SQ_EDC_SEC_CNT__LDS_SEC_MASK 0x000000FFL 3058#define SQ_EDC_SEC_CNT__SGPR_SEC_MASK 0x0000FF00L 3059#define SQ_EDC_SEC_CNT__VGPR_SEC_MASK 0x00FF0000L 3060//SQ_EDC_DED_CNT 3061#define SQ_EDC_DED_CNT__LDS_DED__SHIFT 0x0 3062#define SQ_EDC_DED_CNT__SGPR_DED__SHIFT 0x8 3063#define SQ_EDC_DED_CNT__VGPR_DED__SHIFT 0x10 3064#define SQ_EDC_DED_CNT__LDS_DED_MASK 0x000000FFL 3065#define SQ_EDC_DED_CNT__SGPR_DED_MASK 0x0000FF00L 3066#define SQ_EDC_DED_CNT__VGPR_DED_MASK 0x00FF0000L 3067//SQ_EDC_INFO 3068#define SQ_EDC_INFO__WAVE_ID__SHIFT 0x0 3069#define SQ_EDC_INFO__SIMD_ID__SHIFT 0x4 3070#define SQ_EDC_INFO__SOURCE__SHIFT 0x6 3071#define SQ_EDC_INFO__VM_ID__SHIFT 0x9 3072#define SQ_EDC_INFO__WAVE_ID_MASK 0x0000000FL 3073#define SQ_EDC_INFO__SIMD_ID_MASK 0x00000030L 3074#define SQ_EDC_INFO__SOURCE_MASK 0x000001C0L 3075#define SQ_EDC_INFO__VM_ID_MASK 0x00001E00L 3076//SQ_EDC_CNT 3077#define SQ_EDC_CNT__LDS_D_SEC_COUNT__SHIFT 0x0 3078#define SQ_EDC_CNT__LDS_D_DED_COUNT__SHIFT 0x2 3079#define SQ_EDC_CNT__LDS_I_SEC_COUNT__SHIFT 0x4 3080#define SQ_EDC_CNT__LDS_I_DED_COUNT__SHIFT 0x6 3081#define SQ_EDC_CNT__SGPR_SEC_COUNT__SHIFT 0x8 3082#define SQ_EDC_CNT__SGPR_DED_COUNT__SHIFT 0xa 3083#define SQ_EDC_CNT__VGPR0_SEC_COUNT__SHIFT 0xc 3084#define SQ_EDC_CNT__VGPR0_DED_COUNT__SHIFT 0xe 3085#define SQ_EDC_CNT__VGPR1_SEC_COUNT__SHIFT 0x10 3086#define SQ_EDC_CNT__VGPR1_DED_COUNT__SHIFT 0x12 3087#define SQ_EDC_CNT__VGPR2_SEC_COUNT__SHIFT 0x14 3088#define SQ_EDC_CNT__VGPR2_DED_COUNT__SHIFT 0x16 3089#define SQ_EDC_CNT__VGPR3_SEC_COUNT__SHIFT 0x18 3090#define SQ_EDC_CNT__VGPR3_DED_COUNT__SHIFT 0x1a 3091#define SQ_EDC_CNT__LDS_D_SEC_COUNT_MASK 0x00000003L 3092#define SQ_EDC_CNT__LDS_D_DED_COUNT_MASK 0x0000000CL 3093#define SQ_EDC_CNT__LDS_I_SEC_COUNT_MASK 0x00000030L 3094#define SQ_EDC_CNT__LDS_I_DED_COUNT_MASK 0x000000C0L 3095#define SQ_EDC_CNT__SGPR_SEC_COUNT_MASK 0x00000300L 3096#define SQ_EDC_CNT__SGPR_DED_COUNT_MASK 0x00000C00L 3097#define SQ_EDC_CNT__VGPR0_SEC_COUNT_MASK 0x00003000L 3098#define SQ_EDC_CNT__VGPR0_DED_COUNT_MASK 0x0000C000L 3099#define SQ_EDC_CNT__VGPR1_SEC_COUNT_MASK 0x00030000L 3100#define SQ_EDC_CNT__VGPR1_DED_COUNT_MASK 0x000C0000L 3101#define SQ_EDC_CNT__VGPR2_SEC_COUNT_MASK 0x00300000L 3102#define SQ_EDC_CNT__VGPR2_DED_COUNT_MASK 0x00C00000L 3103#define SQ_EDC_CNT__VGPR3_SEC_COUNT_MASK 0x03000000L 3104#define SQ_EDC_CNT__VGPR3_DED_COUNT_MASK 0x0C000000L 3105//SQ_EDC_FUE_CNTL 3106#define SQ_EDC_FUE_CNTL__BLOCK_FUE_FLAGS__SHIFT 0x0 3107#define SQ_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES__SHIFT 0x10 3108#define SQ_EDC_FUE_CNTL__BLOCK_FUE_FLAGS_MASK 0x0000FFFFL 3109#define SQ_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES_MASK 0xFFFF0000L 3110//SQ_THREAD_TRACE_WORD_CMN 3111#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE__SHIFT 0x0 3112#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA__SHIFT 0x4 3113#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE_MASK 0x000FL 3114#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA_MASK 0x0010L 3115//SQ_THREAD_TRACE_WORD_EVENT 3116#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE__SHIFT 0x0 3117#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA__SHIFT 0x4 3118#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID__SHIFT 0x5 3119#define SQ_THREAD_TRACE_WORD_EVENT__STAGE__SHIFT 0x6 3120#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE__SHIFT 0xa 3121#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE_MASK 0x000FL 3122#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA_MASK 0x0010L 3123#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID_MASK 0x0020L 3124#define SQ_THREAD_TRACE_WORD_EVENT__STAGE_MASK 0x01C0L 3125#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE_MASK 0xFC00L 3126//SQ_THREAD_TRACE_WORD_INST 3127#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE__SHIFT 0x0 3128#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA__SHIFT 0x4 3129#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID__SHIFT 0x5 3130#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID__SHIFT 0x9 3131#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE__SHIFT 0xb 3132#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE_MASK 0x000FL 3133#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA_MASK 0x0010L 3134#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID_MASK 0x01E0L 3135#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID_MASK 0x0600L 3136#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE_MASK 0xF800L 3137//SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2 3138#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE__SHIFT 0x0 3139#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA__SHIFT 0x4 3140#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID__SHIFT 0x5 3141#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID__SHIFT 0x9 3142#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TRAP_ERROR__SHIFT 0xf 3143#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO__SHIFT 0x10 3144#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL 3145#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA_MASK 0x00000010L 3146#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID_MASK 0x000001E0L 3147#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID_MASK 0x00000600L 3148#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TRAP_ERROR_MASK 0x00008000L 3149#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO_MASK 0xFFFF0000L 3150//SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2 3151#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE__SHIFT 0x0 3152#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA__SHIFT 0x4 3153#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID__SHIFT 0x5 3154#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID__SHIFT 0x6 3155#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID__SHIFT 0xa 3156#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID__SHIFT 0xe 3157#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO__SHIFT 0x10 3158#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL 3159#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA_MASK 0x00000010L 3160#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID_MASK 0x00000020L 3161#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID_MASK 0x000003C0L 3162#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID_MASK 0x00003C00L 3163#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID_MASK 0x0000C000L 3164#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO_MASK 0xFFFF0000L 3165//SQ_THREAD_TRACE_WORD_ISSUE 3166#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE__SHIFT 0x0 3167#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA__SHIFT 0x4 3168#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID__SHIFT 0x5 3169#define SQ_THREAD_TRACE_WORD_ISSUE__INST0__SHIFT 0x8 3170#define SQ_THREAD_TRACE_WORD_ISSUE__INST1__SHIFT 0xa 3171#define SQ_THREAD_TRACE_WORD_ISSUE__INST2__SHIFT 0xc 3172#define SQ_THREAD_TRACE_WORD_ISSUE__INST3__SHIFT 0xe 3173#define SQ_THREAD_TRACE_WORD_ISSUE__INST4__SHIFT 0x10 3174#define SQ_THREAD_TRACE_WORD_ISSUE__INST5__SHIFT 0x12 3175#define SQ_THREAD_TRACE_WORD_ISSUE__INST6__SHIFT 0x14 3176#define SQ_THREAD_TRACE_WORD_ISSUE__INST7__SHIFT 0x16 3177#define SQ_THREAD_TRACE_WORD_ISSUE__INST8__SHIFT 0x18 3178#define SQ_THREAD_TRACE_WORD_ISSUE__INST9__SHIFT 0x1a 3179#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE_MASK 0x0000000FL 3180#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA_MASK 0x00000010L 3181#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID_MASK 0x00000060L 3182#define SQ_THREAD_TRACE_WORD_ISSUE__INST0_MASK 0x00000300L 3183#define SQ_THREAD_TRACE_WORD_ISSUE__INST1_MASK 0x00000C00L 3184#define SQ_THREAD_TRACE_WORD_ISSUE__INST2_MASK 0x00003000L 3185#define SQ_THREAD_TRACE_WORD_ISSUE__INST3_MASK 0x0000C000L 3186#define SQ_THREAD_TRACE_WORD_ISSUE__INST4_MASK 0x00030000L 3187#define SQ_THREAD_TRACE_WORD_ISSUE__INST5_MASK 0x000C0000L 3188#define SQ_THREAD_TRACE_WORD_ISSUE__INST6_MASK 0x00300000L 3189#define SQ_THREAD_TRACE_WORD_ISSUE__INST7_MASK 0x00C00000L 3190#define SQ_THREAD_TRACE_WORD_ISSUE__INST8_MASK 0x03000000L 3191#define SQ_THREAD_TRACE_WORD_ISSUE__INST9_MASK 0x0C000000L 3192//SQ_THREAD_TRACE_WORD_MISC 3193#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE__SHIFT 0x0 3194#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA__SHIFT 0x4 3195#define SQ_THREAD_TRACE_WORD_MISC__SH_ID__SHIFT 0xc 3196#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE__SHIFT 0xd 3197#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE_MASK 0x000FL 3198#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA_MASK 0x0FF0L 3199#define SQ_THREAD_TRACE_WORD_MISC__SH_ID_MASK 0x1000L 3200#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE_MASK 0xE000L 3201//SQ_THREAD_TRACE_WORD_PERF_1_OF_2 3202#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE__SHIFT 0x0 3203#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA__SHIFT 0x4 3204#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID__SHIFT 0x5 3205#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID__SHIFT 0x6 3206#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK__SHIFT 0xa 3207#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0__SHIFT 0xc 3208#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO__SHIFT 0x19 3209#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL 3210#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA_MASK 0x00000010L 3211#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID_MASK 0x00000020L 3212#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID_MASK 0x000003C0L 3213#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK_MASK 0x00000C00L 3214#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0_MASK 0x01FFF000L 3215#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO_MASK 0xFE000000L 3216//SQ_THREAD_TRACE_WORD_REG_1_OF_2 3217#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE__SHIFT 0x0 3218#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA__SHIFT 0x4 3219#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID__SHIFT 0x5 3220#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID__SHIFT 0x7 3221#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV__SHIFT 0x9 3222#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE__SHIFT 0xa 3223#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV__SHIFT 0xe 3224#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP__SHIFT 0xf 3225#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR__SHIFT 0x10 3226#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL 3227#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA_MASK 0x00000010L 3228#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID_MASK 0x00000060L 3229#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID_MASK 0x00000180L 3230#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV_MASK 0x00000200L 3231#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE_MASK 0x00001C00L 3232#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV_MASK 0x00004000L 3233#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP_MASK 0x00008000L 3234#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR_MASK 0xFFFF0000L 3235//SQ_THREAD_TRACE_WORD_REG_2_OF_2 3236#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA__SHIFT 0x0 3237#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA_MASK 0xFFFFFFFFL 3238//SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2 3239#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE__SHIFT 0x0 3240#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA__SHIFT 0x4 3241#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID__SHIFT 0x5 3242#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID__SHIFT 0x7 3243#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR__SHIFT 0x9 3244#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO__SHIFT 0x10 3245#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL 3246#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA_MASK 0x00000010L 3247#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID_MASK 0x00000060L 3248#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID_MASK 0x00000180L 3249#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR_MASK 0x0000FE00L 3250#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO_MASK 0xFFFF0000L 3251//SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2 3252#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI__SHIFT 0x0 3253#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI_MASK 0x0000FFFFL 3254//SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2 3255#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE__SHIFT 0x0 3256#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO__SHIFT 0x10 3257#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL 3258#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO_MASK 0xFFFF0000L 3259//SQ_THREAD_TRACE_WORD_WAVE 3260#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE__SHIFT 0x0 3261#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA__SHIFT 0x4 3262#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID__SHIFT 0x5 3263#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID__SHIFT 0x6 3264#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID__SHIFT 0xa 3265#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID__SHIFT 0xe 3266#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE_MASK 0x000FL 3267#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA_MASK 0x0010L 3268#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID_MASK 0x0020L 3269#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID_MASK 0x03C0L 3270#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID_MASK 0x3C00L 3271#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID_MASK 0xC000L 3272//SQ_THREAD_TRACE_WORD_WAVE_START 3273#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE__SHIFT 0x0 3274#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA__SHIFT 0x4 3275#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID__SHIFT 0x5 3276#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID__SHIFT 0x6 3277#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID__SHIFT 0xa 3278#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID__SHIFT 0xe 3279#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER__SHIFT 0x10 3280#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED__SHIFT 0x15 3281#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT__SHIFT 0x16 3282#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID__SHIFT 0x1d 3283#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE_MASK 0x0000000FL 3284#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA_MASK 0x00000010L 3285#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID_MASK 0x00000020L 3286#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID_MASK 0x000003C0L 3287#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID_MASK 0x00003C00L 3288#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID_MASK 0x0000C000L 3289#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER_MASK 0x001F0000L 3290#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED_MASK 0x00200000L 3291#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT_MASK 0x1FC00000L 3292#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID_MASK 0xE0000000L 3293//SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2 3294#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI__SHIFT 0x0 3295#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI_MASK 0x00FFFFFFL 3296//SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2 3297#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI__SHIFT 0x0 3298#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI_MASK 0xFFFFL 3299//SQ_THREAD_TRACE_WORD_PERF_2_OF_2 3300#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI__SHIFT 0x0 3301#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2__SHIFT 0x6 3302#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3__SHIFT 0x13 3303#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI_MASK 0x0000003FL 3304#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2_MASK 0x0007FFC0L 3305#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3_MASK 0xFFF80000L 3306//SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2 3307#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI__SHIFT 0x0 3308#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI_MASK 0xFFFFFFFFL 3309//SQ_WREXEC_EXEC_HI 3310#define SQ_WREXEC_EXEC_HI__ADDR_HI__SHIFT 0x0 3311#define SQ_WREXEC_EXEC_HI__FIRST_WAVE__SHIFT 0x1a 3312#define SQ_WREXEC_EXEC_HI__ATC__SHIFT 0x1b 3313#define SQ_WREXEC_EXEC_HI__MTYPE__SHIFT 0x1c 3314#define SQ_WREXEC_EXEC_HI__MSB__SHIFT 0x1f 3315#define SQ_WREXEC_EXEC_HI__ADDR_HI_MASK 0x0000FFFFL 3316#define SQ_WREXEC_EXEC_HI__FIRST_WAVE_MASK 0x04000000L 3317#define SQ_WREXEC_EXEC_HI__ATC_MASK 0x08000000L 3318#define SQ_WREXEC_EXEC_HI__MTYPE_MASK 0x70000000L 3319#define SQ_WREXEC_EXEC_HI__MSB_MASK 0x80000000L 3320//SQ_WREXEC_EXEC_LO 3321#define SQ_WREXEC_EXEC_LO__ADDR_LO__SHIFT 0x0 3322#define SQ_WREXEC_EXEC_LO__ADDR_LO_MASK 0xFFFFFFFFL 3323//SQ_BUF_RSRC_WORD0 3324#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0 3325#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS_MASK 0xFFFFFFFFL 3326//SQ_BUF_RSRC_WORD1 3327#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0 3328#define SQ_BUF_RSRC_WORD1__STRIDE__SHIFT 0x10 3329#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE__SHIFT 0x1e 3330#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE__SHIFT 0x1f 3331#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0x0000FFFFL 3332#define SQ_BUF_RSRC_WORD1__STRIDE_MASK 0x3FFF0000L 3333#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE_MASK 0x40000000L 3334#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE_MASK 0x80000000L 3335//SQ_BUF_RSRC_WORD2 3336#define SQ_BUF_RSRC_WORD2__NUM_RECORDS__SHIFT 0x0 3337#define SQ_BUF_RSRC_WORD2__NUM_RECORDS_MASK 0xFFFFFFFFL 3338//SQ_BUF_RSRC_WORD3 3339#define SQ_BUF_RSRC_WORD3__DST_SEL_X__SHIFT 0x0 3340#define SQ_BUF_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3 3341#define SQ_BUF_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6 3342#define SQ_BUF_RSRC_WORD3__DST_SEL_W__SHIFT 0x9 3343#define SQ_BUF_RSRC_WORD3__NUM_FORMAT__SHIFT 0xc 3344#define SQ_BUF_RSRC_WORD3__DATA_FORMAT__SHIFT 0xf 3345#define SQ_BUF_RSRC_WORD3__USER_VM_ENABLE__SHIFT 0x13 3346#define SQ_BUF_RSRC_WORD3__USER_VM_MODE__SHIFT 0x14 3347#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE__SHIFT 0x15 3348#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE__SHIFT 0x17 3349#define SQ_BUF_RSRC_WORD3__NV__SHIFT 0x1b 3350#define SQ_BUF_RSRC_WORD3__TYPE__SHIFT 0x1e 3351#define SQ_BUF_RSRC_WORD3__DST_SEL_X_MASK 0x00000007L 3352#define SQ_BUF_RSRC_WORD3__DST_SEL_Y_MASK 0x00000038L 3353#define SQ_BUF_RSRC_WORD3__DST_SEL_Z_MASK 0x000001C0L 3354#define SQ_BUF_RSRC_WORD3__DST_SEL_W_MASK 0x00000E00L 3355#define SQ_BUF_RSRC_WORD3__NUM_FORMAT_MASK 0x00007000L 3356#define SQ_BUF_RSRC_WORD3__DATA_FORMAT_MASK 0x00078000L 3357#define SQ_BUF_RSRC_WORD3__USER_VM_ENABLE_MASK 0x00080000L 3358#define SQ_BUF_RSRC_WORD3__USER_VM_MODE_MASK 0x00100000L 3359#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE_MASK 0x00600000L 3360#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE_MASK 0x00800000L 3361#define SQ_BUF_RSRC_WORD3__NV_MASK 0x08000000L 3362#define SQ_BUF_RSRC_WORD3__TYPE_MASK 0xC0000000L 3363//SQ_IMG_RSRC_WORD0 3364#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0 3365#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS_MASK 0xFFFFFFFFL 3366//SQ_IMG_RSRC_WORD1 3367#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0 3368#define SQ_IMG_RSRC_WORD1__MIN_LOD__SHIFT 0x8 3369#define SQ_IMG_RSRC_WORD1__DATA_FORMAT__SHIFT 0x14 3370#define SQ_IMG_RSRC_WORD1__NUM_FORMAT__SHIFT 0x1a 3371#define SQ_IMG_RSRC_WORD1__NV__SHIFT 0x1e 3372#define SQ_IMG_RSRC_WORD1__META_DIRECT__SHIFT 0x1f 3373#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0x000000FFL 3374#define SQ_IMG_RSRC_WORD1__MIN_LOD_MASK 0x000FFF00L 3375#define SQ_IMG_RSRC_WORD1__DATA_FORMAT_MASK 0x03F00000L 3376#define SQ_IMG_RSRC_WORD1__NUM_FORMAT_MASK 0x3C000000L 3377#define SQ_IMG_RSRC_WORD1__NV_MASK 0x40000000L 3378#define SQ_IMG_RSRC_WORD1__META_DIRECT_MASK 0x80000000L 3379//SQ_IMG_RSRC_WORD2 3380#define SQ_IMG_RSRC_WORD2__WIDTH__SHIFT 0x0 3381#define SQ_IMG_RSRC_WORD2__HEIGHT__SHIFT 0xe 3382#define SQ_IMG_RSRC_WORD2__PERF_MOD__SHIFT 0x1c 3383#define SQ_IMG_RSRC_WORD2__WIDTH_MASK 0x00003FFFL 3384#define SQ_IMG_RSRC_WORD2__HEIGHT_MASK 0x0FFFC000L 3385#define SQ_IMG_RSRC_WORD2__PERF_MOD_MASK 0x70000000L 3386//SQ_IMG_RSRC_WORD3 3387#define SQ_IMG_RSRC_WORD3__DST_SEL_X__SHIFT 0x0 3388#define SQ_IMG_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3 3389#define SQ_IMG_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6 3390#define SQ_IMG_RSRC_WORD3__DST_SEL_W__SHIFT 0x9 3391#define SQ_IMG_RSRC_WORD3__BASE_LEVEL__SHIFT 0xc 3392#define SQ_IMG_RSRC_WORD3__LAST_LEVEL__SHIFT 0x10 3393#define SQ_IMG_RSRC_WORD3__SW_MODE__SHIFT 0x14 3394#define SQ_IMG_RSRC_WORD3__TYPE__SHIFT 0x1c 3395#define SQ_IMG_RSRC_WORD3__DST_SEL_X_MASK 0x00000007L 3396#define SQ_IMG_RSRC_WORD3__DST_SEL_Y_MASK 0x00000038L 3397#define SQ_IMG_RSRC_WORD3__DST_SEL_Z_MASK 0x000001C0L 3398#define SQ_IMG_RSRC_WORD3__DST_SEL_W_MASK 0x00000E00L 3399#define SQ_IMG_RSRC_WORD3__BASE_LEVEL_MASK 0x0000F000L 3400#define SQ_IMG_RSRC_WORD3__LAST_LEVEL_MASK 0x000F0000L 3401#define SQ_IMG_RSRC_WORD3__SW_MODE_MASK 0x01F00000L 3402#define SQ_IMG_RSRC_WORD3__TYPE_MASK 0xF0000000L 3403//SQ_IMG_RSRC_WORD4 3404#define SQ_IMG_RSRC_WORD4__DEPTH__SHIFT 0x0 3405#define SQ_IMG_RSRC_WORD4__PITCH__SHIFT 0xd 3406#define SQ_IMG_RSRC_WORD4__BC_SWIZZLE__SHIFT 0x1d 3407#define SQ_IMG_RSRC_WORD4__DEPTH_MASK 0x00001FFFL 3408#define SQ_IMG_RSRC_WORD4__PITCH_MASK 0x1FFFE000L 3409#define SQ_IMG_RSRC_WORD4__BC_SWIZZLE_MASK 0xE0000000L 3410//SQ_IMG_RSRC_WORD5 3411#define SQ_IMG_RSRC_WORD5__BASE_ARRAY__SHIFT 0x0 3412#define SQ_IMG_RSRC_WORD5__ARRAY_PITCH__SHIFT 0xd 3413#define SQ_IMG_RSRC_WORD5__META_DATA_ADDRESS__SHIFT 0x11 3414#define SQ_IMG_RSRC_WORD5__META_LINEAR__SHIFT 0x19 3415#define SQ_IMG_RSRC_WORD5__META_PIPE_ALIGNED__SHIFT 0x1a 3416#define SQ_IMG_RSRC_WORD5__META_RB_ALIGNED__SHIFT 0x1b 3417#define SQ_IMG_RSRC_WORD5__MAX_MIP__SHIFT 0x1c 3418#define SQ_IMG_RSRC_WORD5__BASE_ARRAY_MASK 0x00001FFFL 3419#define SQ_IMG_RSRC_WORD5__ARRAY_PITCH_MASK 0x0001E000L 3420#define SQ_IMG_RSRC_WORD5__META_DATA_ADDRESS_MASK 0x01FE0000L 3421#define SQ_IMG_RSRC_WORD5__META_LINEAR_MASK 0x02000000L 3422#define SQ_IMG_RSRC_WORD5__META_PIPE_ALIGNED_MASK 0x04000000L 3423#define SQ_IMG_RSRC_WORD5__META_RB_ALIGNED_MASK 0x08000000L 3424#define SQ_IMG_RSRC_WORD5__MAX_MIP_MASK 0xF0000000L 3425//SQ_IMG_RSRC_WORD6 3426#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN__SHIFT 0x0 3427#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID__SHIFT 0xc 3428#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN__SHIFT 0x14 3429#define SQ_IMG_RSRC_WORD6__COMPRESSION_EN__SHIFT 0x15 3430#define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB__SHIFT 0x16 3431#define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM__SHIFT 0x17 3432#define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS__SHIFT 0x18 3433#define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS__SHIFT 0x1c 3434#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN_MASK 0x00000FFFL 3435#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID_MASK 0x000FF000L 3436#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN_MASK 0x00100000L 3437#define SQ_IMG_RSRC_WORD6__COMPRESSION_EN_MASK 0x00200000L 3438#define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB_MASK 0x00400000L 3439#define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM_MASK 0x00800000L 3440#define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS_MASK 0x0F000000L 3441#define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS_MASK 0xF0000000L 3442//SQ_IMG_RSRC_WORD7 3443#define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS__SHIFT 0x0 3444#define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS_MASK 0xFFFFFFFFL 3445//SQ_IMG_SAMP_WORD0 3446#define SQ_IMG_SAMP_WORD0__CLAMP_X__SHIFT 0x0 3447#define SQ_IMG_SAMP_WORD0__CLAMP_Y__SHIFT 0x3 3448#define SQ_IMG_SAMP_WORD0__CLAMP_Z__SHIFT 0x6 3449#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO__SHIFT 0x9 3450#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC__SHIFT 0xc 3451#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED__SHIFT 0xf 3452#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD__SHIFT 0x10 3453#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC__SHIFT 0x13 3454#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA__SHIFT 0x14 3455#define SQ_IMG_SAMP_WORD0__ANISO_BIAS__SHIFT 0x15 3456#define SQ_IMG_SAMP_WORD0__TRUNC_COORD__SHIFT 0x1b 3457#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP__SHIFT 0x1c 3458#define SQ_IMG_SAMP_WORD0__FILTER_MODE__SHIFT 0x1d 3459#define SQ_IMG_SAMP_WORD0__COMPAT_MODE__SHIFT 0x1f 3460#define SQ_IMG_SAMP_WORD0__CLAMP_X_MASK 0x00000007L 3461#define SQ_IMG_SAMP_WORD0__CLAMP_Y_MASK 0x00000038L 3462#define SQ_IMG_SAMP_WORD0__CLAMP_Z_MASK 0x000001C0L 3463#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO_MASK 0x00000E00L 3464#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC_MASK 0x00007000L 3465#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED_MASK 0x00008000L 3466#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD_MASK 0x00070000L 3467#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC_MASK 0x00080000L 3468#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA_MASK 0x00100000L 3469#define SQ_IMG_SAMP_WORD0__ANISO_BIAS_MASK 0x07E00000L 3470#define SQ_IMG_SAMP_WORD0__TRUNC_COORD_MASK 0x08000000L 3471#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP_MASK 0x10000000L 3472#define SQ_IMG_SAMP_WORD0__FILTER_MODE_MASK 0x60000000L 3473#define SQ_IMG_SAMP_WORD0__COMPAT_MODE_MASK 0x80000000L 3474//SQ_IMG_SAMP_WORD1 3475#define SQ_IMG_SAMP_WORD1__MIN_LOD__SHIFT 0x0 3476#define SQ_IMG_SAMP_WORD1__MAX_LOD__SHIFT 0xc 3477#define SQ_IMG_SAMP_WORD1__PERF_MIP__SHIFT 0x18 3478#define SQ_IMG_SAMP_WORD1__PERF_Z__SHIFT 0x1c 3479#define SQ_IMG_SAMP_WORD1__MIN_LOD_MASK 0x00000FFFL 3480#define SQ_IMG_SAMP_WORD1__MAX_LOD_MASK 0x00FFF000L 3481#define SQ_IMG_SAMP_WORD1__PERF_MIP_MASK 0x0F000000L 3482#define SQ_IMG_SAMP_WORD1__PERF_Z_MASK 0xF0000000L 3483//SQ_IMG_SAMP_WORD2 3484#define SQ_IMG_SAMP_WORD2__LOD_BIAS__SHIFT 0x0 3485#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC__SHIFT 0xe 3486#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER__SHIFT 0x14 3487#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER__SHIFT 0x16 3488#define SQ_IMG_SAMP_WORD2__Z_FILTER__SHIFT 0x18 3489#define SQ_IMG_SAMP_WORD2__MIP_FILTER__SHIFT 0x1a 3490#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP__SHIFT 0x1c 3491#define SQ_IMG_SAMP_WORD2__BLEND_ZERO_PRT__SHIFT 0x1d 3492#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX__SHIFT 0x1e 3493#define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE__SHIFT 0x1f 3494#define SQ_IMG_SAMP_WORD2__LOD_BIAS_MASK 0x00003FFFL 3495#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC_MASK 0x000FC000L 3496#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER_MASK 0x00300000L 3497#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER_MASK 0x00C00000L 3498#define SQ_IMG_SAMP_WORD2__Z_FILTER_MASK 0x03000000L 3499#define SQ_IMG_SAMP_WORD2__MIP_FILTER_MASK 0x0C000000L 3500#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP_MASK 0x10000000L 3501#define SQ_IMG_SAMP_WORD2__BLEND_ZERO_PRT_MASK 0x20000000L 3502#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX_MASK 0x40000000L 3503#define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE_MASK 0x80000000L 3504//SQ_IMG_SAMP_WORD3 3505#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR__SHIFT 0x0 3506#define SQ_IMG_SAMP_WORD3__SKIP_DEGAMMA__SHIFT 0xc 3507#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE__SHIFT 0x1e 3508#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR_MASK 0x00000FFFL 3509#define SQ_IMG_SAMP_WORD3__SKIP_DEGAMMA_MASK 0x00001000L 3510#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE_MASK 0xC0000000L 3511//SQ_FLAT_SCRATCH_WORD0 3512#define SQ_FLAT_SCRATCH_WORD0__SIZE__SHIFT 0x0 3513#define SQ_FLAT_SCRATCH_WORD0__SIZE_MASK 0x0007FFFFL 3514//SQ_FLAT_SCRATCH_WORD1 3515#define SQ_FLAT_SCRATCH_WORD1__OFFSET__SHIFT 0x0 3516#define SQ_FLAT_SCRATCH_WORD1__OFFSET_MASK 0x00FFFFFFL 3517//SQ_M0_GPR_IDX_WORD 3518#define SQ_M0_GPR_IDX_WORD__INDEX__SHIFT 0x0 3519#define SQ_M0_GPR_IDX_WORD__VSRC0_REL__SHIFT 0xc 3520#define SQ_M0_GPR_IDX_WORD__VSRC1_REL__SHIFT 0xd 3521#define SQ_M0_GPR_IDX_WORD__VSRC2_REL__SHIFT 0xe 3522#define SQ_M0_GPR_IDX_WORD__VDST_REL__SHIFT 0xf 3523#define SQ_M0_GPR_IDX_WORD__INDEX_MASK 0x000000FFL 3524#define SQ_M0_GPR_IDX_WORD__VSRC0_REL_MASK 0x00001000L 3525#define SQ_M0_GPR_IDX_WORD__VSRC1_REL_MASK 0x00002000L 3526#define SQ_M0_GPR_IDX_WORD__VSRC2_REL_MASK 0x00004000L 3527#define SQ_M0_GPR_IDX_WORD__VDST_REL_MASK 0x00008000L 3528//SQC_ICACHE_UTCL1_CNTL1 3529#define SQC_ICACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 3530#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1 3531#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 3532#define SQC_ICACHE_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3 3533#define SQC_ICACHE_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 3534#define SQC_ICACHE_UTCL1_CNTL1__CLIENTID__SHIFT 0x7 3535#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11 3536#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12 3537#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT 0x13 3538#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT 0x17 3539#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT 0x18 3540#define SQC_ICACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19 3541#define SQC_ICACHE_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a 3542#define SQC_ICACHE_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b 3543#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c 3544#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e 3545#define SQC_ICACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L 3546#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L 3547#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L 3548#define SQC_ICACHE_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L 3549#define SQC_ICACHE_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L 3550#define SQC_ICACHE_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L 3551#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L 3552#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L 3553#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK 0x00780000L 3554#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK 0x00800000L 3555#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK 0x01000000L 3556#define SQC_ICACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L 3557#define SQC_ICACHE_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L 3558#define SQC_ICACHE_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L 3559#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L 3560#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L 3561//SQC_ICACHE_UTCL1_CNTL2 3562#define SQC_ICACHE_UTCL1_CNTL2__SPARE__SHIFT 0x0 3563#define SQC_ICACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8 3564#define SQC_ICACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 3565#define SQC_ICACHE_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa 3566#define SQC_ICACHE_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb 3567#define SQC_ICACHE_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc 3568#define SQC_ICACHE_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd 3569#define SQC_ICACHE_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe 3570#define SQC_ICACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf 3571#define SQC_ICACHE_UTCL1_CNTL2__ARB_BURST_MODE__SHIFT 0x10 3572#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12 3573#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13 3574#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14 3575#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT 0x15 3576#define SQC_ICACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a 3577#define SQC_ICACHE_UTCL1_CNTL2__SPARE_MASK 0x000000FFL 3578#define SQC_ICACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L 3579#define SQC_ICACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L 3580#define SQC_ICACHE_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L 3581#define SQC_ICACHE_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L 3582#define SQC_ICACHE_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L 3583#define SQC_ICACHE_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L 3584#define SQC_ICACHE_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L 3585#define SQC_ICACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L 3586#define SQC_ICACHE_UTCL1_CNTL2__ARB_BURST_MODE_MASK 0x00030000L 3587#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L 3588#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L 3589#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L 3590#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L 3591#define SQC_ICACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L 3592//SQC_DCACHE_UTCL1_CNTL1 3593#define SQC_DCACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 3594#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1 3595#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 3596#define SQC_DCACHE_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3 3597#define SQC_DCACHE_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 3598#define SQC_DCACHE_UTCL1_CNTL1__CLIENTID__SHIFT 0x7 3599#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11 3600#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12 3601#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT 0x13 3602#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT 0x17 3603#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT 0x18 3604#define SQC_DCACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19 3605#define SQC_DCACHE_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a 3606#define SQC_DCACHE_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b 3607#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c 3608#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e 3609#define SQC_DCACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L 3610#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L 3611#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L 3612#define SQC_DCACHE_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L 3613#define SQC_DCACHE_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L 3614#define SQC_DCACHE_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L 3615#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L 3616#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L 3617#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK 0x00780000L 3618#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK 0x00800000L 3619#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK 0x01000000L 3620#define SQC_DCACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L 3621#define SQC_DCACHE_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L 3622#define SQC_DCACHE_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L 3623#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L 3624#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L 3625//SQC_DCACHE_UTCL1_CNTL2 3626#define SQC_DCACHE_UTCL1_CNTL2__SPARE__SHIFT 0x0 3627#define SQC_DCACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8 3628#define SQC_DCACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 3629#define SQC_DCACHE_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa 3630#define SQC_DCACHE_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb 3631#define SQC_DCACHE_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc 3632#define SQC_DCACHE_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd 3633#define SQC_DCACHE_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe 3634#define SQC_DCACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf 3635#define SQC_DCACHE_UTCL1_CNTL2__ARB_BURST_MODE__SHIFT 0x10 3636#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12 3637#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13 3638#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14 3639#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT 0x15 3640#define SQC_DCACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a 3641#define SQC_DCACHE_UTCL1_CNTL2__SPARE_MASK 0x000000FFL 3642#define SQC_DCACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L 3643#define SQC_DCACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L 3644#define SQC_DCACHE_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L 3645#define SQC_DCACHE_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L 3646#define SQC_DCACHE_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L 3647#define SQC_DCACHE_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L 3648#define SQC_DCACHE_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L 3649#define SQC_DCACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L 3650#define SQC_DCACHE_UTCL1_CNTL2__ARB_BURST_MODE_MASK 0x00030000L 3651#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L 3652#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L 3653#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L 3654#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L 3655#define SQC_DCACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L 3656//SQC_ICACHE_UTCL1_STATUS 3657#define SQC_ICACHE_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 3658#define SQC_ICACHE_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 3659#define SQC_ICACHE_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 3660#define SQC_ICACHE_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L 3661#define SQC_ICACHE_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L 3662#define SQC_ICACHE_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L 3663//SQC_DCACHE_UTCL1_STATUS 3664#define SQC_DCACHE_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 3665#define SQC_DCACHE_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 3666#define SQC_DCACHE_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 3667#define SQC_DCACHE_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L 3668#define SQC_DCACHE_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L 3669#define SQC_DCACHE_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L 3670 3671 3672// addressBlock: gc_shsdec 3673//SX_DEBUG_1 3674#define SX_DEBUG_1__SX_DB_QUAD_CREDIT__SHIFT 0x0 3675#define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x8 3676#define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x9 3677#define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0xa 3678#define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT__SHIFT 0xb 3679#define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT__SHIFT 0xc 3680#define SX_DEBUG_1__PC_CFG__SHIFT 0xd 3681#define SX_DEBUG_1__DEBUG_DATA__SHIFT 0xe 3682#define SX_DEBUG_1__SX_DB_QUAD_CREDIT_MASK 0x0000007FL 3683#define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x00000100L 3684#define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS_MASK 0x00000200L 3685#define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x00000400L 3686#define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT_MASK 0x00000800L 3687#define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT_MASK 0x00001000L 3688#define SX_DEBUG_1__PC_CFG_MASK 0x00002000L 3689#define SX_DEBUG_1__DEBUG_DATA_MASK 0xFFFFC000L 3690//SPI_PS_MAX_WAVE_ID 3691#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 3692#define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID__SHIFT 0x10 3693#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL 3694#define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID_MASK 0x03FF0000L 3695//SPI_START_PHASE 3696#define SPI_START_PHASE__VGPR_START_PHASE__SHIFT 0x0 3697#define SPI_START_PHASE__SGPR_START_PHASE__SHIFT 0x2 3698#define SPI_START_PHASE__WAVE_START_PHASE__SHIFT 0x4 3699#define SPI_START_PHASE__VGPR_START_PHASE_MASK 0x00000003L 3700#define SPI_START_PHASE__SGPR_START_PHASE_MASK 0x0000000CL 3701#define SPI_START_PHASE__WAVE_START_PHASE_MASK 0x00000030L 3702//SPI_GFX_CNTL 3703#define SPI_GFX_CNTL__RESET_COUNTS__SHIFT 0x0 3704#define SPI_GFX_CNTL__RESET_COUNTS_MASK 0x00000001L 3705//SPI_DSM_CNTL 3706#define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA__SHIFT 0x0 3707#define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 3708#define SPI_DSM_CNTL__UNUSED__SHIFT 0x3 3709#define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA_MASK 0x00000003L 3710#define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L 3711#define SPI_DSM_CNTL__UNUSED_MASK 0xFFFFFFF8L 3712//SPI_DSM_CNTL2 3713#define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT__SHIFT 0x0 3714#define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY__SHIFT 0x2 3715#define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY__SHIFT 0x4 3716#define SPI_DSM_CNTL2__UNUSED__SHIFT 0xa 3717#define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT_MASK 0x00000003L 3718#define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY_MASK 0x00000004L 3719#define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY_MASK 0x000003F0L 3720#define SPI_DSM_CNTL2__UNUSED_MASK 0xFFFFFC00L 3721//SPI_EDC_CNT 3722#define SPI_EDC_CNT__SPI_SR_MEM_SED_COUNT__SHIFT 0x0 3723#define SPI_EDC_CNT__SPI_SR_MEM_SED_COUNT_MASK 0x00000003L 3724//SPI_CONFIG_PS_CU_EN 3725#define SPI_CONFIG_PS_CU_EN__ENABLE__SHIFT 0x0 3726#define SPI_CONFIG_PS_CU_EN__PKR0_CU_EN__SHIFT 0x1 3727#define SPI_CONFIG_PS_CU_EN__PKR1_CU_EN__SHIFT 0x10 3728#define SPI_CONFIG_PS_CU_EN__ENABLE_MASK 0x00000001L 3729#define SPI_CONFIG_PS_CU_EN__PKR0_CU_EN_MASK 0x0000FFFEL 3730#define SPI_CONFIG_PS_CU_EN__PKR1_CU_EN_MASK 0xFFFF0000L 3731//SPI_WF_LIFETIME_CNTL 3732#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD__SHIFT 0x0 3733#define SPI_WF_LIFETIME_CNTL__EN__SHIFT 0x4 3734#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD_MASK 0x0000000FL 3735#define SPI_WF_LIFETIME_CNTL__EN_MASK 0x00000010L 3736//SPI_WF_LIFETIME_LIMIT_0 3737#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT__SHIFT 0x0 3738#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN__SHIFT 0x1f 3739#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT_MASK 0x7FFFFFFFL 3740#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN_MASK 0x80000000L 3741//SPI_WF_LIFETIME_LIMIT_1 3742#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT__SHIFT 0x0 3743#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN__SHIFT 0x1f 3744#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT_MASK 0x7FFFFFFFL 3745#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN_MASK 0x80000000L 3746//SPI_WF_LIFETIME_LIMIT_2 3747#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT__SHIFT 0x0 3748#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN__SHIFT 0x1f 3749#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT_MASK 0x7FFFFFFFL 3750#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN_MASK 0x80000000L 3751//SPI_WF_LIFETIME_LIMIT_3 3752#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT__SHIFT 0x0 3753#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN__SHIFT 0x1f 3754#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT_MASK 0x7FFFFFFFL 3755#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN_MASK 0x80000000L 3756//SPI_WF_LIFETIME_LIMIT_4 3757#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT__SHIFT 0x0 3758#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN__SHIFT 0x1f 3759#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT_MASK 0x7FFFFFFFL 3760#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN_MASK 0x80000000L 3761//SPI_WF_LIFETIME_LIMIT_5 3762#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT__SHIFT 0x0 3763#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN__SHIFT 0x1f 3764#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT_MASK 0x7FFFFFFFL 3765#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN_MASK 0x80000000L 3766//SPI_WF_LIFETIME_LIMIT_6 3767#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT__SHIFT 0x0 3768#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN__SHIFT 0x1f 3769#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT_MASK 0x7FFFFFFFL 3770#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN_MASK 0x80000000L 3771//SPI_WF_LIFETIME_LIMIT_7 3772#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT__SHIFT 0x0 3773#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN__SHIFT 0x1f 3774#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT_MASK 0x7FFFFFFFL 3775#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN_MASK 0x80000000L 3776//SPI_WF_LIFETIME_LIMIT_8 3777#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT__SHIFT 0x0 3778#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN__SHIFT 0x1f 3779#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT_MASK 0x7FFFFFFFL 3780#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN_MASK 0x80000000L 3781//SPI_WF_LIFETIME_LIMIT_9 3782#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT__SHIFT 0x0 3783#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN__SHIFT 0x1f 3784#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT_MASK 0x7FFFFFFFL 3785#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN_MASK 0x80000000L 3786//SPI_WF_LIFETIME_STATUS_0 3787#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT__SHIFT 0x0 3788#define SPI_WF_LIFETIME_STATUS_0__INT_SENT__SHIFT 0x1f 3789#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT_MASK 0x7FFFFFFFL 3790#define SPI_WF_LIFETIME_STATUS_0__INT_SENT_MASK 0x80000000L 3791//SPI_WF_LIFETIME_STATUS_1 3792#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT__SHIFT 0x0 3793#define SPI_WF_LIFETIME_STATUS_1__INT_SENT__SHIFT 0x1f 3794#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT_MASK 0x7FFFFFFFL 3795#define SPI_WF_LIFETIME_STATUS_1__INT_SENT_MASK 0x80000000L 3796//SPI_WF_LIFETIME_STATUS_2 3797#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT__SHIFT 0x0 3798#define SPI_WF_LIFETIME_STATUS_2__INT_SENT__SHIFT 0x1f 3799#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT_MASK 0x7FFFFFFFL 3800#define SPI_WF_LIFETIME_STATUS_2__INT_SENT_MASK 0x80000000L 3801//SPI_WF_LIFETIME_STATUS_3 3802#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT__SHIFT 0x0 3803#define SPI_WF_LIFETIME_STATUS_3__INT_SENT__SHIFT 0x1f 3804#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT_MASK 0x7FFFFFFFL 3805#define SPI_WF_LIFETIME_STATUS_3__INT_SENT_MASK 0x80000000L 3806//SPI_WF_LIFETIME_STATUS_4 3807#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT__SHIFT 0x0 3808#define SPI_WF_LIFETIME_STATUS_4__INT_SENT__SHIFT 0x1f 3809#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT_MASK 0x7FFFFFFFL 3810#define SPI_WF_LIFETIME_STATUS_4__INT_SENT_MASK 0x80000000L 3811//SPI_WF_LIFETIME_STATUS_5 3812#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT__SHIFT 0x0 3813#define SPI_WF_LIFETIME_STATUS_5__INT_SENT__SHIFT 0x1f 3814#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT_MASK 0x7FFFFFFFL 3815#define SPI_WF_LIFETIME_STATUS_5__INT_SENT_MASK 0x80000000L 3816//SPI_WF_LIFETIME_STATUS_6 3817#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT__SHIFT 0x0 3818#define SPI_WF_LIFETIME_STATUS_6__INT_SENT__SHIFT 0x1f 3819#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT_MASK 0x7FFFFFFFL 3820#define SPI_WF_LIFETIME_STATUS_6__INT_SENT_MASK 0x80000000L 3821//SPI_WF_LIFETIME_STATUS_7 3822#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT__SHIFT 0x0 3823#define SPI_WF_LIFETIME_STATUS_7__INT_SENT__SHIFT 0x1f 3824#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT_MASK 0x7FFFFFFFL 3825#define SPI_WF_LIFETIME_STATUS_7__INT_SENT_MASK 0x80000000L 3826//SPI_WF_LIFETIME_STATUS_8 3827#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT__SHIFT 0x0 3828#define SPI_WF_LIFETIME_STATUS_8__INT_SENT__SHIFT 0x1f 3829#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT_MASK 0x7FFFFFFFL 3830#define SPI_WF_LIFETIME_STATUS_8__INT_SENT_MASK 0x80000000L 3831//SPI_WF_LIFETIME_STATUS_9 3832#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT__SHIFT 0x0 3833#define SPI_WF_LIFETIME_STATUS_9__INT_SENT__SHIFT 0x1f 3834#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT_MASK 0x7FFFFFFFL 3835#define SPI_WF_LIFETIME_STATUS_9__INT_SENT_MASK 0x80000000L 3836//SPI_WF_LIFETIME_STATUS_10 3837#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT__SHIFT 0x0 3838#define SPI_WF_LIFETIME_STATUS_10__INT_SENT__SHIFT 0x1f 3839#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT_MASK 0x7FFFFFFFL 3840#define SPI_WF_LIFETIME_STATUS_10__INT_SENT_MASK 0x80000000L 3841//SPI_WF_LIFETIME_STATUS_11 3842#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT__SHIFT 0x0 3843#define SPI_WF_LIFETIME_STATUS_11__INT_SENT__SHIFT 0x1f 3844#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT_MASK 0x7FFFFFFFL 3845#define SPI_WF_LIFETIME_STATUS_11__INT_SENT_MASK 0x80000000L 3846//SPI_WF_LIFETIME_STATUS_12 3847#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT__SHIFT 0x0 3848#define SPI_WF_LIFETIME_STATUS_12__INT_SENT__SHIFT 0x1f 3849#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT_MASK 0x7FFFFFFFL 3850#define SPI_WF_LIFETIME_STATUS_12__INT_SENT_MASK 0x80000000L 3851//SPI_WF_LIFETIME_STATUS_13 3852#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT__SHIFT 0x0 3853#define SPI_WF_LIFETIME_STATUS_13__INT_SENT__SHIFT 0x1f 3854#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT_MASK 0x7FFFFFFFL 3855#define SPI_WF_LIFETIME_STATUS_13__INT_SENT_MASK 0x80000000L 3856//SPI_WF_LIFETIME_STATUS_14 3857#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT__SHIFT 0x0 3858#define SPI_WF_LIFETIME_STATUS_14__INT_SENT__SHIFT 0x1f 3859#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT_MASK 0x7FFFFFFFL 3860#define SPI_WF_LIFETIME_STATUS_14__INT_SENT_MASK 0x80000000L 3861//SPI_WF_LIFETIME_STATUS_15 3862#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT__SHIFT 0x0 3863#define SPI_WF_LIFETIME_STATUS_15__INT_SENT__SHIFT 0x1f 3864#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT_MASK 0x7FFFFFFFL 3865#define SPI_WF_LIFETIME_STATUS_15__INT_SENT_MASK 0x80000000L 3866//SPI_WF_LIFETIME_STATUS_16 3867#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT__SHIFT 0x0 3868#define SPI_WF_LIFETIME_STATUS_16__INT_SENT__SHIFT 0x1f 3869#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT_MASK 0x7FFFFFFFL 3870#define SPI_WF_LIFETIME_STATUS_16__INT_SENT_MASK 0x80000000L 3871//SPI_WF_LIFETIME_STATUS_17 3872#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT__SHIFT 0x0 3873#define SPI_WF_LIFETIME_STATUS_17__INT_SENT__SHIFT 0x1f 3874#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT_MASK 0x7FFFFFFFL 3875#define SPI_WF_LIFETIME_STATUS_17__INT_SENT_MASK 0x80000000L 3876//SPI_WF_LIFETIME_STATUS_18 3877#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT__SHIFT 0x0 3878#define SPI_WF_LIFETIME_STATUS_18__INT_SENT__SHIFT 0x1f 3879#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT_MASK 0x7FFFFFFFL 3880#define SPI_WF_LIFETIME_STATUS_18__INT_SENT_MASK 0x80000000L 3881//SPI_WF_LIFETIME_STATUS_19 3882#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT__SHIFT 0x0 3883#define SPI_WF_LIFETIME_STATUS_19__INT_SENT__SHIFT 0x1f 3884#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT_MASK 0x7FFFFFFFL 3885#define SPI_WF_LIFETIME_STATUS_19__INT_SENT_MASK 0x80000000L 3886//SPI_WF_LIFETIME_STATUS_20 3887#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT__SHIFT 0x0 3888#define SPI_WF_LIFETIME_STATUS_20__INT_SENT__SHIFT 0x1f 3889#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT_MASK 0x7FFFFFFFL 3890#define SPI_WF_LIFETIME_STATUS_20__INT_SENT_MASK 0x80000000L 3891//SPI_LB_CTR_CTRL 3892#define SPI_LB_CTR_CTRL__LOAD__SHIFT 0x0 3893#define SPI_LB_CTR_CTRL__WAVES_SELECT__SHIFT 0x1 3894#define SPI_LB_CTR_CTRL__CLEAR_ON_READ__SHIFT 0x3 3895#define SPI_LB_CTR_CTRL__RESET_COUNTS__SHIFT 0x4 3896#define SPI_LB_CTR_CTRL__LOAD_MASK 0x00000001L 3897#define SPI_LB_CTR_CTRL__WAVES_SELECT_MASK 0x00000006L 3898#define SPI_LB_CTR_CTRL__CLEAR_ON_READ_MASK 0x00000008L 3899#define SPI_LB_CTR_CTRL__RESET_COUNTS_MASK 0x00000010L 3900//SPI_LB_CU_MASK 3901#define SPI_LB_CU_MASK__CU_MASK__SHIFT 0x0 3902#define SPI_LB_CU_MASK__CU_MASK_MASK 0xFFFFL 3903//SPI_LB_DATA_REG 3904#define SPI_LB_DATA_REG__CNT_DATA__SHIFT 0x0 3905#define SPI_LB_DATA_REG__CNT_DATA_MASK 0xFFFFFFFFL 3906//SPI_PG_ENABLE_STATIC_CU_MASK 3907#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK__SHIFT 0x0 3908#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK_MASK 0xFFFFL 3909//SPI_GDS_CREDITS 3910#define SPI_GDS_CREDITS__DS_DATA_CREDITS__SHIFT 0x0 3911#define SPI_GDS_CREDITS__DS_CMD_CREDITS__SHIFT 0x8 3912#define SPI_GDS_CREDITS__UNUSED__SHIFT 0x10 3913#define SPI_GDS_CREDITS__DS_DATA_CREDITS_MASK 0x000000FFL 3914#define SPI_GDS_CREDITS__DS_CMD_CREDITS_MASK 0x0000FF00L 3915#define SPI_GDS_CREDITS__UNUSED_MASK 0xFFFF0000L 3916//SPI_SX_EXPORT_BUFFER_SIZES 3917#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE__SHIFT 0x0 3918#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE__SHIFT 0x10 3919#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE_MASK 0x0000FFFFL 3920#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE_MASK 0xFFFF0000L 3921//SPI_SX_SCOREBOARD_BUFFER_SIZES 3922#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE__SHIFT 0x0 3923#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE__SHIFT 0x10 3924#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE_MASK 0x0000FFFFL 3925#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE_MASK 0xFFFF0000L 3926//SPI_CSQ_WF_ACTIVE_STATUS 3927#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE__SHIFT 0x0 3928#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE_MASK 0xFFFFFFFFL 3929//SPI_CSQ_WF_ACTIVE_COUNT_0 3930#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT__SHIFT 0x0 3931#define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS__SHIFT 0x10 3932#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x000007FFL 3933#define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS_MASK 0x07FF0000L 3934//SPI_CSQ_WF_ACTIVE_COUNT_1 3935#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT__SHIFT 0x0 3936#define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS__SHIFT 0x10 3937#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK 0x000007FFL 3938#define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS_MASK 0x07FF0000L 3939//SPI_CSQ_WF_ACTIVE_COUNT_2 3940#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT__SHIFT 0x0 3941#define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS__SHIFT 0x10 3942#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT_MASK 0x000007FFL 3943#define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS_MASK 0x07FF0000L 3944//SPI_CSQ_WF_ACTIVE_COUNT_3 3945#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT__SHIFT 0x0 3946#define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS__SHIFT 0x10 3947#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT_MASK 0x000007FFL 3948#define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS_MASK 0x07FF0000L 3949//SPI_CSQ_WF_ACTIVE_COUNT_4 3950#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT__SHIFT 0x0 3951#define SPI_CSQ_WF_ACTIVE_COUNT_4__EVENTS__SHIFT 0x10 3952#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT_MASK 0x000007FFL 3953#define SPI_CSQ_WF_ACTIVE_COUNT_4__EVENTS_MASK 0x07FF0000L 3954//SPI_CSQ_WF_ACTIVE_COUNT_5 3955#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT__SHIFT 0x0 3956#define SPI_CSQ_WF_ACTIVE_COUNT_5__EVENTS__SHIFT 0x10 3957#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT_MASK 0x000007FFL 3958#define SPI_CSQ_WF_ACTIVE_COUNT_5__EVENTS_MASK 0x07FF0000L 3959//SPI_CSQ_WF_ACTIVE_COUNT_6 3960#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT__SHIFT 0x0 3961#define SPI_CSQ_WF_ACTIVE_COUNT_6__EVENTS__SHIFT 0x10 3962#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT_MASK 0x000007FFL 3963#define SPI_CSQ_WF_ACTIVE_COUNT_6__EVENTS_MASK 0x07FF0000L 3964//SPI_CSQ_WF_ACTIVE_COUNT_7 3965#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT__SHIFT 0x0 3966#define SPI_CSQ_WF_ACTIVE_COUNT_7__EVENTS__SHIFT 0x10 3967#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT_MASK 0x000007FFL 3968#define SPI_CSQ_WF_ACTIVE_COUNT_7__EVENTS_MASK 0x07FF0000L 3969//SPI_LB_DATA_WAVES 3970#define SPI_LB_DATA_WAVES__COUNT0__SHIFT 0x0 3971#define SPI_LB_DATA_WAVES__COUNT1__SHIFT 0x10 3972#define SPI_LB_DATA_WAVES__COUNT0_MASK 0x0000FFFFL 3973#define SPI_LB_DATA_WAVES__COUNT1_MASK 0xFFFF0000L 3974//SPI_LB_DATA_PERCU_WAVE_HSGS 3975#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_HS__SHIFT 0x0 3976#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_GS__SHIFT 0x10 3977#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_HS_MASK 0x0000FFFFL 3978#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_GS_MASK 0xFFFF0000L 3979//SPI_LB_DATA_PERCU_WAVE_VSPS 3980#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_VS__SHIFT 0x0 3981#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_PS__SHIFT 0x10 3982#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_VS_MASK 0x0000FFFFL 3983#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_PS_MASK 0xFFFF0000L 3984//SPI_LB_DATA_PERCU_WAVE_CS 3985#define SPI_LB_DATA_PERCU_WAVE_CS__ACTIVE__SHIFT 0x0 3986#define SPI_LB_DATA_PERCU_WAVE_CS__ACTIVE_MASK 0xFFFFL 3987//SPI_P0_TRAP_SCREEN_PSBA_LO 3988#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0 3989#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xFFFFFFFFL 3990//SPI_P0_TRAP_SCREEN_PSBA_HI 3991#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0 3992#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xFFL 3993//SPI_P0_TRAP_SCREEN_PSMA_LO 3994#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0 3995#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xFFFFFFFFL 3996//SPI_P0_TRAP_SCREEN_PSMA_HI 3997#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0 3998#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xFFL 3999//SPI_P0_TRAP_SCREEN_GPR_MIN 4000#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0
4001#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6 4002#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x003FL 4003#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x03C0L 4004//SPI_P1_TRAP_SCREEN_PSBA_LO 4005#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0 4006#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xFFFFFFFFL 4007//SPI_P1_TRAP_SCREEN_PSBA_HI 4008#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0 4009#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xFFL 4010//SPI_P1_TRAP_SCREEN_PSMA_LO 4011#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0 4012#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xFFFFFFFFL 4013//SPI_P1_TRAP_SCREEN_PSMA_HI 4014#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0 4015#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xFFL 4016//SPI_P1_TRAP_SCREEN_GPR_MIN 4017#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0 4018#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6 4019#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x003FL 4020#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x03C0L 4021 4022 4023// addressBlock: gc_tpdec 4024//TD_CNTL 4025#define TD_CNTL__SYNC_PHASE_SH__SHIFT 0x0 4026#define TD_CNTL__SYNC_PHASE_VC_SMX__SHIFT 0x4 4027#define TD_CNTL__PAD_STALL_EN__SHIFT 0x8 4028#define TD_CNTL__EXTEND_LDS_STALL__SHIFT 0x9 4029#define TD_CNTL__LDS_STALL_PHASE_ADJUST__SHIFT 0xb 4030#define TD_CNTL__PRECISION_COMPATIBILITY__SHIFT 0xf 4031#define TD_CNTL__GATHER4_FLOAT_MODE__SHIFT 0x10 4032#define TD_CNTL__LD_FLOAT_MODE__SHIFT 0x12 4033#define TD_CNTL__GATHER4_DX9_MODE__SHIFT 0x13 4034#define TD_CNTL__DISABLE_POWER_THROTTLE__SHIFT 0x14 4035#define TD_CNTL__ENABLE_ROUND_TO_ZERO__SHIFT 0x15 4036#define TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT__SHIFT 0x17 4037#define TD_CNTL__DISABLE_MM_QNAN_COMPARE_RESULT__SHIFT 0x18 4038#define TD_CNTL__SYNC_PHASE_SH_MASK 0x00000003L 4039#define TD_CNTL__SYNC_PHASE_VC_SMX_MASK 0x00000030L 4040#define TD_CNTL__PAD_STALL_EN_MASK 0x00000100L 4041#define TD_CNTL__EXTEND_LDS_STALL_MASK 0x00000600L 4042#define TD_CNTL__LDS_STALL_PHASE_ADJUST_MASK 0x00001800L 4043#define TD_CNTL__PRECISION_COMPATIBILITY_MASK 0x00008000L 4044#define TD_CNTL__GATHER4_FLOAT_MODE_MASK 0x00010000L 4045#define TD_CNTL__LD_FLOAT_MODE_MASK 0x00040000L 4046#define TD_CNTL__GATHER4_DX9_MODE_MASK 0x00080000L 4047#define TD_CNTL__DISABLE_POWER_THROTTLE_MASK 0x00100000L 4048#define TD_CNTL__ENABLE_ROUND_TO_ZERO_MASK 0x00200000L 4049#define TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT_MASK 0x00800000L 4050#define TD_CNTL__DISABLE_MM_QNAN_COMPARE_RESULT_MASK 0x01000000L 4051//TD_STATUS 4052#define TD_STATUS__BUSY__SHIFT 0x1f 4053#define TD_STATUS__BUSY_MASK 0x80000000L 4054//TD_DSM_CNTL 4055#define TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA__SHIFT 0x0 4056#define TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE__SHIFT 0x2 4057#define TD_DSM_CNTL__TD_SS_FIFO_HI_DSM_IRRITATOR_DATA__SHIFT 0x3 4058#define TD_DSM_CNTL__TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE__SHIFT 0x5 4059#define TD_DSM_CNTL__TD_CS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x6 4060#define TD_DSM_CNTL__TD_CS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8 4061#define TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA_MASK 0x00000003L 4062#define TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE_MASK 0x00000004L 4063#define TD_DSM_CNTL__TD_SS_FIFO_HI_DSM_IRRITATOR_DATA_MASK 0x00000018L 4064#define TD_DSM_CNTL__TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE_MASK 0x00000020L 4065#define TD_DSM_CNTL__TD_CS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L 4066#define TD_DSM_CNTL__TD_CS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L 4067//TD_DSM_CNTL2 4068#define TD_DSM_CNTL2__TD_SS_FIFO_LO_ENABLE_ERROR_INJECT__SHIFT 0x0 4069#define TD_DSM_CNTL2__TD_SS_FIFO_LO_SELECT_INJECT_DELAY__SHIFT 0x2 4070#define TD_DSM_CNTL2__TD_SS_FIFO_HI_ENABLE_ERROR_INJECT__SHIFT 0x3 4071#define TD_DSM_CNTL2__TD_SS_FIFO_HI_SELECT_INJECT_DELAY__SHIFT 0x5 4072#define TD_DSM_CNTL2__TD_CS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x6 4073#define TD_DSM_CNTL2__TD_CS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x8 4074#define TD_DSM_CNTL2__TD_INJECT_DELAY__SHIFT 0x1a 4075#define TD_DSM_CNTL2__TD_SS_FIFO_LO_ENABLE_ERROR_INJECT_MASK 0x00000003L 4076#define TD_DSM_CNTL2__TD_SS_FIFO_LO_SELECT_INJECT_DELAY_MASK 0x00000004L 4077#define TD_DSM_CNTL2__TD_SS_FIFO_HI_ENABLE_ERROR_INJECT_MASK 0x00000018L 4078#define TD_DSM_CNTL2__TD_SS_FIFO_HI_SELECT_INJECT_DELAY_MASK 0x00000020L 4079#define TD_DSM_CNTL2__TD_CS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L 4080#define TD_DSM_CNTL2__TD_CS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L 4081#define TD_DSM_CNTL2__TD_INJECT_DELAY_MASK 0xFC000000L 4082//TD_SCRATCH 4083#define TD_SCRATCH__SCRATCH__SHIFT 0x0 4084#define TD_SCRATCH__SCRATCH_MASK 0xFFFFFFFFL 4085//TA_CNTL 4086#define TA_CNTL__FX_XNACK_CREDIT__SHIFT 0x0 4087#define TA_CNTL__SQ_XNACK_CREDIT__SHIFT 0x9 4088#define TA_CNTL__TC_DATA_CREDIT__SHIFT 0xd 4089#define TA_CNTL__ALIGNER_CREDIT__SHIFT 0x10 4090#define TA_CNTL__TD_FIFO_CREDIT__SHIFT 0x16 4091#define TA_CNTL__FX_XNACK_CREDIT_MASK 0x0000007FL 4092#define TA_CNTL__SQ_XNACK_CREDIT_MASK 0x00001E00L 4093#define TA_CNTL__TC_DATA_CREDIT_MASK 0x0000E000L 4094#define TA_CNTL__ALIGNER_CREDIT_MASK 0x001F0000L 4095#define TA_CNTL__TD_FIFO_CREDIT_MASK 0xFFC00000L 4096//TA_CNTL_AUX 4097#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N__SHIFT 0x0 4098#define TA_CNTL_AUX__RESERVED__SHIFT 0x1 4099#define TA_CNTL_AUX__TFAULT_EN_OVERRIDE__SHIFT 0x5 4100#define TA_CNTL_AUX__GATHERH_DST_SEL__SHIFT 0x6 4101#define TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE__SHIFT 0x7 4102#define TA_CNTL_AUX__NONIMG_ANISO_BYPASS__SHIFT 0x9 4103#define TA_CNTL_AUX__ANISO_HALF_THRESH__SHIFT 0xa 4104#define TA_CNTL_AUX__ANISO_ERROR_FP_VBIAS__SHIFT 0xc 4105#define TA_CNTL_AUX__ANISO_STEP_ORDER__SHIFT 0xd 4106#define TA_CNTL_AUX__ANISO_STEP__SHIFT 0xe 4107#define TA_CNTL_AUX__MINMAG_UNNORM__SHIFT 0xf 4108#define TA_CNTL_AUX__ANISO_WEIGHT_MODE__SHIFT 0x10 4109#define TA_CNTL_AUX__ANISO_RATIO_LUT__SHIFT 0x11 4110#define TA_CNTL_AUX__ANISO_TAP__SHIFT 0x12 4111#define TA_CNTL_AUX__ANISO_MIP_ADJ_MODE__SHIFT 0x13 4112#define TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE__SHIFT 0x14 4113#define TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE__SHIFT 0x15 4114#define TA_CNTL_AUX__DETERMINISM_MISC_DISABLE__SHIFT 0x16 4115#define TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE__SHIFT 0x17 4116#define TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE__SHIFT 0x18 4117#define TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE__SHIFT 0x19 4118#define TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE__SHIFT 0x1a 4119#define TA_CNTL_AUX__DISABLE_DWORD_X2_COALESCE__SHIFT 0x1b 4120#define TA_CNTL_AUX__CUBEMAP_SLICE_CLAMP__SHIFT 0x1c 4121#define TA_CNTL_AUX__TRUNC_SMALL_NEG__SHIFT 0x1d 4122#define TA_CNTL_AUX__ARRAY_ROUND_MODE__SHIFT 0x1e 4123#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N_MASK 0x00000001L 4124#define TA_CNTL_AUX__RESERVED_MASK 0x0000000EL 4125#define TA_CNTL_AUX__TFAULT_EN_OVERRIDE_MASK 0x00000020L 4126#define TA_CNTL_AUX__GATHERH_DST_SEL_MASK 0x00000040L 4127#define TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE_MASK 0x00000080L 4128#define TA_CNTL_AUX__NONIMG_ANISO_BYPASS_MASK 0x00000200L 4129#define TA_CNTL_AUX__ANISO_HALF_THRESH_MASK 0x00000C00L 4130#define TA_CNTL_AUX__ANISO_ERROR_FP_VBIAS_MASK 0x00001000L 4131#define TA_CNTL_AUX__ANISO_STEP_ORDER_MASK 0x00002000L 4132#define TA_CNTL_AUX__ANISO_STEP_MASK 0x00004000L 4133#define TA_CNTL_AUX__MINMAG_UNNORM_MASK 0x00008000L 4134#define TA_CNTL_AUX__ANISO_WEIGHT_MODE_MASK 0x00010000L 4135#define TA_CNTL_AUX__ANISO_RATIO_LUT_MASK 0x00020000L 4136#define TA_CNTL_AUX__ANISO_TAP_MASK 0x00040000L 4137#define TA_CNTL_AUX__ANISO_MIP_ADJ_MODE_MASK 0x00080000L 4138#define TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE_MASK 0x00100000L 4139#define TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE_MASK 0x00200000L 4140#define TA_CNTL_AUX__DETERMINISM_MISC_DISABLE_MASK 0x00400000L 4141#define TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE_MASK 0x00800000L 4142#define TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE_MASK 0x01000000L 4143#define TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE_MASK 0x02000000L 4144#define TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE_MASK 0x04000000L 4145#define TA_CNTL_AUX__DISABLE_DWORD_X2_COALESCE_MASK 0x08000000L 4146#define TA_CNTL_AUX__CUBEMAP_SLICE_CLAMP_MASK 0x10000000L 4147#define TA_CNTL_AUX__TRUNC_SMALL_NEG_MASK 0x20000000L 4148#define TA_CNTL_AUX__ARRAY_ROUND_MODE_MASK 0xC0000000L 4149//TA_RESERVED_010C 4150#define TA_RESERVED_010C__Unused__SHIFT 0x0 4151#define TA_RESERVED_010C__Unused_MASK 0xFFFFFFFFL 4152//TA_STATUS 4153#define TA_STATUS__FG_PFIFO_EMPTYB__SHIFT 0xc 4154#define TA_STATUS__FG_LFIFO_EMPTYB__SHIFT 0xd 4155#define TA_STATUS__FG_SFIFO_EMPTYB__SHIFT 0xe 4156#define TA_STATUS__FL_PFIFO_EMPTYB__SHIFT 0x10 4157#define TA_STATUS__FL_LFIFO_EMPTYB__SHIFT 0x11 4158#define TA_STATUS__FL_SFIFO_EMPTYB__SHIFT 0x12 4159#define TA_STATUS__FA_PFIFO_EMPTYB__SHIFT 0x14 4160#define TA_STATUS__FA_LFIFO_EMPTYB__SHIFT 0x15 4161#define TA_STATUS__FA_SFIFO_EMPTYB__SHIFT 0x16 4162#define TA_STATUS__IN_BUSY__SHIFT 0x18 4163#define TA_STATUS__FG_BUSY__SHIFT 0x19 4164#define TA_STATUS__LA_BUSY__SHIFT 0x1a 4165#define TA_STATUS__FL_BUSY__SHIFT 0x1b 4166#define TA_STATUS__TA_BUSY__SHIFT 0x1c 4167#define TA_STATUS__FA_BUSY__SHIFT 0x1d 4168#define TA_STATUS__AL_BUSY__SHIFT 0x1e 4169#define TA_STATUS__BUSY__SHIFT 0x1f 4170#define TA_STATUS__FG_PFIFO_EMPTYB_MASK 0x00001000L 4171#define TA_STATUS__FG_LFIFO_EMPTYB_MASK 0x00002000L 4172#define TA_STATUS__FG_SFIFO_EMPTYB_MASK 0x00004000L 4173#define TA_STATUS__FL_PFIFO_EMPTYB_MASK 0x00010000L 4174#define TA_STATUS__FL_LFIFO_EMPTYB_MASK 0x00020000L 4175#define TA_STATUS__FL_SFIFO_EMPTYB_MASK 0x00040000L 4176#define TA_STATUS__FA_PFIFO_EMPTYB_MASK 0x00100000L 4177#define TA_STATUS__FA_LFIFO_EMPTYB_MASK 0x00200000L 4178#define TA_STATUS__FA_SFIFO_EMPTYB_MASK 0x00400000L 4179#define TA_STATUS__IN_BUSY_MASK 0x01000000L 4180#define TA_STATUS__FG_BUSY_MASK 0x02000000L 4181#define TA_STATUS__LA_BUSY_MASK 0x04000000L 4182#define TA_STATUS__FL_BUSY_MASK 0x08000000L 4183#define TA_STATUS__TA_BUSY_MASK 0x10000000L 4184#define TA_STATUS__FA_BUSY_MASK 0x20000000L 4185#define TA_STATUS__AL_BUSY_MASK 0x40000000L 4186#define TA_STATUS__BUSY_MASK 0x80000000L 4187//TA_SCRATCH 4188#define TA_SCRATCH__SCRATCH__SHIFT 0x0 4189#define TA_SCRATCH__SCRATCH_MASK 0xFFFFFFFFL 4190 4191 4192// addressBlock: gc_gdsdec 4193//GDS_CONFIG 4194#define GDS_CONFIG__SH0_GPR_PHASE_SEL__SHIFT 0x1 4195#define GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT 0x3 4196#define GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT 0x5 4197#define GDS_CONFIG__SH3_GPR_PHASE_SEL__SHIFT 0x7 4198#define GDS_CONFIG__SH0_GPR_PHASE_SEL_MASK 0x00000006L 4199#define GDS_CONFIG__SH1_GPR_PHASE_SEL_MASK 0x00000018L 4200#define GDS_CONFIG__SH2_GPR_PHASE_SEL_MASK 0x00000060L 4201#define GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK 0x00000180L 4202//GDS_CNTL_STATUS 4203#define GDS_CNTL_STATUS__GDS_BUSY__SHIFT 0x0 4204#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY__SHIFT 0x1 4205#define GDS_CNTL_STATUS__ORD_APP_BUSY__SHIFT 0x2 4206#define GDS_CNTL_STATUS__DS_BANK_CONFLICT__SHIFT 0x3 4207#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT__SHIFT 0x4 4208#define GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT 0x5 4209#define GDS_CNTL_STATUS__DS_RD_CLAMP__SHIFT 0x6 4210#define GDS_CNTL_STATUS__GRBM_RBUF_BUSY__SHIFT 0x7 4211#define GDS_CNTL_STATUS__DS_BUSY__SHIFT 0x8 4212#define GDS_CNTL_STATUS__GWS_BUSY__SHIFT 0x9 4213#define GDS_CNTL_STATUS__ORD_FIFO_BUSY__SHIFT 0xa 4214#define GDS_CNTL_STATUS__CREDIT_BUSY0__SHIFT 0xb 4215#define GDS_CNTL_STATUS__CREDIT_BUSY1__SHIFT 0xc 4216#define GDS_CNTL_STATUS__CREDIT_BUSY2__SHIFT 0xd 4217#define GDS_CNTL_STATUS__CREDIT_BUSY3__SHIFT 0xe 4218#define GDS_CNTL_STATUS__GDS_BUSY_MASK 0x00000001L 4219#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY_MASK 0x00000002L 4220#define GDS_CNTL_STATUS__ORD_APP_BUSY_MASK 0x00000004L 4221#define GDS_CNTL_STATUS__DS_BANK_CONFLICT_MASK 0x00000008L 4222#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT_MASK 0x00000010L 4223#define GDS_CNTL_STATUS__DS_WR_CLAMP_MASK 0x00000020L 4224#define GDS_CNTL_STATUS__DS_RD_CLAMP_MASK 0x00000040L 4225#define GDS_CNTL_STATUS__GRBM_RBUF_BUSY_MASK 0x00000080L 4226#define GDS_CNTL_STATUS__DS_BUSY_MASK 0x00000100L 4227#define GDS_CNTL_STATUS__GWS_BUSY_MASK 0x00000200L 4228#define GDS_CNTL_STATUS__ORD_FIFO_BUSY_MASK 0x00000400L 4229#define GDS_CNTL_STATUS__CREDIT_BUSY0_MASK 0x00000800L 4230#define GDS_CNTL_STATUS__CREDIT_BUSY1_MASK 0x00001000L 4231#define GDS_CNTL_STATUS__CREDIT_BUSY2_MASK 0x00002000L 4232#define GDS_CNTL_STATUS__CREDIT_BUSY3_MASK 0x00004000L 4233//GDS_ENHANCE2 4234#define GDS_ENHANCE2__MISC__SHIFT 0x0 4235#define GDS_ENHANCE2__UNUSED__SHIFT 0x10 4236#define GDS_ENHANCE2__MISC_MASK 0x0000FFFFL 4237#define GDS_ENHANCE2__UNUSED_MASK 0xFFFF0000L 4238//GDS_PROTECTION_FAULT 4239#define GDS_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0 4240#define GDS_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1 4241#define GDS_PROTECTION_FAULT__GRBM__SHIFT 0x2 4242#define GDS_PROTECTION_FAULT__SH_ID__SHIFT 0x3 4243#define GDS_PROTECTION_FAULT__CU_ID__SHIFT 0x6 4244#define GDS_PROTECTION_FAULT__SIMD_ID__SHIFT 0xa 4245#define GDS_PROTECTION_FAULT__WAVE_ID__SHIFT 0xc 4246#define GDS_PROTECTION_FAULT__ADDRESS__SHIFT 0x10 4247#define GDS_PROTECTION_FAULT__WRITE_DIS_MASK 0x00000001L 4248#define GDS_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x00000002L 4249#define GDS_PROTECTION_FAULT__GRBM_MASK 0x00000004L 4250#define GDS_PROTECTION_FAULT__SH_ID_MASK 0x00000038L 4251#define GDS_PROTECTION_FAULT__CU_ID_MASK 0x000003C0L 4252#define GDS_PROTECTION_FAULT__SIMD_ID_MASK 0x00000C00L 4253#define GDS_PROTECTION_FAULT__WAVE_ID_MASK 0x0000F000L 4254#define GDS_PROTECTION_FAULT__ADDRESS_MASK 0xFFFF0000L 4255//GDS_VM_PROTECTION_FAULT 4256#define GDS_VM_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0 4257#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1 4258#define GDS_VM_PROTECTION_FAULT__GWS__SHIFT 0x2 4259#define GDS_VM_PROTECTION_FAULT__OA__SHIFT 0x3 4260#define GDS_VM_PROTECTION_FAULT__GRBM__SHIFT 0x4 4261#define GDS_VM_PROTECTION_FAULT__TMZ__SHIFT 0x5 4262#define GDS_VM_PROTECTION_FAULT__VMID__SHIFT 0x8 4263#define GDS_VM_PROTECTION_FAULT__ADDRESS__SHIFT 0x10 4264#define GDS_VM_PROTECTION_FAULT__WRITE_DIS_MASK 0x00000001L 4265#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x00000002L 4266#define GDS_VM_PROTECTION_FAULT__GWS_MASK 0x00000004L 4267#define GDS_VM_PROTECTION_FAULT__OA_MASK 0x00000008L 4268#define GDS_VM_PROTECTION_FAULT__GRBM_MASK 0x00000010L 4269#define GDS_VM_PROTECTION_FAULT__TMZ_MASK 0x00000020L 4270#define GDS_VM_PROTECTION_FAULT__VMID_MASK 0x00000F00L 4271#define GDS_VM_PROTECTION_FAULT__ADDRESS_MASK 0xFFFF0000L 4272//GDS_EDC_CNT 4273#define GDS_EDC_CNT__GDS_MEM_DED__SHIFT 0x0 4274#define GDS_EDC_CNT__GDS_INPUT_QUEUE_SED__SHIFT 0x2 4275#define GDS_EDC_CNT__GDS_MEM_SEC__SHIFT 0x4 4276#define GDS_EDC_CNT__UNUSED__SHIFT 0x6 4277#define GDS_EDC_CNT__GDS_MEM_DED_MASK 0x00000003L 4278#define GDS_EDC_CNT__GDS_INPUT_QUEUE_SED_MASK 0x0000000CL 4279#define GDS_EDC_CNT__GDS_MEM_SEC_MASK 0x00000030L 4280#define GDS_EDC_CNT__UNUSED_MASK 0xFFFFFFC0L 4281//GDS_EDC_GRBM_CNT 4282#define GDS_EDC_GRBM_CNT__DED__SHIFT 0x0 4283#define GDS_EDC_GRBM_CNT__SEC__SHIFT 0x2 4284#define GDS_EDC_GRBM_CNT__UNUSED__SHIFT 0x4 4285#define GDS_EDC_GRBM_CNT__DED_MASK 0x00000003L 4286#define GDS_EDC_GRBM_CNT__SEC_MASK 0x0000000CL 4287#define GDS_EDC_GRBM_CNT__UNUSED_MASK 0xFFFFFFF0L 4288//GDS_EDC_OA_DED 4289#define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED__SHIFT 0x0 4290#define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED__SHIFT 0x1 4291#define GDS_EDC_OA_DED__ME0_CS_DED__SHIFT 0x2 4292#define GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED__SHIFT 0x3 4293#define GDS_EDC_OA_DED__ME1_PIPE0_DED__SHIFT 0x4 4294#define GDS_EDC_OA_DED__ME1_PIPE1_DED__SHIFT 0x5 4295#define GDS_EDC_OA_DED__ME1_PIPE2_DED__SHIFT 0x6 4296#define GDS_EDC_OA_DED__ME1_PIPE3_DED__SHIFT 0x7 4297#define GDS_EDC_OA_DED__ME2_PIPE0_DED__SHIFT 0x8 4298#define GDS_EDC_OA_DED__ME2_PIPE1_DED__SHIFT 0x9 4299#define GDS_EDC_OA_DED__ME2_PIPE2_DED__SHIFT 0xa 4300#define GDS_EDC_OA_DED__ME2_PIPE3_DED__SHIFT 0xb 4301#define GDS_EDC_OA_DED__UNUSED1__SHIFT 0xc 4302#define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED_MASK 0x00000001L 4303#define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED_MASK 0x00000002L 4304#define GDS_EDC_OA_DED__ME0_CS_DED_MASK 0x00000004L 4305#define GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED_MASK 0x00000008L 4306#define GDS_EDC_OA_DED__ME1_PIPE0_DED_MASK 0x00000010L 4307#define GDS_EDC_OA_DED__ME1_PIPE1_DED_MASK 0x00000020L 4308#define GDS_EDC_OA_DED__ME1_PIPE2_DED_MASK 0x00000040L 4309#define GDS_EDC_OA_DED__ME1_PIPE3_DED_MASK 0x00000080L 4310#define GDS_EDC_OA_DED__ME2_PIPE0_DED_MASK 0x00000100L 4311#define GDS_EDC_OA_DED__ME2_PIPE1_DED_MASK 0x00000200L 4312#define GDS_EDC_OA_DED__ME2_PIPE2_DED_MASK 0x00000400L 4313#define GDS_EDC_OA_DED__ME2_PIPE3_DED_MASK 0x00000800L 4314#define GDS_EDC_OA_DED__UNUSED1_MASK 0xFFFFF000L 4315//GDS_DSM_CNTL 4316#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0__SHIFT 0x0 4317#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1__SHIFT 0x1 4318#define GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 4319#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0__SHIFT 0x3 4320#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1__SHIFT 0x4 4321#define GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE__SHIFT 0x5 4322#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0__SHIFT 0x6 4323#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1__SHIFT 0x7 4324#define GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x8 4325#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0__SHIFT 0x9 4326#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1__SHIFT 0xa 4327#define GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xb 4328#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0__SHIFT 0xc 4329#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1__SHIFT 0xd 4330#define GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE__SHIFT 0xe 4331#define GDS_DSM_CNTL__UNUSED__SHIFT 0xf 4332#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0_MASK 0x00000001L 4333#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1_MASK 0x00000002L 4334#define GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L 4335#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0_MASK 0x00000008L 4336#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1_MASK 0x00000010L 4337#define GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE_MASK 0x00000020L 4338#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0_MASK 0x00000040L 4339#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1_MASK 0x00000080L 4340#define GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000100L 4341#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0_MASK 0x00000200L 4342#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1_MASK 0x00000400L 4343#define GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000800L 4344#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0_MASK 0x00001000L 4345#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1_MASK 0x00002000L 4346#define GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L 4347#define GDS_DSM_CNTL__UNUSED_MASK 0xFFFF8000L 4348//GDS_EDC_OA_PHY_CNT 4349#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC__SHIFT 0x0 4350#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED__SHIFT 0x2 4351#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC__SHIFT 0x4 4352#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED__SHIFT 0x6 4353#define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SED__SHIFT 0x8 4354#define GDS_EDC_OA_PHY_CNT__UNUSED1__SHIFT 0xa 4355#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC_MASK 0x00000003L 4356#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED_MASK 0x0000000CL 4357#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC_MASK 0x00000030L 4358#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED_MASK 0x000000C0L 4359#define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SED_MASK 0x00000300L 4360#define GDS_EDC_OA_PHY_CNT__UNUSED1_MASK 0xFFFFFC00L 4361//GDS_EDC_OA_PIPE_CNT 4362#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC__SHIFT 0x0 4363#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED__SHIFT 0x2 4364#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC__SHIFT 0x4 4365#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED__SHIFT 0x6 4366#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC__SHIFT 0x8 4367#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED__SHIFT 0xa 4368#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC__SHIFT 0xc 4369#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED__SHIFT 0xe 4370#define GDS_EDC_OA_PIPE_CNT__UNUSED__SHIFT 0x10 4371#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC_MASK 0x00000003L 4372#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED_MASK 0x0000000CL 4373#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC_MASK 0x00000030L 4374#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED_MASK 0x000000C0L 4375#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC_MASK 0x00000300L 4376#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED_MASK 0x00000C00L 4377#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC_MASK 0x00003000L 4378#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED_MASK 0x0000C000L 4379#define GDS_EDC_OA_PIPE_CNT__UNUSED_MASK 0xFFFF0000L 4380//GDS_DSM_CNTL2 4381#define GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT__SHIFT 0x0 4382#define GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY__SHIFT 0x2 4383#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT__SHIFT 0x3 4384#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY__SHIFT 0x5 4385#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT__SHIFT 0x6 4386#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY__SHIFT 0x8 4387#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9 4388#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY__SHIFT 0xb 4389#define GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT__SHIFT 0xc 4390#define GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY__SHIFT 0xe 4391#define GDS_DSM_CNTL2__UNUSED__SHIFT 0xf 4392#define GDS_DSM_CNTL2__GDS_INJECT_DELAY__SHIFT 0x1a 4393#define GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT_MASK 0x00000003L 4394#define GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY_MASK 0x00000004L 4395#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT_MASK 0x00000018L 4396#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY_MASK 0x00000020L 4397#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT_MASK 0x000000C0L 4398#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY_MASK 0x00000100L 4399#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L 4400#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L 4401#define GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT_MASK 0x00003000L 4402#define GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY_MASK 0x00004000L 4403#define GDS_DSM_CNTL2__UNUSED_MASK 0x03FF8000L 4404#define GDS_DSM_CNTL2__GDS_INJECT_DELAY_MASK 0xFC000000L 4405//GDS_WD_GDS_CSB 4406#define GDS_WD_GDS_CSB__COUNTER__SHIFT 0x0 4407#define GDS_WD_GDS_CSB__UNUSED__SHIFT 0xd 4408#define GDS_WD_GDS_CSB__COUNTER_MASK 0x00001FFFL 4409#define GDS_WD_GDS_CSB__UNUSED_MASK 0xFFFFE000L 4410 4411 4412// addressBlock: gc_rbdec 4413//DB_DEBUG 4414#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE__SHIFT 0x0 4415#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE__SHIFT 0x1 4416#define DB_DEBUG__FETCH_FULL_Z_TILE__SHIFT 0x2 4417#define DB_DEBUG__FETCH_FULL_STENCIL_TILE__SHIFT 0x3 4418#define DB_DEBUG__FORCE_Z_MODE__SHIFT 0x4 4419#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ__SHIFT 0x6 4420#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ__SHIFT 0x7 4421#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE__SHIFT 0x8 4422#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT 0xa 4423#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1__SHIFT 0xc 4424#define DB_DEBUG__DEBUG_FAST_Z_DISABLE__SHIFT 0xe 4425#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE__SHIFT 0xf 4426#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE__SHIFT 0x10 4427#define DB_DEBUG__DISABLE_SUMM_SQUADS__SHIFT 0x11 4428#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS__SHIFT 0x12 4429#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE__SHIFT 0x13 4430#define DB_DEBUG__NEVER_FREE_Z_ONLY__SHIFT 0x15 4431#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS__SHIFT 0x16 4432#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT 0x17 4433#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES__SHIFT 0x18 4434#define DB_DEBUG__ONE_FREE_IN_FLIGHT__SHIFT 0x1c 4435#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT 0x1d 4436#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC__SHIFT 0x1e 4437#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC__SHIFT 0x1f 4438#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE_MASK 0x00000001L 4439#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE_MASK 0x00000002L 4440#define DB_DEBUG__FETCH_FULL_Z_TILE_MASK 0x00000004L 4441#define DB_DEBUG__FETCH_FULL_STENCIL_TILE_MASK 0x00000008L 4442#define DB_DEBUG__FORCE_Z_MODE_MASK 0x00000030L 4443#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ_MASK 0x00000040L 4444#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ_MASK 0x00000080L 4445#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE_MASK 0x00000300L 4446#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0_MASK 0x00000C00L 4447#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1_MASK 0x00003000L 4448#define DB_DEBUG__DEBUG_FAST_Z_DISABLE_MASK 0x00004000L 4449#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE_MASK 0x00008000L 4450#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE_MASK 0x00010000L 4451#define DB_DEBUG__DISABLE_SUMM_SQUADS_MASK 0x00020000L 4452#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS_MASK 0x00040000L 4453#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE_MASK 0x00180000L 4454#define DB_DEBUG__NEVER_FREE_Z_ONLY_MASK 0x00200000L 4455#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS_MASK 0x00400000L 4456#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK 0x00800000L 4457#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES_MASK 0x0F000000L 4458#define DB_DEBUG__ONE_FREE_IN_FLIGHT_MASK 0x10000000L 4459#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT_MASK 0x20000000L 4460#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC_MASK 0x40000000L 4461#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC_MASK 0x80000000L 4462//DB_DEBUG2 4463#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING__SHIFT 0x0 4464#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE__SHIFT 0x1 4465#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE__SHIFT 0x2 4466#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB__SHIFT 0x3 4467#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 0x4 4468#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL__SHIFT 0x5 4469#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ__SHIFT 0x6 4470#define DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL__SHIFT 0x7 4471#define DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE__SHIFT 0x8 4472#define DB_DEBUG2__CLK_OFF_DELAY__SHIFT 0x9 4473#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER__SHIFT 0xe 4474#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING__SHIFT 0xf 4475#define DB_DEBUG2__RESERVED__SHIFT 0x10 4476#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING__SHIFT 0x11 4477#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING__SHIFT 0x12 4478#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL__SHIFT 0x13 4479#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM__SHIFT 0x1c 4480#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT 0x1d 4481#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM__SHIFT 0x1e 4482#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT__SHIFT 0x1f 4483#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING_MASK 0x00000001L 4484#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE_MASK 0x00000002L 4485#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE_MASK 0x00000004L 4486#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB_MASK 0x00000008L 4487#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK 0x00000010L 4488#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_MASK 0x00000020L 4489#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ_MASK 0x00000040L 4490#define DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL_MASK 0x00000080L 4491#define DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE_MASK 0x00000100L 4492#define DB_DEBUG2__CLK_OFF_DELAY_MASK 0x00003E00L 4493#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER_MASK 0x00004000L 4494#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING_MASK 0x00008000L 4495#define DB_DEBUG2__RESERVED_MASK 0x00010000L 4496#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING_MASK 0x00020000L 4497#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING_MASK 0x00040000L 4498#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL_MASK 0x00080000L 4499#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM_MASK 0x10000000L 4500#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL_MASK 0x20000000L 4501#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM_MASK 0x40000000L 4502#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT_MASK 0x80000000L 4503//DB_DEBUG3 4504#define DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION__SHIFT 0x0 4505#define DB_DEBUG3__ROUND_ZRANGE_CORRECTION__SHIFT 0x1 4506#define DB_DEBUG3__FORCE_DB_IS_GOOD__SHIFT 0x2 4507#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION__SHIFT 0x3 4508#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT 0x4 4509#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z__SHIFT 0x5 4510#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z__SHIFT 0x6 4511#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS__SHIFT 0x7 4512#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION__SHIFT 0x8 4513#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT__SHIFT 0x9 4514#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT 0xa 4515#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS__SHIFT 0xb 4516#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING__SHIFT 0xc 4517#define DB_DEBUG3__DISABLE_OP_DF_BYPASS__SHIFT 0xd 4518#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE__SHIFT 0xe 4519#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK__SHIFT 0xf 4520#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION__SHIFT 0x10 4521#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE__SHIFT 0x11 4522#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING__SHIFT 0x12 4523#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE__SHIFT 0x13 4524#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE__SHIFT 0x14 4525#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT__SHIFT 0x15 4526#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB__SHIFT 0x16 4527#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD__SHIFT 0x17 4528#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT__SHIFT 0x18 4529#define DB_DEBUG3__DISABLE_DI_DT_STALL__SHIFT 0x19 4530#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET__SHIFT 0x1a 4531#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX__SHIFT 0x1b 4532#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND__SHIFT 0x1c 4533#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND__SHIFT 0x1d 4534#define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE__SHIFT 0x1e 4535#define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK__SHIFT 0x1f 4536#define DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION_MASK 0x00000001L 4537#define DB_DEBUG3__ROUND_ZRANGE_CORRECTION_MASK 0x00000002L 4538#define DB_DEBUG3__FORCE_DB_IS_GOOD_MASK 0x00000004L 4539#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION_MASK 0x00000008L 4540#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP_MASK 0x00000010L 4541#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z_MASK 0x00000020L 4542#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z_MASK 0x00000040L 4543#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS_MASK 0x00000080L 4544#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION_MASK 0x00000100L 4545#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT_MASK 0x00000200L 4546#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP_MASK 0x00000400L 4547#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS_MASK 0x00000800L 4548#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING_MASK 0x00001000L 4549#define DB_DEBUG3__DISABLE_OP_DF_BYPASS_MASK 0x00002000L 4550#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE_MASK 0x00004000L 4551#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK_MASK 0x00008000L 4552#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION_MASK 0x00010000L 4553#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE_MASK 0x00020000L 4554#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING_MASK 0x00040000L 4555#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK 0x00080000L 4556#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK 0x00100000L 4557#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT_MASK 0x00200000L 4558#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB_MASK 0x00400000L 4559#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD_MASK 0x00800000L 4560#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT_MASK 0x01000000L 4561#define DB_DEBUG3__DISABLE_DI_DT_STALL_MASK 0x02000000L 4562#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET_MASK 0x04000000L 4563#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX_MASK 0x08000000L 4564#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND_MASK 0x10000000L 4565#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND_MASK 0x20000000L 4566#define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE_MASK 0x40000000L 4567#define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK_MASK 0x80000000L 4568//DB_DEBUG4 4569#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION__SHIFT 0x0 4570#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION__SHIFT 0x1 4571#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL__SHIFT 0x2 4572#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL__SHIFT 0x3 4573#define DB_DEBUG4__DISABLE_4XAA_2P_ZD_HOLDOFF__SHIFT 0x4 4574#define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION__SHIFT 0x5 4575#define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE__SHIFT 0x6 4576#define DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN__SHIFT 0x7 4577#define DB_DEBUG4__DFSM_CONVERT_PASSTHROUGH_TO_BYPASS__SHIFT 0x8 4578#define DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR__SHIFT 0x9 4579#define DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR__SHIFT 0xa 4580#define DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR__SHIFT 0xb 4581#define DB_DEBUG4__DISABLE_SEPARATE_DFSM_CLK__SHIFT 0xc 4582#define DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP__SHIFT 0xd 4583#define DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION__SHIFT 0xe 4584#define DB_DEBUG4__DISABLE_TS_WRITE_L0__SHIFT 0xf 4585#define DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE__SHIFT 0x10 4586#define DB_DEBUG4__DISABLE_HIZ_Q1_TS_COLLISION_DETECT__SHIFT 0x11 4587#define DB_DEBUG4__DISABLE_HIZ_Q2_TS_COLLISION_DETECT__SHIFT 0x12 4588#define DB_DEBUG4__DB_EXTRA_DEBUG4__SHIFT 0x13 4589#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION_MASK 0x00000001L 4590#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION_MASK 0x00000002L 4591#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL_MASK 0x00000004L 4592#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL_MASK 0x00000008L 4593#define DB_DEBUG4__DISABLE_4XAA_2P_ZD_HOLDOFF_MASK 0x00000010L 4594#define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION_MASK 0x00000020L 4595#define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE_MASK 0x00000040L 4596#define DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN_MASK 0x00000080L 4597#define DB_DEBUG4__DFSM_CONVERT_PASSTHROUGH_TO_BYPASS_MASK 0x00000100L 4598#define DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR_MASK 0x00000200L 4599#define DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR_MASK 0x00000400L 4600#define DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR_MASK 0x00000800L 4601#define DB_DEBUG4__DISABLE_SEPARATE_DFSM_CLK_MASK 0x00001000L 4602#define DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP_MASK 0x00002000L 4603#define DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION_MASK 0x00004000L 4604#define DB_DEBUG4__DISABLE_TS_WRITE_L0_MASK 0x00008000L 4605#define DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE_MASK 0x00010000L 4606#define DB_DEBUG4__DISABLE_HIZ_Q1_TS_COLLISION_DETECT_MASK 0x00020000L 4607#define DB_DEBUG4__DISABLE_HIZ_Q2_TS_COLLISION_DETECT_MASK 0x00040000L 4608#define DB_DEBUG4__DB_EXTRA_DEBUG4_MASK 0xFFF80000L 4609//DB_CREDIT_LIMIT 4610#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS__SHIFT 0x0 4611#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS__SHIFT 0x5 4612#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS__SHIFT 0xa 4613#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS__SHIFT 0x18 4614#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS_MASK 0x0000001FL 4615#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS_MASK 0x000003E0L 4616#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS_MASK 0x00001C00L 4617#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS_MASK 0x7F000000L 4618//DB_WATERMARKS 4619#define DB_WATERMARKS__DEPTH_FREE__SHIFT 0x0 4620#define DB_WATERMARKS__DEPTH_FLUSH__SHIFT 0x5 4621#define DB_WATERMARKS__FORCE_SUMMARIZE__SHIFT 0xb 4622#define DB_WATERMARKS__DEPTH_PENDING_FREE__SHIFT 0xf 4623#define DB_WATERMARKS__DEPTH_CACHELINE_FREE__SHIFT 0x14 4624#define DB_WATERMARKS__AUTO_FLUSH_HTILE__SHIFT 0x1e 4625#define DB_WATERMARKS__AUTO_FLUSH_QUAD__SHIFT 0x1f 4626#define DB_WATERMARKS__DEPTH_FREE_MASK 0x0000001FL 4627#define DB_WATERMARKS__DEPTH_FLUSH_MASK 0x000007E0L 4628#define DB_WATERMARKS__FORCE_SUMMARIZE_MASK 0x00007800L 4629#define DB_WATERMARKS__DEPTH_PENDING_FREE_MASK 0x000F8000L 4630#define DB_WATERMARKS__DEPTH_CACHELINE_FREE_MASK 0x0FF00000L 4631#define DB_WATERMARKS__AUTO_FLUSH_HTILE_MASK 0x40000000L 4632#define DB_WATERMARKS__AUTO_FLUSH_QUAD_MASK 0x80000000L 4633//DB_SUBTILE_CONTROL 4634#define DB_SUBTILE_CONTROL__MSAA1_X__SHIFT 0x0 4635#define DB_SUBTILE_CONTROL__MSAA1_Y__SHIFT 0x2 4636#define DB_SUBTILE_CONTROL__MSAA2_X__SHIFT 0x4 4637#define DB_SUBTILE_CONTROL__MSAA2_Y__SHIFT 0x6 4638#define DB_SUBTILE_CONTROL__MSAA4_X__SHIFT 0x8 4639#define DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT 0xa 4640#define DB_SUBTILE_CONTROL__MSAA8_X__SHIFT 0xc 4641#define DB_SUBTILE_CONTROL__MSAA8_Y__SHIFT 0xe 4642#define DB_SUBTILE_CONTROL__MSAA16_X__SHIFT 0x10 4643#define DB_SUBTILE_CONTROL__MSAA16_Y__SHIFT 0x12 4644#define DB_SUBTILE_CONTROL__MSAA1_X_MASK 0x00000003L 4645#define DB_SUBTILE_CONTROL__MSAA1_Y_MASK 0x0000000CL 4646#define DB_SUBTILE_CONTROL__MSAA2_X_MASK 0x00000030L 4647#define DB_SUBTILE_CONTROL__MSAA2_Y_MASK 0x000000C0L 4648#define DB_SUBTILE_CONTROL__MSAA4_X_MASK 0x00000300L 4649#define DB_SUBTILE_CONTROL__MSAA4_Y_MASK 0x00000C00L 4650#define DB_SUBTILE_CONTROL__MSAA8_X_MASK 0x00003000L 4651#define DB_SUBTILE_CONTROL__MSAA8_Y_MASK 0x0000C000L 4652#define DB_SUBTILE_CONTROL__MSAA16_X_MASK 0x00030000L 4653#define DB_SUBTILE_CONTROL__MSAA16_Y_MASK 0x000C0000L 4654//DB_FREE_CACHELINES 4655#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH__SHIFT 0x0 4656#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH__SHIFT 0x7 4657#define DB_FREE_CACHELINES__FREE_Z_DEPTH__SHIFT 0xe 4658#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH__SHIFT 0x14 4659#define DB_FREE_CACHELINES__QUAD_READ_REQS__SHIFT 0x18 4660#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH_MASK 0x0000007FL 4661#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH_MASK 0x00003F80L 4662#define DB_FREE_CACHELINES__FREE_Z_DEPTH_MASK 0x000FC000L 4663#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH_MASK 0x00F00000L 4664#define DB_FREE_CACHELINES__QUAD_READ_REQS_MASK 0xFF000000L 4665//DB_FIFO_DEPTH1 4666#define DB_FIFO_DEPTH1__DB_RMI_RDREQ_CREDITS__SHIFT 0x0 4667#define DB_FIFO_DEPTH1__DB_RMI_WRREQ_CREDITS__SHIFT 0x5 4668#define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT 0xa 4669#define DB_FIFO_DEPTH1__QC_DEPTH__SHIFT 0x10 4670#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH__SHIFT 0x15 4671#define DB_FIFO_DEPTH1__DB_RMI_RDREQ_CREDITS_MASK 0x0000001FL 4672#define DB_FIFO_DEPTH1__DB_RMI_WRREQ_CREDITS_MASK 0x000003E0L 4673#define DB_FIFO_DEPTH1__MCC_DEPTH_MASK 0x0000FC00L 4674#define DB_FIFO_DEPTH1__QC_DEPTH_MASK 0x001F0000L 4675#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH_MASK 0x1FE00000L 4676//DB_FIFO_DEPTH2 4677#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH__SHIFT 0x0 4678#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH__SHIFT 0x8 4679#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH__SHIFT 0xf 4680#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH__SHIFT 0x19 4681#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH_MASK 0x000000FFL 4682#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH_MASK 0x00007F00L 4683#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH_MASK 0x01FF8000L 4684#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH_MASK 0xFE000000L 4685//DB_EXCEPTION_CONTROL 4686#define DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE__SHIFT 0x0 4687#define DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE__SHIFT 0x1 4688#define DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE__SHIFT 0x2 4689#define DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE_MASK 0x00000001L 4690#define DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE_MASK 0x00000002L 4691#define DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE_MASK 0x00000004L 4692//DB_RING_CONTROL 4693#define DB_RING_CONTROL__COUNTER_CONTROL__SHIFT 0x0 4694#define DB_RING_CONTROL__COUNTER_CONTROL_MASK 0x00000003L 4695//DB_MEM_ARB_WATERMARKS 4696#define DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK__SHIFT 0x0 4697#define DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK__SHIFT 0x8 4698#define DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK__SHIFT 0x10 4699#define DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK__SHIFT 0x18 4700#define DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK_MASK 0x00000007L 4701#define DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK_MASK 0x00000700L 4702#define DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK_MASK 0x00070000L 4703#define DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK_MASK 0x07000000L 4704//DB_RMI_CACHE_POLICY 4705#define DB_RMI_CACHE_POLICY__Z_RD__SHIFT 0x0 4706#define DB_RMI_CACHE_POLICY__S_RD__SHIFT 0x1 4707#define DB_RMI_CACHE_POLICY__HTILE_RD__SHIFT 0x2 4708#define DB_RMI_CACHE_POLICY__Z_WR__SHIFT 0x8 4709#define DB_RMI_CACHE_POLICY__S_WR__SHIFT 0x9 4710#define DB_RMI_CACHE_POLICY__HTILE_WR__SHIFT 0xa 4711#define DB_RMI_CACHE_POLICY__ZPCPSD_WR__SHIFT 0xb 4712#define DB_RMI_CACHE_POLICY__CC_RD__SHIFT 0x10 4713#define DB_RMI_CACHE_POLICY__FMASK_RD__SHIFT 0x11 4714#define DB_RMI_CACHE_POLICY__CMASK_RD__SHIFT 0x12 4715#define DB_RMI_CACHE_POLICY__DCC_RD__SHIFT 0x13 4716#define DB_RMI_CACHE_POLICY__CC_WR__SHIFT 0x18 4717#define DB_RMI_CACHE_POLICY__FMASK_WR__SHIFT 0x19 4718#define DB_RMI_CACHE_POLICY__CMASK_WR__SHIFT 0x1a 4719#define DB_RMI_CACHE_POLICY__DCC_WR__SHIFT 0x1b 4720#define DB_RMI_CACHE_POLICY__Z_RD_MASK 0x00000001L 4721#define DB_RMI_CACHE_POLICY__S_RD_MASK 0x00000002L 4722#define DB_RMI_CACHE_POLICY__HTILE_RD_MASK 0x00000004L 4723#define DB_RMI_CACHE_POLICY__Z_WR_MASK 0x00000100L 4724#define DB_RMI_CACHE_POLICY__S_WR_MASK 0x00000200L 4725#define DB_RMI_CACHE_POLICY__HTILE_WR_MASK 0x00000400L 4726#define DB_RMI_CACHE_POLICY__ZPCPSD_WR_MASK 0x00000800L 4727#define DB_RMI_CACHE_POLICY__CC_RD_MASK 0x00010000L 4728#define DB_RMI_CACHE_POLICY__FMASK_RD_MASK 0x00020000L 4729#define DB_RMI_CACHE_POLICY__CMASK_RD_MASK 0x00040000L 4730#define DB_RMI_CACHE_POLICY__DCC_RD_MASK 0x00080000L 4731#define DB_RMI_CACHE_POLICY__CC_WR_MASK 0x01000000L 4732#define DB_RMI_CACHE_POLICY__FMASK_WR_MASK 0x02000000L 4733#define DB_RMI_CACHE_POLICY__CMASK_WR_MASK 0x04000000L 4734#define DB_RMI_CACHE_POLICY__DCC_WR_MASK 0x08000000L 4735//DB_DFSM_CONFIG 4736#define DB_DFSM_CONFIG__BYPASS_DFSM__SHIFT 0x0 4737#define DB_DFSM_CONFIG__DISABLE_PUNCHOUT__SHIFT 0x1 4738#define DB_DFSM_CONFIG__DISABLE_POPS__SHIFT 0x2 4739#define DB_DFSM_CONFIG__FORCE_FLUSH__SHIFT 0x3 4740#define DB_DFSM_CONFIG__MIDDLE_PIPE_MAX_DEPTH__SHIFT 0x8 4741#define DB_DFSM_CONFIG__BYPASS_DFSM_MASK 0x00000001L 4742#define DB_DFSM_CONFIG__DISABLE_PUNCHOUT_MASK 0x00000002L 4743#define DB_DFSM_CONFIG__DISABLE_POPS_MASK 0x00000004L 4744#define DB_DFSM_CONFIG__FORCE_FLUSH_MASK 0x00000008L 4745#define DB_DFSM_CONFIG__MIDDLE_PIPE_MAX_DEPTH_MASK 0x00007F00L 4746//DB_DFSM_WATERMARK 4747#define DB_DFSM_WATERMARK__DFSM_HIGH_WATERMARK__SHIFT 0x0 4748#define DB_DFSM_WATERMARK__POPS_HIGH_WATERMARK__SHIFT 0x10 4749#define DB_DFSM_WATERMARK__DFSM_HIGH_WATERMARK_MASK 0x0000FFFFL 4750#define DB_DFSM_WATERMARK__POPS_HIGH_WATERMARK_MASK 0xFFFF0000L 4751//DB_DFSM_TILES_IN_FLIGHT 4752#define DB_DFSM_TILES_IN_FLIGHT__HIGH_WATERMARK__SHIFT 0x0 4753#define DB_DFSM_TILES_IN_FLIGHT__HARD_LIMIT__SHIFT 0x10 4754#define DB_DFSM_TILES_IN_FLIGHT__HIGH_WATERMARK_MASK 0x0000FFFFL 4755#define DB_DFSM_TILES_IN_FLIGHT__HARD_LIMIT_MASK 0xFFFF0000L 4756//DB_DFSM_PRIMS_IN_FLIGHT 4757#define DB_DFSM_PRIMS_IN_FLIGHT__HIGH_WATERMARK__SHIFT 0x0 4758#define DB_DFSM_PRIMS_IN_FLIGHT__HARD_LIMIT__SHIFT 0x10 4759#define DB_DFSM_PRIMS_IN_FLIGHT__HIGH_WATERMARK_MASK 0x0000FFFFL 4760#define DB_DFSM_PRIMS_IN_FLIGHT__HARD_LIMIT_MASK 0xFFFF0000L 4761//DB_DFSM_WATCHDOG 4762#define DB_DFSM_WATCHDOG__TIMER_TARGET__SHIFT 0x0 4763#define DB_DFSM_WATCHDOG__TIMER_TARGET_MASK 0xFFFFFFFFL 4764//DB_DFSM_FLUSH_ENABLE 4765#define DB_DFSM_FLUSH_ENABLE__PRIMARY_EVENTS__SHIFT 0x0 4766#define DB_DFSM_FLUSH_ENABLE__AUX_FORCE_PASSTHRU__SHIFT 0x18 4767#define DB_DFSM_FLUSH_ENABLE__AUX_EVENTS__SHIFT 0x1c 4768#define DB_DFSM_FLUSH_ENABLE__PRIMARY_EVENTS_MASK 0x000003FFL 4769#define DB_DFSM_FLUSH_ENABLE__AUX_FORCE_PASSTHRU_MASK 0x0F000000L 4770#define DB_DFSM_FLUSH_ENABLE__AUX_EVENTS_MASK 0xF0000000L 4771//DB_DFSM_FLUSH_AUX_EVENT 4772#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_A__SHIFT 0x0 4773#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_B__SHIFT 0x8 4774#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_C__SHIFT 0x10 4775#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_D__SHIFT 0x18 4776#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_A_MASK 0x000000FFL 4777#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_B_MASK 0x0000FF00L 4778#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_C_MASK 0x00FF0000L 4779#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_D_MASK 0xFF000000L 4780//CC_RB_REDUNDANCY 4781#define CC_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8 4782#define CC_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc 4783#define CC_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10 4784#define CC_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14 4785#define CC_RB_REDUNDANCY__FAILED_RB0_MASK 0x00000F00L 4786#define CC_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x00001000L 4787#define CC_RB_REDUNDANCY__FAILED_RB1_MASK 0x000F0000L 4788#define CC_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x00100000L 4789//CC_RB_BACKEND_DISABLE 4790#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10 4791#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00FF0000L 4792//GB_ADDR_CONFIG 4793#define GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 4794#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 4795#define GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6 4796#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 4797#define GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 4798#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 4799#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 4800#define GB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x15 4801#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 4802#define GB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a 4803#define GB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 4804#define GB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 4805#define GB_ADDR_CONFIG__SE_ENABLE__SHIFT 0x1f 4806#define GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 4807#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 4808#define GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L 4809#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 4810#define GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 4811#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L 4812#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 4813#define GB_ADDR_CONFIG__NUM_GPUS_MASK 0x00E00000L 4814#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L 4815#define GB_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L 4816#define GB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L 4817#define GB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L 4818#define GB_ADDR_CONFIG__SE_ENABLE_MASK 0x80000000L 4819//GB_BACKEND_MAP 4820#define GB_BACKEND_MAP__BACKEND_MAP__SHIFT 0x0 4821#define GB_BACKEND_MAP__BACKEND_MAP_MASK 0xFFFFFFFFL 4822//GB_GPU_ID 4823#define GB_GPU_ID__GPU_ID__SHIFT 0x0 4824#define GB_GPU_ID__GPU_ID_MASK 0x0000000FL 4825//CC_RB_DAISY_CHAIN 4826#define CC_RB_DAISY_CHAIN__RB_0__SHIFT 0x0 4827#define CC_RB_DAISY_CHAIN__RB_1__SHIFT 0x4 4828#define CC_RB_DAISY_CHAIN__RB_2__SHIFT 0x8 4829#define CC_RB_DAISY_CHAIN__RB_3__SHIFT 0xc 4830#define CC_RB_DAISY_CHAIN__RB_4__SHIFT 0x10 4831#define CC_RB_DAISY_CHAIN__RB_5__SHIFT 0x14 4832#define CC_RB_DAISY_CHAIN__RB_6__SHIFT 0x18 4833#define CC_RB_DAISY_CHAIN__RB_7__SHIFT 0x1c 4834#define CC_RB_DAISY_CHAIN__RB_0_MASK 0x0000000FL 4835#define CC_RB_DAISY_CHAIN__RB_1_MASK 0x000000F0L 4836#define CC_RB_DAISY_CHAIN__RB_2_MASK 0x00000F00L 4837#define CC_RB_DAISY_CHAIN__RB_3_MASK 0x0000F000L 4838#define CC_RB_DAISY_CHAIN__RB_4_MASK 0x000F0000L 4839#define CC_RB_DAISY_CHAIN__RB_5_MASK 0x00F00000L 4840#define CC_RB_DAISY_CHAIN__RB_6_MASK 0x0F000000L 4841#define CC_RB_DAISY_CHAIN__RB_7_MASK 0xF0000000L 4842//GB_ADDR_CONFIG_READ 4843#define GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 4844#define GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 4845#define GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT 0x6 4846#define GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 4847#define GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc 4848#define GB_ADDR_CONFIG_READ__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 4849#define GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 4850#define GB_ADDR_CONFIG_READ__NUM_GPUS__SHIFT 0x15 4851#define GB_ADDR_CONFIG_READ__MULTI_GPU_TILE_SIZE__SHIFT 0x18 4852#define GB_ADDR_CONFIG_READ__NUM_RB_PER_SE__SHIFT 0x1a 4853#define GB_ADDR_CONFIG_READ__ROW_SIZE__SHIFT 0x1c 4854#define GB_ADDR_CONFIG_READ__NUM_LOWER_PIPES__SHIFT 0x1e 4855#define GB_ADDR_CONFIG_READ__SE_ENABLE__SHIFT 0x1f 4856#define GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L 4857#define GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 4858#define GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L 4859#define GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 4860#define GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L 4861#define GB_ADDR_CONFIG_READ__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L 4862#define GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L 4863#define GB_ADDR_CONFIG_READ__NUM_GPUS_MASK 0x00E00000L 4864#define GB_ADDR_CONFIG_READ__MULTI_GPU_TILE_SIZE_MASK 0x03000000L 4865#define GB_ADDR_CONFIG_READ__NUM_RB_PER_SE_MASK 0x0C000000L 4866#define GB_ADDR_CONFIG_READ__ROW_SIZE_MASK 0x30000000L 4867#define GB_ADDR_CONFIG_READ__NUM_LOWER_PIPES_MASK 0x40000000L 4868#define GB_ADDR_CONFIG_READ__SE_ENABLE_MASK 0x80000000L 4869//GB_TILE_MODE0 4870#define GB_TILE_MODE0__ARRAY_MODE__SHIFT 0x2 4871#define GB_TILE_MODE0__PIPE_CONFIG__SHIFT 0x6 4872#define GB_TILE_MODE0__TILE_SPLIT__SHIFT 0xb 4873#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT 0x16 4874#define GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT 0x19 4875#define GB_TILE_MODE0__ARRAY_MODE_MASK 0x0000003CL 4876#define GB_TILE_MODE0__PIPE_CONFIG_MASK 0x000007C0L 4877#define GB_TILE_MODE0__TILE_SPLIT_MASK 0x00003800L 4878#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW_MASK 0x01C00000L 4879#define GB_TILE_MODE0__SAMPLE_SPLIT_MASK 0x06000000L 4880//GB_TILE_MODE1 4881#define GB_TILE_MODE1__ARRAY_MODE__SHIFT 0x2 4882#define GB_TILE_MODE1__PIPE_CONFIG__SHIFT 0x6 4883#define GB_TILE_MODE1__TILE_SPLIT__SHIFT 0xb 4884#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW__SHIFT 0x16 4885#define GB_TILE_MODE1__SAMPLE_SPLIT__SHIFT 0x19 4886#define GB_TILE_MODE1__ARRAY_MODE_MASK 0x0000003CL 4887#define GB_TILE_MODE1__PIPE_CONFIG_MASK 0x000007C0L 4888#define GB_TILE_MODE1__TILE_SPLIT_MASK 0x00003800L 4889#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW_MASK 0x01C00000L 4890#define GB_TILE_MODE1__SAMPLE_SPLIT_MASK 0x06000000L 4891//GB_TILE_MODE2 4892#define GB_TILE_MODE2__ARRAY_MODE__SHIFT 0x2 4893#define GB_TILE_MODE2__PIPE_CONFIG__SHIFT 0x6 4894#define GB_TILE_MODE2__TILE_SPLIT__SHIFT 0xb 4895#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW__SHIFT 0x16 4896#define GB_TILE_MODE2__SAMPLE_SPLIT__SHIFT 0x19 4897#define GB_TILE_MODE2__ARRAY_MODE_MASK 0x0000003CL 4898#define GB_TILE_MODE2__PIPE_CONFIG_MASK 0x000007C0L 4899#define GB_TILE_MODE2__TILE_SPLIT_MASK 0x00003800L 4900#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW_MASK 0x01C00000L 4901#define GB_TILE_MODE2__SAMPLE_SPLIT_MASK 0x06000000L 4902//GB_TILE_MODE3 4903#define GB_TILE_MODE3__ARRAY_MODE__SHIFT 0x2 4904#define GB_TILE_MODE3__PIPE_CONFIG__SHIFT 0x6 4905#define GB_TILE_MODE3__TILE_SPLIT__SHIFT 0xb 4906#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW__SHIFT 0x16 4907#define GB_TILE_MODE3__SAMPLE_SPLIT__SHIFT 0x19 4908#define GB_TILE_MODE3__ARRAY_MODE_MASK 0x0000003CL 4909#define GB_TILE_MODE3__PIPE_CONFIG_MASK 0x000007C0L 4910#define GB_TILE_MODE3__TILE_SPLIT_MASK 0x00003800L 4911#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW_MASK 0x01C00000L 4912#define GB_TILE_MODE3__SAMPLE_SPLIT_MASK 0x06000000L 4913//GB_TILE_MODE4 4914#define GB_TILE_MODE4__ARRAY_MODE__SHIFT 0x2 4915#define GB_TILE_MODE4__PIPE_CONFIG__SHIFT 0x6 4916#define GB_TILE_MODE4__TILE_SPLIT__SHIFT 0xb 4917#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW__SHIFT 0x16 4918#define GB_TILE_MODE4__SAMPLE_SPLIT__SHIFT 0x19 4919#define GB_TILE_MODE4__ARRAY_MODE_MASK 0x0000003CL 4920#define GB_TILE_MODE4__PIPE_CONFIG_MASK 0x000007C0L 4921#define GB_TILE_MODE4__TILE_SPLIT_MASK 0x00003800L 4922#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW_MASK 0x01C00000L 4923#define GB_TILE_MODE4__SAMPLE_SPLIT_MASK 0x06000000L 4924//GB_TILE_MODE5 4925#define GB_TILE_MODE5__ARRAY_MODE__SHIFT 0x2 4926#define GB_TILE_MODE5__PIPE_CONFIG__SHIFT 0x6 4927#define GB_TILE_MODE5__TILE_SPLIT__SHIFT 0xb 4928#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW__SHIFT 0x16 4929#define GB_TILE_MODE5__SAMPLE_SPLIT__SHIFT 0x19 4930#define GB_TILE_MODE5__ARRAY_MODE_MASK 0x0000003CL 4931#define GB_TILE_MODE5__PIPE_CONFIG_MASK 0x000007C0L 4932#define GB_TILE_MODE5__TILE_SPLIT_MASK 0x00003800L 4933#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW_MASK 0x01C00000L 4934#define GB_TILE_MODE5__SAMPLE_SPLIT_MASK 0x06000000L 4935//GB_TILE_MODE6 4936#define GB_TILE_MODE6__ARRAY_MODE__SHIFT 0x2 4937#define GB_TILE_MODE6__PIPE_CONFIG__SHIFT 0x6 4938#define GB_TILE_MODE6__TILE_SPLIT__SHIFT 0xb 4939#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW__SHIFT 0x16 4940#define GB_TILE_MODE6__SAMPLE_SPLIT__SHIFT 0x19 4941#define GB_TILE_MODE6__ARRAY_MODE_MASK 0x0000003CL 4942#define GB_TILE_MODE6__PIPE_CONFIG_MASK 0x000007C0L 4943#define GB_TILE_MODE6__TILE_SPLIT_MASK 0x00003800L 4944#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW_MASK 0x01C00000L 4945#define GB_TILE_MODE6__SAMPLE_SPLIT_MASK 0x06000000L 4946//GB_TILE_MODE7 4947#define GB_TILE_MODE7__ARRAY_MODE__SHIFT 0x2 4948#define GB_TILE_MODE7__PIPE_CONFIG__SHIFT 0x6 4949#define GB_TILE_MODE7__TILE_SPLIT__SHIFT 0xb 4950#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW__SHIFT 0x16 4951#define GB_TILE_MODE7__SAMPLE_SPLIT__SHIFT 0x19 4952#define GB_TILE_MODE7__ARRAY_MODE_MASK 0x0000003CL 4953#define GB_TILE_MODE7__PIPE_CONFIG_MASK 0x000007C0L 4954#define GB_TILE_MODE7__TILE_SPLIT_MASK 0x00003800L 4955#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW_MASK 0x01C00000L 4956#define GB_TILE_MODE7__SAMPLE_SPLIT_MASK 0x06000000L 4957//GB_TILE_MODE8 4958#define GB_TILE_MODE8__ARRAY_MODE__SHIFT 0x2 4959#define GB_TILE_MODE8__PIPE_CONFIG__SHIFT 0x6 4960#define GB_TILE_MODE8__TILE_SPLIT__SHIFT 0xb 4961#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW__SHIFT 0x16 4962#define GB_TILE_MODE8__SAMPLE_SPLIT__SHIFT 0x19 4963#define GB_TILE_MODE8__ARRAY_MODE_MASK 0x0000003CL 4964#define GB_TILE_MODE8__PIPE_CONFIG_MASK 0x000007C0L 4965#define GB_TILE_MODE8__TILE_SPLIT_MASK 0x00003800L 4966#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW_MASK 0x01C00000L 4967#define GB_TILE_MODE8__SAMPLE_SPLIT_MASK 0x06000000L 4968//GB_TILE_MODE9 4969#define GB_TILE_MODE9__ARRAY_MODE__SHIFT 0x2 4970#define GB_TILE_MODE9__PIPE_CONFIG__SHIFT 0x6 4971#define GB_TILE_MODE9__TILE_SPLIT__SHIFT 0xb 4972#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW__SHIFT 0x16 4973#define GB_TILE_MODE9__SAMPLE_SPLIT__SHIFT 0x19 4974#define GB_TILE_MODE9__ARRAY_MODE_MASK 0x0000003CL 4975#define GB_TILE_MODE9__PIPE_CONFIG_MASK 0x000007C0L 4976#define GB_TILE_MODE9__TILE_SPLIT_MASK 0x00003800L 4977#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW_MASK 0x01C00000L 4978#define GB_TILE_MODE9__SAMPLE_SPLIT_MASK 0x06000000L 4979//GB_TILE_MODE10 4980#define GB_TILE_MODE10__ARRAY_MODE__SHIFT 0x2 4981#define GB_TILE_MODE10__PIPE_CONFIG__SHIFT 0x6 4982#define GB_TILE_MODE10__TILE_SPLIT__SHIFT 0xb 4983#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW__SHIFT 0x16 4984#define GB_TILE_MODE10__SAMPLE_SPLIT__SHIFT 0x19 4985#define GB_TILE_MODE10__ARRAY_MODE_MASK 0x0000003CL 4986#define GB_TILE_MODE10__PIPE_CONFIG_MASK 0x000007C0L 4987#define GB_TILE_MODE10__TILE_SPLIT_MASK 0x00003800L 4988#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW_MASK 0x01C00000L 4989#define GB_TILE_MODE10__SAMPLE_SPLIT_MASK 0x06000000L 4990//GB_TILE_MODE11 4991#define GB_TILE_MODE11__ARRAY_MODE__SHIFT 0x2 4992#define GB_TILE_MODE11__PIPE_CONFIG__SHIFT 0x6 4993#define GB_TILE_MODE11__TILE_SPLIT__SHIFT 0xb 4994#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW__SHIFT 0x16 4995#define GB_TILE_MODE11__SAMPLE_SPLIT__SHIFT 0x19 4996#define GB_TILE_MODE11__ARRAY_MODE_MASK 0x0000003CL 4997#define GB_TILE_MODE11__PIPE_CONFIG_MASK 0x000007C0L 4998#define GB_TILE_MODE11__TILE_SPLIT_MASK 0x00003800L 4999#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW_MASK 0x01C00000L 5000#define GB_TILE_MODE11__SAMPLE_SPLIT_MASK 0x06000000L
5001//GB_TILE_MODE12 5002#define GB_TILE_MODE12__ARRAY_MODE__SHIFT 0x2 5003#define GB_TILE_MODE12__PIPE_CONFIG__SHIFT 0x6 5004#define GB_TILE_MODE12__TILE_SPLIT__SHIFT 0xb 5005#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW__SHIFT 0x16 5006#define GB_TILE_MODE12__SAMPLE_SPLIT__SHIFT 0x19 5007#define GB_TILE_MODE12__ARRAY_MODE_MASK 0x0000003CL 5008#define GB_TILE_MODE12__PIPE_CONFIG_MASK 0x000007C0L 5009#define GB_TILE_MODE12__TILE_SPLIT_MASK 0x00003800L 5010#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW_MASK 0x01C00000L 5011#define GB_TILE_MODE12__SAMPLE_SPLIT_MASK 0x06000000L 5012//GB_TILE_MODE13 5013#define GB_TILE_MODE13__ARRAY_MODE__SHIFT 0x2 5014#define GB_TILE_MODE13__PIPE_CONFIG__SHIFT 0x6 5015#define GB_TILE_MODE13__TILE_SPLIT__SHIFT 0xb 5016#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW__SHIFT 0x16 5017#define GB_TILE_MODE13__SAMPLE_SPLIT__SHIFT 0x19 5018#define GB_TILE_MODE13__ARRAY_MODE_MASK 0x0000003CL 5019#define GB_TILE_MODE13__PIPE_CONFIG_MASK 0x000007C0L 5020#define GB_TILE_MODE13__TILE_SPLIT_MASK 0x00003800L 5021#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW_MASK 0x01C00000L 5022#define GB_TILE_MODE13__SAMPLE_SPLIT_MASK 0x06000000L 5023//GB_TILE_MODE14 5024#define GB_TILE_MODE14__ARRAY_MODE__SHIFT 0x2 5025#define GB_TILE_MODE14__PIPE_CONFIG__SHIFT 0x6 5026#define GB_TILE_MODE14__TILE_SPLIT__SHIFT 0xb 5027#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW__SHIFT 0x16 5028#define GB_TILE_MODE14__SAMPLE_SPLIT__SHIFT 0x19 5029#define GB_TILE_MODE14__ARRAY_MODE_MASK 0x0000003CL 5030#define GB_TILE_MODE14__PIPE_CONFIG_MASK 0x000007C0L 5031#define GB_TILE_MODE14__TILE_SPLIT_MASK 0x00003800L 5032#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW_MASK 0x01C00000L 5033#define GB_TILE_MODE14__SAMPLE_SPLIT_MASK 0x06000000L 5034//GB_TILE_MODE15 5035#define GB_TILE_MODE15__ARRAY_MODE__SHIFT 0x2 5036#define GB_TILE_MODE15__PIPE_CONFIG__SHIFT 0x6 5037#define GB_TILE_MODE15__TILE_SPLIT__SHIFT 0xb 5038#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW__SHIFT 0x16 5039#define GB_TILE_MODE15__SAMPLE_SPLIT__SHIFT 0x19 5040#define GB_TILE_MODE15__ARRAY_MODE_MASK 0x0000003CL 5041#define GB_TILE_MODE15__PIPE_CONFIG_MASK 0x000007C0L 5042#define GB_TILE_MODE15__TILE_SPLIT_MASK 0x00003800L 5043#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW_MASK 0x01C00000L 5044#define GB_TILE_MODE15__SAMPLE_SPLIT_MASK 0x06000000L 5045//GB_TILE_MODE16 5046#define GB_TILE_MODE16__ARRAY_MODE__SHIFT 0x2 5047#define GB_TILE_MODE16__PIPE_CONFIG__SHIFT 0x6 5048#define GB_TILE_MODE16__TILE_SPLIT__SHIFT 0xb 5049#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW__SHIFT 0x16 5050#define GB_TILE_MODE16__SAMPLE_SPLIT__SHIFT 0x19 5051#define GB_TILE_MODE16__ARRAY_MODE_MASK 0x0000003CL 5052#define GB_TILE_MODE16__PIPE_CONFIG_MASK 0x000007C0L 5053#define GB_TILE_MODE16__TILE_SPLIT_MASK 0x00003800L 5054#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW_MASK 0x01C00000L 5055#define GB_TILE_MODE16__SAMPLE_SPLIT_MASK 0x06000000L 5056//GB_TILE_MODE17 5057#define GB_TILE_MODE17__ARRAY_MODE__SHIFT 0x2 5058#define GB_TILE_MODE17__PIPE_CONFIG__SHIFT 0x6 5059#define GB_TILE_MODE17__TILE_SPLIT__SHIFT 0xb 5060#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW__SHIFT 0x16 5061#define GB_TILE_MODE17__SAMPLE_SPLIT__SHIFT 0x19 5062#define GB_TILE_MODE17__ARRAY_MODE_MASK 0x0000003CL 5063#define GB_TILE_MODE17__PIPE_CONFIG_MASK 0x000007C0L 5064#define GB_TILE_MODE17__TILE_SPLIT_MASK 0x00003800L 5065#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW_MASK 0x01C00000L 5066#define GB_TILE_MODE17__SAMPLE_SPLIT_MASK 0x06000000L 5067//GB_TILE_MODE18 5068#define GB_TILE_MODE18__ARRAY_MODE__SHIFT 0x2 5069#define GB_TILE_MODE18__PIPE_CONFIG__SHIFT 0x6 5070#define GB_TILE_MODE18__TILE_SPLIT__SHIFT 0xb 5071#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW__SHIFT 0x16 5072#define GB_TILE_MODE18__SAMPLE_SPLIT__SHIFT 0x19 5073#define GB_TILE_MODE18__ARRAY_MODE_MASK 0x0000003CL 5074#define GB_TILE_MODE18__PIPE_CONFIG_MASK 0x000007C0L 5075#define GB_TILE_MODE18__TILE_SPLIT_MASK 0x00003800L 5076#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW_MASK 0x01C00000L 5077#define GB_TILE_MODE18__SAMPLE_SPLIT_MASK 0x06000000L 5078//GB_TILE_MODE19 5079#define GB_TILE_MODE19__ARRAY_MODE__SHIFT 0x2 5080#define GB_TILE_MODE19__PIPE_CONFIG__SHIFT 0x6 5081#define GB_TILE_MODE19__TILE_SPLIT__SHIFT 0xb 5082#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW__SHIFT 0x16 5083#define GB_TILE_MODE19__SAMPLE_SPLIT__SHIFT 0x19 5084#define GB_TILE_MODE19__ARRAY_MODE_MASK 0x0000003CL 5085#define GB_TILE_MODE19__PIPE_CONFIG_MASK 0x000007C0L 5086#define GB_TILE_MODE19__TILE_SPLIT_MASK 0x00003800L 5087#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW_MASK 0x01C00000L 5088#define GB_TILE_MODE19__SAMPLE_SPLIT_MASK 0x06000000L 5089//GB_TILE_MODE20 5090#define GB_TILE_MODE20__ARRAY_MODE__SHIFT 0x2 5091#define GB_TILE_MODE20__PIPE_CONFIG__SHIFT 0x6 5092#define GB_TILE_MODE20__TILE_SPLIT__SHIFT 0xb 5093#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW__SHIFT 0x16 5094#define GB_TILE_MODE20__SAMPLE_SPLIT__SHIFT 0x19 5095#define GB_TILE_MODE20__ARRAY_MODE_MASK 0x0000003CL 5096#define GB_TILE_MODE20__PIPE_CONFIG_MASK 0x000007C0L 5097#define GB_TILE_MODE20__TILE_SPLIT_MASK 0x00003800L 5098#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW_MASK 0x01C00000L 5099#define GB_TILE_MODE20__SAMPLE_SPLIT_MASK 0x06000000L 5100//GB_TILE_MODE21 5101#define GB_TILE_MODE21__ARRAY_MODE__SHIFT 0x2 5102#define GB_TILE_MODE21__PIPE_CONFIG__SHIFT 0x6 5103#define GB_TILE_MODE21__TILE_SPLIT__SHIFT 0xb 5104#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW__SHIFT 0x16 5105#define GB_TILE_MODE21__SAMPLE_SPLIT__SHIFT 0x19 5106#define GB_TILE_MODE21__ARRAY_MODE_MASK 0x0000003CL 5107#define GB_TILE_MODE21__PIPE_CONFIG_MASK 0x000007C0L 5108#define GB_TILE_MODE21__TILE_SPLIT_MASK 0x00003800L 5109#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW_MASK 0x01C00000L 5110#define GB_TILE_MODE21__SAMPLE_SPLIT_MASK 0x06000000L 5111//GB_TILE_MODE22 5112#define GB_TILE_MODE22__ARRAY_MODE__SHIFT 0x2 5113#define GB_TILE_MODE22__PIPE_CONFIG__SHIFT 0x6 5114#define GB_TILE_MODE22__TILE_SPLIT__SHIFT 0xb 5115#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW__SHIFT 0x16 5116#define GB_TILE_MODE22__SAMPLE_SPLIT__SHIFT 0x19 5117#define GB_TILE_MODE22__ARRAY_MODE_MASK 0x0000003CL 5118#define GB_TILE_MODE22__PIPE_CONFIG_MASK 0x000007C0L 5119#define GB_TILE_MODE22__TILE_SPLIT_MASK 0x00003800L 5120#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW_MASK 0x01C00000L 5121#define GB_TILE_MODE22__SAMPLE_SPLIT_MASK 0x06000000L 5122//GB_TILE_MODE23 5123#define GB_TILE_MODE23__ARRAY_MODE__SHIFT 0x2 5124#define GB_TILE_MODE23__PIPE_CONFIG__SHIFT 0x6 5125#define GB_TILE_MODE23__TILE_SPLIT__SHIFT 0xb 5126#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW__SHIFT 0x16 5127#define GB_TILE_MODE23__SAMPLE_SPLIT__SHIFT 0x19 5128#define GB_TILE_MODE23__ARRAY_MODE_MASK 0x0000003CL 5129#define GB_TILE_MODE23__PIPE_CONFIG_MASK 0x000007C0L 5130#define GB_TILE_MODE23__TILE_SPLIT_MASK 0x00003800L 5131#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW_MASK 0x01C00000L 5132#define GB_TILE_MODE23__SAMPLE_SPLIT_MASK 0x06000000L 5133//GB_TILE_MODE24 5134#define GB_TILE_MODE24__ARRAY_MODE__SHIFT 0x2 5135#define GB_TILE_MODE24__PIPE_CONFIG__SHIFT 0x6 5136#define GB_TILE_MODE24__TILE_SPLIT__SHIFT 0xb 5137#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW__SHIFT 0x16 5138#define GB_TILE_MODE24__SAMPLE_SPLIT__SHIFT 0x19 5139#define GB_TILE_MODE24__ARRAY_MODE_MASK 0x0000003CL 5140#define GB_TILE_MODE24__PIPE_CONFIG_MASK 0x000007C0L 5141#define GB_TILE_MODE24__TILE_SPLIT_MASK 0x00003800L 5142#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW_MASK 0x01C00000L 5143#define GB_TILE_MODE24__SAMPLE_SPLIT_MASK 0x06000000L 5144//GB_TILE_MODE25 5145#define GB_TILE_MODE25__ARRAY_MODE__SHIFT 0x2 5146#define GB_TILE_MODE25__PIPE_CONFIG__SHIFT 0x6 5147#define GB_TILE_MODE25__TILE_SPLIT__SHIFT 0xb 5148#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW__SHIFT 0x16 5149#define GB_TILE_MODE25__SAMPLE_SPLIT__SHIFT 0x19 5150#define GB_TILE_MODE25__ARRAY_MODE_MASK 0x0000003CL 5151#define GB_TILE_MODE25__PIPE_CONFIG_MASK 0x000007C0L 5152#define GB_TILE_MODE25__TILE_SPLIT_MASK 0x00003800L 5153#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW_MASK 0x01C00000L 5154#define GB_TILE_MODE25__SAMPLE_SPLIT_MASK 0x06000000L 5155//GB_TILE_MODE26 5156#define GB_TILE_MODE26__ARRAY_MODE__SHIFT 0x2 5157#define GB_TILE_MODE26__PIPE_CONFIG__SHIFT 0x6 5158#define GB_TILE_MODE26__TILE_SPLIT__SHIFT 0xb 5159#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW__SHIFT 0x16 5160#define GB_TILE_MODE26__SAMPLE_SPLIT__SHIFT 0x19 5161#define GB_TILE_MODE26__ARRAY_MODE_MASK 0x0000003CL 5162#define GB_TILE_MODE26__PIPE_CONFIG_MASK 0x000007C0L 5163#define GB_TILE_MODE26__TILE_SPLIT_MASK 0x00003800L 5164#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW_MASK 0x01C00000L 5165#define GB_TILE_MODE26__SAMPLE_SPLIT_MASK 0x06000000L 5166//GB_TILE_MODE27 5167#define GB_TILE_MODE27__ARRAY_MODE__SHIFT 0x2 5168#define GB_TILE_MODE27__PIPE_CONFIG__SHIFT 0x6 5169#define GB_TILE_MODE27__TILE_SPLIT__SHIFT 0xb 5170#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW__SHIFT 0x16 5171#define GB_TILE_MODE27__SAMPLE_SPLIT__SHIFT 0x19 5172#define GB_TILE_MODE27__ARRAY_MODE_MASK 0x0000003CL 5173#define GB_TILE_MODE27__PIPE_CONFIG_MASK 0x000007C0L 5174#define GB_TILE_MODE27__TILE_SPLIT_MASK 0x00003800L 5175#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW_MASK 0x01C00000L 5176#define GB_TILE_MODE27__SAMPLE_SPLIT_MASK 0x06000000L 5177//GB_TILE_MODE28 5178#define GB_TILE_MODE28__ARRAY_MODE__SHIFT 0x2 5179#define GB_TILE_MODE28__PIPE_CONFIG__SHIFT 0x6 5180#define GB_TILE_MODE28__TILE_SPLIT__SHIFT 0xb 5181#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW__SHIFT 0x16 5182#define GB_TILE_MODE28__SAMPLE_SPLIT__SHIFT 0x19 5183#define GB_TILE_MODE28__ARRAY_MODE_MASK 0x0000003CL 5184#define GB_TILE_MODE28__PIPE_CONFIG_MASK 0x000007C0L 5185#define GB_TILE_MODE28__TILE_SPLIT_MASK 0x00003800L 5186#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW_MASK 0x01C00000L 5187#define GB_TILE_MODE28__SAMPLE_SPLIT_MASK 0x06000000L 5188//GB_TILE_MODE29 5189#define GB_TILE_MODE29__ARRAY_MODE__SHIFT 0x2 5190#define GB_TILE_MODE29__PIPE_CONFIG__SHIFT 0x6 5191#define GB_TILE_MODE29__TILE_SPLIT__SHIFT 0xb 5192#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW__SHIFT 0x16 5193#define GB_TILE_MODE29__SAMPLE_SPLIT__SHIFT 0x19 5194#define GB_TILE_MODE29__ARRAY_MODE_MASK 0x0000003CL 5195#define GB_TILE_MODE29__PIPE_CONFIG_MASK 0x000007C0L 5196#define GB_TILE_MODE29__TILE_SPLIT_MASK 0x00003800L 5197#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW_MASK 0x01C00000L 5198#define GB_TILE_MODE29__SAMPLE_SPLIT_MASK 0x06000000L 5199//GB_TILE_MODE30 5200#define GB_TILE_MODE30__ARRAY_MODE__SHIFT 0x2 5201#define GB_TILE_MODE30__PIPE_CONFIG__SHIFT 0x6 5202#define GB_TILE_MODE30__TILE_SPLIT__SHIFT 0xb 5203#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW__SHIFT 0x16 5204#define GB_TILE_MODE30__SAMPLE_SPLIT__SHIFT 0x19 5205#define GB_TILE_MODE30__ARRAY_MODE_MASK 0x0000003CL 5206#define GB_TILE_MODE30__PIPE_CONFIG_MASK 0x000007C0L 5207#define GB_TILE_MODE30__TILE_SPLIT_MASK 0x00003800L 5208#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW_MASK 0x01C00000L 5209#define GB_TILE_MODE30__SAMPLE_SPLIT_MASK 0x06000000L 5210//GB_TILE_MODE31 5211#define GB_TILE_MODE31__ARRAY_MODE__SHIFT 0x2 5212#define GB_TILE_MODE31__PIPE_CONFIG__SHIFT 0x6 5213#define GB_TILE_MODE31__TILE_SPLIT__SHIFT 0xb 5214#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW__SHIFT 0x16 5215#define GB_TILE_MODE31__SAMPLE_SPLIT__SHIFT 0x19 5216#define GB_TILE_MODE31__ARRAY_MODE_MASK 0x0000003CL 5217#define GB_TILE_MODE31__PIPE_CONFIG_MASK 0x000007C0L 5218#define GB_TILE_MODE31__TILE_SPLIT_MASK 0x00003800L 5219#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW_MASK 0x01C00000L 5220#define GB_TILE_MODE31__SAMPLE_SPLIT_MASK 0x06000000L 5221//GB_MACROTILE_MODE0 5222#define GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT 0x0 5223#define GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT 0x2 5224#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT 0x4 5225#define GB_MACROTILE_MODE0__NUM_BANKS__SHIFT 0x6 5226#define GB_MACROTILE_MODE0__BANK_WIDTH_MASK 0x00000003L 5227#define GB_MACROTILE_MODE0__BANK_HEIGHT_MASK 0x0000000CL 5228#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT_MASK 0x00000030L 5229#define GB_MACROTILE_MODE0__NUM_BANKS_MASK 0x000000C0L 5230//GB_MACROTILE_MODE1 5231#define GB_MACROTILE_MODE1__BANK_WIDTH__SHIFT 0x0 5232#define GB_MACROTILE_MODE1__BANK_HEIGHT__SHIFT 0x2 5233#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT__SHIFT 0x4 5234#define GB_MACROTILE_MODE1__NUM_BANKS__SHIFT 0x6 5235#define GB_MACROTILE_MODE1__BANK_WIDTH_MASK 0x00000003L 5236#define GB_MACROTILE_MODE1__BANK_HEIGHT_MASK 0x0000000CL 5237#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT_MASK 0x00000030L 5238#define GB_MACROTILE_MODE1__NUM_BANKS_MASK 0x000000C0L 5239//GB_MACROTILE_MODE2 5240#define GB_MACROTILE_MODE2__BANK_WIDTH__SHIFT 0x0 5241#define GB_MACROTILE_MODE2__BANK_HEIGHT__SHIFT 0x2 5242#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT__SHIFT 0x4 5243#define GB_MACROTILE_MODE2__NUM_BANKS__SHIFT 0x6 5244#define GB_MACROTILE_MODE2__BANK_WIDTH_MASK 0x00000003L 5245#define GB_MACROTILE_MODE2__BANK_HEIGHT_MASK 0x0000000CL 5246#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT_MASK 0x00000030L 5247#define GB_MACROTILE_MODE2__NUM_BANKS_MASK 0x000000C0L 5248//GB_MACROTILE_MODE3 5249#define GB_MACROTILE_MODE3__BANK_WIDTH__SHIFT 0x0 5250#define GB_MACROTILE_MODE3__BANK_HEIGHT__SHIFT 0x2 5251#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT__SHIFT 0x4 5252#define GB_MACROTILE_MODE3__NUM_BANKS__SHIFT 0x6 5253#define GB_MACROTILE_MODE3__BANK_WIDTH_MASK 0x00000003L 5254#define GB_MACROTILE_MODE3__BANK_HEIGHT_MASK 0x0000000CL 5255#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT_MASK 0x00000030L 5256#define GB_MACROTILE_MODE3__NUM_BANKS_MASK 0x000000C0L 5257//GB_MACROTILE_MODE4 5258#define GB_MACROTILE_MODE4__BANK_WIDTH__SHIFT 0x0 5259#define GB_MACROTILE_MODE4__BANK_HEIGHT__SHIFT 0x2 5260#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT__SHIFT 0x4 5261#define GB_MACROTILE_MODE4__NUM_BANKS__SHIFT 0x6 5262#define GB_MACROTILE_MODE4__BANK_WIDTH_MASK 0x00000003L 5263#define GB_MACROTILE_MODE4__BANK_HEIGHT_MASK 0x0000000CL 5264#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT_MASK 0x00000030L 5265#define GB_MACROTILE_MODE4__NUM_BANKS_MASK 0x000000C0L 5266//GB_MACROTILE_MODE5 5267#define GB_MACROTILE_MODE5__BANK_WIDTH__SHIFT 0x0 5268#define GB_MACROTILE_MODE5__BANK_HEIGHT__SHIFT 0x2 5269#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT__SHIFT 0x4 5270#define GB_MACROTILE_MODE5__NUM_BANKS__SHIFT 0x6 5271#define GB_MACROTILE_MODE5__BANK_WIDTH_MASK 0x00000003L 5272#define GB_MACROTILE_MODE5__BANK_HEIGHT_MASK 0x0000000CL 5273#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT_MASK 0x00000030L 5274#define GB_MACROTILE_MODE5__NUM_BANKS_MASK 0x000000C0L 5275//GB_MACROTILE_MODE6 5276#define GB_MACROTILE_MODE6__BANK_WIDTH__SHIFT 0x0 5277#define GB_MACROTILE_MODE6__BANK_HEIGHT__SHIFT 0x2 5278#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT__SHIFT 0x4 5279#define GB_MACROTILE_MODE6__NUM_BANKS__SHIFT 0x6 5280#define GB_MACROTILE_MODE6__BANK_WIDTH_MASK 0x00000003L 5281#define GB_MACROTILE_MODE6__BANK_HEIGHT_MASK 0x0000000CL 5282#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT_MASK 0x00000030L 5283#define GB_MACROTILE_MODE6__NUM_BANKS_MASK 0x000000C0L 5284//GB_MACROTILE_MODE7 5285#define GB_MACROTILE_MODE7__BANK_WIDTH__SHIFT 0x0 5286#define GB_MACROTILE_MODE7__BANK_HEIGHT__SHIFT 0x2 5287#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT__SHIFT 0x4 5288#define GB_MACROTILE_MODE7__NUM_BANKS__SHIFT 0x6 5289#define GB_MACROTILE_MODE7__BANK_WIDTH_MASK 0x00000003L 5290#define GB_MACROTILE_MODE7__BANK_HEIGHT_MASK 0x0000000CL 5291#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT_MASK 0x00000030L 5292#define GB_MACROTILE_MODE7__NUM_BANKS_MASK 0x000000C0L 5293//GB_MACROTILE_MODE8 5294#define GB_MACROTILE_MODE8__BANK_WIDTH__SHIFT 0x0 5295#define GB_MACROTILE_MODE8__BANK_HEIGHT__SHIFT 0x2 5296#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT__SHIFT 0x4 5297#define GB_MACROTILE_MODE8__NUM_BANKS__SHIFT 0x6 5298#define GB_MACROTILE_MODE8__BANK_WIDTH_MASK 0x00000003L 5299#define GB_MACROTILE_MODE8__BANK_HEIGHT_MASK 0x0000000CL 5300#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT_MASK 0x00000030L 5301#define GB_MACROTILE_MODE8__NUM_BANKS_MASK 0x000000C0L 5302//GB_MACROTILE_MODE9 5303#define GB_MACROTILE_MODE9__BANK_WIDTH__SHIFT 0x0 5304#define GB_MACROTILE_MODE9__BANK_HEIGHT__SHIFT 0x2 5305#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT__SHIFT 0x4 5306#define GB_MACROTILE_MODE9__NUM_BANKS__SHIFT 0x6 5307#define GB_MACROTILE_MODE9__BANK_WIDTH_MASK 0x00000003L 5308#define GB_MACROTILE_MODE9__BANK_HEIGHT_MASK 0x0000000CL 5309#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT_MASK 0x00000030L 5310#define GB_MACROTILE_MODE9__NUM_BANKS_MASK 0x000000C0L 5311//GB_MACROTILE_MODE10 5312#define GB_MACROTILE_MODE10__BANK_WIDTH__SHIFT 0x0 5313#define GB_MACROTILE_MODE10__BANK_HEIGHT__SHIFT 0x2 5314#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT__SHIFT 0x4 5315#define GB_MACROTILE_MODE10__NUM_BANKS__SHIFT 0x6 5316#define GB_MACROTILE_MODE10__BANK_WIDTH_MASK 0x00000003L 5317#define GB_MACROTILE_MODE10__BANK_HEIGHT_MASK 0x0000000CL 5318#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT_MASK 0x00000030L 5319#define GB_MACROTILE_MODE10__NUM_BANKS_MASK 0x000000C0L 5320//GB_MACROTILE_MODE11 5321#define GB_MACROTILE_MODE11__BANK_WIDTH__SHIFT 0x0 5322#define GB_MACROTILE_MODE11__BANK_HEIGHT__SHIFT 0x2 5323#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT__SHIFT 0x4 5324#define GB_MACROTILE_MODE11__NUM_BANKS__SHIFT 0x6 5325#define GB_MACROTILE_MODE11__BANK_WIDTH_MASK 0x00000003L 5326#define GB_MACROTILE_MODE11__BANK_HEIGHT_MASK 0x0000000CL 5327#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT_MASK 0x00000030L 5328#define GB_MACROTILE_MODE11__NUM_BANKS_MASK 0x000000C0L 5329//GB_MACROTILE_MODE12 5330#define GB_MACROTILE_MODE12__BANK_WIDTH__SHIFT 0x0 5331#define GB_MACROTILE_MODE12__BANK_HEIGHT__SHIFT 0x2 5332#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT__SHIFT 0x4 5333#define GB_MACROTILE_MODE12__NUM_BANKS__SHIFT 0x6 5334#define GB_MACROTILE_MODE12__BANK_WIDTH_MASK 0x00000003L 5335#define GB_MACROTILE_MODE12__BANK_HEIGHT_MASK 0x0000000CL 5336#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT_MASK 0x00000030L 5337#define GB_MACROTILE_MODE12__NUM_BANKS_MASK 0x000000C0L 5338//GB_MACROTILE_MODE13 5339#define GB_MACROTILE_MODE13__BANK_WIDTH__SHIFT 0x0 5340#define GB_MACROTILE_MODE13__BANK_HEIGHT__SHIFT 0x2 5341#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT__SHIFT 0x4 5342#define GB_MACROTILE_MODE13__NUM_BANKS__SHIFT 0x6 5343#define GB_MACROTILE_MODE13__BANK_WIDTH_MASK 0x00000003L 5344#define GB_MACROTILE_MODE13__BANK_HEIGHT_MASK 0x0000000CL 5345#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT_MASK 0x00000030L 5346#define GB_MACROTILE_MODE13__NUM_BANKS_MASK 0x000000C0L 5347//GB_MACROTILE_MODE14 5348#define GB_MACROTILE_MODE14__BANK_WIDTH__SHIFT 0x0 5349#define GB_MACROTILE_MODE14__BANK_HEIGHT__SHIFT 0x2 5350#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT__SHIFT 0x4 5351#define GB_MACROTILE_MODE14__NUM_BANKS__SHIFT 0x6 5352#define GB_MACROTILE_MODE14__BANK_WIDTH_MASK 0x00000003L 5353#define GB_MACROTILE_MODE14__BANK_HEIGHT_MASK 0x0000000CL 5354#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT_MASK 0x00000030L 5355#define GB_MACROTILE_MODE14__NUM_BANKS_MASK 0x000000C0L 5356//GB_MACROTILE_MODE15 5357#define GB_MACROTILE_MODE15__BANK_WIDTH__SHIFT 0x0 5358#define GB_MACROTILE_MODE15__BANK_HEIGHT__SHIFT 0x2 5359#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT__SHIFT 0x4 5360#define GB_MACROTILE_MODE15__NUM_BANKS__SHIFT 0x6 5361#define GB_MACROTILE_MODE15__BANK_WIDTH_MASK 0x00000003L 5362#define GB_MACROTILE_MODE15__BANK_HEIGHT_MASK 0x0000000CL 5363#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT_MASK 0x00000030L 5364#define GB_MACROTILE_MODE15__NUM_BANKS_MASK 0x000000C0L 5365//CB_HW_CONTROL 5366#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT__SHIFT 0x0 5367#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT__SHIFT 0x6 5368#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT__SHIFT 0xc 5369#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT 0x10 5370#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING__SHIFT 0x12 5371#define CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT 0x13 5372#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE__SHIFT 0x14 5373#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT 0x15 5374#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK__SHIFT 0x16 5375#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG__SHIFT 0x17 5376#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x18 5377#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x19 5378#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0x1a 5379#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT 0x1b 5380#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT__SHIFT 0x1c 5381#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT__SHIFT 0x1d 5382#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT 0x1e 5383#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT 0x1f 5384#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT_MASK 0x0000000FL 5385#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT_MASK 0x000003C0L 5386#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT_MASK 0x0000F000L 5387#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK 0x00010000L 5388#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING_MASK 0x00040000L 5389#define CB_HW_CONTROL__FORCE_NEEDS_DST_MASK 0x00080000L 5390#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE_MASK 0x00100000L 5391#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK 0x00200000L 5392#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK_MASK 0x00400000L 5393#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG_MASK 0x00800000L 5394#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x01000000L 5395#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK 0x02000000L 5396#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x04000000L 5397#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK 0x08000000L 5398#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT_MASK 0x10000000L 5399#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT_MASK 0x20000000L 5400#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT_MASK 0x40000000L 5401#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE_MASK 0x80000000L 5402//CB_HW_CONTROL_1 5403#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS__SHIFT 0x0 5404#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS__SHIFT 0x5 5405#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT 0xb 5406#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH__SHIFT 0x11 5407#define CB_HW_CONTROL_1__RMI_CREDITS__SHIFT 0x1a 5408#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS_MASK 0x0000001FL 5409#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS_MASK 0x000007E0L 5410#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK 0x0001F800L 5411#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH_MASK 0x03FE0000L 5412#define CB_HW_CONTROL_1__RMI_CREDITS_MASK 0xFC000000L 5413//CB_HW_CONTROL_2 5414#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH__SHIFT 0x0 5415#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH__SHIFT 0x8 5416#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH__SHIFT 0xf 5417#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8__SHIFT 0x18 5418#define CB_HW_CONTROL_2__CHICKEN_BITS__SHIFT 0x1c 5419#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH_MASK 0x000000FFL 5420#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH_MASK 0x00007F00L 5421#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH_MASK 0x007F8000L 5422#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8_MASK 0x0F000000L 5423#define CB_HW_CONTROL_2__CHICKEN_BITS_MASK 0xF0000000L 5424//CB_HW_CONTROL_3 5425#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL__SHIFT 0x0 5426#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED__SHIFT 0x1 5427#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT__SHIFT 0x2 5428#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP__SHIFT 0x3 5429#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR__SHIFT 0x4 5430#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM__SHIFT 0x5 5431#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_KEY_MOD__SHIFT 0x6 5432#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING__SHIFT 0x7 5433#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION__SHIFT 0x8 5434#define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS__SHIFT 0x9 5435#define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS__SHIFT 0xa 5436#define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION__SHIFT 0xb 5437#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967__SHIFT 0xc 5438#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657__SHIFT 0xd 5439#define CB_HW_CONTROL_3__DISABLE_OC_FIXES_OF_BUG_522542__SHIFT 0xe 5440#define CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH__SHIFT 0xf 5441#define CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH__SHIFT 0x10 5442#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC__SHIFT 0x11 5443#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_FC__SHIFT 0x12 5444#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC__SHIFT 0x13 5445#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CM__SHIFT 0x14 5446#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC__SHIFT 0x15 5447#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_FC__SHIFT 0x16 5448#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC__SHIFT 0x17 5449#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CM__SHIFT 0x18 5450#define CB_HW_CONTROL_3__DISABLE_NACK_COLOR_RD_WR_OPT__SHIFT 0x19 5451#define CB_HW_CONTROL_3__DISABLE_BLENDER_CLOCK_GATING__SHIFT 0x1a 5452#define CB_HW_CONTROL_3__DISABLE_DUALSRC_WITH_OBJPRIMID_FIX__SHIFT 0x1b 5453#define CB_HW_CONTROL_3__COLOR_CACHE_PREFETCH_NUM_CLS__SHIFT 0x1c 5454#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL_MASK 0x00000001L 5455#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED_MASK 0x00000002L 5456#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT_MASK 0x00000004L 5457#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP_MASK 0x00000008L 5458#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR_MASK 0x00000010L 5459#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM_MASK 0x00000020L 5460#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_KEY_MOD_MASK 0x00000040L 5461#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING_MASK 0x00000080L 5462#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION_MASK 0x00000100L 5463#define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS_MASK 0x00000200L 5464#define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS_MASK 0x00000400L 5465#define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION_MASK 0x00000800L 5466#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967_MASK 0x00001000L 5467#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657_MASK 0x00002000L 5468#define CB_HW_CONTROL_3__DISABLE_OC_FIXES_OF_BUG_522542_MASK 0x00004000L 5469#define CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH_MASK 0x00008000L 5470#define CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH_MASK 0x00010000L 5471#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC_MASK 0x00020000L 5472#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_FC_MASK 0x00040000L 5473#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC_MASK 0x00080000L 5474#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CM_MASK 0x00100000L 5475#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC_MASK 0x00200000L 5476#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_FC_MASK 0x00400000L 5477#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC_MASK 0x00800000L 5478#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CM_MASK 0x01000000L 5479#define CB_HW_CONTROL_3__DISABLE_NACK_COLOR_RD_WR_OPT_MASK 0x02000000L 5480#define CB_HW_CONTROL_3__DISABLE_BLENDER_CLOCK_GATING_MASK 0x04000000L 5481#define CB_HW_CONTROL_3__DISABLE_DUALSRC_WITH_OBJPRIMID_FIX_MASK 0x08000000L 5482#define CB_HW_CONTROL_3__COLOR_CACHE_PREFETCH_NUM_CLS_MASK 0x30000000L 5483//CB_HW_MEM_ARBITER_RD 5484#define CB_HW_MEM_ARBITER_RD__MODE__SHIFT 0x0 5485#define CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE__SHIFT 0x2 5486#define CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE__SHIFT 0x6 5487#define CB_HW_MEM_ARBITER_RD__WEIGHT_CC__SHIFT 0xa 5488#define CB_HW_MEM_ARBITER_RD__WEIGHT_FC__SHIFT 0xc 5489#define CB_HW_MEM_ARBITER_RD__WEIGHT_CM__SHIFT 0xe 5490#define CB_HW_MEM_ARBITER_RD__WEIGHT_DC__SHIFT 0x10 5491#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS__SHIFT 0x12 5492#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS__SHIFT 0x14 5493#define CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS__SHIFT 0x16 5494#define CB_HW_MEM_ARBITER_RD__SCALE_AGE__SHIFT 0x17 5495#define CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT__SHIFT 0x1a 5496#define CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS__SHIFT 0x1d 5497#define CB_HW_MEM_ARBITER_RD__MODE_MASK 0x00000003L 5498#define CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE_MASK 0x0000003CL 5499#define CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE_MASK 0x000003C0L 5500#define CB_HW_MEM_ARBITER_RD__WEIGHT_CC_MASK 0x00000C00L 5501#define CB_HW_MEM_ARBITER_RD__WEIGHT_FC_MASK 0x00003000L 5502#define CB_HW_MEM_ARBITER_RD__WEIGHT_CM_MASK 0x0000C000L 5503#define CB_HW_MEM_ARBITER_RD__WEIGHT_DC_MASK 0x00030000L 5504#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS_MASK 0x000C0000L 5505#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS_MASK 0x00300000L 5506#define CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS_MASK 0x00400000L 5507#define CB_HW_MEM_ARBITER_RD__SCALE_AGE_MASK 0x03800000L 5508#define CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT_MASK 0x1C000000L 5509#define CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS_MASK 0x20000000L 5510//CB_HW_MEM_ARBITER_WR 5511#define CB_HW_MEM_ARBITER_WR__MODE__SHIFT 0x0 5512#define CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE__SHIFT 0x2 5513#define CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE__SHIFT 0x6 5514#define CB_HW_MEM_ARBITER_WR__WEIGHT_CC__SHIFT 0xa 5515#define CB_HW_MEM_ARBITER_WR__WEIGHT_FC__SHIFT 0xc 5516#define CB_HW_MEM_ARBITER_WR__WEIGHT_CM__SHIFT 0xe 5517#define CB_HW_MEM_ARBITER_WR__WEIGHT_DC__SHIFT 0x10 5518#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS__SHIFT 0x12 5519#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS__SHIFT 0x14 5520#define CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK__SHIFT 0x16 5521#define CB_HW_MEM_ARBITER_WR__SCALE_AGE__SHIFT 0x17 5522#define CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT__SHIFT 0x1a 5523#define CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS__SHIFT 0x1d 5524#define CB_HW_MEM_ARBITER_WR__MODE_MASK 0x00000003L 5525#define CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE_MASK 0x0000003CL 5526#define CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE_MASK 0x000003C0L 5527#define CB_HW_MEM_ARBITER_WR__WEIGHT_CC_MASK 0x00000C00L 5528#define CB_HW_MEM_ARBITER_WR__WEIGHT_FC_MASK 0x00003000L 5529#define CB_HW_MEM_ARBITER_WR__WEIGHT_CM_MASK 0x0000C000L 5530#define CB_HW_MEM_ARBITER_WR__WEIGHT_DC_MASK 0x00030000L 5531#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS_MASK 0x000C0000L 5532#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS_MASK 0x00300000L 5533#define CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK_MASK 0x00400000L 5534#define CB_HW_MEM_ARBITER_WR__SCALE_AGE_MASK 0x03800000L 5535#define CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT_MASK 0x1C000000L 5536#define CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS_MASK 0x20000000L 5537//CB_DCC_CONFIG 5538#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH__SHIFT 0x0 5539#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE__SHIFT 0x5 5540#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE__SHIFT 0x6 5541#define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH__SHIFT 0x8 5542#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH__SHIFT 0x10 5543#define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT__SHIFT 0x18 5544#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS__SHIFT 0x1c 5545#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH_MASK 0x0000001FL 5546#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE_MASK 0x00000020L 5547#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE_MASK 0x00000040L 5548#define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH_MASK 0x0000FF00L 5549#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH_MASK 0x007F0000L 5550#define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT_MASK 0x0F000000L 5551#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS_MASK 0xF0000000L 5552//GC_USER_RB_REDUNDANCY 5553#define GC_USER_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8 5554#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc 5555#define GC_USER_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10 5556#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14 5557#define GC_USER_RB_REDUNDANCY__FAILED_RB0_MASK 0x00000F00L 5558#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x00001000L 5559#define GC_USER_RB_REDUNDANCY__FAILED_RB1_MASK 0x000F0000L 5560#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x00100000L 5561//GC_USER_RB_BACKEND_DISABLE 5562#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10 5563#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00FF0000L 5564 5565 5566// addressBlock: gc_ea_gceadec2 5567//GCEA_EDC_CNT 5568#define GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 5569#define GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 5570#define GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 5571#define GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 5572#define GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 5573#define GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa 5574#define GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc 5575#define GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe 5576#define GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 5577#define GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 5578#define GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14 5579#define GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16 5580#define GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18 5581#define GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a 5582#define GCEA_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c 5583#define GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 5584#define GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 5585#define GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 5586#define GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 5587#define GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 5588#define GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 5589#define GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L 5590#define GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L 5591#define GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L 5592#define GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L 5593#define GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L 5594#define GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L 5595#define GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L 5596#define GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L 5597#define GCEA_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L 5598//GCEA_EDC_CNT2 5599#define GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 5600#define GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 5601#define GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 5602#define GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 5603#define GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 5604#define GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa 5605#define GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc 5606#define GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe 5607#define GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 5608#define GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 5609#define GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 5610#define GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 5611#define GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 5612#define GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 5613#define GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L 5614#define GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L 5615//GCEA_DSM_CNTL 5616#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 5617#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 5618#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 5619#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 5620#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 5621#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 5622#define GCEA_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 5623#define GCEA_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb 5624#define GCEA_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc 5625#define GCEA_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe 5626#define GCEA_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf 5627#define GCEA_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 5628#define GCEA_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 5629#define GCEA_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 5630#define GCEA_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 5631#define GCEA_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 5632#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L 5633#define GCEA_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L 5634#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L 5635#define GCEA_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L 5636#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L 5637#define GCEA_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L 5638#define GCEA_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L 5639#define GCEA_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L 5640#define GCEA_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L 5641#define GCEA_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L 5642#define GCEA_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L 5643#define GCEA_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L 5644#define GCEA_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L 5645#define GCEA_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L 5646#define GCEA_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L 5647#define GCEA_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L 5648//GCEA_DSM_CNTLA 5649#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 5650#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 5651#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 5652#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 5653#define GCEA_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 5654#define GCEA_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 5655#define GCEA_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 5656#define GCEA_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb 5657#define GCEA_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc 5658#define GCEA_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe 5659#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf 5660#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 5661#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 5662#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 5663#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L 5664#define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L 5665#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L 5666#define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L 5667#define GCEA_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L 5668#define GCEA_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L 5669#define GCEA_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L 5670#define GCEA_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L 5671#define GCEA_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L 5672#define GCEA_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L 5673#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L 5674#define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L 5675#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L 5676#define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L 5677//GCEA_DSM_CNTLB 5678//GCEA_DSM_CNTL2 5679#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 5680#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 5681#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 5682#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 5683#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 5684#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 5685#define GCEA_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 5686#define GCEA_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb 5687#define GCEA_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc 5688#define GCEA_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe 5689#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf 5690#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 5691#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 5692#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 5693#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 5694#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 5695#define GCEA_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a 5696#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L 5697#define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L 5698#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L 5699#define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L 5700#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L 5701#define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L 5702#define GCEA_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L 5703#define GCEA_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L 5704#define GCEA_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L 5705#define GCEA_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L 5706#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L 5707#define GCEA_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L 5708#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L 5709#define GCEA_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L 5710#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L 5711#define GCEA_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L 5712#define GCEA_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L 5713//GCEA_DSM_CNTL2A 5714#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 5715#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 5716#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 5717#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 5718#define GCEA_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 5719#define GCEA_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 5720#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 5721#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb 5722#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc 5723#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe 5724#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf 5725#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 5726#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 5727#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 5728#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L 5729#define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L 5730#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L 5731#define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L 5732#define GCEA_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L 5733#define GCEA_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L 5734#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L 5735#define GCEA_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L 5736#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L 5737#define GCEA_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L 5738#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L 5739#define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L 5740#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L 5741#define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L 5742//GCEA_DSM_CNTL2B 5743//GCEA_TCC_XBR_CREDITS 5744#define GCEA_TCC_XBR_CREDITS__DRAM_RD_LIMIT__SHIFT 0x0 5745#define GCEA_TCC_XBR_CREDITS__DRAM_RD_RESERVE__SHIFT 0x6 5746#define GCEA_TCC_XBR_CREDITS__IO_RD_LIMIT__SHIFT 0x8 5747#define GCEA_TCC_XBR_CREDITS__IO_RD_RESERVE__SHIFT 0xe 5748#define GCEA_TCC_XBR_CREDITS__DRAM_WR_LIMIT__SHIFT 0x10 5749#define GCEA_TCC_XBR_CREDITS__DRAM_WR_RESERVE__SHIFT 0x16 5750#define GCEA_TCC_XBR_CREDITS__IO_WR_LIMIT__SHIFT 0x18 5751#define GCEA_TCC_XBR_CREDITS__IO_WR_RESERVE__SHIFT 0x1e 5752#define GCEA_TCC_XBR_CREDITS__DRAM_RD_LIMIT_MASK 0x0000003FL 5753#define GCEA_TCC_XBR_CREDITS__DRAM_RD_RESERVE_MASK 0x000000C0L 5754#define GCEA_TCC_XBR_CREDITS__IO_RD_LIMIT_MASK 0x00003F00L 5755#define GCEA_TCC_XBR_CREDITS__IO_RD_RESERVE_MASK 0x0000C000L 5756#define GCEA_TCC_XBR_CREDITS__DRAM_WR_LIMIT_MASK 0x003F0000L 5757#define GCEA_TCC_XBR_CREDITS__DRAM_WR_RESERVE_MASK 0x00C00000L 5758#define GCEA_TCC_XBR_CREDITS__IO_WR_LIMIT_MASK 0x3F000000L 5759#define GCEA_TCC_XBR_CREDITS__IO_WR_RESERVE_MASK 0xC0000000L 5760//GCEA_TCC_XBR_MAXBURST 5761#define GCEA_TCC_XBR_MAXBURST__DRAM_RD__SHIFT 0x0 5762#define GCEA_TCC_XBR_MAXBURST__IO_RD__SHIFT 0x4 5763#define GCEA_TCC_XBR_MAXBURST__DRAM_WR__SHIFT 0x8 5764#define GCEA_TCC_XBR_MAXBURST__IO_WR__SHIFT 0xc 5765#define GCEA_TCC_XBR_MAXBURST__DRAM_RD_MASK 0x0000000FL 5766#define GCEA_TCC_XBR_MAXBURST__IO_RD_MASK 0x000000F0L 5767#define GCEA_TCC_XBR_MAXBURST__DRAM_WR_MASK 0x00000F00L 5768#define GCEA_TCC_XBR_MAXBURST__IO_WR_MASK 0x0000F000L 5769//GCEA_PROBE_CNTL 5770#define GCEA_PROBE_CNTL__REQ2RSP_DELAY__SHIFT 0x0 5771#define GCEA_PROBE_CNTL__PRB_FILTER_DISABLE__SHIFT 0x5 5772#define GCEA_PROBE_CNTL__REQ2RSP_DELAY_MASK 0x0000001FL 5773#define GCEA_PROBE_CNTL__PRB_FILTER_DISABLE_MASK 0x00000020L 5774//GCEA_PROBE_MAP 5775#define GCEA_PROBE_MAP__CHADDR0_TO_RIGHTTCC__SHIFT 0x0 5776#define GCEA_PROBE_MAP__CHADDR1_TO_RIGHTTCC__SHIFT 0x1 5777#define GCEA_PROBE_MAP__CHADDR2_TO_RIGHTTCC__SHIFT 0x2 5778#define GCEA_PROBE_MAP__CHADDR3_TO_RIGHTTCC__SHIFT 0x3 5779#define GCEA_PROBE_MAP__CHADDR4_TO_RIGHTTCC__SHIFT 0x4 5780#define GCEA_PROBE_MAP__CHADDR5_TO_RIGHTTCC__SHIFT 0x5 5781#define GCEA_PROBE_MAP__CHADDR6_TO_RIGHTTCC__SHIFT 0x6 5782#define GCEA_PROBE_MAP__CHADDR7_TO_RIGHTTCC__SHIFT 0x7 5783#define GCEA_PROBE_MAP__CHADDR8_TO_RIGHTTCC__SHIFT 0x8 5784#define GCEA_PROBE_MAP__CHADDR9_TO_RIGHTTCC__SHIFT 0x9 5785#define GCEA_PROBE_MAP__CHADDR10_TO_RIGHTTCC__SHIFT 0xa 5786#define GCEA_PROBE_MAP__CHADDR11_TO_RIGHTTCC__SHIFT 0xb 5787#define GCEA_PROBE_MAP__CHADDR12_TO_RIGHTTCC__SHIFT 0xc 5788#define GCEA_PROBE_MAP__CHADDR13_TO_RIGHTTCC__SHIFT 0xd 5789#define GCEA_PROBE_MAP__CHADDR14_TO_RIGHTTCC__SHIFT 0xe 5790#define GCEA_PROBE_MAP__CHADDR15_TO_RIGHTTCC__SHIFT 0xf 5791#define GCEA_PROBE_MAP__INTLV_SIZE__SHIFT 0x10 5792#define GCEA_PROBE_MAP__CHADDR0_TO_RIGHTTCC_MASK 0x00000001L 5793#define GCEA_PROBE_MAP__CHADDR1_TO_RIGHTTCC_MASK 0x00000002L 5794#define GCEA_PROBE_MAP__CHADDR2_TO_RIGHTTCC_MASK 0x00000004L 5795#define GCEA_PROBE_MAP__CHADDR3_TO_RIGHTTCC_MASK 0x00000008L 5796#define GCEA_PROBE_MAP__CHADDR4_TO_RIGHTTCC_MASK 0x00000010L 5797#define GCEA_PROBE_MAP__CHADDR5_TO_RIGHTTCC_MASK 0x00000020L 5798#define GCEA_PROBE_MAP__CHADDR6_TO_RIGHTTCC_MASK 0x00000040L 5799#define GCEA_PROBE_MAP__CHADDR7_TO_RIGHTTCC_MASK 0x00000080L 5800#define GCEA_PROBE_MAP__CHADDR8_TO_RIGHTTCC_MASK 0x00000100L 5801#define GCEA_PROBE_MAP__CHADDR9_TO_RIGHTTCC_MASK 0x00000200L 5802#define GCEA_PROBE_MAP__CHADDR10_TO_RIGHTTCC_MASK 0x00000400L 5803#define GCEA_PROBE_MAP__CHADDR11_TO_RIGHTTCC_MASK 0x00000800L 5804#define GCEA_PROBE_MAP__CHADDR12_TO_RIGHTTCC_MASK 0x00001000L 5805#define GCEA_PROBE_MAP__CHADDR13_TO_RIGHTTCC_MASK 0x00002000L 5806#define GCEA_PROBE_MAP__CHADDR14_TO_RIGHTTCC_MASK 0x00004000L 5807#define GCEA_PROBE_MAP__CHADDR15_TO_RIGHTTCC_MASK 0x00008000L 5808#define GCEA_PROBE_MAP__INTLV_SIZE_MASK 0x00030000L 5809//GCEA_ERR_STATUS 5810#define GCEA_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 5811#define GCEA_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 5812#define GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0x8 5813#define GCEA_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0x9 5814#define GCEA_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xa 5815#define GCEA_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL 5816#define GCEA_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L 5817#define GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000100L 5818#define GCEA_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000200L 5819#define GCEA_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00000400L 5820//GCEA_MISC2 5821#define GCEA_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 5822#define GCEA_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 5823#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 5824#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 5825#define GCEA_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L 5826#define GCEA_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L 5827#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL 5828#define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L 5829//GCEA_SDP_BACKDOOR_CMDCREDITS0 5830#define GCEA_SDP_BACKDOOR_CMDCREDITS0__CREDITS_RECEIVED__SHIFT 0x0 5831#define GCEA_SDP_BACKDOOR_CMDCREDITS0__CREDITS_RECEIVED_MASK 0xFFFFFFFFL 5832//GCEA_SDP_BACKDOOR_CMDCREDITS1 5833#define GCEA_SDP_BACKDOOR_CMDCREDITS1__CREDITS_RECEIVED__SHIFT 0x0 5834#define GCEA_SDP_BACKDOOR_CMDCREDITS1__CREDITS_RECEIVED_MASK 0x7FFFFFFFL 5835//GCEA_SDP_BACKDOOR_DATACREDITS0 5836#define GCEA_SDP_BACKDOOR_DATACREDITS0__CREDITS_RECEIVED__SHIFT 0x0 5837#define GCEA_SDP_BACKDOOR_DATACREDITS0__CREDITS_RECEIVED_MASK 0xFFFFFFFFL 5838//GCEA_SDP_BACKDOOR_DATACREDITS1 5839#define GCEA_SDP_BACKDOOR_DATACREDITS1__CREDITS_RECEIVED__SHIFT 0x0 5840#define GCEA_SDP_BACKDOOR_DATACREDITS1__CREDITS_RECEIVED_MASK 0x7FFFFFFFL 5841//GCEA_SDP_BACKDOOR_MISCCREDITS 5842#define GCEA_SDP_BACKDOOR_MISCCREDITS__RDRSP_CREDITS_RELEASED__SHIFT 0x0 5843#define GCEA_SDP_BACKDOOR_MISCCREDITS__WRRSP_CREDITS_RELEASED__SHIFT 0x8 5844#define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_REQ_CREDITS_RELEASED__SHIFT 0x10 5845#define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_RSP_CREDITS_RECEIVED__SHIFT 0x17 5846#define GCEA_SDP_BACKDOOR_MISCCREDITS__RDRSP_CREDITS_RELEASED_MASK 0x000000FFL 5847#define GCEA_SDP_BACKDOOR_MISCCREDITS__WRRSP_CREDITS_RELEASED_MASK 0x0000FF00L 5848#define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_REQ_CREDITS_RELEASED_MASK 0x007F0000L 5849#define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_RSP_CREDITS_RECEIVED_MASK 0x3F800000L 5850//GCEA_SDP_ENABLE 5851#define GCEA_SDP_ENABLE__ENABLE__SHIFT 0x0 5852#define GCEA_SDP_ENABLE__ENABLE_MASK 0x00000001L 5853 5854 5855// addressBlock: gc_rmi_rmidec 5856//RMI_GENERAL_CNTL 5857#define RMI_GENERAL_CNTL__BURST_DISABLE__SHIFT 0x0 5858#define RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE__SHIFT 0x1 5859#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG__SHIFT 0x11 5860#define RMI_GENERAL_CNTL__RB0_HARVEST_EN__SHIFT 0x13 5861#define RMI_GENERAL_CNTL__RB1_HARVEST_EN__SHIFT 0x14 5862#define RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE__SHIFT 0x15 5863#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_UPDATE__SHIFT 0x19 5864#define RMI_GENERAL_CNTL__SKID_FIFO_0_OVERFLOW_ERROR_MASK__SHIFT 0x1a 5865#define RMI_GENERAL_CNTL__SKID_FIFO_0_UNDERFLOW_ERROR_MASK__SHIFT 0x1b 5866#define RMI_GENERAL_CNTL__SKID_FIFO_1_OVERFLOW_ERROR_MASK__SHIFT 0x1c 5867#define RMI_GENERAL_CNTL__SKID_FIFO_1_UNDERFLOW_ERROR_MASK__SHIFT 0x1d 5868#define RMI_GENERAL_CNTL__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK__SHIFT 0x1e 5869#define RMI_GENERAL_CNTL__BURST_DISABLE_MASK 0x00000001L 5870#define RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE_MASK 0x0001FFFEL 5871#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_MASK 0x00060000L 5872#define RMI_GENERAL_CNTL__RB0_HARVEST_EN_MASK 0x00080000L 5873#define RMI_GENERAL_CNTL__RB1_HARVEST_EN_MASK 0x00100000L 5874#define RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE_MASK 0x01E00000L 5875#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_UPDATE_MASK 0x02000000L 5876#define RMI_GENERAL_CNTL__SKID_FIFO_0_OVERFLOW_ERROR_MASK_MASK 0x04000000L 5877#define RMI_GENERAL_CNTL__SKID_FIFO_0_UNDERFLOW_ERROR_MASK_MASK 0x08000000L 5878#define RMI_GENERAL_CNTL__SKID_FIFO_1_OVERFLOW_ERROR_MASK_MASK 0x10000000L 5879#define RMI_GENERAL_CNTL__SKID_FIFO_1_UNDERFLOW_ERROR_MASK_MASK 0x20000000L 5880#define RMI_GENERAL_CNTL__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK_MASK 0x40000000L 5881//RMI_GENERAL_CNTL1 5882#define RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE__SHIFT 0x0 5883#define RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE__SHIFT 0x4 5884#define RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE__SHIFT 0x6 5885#define RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK__SHIFT 0x8 5886#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE__SHIFT 0x9 5887#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE__SHIFT 0xa 5888#define RMI_GENERAL_CNTL1__UTCL1_PROBE0_RR_ARB_BURST_HINT_EN__SHIFT 0xb 5889#define RMI_GENERAL_CNTL1__UTCL1_PROBE1_RR_ARB_BURST_HINT_EN__SHIFT 0xc 5890#define RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE_MASK 0x0000000FL 5891#define RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE_MASK 0x00000030L 5892#define RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE_MASK 0x000000C0L 5893#define RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK_MASK 0x00000100L 5894#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE_MASK 0x00000200L 5895#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_MASK 0x00000400L 5896#define RMI_GENERAL_CNTL1__UTCL1_PROBE0_RR_ARB_BURST_HINT_EN_MASK 0x00000800L 5897#define RMI_GENERAL_CNTL1__UTCL1_PROBE1_RR_ARB_BURST_HINT_EN_MASK 0x00001000L 5898//RMI_GENERAL_STATUS 5899#define RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED__SHIFT 0x0 5900#define RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR__SHIFT 0x1 5901#define RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR__SHIFT 0x2 5902#define RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR__SHIFT 0x3 5903#define RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR__SHIFT 0x4 5904#define RMI_GENERAL_STATUS__RMI_XBAR_BUSY__SHIFT 0x5 5905#define RMI_GENERAL_STATUS__RMI_UTCL1_BUSY__SHIFT 0x6 5906#define RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY__SHIFT 0x7 5907#define RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY__SHIFT 0x8 5908#define RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY__SHIFT 0x9 5909#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY__SHIFT 0xa 5910#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY__SHIFT 0xb 5911#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY__SHIFT 0xc 5912#define RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY__SHIFT 0xd 5913#define RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY__SHIFT 0xe 5914#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY__SHIFT 0xf 5915#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_1_BUSY__SHIFT 0x10 5916#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_1_BUSY__SHIFT 0x11 5917#define RMI_GENERAL_STATUS__UTC_PROBE1_BUSY__SHIFT 0x12 5918#define RMI_GENERAL_STATUS__UTC_PROBE0_BUSY__SHIFT 0x13 5919#define RMI_GENERAL_STATUS__RMI_XNACK_BUSY__SHIFT 0x14 5920#define RMI_GENERAL_STATUS__XNACK_FIFO_NUM_USED__SHIFT 0x15 5921#define RMI_GENERAL_STATUS__XNACK_FIFO_EMPTY__SHIFT 0x1d 5922#define RMI_GENERAL_STATUS__XNACK_FIFO_FULL__SHIFT 0x1e 5923#define RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR__SHIFT 0x1f 5924#define RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED_MASK 0x00000001L 5925#define RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR_MASK 0x00000002L 5926#define RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR_MASK 0x00000004L 5927#define RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR_MASK 0x00000008L 5928#define RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR_MASK 0x00000010L 5929#define RMI_GENERAL_STATUS__RMI_XBAR_BUSY_MASK 0x00000020L 5930#define RMI_GENERAL_STATUS__RMI_UTCL1_BUSY_MASK 0x00000040L 5931#define RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY_MASK 0x00000080L 5932#define RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY_MASK 0x00000100L 5933#define RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY_MASK 0x00000200L 5934#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY_MASK 0x00000400L 5935#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY_MASK 0x00000800L 5936#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY_MASK 0x00001000L 5937#define RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY_MASK 0x00002000L 5938#define RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY_MASK 0x00004000L 5939#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY_MASK 0x00008000L 5940#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_1_BUSY_MASK 0x00010000L 5941#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_1_BUSY_MASK 0x00020000L 5942#define RMI_GENERAL_STATUS__UTC_PROBE1_BUSY_MASK 0x00040000L 5943#define RMI_GENERAL_STATUS__UTC_PROBE0_BUSY_MASK 0x00080000L 5944#define RMI_GENERAL_STATUS__RMI_XNACK_BUSY_MASK 0x00100000L 5945#define RMI_GENERAL_STATUS__XNACK_FIFO_NUM_USED_MASK 0x1FE00000L 5946#define RMI_GENERAL_STATUS__XNACK_FIFO_EMPTY_MASK 0x20000000L 5947#define RMI_GENERAL_STATUS__XNACK_FIFO_FULL_MASK 0x40000000L 5948#define RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK 0x80000000L 5949//RMI_SUBBLOCK_STATUS0 5950#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0__SHIFT 0x0 5951#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0__SHIFT 0x7 5952#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0__SHIFT 0x8 5953#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1__SHIFT 0x9 5954#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1__SHIFT 0x10 5955#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1__SHIFT 0x11 5956#define RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT__SHIFT 0x12 5957#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0_MASK 0x0000007FL 5958#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0_MASK 0x00000080L 5959#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0_MASK 0x00000100L 5960#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1_MASK 0x0000FE00L 5961#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1_MASK 0x00010000L 5962#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1_MASK 0x00020000L 5963#define RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT_MASK 0x0FFC0000L 5964//RMI_SUBBLOCK_STATUS1 5965#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE__SHIFT 0x0 5966#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE__SHIFT 0xa 5967#define RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT__SHIFT 0x14 5968#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE_MASK 0x000003FFL 5969#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE_MASK 0x000FFC00L 5970#define RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT_MASK 0x3FF00000L 5971//RMI_SUBBLOCK_STATUS2 5972#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED__SHIFT 0x0 5973#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED__SHIFT 0x9 5974#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED_MASK 0x000001FFL 5975#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED_MASK 0x0003FE00L 5976//RMI_SUBBLOCK_STATUS3 5977#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL__SHIFT 0x0 5978#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL__SHIFT 0xa 5979#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL_MASK 0x000003FFL 5980#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL_MASK 0x000FFC00L 5981//RMI_XBAR_CONFIG 5982#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE__SHIFT 0x0 5983#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE__SHIFT 0x2 5984#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE__SHIFT 0x6 5985#define RMI_XBAR_CONFIG__ARBITER_DIS__SHIFT 0x7 5986#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ__SHIFT 0x8 5987#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE__SHIFT 0xc 5988#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB0__SHIFT 0xd 5989#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB1__SHIFT 0xe 5990#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE_MASK 0x00000003L 5991#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE_MASK 0x0000003CL 5992#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE_MASK 0x00000040L 5993#define RMI_XBAR_CONFIG__ARBITER_DIS_MASK 0x00000080L 5994#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_MASK 0x00000F00L 5995#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE_MASK 0x00001000L 5996#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB0_MASK 0x00002000L 5997#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB1_MASK 0x00004000L 5998//RMI_PROBE_POP_LOGIC_CNTL 5999#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH__SHIFT 0x0 6000#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS__SHIFT 0x7
6001#define RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2__SHIFT 0x8 6002#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH__SHIFT 0xa 6003#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS__SHIFT 0x11 6004#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH_MASK 0x0000007FL 6005#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS_MASK 0x00000080L 6006#define RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2_MASK 0x00000300L 6007#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH_MASK 0x0001FC00L 6008#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS_MASK 0x00020000L 6009//RMI_UTC_XNACK_N_MISC_CNTL 6010#define RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC__SHIFT 0x0 6011#define RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE__SHIFT 0x8 6012#define RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE__SHIFT 0xc 6013#define RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE__SHIFT 0xd 6014#define RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC_MASK 0x000000FFL 6015#define RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE_MASK 0x00000F00L 6016#define RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE_MASK 0x00001000L 6017#define RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE_MASK 0x00002000L 6018//RMI_DEMUX_CNTL 6019#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL__SHIFT 0x0 6020#define RMI_DEMUX_CNTL__DEMUX_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT 0x1 6021#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_OVERRIDE__SHIFT 0x4 6022#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE__SHIFT 0x6 6023#define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE__SHIFT 0xe 6024#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL__SHIFT 0x10 6025#define RMI_DEMUX_CNTL__DEMUX_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT 0x11 6026#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_OVERRIDE__SHIFT 0x14 6027#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE__SHIFT 0x16 6028#define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE__SHIFT 0x1e 6029#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_MASK 0x00000001L 6030#define RMI_DEMUX_CNTL__DEMUX_ARB0_BREAK_LOB_ON_IDLEIN_MASK 0x00000002L 6031#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_OVERRIDE_MASK 0x00000030L 6032#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE_MASK 0x00003FC0L 6033#define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE_MASK 0x0000C000L 6034#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_MASK 0x00010000L 6035#define RMI_DEMUX_CNTL__DEMUX_ARB1_BREAK_LOB_ON_IDLEIN_MASK 0x00020000L 6036#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_OVERRIDE_MASK 0x00300000L 6037#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE_MASK 0x3FC00000L 6038#define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE_MASK 0xC0000000L 6039//RMI_UTCL1_CNTL1 6040#define RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 6041#define RMI_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1 6042#define RMI_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 6043#define RMI_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3 6044#define RMI_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 6045#define RMI_UTCL1_CNTL1__CLIENTID__SHIFT 0x7 6046#define RMI_UTCL1_CNTL1__USERVM_DIS__SHIFT 0x10 6047#define RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11 6048#define RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12 6049#define RMI_UTCL1_CNTL1__REG_INV_VMID__SHIFT 0x13 6050#define RMI_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17 6051#define RMI_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT 0x18 6052#define RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19 6053#define RMI_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a 6054#define RMI_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b 6055#define RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c 6056#define RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e 6057#define RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L 6058#define RMI_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L 6059#define RMI_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L 6060#define RMI_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L 6061#define RMI_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L 6062#define RMI_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L 6063#define RMI_UTCL1_CNTL1__USERVM_DIS_MASK 0x00010000L 6064#define RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L 6065#define RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L 6066#define RMI_UTCL1_CNTL1__REG_INV_VMID_MASK 0x00780000L 6067#define RMI_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L 6068#define RMI_UTCL1_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L 6069#define RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L 6070#define RMI_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L 6071#define RMI_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L 6072#define RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L 6073#define RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L 6074//RMI_UTCL1_CNTL2 6075#define RMI_UTCL1_CNTL2__UTC_SPARE__SHIFT 0x0 6076#define RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 6077#define RMI_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa 6078#define RMI_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb 6079#define RMI_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc 6080#define RMI_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd 6081#define RMI_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe 6082#define RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf 6083#define RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE__SHIFT 0x10 6084#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12 6085#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR__SHIFT 0x13 6086#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID__SHIFT 0x14 6087#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID__SHIFT 0x15 6088#define RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ__SHIFT 0x19 6089#define RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K__SHIFT 0x1a 6090#define RMI_UTCL1_CNTL2__UTC_SPARE_MASK 0x000000FFL 6091#define RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L 6092#define RMI_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L 6093#define RMI_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L 6094#define RMI_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L 6095#define RMI_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L 6096#define RMI_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L 6097#define RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L 6098#define RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE_MASK 0x00030000L 6099#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L 6100#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR_MASK 0x00080000L 6101#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID_MASK 0x00100000L 6102#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID_MASK 0x01E00000L 6103#define RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ_MASK 0x02000000L 6104#define RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K_MASK 0x04000000L 6105//RMI_UTC_UNIT_CONFIG 6106//RMI_TCIW_FORMATTER0_CNTL 6107#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_OVERRIDE__SHIFT 0x0 6108#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_TIME_OUT_WINDOW__SHIFT 0x1 6109#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ__SHIFT 0x9 6110#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA__SHIFT 0x13 6111#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_UPDATE__SHIFT 0x1b 6112#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_REQ_SAFE_MODE__SHIFT 0x1c 6113#define RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS__SHIFT 0x1d 6114#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_AT_LAST_OF_BURST__SHIFT 0x1e 6115#define RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA__SHIFT 0x1f 6116#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_OVERRIDE_MASK 0x00000001L 6117#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_TIME_OUT_WINDOW_MASK 0x000001FEL 6118#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ_MASK 0x0007FE00L 6119#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_MASK 0x07F80000L 6120#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_UPDATE_MASK 0x08000000L 6121#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_REQ_SAFE_MODE_MASK 0x10000000L 6122#define RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS_MASK 0x20000000L 6123#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_AT_LAST_OF_BURST_MASK 0x40000000L 6124#define RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA_MASK 0x80000000L 6125//RMI_TCIW_FORMATTER1_CNTL 6126#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE__SHIFT 0x0 6127#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW__SHIFT 0x1 6128#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ__SHIFT 0x9 6129#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA__SHIFT 0x13 6130#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_UPDATE__SHIFT 0x1b 6131#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_REQ_SAFE_MODE__SHIFT 0x1c 6132#define RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS__SHIFT 0x1d 6133#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST__SHIFT 0x1e 6134#define RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA__SHIFT 0x1f 6135#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE_MASK 0x00000001L 6136#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW_MASK 0x000001FEL 6137#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ_MASK 0x0007FE00L 6138#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_MASK 0x07F80000L 6139#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_UPDATE_MASK 0x08000000L 6140#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_REQ_SAFE_MODE_MASK 0x10000000L 6141#define RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS_MASK 0x20000000L 6142#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST_MASK 0x40000000L 6143#define RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA_MASK 0x80000000L 6144//RMI_SCOREBOARD_CNTL 6145#define RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH__SHIFT 0x0 6146#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0__SHIFT 0x1 6147#define RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH__SHIFT 0x2 6148#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1__SHIFT 0x3 6149#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB1__SHIFT 0x4 6150#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN__SHIFT 0x5 6151#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE__SHIFT 0x6 6152#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB0__SHIFT 0x7 6153#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_EN__SHIFT 0x8 6154#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE__SHIFT 0x9 6155#define RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH_MASK 0x00000001L 6156#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0_MASK 0x00000002L 6157#define RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH_MASK 0x00000004L 6158#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1_MASK 0x00000008L 6159#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB1_MASK 0x00000010L 6160#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN_MASK 0x00000020L 6161#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE_MASK 0x00000040L 6162#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB0_MASK 0x00000080L 6163#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_EN_MASK 0x00000100L 6164#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE_MASK 0x001FFE00L 6165//RMI_SCOREBOARD_STATUS0 6166#define RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID__SHIFT 0x0 6167#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG__SHIFT 0x1 6168#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID__SHIFT 0x2 6169#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE__SHIFT 0x12 6170#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE__SHIFT 0x13 6171#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE__SHIFT 0x14 6172#define RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE__SHIFT 0x15 6173#define RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID_MASK 0x00000001L 6174#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG_MASK 0x00000002L 6175#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID_MASK 0x0003FFFCL 6176#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE_MASK 0x00040000L 6177#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE_MASK 0x00080000L 6178#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE_MASK 0x00100000L 6179#define RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE_MASK 0x00200000L 6180//RMI_SCOREBOARD_STATUS1 6181#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0__SHIFT 0x0 6182#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0__SHIFT 0xc 6183#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0__SHIFT 0xd 6184#define RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED__SHIFT 0xe 6185#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1__SHIFT 0xf 6186#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1__SHIFT 0x1b 6187#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1__SHIFT 0x1c 6188#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1__SHIFT 0x1d 6189#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0__SHIFT 0x1e 6190#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0_MASK 0x00000FFFL 6191#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0_MASK 0x00001000L 6192#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0_MASK 0x00002000L 6193#define RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED_MASK 0x00004000L 6194#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1_MASK 0x07FF8000L 6195#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1_MASK 0x08000000L 6196#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1_MASK 0x10000000L 6197#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1_MASK 0x20000000L 6198#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0_MASK 0x40000000L 6199//RMI_SCOREBOARD_STATUS2 6200#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0__SHIFT 0x0 6201#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0__SHIFT 0xc 6202#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1__SHIFT 0xd 6203#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1__SHIFT 0x19 6204#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1__SHIFT 0x1a 6205#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0__SHIFT 0x1b 6206#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0__SHIFT 0x1c 6207#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1__SHIFT 0x1d 6208#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0__SHIFT 0x1e 6209#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1__SHIFT 0x1f 6210#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0_MASK 0x00000FFFL 6211#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0_MASK 0x00001000L 6212#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1_MASK 0x01FFE000L 6213#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1_MASK 0x02000000L 6214#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1_MASK 0x04000000L 6215#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0_MASK 0x08000000L 6216#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0_MASK 0x10000000L 6217#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1_MASK 0x20000000L 6218#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0_MASK 0x40000000L 6219#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1_MASK 0x80000000L 6220//RMI_XBAR_ARBITER_CONFIG 6221#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE__SHIFT 0x0 6222#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR__SHIFT 0x2 6223#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL__SHIFT 0x3 6224#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT 0x4 6225#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE__SHIFT 0x6 6226#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE__SHIFT 0x8 6227#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE__SHIFT 0x10 6228#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR__SHIFT 0x12 6229#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL__SHIFT 0x13 6230#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT 0x14 6231#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE__SHIFT 0x16 6232#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE__SHIFT 0x18 6233#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE_MASK 0x00000003L 6234#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR_MASK 0x00000004L 6235#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_MASK 0x00000008L 6236#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN_MASK 0x00000010L 6237#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE_MASK 0x000000C0L 6238#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE_MASK 0x0000FF00L 6239#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE_MASK 0x00030000L 6240#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR_MASK 0x00040000L 6241#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_MASK 0x00080000L 6242#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN_MASK 0x00100000L 6243#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE_MASK 0x00C00000L 6244#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE_MASK 0xFF000000L 6245//RMI_XBAR_ARBITER_CONFIG_1 6246#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD__SHIFT 0x0 6247#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR__SHIFT 0x8 6248#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_RD__SHIFT 0x10 6249#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_WR__SHIFT 0x18 6250#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD_MASK 0x000000FFL 6251#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR_MASK 0x0000FF00L 6252#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_RD_MASK 0x00FF0000L 6253#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_WR_MASK 0xFF000000L 6254//RMI_CLOCK_CNTRL 6255#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK__SHIFT 0x0 6256#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK__SHIFT 0x5 6257#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK__SHIFT 0xa 6258#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK__SHIFT 0xf 6259#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_BUSY_MASK__SHIFT 0x14 6260#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_WAKEUP_MASK__SHIFT 0x19 6261#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK_MASK 0x0000001FL 6262#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK_MASK 0x000003E0L 6263#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK_MASK 0x00007C00L 6264#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK_MASK 0x000F8000L 6265#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_BUSY_MASK_MASK 0x01F00000L 6266#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_WAKEUP_MASK_MASK 0x3E000000L 6267//RMI_UTCL1_STATUS 6268#define RMI_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 6269#define RMI_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 6270#define RMI_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 6271#define RMI_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L 6272#define RMI_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L 6273#define RMI_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L 6274//RMI_SPARE 6275#define RMI_SPARE__RMI_ARBITER_STALL_TIMER_ENABLED_ALLOW_STREAMING__SHIFT 0x0 6276#define RMI_SPARE__SPARE_BIT_1__SHIFT 0x1 6277#define RMI_SPARE__SPARE_BIT_2__SHIFT 0x2 6278#define RMI_SPARE__SPARE_BIT_3__SHIFT 0x3 6279#define RMI_SPARE__SPARE_BIT_4__SHIFT 0x4 6280#define RMI_SPARE__SPARE_BIT_5__SHIFT 0x5 6281#define RMI_SPARE__SPARE_BIT_6__SHIFT 0x6 6282#define RMI_SPARE__SPARE_BIT_7__SHIFT 0x7 6283#define RMI_SPARE__SPARE_BIT_8_0__SHIFT 0x8 6284#define RMI_SPARE__SPARE_BIT_16_0__SHIFT 0x10 6285#define RMI_SPARE__RMI_ARBITER_STALL_TIMER_ENABLED_ALLOW_STREAMING_MASK 0x00000001L 6286#define RMI_SPARE__SPARE_BIT_1_MASK 0x00000002L 6287#define RMI_SPARE__SPARE_BIT_2_MASK 0x00000004L 6288#define RMI_SPARE__SPARE_BIT_3_MASK 0x00000008L 6289#define RMI_SPARE__SPARE_BIT_4_MASK 0x00000010L 6290#define RMI_SPARE__SPARE_BIT_5_MASK 0x00000020L 6291#define RMI_SPARE__SPARE_BIT_6_MASK 0x00000040L 6292#define RMI_SPARE__SPARE_BIT_7_MASK 0x00000080L 6293#define RMI_SPARE__SPARE_BIT_8_0_MASK 0x0000FF00L 6294#define RMI_SPARE__SPARE_BIT_16_0_MASK 0xFFFF0000L 6295//RMI_SPARE_1 6296#define RMI_SPARE_1__SPARE_BIT_8__SHIFT 0x0 6297#define RMI_SPARE_1__SPARE_BIT_9__SHIFT 0x1 6298#define RMI_SPARE_1__SPARE_BIT_10__SHIFT 0x2 6299#define RMI_SPARE_1__SPARE_BIT_11__SHIFT 0x3 6300#define RMI_SPARE_1__SPARE_BIT_12__SHIFT 0x4 6301#define RMI_SPARE_1__SPARE_BIT_13__SHIFT 0x5 6302#define RMI_SPARE_1__SPARE_BIT_14__SHIFT 0x6 6303#define RMI_SPARE_1__SPARE_BIT_15__SHIFT 0x7 6304#define RMI_SPARE_1__SPARE_BIT_8_1__SHIFT 0x8 6305#define RMI_SPARE_1__SPARE_BIT_16_1__SHIFT 0x10 6306#define RMI_SPARE_1__SPARE_BIT_8_MASK 0x00000001L 6307#define RMI_SPARE_1__SPARE_BIT_9_MASK 0x00000002L 6308#define RMI_SPARE_1__SPARE_BIT_10_MASK 0x00000004L 6309#define RMI_SPARE_1__SPARE_BIT_11_MASK 0x00000008L 6310#define RMI_SPARE_1__SPARE_BIT_12_MASK 0x00000010L 6311#define RMI_SPARE_1__SPARE_BIT_13_MASK 0x00000020L 6312#define RMI_SPARE_1__SPARE_BIT_14_MASK 0x00000040L 6313#define RMI_SPARE_1__SPARE_BIT_15_MASK 0x00000080L 6314#define RMI_SPARE_1__SPARE_BIT_8_1_MASK 0x0000FF00L 6315#define RMI_SPARE_1__SPARE_BIT_16_1_MASK 0xFFFF0000L 6316//RMI_SPARE_2 6317#define RMI_SPARE_2__SPARE_BIT_16__SHIFT 0x0 6318#define RMI_SPARE_2__SPARE_BIT_17__SHIFT 0x1 6319#define RMI_SPARE_2__SPARE_BIT_18__SHIFT 0x2 6320#define RMI_SPARE_2__SPARE_BIT_19__SHIFT 0x3 6321#define RMI_SPARE_2__SPARE_BIT_20__SHIFT 0x4 6322#define RMI_SPARE_2__SPARE_BIT_21__SHIFT 0x5 6323#define RMI_SPARE_2__SPARE_BIT_22__SHIFT 0x6 6324#define RMI_SPARE_2__SPARE_BIT_23__SHIFT 0x7 6325#define RMI_SPARE_2__SPARE_BIT_4_0__SHIFT 0x8 6326#define RMI_SPARE_2__SPARE_BIT_4_1__SHIFT 0xc 6327#define RMI_SPARE_2__SPARE_BIT_8_2__SHIFT 0x10 6328#define RMI_SPARE_2__SPARE_BIT_8_3__SHIFT 0x18 6329#define RMI_SPARE_2__SPARE_BIT_16_MASK 0x00000001L 6330#define RMI_SPARE_2__SPARE_BIT_17_MASK 0x00000002L 6331#define RMI_SPARE_2__SPARE_BIT_18_MASK 0x00000004L 6332#define RMI_SPARE_2__SPARE_BIT_19_MASK 0x00000008L 6333#define RMI_SPARE_2__SPARE_BIT_20_MASK 0x00000010L 6334#define RMI_SPARE_2__SPARE_BIT_21_MASK 0x00000020L 6335#define RMI_SPARE_2__SPARE_BIT_22_MASK 0x00000040L 6336#define RMI_SPARE_2__SPARE_BIT_23_MASK 0x00000080L 6337#define RMI_SPARE_2__SPARE_BIT_4_0_MASK 0x00000F00L 6338#define RMI_SPARE_2__SPARE_BIT_4_1_MASK 0x0000F000L 6339#define RMI_SPARE_2__SPARE_BIT_8_2_MASK 0x00FF0000L 6340#define RMI_SPARE_2__SPARE_BIT_8_3_MASK 0xFF000000L 6341 6342 6343// addressBlock: gc_dbgu_gfx_dbgudec 6344//port_a_addr 6345#define port_a_addr__Index__SHIFT 0x0 6346#define port_a_addr__Reserved__SHIFT 0x8 6347#define port_a_addr__ReadEnable__SHIFT 0x1f 6348#define port_a_addr__Index_MASK 0x000000FFL 6349#define port_a_addr__Reserved_MASK 0x7FFFFF00L 6350#define port_a_addr__ReadEnable_MASK 0x80000000L 6351//port_a_data_lo 6352#define port_a_data_lo__Data__SHIFT 0x0 6353#define port_a_data_lo__Data_MASK 0xFFFFFFFFL 6354//port_a_data_hi 6355#define port_a_data_hi__Data__SHIFT 0x0 6356#define port_a_data_hi__Data_MASK 0xFFFFFFFFL 6357//port_b_addr 6358#define port_b_addr__Index__SHIFT 0x0 6359#define port_b_addr__Reserved__SHIFT 0x8 6360#define port_b_addr__ReadEnable__SHIFT 0x1f 6361#define port_b_addr__Index_MASK 0x000000FFL 6362#define port_b_addr__Reserved_MASK 0x7FFFFF00L 6363#define port_b_addr__ReadEnable_MASK 0x80000000L 6364//port_b_data_lo 6365#define port_b_data_lo__Data__SHIFT 0x0 6366#define port_b_data_lo__Data_MASK 0xFFFFFFFFL 6367//port_b_data_hi 6368#define port_b_data_hi__Data__SHIFT 0x0 6369#define port_b_data_hi__Data_MASK 0xFFFFFFFFL 6370//port_c_addr 6371#define port_c_addr__Index__SHIFT 0x0 6372#define port_c_addr__Reserved__SHIFT 0x8 6373#define port_c_addr__ReadEnable__SHIFT 0x1f 6374#define port_c_addr__Index_MASK 0x000000FFL 6375#define port_c_addr__Reserved_MASK 0x7FFFFF00L 6376#define port_c_addr__ReadEnable_MASK 0x80000000L 6377//port_c_data_lo 6378#define port_c_data_lo__Data__SHIFT 0x0 6379#define port_c_data_lo__Data_MASK 0xFFFFFFFFL 6380//port_c_data_hi 6381#define port_c_data_hi__Data__SHIFT 0x0 6382#define port_c_data_hi__Data_MASK 0xFFFFFFFFL 6383//port_d_addr 6384#define port_d_addr__Index__SHIFT 0x0 6385#define port_d_addr__Reserved__SHIFT 0x8 6386#define port_d_addr__ReadEnable__SHIFT 0x1f 6387#define port_d_addr__Index_MASK 0x000000FFL 6388#define port_d_addr__Reserved_MASK 0x7FFFFF00L 6389#define port_d_addr__ReadEnable_MASK 0x80000000L 6390//port_d_data_lo 6391#define port_d_data_lo__Data__SHIFT 0x0 6392#define port_d_data_lo__Data_MASK 0xFFFFFFFFL 6393//port_d_data_hi 6394#define port_d_data_hi__Data__SHIFT 0x0 6395#define port_d_data_hi__Data_MASK 0xFFFFFFFFL 6396 6397 6398// addressBlock: gc_utcl2_atcl2dec 6399//ATC_L2_CNTL 6400#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0 6401#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x3 6402#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x6 6403#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x7 6404#define ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT 0x8 6405#define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb 6406#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x00000003L 6407#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x00000018L 6408#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000040L 6409#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000080L 6410#define ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK 0x00000700L 6411#define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L 6412//ATC_L2_CNTL2 6413#define ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0 6414#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x6 6415#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x8 6416#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0x9 6417#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xc 6418#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0xf 6419#define ATC_L2_CNTL2__BANK_SELECT_MASK 0x0000003FL 6420#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L 6421#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000100L 6422#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0x00000E00L 6423#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x00007000L 6424#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x001F8000L 6425//ATC_L2_CACHE_DATA0 6426#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x0 6427#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x1 6428#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x2 6429#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT 0x17 6430#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x00000001L 6431#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x00000002L 6432#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x007FFFFCL 6433#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK 0x07800000L 6434//ATC_L2_CACHE_DATA1 6435#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x0 6436#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xFFFFFFFFL 6437//ATC_L2_CACHE_DATA2 6438#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0 6439#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL 6440//ATC_L2_CNTL3 6441#define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0x0 6442#define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT 0x3 6443#define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK 0x00000007L 6444#define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK 0x000001F8L 6445//ATC_L2_STATUS 6446#define ATC_L2_STATUS__BUSY__SHIFT 0x0 6447#define ATC_L2_STATUS__PARITY_ERROR_INFO__SHIFT 0x1 6448#define ATC_L2_STATUS__BUSY_MASK 0x00000001L 6449#define ATC_L2_STATUS__PARITY_ERROR_INFO_MASK 0x3FFFFFFEL 6450//ATC_L2_STATUS2 6451#define ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO__SHIFT 0x0 6452#define ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO__SHIFT 0x8 6453#define ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO_MASK 0x000000FFL 6454#define ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO_MASK 0x0000FF00L 6455//ATC_L2_MISC_CG 6456#define ATC_L2_MISC_CG__OFFDLY__SHIFT 0x6 6457#define ATC_L2_MISC_CG__ENABLE__SHIFT 0x12 6458#define ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13 6459#define ATC_L2_MISC_CG__OFFDLY_MASK 0x00000FC0L 6460#define ATC_L2_MISC_CG__ENABLE_MASK 0x00040000L 6461#define ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK 0x00080000L 6462//ATC_L2_MEM_POWER_LS 6463#define ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 6464#define ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 6465#define ATC_L2_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL 6466#define ATC_L2_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L 6467//ATC_L2_CGTT_CLK_CTRL 6468#define ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 6469#define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 6470#define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf 6471#define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 6472#define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 6473#define ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 6474#define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 6475#define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L 6476#define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L 6477#define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L 6478 6479 6480// addressBlock: gc_utcl2_vml2pfdec 6481//VM_L2_CNTL 6482#define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0 6483#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1 6484#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2 6485#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4 6486#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8 6487#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9 6488#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa 6489#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb 6490#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc 6491#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf 6492#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12 6493#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13 6494#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15 6495#define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT 0x1a 6496#define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L 6497#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L 6498#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL 6499#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L 6500#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L 6501#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L 6502#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L 6503#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L 6504#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L 6505#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L 6506#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L 6507#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L 6508#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L 6509#define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK 0x0C000000L 6510//VM_L2_CNTL2 6511#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0 6512#define VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1 6513#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15 6514#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16 6515#define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT 0x17 6516#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a 6517#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c 6518#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L 6519#define VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L 6520#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L 6521#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L 6522#define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK 0x03800000L 6523#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L 6524#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L 6525//VM_L2_CNTL3 6526#define VM_L2_CNTL3__BANK_SELECT__SHIFT 0x0 6527#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6 6528#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8 6529#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf 6530#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14 6531#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15 6532#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18 6533#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c 6534#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d 6535#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e 6536#define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f 6537#define VM_L2_CNTL3__BANK_SELECT_MASK 0x0000003FL 6538#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L 6539#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L 6540#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L 6541#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L 6542#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L 6543#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L 6544#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L 6545#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L 6546#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L 6547#define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L 6548//VM_L2_STATUS 6549#define VM_L2_STATUS__L2_BUSY__SHIFT 0x0 6550#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1 6551#define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT 0x11 6552#define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT 0x12 6553#define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT 0x13 6554#define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT 0x14 6555#define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT 0x15 6556#define VM_L2_STATUS__L2_BUSY_MASK 0x00000001L 6557#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001FFFEL 6558#define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK 0x00020000L 6559#define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK 0x00040000L 6560#define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK 0x00080000L 6561#define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK 0x00100000L 6562#define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK 0x00200000L 6563//VM_DUMMY_PAGE_FAULT_CNTL 6564#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0 6565#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1 6566#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT 0x2 6567#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L 6568#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L 6569#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK 0x000000FCL 6570//VM_DUMMY_PAGE_FAULT_ADDR_LO32 6571#define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT 0x0 6572#define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL 6573//VM_DUMMY_PAGE_FAULT_ADDR_HI32 6574#define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT 0x0 6575#define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK 0x0000000FL 6576//VM_L2_PROTECTION_FAULT_CNTL 6577#define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 6578#define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x1 6579#define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x2 6580#define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x3 6581#define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 6582#define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x5 6583#define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x6 6584#define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 6585#define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x8 6586#define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x9 6587#define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 6588#define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb 6589#define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 6590#define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0xd 6591#define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x1d 6592#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT 0x1e 6593#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT 0x1f 6594#define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L 6595#define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000002L 6596#define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000004L 6597#define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000008L 6598#define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L 6599#define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000020L 6600#define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000040L 6601#define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L 6602#define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000100L 6603#define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000200L 6604#define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 6605#define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L 6606#define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 6607#define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x1FFFE000L 6608#define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x20000000L 6609#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK 0x40000000L 6610#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK 0x80000000L 6611//VM_L2_PROTECTION_FAULT_CNTL2 6612#define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x0 6613#define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x10 6614#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT 0x11 6615#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT 0x12 6616#define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT 0x13 6617#define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x0000FFFFL 6618#define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x00010000L 6619#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK 0x00020000L 6620#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK 0x00040000L 6621#define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK 0x00080000L 6622//VM_L2_PROTECTION_FAULT_MM_CNTL3 6623#define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 6624#define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL 6625//VM_L2_PROTECTION_FAULT_MM_CNTL4 6626#define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 6627#define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL 6628//VM_L2_PROTECTION_FAULT_STATUS 6629#define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT 0x0 6630#define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT 0x1 6631#define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT 0x4 6632#define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT 0x8 6633#define VM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT 0x9 6634#define VM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT 0x12 6635#define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x13 6636#define VM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x14 6637#define VM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT 0x18 6638#define VM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT 0x19 6639#define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK 0x00000001L 6640#define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK 0x0000000EL 6641#define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK 0x000000F0L 6642#define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK 0x00000100L 6643#define VM_L2_PROTECTION_FAULT_STATUS__CID_MASK 0x0003FE00L 6644#define VM_L2_PROTECTION_FAULT_STATUS__RW_MASK 0x00040000L 6645#define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x00080000L 6646#define VM_L2_PROTECTION_FAULT_STATUS__VMID_MASK 0x00F00000L 6647#define VM_L2_PROTECTION_FAULT_STATUS__VF_MASK 0x01000000L 6648#define VM_L2_PROTECTION_FAULT_STATUS__VFID_MASK 0x1E000000L 6649//VM_L2_PROTECTION_FAULT_ADDR_LO32 6650#define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0 6651#define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL 6652//VM_L2_PROTECTION_FAULT_ADDR_HI32 6653#define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0 6654#define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL 6655//VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 6656#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT 0x0 6657#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL 6658//VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 6659#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT 0x0 6660#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK 0x0000000FL 6661//VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 6662#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6663#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6664//VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 6665#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6666#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6667//VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 6668#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 6669#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 6670//VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 6671#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 6672#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 6673//VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 6674#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT 0x0 6675#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK 0xFFFFFFFFL 6676//VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 6677#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT 0x0 6678#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK 0x0000000FL 6679//VM_L2_CNTL4 6680#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0 6681#define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT 0x6 6682#define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT 0x7 6683#define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x8 6684#define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x12 6685#define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT 0x1c 6686#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL 6687#define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK 0x00000040L 6688#define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK 0x00000080L 6689#define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0003FF00L 6690#define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0FFC0000L 6691#define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK 0x10000000L 6692//VM_L2_MM_GROUP_RT_CLASSES 6693#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT 0x0 6694#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT 0x1 6695#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT 0x2 6696#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT 0x3 6697#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT 0x4 6698#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT 0x5 6699#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT 0x6 6700#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT 0x7 6701#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT 0x8 6702#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT 0x9 6703#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0xa 6704#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT 0xb 6705#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT 0xc 6706#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT 0xd 6707#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT 0xe 6708#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT 0xf 6709#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT 0x10 6710#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT 0x11 6711#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT 0x12 6712#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT 0x13 6713#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT 0x14 6714#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT 0x15 6715#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT 0x16 6716#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT 0x17 6717#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT 0x18 6718#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT 0x19 6719#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT 0x1a 6720#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT 0x1b 6721#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT 0x1c 6722#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT 0x1d 6723#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT 0x1e 6724#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT 0x1f 6725#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK 0x00000001L 6726#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK 0x00000002L 6727#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK 0x00000004L 6728#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK 0x00000008L 6729#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK 0x00000010L 6730#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK 0x00000020L 6731#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK 0x00000040L 6732#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK 0x00000080L 6733#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK 0x00000100L 6734#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK 0x00000200L 6735#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK 0x00000400L 6736#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK 0x00000800L 6737#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK 0x00001000L 6738#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK 0x00002000L 6739#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK 0x00004000L 6740#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK 0x00008000L 6741#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK 0x00010000L 6742#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK 0x00020000L 6743#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK 0x00040000L 6744#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK 0x00080000L 6745#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK 0x00100000L 6746#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK 0x00200000L 6747#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK 0x00400000L 6748#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK 0x00800000L 6749#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK 0x01000000L 6750#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK 0x02000000L 6751#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK 0x04000000L 6752#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK 0x08000000L 6753#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK 0x10000000L 6754#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK 0x20000000L 6755#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK 0x40000000L 6756#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK 0x80000000L 6757//VM_L2_BANK_SELECT_RESERVED_CID 6758#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0 6759#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa 6760#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14 6761#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 6762#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 6763#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL 6764#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L 6765#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x00100000L 6766#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L 6767#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L 6768//VM_L2_BANK_SELECT_RESERVED_CID2 6769#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x0 6770#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa 6771#define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x14 6772#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 6773#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 6774#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL 6775#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L 6776#define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x00100000L 6777#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L 6778#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L 6779//VM_L2_CACHE_PARITY_CNTL 6780#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT 0x0 6781#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT 0x1 6782#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT 0x2 6783#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT 0x3 6784#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT 0x4 6785#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT 0x5 6786#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT 0x6 6787#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT 0x9 6788#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT 0xc 6789#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK 0x00000001L 6790#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK 0x00000002L 6791#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK 0x00000004L 6792#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK 0x00000008L 6793#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK 0x00000010L 6794#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK 0x00000020L 6795#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK 0x000001C0L 6796#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK 0x00000E00L 6797#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK 0x0000F000L 6798//VM_L2_CGTT_CLK_CTRL 6799#define VM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 6800#define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 6801#define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf 6802#define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 6803#define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 6804#define VM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 6805#define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 6806#define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L 6807#define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L 6808#define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L 6809 6810 6811// addressBlock: gc_utcl2_vml2vcdec 6812//VM_CONTEXT0_CNTL 6813#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0 6814#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 6815#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 6816#define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 6817#define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 6818#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 6819#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 6820#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 6821#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 6822#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 6823#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 6824#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 6825#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 6826#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 6827#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 6828#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 6829#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 6830#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 6831#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 6832#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 6833#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 6834#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 6835#define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 6836#define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 6837#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 6838#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 6839#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 6840#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 6841#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 6842#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 6843#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 6844#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 6845#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 6846#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 6847#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 6848#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 6849#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 6850#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 6851//VM_CONTEXT1_CNTL 6852#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0 6853#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 6854#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 6855#define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 6856#define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 6857#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 6858#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 6859#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 6860#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 6861#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 6862#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 6863#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 6864#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 6865#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 6866#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 6867#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 6868#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 6869#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 6870#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 6871#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 6872#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 6873#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 6874#define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 6875#define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 6876#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 6877#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 6878#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 6879#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 6880#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 6881#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 6882#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 6883#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 6884#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 6885#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 6886#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 6887#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 6888#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 6889#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 6890//VM_CONTEXT2_CNTL 6891#define VM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT 0x0 6892#define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 6893#define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 6894#define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 6895#define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 6896#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 6897#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 6898#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 6899#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 6900#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 6901#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 6902#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 6903#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 6904#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 6905#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 6906#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 6907#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 6908#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 6909#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 6910#define VM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 6911#define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 6912#define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 6913#define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 6914#define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 6915#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 6916#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 6917#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 6918#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 6919#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 6920#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 6921#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 6922#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 6923#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 6924#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 6925#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 6926#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 6927#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 6928#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 6929//VM_CONTEXT3_CNTL 6930#define VM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT 0x0 6931#define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 6932#define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 6933#define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 6934#define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 6935#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 6936#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 6937#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 6938#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 6939#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 6940#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 6941#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 6942#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 6943#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 6944#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 6945#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 6946#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 6947#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 6948#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 6949#define VM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 6950#define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 6951#define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 6952#define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 6953#define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 6954#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 6955#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 6956#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 6957#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 6958#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 6959#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 6960#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 6961#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 6962#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 6963#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 6964#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 6965#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 6966#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 6967#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 6968//VM_CONTEXT4_CNTL 6969#define VM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT 0x0 6970#define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 6971#define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 6972#define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 6973#define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 6974#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 6975#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 6976#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 6977#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 6978#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 6979#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 6980#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 6981#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 6982#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 6983#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 6984#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 6985#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 6986#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 6987#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 6988#define VM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 6989#define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 6990#define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 6991#define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 6992#define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 6993#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 6994#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 6995#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 6996#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 6997#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 6998#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 6999#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 7000#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L
7001#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 7002#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 7003#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 7004#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 7005#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 7006#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 7007//VM_CONTEXT5_CNTL 7008#define VM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT 0x0 7009#define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 7010#define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 7011#define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 7012#define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 7013#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 7014#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 7015#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 7016#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 7017#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 7018#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 7019#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 7020#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 7021#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 7022#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 7023#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 7024#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 7025#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 7026#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 7027#define VM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 7028#define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 7029#define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 7030#define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 7031#define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 7032#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 7033#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 7034#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 7035#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 7036#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 7037#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 7038#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 7039#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 7040#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 7041#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 7042#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 7043#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 7044#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 7045#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 7046//VM_CONTEXT6_CNTL 7047#define VM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT 0x0 7048#define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 7049#define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 7050#define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 7051#define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 7052#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 7053#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 7054#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 7055#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 7056#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 7057#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 7058#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 7059#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 7060#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 7061#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 7062#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 7063#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 7064#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 7065#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 7066#define VM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 7067#define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 7068#define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 7069#define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 7070#define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 7071#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 7072#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 7073#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 7074#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 7075#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 7076#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 7077#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 7078#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 7079#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 7080#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 7081#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 7082#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 7083#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 7084#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 7085//VM_CONTEXT7_CNTL 7086#define VM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT 0x0 7087#define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 7088#define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 7089#define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 7090#define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 7091#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 7092#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 7093#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 7094#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 7095#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 7096#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 7097#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 7098#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 7099#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 7100#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 7101#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 7102#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 7103#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 7104#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 7105#define VM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 7106#define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 7107#define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 7108#define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 7109#define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 7110#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 7111#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 7112#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 7113#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 7114#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 7115#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 7116#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 7117#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 7118#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 7119#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 7120#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 7121#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 7122#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 7123#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 7124//VM_CONTEXT8_CNTL 7125#define VM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT 0x0 7126#define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 7127#define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 7128#define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 7129#define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 7130#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 7131#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 7132#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 7133#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 7134#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 7135#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 7136#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 7137#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 7138#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 7139#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 7140#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 7141#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 7142#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 7143#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 7144#define VM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 7145#define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 7146#define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 7147#define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 7148#define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 7149#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 7150#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 7151#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 7152#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 7153#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 7154#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 7155#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 7156#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 7157#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 7158#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 7159#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 7160#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 7161#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 7162#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 7163//VM_CONTEXT9_CNTL 7164#define VM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT 0x0 7165#define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 7166#define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 7167#define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 7168#define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 7169#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 7170#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 7171#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 7172#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 7173#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 7174#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 7175#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 7176#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 7177#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 7178#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 7179#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 7180#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 7181#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 7182#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 7183#define VM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 7184#define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 7185#define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 7186#define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 7187#define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 7188#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 7189#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 7190#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 7191#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 7192#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 7193#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 7194#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 7195#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 7196#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 7197#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 7198#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 7199#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 7200#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 7201#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 7202//VM_CONTEXT10_CNTL 7203#define VM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT 0x0 7204#define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 7205#define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 7206#define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 7207#define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 7208#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 7209#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 7210#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 7211#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 7212#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 7213#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 7214#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 7215#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 7216#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 7217#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 7218#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 7219#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 7220#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 7221#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 7222#define VM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 7223#define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 7224#define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 7225#define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 7226#define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 7227#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 7228#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 7229#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 7230#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 7231#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 7232#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 7233#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 7234#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 7235#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 7236#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 7237#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 7238#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 7239#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 7240#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 7241//VM_CONTEXT11_CNTL 7242#define VM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT 0x0 7243#define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 7244#define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 7245#define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 7246#define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 7247#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 7248#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 7249#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 7250#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 7251#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 7252#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 7253#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 7254#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 7255#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 7256#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 7257#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 7258#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 7259#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 7260#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 7261#define VM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 7262#define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 7263#define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 7264#define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 7265#define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 7266#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 7267#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 7268#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 7269#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 7270#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 7271#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 7272#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 7273#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 7274#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 7275#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 7276#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 7277#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 7278#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 7279#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 7280//VM_CONTEXT12_CNTL 7281#define VM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT 0x0 7282#define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 7283#define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 7284#define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 7285#define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 7286#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 7287#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 7288#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 7289#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 7290#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 7291#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 7292#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 7293#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 7294#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 7295#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 7296#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 7297#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 7298#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 7299#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 7300#define VM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 7301#define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 7302#define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 7303#define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 7304#define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 7305#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 7306#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 7307#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 7308#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 7309#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 7310#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 7311#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 7312#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 7313#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 7314#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 7315#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 7316#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 7317#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 7318#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 7319//VM_CONTEXT13_CNTL 7320#define VM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT 0x0 7321#define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 7322#define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 7323#define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 7324#define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 7325#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 7326#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 7327#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 7328#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 7329#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 7330#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 7331#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 7332#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 7333#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 7334#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 7335#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 7336#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 7337#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 7338#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 7339#define VM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 7340#define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 7341#define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 7342#define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 7343#define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 7344#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 7345#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 7346#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 7347#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 7348#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 7349#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 7350#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 7351#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 7352#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 7353#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 7354#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 7355#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 7356#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 7357#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 7358//VM_CONTEXT14_CNTL 7359#define VM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT 0x0 7360#define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 7361#define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 7362#define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 7363#define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 7364#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 7365#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 7366#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 7367#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 7368#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 7369#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 7370#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 7371#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 7372#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 7373#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 7374#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 7375#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 7376#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 7377#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 7378#define VM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 7379#define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 7380#define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 7381#define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 7382#define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 7383#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 7384#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 7385#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 7386#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 7387#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 7388#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 7389#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 7390#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 7391#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 7392#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 7393#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 7394#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 7395#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 7396#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 7397//VM_CONTEXT15_CNTL 7398#define VM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT 0x0 7399#define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 7400#define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 7401#define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 7402#define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 7403#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 7404#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 7405#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 7406#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 7407#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 7408#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 7409#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 7410#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 7411#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 7412#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 7413#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 7414#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 7415#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 7416#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 7417#define VM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 7418#define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 7419#define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 7420#define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 7421#define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 7422#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 7423#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 7424#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 7425#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 7426#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 7427#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 7428#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 7429#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 7430#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 7431#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 7432#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 7433#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 7434#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 7435#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 7436//VM_CONTEXTS_DISABLE 7437#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0 7438#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1 7439#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2 7440#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3 7441#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4 7442#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5 7443#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6 7444#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7 7445#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8 7446#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9 7447#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa 7448#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb 7449#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc 7450#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd 7451#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe 7452#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf 7453#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L 7454#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L 7455#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L 7456#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L 7457#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L 7458#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L 7459#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L 7460#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L 7461#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L 7462#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L 7463#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L 7464#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L 7465#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L 7466#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L 7467#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L 7468#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L 7469//VM_INVALIDATE_ENG0_SEM 7470#define VM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT 0x0 7471#define VM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK 0x00000001L 7472//VM_INVALIDATE_ENG1_SEM 7473#define VM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT 0x0 7474#define VM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK 0x00000001L 7475//VM_INVALIDATE_ENG2_SEM 7476#define VM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT 0x0 7477#define VM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK 0x00000001L 7478//VM_INVALIDATE_ENG3_SEM 7479#define VM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT 0x0 7480#define VM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK 0x00000001L 7481//VM_INVALIDATE_ENG4_SEM 7482#define VM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT 0x0 7483#define VM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK 0x00000001L 7484//VM_INVALIDATE_ENG5_SEM 7485#define VM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT 0x0 7486#define VM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK 0x00000001L 7487//VM_INVALIDATE_ENG6_SEM 7488#define VM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT 0x0 7489#define VM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK 0x00000001L 7490//VM_INVALIDATE_ENG7_SEM 7491#define VM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT 0x0 7492#define VM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK 0x00000001L 7493//VM_INVALIDATE_ENG8_SEM 7494#define VM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT 0x0 7495#define VM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK 0x00000001L 7496//VM_INVALIDATE_ENG9_SEM 7497#define VM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT 0x0 7498#define VM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK 0x00000001L 7499//VM_INVALIDATE_ENG10_SEM 7500#define VM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT 0x0 7501#define VM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK 0x00000001L 7502//VM_INVALIDATE_ENG11_SEM 7503#define VM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT 0x0 7504#define VM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK 0x00000001L 7505//VM_INVALIDATE_ENG12_SEM 7506#define VM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT 0x0 7507#define VM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK 0x00000001L 7508//VM_INVALIDATE_ENG13_SEM 7509#define VM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT 0x0 7510#define VM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK 0x00000001L 7511//VM_INVALIDATE_ENG14_SEM 7512#define VM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT 0x0 7513#define VM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK 0x00000001L 7514//VM_INVALIDATE_ENG15_SEM 7515#define VM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT 0x0 7516#define VM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK 0x00000001L 7517//VM_INVALIDATE_ENG16_SEM 7518#define VM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT 0x0 7519#define VM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK 0x00000001L 7520//VM_INVALIDATE_ENG17_SEM 7521#define VM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT 0x0 7522#define VM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK 0x00000001L 7523//VM_INVALIDATE_ENG0_REQ 7524#define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 7525#define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT 0x10 7526#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 7527#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 7528#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 7529#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 7530#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 7531#define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 7532#define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 7533#define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK 0x00030000L 7534#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 7535#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 7536#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 7537#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 7538#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 7539#define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 7540//VM_INVALIDATE_ENG1_REQ 7541#define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 7542#define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT 0x10 7543#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 7544#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 7545#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 7546#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 7547#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 7548#define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 7549#define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 7550#define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK 0x00030000L 7551#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 7552#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 7553#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 7554#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 7555#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 7556#define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 7557//VM_INVALIDATE_ENG2_REQ 7558#define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 7559#define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT 0x10 7560#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 7561#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 7562#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 7563#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 7564#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 7565#define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 7566#define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 7567#define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK 0x00030000L 7568#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 7569#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 7570#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 7571#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 7572#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 7573#define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 7574//VM_INVALIDATE_ENG3_REQ 7575#define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 7576#define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT 0x10 7577#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 7578#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 7579#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 7580#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 7581#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 7582#define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 7583#define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 7584#define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK 0x00030000L 7585#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 7586#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 7587#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 7588#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 7589#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 7590#define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 7591//VM_INVALIDATE_ENG4_REQ 7592#define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 7593#define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT 0x10 7594#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 7595#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 7596#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 7597#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 7598#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 7599#define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 7600#define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 7601#define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK 0x00030000L 7602#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 7603#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 7604#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 7605#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 7606#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 7607#define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 7608//VM_INVALIDATE_ENG5_REQ 7609#define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 7610#define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT 0x10 7611#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 7612#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 7613#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 7614#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 7615#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 7616#define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 7617#define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 7618#define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK 0x00030000L 7619#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 7620#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 7621#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 7622#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 7623#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 7624#define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 7625//VM_INVALIDATE_ENG6_REQ 7626#define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 7627#define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT 0x10 7628#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 7629#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 7630#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 7631#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 7632#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 7633#define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 7634#define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 7635#define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK 0x00030000L 7636#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 7637#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 7638#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 7639#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 7640#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 7641#define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 7642//VM_INVALIDATE_ENG7_REQ 7643#define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 7644#define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT 0x10 7645#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 7646#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 7647#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 7648#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 7649#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 7650#define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 7651#define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 7652#define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK 0x00030000L 7653#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 7654#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 7655#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 7656#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 7657#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 7658#define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 7659//VM_INVALIDATE_ENG8_REQ 7660#define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 7661#define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT 0x10 7662#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 7663#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 7664#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 7665#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 7666#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 7667#define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 7668#define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 7669#define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK 0x00030000L 7670#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 7671#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 7672#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 7673#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 7674#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 7675#define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 7676//VM_INVALIDATE_ENG9_REQ 7677#define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 7678#define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT 0x10 7679#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 7680#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 7681#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 7682#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 7683#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 7684#define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 7685#define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 7686#define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK 0x00030000L 7687#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 7688#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 7689#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 7690#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 7691#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 7692#define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 7693//VM_INVALIDATE_ENG10_REQ 7694#define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 7695#define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT 0x10 7696#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 7697#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 7698#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 7699#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 7700#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 7701#define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 7702#define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 7703#define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK 0x00030000L 7704#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 7705#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 7706#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 7707#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 7708#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 7709#define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 7710//VM_INVALIDATE_ENG11_REQ 7711#define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 7712#define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT 0x10 7713#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 7714#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 7715#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 7716#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 7717#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 7718#define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 7719#define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 7720#define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK 0x00030000L 7721#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 7722#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 7723#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 7724#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 7725#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 7726#define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 7727//VM_INVALIDATE_ENG12_REQ 7728#define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 7729#define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT 0x10 7730#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 7731#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 7732#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 7733#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 7734#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 7735#define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 7736#define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 7737#define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK 0x00030000L 7738#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 7739#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 7740#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 7741#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 7742#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 7743#define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 7744//VM_INVALIDATE_ENG13_REQ 7745#define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 7746#define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT 0x10 7747#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 7748#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 7749#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 7750#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 7751#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 7752#define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 7753#define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 7754#define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK 0x00030000L 7755#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 7756#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 7757#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 7758#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 7759#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 7760#define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 7761//VM_INVALIDATE_ENG14_REQ 7762#define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 7763#define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT 0x10 7764#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 7765#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 7766#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 7767#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 7768#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 7769#define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 7770#define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 7771#define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK 0x00030000L 7772#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 7773#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 7774#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 7775#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 7776#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 7777#define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 7778//VM_INVALIDATE_ENG15_REQ 7779#define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 7780#define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT 0x10 7781#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 7782#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 7783#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 7784#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 7785#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 7786#define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 7787#define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 7788#define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK 0x00030000L 7789#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 7790#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 7791#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 7792#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 7793#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 7794#define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 7795//VM_INVALIDATE_ENG16_REQ 7796#define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 7797#define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT 0x10 7798#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 7799#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 7800#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 7801#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 7802#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 7803#define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 7804#define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 7805#define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK 0x00030000L 7806#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 7807#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 7808#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 7809#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 7810#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 7811#define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 7812//VM_INVALIDATE_ENG17_REQ 7813#define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 7814#define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT 0x10 7815#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 7816#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 7817#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 7818#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 7819#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 7820#define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 7821#define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 7822#define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK 0x00030000L 7823#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 7824#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 7825#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 7826#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 7827#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 7828#define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 7829//VM_INVALIDATE_ENG0_ACK 7830#define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 7831#define VM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT 0x10 7832#define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 7833#define VM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK 0x00010000L 7834//VM_INVALIDATE_ENG1_ACK 7835#define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 7836#define VM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT 0x10 7837#define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 7838#define VM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK 0x00010000L 7839//VM_INVALIDATE_ENG2_ACK 7840#define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 7841#define VM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT 0x10 7842#define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 7843#define VM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK 0x00010000L 7844//VM_INVALIDATE_ENG3_ACK 7845#define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 7846#define VM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT 0x10 7847#define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 7848#define VM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK 0x00010000L 7849//VM_INVALIDATE_ENG4_ACK 7850#define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 7851#define VM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT 0x10 7852#define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 7853#define VM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK 0x00010000L 7854//VM_INVALIDATE_ENG5_ACK 7855#define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 7856#define VM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT 0x10 7857#define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 7858#define VM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK 0x00010000L 7859//VM_INVALIDATE_ENG6_ACK 7860#define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 7861#define VM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT 0x10 7862#define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 7863#define VM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK 0x00010000L 7864//VM_INVALIDATE_ENG7_ACK 7865#define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 7866#define VM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT 0x10 7867#define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 7868#define VM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK 0x00010000L 7869//VM_INVALIDATE_ENG8_ACK 7870#define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 7871#define VM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT 0x10 7872#define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 7873#define VM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK 0x00010000L 7874//VM_INVALIDATE_ENG9_ACK 7875#define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 7876#define VM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT 0x10 7877#define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 7878#define VM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK 0x00010000L 7879//VM_INVALIDATE_ENG10_ACK 7880#define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 7881#define VM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT 0x10 7882#define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 7883#define VM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK 0x00010000L 7884//VM_INVALIDATE_ENG11_ACK 7885#define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 7886#define VM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT 0x10 7887#define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 7888#define VM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK 0x00010000L 7889//VM_INVALIDATE_ENG12_ACK 7890#define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 7891#define VM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT 0x10 7892#define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 7893#define VM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK 0x00010000L 7894//VM_INVALIDATE_ENG13_ACK 7895#define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 7896#define VM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT 0x10 7897#define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 7898#define VM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK 0x00010000L 7899//VM_INVALIDATE_ENG14_ACK 7900#define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 7901#define VM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT 0x10 7902#define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 7903#define VM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK 0x00010000L 7904//VM_INVALIDATE_ENG15_ACK 7905#define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 7906#define VM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT 0x10 7907#define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 7908#define VM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK 0x00010000L 7909//VM_INVALIDATE_ENG16_ACK 7910#define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 7911#define VM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT 0x10 7912#define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 7913#define VM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK 0x00010000L 7914//VM_INVALIDATE_ENG17_ACK 7915#define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 7916#define VM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT 0x10 7917#define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 7918#define VM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK 0x00010000L 7919//VM_INVALIDATE_ENG0_ADDR_RANGE_LO32 7920#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 7921#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 7922#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 7923#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 7924//VM_INVALIDATE_ENG0_ADDR_RANGE_HI32 7925#define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 7926#define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 7927//VM_INVALIDATE_ENG1_ADDR_RANGE_LO32 7928#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 7929#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 7930#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 7931#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 7932//VM_INVALIDATE_ENG1_ADDR_RANGE_HI32 7933#define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 7934#define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 7935//VM_INVALIDATE_ENG2_ADDR_RANGE_LO32 7936#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 7937#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 7938#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 7939#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 7940//VM_INVALIDATE_ENG2_ADDR_RANGE_HI32 7941#define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 7942#define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 7943//VM_INVALIDATE_ENG3_ADDR_RANGE_LO32 7944#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 7945#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 7946#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 7947#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 7948//VM_INVALIDATE_ENG3_ADDR_RANGE_HI32 7949#define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 7950#define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 7951//VM_INVALIDATE_ENG4_ADDR_RANGE_LO32 7952#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 7953#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 7954#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 7955#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 7956//VM_INVALIDATE_ENG4_ADDR_RANGE_HI32 7957#define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 7958#define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 7959//VM_INVALIDATE_ENG5_ADDR_RANGE_LO32 7960#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 7961#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 7962#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 7963#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 7964//VM_INVALIDATE_ENG5_ADDR_RANGE_HI32 7965#define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 7966#define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 7967//VM_INVALIDATE_ENG6_ADDR_RANGE_LO32 7968#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 7969#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 7970#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 7971#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 7972//VM_INVALIDATE_ENG6_ADDR_RANGE_HI32 7973#define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 7974#define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 7975//VM_INVALIDATE_ENG7_ADDR_RANGE_LO32 7976#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 7977#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 7978#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 7979#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 7980//VM_INVALIDATE_ENG7_ADDR_RANGE_HI32 7981#define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 7982#define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 7983//VM_INVALIDATE_ENG8_ADDR_RANGE_LO32 7984#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 7985#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 7986#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 7987#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 7988//VM_INVALIDATE_ENG8_ADDR_RANGE_HI32 7989#define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 7990#define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 7991//VM_INVALIDATE_ENG9_ADDR_RANGE_LO32 7992#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 7993#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 7994#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 7995#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 7996//VM_INVALIDATE_ENG9_ADDR_RANGE_HI32 7997#define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 7998#define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 7999//VM_INVALIDATE_ENG10_ADDR_RANGE_LO32 8000#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0
8001#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 8002#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 8003#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 8004//VM_INVALIDATE_ENG10_ADDR_RANGE_HI32 8005#define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 8006#define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 8007//VM_INVALIDATE_ENG11_ADDR_RANGE_LO32 8008#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 8009#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 8010#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 8011#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 8012//VM_INVALIDATE_ENG11_ADDR_RANGE_HI32 8013#define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 8014#define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 8015//VM_INVALIDATE_ENG12_ADDR_RANGE_LO32 8016#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 8017#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 8018#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 8019#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 8020//VM_INVALIDATE_ENG12_ADDR_RANGE_HI32 8021#define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 8022#define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 8023//VM_INVALIDATE_ENG13_ADDR_RANGE_LO32 8024#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 8025#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 8026#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 8027#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 8028//VM_INVALIDATE_ENG13_ADDR_RANGE_HI32 8029#define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 8030#define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 8031//VM_INVALIDATE_ENG14_ADDR_RANGE_LO32 8032#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 8033#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 8034#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 8035#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 8036//VM_INVALIDATE_ENG14_ADDR_RANGE_HI32 8037#define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 8038#define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 8039//VM_INVALIDATE_ENG15_ADDR_RANGE_LO32 8040#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 8041#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 8042#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 8043#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 8044//VM_INVALIDATE_ENG15_ADDR_RANGE_HI32 8045#define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 8046#define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 8047//VM_INVALIDATE_ENG16_ADDR_RANGE_LO32 8048#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 8049#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 8050#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 8051#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 8052//VM_INVALIDATE_ENG16_ADDR_RANGE_HI32 8053#define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 8054#define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 8055//VM_INVALIDATE_ENG17_ADDR_RANGE_LO32 8056#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 8057#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 8058#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 8059#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 8060//VM_INVALIDATE_ENG17_ADDR_RANGE_HI32 8061#define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 8062#define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 8063//VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 8064#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 8065#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 8066//VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 8067#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 8068#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 8069//VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 8070#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 8071#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 8072//VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 8073#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 8074#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 8075//VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 8076#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 8077#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 8078//VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 8079#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 8080#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 8081//VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 8082#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 8083#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 8084//VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 8085#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 8086#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 8087//VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 8088#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 8089#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 8090//VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 8091#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 8092#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 8093//VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 8094#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 8095#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 8096//VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 8097#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 8098#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 8099//VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 8100#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 8101#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 8102//VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 8103#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 8104#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 8105//VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 8106#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 8107#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 8108//VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 8109#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 8110#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 8111//VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 8112#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 8113#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 8114//VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 8115#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 8116#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 8117//VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 8118#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 8119#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 8120//VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 8121#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 8122#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 8123//VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 8124#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 8125#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 8126//VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 8127#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 8128#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 8129//VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 8130#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 8131#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 8132//VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 8133#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 8134#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 8135//VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 8136#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 8137#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 8138//VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 8139#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 8140#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 8141//VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 8142#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 8143#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 8144//VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 8145#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 8146#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 8147//VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 8148#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 8149#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 8150//VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 8151#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 8152#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 8153//VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 8154#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 8155#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 8156//VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 8157#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 8158#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 8159//VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 8160#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 8161#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 8162//VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 8163#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 8164#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 8165//VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 8166#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 8167#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 8168//VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 8169#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 8170#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 8171//VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 8172#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 8173#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 8174//VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 8175#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 8176#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 8177//VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 8178#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 8179#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 8180//VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 8181#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 8182#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 8183//VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 8184#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 8185#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 8186//VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 8187#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 8188#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 8189//VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 8190#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 8191#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 8192//VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 8193#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 8194#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 8195//VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 8196#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 8197#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 8198//VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 8199#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 8200#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 8201//VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 8202#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 8203#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 8204//VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 8205#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 8206#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 8207//VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 8208#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 8209#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 8210//VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 8211#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 8212#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 8213//VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 8214#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 8215#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 8216//VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 8217#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 8218#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 8219//VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 8220#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 8221#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 8222//VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 8223#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 8224#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 8225//VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 8226#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 8227#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 8228//VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 8229#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 8230#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 8231//VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 8232#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 8233#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 8234//VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 8235#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 8236#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 8237//VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 8238#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 8239#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 8240//VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 8241#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 8242#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 8243//VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 8244#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 8245#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 8246//VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 8247#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 8248#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 8249//VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 8250#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 8251#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 8252//VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 8253#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 8254#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 8255//VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 8256#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 8257#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 8258//VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 8259#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 8260#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 8261//VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 8262#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 8263#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 8264//VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 8265#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 8266#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 8267//VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 8268#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 8269#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 8270//VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 8271#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 8272#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 8273//VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 8274#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 8275#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 8276//VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 8277#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 8278#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 8279//VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 8280#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 8281#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 8282//VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 8283#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 8284#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 8285//VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 8286#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 8287#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 8288//VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 8289#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 8290#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 8291//VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 8292#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 8293#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 8294//VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 8295#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 8296#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 8297//VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 8298#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 8299#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 8300//VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 8301#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 8302#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 8303//VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 8304#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 8305#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 8306//VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 8307#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 8308#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 8309//VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 8310#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 8311#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 8312//VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 8313#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 8314#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 8315//VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 8316#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 8317#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 8318//VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 8319#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 8320#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 8321//VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 8322#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 8323#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 8324//VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 8325#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 8326#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 8327//VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 8328#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 8329#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 8330//VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 8331#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 8332#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 8333//VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 8334#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 8335#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 8336//VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 8337#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 8338#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 8339//VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 8340#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 8341#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 8342//VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 8343#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 8344#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 8345//VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 8346#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 8347#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 8348//VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 8349#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 8350#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 8351 8352 8353// addressBlock: gc_utcl2_vmsharedpfdec 8354//MC_VM_NB_MMIOBASE 8355#define MC_VM_NB_MMIOBASE__MMIOBASE__SHIFT 0x0 8356#define MC_VM_NB_MMIOBASE__MMIOBASE_MASK 0xFFFFFFFFL 8357//MC_VM_NB_MMIOLIMIT 8358#define MC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT 0x0 8359#define MC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK 0xFFFFFFFFL 8360//MC_VM_NB_PCI_CTRL 8361#define MC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT 0x17 8362#define MC_VM_NB_PCI_CTRL__MMIOENABLE_MASK 0x00800000L 8363//MC_VM_NB_PCI_ARB 8364#define MC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3 8365#define MC_VM_NB_PCI_ARB__VGA_HOLE_MASK 0x00000008L 8366//MC_VM_NB_TOP_OF_DRAM_SLOT1 8367#define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17 8368#define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xFF800000L 8369//MC_VM_NB_LOWER_TOP_OF_DRAM2 8370#define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x0 8371#define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x17 8372#define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x00000001L 8373#define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xFF800000L 8374//MC_VM_NB_UPPER_TOP_OF_DRAM2 8375#define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x0 8376#define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0x00000FFFL 8377//MC_VM_FB_OFFSET 8378#define MC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0 8379#define MC_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL 8380//MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 8381#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT 0x0 8382#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK 0xFFFFFFFFL 8383//MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 8384#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT 0x0 8385#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK 0x0000000FL 8386//MC_VM_STEERING 8387#define MC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0 8388#define MC_VM_STEERING__DEFAULT_STEERING_MASK 0x00000003L 8389//MC_SHARED_VIRT_RESET_REQ 8390#define MC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0 8391#define MC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f 8392#define MC_SHARED_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL 8393#define MC_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L 8394//MC_MEM_POWER_LS 8395#define MC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 8396#define MC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 8397#define MC_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL 8398#define MC_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L 8399//MC_VM_CACHEABLE_DRAM_ADDRESS_START 8400#define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT 0x0 8401#define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL 8402//MC_VM_CACHEABLE_DRAM_ADDRESS_END 8403#define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT 0x0 8404#define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL 8405//MC_VM_APT_CNTL 8406#define MC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT 0x0 8407#define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT 0x1 8408#define MC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK 0x00000001L 8409#define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK 0x00000002L 8410//MC_VM_LOCAL_HBM_ADDRESS_START 8411#define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS__SHIFT 0x0 8412#define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL 8413//MC_VM_LOCAL_HBM_ADDRESS_END 8414#define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS__SHIFT 0x0 8415#define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL 8416//MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 8417#define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0 8418#define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L 8419 8420 8421// addressBlock: gc_utcl2_vmsharedvcdec 8422//MC_VM_FB_LOCATION_BASE 8423#define MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0 8424#define MC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL 8425//MC_VM_FB_LOCATION_TOP 8426#define MC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0 8427#define MC_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL 8428//MC_VM_AGP_TOP 8429#define MC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0 8430#define MC_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL 8431//MC_VM_AGP_BOT 8432#define MC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0 8433#define MC_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL 8434//MC_VM_AGP_BASE 8435#define MC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0 8436#define MC_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL 8437//MC_VM_SYSTEM_APERTURE_LOW_ADDR 8438#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT 0x0 8439#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL 8440//MC_VM_SYSTEM_APERTURE_HIGH_ADDR 8441#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT 0x0 8442#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL 8443//MC_VM_MX_L1_TLB_CNTL 8444#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 8445#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 8446#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 8447#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 8448#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7 8449#define MC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT 0xb 8450#define MC_VM_MX_L1_TLB_CNTL__ATC_EN__SHIFT 0xd 8451#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L 8452#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L 8453#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L 8454#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L 8455#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L 8456#define MC_VM_MX_L1_TLB_CNTL__MTYPE_MASK 0x00001800L 8457#define MC_VM_MX_L1_TLB_CNTL__ATC_EN_MASK 0x00002000L 8458 8459 8460// addressBlock: gc_ea_gceadec 8461//GCEA_DRAM_RD_CLI2GRP_MAP0 8462#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 8463#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 8464#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 8465#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 8466#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 8467#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 8468#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 8469#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 8470#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 8471#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 8472#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 8473#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 8474#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 8475#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 8476#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 8477#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 8478#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 8479#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 8480#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 8481#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 8482#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 8483#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 8484#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 8485#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 8486#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 8487#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 8488#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 8489#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 8490#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 8491#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 8492#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 8493#define GCEA_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 8494//GCEA_DRAM_RD_CLI2GRP_MAP1 8495#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 8496#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 8497#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 8498#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 8499#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 8500#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 8501#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 8502#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 8503#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 8504#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 8505#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 8506#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 8507#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 8508#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 8509#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 8510#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 8511#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 8512#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 8513#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 8514#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 8515#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 8516#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 8517#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 8518#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 8519#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 8520#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 8521#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 8522#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 8523#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 8524#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 8525#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 8526#define GCEA_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 8527//GCEA_DRAM_WR_CLI2GRP_MAP0 8528#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 8529#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 8530#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 8531#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 8532#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 8533#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 8534#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 8535#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 8536#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 8537#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 8538#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 8539#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 8540#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 8541#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 8542#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 8543#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 8544#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 8545#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 8546#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 8547#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 8548#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 8549#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 8550#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 8551#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 8552#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 8553#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 8554#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 8555#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 8556#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 8557#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 8558#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 8559#define GCEA_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 8560//GCEA_DRAM_WR_CLI2GRP_MAP1 8561#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 8562#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 8563#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 8564#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 8565#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 8566#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 8567#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 8568#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 8569#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 8570#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 8571#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 8572#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 8573#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 8574#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 8575#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 8576#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 8577#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 8578#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 8579#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 8580#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 8581#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 8582#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 8583#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 8584#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 8585#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 8586#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 8587#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 8588#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 8589#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 8590#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 8591#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 8592#define GCEA_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 8593//GCEA_DRAM_RD_GRP2VC_MAP 8594#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 8595#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 8596#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 8597#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 8598#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 8599#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 8600#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 8601#define GCEA_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 8602//GCEA_DRAM_WR_GRP2VC_MAP 8603#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 8604#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 8605#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 8606#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 8607#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 8608#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 8609#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 8610#define GCEA_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 8611//GCEA_DRAM_RD_LAZY 8612#define GCEA_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 8613#define GCEA_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 8614#define GCEA_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 8615#define GCEA_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 8616#define GCEA_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L 8617#define GCEA_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L 8618#define GCEA_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L 8619#define GCEA_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L 8620//GCEA_DRAM_WR_LAZY 8621#define GCEA_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 8622#define GCEA_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 8623#define GCEA_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 8624#define GCEA_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 8625#define GCEA_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L 8626#define GCEA_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L 8627#define GCEA_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L 8628#define GCEA_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L 8629//GCEA_DRAM_RD_CAM_CNTL 8630#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 8631#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 8632#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 8633#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 8634#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 8635#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 8636#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 8637#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 8638#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 8639#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 8640#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 8641#define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 8642#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 8643#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 8644#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 8645#define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 8646//GCEA_DRAM_WR_CAM_CNTL 8647#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 8648#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 8649#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 8650#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 8651#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 8652#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 8653#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 8654#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 8655#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 8656#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 8657#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 8658#define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 8659#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 8660#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 8661#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 8662#define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 8663//GCEA_DRAM_PAGE_BURST 8664#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 8665#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 8666#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 8667#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 8668#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL 8669#define GCEA_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 8670#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 8671#define GCEA_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L 8672//GCEA_DRAM_RD_PRI_AGE 8673#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 8674#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 8675#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 8676#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 8677#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 8678#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 8679#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 8680#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 8681#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 8682#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 8683#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 8684#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 8685#define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 8686#define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 8687#define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 8688#define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 8689//GCEA_DRAM_WR_PRI_AGE 8690#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 8691#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 8692#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 8693#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 8694#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 8695#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 8696#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 8697#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 8698#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 8699#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 8700#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 8701#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 8702#define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 8703#define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 8704#define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 8705#define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 8706//GCEA_DRAM_RD_PRI_QUEUING 8707#define GCEA_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 8708#define GCEA_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 8709#define GCEA_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 8710#define GCEA_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 8711#define GCEA_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 8712#define GCEA_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 8713#define GCEA_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 8714#define GCEA_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 8715//GCEA_DRAM_WR_PRI_QUEUING 8716#define GCEA_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 8717#define GCEA_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 8718#define GCEA_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 8719#define GCEA_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 8720#define GCEA_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 8721#define GCEA_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 8722#define GCEA_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 8723#define GCEA_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 8724//GCEA_DRAM_RD_PRI_FIXED 8725#define GCEA_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 8726#define GCEA_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 8727#define GCEA_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 8728#define GCEA_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 8729#define GCEA_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 8730#define GCEA_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 8731#define GCEA_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 8732#define GCEA_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 8733//GCEA_DRAM_WR_PRI_FIXED 8734#define GCEA_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 8735#define GCEA_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 8736#define GCEA_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 8737#define GCEA_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 8738#define GCEA_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 8739#define GCEA_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 8740#define GCEA_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 8741#define GCEA_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 8742//GCEA_DRAM_RD_PRI_URGENCY 8743#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 8744#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 8745#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 8746#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 8747#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 8748#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 8749#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 8750#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 8751#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 8752#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 8753#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 8754#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 8755#define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 8756#define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 8757#define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 8758#define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 8759//GCEA_DRAM_WR_PRI_URGENCY 8760#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 8761#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 8762#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 8763#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 8764#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 8765#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 8766#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 8767#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 8768#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 8769#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 8770#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 8771#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 8772#define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 8773#define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 8774#define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 8775#define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 8776//GCEA_DRAM_RD_PRI_QUANT_PRI1 8777#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 8778#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 8779#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 8780#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 8781#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 8782#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 8783#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 8784#define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 8785//GCEA_DRAM_RD_PRI_QUANT_PRI2 8786#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 8787#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 8788#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 8789#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 8790#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 8791#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 8792#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 8793#define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 8794//GCEA_DRAM_RD_PRI_QUANT_PRI3 8795#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 8796#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 8797#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 8798#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 8799#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 8800#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 8801#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 8802#define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 8803//GCEA_DRAM_WR_PRI_QUANT_PRI1 8804#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 8805#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 8806#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 8807#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 8808#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 8809#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 8810#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 8811#define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 8812//GCEA_DRAM_WR_PRI_QUANT_PRI2 8813#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 8814#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 8815#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 8816#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 8817#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 8818#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 8819#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 8820#define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 8821//GCEA_DRAM_WR_PRI_QUANT_PRI3 8822#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 8823#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 8824#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 8825#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 8826#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 8827#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 8828#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 8829#define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 8830//GCEA_ADDRNORM_BASE_ADDR0 8831#define GCEA_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 8832#define GCEA_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 8833#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x4 8834#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x8 8835#define GCEA_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc 8836#define GCEA_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L 8837#define GCEA_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 8838#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x000000F0L 8839#define GCEA_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000700L 8840#define GCEA_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L 8841//GCEA_ADDRNORM_LIMIT_ADDR0 8842#define GCEA_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 8843#define GCEA_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 8844#define GCEA_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES__SHIFT 0xa 8845#define GCEA_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc 8846#define GCEA_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000000FL 8847#define GCEA_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L 8848#define GCEA_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES_MASK 0x00000C00L 8849#define GCEA_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L 8850//GCEA_ADDRNORM_BASE_ADDR1 8851#define GCEA_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 8852#define GCEA_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 8853#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x4 8854#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x8 8855#define GCEA_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc 8856#define GCEA_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L 8857#define GCEA_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 8858#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x000000F0L 8859#define GCEA_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000700L 8860#define GCEA_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L 8861//GCEA_ADDRNORM_LIMIT_ADDR1 8862#define GCEA_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 8863#define GCEA_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 8864#define GCEA_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES__SHIFT 0xa 8865#define GCEA_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc 8866#define GCEA_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000000FL 8867#define GCEA_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L 8868#define GCEA_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES_MASK 0x00000C00L 8869#define GCEA_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L 8870//GCEA_ADDRNORM_OFFSET_ADDR1 8871#define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0 8872#define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0x14 8873#define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L 8874#define GCEA_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0xFFF00000L 8875//GCEA_ADDRNORM_HOLE_CNTL 8876#define GCEA_ADDRNORM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 8877#define GCEA_ADDRNORM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 8878#define GCEA_ADDRNORM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L 8879#define GCEA_ADDRNORM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L 8880//GCEA_ADDRDEC_BANK_CFG 8881#define GCEA_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0 8882#define GCEA_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x5 8883#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xa 8884#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xd 8885#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x10 8886#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x11 8887#define GCEA_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000001FL 8888#define GCEA_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x000003E0L 8889#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00001C00L 8890#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x0000E000L 8891#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00010000L 8892#define GCEA_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00020000L 8893//GCEA_ADDRDEC_MISC_CFG 8894#define GCEA_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0 8895#define GCEA_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1 8896#define GCEA_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2 8897#define GCEA_ADDRDEC_MISC_CFG__VCM_EN3__SHIFT 0x3 8898#define GCEA_ADDRDEC_MISC_CFG__VCM_EN4__SHIFT 0x4 8899#define GCEA_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8 8900#define GCEA_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9 8901#define GCEA_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc 8902#define GCEA_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x10 8903#define GCEA_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x14 8904#define GCEA_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x16 8905#define GCEA_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x18 8906#define GCEA_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1b 8907#define GCEA_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L 8908#define GCEA_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L 8909#define GCEA_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L 8910#define GCEA_ADDRDEC_MISC_CFG__VCM_EN3_MASK 0x00000008L 8911#define GCEA_ADDRDEC_MISC_CFG__VCM_EN4_MASK 0x00000010L 8912#define GCEA_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L 8913#define GCEA_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L 8914#define GCEA_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0000F000L 8915#define GCEA_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x000F0000L 8916#define GCEA_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00300000L 8917#define GCEA_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x00C00000L 8918#define GCEA_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x07000000L 8919#define GCEA_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0x38000000L 8920//GCEA_ADDRDECDRAM_ADDR_HASH_BANK0 8921#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0 8922#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1 8923#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe 8924#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L 8925#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL 8926#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L 8927//GCEA_ADDRDECDRAM_ADDR_HASH_BANK1 8928#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0 8929#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1 8930#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe 8931#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L 8932#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL 8933#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L 8934//GCEA_ADDRDECDRAM_ADDR_HASH_BANK2 8935#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0 8936#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1 8937#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe 8938#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L 8939#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL 8940#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L 8941//GCEA_ADDRDECDRAM_ADDR_HASH_BANK3 8942#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0 8943#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1 8944#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe 8945#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L 8946#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL 8947#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L 8948//GCEA_ADDRDECDRAM_ADDR_HASH_BANK4 8949#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0 8950#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1 8951#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe 8952#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L 8953#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL 8954#define GCEA_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L 8955//GCEA_ADDRDECDRAM_ADDR_HASH_PC 8956#define GCEA_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0 8957#define GCEA_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT 0x1 8958#define GCEA_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe 8959#define GCEA_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L 8960#define GCEA_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL 8961#define GCEA_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L 8962//GCEA_ADDRDECDRAM_ADDR_HASH_PC2 8963#define GCEA_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0 8964#define GCEA_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000001FL 8965//GCEA_ADDRDECDRAM_ADDR_HASH_CS0 8966#define GCEA_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0 8967#define GCEA_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1 8968#define GCEA_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L 8969#define GCEA_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL 8970//GCEA_ADDRDECDRAM_ADDR_HASH_CS1 8971#define GCEA_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0 8972#define GCEA_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1 8973#define GCEA_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L 8974#define GCEA_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL 8975//GCEA_ADDRDECDRAM_HARVEST_ENABLE 8976#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 8977#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 8978#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 8979#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 8980#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L 8981#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L 8982#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L 8983#define GCEA_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L 8984//GCEA_ADDRDEC0_BASE_ADDR_CS0 8985#define GCEA_ADDRDEC0_BASE_ADDR_CS0__CS_ENABLE__SHIFT 0x0 8986#define GCEA_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 8987#define GCEA_ADDRDEC0_BASE_ADDR_CS0__CS_ENABLE_MASK 0x00000001L 8988#define GCEA_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 8989//GCEA_ADDRDEC0_BASE_ADDR_CS1 8990#define GCEA_ADDRDEC0_BASE_ADDR_CS1__CS_ENABLE__SHIFT 0x0 8991#define GCEA_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 8992#define GCEA_ADDRDEC0_BASE_ADDR_CS1__CS_ENABLE_MASK 0x00000001L 8993#define GCEA_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 8994//GCEA_ADDRDEC0_BASE_ADDR_CS2 8995#define GCEA_ADDRDEC0_BASE_ADDR_CS2__CS_ENABLE__SHIFT 0x0 8996#define GCEA_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 8997#define GCEA_ADDRDEC0_BASE_ADDR_CS2__CS_ENABLE_MASK 0x00000001L 8998#define GCEA_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 8999//GCEA_ADDRDEC0_BASE_ADDR_CS3 9000#define GCEA_ADDRDEC0_BASE_ADDR_CS3__CS_ENABLE__SHIFT 0x0
9001#define GCEA_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 9002#define GCEA_ADDRDEC0_BASE_ADDR_CS3__CS_ENABLE_MASK 0x00000001L 9003#define GCEA_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 9004//GCEA_ADDRDEC0_BASE_ADDR_SECCS0 9005#define GCEA_ADDRDEC0_BASE_ADDR_SECCS0__CS_ENABLE__SHIFT 0x0 9006#define GCEA_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 9007#define GCEA_ADDRDEC0_BASE_ADDR_SECCS0__CS_ENABLE_MASK 0x00000001L 9008#define GCEA_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 9009//GCEA_ADDRDEC0_BASE_ADDR_SECCS1 9010#define GCEA_ADDRDEC0_BASE_ADDR_SECCS1__CS_ENABLE__SHIFT 0x0 9011#define GCEA_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 9012#define GCEA_ADDRDEC0_BASE_ADDR_SECCS1__CS_ENABLE_MASK 0x00000001L 9013#define GCEA_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 9014//GCEA_ADDRDEC0_BASE_ADDR_SECCS2 9015#define GCEA_ADDRDEC0_BASE_ADDR_SECCS2__CS_ENABLE__SHIFT 0x0 9016#define GCEA_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 9017#define GCEA_ADDRDEC0_BASE_ADDR_SECCS2__CS_ENABLE_MASK 0x00000001L 9018#define GCEA_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 9019//GCEA_ADDRDEC0_BASE_ADDR_SECCS3 9020#define GCEA_ADDRDEC0_BASE_ADDR_SECCS3__CS_ENABLE__SHIFT 0x0 9021#define GCEA_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 9022#define GCEA_ADDRDEC0_BASE_ADDR_SECCS3__CS_ENABLE_MASK 0x00000001L 9023#define GCEA_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 9024//GCEA_ADDRDEC0_ADDR_MASK_CS01 9025#define GCEA_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 9026#define GCEA_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 9027//GCEA_ADDRDEC0_ADDR_MASK_CS23 9028#define GCEA_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 9029#define GCEA_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 9030//GCEA_ADDRDEC0_ADDR_MASK_SECCS01 9031#define GCEA_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 9032#define GCEA_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 9033//GCEA_ADDRDEC0_ADDR_MASK_SECCS23 9034#define GCEA_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 9035#define GCEA_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 9036//GCEA_ADDRDEC0_ADDR_CFG_CS01 9037#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2 9038#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 9039#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 9040#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 9041#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 9042#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 9043#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL 9044#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 9045#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 9046#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 9047#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 9048#define GCEA_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 9049//GCEA_ADDRDEC0_ADDR_CFG_CS23 9050#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2 9051#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 9052#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 9053#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 9054#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 9055#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 9056#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL 9057#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 9058#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 9059#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 9060#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 9061#define GCEA_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 9062//GCEA_ADDRDEC0_ADDR_SEL_CS01 9063#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0 9064#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4 9065#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8 9066#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc 9067#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10 9068#define GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 9069#define GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 9070#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 9071#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 9072#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 9073#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 9074#define GCEA_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x000F0000L 9075#define GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 9076#define GCEA_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 9077//GCEA_ADDRDEC0_ADDR_SEL_CS23 9078#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0 9079#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4 9080#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8 9081#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc 9082#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10 9083#define GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 9084#define GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 9085#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 9086#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 9087#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 9088#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 9089#define GCEA_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x000F0000L 9090#define GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 9091#define GCEA_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 9092//GCEA_ADDRDEC0_COL_SEL_LO_CS01 9093#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0 9094#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4 9095#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8 9096#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc 9097#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10 9098#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14 9099#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18 9100#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 9101#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 9102#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 9103#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 9104#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 9105#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 9106#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 9107#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 9108#define GCEA_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 9109//GCEA_ADDRDEC0_COL_SEL_LO_CS23 9110#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0 9111#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4 9112#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8 9113#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc 9114#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10 9115#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14 9116#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18 9117#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 9118#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 9119#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 9120#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 9121#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 9122#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 9123#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 9124#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 9125#define GCEA_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 9126//GCEA_ADDRDEC0_COL_SEL_HI_CS01 9127#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0 9128#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4 9129#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8 9130#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc 9131#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10 9132#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14 9133#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18 9134#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 9135#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 9136#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 9137#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 9138#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 9139#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 9140#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 9141#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 9142#define GCEA_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 9143//GCEA_ADDRDEC0_COL_SEL_HI_CS23 9144#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0 9145#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4 9146#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8 9147#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc 9148#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10 9149#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14 9150#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18 9151#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 9152#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 9153#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 9154#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 9155#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 9156#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 9157#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 9158#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 9159#define GCEA_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 9160//GCEA_ADDRDEC0_RM_SEL_CS01 9161#define GCEA_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0 9162#define GCEA_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4 9163#define GCEA_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8 9164#define GCEA_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 9165#define GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 9166#define GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 9167#define GCEA_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL 9168#define GCEA_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L 9169#define GCEA_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L 9170#define GCEA_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 9171#define GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 9172#define GCEA_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 9173//GCEA_ADDRDEC0_RM_SEL_CS23 9174#define GCEA_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0 9175#define GCEA_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4 9176#define GCEA_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8 9177#define GCEA_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 9178#define GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 9179#define GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 9180#define GCEA_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL 9181#define GCEA_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L 9182#define GCEA_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L 9183#define GCEA_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 9184#define GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 9185#define GCEA_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 9186//GCEA_ADDRDEC0_RM_SEL_SECCS01 9187#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0 9188#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4 9189#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8 9190#define GCEA_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 9191#define GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 9192#define GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 9193#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 9194#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 9195#define GCEA_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 9196#define GCEA_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 9197#define GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 9198#define GCEA_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 9199//GCEA_ADDRDEC0_RM_SEL_SECCS23 9200#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0 9201#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4 9202#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8 9203#define GCEA_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 9204#define GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 9205#define GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 9206#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 9207#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 9208#define GCEA_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 9209#define GCEA_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 9210#define GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 9211#define GCEA_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 9212//GCEA_ADDRDEC1_BASE_ADDR_CS0 9213#define GCEA_ADDRDEC1_BASE_ADDR_CS0__CS_ENABLE__SHIFT 0x0 9214#define GCEA_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 9215#define GCEA_ADDRDEC1_BASE_ADDR_CS0__CS_ENABLE_MASK 0x00000001L 9216#define GCEA_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 9217//GCEA_ADDRDEC1_BASE_ADDR_CS1 9218#define GCEA_ADDRDEC1_BASE_ADDR_CS1__CS_ENABLE__SHIFT 0x0 9219#define GCEA_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 9220#define GCEA_ADDRDEC1_BASE_ADDR_CS1__CS_ENABLE_MASK 0x00000001L 9221#define GCEA_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 9222//GCEA_ADDRDEC1_BASE_ADDR_CS2 9223#define GCEA_ADDRDEC1_BASE_ADDR_CS2__CS_ENABLE__SHIFT 0x0 9224#define GCEA_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 9225#define GCEA_ADDRDEC1_BASE_ADDR_CS2__CS_ENABLE_MASK 0x00000001L 9226#define GCEA_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 9227//GCEA_ADDRDEC1_BASE_ADDR_CS3 9228#define GCEA_ADDRDEC1_BASE_ADDR_CS3__CS_ENABLE__SHIFT 0x0 9229#define GCEA_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 9230#define GCEA_ADDRDEC1_BASE_ADDR_CS3__CS_ENABLE_MASK 0x00000001L 9231#define GCEA_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 9232//GCEA_ADDRDEC1_BASE_ADDR_SECCS0 9233#define GCEA_ADDRDEC1_BASE_ADDR_SECCS0__CS_ENABLE__SHIFT 0x0 9234#define GCEA_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 9235#define GCEA_ADDRDEC1_BASE_ADDR_SECCS0__CS_ENABLE_MASK 0x00000001L 9236#define GCEA_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 9237//GCEA_ADDRDEC1_BASE_ADDR_SECCS1 9238#define GCEA_ADDRDEC1_BASE_ADDR_SECCS1__CS_ENABLE__SHIFT 0x0 9239#define GCEA_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 9240#define GCEA_ADDRDEC1_BASE_ADDR_SECCS1__CS_ENABLE_MASK 0x00000001L 9241#define GCEA_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 9242//GCEA_ADDRDEC1_BASE_ADDR_SECCS2 9243#define GCEA_ADDRDEC1_BASE_ADDR_SECCS2__CS_ENABLE__SHIFT 0x0 9244#define GCEA_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 9245#define GCEA_ADDRDEC1_BASE_ADDR_SECCS2__CS_ENABLE_MASK 0x00000001L 9246#define GCEA_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 9247//GCEA_ADDRDEC1_BASE_ADDR_SECCS3 9248#define GCEA_ADDRDEC1_BASE_ADDR_SECCS3__CS_ENABLE__SHIFT 0x0 9249#define GCEA_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 9250#define GCEA_ADDRDEC1_BASE_ADDR_SECCS3__CS_ENABLE_MASK 0x00000001L 9251#define GCEA_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 9252//GCEA_ADDRDEC1_ADDR_MASK_CS01 9253#define GCEA_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 9254#define GCEA_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 9255//GCEA_ADDRDEC1_ADDR_MASK_CS23 9256#define GCEA_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 9257#define GCEA_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 9258//GCEA_ADDRDEC1_ADDR_MASK_SECCS01 9259#define GCEA_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 9260#define GCEA_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 9261//GCEA_ADDRDEC1_ADDR_MASK_SECCS23 9262#define GCEA_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 9263#define GCEA_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 9264//GCEA_ADDRDEC1_ADDR_CFG_CS01 9265#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2 9266#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 9267#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 9268#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 9269#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 9270#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 9271#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL 9272#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 9273#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 9274#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 9275#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 9276#define GCEA_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 9277//GCEA_ADDRDEC1_ADDR_CFG_CS23 9278#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2 9279#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 9280#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 9281#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 9282#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 9283#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 9284#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL 9285#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 9286#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 9287#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 9288#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 9289#define GCEA_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 9290//GCEA_ADDRDEC1_ADDR_SEL_CS01 9291#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0 9292#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4 9293#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8 9294#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc 9295#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10 9296#define GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 9297#define GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 9298#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 9299#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 9300#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 9301#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 9302#define GCEA_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x000F0000L 9303#define GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 9304#define GCEA_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 9305//GCEA_ADDRDEC1_ADDR_SEL_CS23 9306#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0 9307#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4 9308#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8 9309#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc 9310#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10 9311#define GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 9312#define GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 9313#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 9314#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 9315#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 9316#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 9317#define GCEA_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x000F0000L 9318#define GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 9319#define GCEA_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 9320//GCEA_ADDRDEC1_COL_SEL_LO_CS01 9321#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0 9322#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4 9323#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8 9324#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc 9325#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10 9326#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14 9327#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18 9328#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 9329#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 9330#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 9331#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 9332#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 9333#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 9334#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 9335#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 9336#define GCEA_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 9337//GCEA_ADDRDEC1_COL_SEL_LO_CS23 9338#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0 9339#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4 9340#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8 9341#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc 9342#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10 9343#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14 9344#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18 9345#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 9346#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 9347#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 9348#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 9349#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 9350#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 9351#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 9352#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 9353#define GCEA_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 9354//GCEA_ADDRDEC1_COL_SEL_HI_CS01 9355#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0 9356#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4 9357#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8 9358#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc 9359#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10 9360#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14 9361#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18 9362#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 9363#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 9364#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 9365#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 9366#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 9367#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 9368#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 9369#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 9370#define GCEA_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 9371//GCEA_ADDRDEC1_COL_SEL_HI_CS23 9372#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0 9373#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4 9374#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8 9375#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc 9376#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10 9377#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14 9378#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18 9379#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 9380#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 9381#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 9382#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 9383#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 9384#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 9385#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 9386#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 9387#define GCEA_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 9388//GCEA_ADDRDEC1_RM_SEL_CS01 9389#define GCEA_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0 9390#define GCEA_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4 9391#define GCEA_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8 9392#define GCEA_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 9393#define GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 9394#define GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 9395#define GCEA_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL 9396#define GCEA_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L 9397#define GCEA_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L 9398#define GCEA_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 9399#define GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 9400#define GCEA_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 9401//GCEA_ADDRDEC1_RM_SEL_CS23 9402#define GCEA_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0 9403#define GCEA_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4 9404#define GCEA_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8 9405#define GCEA_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 9406#define GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 9407#define GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 9408#define GCEA_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL 9409#define GCEA_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L 9410#define GCEA_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L 9411#define GCEA_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 9412#define GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 9413#define GCEA_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 9414//GCEA_ADDRDEC1_RM_SEL_SECCS01 9415#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0 9416#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4 9417#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8 9418#define GCEA_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 9419#define GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 9420#define GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 9421#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 9422#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 9423#define GCEA_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 9424#define GCEA_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 9425#define GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 9426#define GCEA_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 9427//GCEA_ADDRDEC1_RM_SEL_SECCS23 9428#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0 9429#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4 9430#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8 9431#define GCEA_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 9432#define GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 9433#define GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 9434#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 9435#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 9436#define GCEA_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 9437#define GCEA_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 9438#define GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 9439#define GCEA_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 9440//GCEA_IO_RD_CLI2GRP_MAP0 9441#define GCEA_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 9442#define GCEA_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 9443#define GCEA_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 9444#define GCEA_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 9445#define GCEA_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 9446#define GCEA_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 9447#define GCEA_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 9448#define GCEA_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 9449#define GCEA_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 9450#define GCEA_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 9451#define GCEA_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 9452#define GCEA_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 9453#define GCEA_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 9454#define GCEA_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 9455#define GCEA_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 9456#define GCEA_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 9457#define GCEA_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 9458#define GCEA_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 9459#define GCEA_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 9460#define GCEA_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 9461#define GCEA_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 9462#define GCEA_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 9463#define GCEA_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 9464#define GCEA_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 9465#define GCEA_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 9466#define GCEA_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 9467#define GCEA_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 9468#define GCEA_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 9469#define GCEA_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 9470#define GCEA_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 9471#define GCEA_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 9472#define GCEA_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 9473//GCEA_IO_RD_CLI2GRP_MAP1 9474#define GCEA_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 9475#define GCEA_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 9476#define GCEA_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 9477#define GCEA_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 9478#define GCEA_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 9479#define GCEA_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 9480#define GCEA_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 9481#define GCEA_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 9482#define GCEA_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 9483#define GCEA_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 9484#define GCEA_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 9485#define GCEA_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 9486#define GCEA_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 9487#define GCEA_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 9488#define GCEA_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 9489#define GCEA_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 9490#define GCEA_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 9491#define GCEA_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 9492#define GCEA_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 9493#define GCEA_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 9494#define GCEA_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 9495#define GCEA_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 9496#define GCEA_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 9497#define GCEA_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 9498#define GCEA_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 9499#define GCEA_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 9500#define GCEA_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 9501#define GCEA_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 9502#define GCEA_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 9503#define GCEA_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 9504#define GCEA_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 9505#define GCEA_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 9506//GCEA_IO_WR_CLI2GRP_MAP0 9507#define GCEA_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 9508#define GCEA_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 9509#define GCEA_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 9510#define GCEA_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 9511#define GCEA_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 9512#define GCEA_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 9513#define GCEA_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 9514#define GCEA_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 9515#define GCEA_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 9516#define GCEA_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 9517#define GCEA_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 9518#define GCEA_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 9519#define GCEA_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 9520#define GCEA_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 9521#define GCEA_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 9522#define GCEA_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 9523#define GCEA_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 9524#define GCEA_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 9525#define GCEA_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 9526#define GCEA_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 9527#define GCEA_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 9528#define GCEA_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 9529#define GCEA_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 9530#define GCEA_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 9531#define GCEA_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 9532#define GCEA_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 9533#define GCEA_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 9534#define GCEA_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 9535#define GCEA_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 9536#define GCEA_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 9537#define GCEA_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 9538#define GCEA_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 9539//GCEA_IO_WR_CLI2GRP_MAP1 9540#define GCEA_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 9541#define GCEA_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 9542#define GCEA_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 9543#define GCEA_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 9544#define GCEA_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 9545#define GCEA_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 9546#define GCEA_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 9547#define GCEA_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 9548#define GCEA_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 9549#define GCEA_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 9550#define GCEA_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 9551#define GCEA_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 9552#define GCEA_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 9553#define GCEA_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 9554#define GCEA_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 9555#define GCEA_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 9556#define GCEA_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 9557#define GCEA_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 9558#define GCEA_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 9559#define GCEA_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 9560#define GCEA_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 9561#define GCEA_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 9562#define GCEA_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 9563#define GCEA_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 9564#define GCEA_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 9565#define GCEA_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 9566#define GCEA_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 9567#define GCEA_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 9568#define GCEA_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 9569#define GCEA_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 9570#define GCEA_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 9571#define GCEA_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 9572//GCEA_IO_RD_COMBINE_FLUSH 9573#define GCEA_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 9574#define GCEA_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 9575#define GCEA_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 9576#define GCEA_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc 9577#define GCEA_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL 9578#define GCEA_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L 9579#define GCEA_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L 9580#define GCEA_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L 9581//GCEA_IO_WR_COMBINE_FLUSH 9582#define GCEA_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 9583#define GCEA_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 9584#define GCEA_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 9585#define GCEA_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc 9586#define GCEA_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL 9587#define GCEA_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L 9588#define GCEA_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L 9589#define GCEA_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L 9590//GCEA_IO_GROUP_BURST 9591#define GCEA_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 9592#define GCEA_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 9593#define GCEA_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 9594#define GCEA_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 9595#define GCEA_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL 9596#define GCEA_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 9597#define GCEA_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 9598#define GCEA_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L 9599//GCEA_IO_RD_PRI_AGE 9600#define GCEA_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 9601#define GCEA_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 9602#define GCEA_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 9603#define GCEA_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 9604#define GCEA_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 9605#define GCEA_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 9606#define GCEA_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 9607#define GCEA_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 9608#define GCEA_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 9609#define GCEA_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 9610#define GCEA_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 9611#define GCEA_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 9612#define GCEA_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 9613#define GCEA_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 9614#define GCEA_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 9615#define GCEA_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 9616//GCEA_IO_WR_PRI_AGE 9617#define GCEA_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 9618#define GCEA_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 9619#define GCEA_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 9620#define GCEA_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 9621#define GCEA_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 9622#define GCEA_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 9623#define GCEA_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 9624#define GCEA_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 9625#define GCEA_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 9626#define GCEA_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 9627#define GCEA_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 9628#define GCEA_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 9629#define GCEA_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 9630#define GCEA_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 9631#define GCEA_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 9632#define GCEA_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 9633//GCEA_IO_RD_PRI_QUEUING 9634#define GCEA_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 9635#define GCEA_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 9636#define GCEA_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 9637#define GCEA_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 9638#define GCEA_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 9639#define GCEA_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 9640#define GCEA_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 9641#define GCEA_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 9642//GCEA_IO_WR_PRI_QUEUING 9643#define GCEA_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 9644#define GCEA_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 9645#define GCEA_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 9646#define GCEA_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 9647#define GCEA_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 9648#define GCEA_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 9649#define GCEA_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 9650#define GCEA_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 9651//GCEA_IO_RD_PRI_FIXED 9652#define GCEA_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 9653#define GCEA_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 9654#define GCEA_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 9655#define GCEA_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 9656#define GCEA_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 9657#define GCEA_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 9658#define GCEA_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 9659#define GCEA_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 9660//GCEA_IO_WR_PRI_FIXED 9661#define GCEA_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 9662#define GCEA_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 9663#define GCEA_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 9664#define GCEA_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 9665#define GCEA_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 9666#define GCEA_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 9667#define GCEA_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 9668#define GCEA_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 9669//GCEA_IO_RD_PRI_URGENCY 9670#define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 9671#define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 9672#define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 9673#define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 9674#define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 9675#define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 9676#define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 9677#define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 9678#define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 9679#define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 9680#define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 9681#define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 9682#define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 9683#define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 9684#define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 9685#define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 9686//GCEA_IO_WR_PRI_URGENCY 9687#define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 9688#define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 9689#define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 9690#define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 9691#define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 9692#define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 9693#define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 9694#define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 9695#define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 9696#define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 9697#define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 9698#define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 9699#define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 9700#define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 9701#define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 9702#define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 9703//GCEA_IO_RD_PRI_URGENCY_MASK 9704#define GCEA_IO_RD_PRI_URGENCY_MASK__CID0_MASK__SHIFT 0x0 9705#define GCEA_IO_RD_PRI_URGENCY_MASK__CID1_MASK__SHIFT 0x1 9706#define GCEA_IO_RD_PRI_URGENCY_MASK__CID2_MASK__SHIFT 0x2 9707#define GCEA_IO_RD_PRI_URGENCY_MASK__CID3_MASK__SHIFT 0x3 9708#define GCEA_IO_RD_PRI_URGENCY_MASK__CID4_MASK__SHIFT 0x4 9709#define GCEA_IO_RD_PRI_URGENCY_MASK__CID5_MASK__SHIFT 0x5 9710#define GCEA_IO_RD_PRI_URGENCY_MASK__CID6_MASK__SHIFT 0x6 9711#define GCEA_IO_RD_PRI_URGENCY_MASK__CID7_MASK__SHIFT 0x7 9712#define GCEA_IO_RD_PRI_URGENCY_MASK__CID8_MASK__SHIFT 0x8 9713#define GCEA_IO_RD_PRI_URGENCY_MASK__CID9_MASK__SHIFT 0x9 9714#define GCEA_IO_RD_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0xa 9715#define GCEA_IO_RD_PRI_URGENCY_MASK__CID11_MASK__SHIFT 0xb 9716#define GCEA_IO_RD_PRI_URGENCY_MASK__CID12_MASK__SHIFT 0xc 9717#define GCEA_IO_RD_PRI_URGENCY_MASK__CID13_MASK__SHIFT 0xd 9718#define GCEA_IO_RD_PRI_URGENCY_MASK__CID14_MASK__SHIFT 0xe 9719#define GCEA_IO_RD_PRI_URGENCY_MASK__CID15_MASK__SHIFT 0xf 9720#define GCEA_IO_RD_PRI_URGENCY_MASK__CID16_MASK__SHIFT 0x10 9721#define GCEA_IO_RD_PRI_URGENCY_MASK__CID17_MASK__SHIFT 0x11 9722#define GCEA_IO_RD_PRI_URGENCY_MASK__CID18_MASK__SHIFT 0x12 9723#define GCEA_IO_RD_PRI_URGENCY_MASK__CID19_MASK__SHIFT 0x13 9724#define GCEA_IO_RD_PRI_URGENCY_MASK__CID20_MASK__SHIFT 0x14 9725#define GCEA_IO_RD_PRI_URGENCY_MASK__CID21_MASK__SHIFT 0x15 9726#define GCEA_IO_RD_PRI_URGENCY_MASK__CID22_MASK__SHIFT 0x16 9727#define GCEA_IO_RD_PRI_URGENCY_MASK__CID23_MASK__SHIFT 0x17 9728#define GCEA_IO_RD_PRI_URGENCY_MASK__CID24_MASK__SHIFT 0x18 9729#define GCEA_IO_RD_PRI_URGENCY_MASK__CID25_MASK__SHIFT 0x19 9730#define GCEA_IO_RD_PRI_URGENCY_MASK__CID26_MASK__SHIFT 0x1a 9731#define GCEA_IO_RD_PRI_URGENCY_MASK__CID27_MASK__SHIFT 0x1b 9732#define GCEA_IO_RD_PRI_URGENCY_MASK__CID28_MASK__SHIFT 0x1c 9733#define GCEA_IO_RD_PRI_URGENCY_MASK__CID29_MASK__SHIFT 0x1d 9734#define GCEA_IO_RD_PRI_URGENCY_MASK__CID30_MASK__SHIFT 0x1e 9735#define GCEA_IO_RD_PRI_URGENCY_MASK__CID31_MASK__SHIFT 0x1f 9736#define GCEA_IO_RD_PRI_URGENCY_MASK__CID0_MASK_MASK 0x00000001L 9737#define GCEA_IO_RD_PRI_URGENCY_MASK__CID1_MASK_MASK 0x00000002L 9738#define GCEA_IO_RD_PRI_URGENCY_MASK__CID2_MASK_MASK 0x00000004L 9739#define GCEA_IO_RD_PRI_URGENCY_MASK__CID3_MASK_MASK 0x00000008L 9740#define GCEA_IO_RD_PRI_URGENCY_MASK__CID4_MASK_MASK 0x00000010L 9741#define GCEA_IO_RD_PRI_URGENCY_MASK__CID5_MASK_MASK 0x00000020L 9742#define GCEA_IO_RD_PRI_URGENCY_MASK__CID6_MASK_MASK 0x00000040L 9743#define GCEA_IO_RD_PRI_URGENCY_MASK__CID7_MASK_MASK 0x00000080L 9744#define GCEA_IO_RD_PRI_URGENCY_MASK__CID8_MASK_MASK 0x00000100L 9745#define GCEA_IO_RD_PRI_URGENCY_MASK__CID9_MASK_MASK 0x00000200L 9746#define GCEA_IO_RD_PRI_URGENCY_MASK__CID10_MASK_MASK 0x00000400L 9747#define GCEA_IO_RD_PRI_URGENCY_MASK__CID11_MASK_MASK 0x00000800L 9748#define GCEA_IO_RD_PRI_URGENCY_MASK__CID12_MASK_MASK 0x00001000L 9749#define GCEA_IO_RD_PRI_URGENCY_MASK__CID13_MASK_MASK 0x00002000L 9750#define GCEA_IO_RD_PRI_URGENCY_MASK__CID14_MASK_MASK 0x00004000L 9751#define GCEA_IO_RD_PRI_URGENCY_MASK__CID15_MASK_MASK 0x00008000L 9752#define GCEA_IO_RD_PRI_URGENCY_MASK__CID16_MASK_MASK 0x00010000L 9753#define GCEA_IO_RD_PRI_URGENCY_MASK__CID17_MASK_MASK 0x00020000L 9754#define GCEA_IO_RD_PRI_URGENCY_MASK__CID18_MASK_MASK 0x00040000L 9755#define GCEA_IO_RD_PRI_URGENCY_MASK__CID19_MASK_MASK 0x00080000L 9756#define GCEA_IO_RD_PRI_URGENCY_MASK__CID20_MASK_MASK 0x00100000L 9757#define GCEA_IO_RD_PRI_URGENCY_MASK__CID21_MASK_MASK 0x00200000L 9758#define GCEA_IO_RD_PRI_URGENCY_MASK__CID22_MASK_MASK 0x00400000L 9759#define GCEA_IO_RD_PRI_URGENCY_MASK__CID23_MASK_MASK 0x00800000L 9760#define GCEA_IO_RD_PRI_URGENCY_MASK__CID24_MASK_MASK 0x01000000L 9761#define GCEA_IO_RD_PRI_URGENCY_MASK__CID25_MASK_MASK 0x02000000L 9762#define GCEA_IO_RD_PRI_URGENCY_MASK__CID26_MASK_MASK 0x04000000L 9763#define GCEA_IO_RD_PRI_URGENCY_MASK__CID27_MASK_MASK 0x08000000L 9764#define GCEA_IO_RD_PRI_URGENCY_MASK__CID28_MASK_MASK 0x10000000L 9765#define GCEA_IO_RD_PRI_URGENCY_MASK__CID29_MASK_MASK 0x20000000L 9766#define GCEA_IO_RD_PRI_URGENCY_MASK__CID30_MASK_MASK 0x40000000L 9767#define GCEA_IO_RD_PRI_URGENCY_MASK__CID31_MASK_MASK 0x80000000L 9768//GCEA_IO_WR_PRI_URGENCY_MASK 9769#define GCEA_IO_WR_PRI_URGENCY_MASK__CID0_MASK__SHIFT 0x0 9770#define GCEA_IO_WR_PRI_URGENCY_MASK__CID1_MASK__SHIFT 0x1 9771#define GCEA_IO_WR_PRI_URGENCY_MASK__CID2_MASK__SHIFT 0x2 9772#define GCEA_IO_WR_PRI_URGENCY_MASK__CID3_MASK__SHIFT 0x3 9773#define GCEA_IO_WR_PRI_URGENCY_MASK__CID4_MASK__SHIFT 0x4 9774#define GCEA_IO_WR_PRI_URGENCY_MASK__CID5_MASK__SHIFT 0x5 9775#define GCEA_IO_WR_PRI_URGENCY_MASK__CID6_MASK__SHIFT 0x6 9776#define GCEA_IO_WR_PRI_URGENCY_MASK__CID7_MASK__SHIFT 0x7 9777#define GCEA_IO_WR_PRI_URGENCY_MASK__CID8_MASK__SHIFT 0x8 9778#define GCEA_IO_WR_PRI_URGENCY_MASK__CID9_MASK__SHIFT 0x9 9779#define GCEA_IO_WR_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0xa 9780#define GCEA_IO_WR_PRI_URGENCY_MASK__CID11_MASK__SHIFT 0xb 9781#define GCEA_IO_WR_PRI_URGENCY_MASK__CID12_MASK__SHIFT 0xc 9782#define GCEA_IO_WR_PRI_URGENCY_MASK__CID13_MASK__SHIFT 0xd 9783#define GCEA_IO_WR_PRI_URGENCY_MASK__CID14_MASK__SHIFT 0xe 9784#define GCEA_IO_WR_PRI_URGENCY_MASK__CID15_MASK__SHIFT 0xf 9785#define GCEA_IO_WR_PRI_URGENCY_MASK__CID16_MASK__SHIFT 0x10 9786#define GCEA_IO_WR_PRI_URGENCY_MASK__CID17_MASK__SHIFT 0x11 9787#define GCEA_IO_WR_PRI_URGENCY_MASK__CID18_MASK__SHIFT 0x12 9788#define GCEA_IO_WR_PRI_URGENCY_MASK__CID19_MASK__SHIFT 0x13 9789#define GCEA_IO_WR_PRI_URGENCY_MASK__CID20_MASK__SHIFT 0x14 9790#define GCEA_IO_WR_PRI_URGENCY_MASK__CID21_MASK__SHIFT 0x15 9791#define GCEA_IO_WR_PRI_URGENCY_MASK__CID22_MASK__SHIFT 0x16 9792#define GCEA_IO_WR_PRI_URGENCY_MASK__CID23_MASK__SHIFT 0x17 9793#define GCEA_IO_WR_PRI_URGENCY_MASK__CID24_MASK__SHIFT 0x18 9794#define GCEA_IO_WR_PRI_URGENCY_MASK__CID25_MASK__SHIFT 0x19 9795#define GCEA_IO_WR_PRI_URGENCY_MASK__CID26_MASK__SHIFT 0x1a 9796#define GCEA_IO_WR_PRI_URGENCY_MASK__CID27_MASK__SHIFT 0x1b 9797#define GCEA_IO_WR_PRI_URGENCY_MASK__CID28_MASK__SHIFT 0x1c 9798#define GCEA_IO_WR_PRI_URGENCY_MASK__CID29_MASK__SHIFT 0x1d 9799#define GCEA_IO_WR_PRI_URGENCY_MASK__CID30_MASK__SHIFT 0x1e 9800#define GCEA_IO_WR_PRI_URGENCY_MASK__CID31_MASK__SHIFT 0x1f 9801#define GCEA_IO_WR_PRI_URGENCY_MASK__CID0_MASK_MASK 0x00000001L 9802#define GCEA_IO_WR_PRI_URGENCY_MASK__CID1_MASK_MASK 0x00000002L 9803#define GCEA_IO_WR_PRI_URGENCY_MASK__CID2_MASK_MASK 0x00000004L 9804#define GCEA_IO_WR_PRI_URGENCY_MASK__CID3_MASK_MASK 0x00000008L 9805#define GCEA_IO_WR_PRI_URGENCY_MASK__CID4_MASK_MASK 0x00000010L 9806#define GCEA_IO_WR_PRI_URGENCY_MASK__CID5_MASK_MASK 0x00000020L 9807#define GCEA_IO_WR_PRI_URGENCY_MASK__CID6_MASK_MASK 0x00000040L 9808#define GCEA_IO_WR_PRI_URGENCY_MASK__CID7_MASK_MASK 0x00000080L 9809#define GCEA_IO_WR_PRI_URGENCY_MASK__CID8_MASK_MASK 0x00000100L 9810#define GCEA_IO_WR_PRI_URGENCY_MASK__CID9_MASK_MASK 0x00000200L 9811#define GCEA_IO_WR_PRI_URGENCY_MASK__CID10_MASK_MASK 0x00000400L 9812#define GCEA_IO_WR_PRI_URGENCY_MASK__CID11_MASK_MASK 0x00000800L 9813#define GCEA_IO_WR_PRI_URGENCY_MASK__CID12_MASK_MASK 0x00001000L 9814#define GCEA_IO_WR_PRI_URGENCY_MASK__CID13_MASK_MASK 0x00002000L 9815#define GCEA_IO_WR_PRI_URGENCY_MASK__CID14_MASK_MASK 0x00004000L 9816#define GCEA_IO_WR_PRI_URGENCY_MASK__CID15_MASK_MASK 0x00008000L 9817#define GCEA_IO_WR_PRI_URGENCY_MASK__CID16_MASK_MASK 0x00010000L 9818#define GCEA_IO_WR_PRI_URGENCY_MASK__CID17_MASK_MASK 0x00020000L 9819#define GCEA_IO_WR_PRI_URGENCY_MASK__CID18_MASK_MASK 0x00040000L 9820#define GCEA_IO_WR_PRI_URGENCY_MASK__CID19_MASK_MASK 0x00080000L 9821#define GCEA_IO_WR_PRI_URGENCY_MASK__CID20_MASK_MASK 0x00100000L 9822#define GCEA_IO_WR_PRI_URGENCY_MASK__CID21_MASK_MASK 0x00200000L 9823#define GCEA_IO_WR_PRI_URGENCY_MASK__CID22_MASK_MASK 0x00400000L 9824#define GCEA_IO_WR_PRI_URGENCY_MASK__CID23_MASK_MASK 0x00800000L 9825#define GCEA_IO_WR_PRI_URGENCY_MASK__CID24_MASK_MASK 0x01000000L 9826#define GCEA_IO_WR_PRI_URGENCY_MASK__CID25_MASK_MASK 0x02000000L 9827#define GCEA_IO_WR_PRI_URGENCY_MASK__CID26_MASK_MASK 0x04000000L 9828#define GCEA_IO_WR_PRI_URGENCY_MASK__CID27_MASK_MASK 0x08000000L 9829#define GCEA_IO_WR_PRI_URGENCY_MASK__CID28_MASK_MASK 0x10000000L 9830#define GCEA_IO_WR_PRI_URGENCY_MASK__CID29_MASK_MASK 0x20000000L 9831#define GCEA_IO_WR_PRI_URGENCY_MASK__CID30_MASK_MASK 0x40000000L 9832#define GCEA_IO_WR_PRI_URGENCY_MASK__CID31_MASK_MASK 0x80000000L 9833//GCEA_IO_RD_PRI_QUANT_PRI1 9834#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 9835#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 9836#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 9837#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 9838#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 9839#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 9840#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 9841#define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 9842//GCEA_IO_RD_PRI_QUANT_PRI2 9843#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 9844#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 9845#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 9846#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 9847#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 9848#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 9849#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 9850#define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 9851//GCEA_IO_RD_PRI_QUANT_PRI3 9852#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 9853#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 9854#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 9855#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 9856#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 9857#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 9858#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 9859#define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 9860//GCEA_IO_WR_PRI_QUANT_PRI1 9861#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 9862#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 9863#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 9864#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 9865#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 9866#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 9867#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 9868#define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 9869//GCEA_IO_WR_PRI_QUANT_PRI2 9870#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 9871#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 9872#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 9873#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 9874#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 9875#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 9876#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 9877#define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 9878//GCEA_IO_WR_PRI_QUANT_PRI3 9879#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 9880#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 9881#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 9882#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 9883#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 9884#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 9885#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 9886#define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 9887//GCEA_SDP_ARB_DRAM 9888#define GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 9889#define GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 9890#define GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10 9891#define GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11 9892#define GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12 9893#define GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13 9894#define GCEA_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14 9895#define GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL 9896#define GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L 9897#define GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L 9898#define GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L 9899#define GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L 9900#define GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L 9901#define GCEA_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L 9902//GCEA_SDP_ARB_FINAL 9903#define GCEA_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 9904#define GCEA_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 9905#define GCEA_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa 9906#define GCEA_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf 9907#define GCEA_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 9908#define GCEA_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 9909#define GCEA_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 9910#define GCEA_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 9911#define GCEA_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 9912#define GCEA_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 9913#define GCEA_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 9914#define GCEA_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 9915#define GCEA_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 9916#define GCEA_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a 9917#define GCEA_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL 9918#define GCEA_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L 9919#define GCEA_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L 9920#define GCEA_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L 9921#define GCEA_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L 9922#define GCEA_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L 9923#define GCEA_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L 9924#define GCEA_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L 9925#define GCEA_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L 9926#define GCEA_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L 9927#define GCEA_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L 9928#define GCEA_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L 9929#define GCEA_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L 9930#define GCEA_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L 9931//GCEA_SDP_DRAM_PRIORITY 9932#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 9933#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 9934#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 9935#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 9936#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 9937#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 9938#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 9939#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 9940#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 9941#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 9942#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 9943#define GCEA_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 9944#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 9945#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 9946#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 9947#define GCEA_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 9948//GCEA_SDP_IO_PRIORITY 9949#define GCEA_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 9950#define GCEA_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 9951#define GCEA_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 9952#define GCEA_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 9953#define GCEA_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 9954#define GCEA_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 9955#define GCEA_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 9956#define GCEA_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 9957#define GCEA_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 9958#define GCEA_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 9959#define GCEA_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 9960#define GCEA_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 9961#define GCEA_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 9962#define GCEA_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 9963#define GCEA_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 9964#define GCEA_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 9965//GCEA_SDP_CREDITS 9966#define GCEA_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 9967#define GCEA_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 9968#define GCEA_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 9969#define GCEA_SDP_CREDITS__PRB_REQ_CREDITS__SHIFT 0x18 9970#define GCEA_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL 9971#define GCEA_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L 9972#define GCEA_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L 9973#define GCEA_SDP_CREDITS__PRB_REQ_CREDITS_MASK 0x3F000000L 9974//GCEA_SDP_TAG_RESERVE0 9975#define GCEA_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 9976#define GCEA_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 9977#define GCEA_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 9978#define GCEA_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 9979#define GCEA_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL 9980#define GCEA_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L 9981#define GCEA_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L 9982#define GCEA_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L 9983//GCEA_SDP_TAG_RESERVE1 9984#define GCEA_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 9985#define GCEA_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 9986#define GCEA_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 9987#define GCEA_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 9988#define GCEA_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL 9989#define GCEA_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L 9990#define GCEA_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L 9991#define GCEA_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L 9992//GCEA_SDP_VCC_RESERVE0 9993#define GCEA_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 9994#define GCEA_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 9995#define GCEA_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc 9996#define GCEA_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 9997#define GCEA_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 9998#define GCEA_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 9999#define GCEA_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 10000#define GCEA_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L
10001#define GCEA_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 10002#define GCEA_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 10003//GCEA_SDP_VCC_RESERVE1 10004#define GCEA_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 10005#define GCEA_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 10006#define GCEA_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc 10007#define GCEA_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f 10008#define GCEA_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 10009#define GCEA_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 10010#define GCEA_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 10011#define GCEA_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L 10012//GCEA_SDP_VCD_RESERVE0 10013#define GCEA_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 10014#define GCEA_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 10015#define GCEA_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc 10016#define GCEA_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 10017#define GCEA_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 10018#define GCEA_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 10019#define GCEA_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 10020#define GCEA_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 10021#define GCEA_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 10022#define GCEA_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 10023//GCEA_SDP_VCD_RESERVE1 10024#define GCEA_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 10025#define GCEA_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 10026#define GCEA_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc 10027#define GCEA_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f 10028#define GCEA_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 10029#define GCEA_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 10030#define GCEA_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 10031#define GCEA_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L 10032//GCEA_SDP_REQ_CNTL 10033#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 10034#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 10035#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 10036#define GCEA_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 10037#define GCEA_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x4 10038#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L 10039#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L 10040#define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L 10041#define GCEA_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L 10042#define GCEA_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000010L 10043//GCEA_MISC 10044#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 10045#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 10046#define GCEA_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 10047#define GCEA_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 10048#define GCEA_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 10049#define GCEA_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 10050#define GCEA_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6 10051#define GCEA_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7 10052#define GCEA_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8 10053#define GCEA_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9 10054#define GCEA_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa 10055#define GCEA_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb 10056#define GCEA_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc 10057#define GCEA_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd 10058#define GCEA_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe 10059#define GCEA_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf 10060#define GCEA_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11 10061#define GCEA_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13 10062#define GCEA_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15 10063#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a 10064#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b 10065#define GCEA_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c 10066#define GCEA_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d 10067#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e 10068#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f 10069#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L 10070#define GCEA_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L 10071#define GCEA_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L 10072#define GCEA_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L 10073#define GCEA_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L 10074#define GCEA_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L 10075#define GCEA_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L 10076#define GCEA_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L 10077#define GCEA_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L 10078#define GCEA_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L 10079#define GCEA_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L 10080#define GCEA_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L 10081#define GCEA_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L 10082#define GCEA_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L 10083#define GCEA_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L 10084#define GCEA_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L 10085#define GCEA_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L 10086#define GCEA_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L 10087#define GCEA_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L 10088#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L 10089#define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L 10090#define GCEA_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L 10091#define GCEA_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L 10092#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L 10093#define GCEA_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L 10094//GCEA_LATENCY_SAMPLING 10095#define GCEA_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 10096#define GCEA_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 10097#define GCEA_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 10098#define GCEA_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 10099#define GCEA_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 10100#define GCEA_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 10101#define GCEA_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 10102#define GCEA_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 10103#define GCEA_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 10104#define GCEA_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 10105#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa 10106#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb 10107#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc 10108#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd 10109#define GCEA_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe 10110#define GCEA_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 10111#define GCEA_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L 10112#define GCEA_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L 10113#define GCEA_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L 10114#define GCEA_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L 10115#define GCEA_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L 10116#define GCEA_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L 10117#define GCEA_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L 10118#define GCEA_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L 10119#define GCEA_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L 10120#define GCEA_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L 10121#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L 10122#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L 10123#define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L 10124#define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L 10125#define GCEA_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L 10126#define GCEA_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L 10127//GCEA_PERFCOUNTER_LO 10128#define GCEA_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 10129#define GCEA_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 10130//GCEA_PERFCOUNTER_HI 10131#define GCEA_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 10132#define GCEA_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 10133#define GCEA_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 10134#define GCEA_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 10135//GCEA_PERFCOUNTER0_CFG 10136#define GCEA_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 10137#define GCEA_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 10138#define GCEA_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 10139#define GCEA_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 10140#define GCEA_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 10141#define GCEA_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 10142#define GCEA_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 10143#define GCEA_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 10144#define GCEA_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 10145#define GCEA_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 10146//GCEA_PERFCOUNTER1_CFG 10147#define GCEA_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 10148#define GCEA_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 10149#define GCEA_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 10150#define GCEA_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 10151#define GCEA_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 10152#define GCEA_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 10153#define GCEA_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 10154#define GCEA_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 10155#define GCEA_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 10156#define GCEA_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 10157//GCEA_PERFCOUNTER_RSLT_CNTL 10158#define GCEA_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 10159#define GCEA_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 10160#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 10161#define GCEA_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 10162#define GCEA_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 10163#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 10164#define GCEA_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 10165#define GCEA_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 10166#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 10167#define GCEA_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 10168#define GCEA_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 10169#define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 10170 10171 10172// addressBlock: gc_tcdec 10173//TCP_INVALIDATE 10174#define TCP_INVALIDATE__START__SHIFT 0x0 10175#define TCP_INVALIDATE__START_MASK 0x00000001L 10176//TCP_STATUS 10177#define TCP_STATUS__TCP_BUSY__SHIFT 0x0 10178#define TCP_STATUS__INPUT_BUSY__SHIFT 0x1 10179#define TCP_STATUS__ADRS_BUSY__SHIFT 0x2 10180#define TCP_STATUS__TAGRAMS_BUSY__SHIFT 0x3 10181#define TCP_STATUS__CNTRL_BUSY__SHIFT 0x4 10182#define TCP_STATUS__LFIFO_BUSY__SHIFT 0x5 10183#define TCP_STATUS__READ_BUSY__SHIFT 0x6 10184#define TCP_STATUS__FORMAT_BUSY__SHIFT 0x7 10185#define TCP_STATUS__VM_BUSY__SHIFT 0x8 10186#define TCP_STATUS__TCP_BUSY_MASK 0x00000001L 10187#define TCP_STATUS__INPUT_BUSY_MASK 0x00000002L 10188#define TCP_STATUS__ADRS_BUSY_MASK 0x00000004L 10189#define TCP_STATUS__TAGRAMS_BUSY_MASK 0x00000008L 10190#define TCP_STATUS__CNTRL_BUSY_MASK 0x00000010L 10191#define TCP_STATUS__LFIFO_BUSY_MASK 0x00000020L 10192#define TCP_STATUS__READ_BUSY_MASK 0x00000040L 10193#define TCP_STATUS__FORMAT_BUSY_MASK 0x00000080L 10194#define TCP_STATUS__VM_BUSY_MASK 0x00000100L 10195//TCP_CNTL 10196#define TCP_CNTL__FORCE_HIT__SHIFT 0x0 10197#define TCP_CNTL__FORCE_MISS__SHIFT 0x1 10198#define TCP_CNTL__L1_SIZE__SHIFT 0x2 10199#define TCP_CNTL__FLAT_BUF_HASH_ENABLE__SHIFT 0x4 10200#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE__SHIFT 0x5 10201#define TCP_CNTL__FORCE_EOW_TOTAL_CNT__SHIFT 0xf 10202#define TCP_CNTL__FORCE_EOW_TAGRAM_CNT__SHIFT 0x16 10203#define TCP_CNTL__DISABLE_Z_MAP__SHIFT 0x1c 10204#define TCP_CNTL__INV_ALL_VMIDS__SHIFT 0x1d 10205#define TCP_CNTL__ASTC_VE_MSB_TOLERANT__SHIFT 0x1e 10206#define TCP_CNTL__FORCE_HIT_MASK 0x00000001L 10207#define TCP_CNTL__FORCE_MISS_MASK 0x00000002L 10208#define TCP_CNTL__L1_SIZE_MASK 0x0000000CL 10209#define TCP_CNTL__FLAT_BUF_HASH_ENABLE_MASK 0x00000010L 10210#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE_MASK 0x00000020L 10211#define TCP_CNTL__FORCE_EOW_TOTAL_CNT_MASK 0x001F8000L 10212#define TCP_CNTL__FORCE_EOW_TAGRAM_CNT_MASK 0x0FC00000L 10213#define TCP_CNTL__DISABLE_Z_MAP_MASK 0x10000000L 10214#define TCP_CNTL__INV_ALL_VMIDS_MASK 0x20000000L 10215#define TCP_CNTL__ASTC_VE_MSB_TOLERANT_MASK 0x40000000L 10216//TCP_CHAN_STEER_LO 10217#define TCP_CHAN_STEER_LO__CHAN0__SHIFT 0x0 10218#define TCP_CHAN_STEER_LO__CHAN1__SHIFT 0x4 10219#define TCP_CHAN_STEER_LO__CHAN2__SHIFT 0x8 10220#define TCP_CHAN_STEER_LO__CHAN3__SHIFT 0xc 10221#define TCP_CHAN_STEER_LO__CHAN4__SHIFT 0x10 10222#define TCP_CHAN_STEER_LO__CHAN5__SHIFT 0x14 10223#define TCP_CHAN_STEER_LO__CHAN6__SHIFT 0x18 10224#define TCP_CHAN_STEER_LO__CHAN7__SHIFT 0x1c 10225#define TCP_CHAN_STEER_LO__CHAN0_MASK 0x0000000FL 10226#define TCP_CHAN_STEER_LO__CHAN1_MASK 0x000000F0L 10227#define TCP_CHAN_STEER_LO__CHAN2_MASK 0x00000F00L 10228#define TCP_CHAN_STEER_LO__CHAN3_MASK 0x0000F000L 10229#define TCP_CHAN_STEER_LO__CHAN4_MASK 0x000F0000L 10230#define TCP_CHAN_STEER_LO__CHAN5_MASK 0x00F00000L 10231#define TCP_CHAN_STEER_LO__CHAN6_MASK 0x0F000000L 10232#define TCP_CHAN_STEER_LO__CHAN7_MASK 0xF0000000L 10233//TCP_CHAN_STEER_HI 10234#define TCP_CHAN_STEER_HI__CHAN8__SHIFT 0x0 10235#define TCP_CHAN_STEER_HI__CHAN9__SHIFT 0x4 10236#define TCP_CHAN_STEER_HI__CHANA__SHIFT 0x8 10237#define TCP_CHAN_STEER_HI__CHANB__SHIFT 0xc 10238#define TCP_CHAN_STEER_HI__CHANC__SHIFT 0x10 10239#define TCP_CHAN_STEER_HI__CHAND__SHIFT 0x14 10240#define TCP_CHAN_STEER_HI__CHANE__SHIFT 0x18 10241#define TCP_CHAN_STEER_HI__CHANF__SHIFT 0x1c 10242#define TCP_CHAN_STEER_HI__CHAN8_MASK 0x0000000FL 10243#define TCP_CHAN_STEER_HI__CHAN9_MASK 0x000000F0L 10244#define TCP_CHAN_STEER_HI__CHANA_MASK 0x00000F00L 10245#define TCP_CHAN_STEER_HI__CHANB_MASK 0x0000F000L 10246#define TCP_CHAN_STEER_HI__CHANC_MASK 0x000F0000L 10247#define TCP_CHAN_STEER_HI__CHAND_MASK 0x00F00000L 10248#define TCP_CHAN_STEER_HI__CHANE_MASK 0x0F000000L 10249#define TCP_CHAN_STEER_HI__CHANF_MASK 0xF0000000L 10250//TCP_ADDR_CONFIG 10251#define TCP_ADDR_CONFIG__NUM_TCC_BANKS__SHIFT 0x0 10252#define TCP_ADDR_CONFIG__NUM_BANKS__SHIFT 0x4 10253#define TCP_ADDR_CONFIG__COLHI_WIDTH__SHIFT 0x6 10254#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI__SHIFT 0x9 10255#define TCP_ADDR_CONFIG__NUM_TCC_BANKS_MASK 0x0000000FL 10256#define TCP_ADDR_CONFIG__NUM_BANKS_MASK 0x00000030L 10257#define TCP_ADDR_CONFIG__COLHI_WIDTH_MASK 0x000001C0L 10258#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI_MASK 0x00000200L 10259//TCP_CREDIT 10260#define TCP_CREDIT__LFIFO_CREDIT__SHIFT 0x0 10261#define TCP_CREDIT__REQ_FIFO_CREDIT__SHIFT 0x10 10262#define TCP_CREDIT__TD_CREDIT__SHIFT 0x1d 10263#define TCP_CREDIT__LFIFO_CREDIT_MASK 0x000003FFL 10264#define TCP_CREDIT__REQ_FIFO_CREDIT_MASK 0x007F0000L 10265#define TCP_CREDIT__TD_CREDIT_MASK 0xE0000000L 10266//TCP_BUFFER_ADDR_HASH_CNTL 10267#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS__SHIFT 0x0 10268#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS__SHIFT 0x8 10269#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT__SHIFT 0x10 10270#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT__SHIFT 0x18 10271#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS_MASK 0x00000007L 10272#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS_MASK 0x00000700L 10273#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT_MASK 0x00070000L 10274#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT_MASK 0x07000000L 10275//TCP_EDC_CNT 10276#define TCP_EDC_CNT__SEC_COUNT__SHIFT 0x0 10277#define TCP_EDC_CNT__LFIFO_SED_COUNT__SHIFT 0x8 10278#define TCP_EDC_CNT__DED_COUNT__SHIFT 0x10 10279#define TCP_EDC_CNT__SEC_COUNT_MASK 0x000000FFL 10280#define TCP_EDC_CNT__LFIFO_SED_COUNT_MASK 0x0000FF00L 10281#define TCP_EDC_CNT__DED_COUNT_MASK 0x00FF0000L 10282//TC_CFG_L1_LOAD_POLICY0 10283#define TC_CFG_L1_LOAD_POLICY0__POLICY_0__SHIFT 0x0 10284#define TC_CFG_L1_LOAD_POLICY0__POLICY_1__SHIFT 0x2 10285#define TC_CFG_L1_LOAD_POLICY0__POLICY_2__SHIFT 0x4 10286#define TC_CFG_L1_LOAD_POLICY0__POLICY_3__SHIFT 0x6 10287#define TC_CFG_L1_LOAD_POLICY0__POLICY_4__SHIFT 0x8 10288#define TC_CFG_L1_LOAD_POLICY0__POLICY_5__SHIFT 0xa 10289#define TC_CFG_L1_LOAD_POLICY0__POLICY_6__SHIFT 0xc 10290#define TC_CFG_L1_LOAD_POLICY0__POLICY_7__SHIFT 0xe 10291#define TC_CFG_L1_LOAD_POLICY0__POLICY_8__SHIFT 0x10 10292#define TC_CFG_L1_LOAD_POLICY0__POLICY_9__SHIFT 0x12 10293#define TC_CFG_L1_LOAD_POLICY0__POLICY_10__SHIFT 0x14 10294#define TC_CFG_L1_LOAD_POLICY0__POLICY_11__SHIFT 0x16 10295#define TC_CFG_L1_LOAD_POLICY0__POLICY_12__SHIFT 0x18 10296#define TC_CFG_L1_LOAD_POLICY0__POLICY_13__SHIFT 0x1a 10297#define TC_CFG_L1_LOAD_POLICY0__POLICY_14__SHIFT 0x1c 10298#define TC_CFG_L1_LOAD_POLICY0__POLICY_15__SHIFT 0x1e 10299#define TC_CFG_L1_LOAD_POLICY0__POLICY_0_MASK 0x00000003L 10300#define TC_CFG_L1_LOAD_POLICY0__POLICY_1_MASK 0x0000000CL 10301#define TC_CFG_L1_LOAD_POLICY0__POLICY_2_MASK 0x00000030L 10302#define TC_CFG_L1_LOAD_POLICY0__POLICY_3_MASK 0x000000C0L 10303#define TC_CFG_L1_LOAD_POLICY0__POLICY_4_MASK 0x00000300L 10304#define TC_CFG_L1_LOAD_POLICY0__POLICY_5_MASK 0x00000C00L 10305#define TC_CFG_L1_LOAD_POLICY0__POLICY_6_MASK 0x00003000L 10306#define TC_CFG_L1_LOAD_POLICY0__POLICY_7_MASK 0x0000C000L 10307#define TC_CFG_L1_LOAD_POLICY0__POLICY_8_MASK 0x00030000L 10308#define TC_CFG_L1_LOAD_POLICY0__POLICY_9_MASK 0x000C0000L 10309#define TC_CFG_L1_LOAD_POLICY0__POLICY_10_MASK 0x00300000L 10310#define TC_CFG_L1_LOAD_POLICY0__POLICY_11_MASK 0x00C00000L 10311#define TC_CFG_L1_LOAD_POLICY0__POLICY_12_MASK 0x03000000L 10312#define TC_CFG_L1_LOAD_POLICY0__POLICY_13_MASK 0x0C000000L 10313#define TC_CFG_L1_LOAD_POLICY0__POLICY_14_MASK 0x30000000L 10314#define TC_CFG_L1_LOAD_POLICY0__POLICY_15_MASK 0xC0000000L 10315//TC_CFG_L1_LOAD_POLICY1 10316#define TC_CFG_L1_LOAD_POLICY1__POLICY_16__SHIFT 0x0 10317#define TC_CFG_L1_LOAD_POLICY1__POLICY_17__SHIFT 0x2 10318#define TC_CFG_L1_LOAD_POLICY1__POLICY_18__SHIFT 0x4 10319#define TC_CFG_L1_LOAD_POLICY1__POLICY_19__SHIFT 0x6 10320#define TC_CFG_L1_LOAD_POLICY1__POLICY_20__SHIFT 0x8 10321#define TC_CFG_L1_LOAD_POLICY1__POLICY_21__SHIFT 0xa 10322#define TC_CFG_L1_LOAD_POLICY1__POLICY_22__SHIFT 0xc 10323#define TC_CFG_L1_LOAD_POLICY1__POLICY_23__SHIFT 0xe 10324#define TC_CFG_L1_LOAD_POLICY1__POLICY_24__SHIFT 0x10 10325#define TC_CFG_L1_LOAD_POLICY1__POLICY_25__SHIFT 0x12 10326#define TC_CFG_L1_LOAD_POLICY1__POLICY_26__SHIFT 0x14 10327#define TC_CFG_L1_LOAD_POLICY1__POLICY_27__SHIFT 0x16 10328#define TC_CFG_L1_LOAD_POLICY1__POLICY_28__SHIFT 0x18 10329#define TC_CFG_L1_LOAD_POLICY1__POLICY_29__SHIFT 0x1a 10330#define TC_CFG_L1_LOAD_POLICY1__POLICY_30__SHIFT 0x1c 10331#define TC_CFG_L1_LOAD_POLICY1__POLICY_31__SHIFT 0x1e 10332#define TC_CFG_L1_LOAD_POLICY1__POLICY_16_MASK 0x00000003L 10333#define TC_CFG_L1_LOAD_POLICY1__POLICY_17_MASK 0x0000000CL 10334#define TC_CFG_L1_LOAD_POLICY1__POLICY_18_MASK 0x00000030L 10335#define TC_CFG_L1_LOAD_POLICY1__POLICY_19_MASK 0x000000C0L 10336#define TC_CFG_L1_LOAD_POLICY1__POLICY_20_MASK 0x00000300L 10337#define TC_CFG_L1_LOAD_POLICY1__POLICY_21_MASK 0x00000C00L 10338#define TC_CFG_L1_LOAD_POLICY1__POLICY_22_MASK 0x00003000L 10339#define TC_CFG_L1_LOAD_POLICY1__POLICY_23_MASK 0x0000C000L 10340#define TC_CFG_L1_LOAD_POLICY1__POLICY_24_MASK 0x00030000L 10341#define TC_CFG_L1_LOAD_POLICY1__POLICY_25_MASK 0x000C0000L 10342#define TC_CFG_L1_LOAD_POLICY1__POLICY_26_MASK 0x00300000L 10343#define TC_CFG_L1_LOAD_POLICY1__POLICY_27_MASK 0x00C00000L 10344#define TC_CFG_L1_LOAD_POLICY1__POLICY_28_MASK 0x03000000L 10345#define TC_CFG_L1_LOAD_POLICY1__POLICY_29_MASK 0x0C000000L 10346#define TC_CFG_L1_LOAD_POLICY1__POLICY_30_MASK 0x30000000L 10347#define TC_CFG_L1_LOAD_POLICY1__POLICY_31_MASK 0xC0000000L 10348//TC_CFG_L1_STORE_POLICY 10349#define TC_CFG_L1_STORE_POLICY__POLICY_0__SHIFT 0x0 10350#define TC_CFG_L1_STORE_POLICY__POLICY_1__SHIFT 0x1 10351#define TC_CFG_L1_STORE_POLICY__POLICY_2__SHIFT 0x2 10352#define TC_CFG_L1_STORE_POLICY__POLICY_3__SHIFT 0x3 10353#define TC_CFG_L1_STORE_POLICY__POLICY_4__SHIFT 0x4 10354#define TC_CFG_L1_STORE_POLICY__POLICY_5__SHIFT 0x5 10355#define TC_CFG_L1_STORE_POLICY__POLICY_6__SHIFT 0x6 10356#define TC_CFG_L1_STORE_POLICY__POLICY_7__SHIFT 0x7 10357#define TC_CFG_L1_STORE_POLICY__POLICY_8__SHIFT 0x8 10358#define TC_CFG_L1_STORE_POLICY__POLICY_9__SHIFT 0x9 10359#define TC_CFG_L1_STORE_POLICY__POLICY_10__SHIFT 0xa 10360#define TC_CFG_L1_STORE_POLICY__POLICY_11__SHIFT 0xb 10361#define TC_CFG_L1_STORE_POLICY__POLICY_12__SHIFT 0xc 10362#define TC_CFG_L1_STORE_POLICY__POLICY_13__SHIFT 0xd 10363#define TC_CFG_L1_STORE_POLICY__POLICY_14__SHIFT 0xe 10364#define TC_CFG_L1_STORE_POLICY__POLICY_15__SHIFT 0xf 10365#define TC_CFG_L1_STORE_POLICY__POLICY_16__SHIFT 0x10 10366#define TC_CFG_L1_STORE_POLICY__POLICY_17__SHIFT 0x11 10367#define TC_CFG_L1_STORE_POLICY__POLICY_18__SHIFT 0x12 10368#define TC_CFG_L1_STORE_POLICY__POLICY_19__SHIFT 0x13 10369#define TC_CFG_L1_STORE_POLICY__POLICY_20__SHIFT 0x14 10370#define TC_CFG_L1_STORE_POLICY__POLICY_21__SHIFT 0x15 10371#define TC_CFG_L1_STORE_POLICY__POLICY_22__SHIFT 0x16 10372#define TC_CFG_L1_STORE_POLICY__POLICY_23__SHIFT 0x17 10373#define TC_CFG_L1_STORE_POLICY__POLICY_24__SHIFT 0x18 10374#define TC_CFG_L1_STORE_POLICY__POLICY_25__SHIFT 0x19 10375#define TC_CFG_L1_STORE_POLICY__POLICY_26__SHIFT 0x1a 10376#define TC_CFG_L1_STORE_POLICY__POLICY_27__SHIFT 0x1b 10377#define TC_CFG_L1_STORE_POLICY__POLICY_28__SHIFT 0x1c 10378#define TC_CFG_L1_STORE_POLICY__POLICY_29__SHIFT 0x1d 10379#define TC_CFG_L1_STORE_POLICY__POLICY_30__SHIFT 0x1e 10380#define TC_CFG_L1_STORE_POLICY__POLICY_31__SHIFT 0x1f 10381#define TC_CFG_L1_STORE_POLICY__POLICY_0_MASK 0x00000001L 10382#define TC_CFG_L1_STORE_POLICY__POLICY_1_MASK 0x00000002L 10383#define TC_CFG_L1_STORE_POLICY__POLICY_2_MASK 0x00000004L 10384#define TC_CFG_L1_STORE_POLICY__POLICY_3_MASK 0x00000008L 10385#define TC_CFG_L1_STORE_POLICY__POLICY_4_MASK 0x00000010L 10386#define TC_CFG_L1_STORE_POLICY__POLICY_5_MASK 0x00000020L 10387#define TC_CFG_L1_STORE_POLICY__POLICY_6_MASK 0x00000040L 10388#define TC_CFG_L1_STORE_POLICY__POLICY_7_MASK 0x00000080L 10389#define TC_CFG_L1_STORE_POLICY__POLICY_8_MASK 0x00000100L 10390#define TC_CFG_L1_STORE_POLICY__POLICY_9_MASK 0x00000200L 10391#define TC_CFG_L1_STORE_POLICY__POLICY_10_MASK 0x00000400L 10392#define TC_CFG_L1_STORE_POLICY__POLICY_11_MASK 0x00000800L 10393#define TC_CFG_L1_STORE_POLICY__POLICY_12_MASK 0x00001000L 10394#define TC_CFG_L1_STORE_POLICY__POLICY_13_MASK 0x00002000L 10395#define TC_CFG_L1_STORE_POLICY__POLICY_14_MASK 0x00004000L 10396#define TC_CFG_L1_STORE_POLICY__POLICY_15_MASK 0x00008000L 10397#define TC_CFG_L1_STORE_POLICY__POLICY_16_MASK 0x00010000L 10398#define TC_CFG_L1_STORE_POLICY__POLICY_17_MASK 0x00020000L 10399#define TC_CFG_L1_STORE_POLICY__POLICY_18_MASK 0x00040000L 10400#define TC_CFG_L1_STORE_POLICY__POLICY_19_MASK 0x00080000L 10401#define TC_CFG_L1_STORE_POLICY__POLICY_20_MASK 0x00100000L 10402#define TC_CFG_L1_STORE_POLICY__POLICY_21_MASK 0x00200000L 10403#define TC_CFG_L1_STORE_POLICY__POLICY_22_MASK 0x00400000L 10404#define TC_CFG_L1_STORE_POLICY__POLICY_23_MASK 0x00800000L 10405#define TC_CFG_L1_STORE_POLICY__POLICY_24_MASK 0x01000000L 10406#define TC_CFG_L1_STORE_POLICY__POLICY_25_MASK 0x02000000L 10407#define TC_CFG_L1_STORE_POLICY__POLICY_26_MASK 0x04000000L 10408#define TC_CFG_L1_STORE_POLICY__POLICY_27_MASK 0x08000000L 10409#define TC_CFG_L1_STORE_POLICY__POLICY_28_MASK 0x10000000L 10410#define TC_CFG_L1_STORE_POLICY__POLICY_29_MASK 0x20000000L 10411#define TC_CFG_L1_STORE_POLICY__POLICY_30_MASK 0x40000000L 10412#define TC_CFG_L1_STORE_POLICY__POLICY_31_MASK 0x80000000L 10413//TC_CFG_L2_LOAD_POLICY0 10414#define TC_CFG_L2_LOAD_POLICY0__POLICY_0__SHIFT 0x0 10415#define TC_CFG_L2_LOAD_POLICY0__POLICY_1__SHIFT 0x2 10416#define TC_CFG_L2_LOAD_POLICY0__POLICY_2__SHIFT 0x4 10417#define TC_CFG_L2_LOAD_POLICY0__POLICY_3__SHIFT 0x6 10418#define TC_CFG_L2_LOAD_POLICY0__POLICY_4__SHIFT 0x8 10419#define TC_CFG_L2_LOAD_POLICY0__POLICY_5__SHIFT 0xa 10420#define TC_CFG_L2_LOAD_POLICY0__POLICY_6__SHIFT 0xc 10421#define TC_CFG_L2_LOAD_POLICY0__POLICY_7__SHIFT 0xe 10422#define TC_CFG_L2_LOAD_POLICY0__POLICY_8__SHIFT 0x10 10423#define TC_CFG_L2_LOAD_POLICY0__POLICY_9__SHIFT 0x12 10424#define TC_CFG_L2_LOAD_POLICY0__POLICY_10__SHIFT 0x14 10425#define TC_CFG_L2_LOAD_POLICY0__POLICY_11__SHIFT 0x16 10426#define TC_CFG_L2_LOAD_POLICY0__POLICY_12__SHIFT 0x18 10427#define TC_CFG_L2_LOAD_POLICY0__POLICY_13__SHIFT 0x1a 10428#define TC_CFG_L2_LOAD_POLICY0__POLICY_14__SHIFT 0x1c 10429#define TC_CFG_L2_LOAD_POLICY0__POLICY_15__SHIFT 0x1e 10430#define TC_CFG_L2_LOAD_POLICY0__POLICY_0_MASK 0x00000003L 10431#define TC_CFG_L2_LOAD_POLICY0__POLICY_1_MASK 0x0000000CL 10432#define TC_CFG_L2_LOAD_POLICY0__POLICY_2_MASK 0x00000030L 10433#define TC_CFG_L2_LOAD_POLICY0__POLICY_3_MASK 0x000000C0L 10434#define TC_CFG_L2_LOAD_POLICY0__POLICY_4_MASK 0x00000300L 10435#define TC_CFG_L2_LOAD_POLICY0__POLICY_5_MASK 0x00000C00L 10436#define TC_CFG_L2_LOAD_POLICY0__POLICY_6_MASK 0x00003000L 10437#define TC_CFG_L2_LOAD_POLICY0__POLICY_7_MASK 0x0000C000L 10438#define TC_CFG_L2_LOAD_POLICY0__POLICY_8_MASK 0x00030000L 10439#define TC_CFG_L2_LOAD_POLICY0__POLICY_9_MASK 0x000C0000L 10440#define TC_CFG_L2_LOAD_POLICY0__POLICY_10_MASK 0x00300000L 10441#define TC_CFG_L2_LOAD_POLICY0__POLICY_11_MASK 0x00C00000L 10442#define TC_CFG_L2_LOAD_POLICY0__POLICY_12_MASK 0x03000000L 10443#define TC_CFG_L2_LOAD_POLICY0__POLICY_13_MASK 0x0C000000L 10444#define TC_CFG_L2_LOAD_POLICY0__POLICY_14_MASK 0x30000000L 10445#define TC_CFG_L2_LOAD_POLICY0__POLICY_15_MASK 0xC0000000L 10446//TC_CFG_L2_LOAD_POLICY1 10447#define TC_CFG_L2_LOAD_POLICY1__POLICY_16__SHIFT 0x0 10448#define TC_CFG_L2_LOAD_POLICY1__POLICY_17__SHIFT 0x2 10449#define TC_CFG_L2_LOAD_POLICY1__POLICY_18__SHIFT 0x4 10450#define TC_CFG_L2_LOAD_POLICY1__POLICY_19__SHIFT 0x6 10451#define TC_CFG_L2_LOAD_POLICY1__POLICY_20__SHIFT 0x8 10452#define TC_CFG_L2_LOAD_POLICY1__POLICY_21__SHIFT 0xa 10453#define TC_CFG_L2_LOAD_POLICY1__POLICY_22__SHIFT 0xc 10454#define TC_CFG_L2_LOAD_POLICY1__POLICY_23__SHIFT 0xe 10455#define TC_CFG_L2_LOAD_POLICY1__POLICY_24__SHIFT 0x10 10456#define TC_CFG_L2_LOAD_POLICY1__POLICY_25__SHIFT 0x12 10457#define TC_CFG_L2_LOAD_POLICY1__POLICY_26__SHIFT 0x14 10458#define TC_CFG_L2_LOAD_POLICY1__POLICY_27__SHIFT 0x16 10459#define TC_CFG_L2_LOAD_POLICY1__POLICY_28__SHIFT 0x18 10460#define TC_CFG_L2_LOAD_POLICY1__POLICY_29__SHIFT 0x1a 10461#define TC_CFG_L2_LOAD_POLICY1__POLICY_30__SHIFT 0x1c 10462#define TC_CFG_L2_LOAD_POLICY1__POLICY_31__SHIFT 0x1e 10463#define TC_CFG_L2_LOAD_POLICY1__POLICY_16_MASK 0x00000003L 10464#define TC_CFG_L2_LOAD_POLICY1__POLICY_17_MASK 0x0000000CL 10465#define TC_CFG_L2_LOAD_POLICY1__POLICY_18_MASK 0x00000030L 10466#define TC_CFG_L2_LOAD_POLICY1__POLICY_19_MASK 0x000000C0L 10467#define TC_CFG_L2_LOAD_POLICY1__POLICY_20_MASK 0x00000300L 10468#define TC_CFG_L2_LOAD_POLICY1__POLICY_21_MASK 0x00000C00L 10469#define TC_CFG_L2_LOAD_POLICY1__POLICY_22_MASK 0x00003000L 10470#define TC_CFG_L2_LOAD_POLICY1__POLICY_23_MASK 0x0000C000L 10471#define TC_CFG_L2_LOAD_POLICY1__POLICY_24_MASK 0x00030000L 10472#define TC_CFG_L2_LOAD_POLICY1__POLICY_25_MASK 0x000C0000L 10473#define TC_CFG_L2_LOAD_POLICY1__POLICY_26_MASK 0x00300000L 10474#define TC_CFG_L2_LOAD_POLICY1__POLICY_27_MASK 0x00C00000L 10475#define TC_CFG_L2_LOAD_POLICY1__POLICY_28_MASK 0x03000000L 10476#define TC_CFG_L2_LOAD_POLICY1__POLICY_29_MASK 0x0C000000L 10477#define TC_CFG_L2_LOAD_POLICY1__POLICY_30_MASK 0x30000000L 10478#define TC_CFG_L2_LOAD_POLICY1__POLICY_31_MASK 0xC0000000L 10479//TC_CFG_L2_STORE_POLICY0 10480#define TC_CFG_L2_STORE_POLICY0__POLICY_0__SHIFT 0x0 10481#define TC_CFG_L2_STORE_POLICY0__POLICY_1__SHIFT 0x2 10482#define TC_CFG_L2_STORE_POLICY0__POLICY_2__SHIFT 0x4 10483#define TC_CFG_L2_STORE_POLICY0__POLICY_3__SHIFT 0x6 10484#define TC_CFG_L2_STORE_POLICY0__POLICY_4__SHIFT 0x8 10485#define TC_CFG_L2_STORE_POLICY0__POLICY_5__SHIFT 0xa 10486#define TC_CFG_L2_STORE_POLICY0__POLICY_6__SHIFT 0xc 10487#define TC_CFG_L2_STORE_POLICY0__POLICY_7__SHIFT 0xe 10488#define TC_CFG_L2_STORE_POLICY0__POLICY_8__SHIFT 0x10 10489#define TC_CFG_L2_STORE_POLICY0__POLICY_9__SHIFT 0x12 10490#define TC_CFG_L2_STORE_POLICY0__POLICY_10__SHIFT 0x14 10491#define TC_CFG_L2_STORE_POLICY0__POLICY_11__SHIFT 0x16 10492#define TC_CFG_L2_STORE_POLICY0__POLICY_12__SHIFT 0x18 10493#define TC_CFG_L2_STORE_POLICY0__POLICY_13__SHIFT 0x1a 10494#define TC_CFG_L2_STORE_POLICY0__POLICY_14__SHIFT 0x1c 10495#define TC_CFG_L2_STORE_POLICY0__POLICY_15__SHIFT 0x1e 10496#define TC_CFG_L2_STORE_POLICY0__POLICY_0_MASK 0x00000003L 10497#define TC_CFG_L2_STORE_POLICY0__POLICY_1_MASK 0x0000000CL 10498#define TC_CFG_L2_STORE_POLICY0__POLICY_2_MASK 0x00000030L 10499#define TC_CFG_L2_STORE_POLICY0__POLICY_3_MASK 0x000000C0L 10500#define TC_CFG_L2_STORE_POLICY0__POLICY_4_MASK 0x00000300L 10501#define TC_CFG_L2_STORE_POLICY0__POLICY_5_MASK 0x00000C00L 10502#define TC_CFG_L2_STORE_POLICY0__POLICY_6_MASK 0x00003000L 10503#define TC_CFG_L2_STORE_POLICY0__POLICY_7_MASK 0x0000C000L 10504#define TC_CFG_L2_STORE_POLICY0__POLICY_8_MASK 0x00030000L 10505#define TC_CFG_L2_STORE_POLICY0__POLICY_9_MASK 0x000C0000L 10506#define TC_CFG_L2_STORE_POLICY0__POLICY_10_MASK 0x00300000L 10507#define TC_CFG_L2_STORE_POLICY0__POLICY_11_MASK 0x00C00000L 10508#define TC_CFG_L2_STORE_POLICY0__POLICY_12_MASK 0x03000000L 10509#define TC_CFG_L2_STORE_POLICY0__POLICY_13_MASK 0x0C000000L 10510#define TC_CFG_L2_STORE_POLICY0__POLICY_14_MASK 0x30000000L 10511#define TC_CFG_L2_STORE_POLICY0__POLICY_15_MASK 0xC0000000L 10512//TC_CFG_L2_STORE_POLICY1 10513#define TC_CFG_L2_STORE_POLICY1__POLICY_16__SHIFT 0x0 10514#define TC_CFG_L2_STORE_POLICY1__POLICY_17__SHIFT 0x2 10515#define TC_CFG_L2_STORE_POLICY1__POLICY_18__SHIFT 0x4 10516#define TC_CFG_L2_STORE_POLICY1__POLICY_19__SHIFT 0x6 10517#define TC_CFG_L2_STORE_POLICY1__POLICY_20__SHIFT 0x8 10518#define TC_CFG_L2_STORE_POLICY1__POLICY_21__SHIFT 0xa 10519#define TC_CFG_L2_STORE_POLICY1__POLICY_22__SHIFT 0xc 10520#define TC_CFG_L2_STORE_POLICY1__POLICY_23__SHIFT 0xe 10521#define TC_CFG_L2_STORE_POLICY1__POLICY_24__SHIFT 0x10 10522#define TC_CFG_L2_STORE_POLICY1__POLICY_25__SHIFT 0x12 10523#define TC_CFG_L2_STORE_POLICY1__POLICY_26__SHIFT 0x14 10524#define TC_CFG_L2_STORE_POLICY1__POLICY_27__SHIFT 0x16 10525#define TC_CFG_L2_STORE_POLICY1__POLICY_28__SHIFT 0x18 10526#define TC_CFG_L2_STORE_POLICY1__POLICY_29__SHIFT 0x1a 10527#define TC_CFG_L2_STORE_POLICY1__POLICY_30__SHIFT 0x1c 10528#define TC_CFG_L2_STORE_POLICY1__POLICY_31__SHIFT 0x1e 10529#define TC_CFG_L2_STORE_POLICY1__POLICY_16_MASK 0x00000003L 10530#define TC_CFG_L2_STORE_POLICY1__POLICY_17_MASK 0x0000000CL 10531#define TC_CFG_L2_STORE_POLICY1__POLICY_18_MASK 0x00000030L 10532#define TC_CFG_L2_STORE_POLICY1__POLICY_19_MASK 0x000000C0L 10533#define TC_CFG_L2_STORE_POLICY1__POLICY_20_MASK 0x00000300L 10534#define TC_CFG_L2_STORE_POLICY1__POLICY_21_MASK 0x00000C00L 10535#define TC_CFG_L2_STORE_POLICY1__POLICY_22_MASK 0x00003000L 10536#define TC_CFG_L2_STORE_POLICY1__POLICY_23_MASK 0x0000C000L 10537#define TC_CFG_L2_STORE_POLICY1__POLICY_24_MASK 0x00030000L 10538#define TC_CFG_L2_STORE_POLICY1__POLICY_25_MASK 0x000C0000L 10539#define TC_CFG_L2_STORE_POLICY1__POLICY_26_MASK 0x00300000L 10540#define TC_CFG_L2_STORE_POLICY1__POLICY_27_MASK 0x00C00000L 10541#define TC_CFG_L2_STORE_POLICY1__POLICY_28_MASK 0x03000000L 10542#define TC_CFG_L2_STORE_POLICY1__POLICY_29_MASK 0x0C000000L 10543#define TC_CFG_L2_STORE_POLICY1__POLICY_30_MASK 0x30000000L 10544#define TC_CFG_L2_STORE_POLICY1__POLICY_31_MASK 0xC0000000L 10545//TC_CFG_L2_ATOMIC_POLICY 10546#define TC_CFG_L2_ATOMIC_POLICY__POLICY_0__SHIFT 0x0 10547#define TC_CFG_L2_ATOMIC_POLICY__POLICY_1__SHIFT 0x2 10548#define TC_CFG_L2_ATOMIC_POLICY__POLICY_2__SHIFT 0x4 10549#define TC_CFG_L2_ATOMIC_POLICY__POLICY_3__SHIFT 0x6 10550#define TC_CFG_L2_ATOMIC_POLICY__POLICY_4__SHIFT 0x8 10551#define TC_CFG_L2_ATOMIC_POLICY__POLICY_5__SHIFT 0xa 10552#define TC_CFG_L2_ATOMIC_POLICY__POLICY_6__SHIFT 0xc 10553#define TC_CFG_L2_ATOMIC_POLICY__POLICY_7__SHIFT 0xe 10554#define TC_CFG_L2_ATOMIC_POLICY__POLICY_8__SHIFT 0x10 10555#define TC_CFG_L2_ATOMIC_POLICY__POLICY_9__SHIFT 0x12 10556#define TC_CFG_L2_ATOMIC_POLICY__POLICY_10__SHIFT 0x14 10557#define TC_CFG_L2_ATOMIC_POLICY__POLICY_11__SHIFT 0x16 10558#define TC_CFG_L2_ATOMIC_POLICY__POLICY_12__SHIFT 0x18 10559#define TC_CFG_L2_ATOMIC_POLICY__POLICY_13__SHIFT 0x1a 10560#define TC_CFG_L2_ATOMIC_POLICY__POLICY_14__SHIFT 0x1c 10561#define TC_CFG_L2_ATOMIC_POLICY__POLICY_15__SHIFT 0x1e 10562#define TC_CFG_L2_ATOMIC_POLICY__POLICY_0_MASK 0x00000003L 10563#define TC_CFG_L2_ATOMIC_POLICY__POLICY_1_MASK 0x0000000CL 10564#define TC_CFG_L2_ATOMIC_POLICY__POLICY_2_MASK 0x00000030L 10565#define TC_CFG_L2_ATOMIC_POLICY__POLICY_3_MASK 0x000000C0L 10566#define TC_CFG_L2_ATOMIC_POLICY__POLICY_4_MASK 0x00000300L 10567#define TC_CFG_L2_ATOMIC_POLICY__POLICY_5_MASK 0x00000C00L 10568#define TC_CFG_L2_ATOMIC_POLICY__POLICY_6_MASK 0x00003000L 10569#define TC_CFG_L2_ATOMIC_POLICY__POLICY_7_MASK 0x0000C000L 10570#define TC_CFG_L2_ATOMIC_POLICY__POLICY_8_MASK 0x00030000L 10571#define TC_CFG_L2_ATOMIC_POLICY__POLICY_9_MASK 0x000C0000L 10572#define TC_CFG_L2_ATOMIC_POLICY__POLICY_10_MASK 0x00300000L 10573#define TC_CFG_L2_ATOMIC_POLICY__POLICY_11_MASK 0x00C00000L 10574#define TC_CFG_L2_ATOMIC_POLICY__POLICY_12_MASK 0x03000000L 10575#define TC_CFG_L2_ATOMIC_POLICY__POLICY_13_MASK 0x0C000000L 10576#define TC_CFG_L2_ATOMIC_POLICY__POLICY_14_MASK 0x30000000L 10577#define TC_CFG_L2_ATOMIC_POLICY__POLICY_15_MASK 0xC0000000L 10578//TC_CFG_L1_VOLATILE 10579#define TC_CFG_L1_VOLATILE__VOL__SHIFT 0x0 10580#define TC_CFG_L1_VOLATILE__VOL_MASK 0x0000000FL 10581//TC_CFG_L2_VOLATILE 10582#define TC_CFG_L2_VOLATILE__VOL__SHIFT 0x0 10583#define TC_CFG_L2_VOLATILE__VOL_MASK 0x0000000FL 10584//TCI_STATUS 10585#define TCI_STATUS__TCI_BUSY__SHIFT 0x0 10586#define TCI_STATUS__TCI_BUSY_MASK 0x00000001L 10587//TCI_CNTL_1 10588#define TCI_CNTL_1__WBINVL1_NUM_CYCLES__SHIFT 0x0 10589#define TCI_CNTL_1__REQ_FIFO_DEPTH__SHIFT 0x10 10590#define TCI_CNTL_1__WDATA_RAM_DEPTH__SHIFT 0x18 10591#define TCI_CNTL_1__WBINVL1_NUM_CYCLES_MASK 0x0000FFFFL 10592#define TCI_CNTL_1__REQ_FIFO_DEPTH_MASK 0x00FF0000L 10593#define TCI_CNTL_1__WDATA_RAM_DEPTH_MASK 0xFF000000L 10594//TCI_CNTL_2 10595#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2__SHIFT 0x0 10596#define TCI_CNTL_2__TCA_MAX_CREDIT__SHIFT 0x1 10597#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2_MASK 0x00000001L 10598#define TCI_CNTL_2__TCA_MAX_CREDIT_MASK 0x000001FEL 10599//TCC_CTRL 10600#define TCC_CTRL__CACHE_SIZE__SHIFT 0x0 10601#define TCC_CTRL__RATE__SHIFT 0x2 10602#define TCC_CTRL__WRITEBACK_MARGIN__SHIFT 0x4 10603#define TCC_CTRL__METADATA_LATENCY_FIFO_SIZE__SHIFT 0x8 10604#define TCC_CTRL__SRC_FIFO_SIZE__SHIFT 0xc 10605#define TCC_CTRL__LATENCY_FIFO_SIZE__SHIFT 0x10 10606#define TCC_CTRL__LINEAR_SET_HASH__SHIFT 0x15 10607#define TCC_CTRL__MDC_SIZE__SHIFT 0x18 10608#define TCC_CTRL__MDC_SECTOR_SIZE__SHIFT 0x1a 10609#define TCC_CTRL__MDC_SIDEBAND_FIFO_SIZE__SHIFT 0x1c 10610#define TCC_CTRL__CACHE_SIZE_MASK 0x00000003L 10611#define TCC_CTRL__RATE_MASK 0x0000000CL 10612#define TCC_CTRL__WRITEBACK_MARGIN_MASK 0x000000F0L 10613#define TCC_CTRL__METADATA_LATENCY_FIFO_SIZE_MASK 0x00000F00L 10614#define TCC_CTRL__SRC_FIFO_SIZE_MASK 0x0000F000L 10615#define TCC_CTRL__LATENCY_FIFO_SIZE_MASK 0x000F0000L 10616#define TCC_CTRL__LINEAR_SET_HASH_MASK 0x00200000L 10617#define TCC_CTRL__MDC_SIZE_MASK 0x03000000L 10618#define TCC_CTRL__MDC_SECTOR_SIZE_MASK 0x0C000000L 10619#define TCC_CTRL__MDC_SIDEBAND_FIFO_SIZE_MASK 0xF0000000L 10620//TCC_CTRL2 10621#define TCC_CTRL2__PROBE_FIFO_SIZE__SHIFT 0x0 10622#define TCC_CTRL2__PROBE_FIFO_SIZE_MASK 0x0000000FL 10623//TCC_EDC_CNT 10624#define TCC_EDC_CNT__CACHE_DATA_SEC_COUNT__SHIFT 0x0 10625#define TCC_EDC_CNT__CACHE_DATA_DED_COUNT__SHIFT 0x2 10626#define TCC_EDC_CNT__CACHE_DIRTY_SEC_COUNT__SHIFT 0x4 10627#define TCC_EDC_CNT__CACHE_DIRTY_DED_COUNT__SHIFT 0x6 10628#define TCC_EDC_CNT__HIGH_RATE_TAG_SEC_COUNT__SHIFT 0x8 10629#define TCC_EDC_CNT__HIGH_RATE_TAG_DED_COUNT__SHIFT 0xa 10630#define TCC_EDC_CNT__LOW_RATE_TAG_SEC_COUNT__SHIFT 0xc 10631#define TCC_EDC_CNT__LOW_RATE_TAG_DED_COUNT__SHIFT 0xe 10632#define TCC_EDC_CNT__SRC_FIFO_SEC_COUNT__SHIFT 0x10 10633#define TCC_EDC_CNT__SRC_FIFO_DED_COUNT__SHIFT 0x12 10634#define TCC_EDC_CNT__IN_USE_DEC_SED_COUNT__SHIFT 0x14 10635#define TCC_EDC_CNT__IN_USE_TRANSFER_SED_COUNT__SHIFT 0x16 10636#define TCC_EDC_CNT__LATENCY_FIFO_SED_COUNT__SHIFT 0x18 10637#define TCC_EDC_CNT__RETURN_DATA_SED_COUNT__SHIFT 0x1a 10638#define TCC_EDC_CNT__RETURN_CONTROL_SED_COUNT__SHIFT 0x1c 10639#define TCC_EDC_CNT__UC_ATOMIC_FIFO_SED_COUNT__SHIFT 0x1e 10640#define TCC_EDC_CNT__CACHE_DATA_SEC_COUNT_MASK 0x00000003L 10641#define TCC_EDC_CNT__CACHE_DATA_DED_COUNT_MASK 0x0000000CL 10642#define TCC_EDC_CNT__CACHE_DIRTY_SEC_COUNT_MASK 0x00000030L 10643#define TCC_EDC_CNT__CACHE_DIRTY_DED_COUNT_MASK 0x000000C0L 10644#define TCC_EDC_CNT__HIGH_RATE_TAG_SEC_COUNT_MASK 0x00000300L 10645#define TCC_EDC_CNT__HIGH_RATE_TAG_DED_COUNT_MASK 0x00000C00L 10646#define TCC_EDC_CNT__LOW_RATE_TAG_SEC_COUNT_MASK 0x00003000L 10647#define TCC_EDC_CNT__LOW_RATE_TAG_DED_COUNT_MASK 0x0000C000L 10648#define TCC_EDC_CNT__SRC_FIFO_SEC_COUNT_MASK 0x00030000L 10649#define TCC_EDC_CNT__SRC_FIFO_DED_COUNT_MASK 0x000C0000L 10650#define TCC_EDC_CNT__IN_USE_DEC_SED_COUNT_MASK 0x00300000L 10651#define TCC_EDC_CNT__IN_USE_TRANSFER_SED_COUNT_MASK 0x00C00000L 10652#define TCC_EDC_CNT__LATENCY_FIFO_SED_COUNT_MASK 0x03000000L 10653#define TCC_EDC_CNT__RETURN_DATA_SED_COUNT_MASK 0x0C000000L 10654#define TCC_EDC_CNT__RETURN_CONTROL_SED_COUNT_MASK 0x30000000L 10655#define TCC_EDC_CNT__UC_ATOMIC_FIFO_SED_COUNT_MASK 0xC0000000L 10656//TCC_EDC_CNT2 10657#define TCC_EDC_CNT2__WRITE_RETURN_SED_COUNT__SHIFT 0x0 10658#define TCC_EDC_CNT2__WRITE_CACHE_READ_SED_COUNT__SHIFT 0x2 10659#define TCC_EDC_CNT2__SRC_FIFO_NEXT_RAM_SED_COUNT__SHIFT 0x4 10660#define TCC_EDC_CNT2__LATENCY_FIFO_NEXT_RAM_SED_COUNT__SHIFT 0x6 10661#define TCC_EDC_CNT2__CACHE_TAG_PROBE_FIFO_SED_COUNT__SHIFT 0x8 10662#define TCC_EDC_CNT2__WRITE_RETURN_SED_COUNT_MASK 0x00000003L 10663#define TCC_EDC_CNT2__WRITE_CACHE_READ_SED_COUNT_MASK 0x0000000CL 10664#define TCC_EDC_CNT2__SRC_FIFO_NEXT_RAM_SED_COUNT_MASK 0x00000030L 10665#define TCC_EDC_CNT2__LATENCY_FIFO_NEXT_RAM_SED_COUNT_MASK 0x000000C0L 10666#define TCC_EDC_CNT2__CACHE_TAG_PROBE_FIFO_SED_COUNT_MASK 0x00000300L 10667//TCC_REDUNDANCY 10668#define TCC_REDUNDANCY__MC_SEL0__SHIFT 0x0 10669#define TCC_REDUNDANCY__MC_SEL1__SHIFT 0x1 10670#define TCC_REDUNDANCY__MC_SEL0_MASK 0x00000001L 10671#define TCC_REDUNDANCY__MC_SEL1_MASK 0x00000002L 10672//TCC_EXE_DISABLE 10673#define TCC_EXE_DISABLE__EXE_DISABLE__SHIFT 0x1 10674#define TCC_EXE_DISABLE__EXE_DISABLE_MASK 0x00000002L 10675//TCC_DSM_CNTL 10676#define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_DATA_SEL__SHIFT 0x0 10677#define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_SINGLE_WRITE__SHIFT 0x2 10678#define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_DATA_SEL__SHIFT 0x3 10679#define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_SINGLE_WRITE__SHIFT 0x5 10680#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_DATA_SEL__SHIFT 0x6 10681#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_SINGLE_WRITE__SHIFT 0x8 10682#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_DATA_SEL__SHIFT 0x9 10683#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_SINGLE_WRITE__SHIFT 0xb 10684#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_DATA_SEL__SHIFT 0xc 10685#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_SINGLE_WRITE__SHIFT 0xe 10686#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_DATA_SEL__SHIFT 0xf 10687#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_SINGLE_WRITE__SHIFT 0x11 10688#define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_DATA_SEL__SHIFT 0x12 10689#define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_SINGLE_WRITE__SHIFT 0x14 10690#define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_DATA_SEL__SHIFT 0x15 10691#define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_SINGLE_WRITE__SHIFT 0x17 10692#define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_DATA_SEL__SHIFT 0x18 10693#define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_SINGLE_WRITE__SHIFT 0x1a 10694#define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_DATA_SEL__SHIFT 0x1b 10695#define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_SINGLE_WRITE__SHIFT 0x1d 10696#define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_DATA_SEL_MASK 0x00000003L 10697#define TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L 10698#define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_DATA_SEL_MASK 0x00000018L 10699#define TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_SINGLE_WRITE_MASK 0x00000020L 10700#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_DATA_SEL_MASK 0x000000C0L 10701#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_SINGLE_WRITE_MASK 0x00000100L 10702#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_DATA_SEL_MASK 0x00000600L 10703#define TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_SINGLE_WRITE_MASK 0x00000800L 10704#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_DATA_SEL_MASK 0x00003000L 10705#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_SINGLE_WRITE_MASK 0x00004000L 10706#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_DATA_SEL_MASK 0x00018000L 10707#define TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_SINGLE_WRITE_MASK 0x00020000L 10708#define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_DATA_SEL_MASK 0x000C0000L 10709#define TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_SINGLE_WRITE_MASK 0x00100000L 10710#define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_DATA_SEL_MASK 0x00600000L 10711#define TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_SINGLE_WRITE_MASK 0x00800000L 10712#define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_DATA_SEL_MASK 0x03000000L 10713#define TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_SINGLE_WRITE_MASK 0x04000000L 10714#define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_DATA_SEL_MASK 0x18000000L 10715#define TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_SINGLE_WRITE_MASK 0x20000000L 10716//TCC_DSM_CNTLA 10717#define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x0 10718#define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x2 10719#define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x3 10720#define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x5 10721#define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_DATA_SEL__SHIFT 0x6 10722#define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_SINGLE_WRITE__SHIFT 0x8 10723#define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_DATA_SEL__SHIFT 0x9 10724#define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_SINGLE_WRITE__SHIFT 0xb 10725#define TCC_DSM_CNTLA__SRC_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL__SHIFT 0xc 10726#define TCC_DSM_CNTLA__SRC_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0xe 10727#define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL__SHIFT 0xf 10728#define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x11 10729#define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x12 10730#define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x14 10731#define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_DATA_SEL__SHIFT 0x15 10732#define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT 0x17 10733#define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_DATA_SEL__SHIFT 0x18 10734#define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_SINGLE_WRITE__SHIFT 0x1a 10735#define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_DATA_SEL__SHIFT 0x1b 10736#define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_SINGLE_WRITE__SHIFT 0x1d 10737#define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_DATA_SEL_MASK 0x00000003L 10738#define TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L 10739#define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_DATA_SEL_MASK 0x00000018L 10740#define TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00000020L 10741#define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_DATA_SEL_MASK 0x000000C0L 10742#define TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_SINGLE_WRITE_MASK 0x00000100L 10743#define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_DATA_SEL_MASK 0x00000600L 10744#define TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_SINGLE_WRITE_MASK 0x00000800L 10745#define TCC_DSM_CNTLA__SRC_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL_MASK 0x00003000L 10746#define TCC_DSM_CNTLA__SRC_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00004000L 10747#define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL_MASK 0x00018000L 10748#define TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x00020000L 10749#define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_DATA_SEL_MASK 0x000C0000L 10750#define TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00100000L 10751#define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_DATA_SEL_MASK 0x00600000L 10752#define TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_SINGLE_WRITE_MASK 0x00800000L 10753#define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_DATA_SEL_MASK 0x03000000L 10754#define TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_SINGLE_WRITE_MASK 0x04000000L 10755#define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_DATA_SEL_MASK 0x18000000L 10756#define TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_SINGLE_WRITE_MASK 0x20000000L 10757//TCC_DSM_CNTL2 10758#define TCC_DSM_CNTL2__CACHE_DATA_ENABLE_ERROR_INJECT__SHIFT 0x0 10759#define TCC_DSM_CNTL2__CACHE_DATA_SELECT_INJECT_DELAY__SHIFT 0x2 10760#define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_ENABLE_ERROR_INJECT__SHIFT 0x3 10761#define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_SELECT_INJECT_DELAY__SHIFT 0x5 10762#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_ENABLE_ERROR_INJECT__SHIFT 0x6 10763#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_SELECT_INJECT_DELAY__SHIFT 0x8 10764#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_ENABLE_ERROR_INJECT__SHIFT 0x9 10765#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_SELECT_INJECT_DELAY__SHIFT 0xb 10766#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_ENABLE_ERROR_INJECT__SHIFT 0xc 10767#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_SELECT_INJECT_DELAY__SHIFT 0xe 10768#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_ENABLE_ERROR_INJECT__SHIFT 0xf 10769#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_SELECT_INJECT_DELAY__SHIFT 0x11 10770#define TCC_DSM_CNTL2__HIGH_RATE_TAG_ENABLE_ERROR_INJECT__SHIFT 0x12 10771#define TCC_DSM_CNTL2__HIGH_RATE_TAG_SELECT_INJECT_DELAY__SHIFT 0x14 10772#define TCC_DSM_CNTL2__LOW_RATE_TAG_ENABLE_ERROR_INJECT__SHIFT 0x15 10773#define TCC_DSM_CNTL2__LOW_RATE_TAG_SELECT_INJECT_DELAY__SHIFT 0x17 10774#define TCC_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a 10775#define TCC_DSM_CNTL2__CACHE_DATA_ENABLE_ERROR_INJECT_MASK 0x00000003L 10776#define TCC_DSM_CNTL2__CACHE_DATA_SELECT_INJECT_DELAY_MASK 0x00000004L 10777#define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_ENABLE_ERROR_INJECT_MASK 0x00000018L 10778#define TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_SELECT_INJECT_DELAY_MASK 0x00000020L 10779#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_ENABLE_ERROR_INJECT_MASK 0x000000C0L 10780#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_SELECT_INJECT_DELAY_MASK 0x00000100L 10781#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_ENABLE_ERROR_INJECT_MASK 0x00000600L 10782#define TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_SELECT_INJECT_DELAY_MASK 0x00000800L 10783#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_ENABLE_ERROR_INJECT_MASK 0x00003000L 10784#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_SELECT_INJECT_DELAY_MASK 0x00004000L 10785#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_ENABLE_ERROR_INJECT_MASK 0x00018000L 10786#define TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_SELECT_INJECT_DELAY_MASK 0x00020000L 10787#define TCC_DSM_CNTL2__HIGH_RATE_TAG_ENABLE_ERROR_INJECT_MASK 0x000C0000L 10788#define TCC_DSM_CNTL2__HIGH_RATE_TAG_SELECT_INJECT_DELAY_MASK 0x00100000L 10789#define TCC_DSM_CNTL2__LOW_RATE_TAG_ENABLE_ERROR_INJECT_MASK 0x00600000L 10790#define TCC_DSM_CNTL2__LOW_RATE_TAG_SELECT_INJECT_DELAY_MASK 0x00800000L 10791#define TCC_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L 10792//TCC_DSM_CNTL2A 10793#define TCC_DSM_CNTL2A__IN_USE_DEC_ENABLE_ERROR_INJECT__SHIFT 0x0 10794#define TCC_DSM_CNTL2A__IN_USE_DEC_SELECT_INJECT_DELAY__SHIFT 0x2 10795#define TCC_DSM_CNTL2A__IN_USE_TRANSFER_ENABLE_ERROR_INJECT__SHIFT 0x3 10796#define TCC_DSM_CNTL2A__IN_USE_TRANSFER_SELECT_INJECT_DELAY__SHIFT 0x5 10797#define TCC_DSM_CNTL2A__RETURN_DATA_ENABLE_ERROR_INJECT__SHIFT 0x6 10798#define TCC_DSM_CNTL2A__RETURN_DATA_SELECT_INJECT_DELAY__SHIFT 0x8 10799#define TCC_DSM_CNTL2A__RETURN_CONTROL_ENABLE_ERROR_INJECT__SHIFT 0x9 10800#define TCC_DSM_CNTL2A__RETURN_CONTROL_SELECT_INJECT_DELAY__SHIFT 0xb 10801#define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_ENABLE_ERROR_INJECT__SHIFT 0xc 10802#define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_SELECT_INJECT_DELAY__SHIFT 0xe 10803#define TCC_DSM_CNTL2A__WRITE_RETURN_ENABLE_ERROR_INJECT__SHIFT 0xf 10804#define TCC_DSM_CNTL2A__WRITE_RETURN_SELECT_INJECT_DELAY__SHIFT 0x11 10805#define TCC_DSM_CNTL2A__WRITE_CACHE_READ_ENABLE_ERROR_INJECT__SHIFT 0x12 10806#define TCC_DSM_CNTL2A__WRITE_CACHE_READ_SELECT_INJECT_DELAY__SHIFT 0x14 10807#define TCC_DSM_CNTL2A__SRC_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x15 10808#define TCC_DSM_CNTL2A__SRC_FIFO_SELECT_INJECT_DELAY__SHIFT 0x17 10809#define TCC_DSM_CNTL2A__SRC_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x18 10810#define TCC_DSM_CNTL2A__SRC_FIFO_NEXT_RAM_SELECT_INJECT_DELAY__SHIFT 0x1a 10811#define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x1b 10812#define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_SELECT_INJECT_DELAY__SHIFT 0x1d 10813#define TCC_DSM_CNTL2A__IN_USE_DEC_ENABLE_ERROR_INJECT_MASK 0x00000003L 10814#define TCC_DSM_CNTL2A__IN_USE_DEC_SELECT_INJECT_DELAY_MASK 0x00000004L 10815#define TCC_DSM_CNTL2A__IN_USE_TRANSFER_ENABLE_ERROR_INJECT_MASK 0x00000018L 10816#define TCC_DSM_CNTL2A__IN_USE_TRANSFER_SELECT_INJECT_DELAY_MASK 0x00000020L 10817#define TCC_DSM_CNTL2A__RETURN_DATA_ENABLE_ERROR_INJECT_MASK 0x000000C0L 10818#define TCC_DSM_CNTL2A__RETURN_DATA_SELECT_INJECT_DELAY_MASK 0x00000100L 10819#define TCC_DSM_CNTL2A__RETURN_CONTROL_ENABLE_ERROR_INJECT_MASK 0x00000600L 10820#define TCC_DSM_CNTL2A__RETURN_CONTROL_SELECT_INJECT_DELAY_MASK 0x00000800L 10821#define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_ENABLE_ERROR_INJECT_MASK 0x00003000L 10822#define TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_SELECT_INJECT_DELAY_MASK 0x00004000L 10823#define TCC_DSM_CNTL2A__WRITE_RETURN_ENABLE_ERROR_INJECT_MASK 0x00018000L 10824#define TCC_DSM_CNTL2A__WRITE_RETURN_SELECT_INJECT_DELAY_MASK 0x00020000L 10825#define TCC_DSM_CNTL2A__WRITE_CACHE_READ_ENABLE_ERROR_INJECT_MASK 0x000C0000L 10826#define TCC_DSM_CNTL2A__WRITE_CACHE_READ_SELECT_INJECT_DELAY_MASK 0x00100000L 10827#define TCC_DSM_CNTL2A__SRC_FIFO_ENABLE_ERROR_INJECT_MASK 0x00600000L 10828#define TCC_DSM_CNTL2A__SRC_FIFO_SELECT_INJECT_DELAY_MASK 0x00800000L 10829#define TCC_DSM_CNTL2A__SRC_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT_MASK 0x03000000L 10830#define TCC_DSM_CNTL2A__SRC_FIFO_NEXT_RAM_SELECT_INJECT_DELAY_MASK 0x04000000L 10831#define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_ENABLE_ERROR_INJECT_MASK 0x18000000L 10832#define TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_SELECT_INJECT_DELAY_MASK 0x20000000L 10833//TCC_DSM_CNTL2B 10834#define TCC_DSM_CNTL2B__LATENCY_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x0 10835#define TCC_DSM_CNTL2B__LATENCY_FIFO_SELECT_INJECT_DELAY__SHIFT 0x2 10836#define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x3 10837#define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_SELECT_INJECT_DELAY__SHIFT 0x5 10838#define TCC_DSM_CNTL2B__LATENCY_FIFO_ENABLE_ERROR_INJECT_MASK 0x00000003L 10839#define TCC_DSM_CNTL2B__LATENCY_FIFO_SELECT_INJECT_DELAY_MASK 0x00000004L 10840#define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT_MASK 0x00000018L 10841#define TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_SELECT_INJECT_DELAY_MASK 0x00000020L 10842//TCC_WBINVL2 10843#define TCC_WBINVL2__DONE__SHIFT 0x4 10844#define TCC_WBINVL2__DONE_MASK 0x00000010L 10845//TCC_SOFT_RESET 10846#define TCC_SOFT_RESET__HALT_FOR_RESET__SHIFT 0x0 10847#define TCC_SOFT_RESET__HALT_FOR_RESET_MASK 0x00000001L 10848//TCA_CTRL 10849#define TCA_CTRL__HOLE_TIMEOUT__SHIFT 0x0 10850#define TCA_CTRL__RB_STILL_4_PHASE__SHIFT 0x4 10851#define TCA_CTRL__RB_AS_TCI__SHIFT 0x5 10852#define TCA_CTRL__DISABLE_UTCL2_PRIORITY__SHIFT 0x6 10853#define TCA_CTRL__DISABLE_RB_ONLY_TCA_ARBITER__SHIFT 0x7 10854#define TCA_CTRL__HOLE_TIMEOUT_MASK 0x0000000FL 10855#define TCA_CTRL__RB_STILL_4_PHASE_MASK 0x00000010L 10856#define TCA_CTRL__RB_AS_TCI_MASK 0x00000020L 10857#define TCA_CTRL__DISABLE_UTCL2_PRIORITY_MASK 0x00000040L 10858#define TCA_CTRL__DISABLE_RB_ONLY_TCA_ARBITER_MASK 0x00000080L 10859//TCA_BURST_MASK 10860#define TCA_BURST_MASK__ADDR_MASK__SHIFT 0x0 10861#define TCA_BURST_MASK__ADDR_MASK_MASK 0xFFFFFFFFL 10862//TCA_BURST_CTRL 10863#define TCA_BURST_CTRL__MAX_BURST__SHIFT 0x0 10864#define TCA_BURST_CTRL__RB_DISABLE__SHIFT 0x3 10865#define TCA_BURST_CTRL__TCP_DISABLE__SHIFT 0x4 10866#define TCA_BURST_CTRL__SQC_DISABLE__SHIFT 0x5 10867#define TCA_BURST_CTRL__CPF_DISABLE__SHIFT 0x6 10868#define TCA_BURST_CTRL__CPG_DISABLE__SHIFT 0x7 10869#define TCA_BURST_CTRL__IA_DISABLE__SHIFT 0x8 10870#define TCA_BURST_CTRL__WD_DISABLE__SHIFT 0x9 10871#define TCA_BURST_CTRL__SQG_DISABLE__SHIFT 0xa 10872#define TCA_BURST_CTRL__UTCL2_DISABLE__SHIFT 0xb 10873#define TCA_BURST_CTRL__TPI_DISABLE__SHIFT 0xc 10874#define TCA_BURST_CTRL__RLC_DISABLE__SHIFT 0xd 10875#define TCA_BURST_CTRL__PA_DISABLE__SHIFT 0xe 10876#define TCA_BURST_CTRL__MAX_BURST_MASK 0x00000007L 10877#define TCA_BURST_CTRL__RB_DISABLE_MASK 0x00000008L 10878#define TCA_BURST_CTRL__TCP_DISABLE_MASK 0x00000010L 10879#define TCA_BURST_CTRL__SQC_DISABLE_MASK 0x00000020L 10880#define TCA_BURST_CTRL__CPF_DISABLE_MASK 0x00000040L 10881#define TCA_BURST_CTRL__CPG_DISABLE_MASK 0x00000080L 10882#define TCA_BURST_CTRL__IA_DISABLE_MASK 0x00000100L 10883#define TCA_BURST_CTRL__WD_DISABLE_MASK 0x00000200L 10884#define TCA_BURST_CTRL__SQG_DISABLE_MASK 0x00000400L 10885#define TCA_BURST_CTRL__UTCL2_DISABLE_MASK 0x00000800L 10886#define TCA_BURST_CTRL__TPI_DISABLE_MASK 0x00001000L 10887#define TCA_BURST_CTRL__RLC_DISABLE_MASK 0x00002000L 10888#define TCA_BURST_CTRL__PA_DISABLE_MASK 0x00004000L 10889//TCA_DSM_CNTL 10890#define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_DATA_SEL__SHIFT 0x0 10891#define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_SINGLE_WRITE__SHIFT 0x2 10892#define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_DATA_SEL__SHIFT 0x3 10893#define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_SINGLE_WRITE__SHIFT 0x5 10894#define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_DATA_SEL_MASK 0x00000003L 10895#define TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_SINGLE_WRITE_MASK 0x00000004L 10896#define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_DATA_SEL_MASK 0x00000018L 10897#define TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_SINGLE_WRITE_MASK 0x00000020L 10898//TCA_DSM_CNTL2 10899#define TCA_DSM_CNTL2__HOLE_FIFO_SED_ENABLE_ERROR_INJECT__SHIFT 0x0 10900#define TCA_DSM_CNTL2__HOLE_FIFO_SED_SELECT_INJECT_DELAY__SHIFT 0x2 10901#define TCA_DSM_CNTL2__REQ_FIFO_SED_ENABLE_ERROR_INJECT__SHIFT 0x3 10902#define TCA_DSM_CNTL2__REQ_FIFO_SED_SELECT_INJECT_DELAY__SHIFT 0x5 10903#define TCA_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a 10904#define TCA_DSM_CNTL2__HOLE_FIFO_SED_ENABLE_ERROR_INJECT_MASK 0x00000003L 10905#define TCA_DSM_CNTL2__HOLE_FIFO_SED_SELECT_INJECT_DELAY_MASK 0x00000004L 10906#define TCA_DSM_CNTL2__REQ_FIFO_SED_ENABLE_ERROR_INJECT_MASK 0x00000018L 10907#define TCA_DSM_CNTL2__REQ_FIFO_SED_SELECT_INJECT_DELAY_MASK 0x00000020L 10908#define TCA_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L 10909//TCA_EDC_CNT 10910#define TCA_EDC_CNT__HOLE_FIFO_SED_COUNT__SHIFT 0x0 10911#define TCA_EDC_CNT__REQ_FIFO_SED_COUNT__SHIFT 0x2 10912#define TCA_EDC_CNT__HOLE_FIFO_SED_COUNT_MASK 0x00000003L 10913#define TCA_EDC_CNT__REQ_FIFO_SED_COUNT_MASK 0x0000000CL 10914 10915 10916// addressBlock: gc_shdec 10917//SPI_SHADER_PGM_RSRC3_PS 10918#define SPI_SHADER_PGM_RSRC3_PS__CU_EN__SHIFT 0x0 10919#define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT__SHIFT 0x10 10920#define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD__SHIFT 0x16 10921#define SPI_SHADER_PGM_RSRC3_PS__SIMD_DISABLE__SHIFT 0x1a 10922#define SPI_SHADER_PGM_RSRC3_PS__CU_EN_MASK 0x0000FFFFL 10923#define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT_MASK 0x003F0000L 10924#define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD_MASK 0x03C00000L 10925#define SPI_SHADER_PGM_RSRC3_PS__SIMD_DISABLE_MASK 0x3C000000L 10926//SPI_SHADER_PGM_LO_PS 10927#define SPI_SHADER_PGM_LO_PS__MEM_BASE__SHIFT 0x0 10928#define SPI_SHADER_PGM_LO_PS__MEM_BASE_MASK 0xFFFFFFFFL 10929//SPI_SHADER_PGM_HI_PS 10930#define SPI_SHADER_PGM_HI_PS__MEM_BASE__SHIFT 0x0 10931#define SPI_SHADER_PGM_HI_PS__MEM_BASE_MASK 0xFFL 10932//SPI_SHADER_PGM_RSRC1_PS 10933#define SPI_SHADER_PGM_RSRC1_PS__VGPRS__SHIFT 0x0 10934#define SPI_SHADER_PGM_RSRC1_PS__SGPRS__SHIFT 0x6 10935#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY__SHIFT 0xa 10936#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE__SHIFT 0xc 10937#define SPI_SHADER_PGM_RSRC1_PS__PRIV__SHIFT 0x14 10938#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP__SHIFT 0x15 10939#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE__SHIFT 0x17 10940#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE__SHIFT 0x18 10941#define SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL__SHIFT 0x1d 10942#define SPI_SHADER_PGM_RSRC1_PS__VGPRS_MASK 0x0000003FL 10943#define SPI_SHADER_PGM_RSRC1_PS__SGPRS_MASK 0x000003C0L 10944#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY_MASK 0x00000C00L 10945#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE_MASK 0x000FF000L 10946#define SPI_SHADER_PGM_RSRC1_PS__PRIV_MASK 0x00100000L 10947#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP_MASK 0x00200000L 10948#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE_MASK 0x00800000L 10949#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE_MASK 0x01000000L 10950#define SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL_MASK 0x20000000L 10951//SPI_SHADER_PGM_RSRC2_PS 10952#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN__SHIFT 0x0 10953#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR__SHIFT 0x1 10954#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT__SHIFT 0x6 10955#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN__SHIFT 0x7 10956#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE__SHIFT 0x8 10957#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN__SHIFT 0x10 10958#define SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID__SHIFT 0x19 10959#define SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION__SHIFT 0x1a 10960#define SPI_SHADER_PGM_RSRC2_PS__SKIP_USGPR0__SHIFT 0x1b 10961#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB__SHIFT 0x1c 10962#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN_MASK 0x00000001L 10963#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MASK 0x0000003EL 10964#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT_MASK 0x00000040L 10965#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN_MASK 0x00000080L 10966#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE_MASK 0x0000FF00L 10967#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN_MASK 0x01FF0000L 10968#define SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID_MASK 0x02000000L 10969#define SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION_MASK 0x04000000L 10970#define SPI_SHADER_PGM_RSRC2_PS__SKIP_USGPR0_MASK 0x08000000L 10971#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB_MASK 0x10000000L 10972//SPI_SHADER_USER_DATA_PS_0 10973#define SPI_SHADER_USER_DATA_PS_0__DATA__SHIFT 0x0 10974#define SPI_SHADER_USER_DATA_PS_0__DATA_MASK 0xFFFFFFFFL 10975//SPI_SHADER_USER_DATA_PS_1 10976#define SPI_SHADER_USER_DATA_PS_1__DATA__SHIFT 0x0 10977#define SPI_SHADER_USER_DATA_PS_1__DATA_MASK 0xFFFFFFFFL 10978//SPI_SHADER_USER_DATA_PS_2 10979#define SPI_SHADER_USER_DATA_PS_2__DATA__SHIFT 0x0 10980#define SPI_SHADER_USER_DATA_PS_2__DATA_MASK 0xFFFFFFFFL 10981//SPI_SHADER_USER_DATA_PS_3 10982#define SPI_SHADER_USER_DATA_PS_3__DATA__SHIFT 0x0 10983#define SPI_SHADER_USER_DATA_PS_3__DATA_MASK 0xFFFFFFFFL 10984//SPI_SHADER_USER_DATA_PS_4 10985#define SPI_SHADER_USER_DATA_PS_4__DATA__SHIFT 0x0 10986#define SPI_SHADER_USER_DATA_PS_4__DATA_MASK 0xFFFFFFFFL 10987//SPI_SHADER_USER_DATA_PS_5 10988#define SPI_SHADER_USER_DATA_PS_5__DATA__SHIFT 0x0 10989#define SPI_SHADER_USER_DATA_PS_5__DATA_MASK 0xFFFFFFFFL 10990//SPI_SHADER_USER_DATA_PS_6 10991#define SPI_SHADER_USER_DATA_PS_6__DATA__SHIFT 0x0 10992#define SPI_SHADER_USER_DATA_PS_6__DATA_MASK 0xFFFFFFFFL 10993//SPI_SHADER_USER_DATA_PS_7 10994#define SPI_SHADER_USER_DATA_PS_7__DATA__SHIFT 0x0 10995#define SPI_SHADER_USER_DATA_PS_7__DATA_MASK 0xFFFFFFFFL 10996//SPI_SHADER_USER_DATA_PS_8 10997#define SPI_SHADER_USER_DATA_PS_8__DATA__SHIFT 0x0 10998#define SPI_SHADER_USER_DATA_PS_8__DATA_MASK 0xFFFFFFFFL 10999//SPI_SHADER_USER_DATA_PS_9 11000#define SPI_SHADER_USER_DATA_PS_9__DATA__SHIFT 0x0
11001#define SPI_SHADER_USER_DATA_PS_9__DATA_MASK 0xFFFFFFFFL 11002//SPI_SHADER_USER_DATA_PS_10 11003#define SPI_SHADER_USER_DATA_PS_10__DATA__SHIFT 0x0 11004#define SPI_SHADER_USER_DATA_PS_10__DATA_MASK 0xFFFFFFFFL 11005//SPI_SHADER_USER_DATA_PS_11 11006#define SPI_SHADER_USER_DATA_PS_11__DATA__SHIFT 0x0 11007#define SPI_SHADER_USER_DATA_PS_11__DATA_MASK 0xFFFFFFFFL 11008//SPI_SHADER_USER_DATA_PS_12 11009#define SPI_SHADER_USER_DATA_PS_12__DATA__SHIFT 0x0 11010#define SPI_SHADER_USER_DATA_PS_12__DATA_MASK 0xFFFFFFFFL 11011//SPI_SHADER_USER_DATA_PS_13 11012#define SPI_SHADER_USER_DATA_PS_13__DATA__SHIFT 0x0 11013#define SPI_SHADER_USER_DATA_PS_13__DATA_MASK 0xFFFFFFFFL 11014//SPI_SHADER_USER_DATA_PS_14 11015#define SPI_SHADER_USER_DATA_PS_14__DATA__SHIFT 0x0 11016#define SPI_SHADER_USER_DATA_PS_14__DATA_MASK 0xFFFFFFFFL 11017//SPI_SHADER_USER_DATA_PS_15 11018#define SPI_SHADER_USER_DATA_PS_15__DATA__SHIFT 0x0 11019#define SPI_SHADER_USER_DATA_PS_15__DATA_MASK 0xFFFFFFFFL 11020//SPI_SHADER_USER_DATA_PS_16 11021#define SPI_SHADER_USER_DATA_PS_16__DATA__SHIFT 0x0 11022#define SPI_SHADER_USER_DATA_PS_16__DATA_MASK 0xFFFFFFFFL 11023//SPI_SHADER_USER_DATA_PS_17 11024#define SPI_SHADER_USER_DATA_PS_17__DATA__SHIFT 0x0 11025#define SPI_SHADER_USER_DATA_PS_17__DATA_MASK 0xFFFFFFFFL 11026//SPI_SHADER_USER_DATA_PS_18 11027#define SPI_SHADER_USER_DATA_PS_18__DATA__SHIFT 0x0 11028#define SPI_SHADER_USER_DATA_PS_18__DATA_MASK 0xFFFFFFFFL 11029//SPI_SHADER_USER_DATA_PS_19 11030#define SPI_SHADER_USER_DATA_PS_19__DATA__SHIFT 0x0 11031#define SPI_SHADER_USER_DATA_PS_19__DATA_MASK 0xFFFFFFFFL 11032//SPI_SHADER_USER_DATA_PS_20 11033#define SPI_SHADER_USER_DATA_PS_20__DATA__SHIFT 0x0 11034#define SPI_SHADER_USER_DATA_PS_20__DATA_MASK 0xFFFFFFFFL 11035//SPI_SHADER_USER_DATA_PS_21 11036#define SPI_SHADER_USER_DATA_PS_21__DATA__SHIFT 0x0 11037#define SPI_SHADER_USER_DATA_PS_21__DATA_MASK 0xFFFFFFFFL 11038//SPI_SHADER_USER_DATA_PS_22 11039#define SPI_SHADER_USER_DATA_PS_22__DATA__SHIFT 0x0 11040#define SPI_SHADER_USER_DATA_PS_22__DATA_MASK 0xFFFFFFFFL 11041//SPI_SHADER_USER_DATA_PS_23 11042#define SPI_SHADER_USER_DATA_PS_23__DATA__SHIFT 0x0 11043#define SPI_SHADER_USER_DATA_PS_23__DATA_MASK 0xFFFFFFFFL 11044//SPI_SHADER_USER_DATA_PS_24 11045#define SPI_SHADER_USER_DATA_PS_24__DATA__SHIFT 0x0 11046#define SPI_SHADER_USER_DATA_PS_24__DATA_MASK 0xFFFFFFFFL 11047//SPI_SHADER_USER_DATA_PS_25 11048#define SPI_SHADER_USER_DATA_PS_25__DATA__SHIFT 0x0 11049#define SPI_SHADER_USER_DATA_PS_25__DATA_MASK 0xFFFFFFFFL 11050//SPI_SHADER_USER_DATA_PS_26 11051#define SPI_SHADER_USER_DATA_PS_26__DATA__SHIFT 0x0 11052#define SPI_SHADER_USER_DATA_PS_26__DATA_MASK 0xFFFFFFFFL 11053//SPI_SHADER_USER_DATA_PS_27 11054#define SPI_SHADER_USER_DATA_PS_27__DATA__SHIFT 0x0 11055#define SPI_SHADER_USER_DATA_PS_27__DATA_MASK 0xFFFFFFFFL 11056//SPI_SHADER_USER_DATA_PS_28 11057#define SPI_SHADER_USER_DATA_PS_28__DATA__SHIFT 0x0 11058#define SPI_SHADER_USER_DATA_PS_28__DATA_MASK 0xFFFFFFFFL 11059//SPI_SHADER_USER_DATA_PS_29 11060#define SPI_SHADER_USER_DATA_PS_29__DATA__SHIFT 0x0 11061#define SPI_SHADER_USER_DATA_PS_29__DATA_MASK 0xFFFFFFFFL 11062//SPI_SHADER_USER_DATA_PS_30 11063#define SPI_SHADER_USER_DATA_PS_30__DATA__SHIFT 0x0 11064#define SPI_SHADER_USER_DATA_PS_30__DATA_MASK 0xFFFFFFFFL 11065//SPI_SHADER_USER_DATA_PS_31 11066#define SPI_SHADER_USER_DATA_PS_31__DATA__SHIFT 0x0 11067#define SPI_SHADER_USER_DATA_PS_31__DATA_MASK 0xFFFFFFFFL 11068//SPI_SHADER_PGM_RSRC3_VS 11069#define SPI_SHADER_PGM_RSRC3_VS__CU_EN__SHIFT 0x0 11070#define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT__SHIFT 0x10 11071#define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD__SHIFT 0x16 11072#define SPI_SHADER_PGM_RSRC3_VS__SIMD_DISABLE__SHIFT 0x1a 11073#define SPI_SHADER_PGM_RSRC3_VS__CU_EN_MASK 0x0000FFFFL 11074#define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT_MASK 0x003F0000L 11075#define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD_MASK 0x03C00000L 11076#define SPI_SHADER_PGM_RSRC3_VS__SIMD_DISABLE_MASK 0x3C000000L 11077//SPI_SHADER_LATE_ALLOC_VS 11078#define SPI_SHADER_LATE_ALLOC_VS__LIMIT__SHIFT 0x0 11079#define SPI_SHADER_LATE_ALLOC_VS__LIMIT_MASK 0x0000003FL 11080//SPI_SHADER_PGM_LO_VS 11081#define SPI_SHADER_PGM_LO_VS__MEM_BASE__SHIFT 0x0 11082#define SPI_SHADER_PGM_LO_VS__MEM_BASE_MASK 0xFFFFFFFFL 11083//SPI_SHADER_PGM_HI_VS 11084#define SPI_SHADER_PGM_HI_VS__MEM_BASE__SHIFT 0x0 11085#define SPI_SHADER_PGM_HI_VS__MEM_BASE_MASK 0xFFL 11086//SPI_SHADER_PGM_RSRC1_VS 11087#define SPI_SHADER_PGM_RSRC1_VS__VGPRS__SHIFT 0x0 11088#define SPI_SHADER_PGM_RSRC1_VS__SGPRS__SHIFT 0x6 11089#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY__SHIFT 0xa 11090#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE__SHIFT 0xc 11091#define SPI_SHADER_PGM_RSRC1_VS__PRIV__SHIFT 0x14 11092#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP__SHIFT 0x15 11093#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE__SHIFT 0x17 11094#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT__SHIFT 0x18 11095#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE__SHIFT 0x1a 11096#define SPI_SHADER_PGM_RSRC1_VS__FP16_OVFL__SHIFT 0x1f 11097#define SPI_SHADER_PGM_RSRC1_VS__VGPRS_MASK 0x0000003FL 11098#define SPI_SHADER_PGM_RSRC1_VS__SGPRS_MASK 0x000003C0L 11099#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY_MASK 0x00000C00L 11100#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE_MASK 0x000FF000L 11101#define SPI_SHADER_PGM_RSRC1_VS__PRIV_MASK 0x00100000L 11102#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP_MASK 0x00200000L 11103#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE_MASK 0x00800000L 11104#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT_MASK 0x03000000L 11105#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE_MASK 0x04000000L 11106#define SPI_SHADER_PGM_RSRC1_VS__FP16_OVFL_MASK 0x80000000L 11107//SPI_SHADER_PGM_RSRC2_VS 11108#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN__SHIFT 0x0 11109#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR__SHIFT 0x1 11110#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT__SHIFT 0x6 11111#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN__SHIFT 0x7 11112#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN__SHIFT 0x8 11113#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN__SHIFT 0x9 11114#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN__SHIFT 0xa 11115#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN__SHIFT 0xb 11116#define SPI_SHADER_PGM_RSRC2_VS__SO_EN__SHIFT 0xc 11117#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN__SHIFT 0xd 11118#define SPI_SHADER_PGM_RSRC2_VS__PC_BASE_EN__SHIFT 0x16 11119#define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN__SHIFT 0x18 11120#define SPI_SHADER_PGM_RSRC2_VS__SKIP_USGPR0__SHIFT 0x1b 11121#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MSB__SHIFT 0x1c 11122#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN_MASK 0x00000001L 11123#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MASK 0x0000003EL 11124#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT_MASK 0x00000040L 11125#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN_MASK 0x00000080L 11126#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN_MASK 0x00000100L 11127#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN_MASK 0x00000200L 11128#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN_MASK 0x00000400L 11129#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN_MASK 0x00000800L 11130#define SPI_SHADER_PGM_RSRC2_VS__SO_EN_MASK 0x00001000L 11131#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN_MASK 0x003FE000L 11132#define SPI_SHADER_PGM_RSRC2_VS__PC_BASE_EN_MASK 0x00400000L 11133#define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN_MASK 0x01000000L 11134#define SPI_SHADER_PGM_RSRC2_VS__SKIP_USGPR0_MASK 0x08000000L 11135#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MSB_MASK 0x10000000L 11136//SPI_SHADER_USER_DATA_VS_0 11137#define SPI_SHADER_USER_DATA_VS_0__DATA__SHIFT 0x0 11138#define SPI_SHADER_USER_DATA_VS_0__DATA_MASK 0xFFFFFFFFL 11139//SPI_SHADER_USER_DATA_VS_1 11140#define SPI_SHADER_USER_DATA_VS_1__DATA__SHIFT 0x0 11141#define SPI_SHADER_USER_DATA_VS_1__DATA_MASK 0xFFFFFFFFL 11142//SPI_SHADER_USER_DATA_VS_2 11143#define SPI_SHADER_USER_DATA_VS_2__DATA__SHIFT 0x0 11144#define SPI_SHADER_USER_DATA_VS_2__DATA_MASK 0xFFFFFFFFL 11145//SPI_SHADER_USER_DATA_VS_3 11146#define SPI_SHADER_USER_DATA_VS_3__DATA__SHIFT 0x0 11147#define SPI_SHADER_USER_DATA_VS_3__DATA_MASK 0xFFFFFFFFL 11148//SPI_SHADER_USER_DATA_VS_4 11149#define SPI_SHADER_USER_DATA_VS_4__DATA__SHIFT 0x0 11150#define SPI_SHADER_USER_DATA_VS_4__DATA_MASK 0xFFFFFFFFL 11151//SPI_SHADER_USER_DATA_VS_5 11152#define SPI_SHADER_USER_DATA_VS_5__DATA__SHIFT 0x0 11153#define SPI_SHADER_USER_DATA_VS_5__DATA_MASK 0xFFFFFFFFL 11154//SPI_SHADER_USER_DATA_VS_6 11155#define SPI_SHADER_USER_DATA_VS_6__DATA__SHIFT 0x0 11156#define SPI_SHADER_USER_DATA_VS_6__DATA_MASK 0xFFFFFFFFL 11157//SPI_SHADER_USER_DATA_VS_7 11158#define SPI_SHADER_USER_DATA_VS_7__DATA__SHIFT 0x0 11159#define SPI_SHADER_USER_DATA_VS_7__DATA_MASK 0xFFFFFFFFL 11160//SPI_SHADER_USER_DATA_VS_8 11161#define SPI_SHADER_USER_DATA_VS_8__DATA__SHIFT 0x0 11162#define SPI_SHADER_USER_DATA_VS_8__DATA_MASK 0xFFFFFFFFL 11163//SPI_SHADER_USER_DATA_VS_9 11164#define SPI_SHADER_USER_DATA_VS_9__DATA__SHIFT 0x0 11165#define SPI_SHADER_USER_DATA_VS_9__DATA_MASK 0xFFFFFFFFL 11166//SPI_SHADER_USER_DATA_VS_10 11167#define SPI_SHADER_USER_DATA_VS_10__DATA__SHIFT 0x0 11168#define SPI_SHADER_USER_DATA_VS_10__DATA_MASK 0xFFFFFFFFL 11169//SPI_SHADER_USER_DATA_VS_11 11170#define SPI_SHADER_USER_DATA_VS_11__DATA__SHIFT 0x0 11171#define SPI_SHADER_USER_DATA_VS_11__DATA_MASK 0xFFFFFFFFL 11172//SPI_SHADER_USER_DATA_VS_12 11173#define SPI_SHADER_USER_DATA_VS_12__DATA__SHIFT 0x0 11174#define SPI_SHADER_USER_DATA_VS_12__DATA_MASK 0xFFFFFFFFL 11175//SPI_SHADER_USER_DATA_VS_13 11176#define SPI_SHADER_USER_DATA_VS_13__DATA__SHIFT 0x0 11177#define SPI_SHADER_USER_DATA_VS_13__DATA_MASK 0xFFFFFFFFL 11178//SPI_SHADER_USER_DATA_VS_14 11179#define SPI_SHADER_USER_DATA_VS_14__DATA__SHIFT 0x0 11180#define SPI_SHADER_USER_DATA_VS_14__DATA_MASK 0xFFFFFFFFL 11181//SPI_SHADER_USER_DATA_VS_15 11182#define SPI_SHADER_USER_DATA_VS_15__DATA__SHIFT 0x0 11183#define SPI_SHADER_USER_DATA_VS_15__DATA_MASK 0xFFFFFFFFL 11184//SPI_SHADER_USER_DATA_VS_16 11185#define SPI_SHADER_USER_DATA_VS_16__DATA__SHIFT 0x0 11186#define SPI_SHADER_USER_DATA_VS_16__DATA_MASK 0xFFFFFFFFL 11187//SPI_SHADER_USER_DATA_VS_17 11188#define SPI_SHADER_USER_DATA_VS_17__DATA__SHIFT 0x0 11189#define SPI_SHADER_USER_DATA_VS_17__DATA_MASK 0xFFFFFFFFL 11190//SPI_SHADER_USER_DATA_VS_18 11191#define SPI_SHADER_USER_DATA_VS_18__DATA__SHIFT 0x0 11192#define SPI_SHADER_USER_DATA_VS_18__DATA_MASK 0xFFFFFFFFL 11193//SPI_SHADER_USER_DATA_VS_19 11194#define SPI_SHADER_USER_DATA_VS_19__DATA__SHIFT 0x0 11195#define SPI_SHADER_USER_DATA_VS_19__DATA_MASK 0xFFFFFFFFL 11196//SPI_SHADER_USER_DATA_VS_20 11197#define SPI_SHADER_USER_DATA_VS_20__DATA__SHIFT 0x0 11198#define SPI_SHADER_USER_DATA_VS_20__DATA_MASK 0xFFFFFFFFL 11199//SPI_SHADER_USER_DATA_VS_21 11200#define SPI_SHADER_USER_DATA_VS_21__DATA__SHIFT 0x0 11201#define SPI_SHADER_USER_DATA_VS_21__DATA_MASK 0xFFFFFFFFL 11202//SPI_SHADER_USER_DATA_VS_22 11203#define SPI_SHADER_USER_DATA_VS_22__DATA__SHIFT 0x0 11204#define SPI_SHADER_USER_DATA_VS_22__DATA_MASK 0xFFFFFFFFL 11205//SPI_SHADER_USER_DATA_VS_23 11206#define SPI_SHADER_USER_DATA_VS_23__DATA__SHIFT 0x0 11207#define SPI_SHADER_USER_DATA_VS_23__DATA_MASK 0xFFFFFFFFL 11208//SPI_SHADER_USER_DATA_VS_24 11209#define SPI_SHADER_USER_DATA_VS_24__DATA__SHIFT 0x0 11210#define SPI_SHADER_USER_DATA_VS_24__DATA_MASK 0xFFFFFFFFL 11211//SPI_SHADER_USER_DATA_VS_25 11212#define SPI_SHADER_USER_DATA_VS_25__DATA__SHIFT 0x0 11213#define SPI_SHADER_USER_DATA_VS_25__DATA_MASK 0xFFFFFFFFL 11214//SPI_SHADER_USER_DATA_VS_26 11215#define SPI_SHADER_USER_DATA_VS_26__DATA__SHIFT 0x0 11216#define SPI_SHADER_USER_DATA_VS_26__DATA_MASK 0xFFFFFFFFL 11217//SPI_SHADER_USER_DATA_VS_27 11218#define SPI_SHADER_USER_DATA_VS_27__DATA__SHIFT 0x0 11219#define SPI_SHADER_USER_DATA_VS_27__DATA_MASK 0xFFFFFFFFL 11220//SPI_SHADER_USER_DATA_VS_28 11221#define SPI_SHADER_USER_DATA_VS_28__DATA__SHIFT 0x0 11222#define SPI_SHADER_USER_DATA_VS_28__DATA_MASK 0xFFFFFFFFL 11223//SPI_SHADER_USER_DATA_VS_29 11224#define SPI_SHADER_USER_DATA_VS_29__DATA__SHIFT 0x0 11225#define SPI_SHADER_USER_DATA_VS_29__DATA_MASK 0xFFFFFFFFL 11226//SPI_SHADER_USER_DATA_VS_30 11227#define SPI_SHADER_USER_DATA_VS_30__DATA__SHIFT 0x0 11228#define SPI_SHADER_USER_DATA_VS_30__DATA_MASK 0xFFFFFFFFL 11229//SPI_SHADER_USER_DATA_VS_31 11230#define SPI_SHADER_USER_DATA_VS_31__DATA__SHIFT 0x0 11231#define SPI_SHADER_USER_DATA_VS_31__DATA_MASK 0xFFFFFFFFL 11232//SPI_SHADER_PGM_RSRC2_GS_VS 11233#define SPI_SHADER_PGM_RSRC2_GS_VS__SCRATCH_EN__SHIFT 0x0 11234#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR__SHIFT 0x1 11235#define SPI_SHADER_PGM_RSRC2_GS_VS__TRAP_PRESENT__SHIFT 0x6 11236#define SPI_SHADER_PGM_RSRC2_GS_VS__EXCP_EN__SHIFT 0x7 11237#define SPI_SHADER_PGM_RSRC2_GS_VS__VGPR_COMP_CNT__SHIFT 0x10 11238#define SPI_SHADER_PGM_RSRC2_GS_VS__OC_LDS_EN__SHIFT 0x12 11239#define SPI_SHADER_PGM_RSRC2_GS_VS__LDS_SIZE__SHIFT 0x13 11240#define SPI_SHADER_PGM_RSRC2_GS_VS__SKIP_USGPR0__SHIFT 0x1b 11241#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MSB__SHIFT 0x1c 11242#define SPI_SHADER_PGM_RSRC2_GS_VS__SCRATCH_EN_MASK 0x00000001L 11243#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MASK 0x0000003EL 11244#define SPI_SHADER_PGM_RSRC2_GS_VS__TRAP_PRESENT_MASK 0x00000040L 11245#define SPI_SHADER_PGM_RSRC2_GS_VS__EXCP_EN_MASK 0x0000FF80L 11246#define SPI_SHADER_PGM_RSRC2_GS_VS__VGPR_COMP_CNT_MASK 0x00030000L 11247#define SPI_SHADER_PGM_RSRC2_GS_VS__OC_LDS_EN_MASK 0x00040000L 11248#define SPI_SHADER_PGM_RSRC2_GS_VS__LDS_SIZE_MASK 0x07F80000L 11249#define SPI_SHADER_PGM_RSRC2_GS_VS__SKIP_USGPR0_MASK 0x08000000L 11250#define SPI_SHADER_PGM_RSRC2_GS_VS__USER_SGPR_MSB_MASK 0x10000000L 11251//SPI_SHADER_PGM_RSRC4_GS 11252#define SPI_SHADER_PGM_RSRC4_GS__GROUP_FIFO_DEPTH__SHIFT 0x0 11253#define SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS__SHIFT 0x7 11254#define SPI_SHADER_PGM_RSRC4_GS__GROUP_FIFO_DEPTH_MASK 0x0000007FL 11255#define SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS_MASK 0x00003F80L 11256//SPI_SHADER_USER_DATA_ADDR_LO_GS 11257#define SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE__SHIFT 0x0 11258#define SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE_MASK 0xFFFFFFFFL 11259//SPI_SHADER_USER_DATA_ADDR_HI_GS 11260#define SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE__SHIFT 0x0 11261#define SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE_MASK 0xFFFFFFFFL 11262//SPI_SHADER_PGM_LO_ES 11263#define SPI_SHADER_PGM_LO_ES__MEM_BASE__SHIFT 0x0 11264#define SPI_SHADER_PGM_LO_ES__MEM_BASE_MASK 0xFFFFFFFFL 11265//SPI_SHADER_PGM_HI_ES 11266#define SPI_SHADER_PGM_HI_ES__MEM_BASE__SHIFT 0x0 11267#define SPI_SHADER_PGM_HI_ES__MEM_BASE_MASK 0xFFL 11268//SPI_SHADER_PGM_RSRC3_GS 11269#define SPI_SHADER_PGM_RSRC3_GS__CU_EN__SHIFT 0x0 11270#define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT__SHIFT 0x10 11271#define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD__SHIFT 0x16 11272#define SPI_SHADER_PGM_RSRC3_GS__SIMD_DISABLE__SHIFT 0x1a 11273#define SPI_SHADER_PGM_RSRC3_GS__CU_EN_MASK 0x0000FFFFL 11274#define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT_MASK 0x003F0000L 11275#define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD_MASK 0x03C00000L 11276#define SPI_SHADER_PGM_RSRC3_GS__SIMD_DISABLE_MASK 0x3C000000L 11277//SPI_SHADER_PGM_LO_GS 11278#define SPI_SHADER_PGM_LO_GS__MEM_BASE__SHIFT 0x0 11279#define SPI_SHADER_PGM_LO_GS__MEM_BASE_MASK 0xFFFFFFFFL 11280//SPI_SHADER_PGM_HI_GS 11281#define SPI_SHADER_PGM_HI_GS__MEM_BASE__SHIFT 0x0 11282#define SPI_SHADER_PGM_HI_GS__MEM_BASE_MASK 0xFFL 11283//SPI_SHADER_PGM_RSRC1_GS 11284#define SPI_SHADER_PGM_RSRC1_GS__VGPRS__SHIFT 0x0 11285#define SPI_SHADER_PGM_RSRC1_GS__SGPRS__SHIFT 0x6 11286#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY__SHIFT 0xa 11287#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE__SHIFT 0xc 11288#define SPI_SHADER_PGM_RSRC1_GS__PRIV__SHIFT 0x14 11289#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP__SHIFT 0x15 11290#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE__SHIFT 0x17 11291#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE__SHIFT 0x18 11292#define SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT__SHIFT 0x1d 11293#define SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL__SHIFT 0x1f 11294#define SPI_SHADER_PGM_RSRC1_GS__VGPRS_MASK 0x0000003FL 11295#define SPI_SHADER_PGM_RSRC1_GS__SGPRS_MASK 0x000003C0L 11296#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY_MASK 0x00000C00L 11297#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE_MASK 0x000FF000L 11298#define SPI_SHADER_PGM_RSRC1_GS__PRIV_MASK 0x00100000L 11299#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP_MASK 0x00200000L 11300#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE_MASK 0x00800000L 11301#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE_MASK 0x01000000L 11302#define SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT_MASK 0x60000000L 11303#define SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL_MASK 0x80000000L 11304//SPI_SHADER_PGM_RSRC2_GS 11305#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN__SHIFT 0x0 11306#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR__SHIFT 0x1 11307#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT__SHIFT 0x6 11308#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN__SHIFT 0x7 11309#define SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT__SHIFT 0x10 11310#define SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN__SHIFT 0x12 11311#define SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE__SHIFT 0x13 11312#define SPI_SHADER_PGM_RSRC2_GS__SKIP_USGPR0__SHIFT 0x1b 11313#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB__SHIFT 0x1c 11314#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN_MASK 0x00000001L 11315#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MASK 0x0000003EL 11316#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT_MASK 0x00000040L 11317#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN_MASK 0x0000FF80L 11318#define SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT_MASK 0x00030000L 11319#define SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN_MASK 0x00040000L 11320#define SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE_MASK 0x07F80000L 11321#define SPI_SHADER_PGM_RSRC2_GS__SKIP_USGPR0_MASK 0x08000000L 11322#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB_MASK 0x10000000L 11323//SPI_SHADER_USER_DATA_ES_0 11324#define SPI_SHADER_USER_DATA_ES_0__DATA__SHIFT 0x0 11325#define SPI_SHADER_USER_DATA_ES_0__DATA_MASK 0xFFFFFFFFL 11326//SPI_SHADER_USER_DATA_ES_1 11327#define SPI_SHADER_USER_DATA_ES_1__DATA__SHIFT 0x0 11328#define SPI_SHADER_USER_DATA_ES_1__DATA_MASK 0xFFFFFFFFL 11329//SPI_SHADER_USER_DATA_ES_2 11330#define SPI_SHADER_USER_DATA_ES_2__DATA__SHIFT 0x0 11331#define SPI_SHADER_USER_DATA_ES_2__DATA_MASK 0xFFFFFFFFL 11332//SPI_SHADER_USER_DATA_ES_3 11333#define SPI_SHADER_USER_DATA_ES_3__DATA__SHIFT 0x0 11334#define SPI_SHADER_USER_DATA_ES_3__DATA_MASK 0xFFFFFFFFL 11335//SPI_SHADER_USER_DATA_ES_4 11336#define SPI_SHADER_USER_DATA_ES_4__DATA__SHIFT 0x0 11337#define SPI_SHADER_USER_DATA_ES_4__DATA_MASK 0xFFFFFFFFL 11338//SPI_SHADER_USER_DATA_ES_5 11339#define SPI_SHADER_USER_DATA_ES_5__DATA__SHIFT 0x0 11340#define SPI_SHADER_USER_DATA_ES_5__DATA_MASK 0xFFFFFFFFL 11341//SPI_SHADER_USER_DATA_ES_6 11342#define SPI_SHADER_USER_DATA_ES_6__DATA__SHIFT 0x0 11343#define SPI_SHADER_USER_DATA_ES_6__DATA_MASK 0xFFFFFFFFL 11344//SPI_SHADER_USER_DATA_ES_7 11345#define SPI_SHADER_USER_DATA_ES_7__DATA__SHIFT 0x0 11346#define SPI_SHADER_USER_DATA_ES_7__DATA_MASK 0xFFFFFFFFL 11347//SPI_SHADER_USER_DATA_ES_8 11348#define SPI_SHADER_USER_DATA_ES_8__DATA__SHIFT 0x0 11349#define SPI_SHADER_USER_DATA_ES_8__DATA_MASK 0xFFFFFFFFL 11350//SPI_SHADER_USER_DATA_ES_9 11351#define SPI_SHADER_USER_DATA_ES_9__DATA__SHIFT 0x0 11352#define SPI_SHADER_USER_DATA_ES_9__DATA_MASK 0xFFFFFFFFL 11353//SPI_SHADER_USER_DATA_ES_10 11354#define SPI_SHADER_USER_DATA_ES_10__DATA__SHIFT 0x0 11355#define SPI_SHADER_USER_DATA_ES_10__DATA_MASK 0xFFFFFFFFL 11356//SPI_SHADER_USER_DATA_ES_11 11357#define SPI_SHADER_USER_DATA_ES_11__DATA__SHIFT 0x0 11358#define SPI_SHADER_USER_DATA_ES_11__DATA_MASK 0xFFFFFFFFL 11359//SPI_SHADER_USER_DATA_ES_12 11360#define SPI_SHADER_USER_DATA_ES_12__DATA__SHIFT 0x0 11361#define SPI_SHADER_USER_DATA_ES_12__DATA_MASK 0xFFFFFFFFL 11362//SPI_SHADER_USER_DATA_ES_13 11363#define SPI_SHADER_USER_DATA_ES_13__DATA__SHIFT 0x0 11364#define SPI_SHADER_USER_DATA_ES_13__DATA_MASK 0xFFFFFFFFL 11365//SPI_SHADER_USER_DATA_ES_14 11366#define SPI_SHADER_USER_DATA_ES_14__DATA__SHIFT 0x0 11367#define SPI_SHADER_USER_DATA_ES_14__DATA_MASK 0xFFFFFFFFL 11368//SPI_SHADER_USER_DATA_ES_15 11369#define SPI_SHADER_USER_DATA_ES_15__DATA__SHIFT 0x0 11370#define SPI_SHADER_USER_DATA_ES_15__DATA_MASK 0xFFFFFFFFL 11371//SPI_SHADER_USER_DATA_ES_16 11372#define SPI_SHADER_USER_DATA_ES_16__DATA__SHIFT 0x0 11373#define SPI_SHADER_USER_DATA_ES_16__DATA_MASK 0xFFFFFFFFL 11374//SPI_SHADER_USER_DATA_ES_17 11375#define SPI_SHADER_USER_DATA_ES_17__DATA__SHIFT 0x0 11376#define SPI_SHADER_USER_DATA_ES_17__DATA_MASK 0xFFFFFFFFL 11377//SPI_SHADER_USER_DATA_ES_18 11378#define SPI_SHADER_USER_DATA_ES_18__DATA__SHIFT 0x0 11379#define SPI_SHADER_USER_DATA_ES_18__DATA_MASK 0xFFFFFFFFL 11380//SPI_SHADER_USER_DATA_ES_19 11381#define SPI_SHADER_USER_DATA_ES_19__DATA__SHIFT 0x0 11382#define SPI_SHADER_USER_DATA_ES_19__DATA_MASK 0xFFFFFFFFL 11383//SPI_SHADER_USER_DATA_ES_20 11384#define SPI_SHADER_USER_DATA_ES_20__DATA__SHIFT 0x0 11385#define SPI_SHADER_USER_DATA_ES_20__DATA_MASK 0xFFFFFFFFL 11386//SPI_SHADER_USER_DATA_ES_21 11387#define SPI_SHADER_USER_DATA_ES_21__DATA__SHIFT 0x0 11388#define SPI_SHADER_USER_DATA_ES_21__DATA_MASK 0xFFFFFFFFL 11389//SPI_SHADER_USER_DATA_ES_22 11390#define SPI_SHADER_USER_DATA_ES_22__DATA__SHIFT 0x0 11391#define SPI_SHADER_USER_DATA_ES_22__DATA_MASK 0xFFFFFFFFL 11392//SPI_SHADER_USER_DATA_ES_23 11393#define SPI_SHADER_USER_DATA_ES_23__DATA__SHIFT 0x0 11394#define SPI_SHADER_USER_DATA_ES_23__DATA_MASK 0xFFFFFFFFL 11395//SPI_SHADER_USER_DATA_ES_24 11396#define SPI_SHADER_USER_DATA_ES_24__DATA__SHIFT 0x0 11397#define SPI_SHADER_USER_DATA_ES_24__DATA_MASK 0xFFFFFFFFL 11398//SPI_SHADER_USER_DATA_ES_25 11399#define SPI_SHADER_USER_DATA_ES_25__DATA__SHIFT 0x0 11400#define SPI_SHADER_USER_DATA_ES_25__DATA_MASK 0xFFFFFFFFL 11401//SPI_SHADER_USER_DATA_ES_26 11402#define SPI_SHADER_USER_DATA_ES_26__DATA__SHIFT 0x0 11403#define SPI_SHADER_USER_DATA_ES_26__DATA_MASK 0xFFFFFFFFL 11404//SPI_SHADER_USER_DATA_ES_27 11405#define SPI_SHADER_USER_DATA_ES_27__DATA__SHIFT 0x0 11406#define SPI_SHADER_USER_DATA_ES_27__DATA_MASK 0xFFFFFFFFL 11407//SPI_SHADER_USER_DATA_ES_28 11408#define SPI_SHADER_USER_DATA_ES_28__DATA__SHIFT 0x0 11409#define SPI_SHADER_USER_DATA_ES_28__DATA_MASK 0xFFFFFFFFL 11410//SPI_SHADER_USER_DATA_ES_29 11411#define SPI_SHADER_USER_DATA_ES_29__DATA__SHIFT 0x0 11412#define SPI_SHADER_USER_DATA_ES_29__DATA_MASK 0xFFFFFFFFL 11413//SPI_SHADER_USER_DATA_ES_30 11414#define SPI_SHADER_USER_DATA_ES_30__DATA__SHIFT 0x0 11415#define SPI_SHADER_USER_DATA_ES_30__DATA_MASK 0xFFFFFFFFL 11416//SPI_SHADER_USER_DATA_ES_31 11417#define SPI_SHADER_USER_DATA_ES_31__DATA__SHIFT 0x0 11418#define SPI_SHADER_USER_DATA_ES_31__DATA_MASK 0xFFFFFFFFL 11419//SPI_SHADER_PGM_RSRC4_HS 11420#define SPI_SHADER_PGM_RSRC4_HS__GROUP_FIFO_DEPTH__SHIFT 0x0 11421#define SPI_SHADER_PGM_RSRC4_HS__GROUP_FIFO_DEPTH_MASK 0x0000007FL 11422//SPI_SHADER_USER_DATA_ADDR_LO_HS 11423#define SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE__SHIFT 0x0 11424#define SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE_MASK 0xFFFFFFFFL 11425//SPI_SHADER_USER_DATA_ADDR_HI_HS 11426#define SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE__SHIFT 0x0 11427#define SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE_MASK 0xFFFFFFFFL 11428//SPI_SHADER_PGM_LO_LS 11429#define SPI_SHADER_PGM_LO_LS__MEM_BASE__SHIFT 0x0 11430#define SPI_SHADER_PGM_LO_LS__MEM_BASE_MASK 0xFFFFFFFFL 11431//SPI_SHADER_PGM_HI_LS 11432#define SPI_SHADER_PGM_HI_LS__MEM_BASE__SHIFT 0x0 11433#define SPI_SHADER_PGM_HI_LS__MEM_BASE_MASK 0xFFL 11434//SPI_SHADER_PGM_RSRC3_HS 11435#define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT__SHIFT 0x0 11436#define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD__SHIFT 0x6 11437#define SPI_SHADER_PGM_RSRC3_HS__SIMD_DISABLE__SHIFT 0xa 11438#define SPI_SHADER_PGM_RSRC3_HS__CU_EN__SHIFT 0x10 11439#define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT_MASK 0x0000003FL 11440#define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD_MASK 0x000003C0L 11441#define SPI_SHADER_PGM_RSRC3_HS__SIMD_DISABLE_MASK 0x00003C00L 11442#define SPI_SHADER_PGM_RSRC3_HS__CU_EN_MASK 0xFFFF0000L 11443//SPI_SHADER_PGM_LO_HS 11444#define SPI_SHADER_PGM_LO_HS__MEM_BASE__SHIFT 0x0 11445#define SPI_SHADER_PGM_LO_HS__MEM_BASE_MASK 0xFFFFFFFFL 11446//SPI_SHADER_PGM_HI_HS 11447#define SPI_SHADER_PGM_HI_HS__MEM_BASE__SHIFT 0x0 11448#define SPI_SHADER_PGM_HI_HS__MEM_BASE_MASK 0xFFL 11449//SPI_SHADER_PGM_RSRC1_HS 11450#define SPI_SHADER_PGM_RSRC1_HS__VGPRS__SHIFT 0x0 11451#define SPI_SHADER_PGM_RSRC1_HS__SGPRS__SHIFT 0x6 11452#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY__SHIFT 0xa 11453#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE__SHIFT 0xc 11454#define SPI_SHADER_PGM_RSRC1_HS__PRIV__SHIFT 0x14 11455#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP__SHIFT 0x15 11456#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE__SHIFT 0x17 11457#define SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT__SHIFT 0x1c 11458#define SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL__SHIFT 0x1e 11459#define SPI_SHADER_PGM_RSRC1_HS__VGPRS_MASK 0x0000003FL 11460#define SPI_SHADER_PGM_RSRC1_HS__SGPRS_MASK 0x000003C0L 11461#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY_MASK 0x00000C00L 11462#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE_MASK 0x000FF000L 11463#define SPI_SHADER_PGM_RSRC1_HS__PRIV_MASK 0x00100000L 11464#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP_MASK 0x00200000L 11465#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE_MASK 0x00800000L 11466#define SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT_MASK 0x30000000L 11467#define SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL_MASK 0x40000000L 11468//SPI_SHADER_PGM_RSRC2_HS 11469#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN__SHIFT 0x0 11470#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR__SHIFT 0x1 11471#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT__SHIFT 0x6 11472#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN__SHIFT 0x7 11473#define SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE__SHIFT 0x10 11474#define SPI_SHADER_PGM_RSRC2_HS__SKIP_USGPR0__SHIFT 0x1b 11475#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB__SHIFT 0x1c 11476#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN_MASK 0x00000001L 11477#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MASK 0x0000003EL 11478#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT_MASK 0x00000040L 11479#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN_MASK 0x0000FF80L 11480#define SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE_MASK 0x01FF0000L 11481#define SPI_SHADER_PGM_RSRC2_HS__SKIP_USGPR0_MASK 0x08000000L 11482#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB_MASK 0x10000000L 11483//SPI_SHADER_USER_DATA_LS_0 11484#define SPI_SHADER_USER_DATA_LS_0__DATA__SHIFT 0x0 11485#define SPI_SHADER_USER_DATA_LS_0__DATA_MASK 0xFFFFFFFFL 11486//SPI_SHADER_USER_DATA_LS_1 11487#define SPI_SHADER_USER_DATA_LS_1__DATA__SHIFT 0x0 11488#define SPI_SHADER_USER_DATA_LS_1__DATA_MASK 0xFFFFFFFFL 11489//SPI_SHADER_USER_DATA_LS_2 11490#define SPI_SHADER_USER_DATA_LS_2__DATA__SHIFT 0x0 11491#define SPI_SHADER_USER_DATA_LS_2__DATA_MASK 0xFFFFFFFFL 11492//SPI_SHADER_USER_DATA_LS_3 11493#define SPI_SHADER_USER_DATA_LS_3__DATA__SHIFT 0x0 11494#define SPI_SHADER_USER_DATA_LS_3__DATA_MASK 0xFFFFFFFFL 11495//SPI_SHADER_USER_DATA_LS_4 11496#define SPI_SHADER_USER_DATA_LS_4__DATA__SHIFT 0x0 11497#define SPI_SHADER_USER_DATA_LS_4__DATA_MASK 0xFFFFFFFFL 11498//SPI_SHADER_USER_DATA_LS_5 11499#define SPI_SHADER_USER_DATA_LS_5__DATA__SHIFT 0x0 11500#define SPI_SHADER_USER_DATA_LS_5__DATA_MASK 0xFFFFFFFFL 11501//SPI_SHADER_USER_DATA_LS_6 11502#define SPI_SHADER_USER_DATA_LS_6__DATA__SHIFT 0x0 11503#define SPI_SHADER_USER_DATA_LS_6__DATA_MASK 0xFFFFFFFFL 11504//SPI_SHADER_USER_DATA_LS_7 11505#define SPI_SHADER_USER_DATA_LS_7__DATA__SHIFT 0x0 11506#define SPI_SHADER_USER_DATA_LS_7__DATA_MASK 0xFFFFFFFFL 11507//SPI_SHADER_USER_DATA_LS_8 11508#define SPI_SHADER_USER_DATA_LS_8__DATA__SHIFT 0x0 11509#define SPI_SHADER_USER_DATA_LS_8__DATA_MASK 0xFFFFFFFFL 11510//SPI_SHADER_USER_DATA_LS_9 11511#define SPI_SHADER_USER_DATA_LS_9__DATA__SHIFT 0x0 11512#define SPI_SHADER_USER_DATA_LS_9__DATA_MASK 0xFFFFFFFFL 11513//SPI_SHADER_USER_DATA_LS_10 11514#define SPI_SHADER_USER_DATA_LS_10__DATA__SHIFT 0x0 11515#define SPI_SHADER_USER_DATA_LS_10__DATA_MASK 0xFFFFFFFFL 11516//SPI_SHADER_USER_DATA_LS_11 11517#define SPI_SHADER_USER_DATA_LS_11__DATA__SHIFT 0x0 11518#define SPI_SHADER_USER_DATA_LS_11__DATA_MASK 0xFFFFFFFFL 11519//SPI_SHADER_USER_DATA_LS_12 11520#define SPI_SHADER_USER_DATA_LS_12__DATA__SHIFT 0x0 11521#define SPI_SHADER_USER_DATA_LS_12__DATA_MASK 0xFFFFFFFFL 11522//SPI_SHADER_USER_DATA_LS_13 11523#define SPI_SHADER_USER_DATA_LS_13__DATA__SHIFT 0x0 11524#define SPI_SHADER_USER_DATA_LS_13__DATA_MASK 0xFFFFFFFFL 11525//SPI_SHADER_USER_DATA_LS_14 11526#define SPI_SHADER_USER_DATA_LS_14__DATA__SHIFT 0x0 11527#define SPI_SHADER_USER_DATA_LS_14__DATA_MASK 0xFFFFFFFFL 11528//SPI_SHADER_USER_DATA_LS_15 11529#define SPI_SHADER_USER_DATA_LS_15__DATA__SHIFT 0x0 11530#define SPI_SHADER_USER_DATA_LS_15__DATA_MASK 0xFFFFFFFFL 11531//SPI_SHADER_USER_DATA_LS_16 11532#define SPI_SHADER_USER_DATA_LS_16__DATA__SHIFT 0x0 11533#define SPI_SHADER_USER_DATA_LS_16__DATA_MASK 0xFFFFFFFFL 11534//SPI_SHADER_USER_DATA_LS_17 11535#define SPI_SHADER_USER_DATA_LS_17__DATA__SHIFT 0x0 11536#define SPI_SHADER_USER_DATA_LS_17__DATA_MASK 0xFFFFFFFFL 11537//SPI_SHADER_USER_DATA_LS_18 11538#define SPI_SHADER_USER_DATA_LS_18__DATA__SHIFT 0x0 11539#define SPI_SHADER_USER_DATA_LS_18__DATA_MASK 0xFFFFFFFFL 11540//SPI_SHADER_USER_DATA_LS_19 11541#define SPI_SHADER_USER_DATA_LS_19__DATA__SHIFT 0x0 11542#define SPI_SHADER_USER_DATA_LS_19__DATA_MASK 0xFFFFFFFFL 11543//SPI_SHADER_USER_DATA_LS_20 11544#define SPI_SHADER_USER_DATA_LS_20__DATA__SHIFT 0x0 11545#define SPI_SHADER_USER_DATA_LS_20__DATA_MASK 0xFFFFFFFFL 11546//SPI_SHADER_USER_DATA_LS_21 11547#define SPI_SHADER_USER_DATA_LS_21__DATA__SHIFT 0x0 11548#define SPI_SHADER_USER_DATA_LS_21__DATA_MASK 0xFFFFFFFFL 11549//SPI_SHADER_USER_DATA_LS_22 11550#define SPI_SHADER_USER_DATA_LS_22__DATA__SHIFT 0x0 11551#define SPI_SHADER_USER_DATA_LS_22__DATA_MASK 0xFFFFFFFFL 11552//SPI_SHADER_USER_DATA_LS_23 11553#define SPI_SHADER_USER_DATA_LS_23__DATA__SHIFT 0x0 11554#define SPI_SHADER_USER_DATA_LS_23__DATA_MASK 0xFFFFFFFFL 11555//SPI_SHADER_USER_DATA_LS_24 11556#define SPI_SHADER_USER_DATA_LS_24__DATA__SHIFT 0x0 11557#define SPI_SHADER_USER_DATA_LS_24__DATA_MASK 0xFFFFFFFFL 11558//SPI_SHADER_USER_DATA_LS_25 11559#define SPI_SHADER_USER_DATA_LS_25__DATA__SHIFT 0x0 11560#define SPI_SHADER_USER_DATA_LS_25__DATA_MASK 0xFFFFFFFFL 11561//SPI_SHADER_USER_DATA_LS_26 11562#define SPI_SHADER_USER_DATA_LS_26__DATA__SHIFT 0x0 11563#define SPI_SHADER_USER_DATA_LS_26__DATA_MASK 0xFFFFFFFFL 11564//SPI_SHADER_USER_DATA_LS_27 11565#define SPI_SHADER_USER_DATA_LS_27__DATA__SHIFT 0x0 11566#define SPI_SHADER_USER_DATA_LS_27__DATA_MASK 0xFFFFFFFFL 11567//SPI_SHADER_USER_DATA_LS_28 11568#define SPI_SHADER_USER_DATA_LS_28__DATA__SHIFT 0x0 11569#define SPI_SHADER_USER_DATA_LS_28__DATA_MASK 0xFFFFFFFFL 11570//SPI_SHADER_USER_DATA_LS_29 11571#define SPI_SHADER_USER_DATA_LS_29__DATA__SHIFT 0x0 11572#define SPI_SHADER_USER_DATA_LS_29__DATA_MASK 0xFFFFFFFFL 11573//SPI_SHADER_USER_DATA_LS_30 11574#define SPI_SHADER_USER_DATA_LS_30__DATA__SHIFT 0x0 11575#define SPI_SHADER_USER_DATA_LS_30__DATA_MASK 0xFFFFFFFFL 11576//SPI_SHADER_USER_DATA_LS_31 11577#define SPI_SHADER_USER_DATA_LS_31__DATA__SHIFT 0x0 11578#define SPI_SHADER_USER_DATA_LS_31__DATA_MASK 0xFFFFFFFFL 11579//SPI_SHADER_USER_DATA_COMMON_0 11580#define SPI_SHADER_USER_DATA_COMMON_0__DATA__SHIFT 0x0 11581#define SPI_SHADER_USER_DATA_COMMON_0__DATA_MASK 0xFFFFFFFFL 11582//SPI_SHADER_USER_DATA_COMMON_1 11583#define SPI_SHADER_USER_DATA_COMMON_1__DATA__SHIFT 0x0 11584#define SPI_SHADER_USER_DATA_COMMON_1__DATA_MASK 0xFFFFFFFFL 11585//SPI_SHADER_USER_DATA_COMMON_2 11586#define SPI_SHADER_USER_DATA_COMMON_2__DATA__SHIFT 0x0 11587#define SPI_SHADER_USER_DATA_COMMON_2__DATA_MASK 0xFFFFFFFFL 11588//SPI_SHADER_USER_DATA_COMMON_3 11589#define SPI_SHADER_USER_DATA_COMMON_3__DATA__SHIFT 0x0 11590#define SPI_SHADER_USER_DATA_COMMON_3__DATA_MASK 0xFFFFFFFFL 11591//SPI_SHADER_USER_DATA_COMMON_4 11592#define SPI_SHADER_USER_DATA_COMMON_4__DATA__SHIFT 0x0 11593#define SPI_SHADER_USER_DATA_COMMON_4__DATA_MASK 0xFFFFFFFFL 11594//SPI_SHADER_USER_DATA_COMMON_5 11595#define SPI_SHADER_USER_DATA_COMMON_5__DATA__SHIFT 0x0 11596#define SPI_SHADER_USER_DATA_COMMON_5__DATA_MASK 0xFFFFFFFFL 11597//SPI_SHADER_USER_DATA_COMMON_6 11598#define SPI_SHADER_USER_DATA_COMMON_6__DATA__SHIFT 0x0 11599#define SPI_SHADER_USER_DATA_COMMON_6__DATA_MASK 0xFFFFFFFFL 11600//SPI_SHADER_USER_DATA_COMMON_7 11601#define SPI_SHADER_USER_DATA_COMMON_7__DATA__SHIFT 0x0 11602#define SPI_SHADER_USER_DATA_COMMON_7__DATA_MASK 0xFFFFFFFFL 11603//SPI_SHADER_USER_DATA_COMMON_8 11604#define SPI_SHADER_USER_DATA_COMMON_8__DATA__SHIFT 0x0 11605#define SPI_SHADER_USER_DATA_COMMON_8__DATA_MASK 0xFFFFFFFFL 11606//SPI_SHADER_USER_DATA_COMMON_9 11607#define SPI_SHADER_USER_DATA_COMMON_9__DATA__SHIFT 0x0 11608#define SPI_SHADER_USER_DATA_COMMON_9__DATA_MASK 0xFFFFFFFFL 11609//SPI_SHADER_USER_DATA_COMMON_10 11610#define SPI_SHADER_USER_DATA_COMMON_10__DATA__SHIFT 0x0 11611#define SPI_SHADER_USER_DATA_COMMON_10__DATA_MASK 0xFFFFFFFFL 11612//SPI_SHADER_USER_DATA_COMMON_11 11613#define SPI_SHADER_USER_DATA_COMMON_11__DATA__SHIFT 0x0 11614#define SPI_SHADER_USER_DATA_COMMON_11__DATA_MASK 0xFFFFFFFFL 11615//SPI_SHADER_USER_DATA_COMMON_12 11616#define SPI_SHADER_USER_DATA_COMMON_12__DATA__SHIFT 0x0 11617#define SPI_SHADER_USER_DATA_COMMON_12__DATA_MASK 0xFFFFFFFFL 11618//SPI_SHADER_USER_DATA_COMMON_13 11619#define SPI_SHADER_USER_DATA_COMMON_13__DATA__SHIFT 0x0 11620#define SPI_SHADER_USER_DATA_COMMON_13__DATA_MASK 0xFFFFFFFFL 11621//SPI_SHADER_USER_DATA_COMMON_14 11622#define SPI_SHADER_USER_DATA_COMMON_14__DATA__SHIFT 0x0 11623#define SPI_SHADER_USER_DATA_COMMON_14__DATA_MASK 0xFFFFFFFFL 11624//SPI_SHADER_USER_DATA_COMMON_15 11625#define SPI_SHADER_USER_DATA_COMMON_15__DATA__SHIFT 0x0 11626#define SPI_SHADER_USER_DATA_COMMON_15__DATA_MASK 0xFFFFFFFFL 11627//SPI_SHADER_USER_DATA_COMMON_16 11628#define SPI_SHADER_USER_DATA_COMMON_16__DATA__SHIFT 0x0 11629#define SPI_SHADER_USER_DATA_COMMON_16__DATA_MASK 0xFFFFFFFFL 11630//SPI_SHADER_USER_DATA_COMMON_17 11631#define SPI_SHADER_USER_DATA_COMMON_17__DATA__SHIFT 0x0 11632#define SPI_SHADER_USER_DATA_COMMON_17__DATA_MASK 0xFFFFFFFFL 11633//SPI_SHADER_USER_DATA_COMMON_18 11634#define SPI_SHADER_USER_DATA_COMMON_18__DATA__SHIFT 0x0 11635#define SPI_SHADER_USER_DATA_COMMON_18__DATA_MASK 0xFFFFFFFFL 11636//SPI_SHADER_USER_DATA_COMMON_19 11637#define SPI_SHADER_USER_DATA_COMMON_19__DATA__SHIFT 0x0 11638#define SPI_SHADER_USER_DATA_COMMON_19__DATA_MASK 0xFFFFFFFFL 11639//SPI_SHADER_USER_DATA_COMMON_20 11640#define SPI_SHADER_USER_DATA_COMMON_20__DATA__SHIFT 0x0 11641#define SPI_SHADER_USER_DATA_COMMON_20__DATA_MASK 0xFFFFFFFFL 11642//SPI_SHADER_USER_DATA_COMMON_21 11643#define SPI_SHADER_USER_DATA_COMMON_21__DATA__SHIFT 0x0 11644#define SPI_SHADER_USER_DATA_COMMON_21__DATA_MASK 0xFFFFFFFFL 11645//SPI_SHADER_USER_DATA_COMMON_22 11646#define SPI_SHADER_USER_DATA_COMMON_22__DATA__SHIFT 0x0 11647#define SPI_SHADER_USER_DATA_COMMON_22__DATA_MASK 0xFFFFFFFFL 11648//SPI_SHADER_USER_DATA_COMMON_23 11649#define SPI_SHADER_USER_DATA_COMMON_23__DATA__SHIFT 0x0 11650#define SPI_SHADER_USER_DATA_COMMON_23__DATA_MASK 0xFFFFFFFFL 11651//SPI_SHADER_USER_DATA_COMMON_24 11652#define SPI_SHADER_USER_DATA_COMMON_24__DATA__SHIFT 0x0 11653#define SPI_SHADER_USER_DATA_COMMON_24__DATA_MASK 0xFFFFFFFFL 11654//SPI_SHADER_USER_DATA_COMMON_25 11655#define SPI_SHADER_USER_DATA_COMMON_25__DATA__SHIFT 0x0 11656#define SPI_SHADER_USER_DATA_COMMON_25__DATA_MASK 0xFFFFFFFFL 11657//SPI_SHADER_USER_DATA_COMMON_26 11658#define SPI_SHADER_USER_DATA_COMMON_26__DATA__SHIFT 0x0 11659#define SPI_SHADER_USER_DATA_COMMON_26__DATA_MASK 0xFFFFFFFFL 11660//SPI_SHADER_USER_DATA_COMMON_27 11661#define SPI_SHADER_USER_DATA_COMMON_27__DATA__SHIFT 0x0 11662#define SPI_SHADER_USER_DATA_COMMON_27__DATA_MASK 0xFFFFFFFFL 11663//SPI_SHADER_USER_DATA_COMMON_28 11664#define SPI_SHADER_USER_DATA_COMMON_28__DATA__SHIFT 0x0 11665#define SPI_SHADER_USER_DATA_COMMON_28__DATA_MASK 0xFFFFFFFFL 11666//SPI_SHADER_USER_DATA_COMMON_29 11667#define SPI_SHADER_USER_DATA_COMMON_29__DATA__SHIFT 0x0 11668#define SPI_SHADER_USER_DATA_COMMON_29__DATA_MASK 0xFFFFFFFFL 11669//SPI_SHADER_USER_DATA_COMMON_30 11670#define SPI_SHADER_USER_DATA_COMMON_30__DATA__SHIFT 0x0 11671#define SPI_SHADER_USER_DATA_COMMON_30__DATA_MASK 0xFFFFFFFFL 11672//SPI_SHADER_USER_DATA_COMMON_31 11673#define SPI_SHADER_USER_DATA_COMMON_31__DATA__SHIFT 0x0 11674#define SPI_SHADER_USER_DATA_COMMON_31__DATA_MASK 0xFFFFFFFFL 11675//COMPUTE_DISPATCH_INITIATOR 11676#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN__SHIFT 0x0 11677#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN__SHIFT 0x1 11678#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000__SHIFT 0x2 11679#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL__SHIFT 0x3 11680#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE__SHIFT 0x4 11681#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS__SHIFT 0x5 11682#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE__SHIFT 0x6 11683#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL__SHIFT 0xa 11684#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL__SHIFT 0xb 11685#define COMPUTE_DISPATCH_INITIATOR__RESERVED__SHIFT 0xc 11686#define COMPUTE_DISPATCH_INITIATOR__RESTORE__SHIFT 0xe 11687#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN_MASK 0x00000001L 11688#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN_MASK 0x00000002L 11689#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000_MASK 0x00000004L 11690#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL_MASK 0x00000008L 11691#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE_MASK 0x00000010L 11692#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS_MASK 0x00000020L 11693#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE_MASK 0x00000040L 11694#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL_MASK 0x00000400L 11695#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL_MASK 0x00000800L 11696#define COMPUTE_DISPATCH_INITIATOR__RESERVED_MASK 0x00001000L 11697#define COMPUTE_DISPATCH_INITIATOR__RESTORE_MASK 0x00004000L 11698//COMPUTE_DIM_X 11699#define COMPUTE_DIM_X__SIZE__SHIFT 0x0 11700#define COMPUTE_DIM_X__SIZE_MASK 0xFFFFFFFFL 11701//COMPUTE_DIM_Y 11702#define COMPUTE_DIM_Y__SIZE__SHIFT 0x0 11703#define COMPUTE_DIM_Y__SIZE_MASK 0xFFFFFFFFL 11704//COMPUTE_DIM_Z 11705#define COMPUTE_DIM_Z__SIZE__SHIFT 0x0 11706#define COMPUTE_DIM_Z__SIZE_MASK 0xFFFFFFFFL 11707//COMPUTE_START_X 11708#define COMPUTE_START_X__START__SHIFT 0x0 11709#define COMPUTE_START_X__START_MASK 0xFFFFFFFFL 11710//COMPUTE_START_Y 11711#define COMPUTE_START_Y__START__SHIFT 0x0 11712#define COMPUTE_START_Y__START_MASK 0xFFFFFFFFL 11713//COMPUTE_START_Z 11714#define COMPUTE_START_Z__START__SHIFT 0x0 11715#define COMPUTE_START_Z__START_MASK 0xFFFFFFFFL 11716//COMPUTE_NUM_THREAD_X 11717#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL__SHIFT 0x0 11718#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL__SHIFT 0x10 11719#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL_MASK 0x0000FFFFL 11720#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L 11721//COMPUTE_NUM_THREAD_Y 11722#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL__SHIFT 0x0 11723#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL__SHIFT 0x10 11724#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL_MASK 0x0000FFFFL 11725#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L 11726//COMPUTE_NUM_THREAD_Z 11727#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL__SHIFT 0x0 11728#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL__SHIFT 0x10 11729#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL_MASK 0x0000FFFFL 11730#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L 11731//COMPUTE_PIPELINESTAT_ENABLE 11732#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE__SHIFT 0x0 11733#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE_MASK 0x00000001L 11734//COMPUTE_PERFCOUNT_ENABLE 11735#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE__SHIFT 0x0 11736#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE_MASK 0x00000001L 11737//COMPUTE_PGM_LO 11738#define COMPUTE_PGM_LO__DATA__SHIFT 0x0 11739#define COMPUTE_PGM_LO__DATA_MASK 0xFFFFFFFFL 11740//COMPUTE_PGM_HI 11741#define COMPUTE_PGM_HI__DATA__SHIFT 0x0 11742#define COMPUTE_PGM_HI__DATA_MASK 0x000000FFL 11743//COMPUTE_DISPATCH_PKT_ADDR_LO 11744#define COMPUTE_DISPATCH_PKT_ADDR_LO__DATA__SHIFT 0x0 11745#define COMPUTE_DISPATCH_PKT_ADDR_LO__DATA_MASK 0xFFFFFFFFL 11746//COMPUTE_DISPATCH_PKT_ADDR_HI 11747#define COMPUTE_DISPATCH_PKT_ADDR_HI__DATA__SHIFT 0x0 11748#define COMPUTE_DISPATCH_PKT_ADDR_HI__DATA_MASK 0x000000FFL 11749//COMPUTE_DISPATCH_SCRATCH_BASE_LO 11750#define COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA__SHIFT 0x0 11751#define COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA_MASK 0xFFFFFFFFL 11752//COMPUTE_DISPATCH_SCRATCH_BASE_HI 11753#define COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA__SHIFT 0x0 11754#define COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA_MASK 0x000000FFL 11755//COMPUTE_PGM_RSRC1 11756#define COMPUTE_PGM_RSRC1__VGPRS__SHIFT 0x0 11757#define COMPUTE_PGM_RSRC1__SGPRS__SHIFT 0x6 11758#define COMPUTE_PGM_RSRC1__PRIORITY__SHIFT 0xa 11759#define COMPUTE_PGM_RSRC1__FLOAT_MODE__SHIFT 0xc 11760#define COMPUTE_PGM_RSRC1__PRIV__SHIFT 0x14 11761#define COMPUTE_PGM_RSRC1__DX10_CLAMP__SHIFT 0x15 11762#define COMPUTE_PGM_RSRC1__IEEE_MODE__SHIFT 0x17 11763#define COMPUTE_PGM_RSRC1__BULKY__SHIFT 0x18 11764#define COMPUTE_PGM_RSRC1__FP16_OVFL__SHIFT 0x1a 11765#define COMPUTE_PGM_RSRC1__VGPRS_MASK 0x0000003FL 11766#define COMPUTE_PGM_RSRC1__SGPRS_MASK 0x000003C0L 11767#define COMPUTE_PGM_RSRC1__PRIORITY_MASK 0x00000C00L 11768#define COMPUTE_PGM_RSRC1__FLOAT_MODE_MASK 0x000FF000L 11769#define COMPUTE_PGM_RSRC1__PRIV_MASK 0x00100000L 11770#define COMPUTE_PGM_RSRC1__DX10_CLAMP_MASK 0x00200000L 11771#define COMPUTE_PGM_RSRC1__IEEE_MODE_MASK 0x00800000L 11772#define COMPUTE_PGM_RSRC1__BULKY_MASK 0x01000000L 11773#define COMPUTE_PGM_RSRC1__FP16_OVFL_MASK 0x04000000L 11774//COMPUTE_PGM_RSRC2 11775#define COMPUTE_PGM_RSRC2__SCRATCH_EN__SHIFT 0x0 11776#define COMPUTE_PGM_RSRC2__USER_SGPR__SHIFT 0x1 11777#define COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT 0x6 11778#define COMPUTE_PGM_RSRC2__TGID_X_EN__SHIFT 0x7 11779#define COMPUTE_PGM_RSRC2__TGID_Y_EN__SHIFT 0x8 11780#define COMPUTE_PGM_RSRC2__TGID_Z_EN__SHIFT 0x9 11781#define COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT 0xa 11782#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT__SHIFT 0xb 11783#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB__SHIFT 0xd 11784#define COMPUTE_PGM_RSRC2__LDS_SIZE__SHIFT 0xf 11785#define COMPUTE_PGM_RSRC2__EXCP_EN__SHIFT 0x18 11786#define COMPUTE_PGM_RSRC2__SKIP_USGPR0__SHIFT 0x1f 11787#define COMPUTE_PGM_RSRC2__SCRATCH_EN_MASK 0x00000001L 11788#define COMPUTE_PGM_RSRC2__USER_SGPR_MASK 0x0000003EL 11789#define COMPUTE_PGM_RSRC2__TRAP_PRESENT_MASK 0x00000040L 11790#define COMPUTE_PGM_RSRC2__TGID_X_EN_MASK 0x00000080L 11791#define COMPUTE_PGM_RSRC2__TGID_Y_EN_MASK 0x00000100L 11792#define COMPUTE_PGM_RSRC2__TGID_Z_EN_MASK 0x00000200L 11793#define COMPUTE_PGM_RSRC2__TG_SIZE_EN_MASK 0x00000400L 11794#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT_MASK 0x00001800L 11795#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB_MASK 0x00006000L 11796#define COMPUTE_PGM_RSRC2__LDS_SIZE_MASK 0x00FF8000L 11797#define COMPUTE_PGM_RSRC2__EXCP_EN_MASK 0x7F000000L 11798#define COMPUTE_PGM_RSRC2__SKIP_USGPR0_MASK 0x80000000L 11799//COMPUTE_VMID 11800#define COMPUTE_VMID__DATA__SHIFT 0x0 11801#define COMPUTE_VMID__DATA_MASK 0x0000000FL 11802//COMPUTE_RESOURCE_LIMITS 11803#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH__SHIFT 0x0 11804#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU__SHIFT 0xc 11805#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD__SHIFT 0x10 11806#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL__SHIFT 0x16 11807#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST__SHIFT 0x17 11808#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT__SHIFT 0x18 11809#define COMPUTE_RESOURCE_LIMITS__SIMD_DISABLE__SHIFT 0x1b 11810#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH_MASK 0x000003FFL 11811#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU_MASK 0x0000F000L 11812#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD_MASK 0x003F0000L 11813#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL_MASK 0x00400000L 11814#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK 0x00800000L 11815#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT_MASK 0x07000000L 11816#define COMPUTE_RESOURCE_LIMITS__SIMD_DISABLE_MASK 0x78000000L 11817//COMPUTE_STATIC_THREAD_MGMT_SE0 11818#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN__SHIFT 0x0 11819#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN__SHIFT 0x10 11820#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN_MASK 0x0000FFFFL 11821#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN_MASK 0xFFFF0000L 11822//COMPUTE_STATIC_THREAD_MGMT_SE1 11823#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN__SHIFT 0x0 11824#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN__SHIFT 0x10 11825#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN_MASK 0x0000FFFFL 11826#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN_MASK 0xFFFF0000L 11827//COMPUTE_TMPRING_SIZE 11828#define COMPUTE_TMPRING_SIZE__WAVES__SHIFT 0x0 11829#define COMPUTE_TMPRING_SIZE__WAVESIZE__SHIFT 0xc 11830#define COMPUTE_TMPRING_SIZE__WAVES_MASK 0x00000FFFL 11831#define COMPUTE_TMPRING_SIZE__WAVESIZE_MASK 0x01FFF000L 11832//COMPUTE_STATIC_THREAD_MGMT_SE2 11833#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN__SHIFT 0x0 11834#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN__SHIFT 0x10 11835#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN_MASK 0x0000FFFFL 11836#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN_MASK 0xFFFF0000L 11837//COMPUTE_STATIC_THREAD_MGMT_SE3 11838#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN__SHIFT 0x0 11839#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN__SHIFT 0x10 11840#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN_MASK 0x0000FFFFL 11841#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN_MASK 0xFFFF0000L 11842//COMPUTE_RESTART_X 11843#define COMPUTE_RESTART_X__RESTART__SHIFT 0x0 11844#define COMPUTE_RESTART_X__RESTART_MASK 0xFFFFFFFFL 11845//COMPUTE_RESTART_Y 11846#define COMPUTE_RESTART_Y__RESTART__SHIFT 0x0 11847#define COMPUTE_RESTART_Y__RESTART_MASK 0xFFFFFFFFL 11848//COMPUTE_RESTART_Z 11849#define COMPUTE_RESTART_Z__RESTART__SHIFT 0x0 11850#define COMPUTE_RESTART_Z__RESTART_MASK 0xFFFFFFFFL 11851//COMPUTE_THREAD_TRACE_ENABLE 11852#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE__SHIFT 0x0 11853#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE_MASK 0x00000001L 11854//COMPUTE_MISC_RESERVED 11855#define COMPUTE_MISC_RESERVED__SEND_SEID__SHIFT 0x0 11856#define COMPUTE_MISC_RESERVED__RESERVED2__SHIFT 0x2 11857#define COMPUTE_MISC_RESERVED__RESERVED3__SHIFT 0x3 11858#define COMPUTE_MISC_RESERVED__RESERVED4__SHIFT 0x4 11859#define COMPUTE_MISC_RESERVED__WAVE_ID_BASE__SHIFT 0x5 11860#define COMPUTE_MISC_RESERVED__SEND_SEID_MASK 0x00000003L 11861#define COMPUTE_MISC_RESERVED__RESERVED2_MASK 0x00000004L 11862#define COMPUTE_MISC_RESERVED__RESERVED3_MASK 0x00000008L 11863#define COMPUTE_MISC_RESERVED__RESERVED4_MASK 0x00000010L 11864#define COMPUTE_MISC_RESERVED__WAVE_ID_BASE_MASK 0x0001FFE0L 11865//COMPUTE_DISPATCH_ID 11866#define COMPUTE_DISPATCH_ID__DISPATCH_ID__SHIFT 0x0 11867#define COMPUTE_DISPATCH_ID__DISPATCH_ID_MASK 0xFFFFFFFFL 11868//COMPUTE_THREADGROUP_ID 11869#define COMPUTE_THREADGROUP_ID__THREADGROUP_ID__SHIFT 0x0 11870#define COMPUTE_THREADGROUP_ID__THREADGROUP_ID_MASK 0xFFFFFFFFL 11871//COMPUTE_RELAUNCH 11872#define COMPUTE_RELAUNCH__PAYLOAD__SHIFT 0x0 11873#define COMPUTE_RELAUNCH__IS_EVENT__SHIFT 0x1e 11874#define COMPUTE_RELAUNCH__IS_STATE__SHIFT 0x1f 11875#define COMPUTE_RELAUNCH__PAYLOAD_MASK 0x3FFFFFFFL 11876#define COMPUTE_RELAUNCH__IS_EVENT_MASK 0x40000000L 11877#define COMPUTE_RELAUNCH__IS_STATE_MASK 0x80000000L 11878//COMPUTE_WAVE_RESTORE_ADDR_LO 11879#define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR__SHIFT 0x0 11880#define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR_MASK 0xFFFFFFFFL 11881//COMPUTE_WAVE_RESTORE_ADDR_HI 11882#define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR__SHIFT 0x0 11883#define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR_MASK 0xFFFFL 11884//COMPUTE_USER_DATA_0 11885#define COMPUTE_USER_DATA_0__DATA__SHIFT 0x0 11886#define COMPUTE_USER_DATA_0__DATA_MASK 0xFFFFFFFFL 11887//COMPUTE_USER_DATA_1 11888#define COMPUTE_USER_DATA_1__DATA__SHIFT 0x0 11889#define COMPUTE_USER_DATA_1__DATA_MASK 0xFFFFFFFFL 11890//COMPUTE_USER_DATA_2 11891#define COMPUTE_USER_DATA_2__DATA__SHIFT 0x0 11892#define COMPUTE_USER_DATA_2__DATA_MASK 0xFFFFFFFFL 11893//COMPUTE_USER_DATA_3 11894#define COMPUTE_USER_DATA_3__DATA__SHIFT 0x0 11895#define COMPUTE_USER_DATA_3__DATA_MASK 0xFFFFFFFFL 11896//COMPUTE_USER_DATA_4 11897#define COMPUTE_USER_DATA_4__DATA__SHIFT 0x0 11898#define COMPUTE_USER_DATA_4__DATA_MASK 0xFFFFFFFFL 11899//COMPUTE_USER_DATA_5 11900#define COMPUTE_USER_DATA_5__DATA__SHIFT 0x0 11901#define COMPUTE_USER_DATA_5__DATA_MASK 0xFFFFFFFFL 11902//COMPUTE_USER_DATA_6 11903#define COMPUTE_USER_DATA_6__DATA__SHIFT 0x0 11904#define COMPUTE_USER_DATA_6__DATA_MASK 0xFFFFFFFFL 11905//COMPUTE_USER_DATA_7 11906#define COMPUTE_USER_DATA_7__DATA__SHIFT 0x0 11907#define COMPUTE_USER_DATA_7__DATA_MASK 0xFFFFFFFFL 11908//COMPUTE_USER_DATA_8 11909#define COMPUTE_USER_DATA_8__DATA__SHIFT 0x0 11910#define COMPUTE_USER_DATA_8__DATA_MASK 0xFFFFFFFFL 11911//COMPUTE_USER_DATA_9 11912#define COMPUTE_USER_DATA_9__DATA__SHIFT 0x0 11913#define COMPUTE_USER_DATA_9__DATA_MASK 0xFFFFFFFFL 11914//COMPUTE_USER_DATA_10 11915#define COMPUTE_USER_DATA_10__DATA__SHIFT 0x0 11916#define COMPUTE_USER_DATA_10__DATA_MASK 0xFFFFFFFFL 11917//COMPUTE_USER_DATA_11 11918#define COMPUTE_USER_DATA_11__DATA__SHIFT 0x0 11919#define COMPUTE_USER_DATA_11__DATA_MASK 0xFFFFFFFFL 11920//COMPUTE_USER_DATA_12 11921#define COMPUTE_USER_DATA_12__DATA__SHIFT 0x0 11922#define COMPUTE_USER_DATA_12__DATA_MASK 0xFFFFFFFFL 11923//COMPUTE_USER_DATA_13 11924#define COMPUTE_USER_DATA_13__DATA__SHIFT 0x0 11925#define COMPUTE_USER_DATA_13__DATA_MASK 0xFFFFFFFFL 11926//COMPUTE_USER_DATA_14 11927#define COMPUTE_USER_DATA_14__DATA__SHIFT 0x0 11928#define COMPUTE_USER_DATA_14__DATA_MASK 0xFFFFFFFFL 11929//COMPUTE_USER_DATA_15 11930#define COMPUTE_USER_DATA_15__DATA__SHIFT 0x0 11931#define COMPUTE_USER_DATA_15__DATA_MASK 0xFFFFFFFFL 11932//COMPUTE_NOWHERE 11933#define COMPUTE_NOWHERE__DATA__SHIFT 0x0 11934#define COMPUTE_NOWHERE__DATA_MASK 0xFFFFFFFFL 11935 11936 11937// addressBlock: gc_cppdec 11938//CP_DFY_CNTL 11939#define CP_DFY_CNTL__POLICY__SHIFT 0x0 11940#define CP_DFY_CNTL__MTYPE__SHIFT 0x2 11941#define CP_DFY_CNTL__TPI_SDP_SEL__SHIFT 0x1a 11942#define CP_DFY_CNTL__LFSR_RESET__SHIFT 0x1c 11943#define CP_DFY_CNTL__MODE__SHIFT 0x1d 11944#define CP_DFY_CNTL__ENABLE__SHIFT 0x1f 11945#define CP_DFY_CNTL__POLICY_MASK 0x00000001L 11946#define CP_DFY_CNTL__MTYPE_MASK 0x0000000CL 11947#define CP_DFY_CNTL__TPI_SDP_SEL_MASK 0x04000000L 11948#define CP_DFY_CNTL__LFSR_RESET_MASK 0x10000000L 11949#define CP_DFY_CNTL__MODE_MASK 0x60000000L 11950#define CP_DFY_CNTL__ENABLE_MASK 0x80000000L 11951//CP_DFY_STAT 11952#define CP_DFY_STAT__BURST_COUNT__SHIFT 0x0 11953#define CP_DFY_STAT__TAGS_PENDING__SHIFT 0x10 11954#define CP_DFY_STAT__BUSY__SHIFT 0x1f 11955#define CP_DFY_STAT__BURST_COUNT_MASK 0x0000FFFFL 11956#define CP_DFY_STAT__TAGS_PENDING_MASK 0x07FF0000L 11957#define CP_DFY_STAT__BUSY_MASK 0x80000000L 11958//CP_DFY_ADDR_HI 11959#define CP_DFY_ADDR_HI__ADDR_HI__SHIFT 0x0 11960#define CP_DFY_ADDR_HI__ADDR_HI_MASK 0xFFFFFFFFL 11961//CP_DFY_ADDR_LO 11962#define CP_DFY_ADDR_LO__ADDR_LO__SHIFT 0x5 11963#define CP_DFY_ADDR_LO__ADDR_LO_MASK 0xFFFFFFE0L 11964//CP_DFY_DATA_0 11965#define CP_DFY_DATA_0__DATA__SHIFT 0x0 11966#define CP_DFY_DATA_0__DATA_MASK 0xFFFFFFFFL 11967//CP_DFY_DATA_1 11968#define CP_DFY_DATA_1__DATA__SHIFT 0x0 11969#define CP_DFY_DATA_1__DATA_MASK 0xFFFFFFFFL 11970//CP_DFY_DATA_2 11971#define CP_DFY_DATA_2__DATA__SHIFT 0x0 11972#define CP_DFY_DATA_2__DATA_MASK 0xFFFFFFFFL 11973//CP_DFY_DATA_3 11974#define CP_DFY_DATA_3__DATA__SHIFT 0x0 11975#define CP_DFY_DATA_3__DATA_MASK 0xFFFFFFFFL 11976//CP_DFY_DATA_4 11977#define CP_DFY_DATA_4__DATA__SHIFT 0x0 11978#define CP_DFY_DATA_4__DATA_MASK 0xFFFFFFFFL 11979//CP_DFY_DATA_5 11980#define CP_DFY_DATA_5__DATA__SHIFT 0x0 11981#define CP_DFY_DATA_5__DATA_MASK 0xFFFFFFFFL 11982//CP_DFY_DATA_6 11983#define CP_DFY_DATA_6__DATA__SHIFT 0x0 11984#define CP_DFY_DATA_6__DATA_MASK 0xFFFFFFFFL 11985//CP_DFY_DATA_7 11986#define CP_DFY_DATA_7__DATA__SHIFT 0x0 11987#define CP_DFY_DATA_7__DATA_MASK 0xFFFFFFFFL 11988//CP_DFY_DATA_8 11989#define CP_DFY_DATA_8__DATA__SHIFT 0x0 11990#define CP_DFY_DATA_8__DATA_MASK 0xFFFFFFFFL 11991//CP_DFY_DATA_9 11992#define CP_DFY_DATA_9__DATA__SHIFT 0x0 11993#define CP_DFY_DATA_9__DATA_MASK 0xFFFFFFFFL 11994//CP_DFY_DATA_10 11995#define CP_DFY_DATA_10__DATA__SHIFT 0x0 11996#define CP_DFY_DATA_10__DATA_MASK 0xFFFFFFFFL 11997//CP_DFY_DATA_11 11998#define CP_DFY_DATA_11__DATA__SHIFT 0x0 11999#define CP_DFY_DATA_11__DATA_MASK 0xFFFFFFFFL 12000//CP_DFY_DATA_12
12001#define CP_DFY_DATA_12__DATA__SHIFT 0x0 12002#define CP_DFY_DATA_12__DATA_MASK 0xFFFFFFFFL 12003//CP_DFY_DATA_13 12004#define CP_DFY_DATA_13__DATA__SHIFT 0x0 12005#define CP_DFY_DATA_13__DATA_MASK 0xFFFFFFFFL 12006//CP_DFY_DATA_14 12007#define CP_DFY_DATA_14__DATA__SHIFT 0x0 12008#define CP_DFY_DATA_14__DATA_MASK 0xFFFFFFFFL 12009//CP_DFY_DATA_15 12010#define CP_DFY_DATA_15__DATA__SHIFT 0x0 12011#define CP_DFY_DATA_15__DATA_MASK 0xFFFFFFFFL 12012//CP_DFY_CMD 12013#define CP_DFY_CMD__OFFSET__SHIFT 0x0 12014#define CP_DFY_CMD__SIZE__SHIFT 0x10 12015#define CP_DFY_CMD__OFFSET_MASK 0x000001FFL 12016#define CP_DFY_CMD__SIZE_MASK 0xFFFF0000L 12017//CP_EOPQ_WAIT_TIME 12018#define CP_EOPQ_WAIT_TIME__WAIT_TIME__SHIFT 0x0 12019#define CP_EOPQ_WAIT_TIME__SCALE_COUNT__SHIFT 0xa 12020#define CP_EOPQ_WAIT_TIME__WAIT_TIME_MASK 0x000003FFL 12021#define CP_EOPQ_WAIT_TIME__SCALE_COUNT_MASK 0x0003FC00L 12022//CP_CPC_MGCG_SYNC_CNTL 12023#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD__SHIFT 0x0 12024#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD__SHIFT 0x8 12025#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD_MASK 0x000000FFL 12026#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD_MASK 0x0000FF00L 12027//CPC_INT_INFO 12028#define CPC_INT_INFO__ADDR_HI__SHIFT 0x0 12029#define CPC_INT_INFO__TYPE__SHIFT 0x10 12030#define CPC_INT_INFO__VMID__SHIFT 0x14 12031#define CPC_INT_INFO__QUEUE_ID__SHIFT 0x1c 12032#define CPC_INT_INFO__ADDR_HI_MASK 0x0000FFFFL 12033#define CPC_INT_INFO__TYPE_MASK 0x00010000L 12034#define CPC_INT_INFO__VMID_MASK 0x00F00000L 12035#define CPC_INT_INFO__QUEUE_ID_MASK 0x70000000L 12036//CP_VIRT_STATUS 12037#define CP_VIRT_STATUS__VIRT_STATUS__SHIFT 0x0 12038#define CP_VIRT_STATUS__VIRT_STATUS_MASK 0xFFFFFFFFL 12039//CPC_INT_ADDR 12040#define CPC_INT_ADDR__ADDR__SHIFT 0x0 12041#define CPC_INT_ADDR__ADDR_MASK 0xFFFFFFFFL 12042//CPC_INT_PASID 12043#define CPC_INT_PASID__PASID__SHIFT 0x0 12044#define CPC_INT_PASID__PASID_MASK 0x0000FFFFL 12045//CP_GFX_ERROR 12046#define CP_GFX_ERROR__EDC_ERROR_ID__SHIFT 0x0 12047#define CP_GFX_ERROR__SUA_ERROR__SHIFT 0x4 12048#define CP_GFX_ERROR__RSVD1_ERROR__SHIFT 0x5 12049#define CP_GFX_ERROR__RSVD2_ERROR__SHIFT 0x6 12050#define CP_GFX_ERROR__SEM_UTCL1_ERROR__SHIFT 0x7 12051#define CP_GFX_ERROR__QU_STRM_UTCL1_ERROR__SHIFT 0x8 12052#define CP_GFX_ERROR__QU_EOP_UTCL1_ERROR__SHIFT 0x9 12053#define CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR__SHIFT 0xa 12054#define CP_GFX_ERROR__QU_READ_UTCL1_ERROR__SHIFT 0xb 12055#define CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR__SHIFT 0xc 12056#define CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR__SHIFT 0xd 12057#define CP_GFX_ERROR__SHADOW_UTCL1_ERROR__SHIFT 0xe 12058#define CP_GFX_ERROR__APPEND_UTCL1_ERROR__SHIFT 0xf 12059#define CP_GFX_ERROR__CE_DMA_UTCL1_ERROR__SHIFT 0x10 12060#define CP_GFX_ERROR__PFP_VGTDMA_UTCL1_ERROR__SHIFT 0x11 12061#define CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT 0x12 12062#define CP_GFX_ERROR__DMA_DST_UTCL1_ERROR__SHIFT 0x13 12063#define CP_GFX_ERROR__PFP_TC_UTCL1_ERROR__SHIFT 0x14 12064#define CP_GFX_ERROR__ME_TC_UTCL1_ERROR__SHIFT 0x15 12065#define CP_GFX_ERROR__CE_TC_UTCL1_ERROR__SHIFT 0x16 12066#define CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR__SHIFT 0x17 12067#define CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR__SHIFT 0x18 12068#define CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR__SHIFT 0x19 12069#define CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR__SHIFT 0x1a 12070#define CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR__SHIFT 0x1b 12071#define CP_GFX_ERROR__C1_FETCHER_UTCL1_ERROR__SHIFT 0x1c 12072#define CP_GFX_ERROR__C2_FETCHER_UTCL1_ERROR__SHIFT 0x1d 12073#define CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR__SHIFT 0x1e 12074#define CP_GFX_ERROR__CE_INIT_UTCL1_ERROR__SHIFT 0x1f 12075#define CP_GFX_ERROR__EDC_ERROR_ID_MASK 0x0000000FL 12076#define CP_GFX_ERROR__SUA_ERROR_MASK 0x00000010L 12077#define CP_GFX_ERROR__RSVD1_ERROR_MASK 0x00000020L 12078#define CP_GFX_ERROR__RSVD2_ERROR_MASK 0x00000040L 12079#define CP_GFX_ERROR__SEM_UTCL1_ERROR_MASK 0x00000080L 12080#define CP_GFX_ERROR__QU_STRM_UTCL1_ERROR_MASK 0x00000100L 12081#define CP_GFX_ERROR__QU_EOP_UTCL1_ERROR_MASK 0x00000200L 12082#define CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR_MASK 0x00000400L 12083#define CP_GFX_ERROR__QU_READ_UTCL1_ERROR_MASK 0x00000800L 12084#define CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR_MASK 0x00001000L 12085#define CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR_MASK 0x00002000L 12086#define CP_GFX_ERROR__SHADOW_UTCL1_ERROR_MASK 0x00004000L 12087#define CP_GFX_ERROR__APPEND_UTCL1_ERROR_MASK 0x00008000L 12088#define CP_GFX_ERROR__CE_DMA_UTCL1_ERROR_MASK 0x00010000L 12089#define CP_GFX_ERROR__PFP_VGTDMA_UTCL1_ERROR_MASK 0x00020000L 12090#define CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR_MASK 0x00040000L 12091#define CP_GFX_ERROR__DMA_DST_UTCL1_ERROR_MASK 0x00080000L 12092#define CP_GFX_ERROR__PFP_TC_UTCL1_ERROR_MASK 0x00100000L 12093#define CP_GFX_ERROR__ME_TC_UTCL1_ERROR_MASK 0x00200000L 12094#define CP_GFX_ERROR__CE_TC_UTCL1_ERROR_MASK 0x00400000L 12095#define CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR_MASK 0x00800000L 12096#define CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR_MASK 0x01000000L 12097#define CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR_MASK 0x02000000L 12098#define CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR_MASK 0x04000000L 12099#define CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR_MASK 0x08000000L 12100#define CP_GFX_ERROR__C1_FETCHER_UTCL1_ERROR_MASK 0x10000000L 12101#define CP_GFX_ERROR__C2_FETCHER_UTCL1_ERROR_MASK 0x20000000L 12102#define CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR_MASK 0x40000000L 12103#define CP_GFX_ERROR__CE_INIT_UTCL1_ERROR_MASK 0x80000000L 12104//CPG_UTCL1_CNTL 12105#define CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 12106#define CPG_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17 12107#define CPG_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 12108#define CPG_UTCL1_CNTL__BYPASS__SHIFT 0x19 12109#define CPG_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a 12110#define CPG_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b 12111#define CPG_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c 12112#define CPG_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d 12113#define CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e 12114#define CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL 12115#define CPG_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L 12116#define CPG_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L 12117#define CPG_UTCL1_CNTL__BYPASS_MASK 0x02000000L 12118#define CPG_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L 12119#define CPG_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L 12120#define CPG_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L 12121#define CPG_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L 12122#define CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L 12123//CPC_UTCL1_CNTL 12124#define CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 12125#define CPC_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 12126#define CPC_UTCL1_CNTL__BYPASS__SHIFT 0x19 12127#define CPC_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a 12128#define CPC_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b 12129#define CPC_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c 12130#define CPC_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d 12131#define CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e 12132#define CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL 12133#define CPC_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L 12134#define CPC_UTCL1_CNTL__BYPASS_MASK 0x02000000L 12135#define CPC_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L 12136#define CPC_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L 12137#define CPC_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L 12138#define CPC_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L 12139#define CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L 12140//CPF_UTCL1_CNTL 12141#define CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 12142#define CPF_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17 12143#define CPF_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 12144#define CPF_UTCL1_CNTL__BYPASS__SHIFT 0x19 12145#define CPF_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a 12146#define CPF_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b 12147#define CPF_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c 12148#define CPF_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d 12149#define CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e 12150#define CPF_UTCL1_CNTL__FORCE_NO_EXE__SHIFT 0x1f 12151#define CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL 12152#define CPF_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L 12153#define CPF_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L 12154#define CPF_UTCL1_CNTL__BYPASS_MASK 0x02000000L 12155#define CPF_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L 12156#define CPF_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L 12157#define CPF_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L 12158#define CPF_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L 12159#define CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L 12160#define CPF_UTCL1_CNTL__FORCE_NO_EXE_MASK 0x80000000L 12161//CP_AQL_SMM_STATUS 12162#define CP_AQL_SMM_STATUS__AQL_QUEUE_SMM__SHIFT 0x0 12163#define CP_AQL_SMM_STATUS__AQL_QUEUE_SMM_MASK 0xFFFFFFFFL 12164//CP_RB0_BASE 12165#define CP_RB0_BASE__RB_BASE__SHIFT 0x0 12166#define CP_RB0_BASE__RB_BASE_MASK 0xFFFFFFFFL 12167//CP_RB_BASE 12168#define CP_RB_BASE__RB_BASE__SHIFT 0x0 12169#define CP_RB_BASE__RB_BASE_MASK 0xFFFFFFFFL 12170//CP_RB0_CNTL 12171#define CP_RB0_CNTL__RB_BUFSZ__SHIFT 0x0 12172#define CP_RB0_CNTL__RB_BLKSZ__SHIFT 0x8 12173#define CP_RB0_CNTL__BUF_SWAP__SHIFT 0x11 12174#define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 0x14 12175#define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 12176#define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x18 12177#define CP_RB0_CNTL__RB_NO_UPDATE__SHIFT 0x1b 12178#define CP_RB0_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f 12179#define CP_RB0_CNTL__RB_BUFSZ_MASK 0x0000003FL 12180#define CP_RB0_CNTL__RB_BLKSZ_MASK 0x00003F00L 12181#define CP_RB0_CNTL__BUF_SWAP_MASK 0x00060000L 12182#define CP_RB0_CNTL__MIN_AVAILSZ_MASK 0x00300000L 12183#define CP_RB0_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L 12184#define CP_RB0_CNTL__CACHE_POLICY_MASK 0x01000000L 12185#define CP_RB0_CNTL__RB_NO_UPDATE_MASK 0x08000000L 12186#define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L 12187//CP_RB_CNTL 12188#define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x0 12189#define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x8 12190#define CP_RB_CNTL__MIN_AVAILSZ__SHIFT 0x14 12191#define CP_RB_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 12192#define CP_RB_CNTL__CACHE_POLICY__SHIFT 0x18 12193#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x1b 12194#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f 12195#define CP_RB_CNTL__RB_BUFSZ_MASK 0x0000003FL 12196#define CP_RB_CNTL__RB_BLKSZ_MASK 0x00003F00L 12197#define CP_RB_CNTL__MIN_AVAILSZ_MASK 0x00300000L 12198#define CP_RB_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L 12199#define CP_RB_CNTL__CACHE_POLICY_MASK 0x01000000L 12200#define CP_RB_CNTL__RB_NO_UPDATE_MASK 0x08000000L 12201#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L 12202//CP_RB_RPTR_WR 12203#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0x0 12204#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK 0x000FFFFFL 12205//CP_RB0_RPTR_ADDR 12206#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 12207#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL 12208//CP_RB_RPTR_ADDR 12209#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 12210#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL 12211//CP_RB0_RPTR_ADDR_HI 12212#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 12213#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL 12214//CP_RB_RPTR_ADDR_HI 12215#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 12216#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL 12217//CP_RB0_BUFSZ_MASK 12218#define CP_RB0_BUFSZ_MASK__DATA__SHIFT 0x0 12219#define CP_RB0_BUFSZ_MASK__DATA_MASK 0x000FFFFFL 12220//CP_RB_BUFSZ_MASK 12221#define CP_RB_BUFSZ_MASK__DATA__SHIFT 0x0 12222#define CP_RB_BUFSZ_MASK__DATA_MASK 0x000FFFFFL 12223//CP_RB_WPTR_POLL_ADDR_LO 12224#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO__SHIFT 0x2 12225#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO_MASK 0xFFFFFFFCL 12226//CP_RB_WPTR_POLL_ADDR_HI 12227#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI__SHIFT 0x0 12228#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI_MASK 0x0000FFFFL 12229//GC_PRIV_MODE 12230//CP_INT_CNTL 12231#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb 12232#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe 12233#define CP_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 12234#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 12235#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE__SHIFT 0x12 12236#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 12237#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 12238#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE__SHIFT 0x15 12239#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 12240#define CP_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 12241#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 12242#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a 12243#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b 12244#define CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d 12245#define CP_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e 12246#define CP_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f 12247#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L 12248#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L 12249#define CP_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L 12250#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L 12251#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE_MASK 0x00040000L 12252#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L 12253#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L 12254#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE_MASK 0x00200000L 12255#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L 12256#define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L 12257#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L 12258#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L 12259#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L 12260#define CP_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L 12261#define CP_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L 12262#define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L 12263//CP_INT_STATUS 12264#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb 12265#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT__SHIFT 0xe 12266#define CP_INT_STATUS__GPF_INT_STAT__SHIFT 0x10 12267#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 12268#define CP_INT_STATUS__CMP_BUSY_INT_STAT__SHIFT 0x12 12269#define CP_INT_STATUS__CNTX_BUSY_INT_STAT__SHIFT 0x13 12270#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT 0x14 12271#define CP_INT_STATUS__GFX_IDLE_INT_STAT__SHIFT 0x15 12272#define CP_INT_STATUS__PRIV_INSTR_INT_STAT__SHIFT 0x16 12273#define CP_INT_STATUS__PRIV_REG_INT_STAT__SHIFT 0x17 12274#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT__SHIFT 0x18 12275#define CP_INT_STATUS__TIME_STAMP_INT_STAT__SHIFT 0x1a 12276#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b 12277#define CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT 0x1d 12278#define CP_INT_STATUS__GENERIC1_INT_STAT__SHIFT 0x1e 12279#define CP_INT_STATUS__GENERIC0_INT_STAT__SHIFT 0x1f 12280#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L 12281#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L 12282#define CP_INT_STATUS__GPF_INT_STAT_MASK 0x00010000L 12283#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L 12284#define CP_INT_STATUS__CMP_BUSY_INT_STAT_MASK 0x00040000L 12285#define CP_INT_STATUS__CNTX_BUSY_INT_STAT_MASK 0x00080000L 12286#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT_MASK 0x00100000L 12287#define CP_INT_STATUS__GFX_IDLE_INT_STAT_MASK 0x00200000L 12288#define CP_INT_STATUS__PRIV_INSTR_INT_STAT_MASK 0x00400000L 12289#define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK 0x00800000L 12290#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT_MASK 0x01000000L 12291#define CP_INT_STATUS__TIME_STAMP_INT_STAT_MASK 0x04000000L 12292#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L 12293#define CP_INT_STATUS__GENERIC2_INT_STAT_MASK 0x20000000L 12294#define CP_INT_STATUS__GENERIC1_INT_STAT_MASK 0x40000000L 12295#define CP_INT_STATUS__GENERIC0_INT_STAT_MASK 0x80000000L 12296//CP_DEVICE_ID 12297#define CP_DEVICE_ID__DEVICE_ID__SHIFT 0x0 12298#define CP_DEVICE_ID__DEVICE_ID_MASK 0x000000FFL 12299//CP_ME0_PIPE_PRIORITY_CNTS 12300#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 12301#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 12302#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 12303#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 12304#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL 12305#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L 12306#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L 12307#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L 12308//CP_RING_PRIORITY_CNTS 12309#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 12310#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 12311#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 12312#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 12313#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL 12314#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L 12315#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L 12316#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L 12317//CP_ME0_PIPE0_PRIORITY 12318#define CP_ME0_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 12319#define CP_ME0_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L 12320//CP_RING0_PRIORITY 12321#define CP_RING0_PRIORITY__PRIORITY__SHIFT 0x0 12322#define CP_RING0_PRIORITY__PRIORITY_MASK 0x00000003L 12323//CP_ME0_PIPE1_PRIORITY 12324#define CP_ME0_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 12325#define CP_ME0_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L 12326//CP_RING1_PRIORITY 12327#define CP_RING1_PRIORITY__PRIORITY__SHIFT 0x0 12328#define CP_RING1_PRIORITY__PRIORITY_MASK 0x00000003L 12329//CP_ME0_PIPE2_PRIORITY 12330#define CP_ME0_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 12331#define CP_ME0_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L 12332//CP_RING2_PRIORITY 12333#define CP_RING2_PRIORITY__PRIORITY__SHIFT 0x0 12334#define CP_RING2_PRIORITY__PRIORITY_MASK 0x00000003L 12335//CP_FATAL_ERROR 12336#define CP_FATAL_ERROR__CPF_FATAL_ERROR__SHIFT 0x0 12337#define CP_FATAL_ERROR__CPG_FATAL_ERROR__SHIFT 0x1 12338#define CP_FATAL_ERROR__GFX_HALT_PROC__SHIFT 0x2 12339#define CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR__SHIFT 0x3 12340#define CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN__SHIFT 0x4 12341#define CP_FATAL_ERROR__CPF_FATAL_ERROR_MASK 0x00000001L 12342#define CP_FATAL_ERROR__CPG_FATAL_ERROR_MASK 0x00000002L 12343#define CP_FATAL_ERROR__GFX_HALT_PROC_MASK 0x00000004L 12344#define CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR_MASK 0x00000008L 12345#define CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN_MASK 0x00000010L 12346//CP_RB_VMID 12347#define CP_RB_VMID__RB0_VMID__SHIFT 0x0 12348#define CP_RB_VMID__RB1_VMID__SHIFT 0x8 12349#define CP_RB_VMID__RB2_VMID__SHIFT 0x10 12350#define CP_RB_VMID__RB0_VMID_MASK 0x0000000FL 12351#define CP_RB_VMID__RB1_VMID_MASK 0x00000F00L 12352#define CP_RB_VMID__RB2_VMID_MASK 0x000F0000L 12353//CP_ME0_PIPE0_VMID 12354#define CP_ME0_PIPE0_VMID__VMID__SHIFT 0x0 12355#define CP_ME0_PIPE0_VMID__VMID_MASK 0x0000000FL 12356//CP_ME0_PIPE1_VMID 12357#define CP_ME0_PIPE1_VMID__VMID__SHIFT 0x0 12358#define CP_ME0_PIPE1_VMID__VMID_MASK 0x0000000FL 12359//CP_RB0_WPTR 12360#define CP_RB0_WPTR__RB_WPTR__SHIFT 0x0 12361#define CP_RB0_WPTR__RB_WPTR_MASK 0xFFFFFFFFL 12362//CP_RB_WPTR 12363#define CP_RB_WPTR__RB_WPTR__SHIFT 0x0 12364#define CP_RB_WPTR__RB_WPTR_MASK 0xFFFFFFFFL 12365//CP_RB0_WPTR_HI 12366#define CP_RB0_WPTR_HI__RB_WPTR__SHIFT 0x0 12367#define CP_RB0_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL 12368//CP_RB_WPTR_HI 12369#define CP_RB_WPTR_HI__RB_WPTR__SHIFT 0x0 12370#define CP_RB_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL 12371//CP_RB1_WPTR 12372#define CP_RB1_WPTR__RB_WPTR__SHIFT 0x0 12373#define CP_RB1_WPTR__RB_WPTR_MASK 0xFFFFFFFFL 12374//CP_RB1_WPTR_HI 12375#define CP_RB1_WPTR_HI__RB_WPTR__SHIFT 0x0 12376#define CP_RB1_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL 12377//CP_RB2_WPTR 12378#define CP_RB2_WPTR__RB_WPTR__SHIFT 0x0 12379#define CP_RB2_WPTR__RB_WPTR_MASK 0x000FFFFFL 12380//CP_RB_DOORBELL_CONTROL 12381#define CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT 0x1 12382#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2 12383#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e 12384#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f 12385#define CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK 0x00000002L 12386#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL 12387#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000L 12388#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000L 12389//CP_RB_DOORBELL_RANGE_LOWER 12390#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2 12391#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x0FFFFFFCL 12392//CP_RB_DOORBELL_RANGE_UPPER 12393#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2 12394#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x0FFFFFFCL 12395//CP_MEC_DOORBELL_RANGE_LOWER 12396#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2 12397#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x0FFFFFFCL 12398//CP_MEC_DOORBELL_RANGE_UPPER 12399#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2 12400#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x0FFFFFFCL 12401//CPG_UTCL1_ERROR 12402#define CPG_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT 0x0 12403#define CPG_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK 0x00000001L 12404//CPC_UTCL1_ERROR 12405#define CPC_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT 0x0 12406#define CPC_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK 0x00000001L 12407//CP_RB1_BASE 12408#define CP_RB1_BASE__RB_BASE__SHIFT 0x0 12409#define CP_RB1_BASE__RB_BASE_MASK 0xFFFFFFFFL 12410//CP_RB1_CNTL 12411#define CP_RB1_CNTL__RB_BUFSZ__SHIFT 0x0 12412#define CP_RB1_CNTL__RB_BLKSZ__SHIFT 0x8 12413#define CP_RB1_CNTL__MIN_AVAILSZ__SHIFT 0x14 12414#define CP_RB1_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 12415#define CP_RB1_CNTL__CACHE_POLICY__SHIFT 0x18 12416#define CP_RB1_CNTL__RB_NO_UPDATE__SHIFT 0x1b 12417#define CP_RB1_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f 12418#define CP_RB1_CNTL__RB_BUFSZ_MASK 0x0000003FL 12419#define CP_RB1_CNTL__RB_BLKSZ_MASK 0x00003F00L 12420#define CP_RB1_CNTL__MIN_AVAILSZ_MASK 0x00300000L 12421#define CP_RB1_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L 12422#define CP_RB1_CNTL__CACHE_POLICY_MASK 0x01000000L 12423#define CP_RB1_CNTL__RB_NO_UPDATE_MASK 0x08000000L 12424#define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L 12425//CP_RB1_RPTR_ADDR 12426#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 12427#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL 12428//CP_RB1_RPTR_ADDR_HI 12429#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 12430#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL 12431//CP_RB2_BASE 12432#define CP_RB2_BASE__RB_BASE__SHIFT 0x0 12433#define CP_RB2_BASE__RB_BASE_MASK 0xFFFFFFFFL 12434//CP_RB2_CNTL 12435#define CP_RB2_CNTL__RB_BUFSZ__SHIFT 0x0 12436#define CP_RB2_CNTL__RB_BLKSZ__SHIFT 0x8 12437#define CP_RB2_CNTL__MIN_AVAILSZ__SHIFT 0x14 12438#define CP_RB2_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 12439#define CP_RB2_CNTL__CACHE_POLICY__SHIFT 0x18 12440#define CP_RB2_CNTL__RB_NO_UPDATE__SHIFT 0x1b 12441#define CP_RB2_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f 12442#define CP_RB2_CNTL__RB_BUFSZ_MASK 0x0000003FL 12443#define CP_RB2_CNTL__RB_BLKSZ_MASK 0x00003F00L 12444#define CP_RB2_CNTL__MIN_AVAILSZ_MASK 0x00300000L 12445#define CP_RB2_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L 12446#define CP_RB2_CNTL__CACHE_POLICY_MASK 0x01000000L 12447#define CP_RB2_CNTL__RB_NO_UPDATE_MASK 0x08000000L 12448#define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L 12449//CP_RB2_RPTR_ADDR 12450#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 12451#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL 12452//CP_RB2_RPTR_ADDR_HI 12453#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 12454#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL 12455//CP_RB0_ACTIVE 12456#define CP_RB0_ACTIVE__ACTIVE__SHIFT 0x0 12457#define CP_RB0_ACTIVE__ACTIVE_MASK 0x00000001L 12458//CP_RB_ACTIVE 12459#define CP_RB_ACTIVE__ACTIVE__SHIFT 0x0 12460#define CP_RB_ACTIVE__ACTIVE_MASK 0x00000001L 12461//CP_INT_CNTL_RING0 12462#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb 12463#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe 12464#define CP_INT_CNTL_RING0__GPF_INT_ENABLE__SHIFT 0x10 12465#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 12466#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE__SHIFT 0x12 12467#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 12468#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 12469#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE__SHIFT 0x15 12470#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 12471#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE__SHIFT 0x17 12472#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 12473#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE__SHIFT 0x1a 12474#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b 12475#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT 0x1d 12476#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE__SHIFT 0x1e 12477#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE__SHIFT 0x1f 12478#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L 12479#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L 12480#define CP_INT_CNTL_RING0__GPF_INT_ENABLE_MASK 0x00010000L 12481#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L 12482#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE_MASK 0x00040000L 12483#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L 12484#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L 12485#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE_MASK 0x00200000L 12486#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L 12487#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x00800000L 12488#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L 12489#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x04000000L 12490#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L 12491#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE_MASK 0x20000000L 12492#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK 0x40000000L 12493#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE_MASK 0x80000000L 12494//CP_INT_CNTL_RING1 12495#define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb 12496#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe 12497#define CP_INT_CNTL_RING1__GPF_INT_ENABLE__SHIFT 0x10 12498#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 12499#define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE__SHIFT 0x12 12500#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 12501#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 12502#define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE__SHIFT 0x15 12503#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 12504#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE__SHIFT 0x17 12505#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 12506#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE__SHIFT 0x1a 12507#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b 12508#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT 0x1d 12509#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE__SHIFT 0x1e 12510#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE__SHIFT 0x1f 12511#define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L 12512#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L 12513#define CP_INT_CNTL_RING1__GPF_INT_ENABLE_MASK 0x00010000L 12514#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L 12515#define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE_MASK 0x00040000L 12516#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L 12517#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L 12518#define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE_MASK 0x00200000L 12519#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L 12520#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK 0x00800000L 12521#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L 12522#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK 0x04000000L 12523#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L 12524#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK 0x20000000L 12525#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE_MASK 0x40000000L 12526#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE_MASK 0x80000000L 12527//CP_INT_CNTL_RING2 12528#define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb 12529#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe 12530#define CP_INT_CNTL_RING2__GPF_INT_ENABLE__SHIFT 0x10 12531#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 12532#define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE__SHIFT 0x12 12533#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 12534#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 12535#define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE__SHIFT 0x15 12536#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 12537#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE__SHIFT 0x17 12538#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 12539#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE__SHIFT 0x1a 12540#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b 12541#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE__SHIFT 0x1d 12542#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE__SHIFT 0x1e 12543#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE__SHIFT 0x1f 12544#define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L 12545#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L 12546#define CP_INT_CNTL_RING2__GPF_INT_ENABLE_MASK 0x00010000L 12547#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L 12548#define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE_MASK 0x00040000L 12549#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L 12550#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L 12551#define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE_MASK 0x00200000L 12552#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L 12553#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK 0x00800000L 12554#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L 12555#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK 0x04000000L 12556#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L 12557#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE_MASK 0x20000000L 12558#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE_MASK 0x40000000L 12559#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE_MASK 0x80000000L 12560//CP_INT_STATUS_RING0 12561#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb 12562#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT__SHIFT 0xe 12563#define CP_INT_STATUS_RING0__GPF_INT_STAT__SHIFT 0x10 12564#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 12565#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT__SHIFT 0x12 12566#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT__SHIFT 0x13 12567#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT 0x14 12568#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT__SHIFT 0x15 12569#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT__SHIFT 0x16 12570#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT__SHIFT 0x17 12571#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT__SHIFT 0x18 12572#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT__SHIFT 0x1a 12573#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b 12574#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT 0x1d 12575#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT__SHIFT 0x1e 12576#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT__SHIFT 0x1f 12577#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L 12578#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L 12579#define CP_INT_STATUS_RING0__GPF_INT_STAT_MASK 0x00010000L 12580#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L 12581#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT_MASK 0x00040000L 12582#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT_MASK 0x00080000L 12583#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT_MASK 0x00100000L 12584#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT_MASK 0x00200000L 12585#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT_MASK 0x00400000L 12586#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT_MASK 0x00800000L 12587#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT_MASK 0x01000000L 12588#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT_MASK 0x04000000L 12589#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L 12590#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT_MASK 0x20000000L 12591#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT_MASK 0x40000000L 12592#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT_MASK 0x80000000L 12593//CP_INT_STATUS_RING1 12594#define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb 12595#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT__SHIFT 0xe 12596#define CP_INT_STATUS_RING1__GPF_INT_STAT__SHIFT 0x10 12597#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 12598#define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT__SHIFT 0x12 12599#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT__SHIFT 0x13 12600#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT__SHIFT 0x14 12601#define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT__SHIFT 0x15 12602#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT__SHIFT 0x16 12603#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT 0x17 12604#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT__SHIFT 0x18 12605#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT__SHIFT 0x1a 12606#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b 12607#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT 0x1d 12608#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT__SHIFT 0x1e 12609#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT__SHIFT 0x1f 12610#define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L 12611#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L 12612#define CP_INT_STATUS_RING1__GPF_INT_STAT_MASK 0x00010000L 12613#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L 12614#define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT_MASK 0x00040000L 12615#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT_MASK 0x00080000L 12616#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT_MASK 0x00100000L 12617#define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT_MASK 0x00200000L 12618#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT_MASK 0x00400000L 12619#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT_MASK 0x00800000L 12620#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT_MASK 0x01000000L 12621#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT_MASK 0x04000000L 12622#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L 12623#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT_MASK 0x20000000L 12624#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT_MASK 0x40000000L 12625#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT_MASK 0x80000000L 12626//CP_INT_STATUS_RING2 12627#define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb 12628#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT__SHIFT 0xe 12629#define CP_INT_STATUS_RING2__GPF_INT_STAT__SHIFT 0x10 12630#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 12631#define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT__SHIFT 0x12 12632#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT__SHIFT 0x13 12633#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT__SHIFT 0x14 12634#define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT__SHIFT 0x15 12635#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT__SHIFT 0x16 12636#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT__SHIFT 0x17 12637#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT__SHIFT 0x18 12638#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT__SHIFT 0x1a 12639#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b 12640#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT__SHIFT 0x1d 12641#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT__SHIFT 0x1e 12642#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT__SHIFT 0x1f 12643#define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L 12644#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L 12645#define CP_INT_STATUS_RING2__GPF_INT_STAT_MASK 0x00010000L 12646#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L 12647#define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT_MASK 0x00040000L 12648#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT_MASK 0x00080000L 12649#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT_MASK 0x00100000L 12650#define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT_MASK 0x00200000L 12651#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT_MASK 0x00400000L 12652#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT_MASK 0x00800000L 12653#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT_MASK 0x01000000L 12654#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT_MASK 0x04000000L 12655#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L 12656#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT_MASK 0x20000000L 12657#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK 0x40000000L 12658#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT_MASK 0x80000000L 12659#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1 12660#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT_MASK 0x00000002L 12661#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1 12662#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT_MASK 0x00000002L 12663#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1 12664#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT_MASK 0x00000002L 12665//CP_PWR_CNTL 12666#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0__SHIFT 0x0 12667#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1__SHIFT 0x1 12668#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0__SHIFT 0x8 12669#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT 0x9 12670#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2__SHIFT 0xa 12671#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3__SHIFT 0xb 12672#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0__SHIFT 0x10 12673#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1__SHIFT 0x11 12674#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2__SHIFT 0x12 12675#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3__SHIFT 0x13 12676#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0_MASK 0x00000001L 12677#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK 0x00000002L 12678#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0_MASK 0x00000100L 12679#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1_MASK 0x00000200L 12680#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2_MASK 0x00000400L 12681#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3_MASK 0x00000800L 12682#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0_MASK 0x00010000L 12683#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1_MASK 0x00020000L 12684#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2_MASK 0x00040000L 12685#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3_MASK 0x00080000L 12686//CP_MEM_SLP_CNTL 12687#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN__SHIFT 0x0 12688#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN__SHIFT 0x1 12689#define CP_MEM_SLP_CNTL__RESERVED__SHIFT 0x2 12690#define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE__SHIFT 0x7 12691#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY__SHIFT 0x8 12692#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY__SHIFT 0x10 12693#define CP_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18 12694#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x00000001L 12695#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN_MASK 0x00000002L 12696#define CP_MEM_SLP_CNTL__RESERVED_MASK 0x0000007CL 12697#define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE_MASK 0x00000080L 12698#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY_MASK 0x0000FF00L 12699#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY_MASK 0x00FF0000L 12700#define CP_MEM_SLP_CNTL__RESERVED1_MASK 0xFF000000L 12701//CP_ECC_FIRSTOCCURRENCE 12702#define CP_ECC_FIRSTOCCURRENCE__INTERFACE__SHIFT 0x0 12703#define CP_ECC_FIRSTOCCURRENCE__CLIENT__SHIFT 0x4 12704#define CP_ECC_FIRSTOCCURRENCE__ME__SHIFT 0x8 12705#define CP_ECC_FIRSTOCCURRENCE__PIPE__SHIFT 0xa 12706#define CP_ECC_FIRSTOCCURRENCE__QUEUE__SHIFT 0xc 12707#define CP_ECC_FIRSTOCCURRENCE__VMID__SHIFT 0x10 12708#define CP_ECC_FIRSTOCCURRENCE__INTERFACE_MASK 0x00000003L 12709#define CP_ECC_FIRSTOCCURRENCE__CLIENT_MASK 0x000000F0L 12710#define CP_ECC_FIRSTOCCURRENCE__ME_MASK 0x00000300L 12711#define CP_ECC_FIRSTOCCURRENCE__PIPE_MASK 0x00000C00L 12712#define CP_ECC_FIRSTOCCURRENCE__QUEUE_MASK 0x00007000L 12713#define CP_ECC_FIRSTOCCURRENCE__VMID_MASK 0x000F0000L 12714//CP_ECC_FIRSTOCCURRENCE_RING0 12715#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE__SHIFT 0x0 12716#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE_MASK 0xFFFFFFFFL 12717//CP_ECC_FIRSTOCCURRENCE_RING1 12718#define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE__SHIFT 0x0 12719#define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE_MASK 0xFFFFFFFFL 12720//CP_ECC_FIRSTOCCURRENCE_RING2 12721#define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE__SHIFT 0x0 12722#define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE_MASK 0xFFFFFFFFL 12723//GB_EDC_MODE 12724#define GB_EDC_MODE__FORCE_SEC_ON_DED__SHIFT 0xf 12725#define GB_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 12726#define GB_EDC_MODE__GATE_FUE__SHIFT 0x11 12727#define GB_EDC_MODE__DED_MODE__SHIFT 0x14 12728#define GB_EDC_MODE__PROP_FED__SHIFT 0x1d 12729#define GB_EDC_MODE__BYPASS__SHIFT 0x1f 12730#define GB_EDC_MODE__FORCE_SEC_ON_DED_MASK 0x00008000L 12731#define GB_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L 12732#define GB_EDC_MODE__GATE_FUE_MASK 0x00020000L 12733#define GB_EDC_MODE__DED_MODE_MASK 0x00300000L 12734#define GB_EDC_MODE__PROP_FED_MASK 0x20000000L 12735#define GB_EDC_MODE__BYPASS_MASK 0x80000000L 12736//CP_PQ_WPTR_POLL_CNTL 12737#define CP_PQ_WPTR_POLL_CNTL__PERIOD__SHIFT 0x0 12738#define CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT__SHIFT 0x1d 12739#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE__SHIFT 0x1e 12740#define CP_PQ_WPTR_POLL_CNTL__EN__SHIFT 0x1f 12741#define CP_PQ_WPTR_POLL_CNTL__PERIOD_MASK 0x000000FFL 12742#define CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT_MASK 0x20000000L 12743#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE_MASK 0x40000000L 12744#define CP_PQ_WPTR_POLL_CNTL__EN_MASK 0x80000000L 12745//CP_PQ_WPTR_POLL_CNTL1 12746#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK__SHIFT 0x0 12747#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK_MASK 0xFFFFFFFFL 12748//CP_ME1_PIPE0_INT_CNTL 12749#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc 12750#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd 12751#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe 12752#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf 12753#define CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 12754#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 12755#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 12756#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 12757#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a 12758#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b 12759#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d 12760#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e 12761#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f 12762#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L 12763#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L 12764#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L 12765#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L 12766#define CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L 12767#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L 12768#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L 12769#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L 12770#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L 12771#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L 12772#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L 12773#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L 12774#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L 12775//CP_ME1_PIPE1_INT_CNTL 12776#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc 12777#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd 12778#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe 12779#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf 12780#define CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 12781#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 12782#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 12783#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 12784#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a 12785#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b 12786#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d 12787#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e 12788#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f 12789#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L 12790#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L 12791#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L 12792#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L 12793#define CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L 12794#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L 12795#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L 12796#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L 12797#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L 12798#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L 12799#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L 12800#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L 12801#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L 12802//CP_ME1_PIPE2_INT_CNTL 12803#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc 12804#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd 12805#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe 12806#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf 12807#define CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 12808#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 12809#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 12810#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 12811#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a 12812#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b 12813#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d 12814#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e 12815#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f 12816#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L 12817#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L 12818#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L 12819#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L 12820#define CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L 12821#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L 12822#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L 12823#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L 12824#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L 12825#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L 12826#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L 12827#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L 12828#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L 12829//CP_ME1_PIPE3_INT_CNTL 12830#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc 12831#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd 12832#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe 12833#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf 12834#define CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 12835#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 12836#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 12837#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 12838#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a 12839#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b 12840#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d 12841#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e 12842#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f 12843#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L 12844#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L 12845#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L 12846#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L 12847#define CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L 12848#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L 12849#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L 12850#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L 12851#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L 12852#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L 12853#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L 12854#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L 12855#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L 12856//CP_ME2_PIPE0_INT_CNTL 12857#define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc 12858#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd 12859#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe 12860#define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf 12861#define CP_ME2_PIPE0_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 12862#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 12863#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 12864#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 12865#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a 12866#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b 12867#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d 12868#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e 12869#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f 12870#define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L 12871#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L 12872#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L 12873#define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L 12874#define CP_ME2_PIPE0_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L 12875#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L 12876#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L 12877#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L 12878#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L 12879#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L 12880#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L 12881#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L 12882#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L 12883//CP_ME2_PIPE1_INT_CNTL 12884#define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc 12885#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd 12886#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe 12887#define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf 12888#define CP_ME2_PIPE1_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 12889#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 12890#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 12891#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 12892#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a 12893#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b 12894#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d 12895#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e 12896#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f 12897#define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L 12898#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L 12899#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L 12900#define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L 12901#define CP_ME2_PIPE1_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L 12902#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L 12903#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L 12904#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L 12905#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L 12906#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L 12907#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L 12908#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L 12909#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L 12910//CP_ME2_PIPE2_INT_CNTL 12911#define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc 12912#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd 12913#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe 12914#define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf 12915#define CP_ME2_PIPE2_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 12916#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 12917#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 12918#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 12919#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a 12920#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b 12921#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d 12922#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e 12923#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f 12924#define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L 12925#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L 12926#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L 12927#define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L 12928#define CP_ME2_PIPE2_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L 12929#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L 12930#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L 12931#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L 12932#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L 12933#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L 12934#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L 12935#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L 12936#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L 12937//CP_ME2_PIPE3_INT_CNTL 12938#define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc 12939#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd 12940#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe 12941#define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf 12942#define CP_ME2_PIPE3_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 12943#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 12944#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 12945#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 12946#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a 12947#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b 12948#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d 12949#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e 12950#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f 12951#define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L 12952#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L 12953#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L 12954#define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L 12955#define CP_ME2_PIPE3_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L 12956#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L 12957#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L 12958#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L 12959#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L 12960#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L 12961#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L 12962#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L 12963#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L 12964//CP_ME1_PIPE0_INT_STATUS 12965#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc 12966#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd 12967#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe 12968#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf 12969#define CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 12970#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 12971#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 12972#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 12973#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a 12974#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b 12975#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d 12976#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e 12977#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f 12978#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L 12979#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L 12980#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L 12981#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L 12982#define CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L 12983#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L 12984#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L 12985#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L 12986#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L 12987#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L 12988#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L 12989#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L 12990#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L 12991//CP_ME1_PIPE1_INT_STATUS 12992#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc 12993#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd 12994#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe 12995#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf 12996#define CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 12997#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 12998#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 12999#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 13000#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
13001#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b 13002#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d 13003#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e 13004#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f 13005#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L 13006#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L 13007#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L 13008#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L 13009#define CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L 13010#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L 13011#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L 13012#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L 13013#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L 13014#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L 13015#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L 13016#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L 13017#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L 13018//CP_ME1_PIPE2_INT_STATUS 13019#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc 13020#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd 13021#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe 13022#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf 13023#define CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 13024#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 13025#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 13026#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 13027#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a 13028#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b 13029#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d 13030#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e 13031#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f 13032#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L 13033#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L 13034#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L 13035#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L 13036#define CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L 13037#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L 13038#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L 13039#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L 13040#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L 13041#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L 13042#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L 13043#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L 13044#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L 13045//CP_ME1_PIPE3_INT_STATUS 13046#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc 13047#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd 13048#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe 13049#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf 13050#define CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 13051#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 13052#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 13053#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 13054#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a 13055#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b 13056#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d 13057#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e 13058#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f 13059#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L 13060#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L 13061#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L 13062#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L 13063#define CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L 13064#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L 13065#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L 13066#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L 13067#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L 13068#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L 13069#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L 13070#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L 13071#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L 13072//CP_ME2_PIPE0_INT_STATUS 13073#define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc 13074#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd 13075#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe 13076#define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf 13077#define CP_ME2_PIPE0_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 13078#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 13079#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 13080#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 13081#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a 13082#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b 13083#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d 13084#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e 13085#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f 13086#define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L 13087#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L 13088#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L 13089#define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L 13090#define CP_ME2_PIPE0_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L 13091#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L 13092#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L 13093#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L 13094#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L 13095#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L 13096#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L 13097#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L 13098#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L 13099//CP_ME2_PIPE1_INT_STATUS 13100#define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc 13101#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd 13102#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe 13103#define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf 13104#define CP_ME2_PIPE1_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 13105#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 13106#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 13107#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 13108#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a 13109#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b 13110#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d 13111#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e 13112#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f 13113#define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L 13114#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L 13115#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L 13116#define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L 13117#define CP_ME2_PIPE1_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L 13118#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L 13119#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L 13120#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L 13121#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L 13122#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L 13123#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L 13124#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L 13125#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L 13126//CP_ME2_PIPE2_INT_STATUS 13127#define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc 13128#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd 13129#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe 13130#define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf 13131#define CP_ME2_PIPE2_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 13132#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 13133#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 13134#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 13135#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a 13136#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b 13137#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d 13138#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e 13139#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f 13140#define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L 13141#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L 13142#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L 13143#define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L 13144#define CP_ME2_PIPE2_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L 13145#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L 13146#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L 13147#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L 13148#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L 13149#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L 13150#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L 13151#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L 13152#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L 13153//CP_ME2_PIPE3_INT_STATUS 13154#define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc 13155#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd 13156#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe 13157#define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf 13158#define CP_ME2_PIPE3_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 13159#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 13160#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 13161#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 13162#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a 13163#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b 13164#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d 13165#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e 13166#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f 13167#define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L 13168#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L 13169#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L 13170#define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L 13171#define CP_ME2_PIPE3_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L 13172#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L 13173#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L 13174#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L 13175#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L 13176#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L 13177#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L 13178#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L 13179#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L 13180#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 13181#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L 13182#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 13183#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L 13184//CC_GC_EDC_CONFIG 13185#define CC_GC_EDC_CONFIG__DIS_EDC__SHIFT 0x1 13186#define CC_GC_EDC_CONFIG__DIS_EDC_MASK 0x00000002L 13187//CP_ME1_PIPE_PRIORITY_CNTS 13188#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 13189#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 13190#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 13191#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 13192#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL 13193#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L 13194#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L 13195#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L 13196//CP_ME1_PIPE0_PRIORITY 13197#define CP_ME1_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 13198#define CP_ME1_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L 13199//CP_ME1_PIPE1_PRIORITY 13200#define CP_ME1_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 13201#define CP_ME1_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L 13202//CP_ME1_PIPE2_PRIORITY 13203#define CP_ME1_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 13204#define CP_ME1_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L 13205//CP_ME1_PIPE3_PRIORITY 13206#define CP_ME1_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0 13207#define CP_ME1_PIPE3_PRIORITY__PRIORITY_MASK 0x00000003L 13208//CP_ME2_PIPE_PRIORITY_CNTS 13209#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 13210#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 13211#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 13212#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 13213#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL 13214#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L 13215#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L 13216#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L 13217//CP_ME2_PIPE0_PRIORITY 13218#define CP_ME2_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 13219#define CP_ME2_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L 13220//CP_ME2_PIPE1_PRIORITY 13221#define CP_ME2_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 13222#define CP_ME2_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L 13223//CP_ME2_PIPE2_PRIORITY 13224#define CP_ME2_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 13225#define CP_ME2_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L 13226//CP_ME2_PIPE3_PRIORITY 13227#define CP_ME2_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0 13228#define CP_ME2_PIPE3_PRIORITY__PRIORITY_MASK 0x00000003L 13229//CP_CE_PRGRM_CNTR_START 13230#define CP_CE_PRGRM_CNTR_START__IP_START__SHIFT 0x0 13231#define CP_CE_PRGRM_CNTR_START__IP_START_MASK 0x000007FFL 13232//CP_PFP_PRGRM_CNTR_START 13233#define CP_PFP_PRGRM_CNTR_START__IP_START__SHIFT 0x0 13234#define CP_PFP_PRGRM_CNTR_START__IP_START_MASK 0x00001FFFL 13235//CP_ME_PRGRM_CNTR_START 13236#define CP_ME_PRGRM_CNTR_START__IP_START__SHIFT 0x0 13237#define CP_ME_PRGRM_CNTR_START__IP_START_MASK 0x00000FFFL 13238//CP_MEC1_PRGRM_CNTR_START 13239#define CP_MEC1_PRGRM_CNTR_START__IP_START__SHIFT 0x0 13240#define CP_MEC1_PRGRM_CNTR_START__IP_START_MASK 0x0000FFFFL 13241//CP_MEC2_PRGRM_CNTR_START 13242#define CP_MEC2_PRGRM_CNTR_START__IP_START__SHIFT 0x0 13243#define CP_MEC2_PRGRM_CNTR_START__IP_START_MASK 0x0000FFFFL 13244//CP_CE_INTR_ROUTINE_START 13245#define CP_CE_INTR_ROUTINE_START__IR_START__SHIFT 0x0 13246#define CP_CE_INTR_ROUTINE_START__IR_START_MASK 0x000007FFL 13247//CP_PFP_INTR_ROUTINE_START 13248#define CP_PFP_INTR_ROUTINE_START__IR_START__SHIFT 0x0 13249#define CP_PFP_INTR_ROUTINE_START__IR_START_MASK 0x00001FFFL 13250//CP_ME_INTR_ROUTINE_START 13251#define CP_ME_INTR_ROUTINE_START__IR_START__SHIFT 0x0 13252#define CP_ME_INTR_ROUTINE_START__IR_START_MASK 0x00000FFFL 13253//CP_MEC1_INTR_ROUTINE_START 13254#define CP_MEC1_INTR_ROUTINE_START__IR_START__SHIFT 0x0 13255#define CP_MEC1_INTR_ROUTINE_START__IR_START_MASK 0x0000FFFFL 13256//CP_MEC2_INTR_ROUTINE_START 13257#define CP_MEC2_INTR_ROUTINE_START__IR_START__SHIFT 0x0 13258#define CP_MEC2_INTR_ROUTINE_START__IR_START_MASK 0x0000FFFFL 13259//CP_CONTEXT_CNTL 13260#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX__SHIFT 0x0 13261#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX__SHIFT 0x4 13262#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX__SHIFT 0x10 13263#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX__SHIFT 0x14 13264#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX_MASK 0x00000007L 13265#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX_MASK 0x00000070L 13266#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX_MASK 0x00070000L 13267#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX_MASK 0x00700000L 13268//CP_MAX_CONTEXT 13269#define CP_MAX_CONTEXT__MAX_CONTEXT__SHIFT 0x0 13270#define CP_MAX_CONTEXT__MAX_CONTEXT_MASK 0x00000007L 13271//CP_IQ_WAIT_TIME1 13272#define CP_IQ_WAIT_TIME1__IB_OFFLOAD__SHIFT 0x0 13273#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD__SHIFT 0x8 13274#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD__SHIFT 0x10 13275#define CP_IQ_WAIT_TIME1__GWS__SHIFT 0x18 13276#define CP_IQ_WAIT_TIME1__IB_OFFLOAD_MASK 0x000000FFL 13277#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD_MASK 0x0000FF00L 13278#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD_MASK 0x00FF0000L 13279#define CP_IQ_WAIT_TIME1__GWS_MASK 0xFF000000L 13280//CP_IQ_WAIT_TIME2 13281#define CP_IQ_WAIT_TIME2__QUE_SLEEP__SHIFT 0x0 13282#define CP_IQ_WAIT_TIME2__SCH_WAVE__SHIFT 0x8 13283#define CP_IQ_WAIT_TIME2__SEM_REARM__SHIFT 0x10 13284#define CP_IQ_WAIT_TIME2__DEQ_RETRY__SHIFT 0x18 13285#define CP_IQ_WAIT_TIME2__QUE_SLEEP_MASK 0x000000FFL 13286#define CP_IQ_WAIT_TIME2__SCH_WAVE_MASK 0x0000FF00L 13287#define CP_IQ_WAIT_TIME2__SEM_REARM_MASK 0x00FF0000L 13288#define CP_IQ_WAIT_TIME2__DEQ_RETRY_MASK 0xFF000000L 13289//CP_RB0_BASE_HI 13290#define CP_RB0_BASE_HI__RB_BASE_HI__SHIFT 0x0 13291#define CP_RB0_BASE_HI__RB_BASE_HI_MASK 0x000000FFL 13292//CP_RB1_BASE_HI 13293#define CP_RB1_BASE_HI__RB_BASE_HI__SHIFT 0x0 13294#define CP_RB1_BASE_HI__RB_BASE_HI_MASK 0x000000FFL 13295//CP_VMID_RESET 13296#define CP_VMID_RESET__RESET_REQUEST__SHIFT 0x0 13297#define CP_VMID_RESET__RESET_REQUEST_MASK 0x0000FFFFL 13298//CPC_INT_CNTL 13299#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc 13300#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd 13301#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe 13302#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf 13303#define CPC_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 13304#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 13305#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 13306#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 13307#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a 13308#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b 13309#define CPC_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d 13310#define CPC_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e 13311#define CPC_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f 13312#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L 13313#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L 13314#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L 13315#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L 13316#define CPC_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L 13317#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L 13318#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L 13319#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L 13320#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L 13321#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L 13322#define CPC_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L 13323#define CPC_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L 13324#define CPC_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L 13325//CPC_INT_STATUS 13326#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc 13327#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd 13328#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe 13329#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf 13330#define CPC_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 13331#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 13332#define CPC_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 13333#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 13334#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a 13335#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b 13336#define CPC_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d 13337#define CPC_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e 13338#define CPC_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f 13339#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L 13340#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L 13341#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L 13342#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L 13343#define CPC_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L 13344#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L 13345#define CPC_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L 13346#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L 13347#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L 13348#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L 13349#define CPC_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L 13350#define CPC_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L 13351#define CPC_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L 13352//CP_VMID_PREEMPT 13353#define CP_VMID_PREEMPT__PREEMPT_REQUEST__SHIFT 0x0 13354#define CP_VMID_PREEMPT__VIRT_COMMAND__SHIFT 0x10 13355#define CP_VMID_PREEMPT__PREEMPT_REQUEST_MASK 0x0000FFFFL 13356#define CP_VMID_PREEMPT__VIRT_COMMAND_MASK 0x000F0000L 13357//CPC_INT_CNTX_ID 13358#define CPC_INT_CNTX_ID__CNTX_ID__SHIFT 0x0 13359#define CPC_INT_CNTX_ID__CNTX_ID_MASK 0xFFFFFFFFL 13360//CP_PQ_STATUS 13361#define CP_PQ_STATUS__DOORBELL_UPDATED__SHIFT 0x0 13362#define CP_PQ_STATUS__DOORBELL_ENABLE__SHIFT 0x1 13363#define CP_PQ_STATUS__DOORBELL_UPDATED_MASK 0x00000001L 13364#define CP_PQ_STATUS__DOORBELL_ENABLE_MASK 0x00000002L 13365//CP_CPC_IC_BASE_LO 13366#define CP_CPC_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc 13367#define CP_CPC_IC_BASE_LO__IC_BASE_LO_MASK 0xFFFFF000L 13368//CP_CPC_IC_BASE_HI 13369#define CP_CPC_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0 13370#define CP_CPC_IC_BASE_HI__IC_BASE_HI_MASK 0x0000FFFFL 13371//CP_CPC_IC_BASE_CNTL 13372#define CP_CPC_IC_BASE_CNTL__VMID__SHIFT 0x0 13373#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 13374#define CP_CPC_IC_BASE_CNTL__VMID_MASK 0x0000000FL 13375#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY_MASK 0x01000000L 13376//CP_CPC_IC_OP_CNTL 13377#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0 13378#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4 13379#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5 13380#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x00000001L 13381#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE_MASK 0x00000010L 13382#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x00000020L 13383//CP_MEC1_F32_INT_DIS 13384#define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0 13385#define CP_MEC1_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1 13386#define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2 13387#define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3 13388#define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4 13389#define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5 13390#define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6 13391#define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7 13392#define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8 13393#define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9 13394#define CP_MEC1_F32_INT_DIS__GPF_INT_CPF__SHIFT 0xa 13395#define CP_MEC1_F32_INT_DIS__GPF_INT_DMA__SHIFT 0xb 13396#define CP_MEC1_F32_INT_DIS__GPF_INT_CPC__SHIFT 0xc 13397#define CP_MEC1_F32_INT_DIS__EDC_SR_MEM_FED_INT__SHIFT 0xd 13398#define CP_MEC1_F32_INT_DIS__QUEUE_MESSAGE_INT__SHIFT 0xe 13399#define CP_MEC1_F32_INT_DIS__FATAL_EDC_ERROR_INT__SHIFT 0xf 13400#define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x00000001L 13401#define CP_MEC1_F32_INT_DIS__PRIV_REG_INT_MASK 0x00000002L 13402#define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x00000004L 13403#define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x00000008L 13404#define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x00000010L 13405#define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x00000020L 13406#define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x00000040L 13407#define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x00000080L 13408#define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x00000100L 13409#define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT_MASK 0x00000200L 13410#define CP_MEC1_F32_INT_DIS__GPF_INT_CPF_MASK 0x00000400L 13411#define CP_MEC1_F32_INT_DIS__GPF_INT_DMA_MASK 0x00000800L 13412#define CP_MEC1_F32_INT_DIS__GPF_INT_CPC_MASK 0x00001000L 13413#define CP_MEC1_F32_INT_DIS__EDC_SR_MEM_FED_INT_MASK 0x00002000L 13414#define CP_MEC1_F32_INT_DIS__QUEUE_MESSAGE_INT_MASK 0x00004000L 13415#define CP_MEC1_F32_INT_DIS__FATAL_EDC_ERROR_INT_MASK 0x00008000L 13416//CP_MEC2_F32_INT_DIS 13417#define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0 13418#define CP_MEC2_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1 13419#define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2 13420#define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3 13421#define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4 13422#define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5 13423#define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6 13424#define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7 13425#define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8 13426#define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9 13427#define CP_MEC2_F32_INT_DIS__GPF_INT_CPF__SHIFT 0xa 13428#define CP_MEC2_F32_INT_DIS__GPF_INT_DMA__SHIFT 0xb 13429#define CP_MEC2_F32_INT_DIS__GPF_INT_CPC__SHIFT 0xc 13430#define CP_MEC2_F32_INT_DIS__EDC_SR_MEM_FED_INT__SHIFT 0xd 13431#define CP_MEC2_F32_INT_DIS__QUEUE_MESSAGE_INT__SHIFT 0xe 13432#define CP_MEC2_F32_INT_DIS__FATAL_EDC_ERROR_INT__SHIFT 0xf 13433#define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x00000001L 13434#define CP_MEC2_F32_INT_DIS__PRIV_REG_INT_MASK 0x00000002L 13435#define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x00000004L 13436#define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x00000008L 13437#define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x00000010L 13438#define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x00000020L 13439#define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x00000040L 13440#define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x00000080L 13441#define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x00000100L 13442#define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT_MASK 0x00000200L 13443#define CP_MEC2_F32_INT_DIS__GPF_INT_CPF_MASK 0x00000400L 13444#define CP_MEC2_F32_INT_DIS__GPF_INT_DMA_MASK 0x00000800L 13445#define CP_MEC2_F32_INT_DIS__GPF_INT_CPC_MASK 0x00001000L 13446#define CP_MEC2_F32_INT_DIS__EDC_SR_MEM_FED_INT_MASK 0x00002000L 13447#define CP_MEC2_F32_INT_DIS__QUEUE_MESSAGE_INT_MASK 0x00004000L 13448#define CP_MEC2_F32_INT_DIS__FATAL_EDC_ERROR_INT_MASK 0x00008000L 13449//CP_VMID_STATUS 13450#define CP_VMID_STATUS__PREEMPT_DE_STATUS__SHIFT 0x0 13451#define CP_VMID_STATUS__PREEMPT_CE_STATUS__SHIFT 0x10 13452#define CP_VMID_STATUS__PREEMPT_DE_STATUS_MASK 0x0000FFFFL 13453#define CP_VMID_STATUS__PREEMPT_CE_STATUS_MASK 0xFFFF0000L 13454 13455 13456// addressBlock: gc_cppdec2 13457//CP_RB_DOORBELL_CONTROL_SCH_0 13458#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_OFFSET__SHIFT 0x2 13459#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_EN__SHIFT 0x1e 13460#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_HIT__SHIFT 0x1f 13461#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_OFFSET_MASK 0x0FFFFFFCL 13462#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_EN_MASK 0x40000000L 13463#define CP_RB_DOORBELL_CONTROL_SCH_0__DOORBELL_HIT_MASK 0x80000000L 13464//CP_RB_DOORBELL_CONTROL_SCH_1 13465#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_OFFSET__SHIFT 0x2 13466#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_EN__SHIFT 0x1e 13467#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_HIT__SHIFT 0x1f 13468#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_OFFSET_MASK 0x0FFFFFFCL 13469#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_EN_MASK 0x40000000L 13470#define CP_RB_DOORBELL_CONTROL_SCH_1__DOORBELL_HIT_MASK 0x80000000L 13471//CP_RB_DOORBELL_CONTROL_SCH_2 13472#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_OFFSET__SHIFT 0x2 13473#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_EN__SHIFT 0x1e 13474#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_HIT__SHIFT 0x1f 13475#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_OFFSET_MASK 0x0FFFFFFCL 13476#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_EN_MASK 0x40000000L 13477#define CP_RB_DOORBELL_CONTROL_SCH_2__DOORBELL_HIT_MASK 0x80000000L 13478//CP_RB_DOORBELL_CONTROL_SCH_3 13479#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_OFFSET__SHIFT 0x2 13480#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_EN__SHIFT 0x1e 13481#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_HIT__SHIFT 0x1f 13482#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_OFFSET_MASK 0x0FFFFFFCL 13483#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_EN_MASK 0x40000000L 13484#define CP_RB_DOORBELL_CONTROL_SCH_3__DOORBELL_HIT_MASK 0x80000000L 13485//CP_RB_DOORBELL_CONTROL_SCH_4 13486#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_OFFSET__SHIFT 0x2 13487#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_EN__SHIFT 0x1e 13488#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_HIT__SHIFT 0x1f 13489#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_OFFSET_MASK 0x0FFFFFFCL 13490#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_EN_MASK 0x40000000L 13491#define CP_RB_DOORBELL_CONTROL_SCH_4__DOORBELL_HIT_MASK 0x80000000L 13492//CP_RB_DOORBELL_CONTROL_SCH_5 13493#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_OFFSET__SHIFT 0x2 13494#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_EN__SHIFT 0x1e 13495#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_HIT__SHIFT 0x1f 13496#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_OFFSET_MASK 0x0FFFFFFCL 13497#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_EN_MASK 0x40000000L 13498#define CP_RB_DOORBELL_CONTROL_SCH_5__DOORBELL_HIT_MASK 0x80000000L 13499//CP_RB_DOORBELL_CONTROL_SCH_6 13500#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_OFFSET__SHIFT 0x2 13501#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_EN__SHIFT 0x1e 13502#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_HIT__SHIFT 0x1f 13503#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_OFFSET_MASK 0x0FFFFFFCL 13504#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_EN_MASK 0x40000000L 13505#define CP_RB_DOORBELL_CONTROL_SCH_6__DOORBELL_HIT_MASK 0x80000000L 13506//CP_RB_DOORBELL_CONTROL_SCH_7 13507#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_OFFSET__SHIFT 0x2 13508#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_EN__SHIFT 0x1e 13509#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_HIT__SHIFT 0x1f 13510#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_OFFSET_MASK 0x0FFFFFFCL 13511#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_EN_MASK 0x40000000L 13512#define CP_RB_DOORBELL_CONTROL_SCH_7__DOORBELL_HIT_MASK 0x80000000L 13513//CP_RB_DOORBELL_CLEAR 13514#define CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE__SHIFT 0x0 13515#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR__SHIFT 0x8 13516#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR__SHIFT 0x9 13517#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR__SHIFT 0xa 13518#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR__SHIFT 0xb 13519#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR__SHIFT 0xc 13520#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR__SHIFT 0xd 13521#define CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE_MASK 0x00000007L 13522#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR_MASK 0x00000100L 13523#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR_MASK 0x00000200L 13524#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR_MASK 0x00000400L 13525#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR_MASK 0x00000800L 13526#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR_MASK 0x00001000L 13527#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR_MASK 0x00002000L 13528//CP_GFX_MQD_CONTROL 13529#define CP_GFX_MQD_CONTROL__VMID__SHIFT 0x0 13530#define CP_GFX_MQD_CONTROL__EXE_DISABLE__SHIFT 0x17 13531#define CP_GFX_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18 13532#define CP_GFX_MQD_CONTROL__VMID_MASK 0x0000000FL 13533#define CP_GFX_MQD_CONTROL__EXE_DISABLE_MASK 0x00800000L 13534#define CP_GFX_MQD_CONTROL__CACHE_POLICY_MASK 0x01000000L 13535//CP_GFX_MQD_BASE_ADDR 13536#define CP_GFX_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2 13537#define CP_GFX_MQD_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFCL 13538//CP_GFX_MQD_BASE_ADDR_HI 13539#define CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 13540#define CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x0000FFFFL 13541//CP_RB_STATUS 13542#define CP_RB_STATUS__DOORBELL_UPDATED__SHIFT 0x0 13543#define CP_RB_STATUS__DOORBELL_ENABLE__SHIFT 0x1 13544#define CP_RB_STATUS__DOORBELL_UPDATED_MASK 0x00000001L 13545#define CP_RB_STATUS__DOORBELL_ENABLE_MASK 0x00000002L 13546//CPG_UTCL1_STATUS 13547#define CPG_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 13548#define CPG_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 13549#define CPG_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 13550#define CPG_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 13551#define CPG_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 13552#define CPG_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 13553#define CPG_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L 13554#define CPG_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L 13555#define CPG_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L 13556#define CPG_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L 13557#define CPG_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L 13558#define CPG_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L 13559//CPC_UTCL1_STATUS 13560#define CPC_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 13561#define CPC_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 13562#define CPC_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 13563#define CPC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 13564#define CPC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 13565#define CPC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 13566#define CPC_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L 13567#define CPC_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L 13568#define CPC_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L 13569#define CPC_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L 13570#define CPC_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L 13571#define CPC_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L 13572//CPF_UTCL1_STATUS 13573#define CPF_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 13574#define CPF_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 13575#define CPF_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 13576#define CPF_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 13577#define CPF_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 13578#define CPF_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 13579#define CPF_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L 13580#define CPF_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L 13581#define CPF_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L 13582#define CPF_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L 13583#define CPF_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L 13584#define CPF_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L 13585//CP_SD_CNTL 13586#define CP_SD_CNTL__CPF_EN__SHIFT 0x0 13587#define CP_SD_CNTL__CPG_EN__SHIFT 0x1 13588#define CP_SD_CNTL__CPC_EN__SHIFT 0x2 13589#define CP_SD_CNTL__RLC_EN__SHIFT 0x3 13590#define CP_SD_CNTL__SPI_EN__SHIFT 0x4 13591#define CP_SD_CNTL__WD_EN__SHIFT 0x5 13592#define CP_SD_CNTL__IA_EN__SHIFT 0x6 13593#define CP_SD_CNTL__PA_EN__SHIFT 0x7 13594#define CP_SD_CNTL__RMI_EN__SHIFT 0x8 13595#define CP_SD_CNTL__EA_EN__SHIFT 0x9 13596#define CP_SD_CNTL__CPF_EN_MASK 0x00000001L 13597#define CP_SD_CNTL__CPG_EN_MASK 0x00000002L 13598#define CP_SD_CNTL__CPC_EN_MASK 0x00000004L 13599#define CP_SD_CNTL__RLC_EN_MASK 0x00000008L 13600#define CP_SD_CNTL__SPI_EN_MASK 0x00000010L 13601#define CP_SD_CNTL__WD_EN_MASK 0x00000020L 13602#define CP_SD_CNTL__IA_EN_MASK 0x00000040L 13603#define CP_SD_CNTL__PA_EN_MASK 0x00000080L 13604#define CP_SD_CNTL__RMI_EN_MASK 0x00000100L 13605#define CP_SD_CNTL__EA_EN_MASK 0x00000200L 13606//CP_SOFT_RESET_CNTL 13607#define CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET__SHIFT 0x0 13608#define CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET__SHIFT 0x1 13609#define CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET__SHIFT 0x2 13610#define CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET__SHIFT 0x3 13611#define CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET__SHIFT 0x4 13612#define CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET__SHIFT 0x5 13613#define CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET__SHIFT 0x6 13614#define CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET_MASK 0x00000001L 13615#define CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET_MASK 0x00000002L 13616#define CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET_MASK 0x00000004L 13617#define CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET_MASK 0x00000008L 13618#define CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET_MASK 0x00000010L 13619#define CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET_MASK 0x00000020L 13620#define CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET_MASK 0x00000040L 13621//CP_CPC_GFX_CNTL 13622#define CP_CPC_GFX_CNTL__QUEUEID__SHIFT 0x0 13623#define CP_CPC_GFX_CNTL__PIPEID__SHIFT 0x3 13624#define CP_CPC_GFX_CNTL__MEID__SHIFT 0x5 13625#define CP_CPC_GFX_CNTL__VALID__SHIFT 0x7 13626#define CP_CPC_GFX_CNTL__QUEUEID_MASK 0x00000007L 13627#define CP_CPC_GFX_CNTL__PIPEID_MASK 0x00000018L 13628#define CP_CPC_GFX_CNTL__MEID_MASK 0x00000060L 13629#define CP_CPC_GFX_CNTL__VALID_MASK 0x00000080L 13630 13631 13632// addressBlock: gc_spipdec 13633//SPI_ARB_PRIORITY 13634#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0__SHIFT 0x0 13635#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1__SHIFT 0x3 13636#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2__SHIFT 0x6 13637#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3__SHIFT 0x9 13638#define SPI_ARB_PRIORITY__TS0_DUR_MULT__SHIFT 0xc 13639#define SPI_ARB_PRIORITY__TS1_DUR_MULT__SHIFT 0xe 13640#define SPI_ARB_PRIORITY__TS2_DUR_MULT__SHIFT 0x10 13641#define SPI_ARB_PRIORITY__TS3_DUR_MULT__SHIFT 0x12 13642#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0_MASK 0x00000007L 13643#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1_MASK 0x00000038L 13644#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2_MASK 0x000001C0L 13645#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3_MASK 0x00000E00L 13646#define SPI_ARB_PRIORITY__TS0_DUR_MULT_MASK 0x00003000L 13647#define SPI_ARB_PRIORITY__TS1_DUR_MULT_MASK 0x0000C000L 13648#define SPI_ARB_PRIORITY__TS2_DUR_MULT_MASK 0x00030000L 13649#define SPI_ARB_PRIORITY__TS3_DUR_MULT_MASK 0x000C0000L 13650//SPI_ARB_CYCLES_0 13651#define SPI_ARB_CYCLES_0__TS0_DURATION__SHIFT 0x0 13652#define SPI_ARB_CYCLES_0__TS1_DURATION__SHIFT 0x10 13653#define SPI_ARB_CYCLES_0__TS0_DURATION_MASK 0x0000FFFFL 13654#define SPI_ARB_CYCLES_0__TS1_DURATION_MASK 0xFFFF0000L 13655//SPI_ARB_CYCLES_1 13656#define SPI_ARB_CYCLES_1__TS2_DURATION__SHIFT 0x0 13657#define SPI_ARB_CYCLES_1__TS3_DURATION__SHIFT 0x10 13658#define SPI_ARB_CYCLES_1__TS2_DURATION_MASK 0x0000FFFFL 13659#define SPI_ARB_CYCLES_1__TS3_DURATION_MASK 0xFFFF0000L 13660//SPI_WCL_PIPE_PERCENT_GFX 13661#define SPI_WCL_PIPE_PERCENT_GFX__VALUE__SHIFT 0x0 13662#define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE__SHIFT 0x7 13663#define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE__SHIFT 0xc 13664#define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE__SHIFT 0x11 13665#define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE__SHIFT 0x16 13666#define SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK 0x0000007FL 13667#define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE_MASK 0x00000F80L 13668#define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE_MASK 0x0001F000L 13669#define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE_MASK 0x003E0000L 13670#define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE_MASK 0x07C00000L 13671//SPI_WCL_PIPE_PERCENT_HP3D 13672#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE__SHIFT 0x0 13673#define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE__SHIFT 0xc 13674#define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE__SHIFT 0x16 13675#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK 0x0000007FL 13676#define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE_MASK 0x0001F000L 13677#define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE_MASK 0x07C00000L 13678//SPI_WCL_PIPE_PERCENT_CS0 13679#define SPI_WCL_PIPE_PERCENT_CS0__VALUE__SHIFT 0x0 13680#define SPI_WCL_PIPE_PERCENT_CS0__VALUE_MASK 0x7FL 13681//SPI_WCL_PIPE_PERCENT_CS1 13682#define SPI_WCL_PIPE_PERCENT_CS1__VALUE__SHIFT 0x0 13683#define SPI_WCL_PIPE_PERCENT_CS1__VALUE_MASK 0x7FL 13684//SPI_WCL_PIPE_PERCENT_CS2 13685#define SPI_WCL_PIPE_PERCENT_CS2__VALUE__SHIFT 0x0 13686#define SPI_WCL_PIPE_PERCENT_CS2__VALUE_MASK 0x7FL 13687//SPI_WCL_PIPE_PERCENT_CS3 13688#define SPI_WCL_PIPE_PERCENT_CS3__VALUE__SHIFT 0x0 13689#define SPI_WCL_PIPE_PERCENT_CS3__VALUE_MASK 0x7FL 13690//SPI_WCL_PIPE_PERCENT_CS4 13691#define SPI_WCL_PIPE_PERCENT_CS4__VALUE__SHIFT 0x0 13692#define SPI_WCL_PIPE_PERCENT_CS4__VALUE_MASK 0x7FL 13693//SPI_WCL_PIPE_PERCENT_CS5 13694#define SPI_WCL_PIPE_PERCENT_CS5__VALUE__SHIFT 0x0 13695#define SPI_WCL_PIPE_PERCENT_CS5__VALUE_MASK 0x7FL 13696//SPI_WCL_PIPE_PERCENT_CS6 13697#define SPI_WCL_PIPE_PERCENT_CS6__VALUE__SHIFT 0x0 13698#define SPI_WCL_PIPE_PERCENT_CS6__VALUE_MASK 0x7FL 13699//SPI_WCL_PIPE_PERCENT_CS7 13700#define SPI_WCL_PIPE_PERCENT_CS7__VALUE__SHIFT 0x0 13701#define SPI_WCL_PIPE_PERCENT_CS7__VALUE_MASK 0x7FL 13702//SPI_COMPUTE_QUEUE_RESET 13703#define SPI_COMPUTE_QUEUE_RESET__RESET__SHIFT 0x0 13704#define SPI_COMPUTE_QUEUE_RESET__RESET_MASK 0x01L 13705//SPI_RESOURCE_RESERVE_CU_0 13706#define SPI_RESOURCE_RESERVE_CU_0__VGPR__SHIFT 0x0 13707#define SPI_RESOURCE_RESERVE_CU_0__SGPR__SHIFT 0x4 13708#define SPI_RESOURCE_RESERVE_CU_0__LDS__SHIFT 0x8 13709#define SPI_RESOURCE_RESERVE_CU_0__WAVES__SHIFT 0xc 13710#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS__SHIFT 0xf 13711#define SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK 0x0000000FL 13712#define SPI_RESOURCE_RESERVE_CU_0__SGPR_MASK 0x000000F0L 13713#define SPI_RESOURCE_RESERVE_CU_0__LDS_MASK 0x00000F00L 13714#define SPI_RESOURCE_RESERVE_CU_0__WAVES_MASK 0x00007000L 13715#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS_MASK 0x00078000L 13716//SPI_RESOURCE_RESERVE_CU_1 13717#define SPI_RESOURCE_RESERVE_CU_1__VGPR__SHIFT 0x0 13718#define SPI_RESOURCE_RESERVE_CU_1__SGPR__SHIFT 0x4 13719#define SPI_RESOURCE_RESERVE_CU_1__LDS__SHIFT 0x8 13720#define SPI_RESOURCE_RESERVE_CU_1__WAVES__SHIFT 0xc 13721#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS__SHIFT 0xf 13722#define SPI_RESOURCE_RESERVE_CU_1__VGPR_MASK 0x0000000FL 13723#define SPI_RESOURCE_RESERVE_CU_1__SGPR_MASK 0x000000F0L 13724#define SPI_RESOURCE_RESERVE_CU_1__LDS_MASK 0x00000F00L 13725#define SPI_RESOURCE_RESERVE_CU_1__WAVES_MASK 0x00007000L 13726#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS_MASK 0x00078000L 13727//SPI_RESOURCE_RESERVE_CU_2 13728#define SPI_RESOURCE_RESERVE_CU_2__VGPR__SHIFT 0x0 13729#define SPI_RESOURCE_RESERVE_CU_2__SGPR__SHIFT 0x4 13730#define SPI_RESOURCE_RESERVE_CU_2__LDS__SHIFT 0x8 13731#define SPI_RESOURCE_RESERVE_CU_2__WAVES__SHIFT 0xc 13732#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS__SHIFT 0xf 13733#define SPI_RESOURCE_RESERVE_CU_2__VGPR_MASK 0x0000000FL 13734#define SPI_RESOURCE_RESERVE_CU_2__SGPR_MASK 0x000000F0L 13735#define SPI_RESOURCE_RESERVE_CU_2__LDS_MASK 0x00000F00L 13736#define SPI_RESOURCE_RESERVE_CU_2__WAVES_MASK 0x00007000L 13737#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS_MASK 0x00078000L 13738//SPI_RESOURCE_RESERVE_CU_3 13739#define SPI_RESOURCE_RESERVE_CU_3__VGPR__SHIFT 0x0 13740#define SPI_RESOURCE_RESERVE_CU_3__SGPR__SHIFT 0x4 13741#define SPI_RESOURCE_RESERVE_CU_3__LDS__SHIFT 0x8 13742#define SPI_RESOURCE_RESERVE_CU_3__WAVES__SHIFT 0xc 13743#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS__SHIFT 0xf 13744#define SPI_RESOURCE_RESERVE_CU_3__VGPR_MASK 0x0000000FL 13745#define SPI_RESOURCE_RESERVE_CU_3__SGPR_MASK 0x000000F0L 13746#define SPI_RESOURCE_RESERVE_CU_3__LDS_MASK 0x00000F00L 13747#define SPI_RESOURCE_RESERVE_CU_3__WAVES_MASK 0x00007000L 13748#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS_MASK 0x00078000L 13749//SPI_RESOURCE_RESERVE_CU_4 13750#define SPI_RESOURCE_RESERVE_CU_4__VGPR__SHIFT 0x0 13751#define SPI_RESOURCE_RESERVE_CU_4__SGPR__SHIFT 0x4 13752#define SPI_RESOURCE_RESERVE_CU_4__LDS__SHIFT 0x8 13753#define SPI_RESOURCE_RESERVE_CU_4__WAVES__SHIFT 0xc 13754#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS__SHIFT 0xf 13755#define SPI_RESOURCE_RESERVE_CU_4__VGPR_MASK 0x0000000FL 13756#define SPI_RESOURCE_RESERVE_CU_4__SGPR_MASK 0x000000F0L 13757#define SPI_RESOURCE_RESERVE_CU_4__LDS_MASK 0x00000F00L 13758#define SPI_RESOURCE_RESERVE_CU_4__WAVES_MASK 0x00007000L 13759#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS_MASK 0x00078000L 13760//SPI_RESOURCE_RESERVE_CU_5 13761#define SPI_RESOURCE_RESERVE_CU_5__VGPR__SHIFT 0x0 13762#define SPI_RESOURCE_RESERVE_CU_5__SGPR__SHIFT 0x4 13763#define SPI_RESOURCE_RESERVE_CU_5__LDS__SHIFT 0x8 13764#define SPI_RESOURCE_RESERVE_CU_5__WAVES__SHIFT 0xc 13765#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS__SHIFT 0xf 13766#define SPI_RESOURCE_RESERVE_CU_5__VGPR_MASK 0x0000000FL 13767#define SPI_RESOURCE_RESERVE_CU_5__SGPR_MASK 0x000000F0L 13768#define SPI_RESOURCE_RESERVE_CU_5__LDS_MASK 0x00000F00L 13769#define SPI_RESOURCE_RESERVE_CU_5__WAVES_MASK 0x00007000L 13770#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS_MASK 0x00078000L 13771//SPI_RESOURCE_RESERVE_CU_6 13772#define SPI_RESOURCE_RESERVE_CU_6__VGPR__SHIFT 0x0 13773#define SPI_RESOURCE_RESERVE_CU_6__SGPR__SHIFT 0x4 13774#define SPI_RESOURCE_RESERVE_CU_6__LDS__SHIFT 0x8 13775#define SPI_RESOURCE_RESERVE_CU_6__WAVES__SHIFT 0xc 13776#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS__SHIFT 0xf 13777#define SPI_RESOURCE_RESERVE_CU_6__VGPR_MASK 0x0000000FL 13778#define SPI_RESOURCE_RESERVE_CU_6__SGPR_MASK 0x000000F0L 13779#define SPI_RESOURCE_RESERVE_CU_6__LDS_MASK 0x00000F00L 13780#define SPI_RESOURCE_RESERVE_CU_6__WAVES_MASK 0x00007000L 13781#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS_MASK 0x00078000L 13782//SPI_RESOURCE_RESERVE_CU_7 13783#define SPI_RESOURCE_RESERVE_CU_7__VGPR__SHIFT 0x0 13784#define SPI_RESOURCE_RESERVE_CU_7__SGPR__SHIFT 0x4 13785#define SPI_RESOURCE_RESERVE_CU_7__LDS__SHIFT 0x8 13786#define SPI_RESOURCE_RESERVE_CU_7__WAVES__SHIFT 0xc 13787#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS__SHIFT 0xf 13788#define SPI_RESOURCE_RESERVE_CU_7__VGPR_MASK 0x0000000FL 13789#define SPI_RESOURCE_RESERVE_CU_7__SGPR_MASK 0x000000F0L 13790#define SPI_RESOURCE_RESERVE_CU_7__LDS_MASK 0x00000F00L 13791#define SPI_RESOURCE_RESERVE_CU_7__WAVES_MASK 0x00007000L 13792#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS_MASK 0x00078000L 13793//SPI_RESOURCE_RESERVE_CU_8 13794#define SPI_RESOURCE_RESERVE_CU_8__VGPR__SHIFT 0x0 13795#define SPI_RESOURCE_RESERVE_CU_8__SGPR__SHIFT 0x4 13796#define SPI_RESOURCE_RESERVE_CU_8__LDS__SHIFT 0x8 13797#define SPI_RESOURCE_RESERVE_CU_8__WAVES__SHIFT 0xc 13798#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS__SHIFT 0xf 13799#define SPI_RESOURCE_RESERVE_CU_8__VGPR_MASK 0x0000000FL 13800#define SPI_RESOURCE_RESERVE_CU_8__SGPR_MASK 0x000000F0L 13801#define SPI_RESOURCE_RESERVE_CU_8__LDS_MASK 0x00000F00L 13802#define SPI_RESOURCE_RESERVE_CU_8__WAVES_MASK 0x00007000L 13803#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS_MASK 0x00078000L 13804//SPI_RESOURCE_RESERVE_CU_9 13805#define SPI_RESOURCE_RESERVE_CU_9__VGPR__SHIFT 0x0 13806#define SPI_RESOURCE_RESERVE_CU_9__SGPR__SHIFT 0x4 13807#define SPI_RESOURCE_RESERVE_CU_9__LDS__SHIFT 0x8 13808#define SPI_RESOURCE_RESERVE_CU_9__WAVES__SHIFT 0xc 13809#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS__SHIFT 0xf 13810#define SPI_RESOURCE_RESERVE_CU_9__VGPR_MASK 0x0000000FL 13811#define SPI_RESOURCE_RESERVE_CU_9__SGPR_MASK 0x000000F0L 13812#define SPI_RESOURCE_RESERVE_CU_9__LDS_MASK 0x00000F00L 13813#define SPI_RESOURCE_RESERVE_CU_9__WAVES_MASK 0x00007000L 13814#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS_MASK 0x00078000L 13815//SPI_RESOURCE_RESERVE_EN_CU_0 13816#define SPI_RESOURCE_RESERVE_EN_CU_0__EN__SHIFT 0x0 13817#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK__SHIFT 0x1 13818#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK__SHIFT 0x10 13819#define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY__SHIFT 0x18 13820#define SPI_RESOURCE_RESERVE_EN_CU_0__EN_MASK 0x00000001L 13821#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK_MASK 0x0000FFFEL 13822#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK_MASK 0x00FF0000L 13823#define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY_MASK 0x01000000L 13824//SPI_RESOURCE_RESERVE_EN_CU_1 13825#define SPI_RESOURCE_RESERVE_EN_CU_1__EN__SHIFT 0x0 13826#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK__SHIFT 0x1 13827#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK__SHIFT 0x10 13828#define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY__SHIFT 0x18 13829#define SPI_RESOURCE_RESERVE_EN_CU_1__EN_MASK 0x00000001L 13830#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK_MASK 0x0000FFFEL 13831#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK_MASK 0x00FF0000L 13832#define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY_MASK 0x01000000L 13833//SPI_RESOURCE_RESERVE_EN_CU_2 13834#define SPI_RESOURCE_RESERVE_EN_CU_2__EN__SHIFT 0x0 13835#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK__SHIFT 0x1 13836#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK__SHIFT 0x10 13837#define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY__SHIFT 0x18 13838#define SPI_RESOURCE_RESERVE_EN_CU_2__EN_MASK 0x00000001L 13839#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK_MASK 0x0000FFFEL 13840#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK_MASK 0x00FF0000L 13841#define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY_MASK 0x01000000L 13842//SPI_RESOURCE_RESERVE_EN_CU_3 13843#define SPI_RESOURCE_RESERVE_EN_CU_3__EN__SHIFT 0x0 13844#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK__SHIFT 0x1 13845#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK__SHIFT 0x10 13846#define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY__SHIFT 0x18 13847#define SPI_RESOURCE_RESERVE_EN_CU_3__EN_MASK 0x00000001L 13848#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK_MASK 0x0000FFFEL 13849#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK_MASK 0x00FF0000L 13850#define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY_MASK 0x01000000L 13851//SPI_RESOURCE_RESERVE_EN_CU_4 13852#define SPI_RESOURCE_RESERVE_EN_CU_4__EN__SHIFT 0x0 13853#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK__SHIFT 0x1 13854#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK__SHIFT 0x10 13855#define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY__SHIFT 0x18 13856#define SPI_RESOURCE_RESERVE_EN_CU_4__EN_MASK 0x00000001L 13857#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK_MASK 0x0000FFFEL 13858#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK_MASK 0x00FF0000L 13859#define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY_MASK 0x01000000L 13860//SPI_RESOURCE_RESERVE_EN_CU_5 13861#define SPI_RESOURCE_RESERVE_EN_CU_5__EN__SHIFT 0x0 13862#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK__SHIFT 0x1 13863#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK__SHIFT 0x10 13864#define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY__SHIFT 0x18 13865#define SPI_RESOURCE_RESERVE_EN_CU_5__EN_MASK 0x00000001L 13866#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK_MASK 0x0000FFFEL 13867#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK_MASK 0x00FF0000L 13868#define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY_MASK 0x01000000L 13869//SPI_RESOURCE_RESERVE_EN_CU_6 13870#define SPI_RESOURCE_RESERVE_EN_CU_6__EN__SHIFT 0x0 13871#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK__SHIFT 0x1 13872#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK__SHIFT 0x10 13873#define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY__SHIFT 0x18 13874#define SPI_RESOURCE_RESERVE_EN_CU_6__EN_MASK 0x00000001L 13875#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK_MASK 0x0000FFFEL 13876#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK_MASK 0x00FF0000L 13877#define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY_MASK 0x01000000L 13878//SPI_RESOURCE_RESERVE_EN_CU_7 13879#define SPI_RESOURCE_RESERVE_EN_CU_7__EN__SHIFT 0x0 13880#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK__SHIFT 0x1 13881#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK__SHIFT 0x10 13882#define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY__SHIFT 0x18 13883#define SPI_RESOURCE_RESERVE_EN_CU_7__EN_MASK 0x00000001L 13884#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK_MASK 0x0000FFFEL 13885#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK_MASK 0x00FF0000L 13886#define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY_MASK 0x01000000L 13887//SPI_RESOURCE_RESERVE_EN_CU_8 13888#define SPI_RESOURCE_RESERVE_EN_CU_8__EN__SHIFT 0x0 13889#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK__SHIFT 0x1 13890#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK__SHIFT 0x10 13891#define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY__SHIFT 0x18 13892#define SPI_RESOURCE_RESERVE_EN_CU_8__EN_MASK 0x00000001L 13893#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK_MASK 0x0000FFFEL 13894#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK_MASK 0x00FF0000L 13895#define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY_MASK 0x01000000L 13896//SPI_RESOURCE_RESERVE_EN_CU_9 13897#define SPI_RESOURCE_RESERVE_EN_CU_9__EN__SHIFT 0x0 13898#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK__SHIFT 0x1 13899#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK__SHIFT 0x10 13900#define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY__SHIFT 0x18 13901#define SPI_RESOURCE_RESERVE_EN_CU_9__EN_MASK 0x00000001L 13902#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK_MASK 0x0000FFFEL 13903#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK_MASK 0x00FF0000L 13904#define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY_MASK 0x01000000L 13905//SPI_RESOURCE_RESERVE_CU_10 13906#define SPI_RESOURCE_RESERVE_CU_10__VGPR__SHIFT 0x0 13907#define SPI_RESOURCE_RESERVE_CU_10__SGPR__SHIFT 0x4 13908#define SPI_RESOURCE_RESERVE_CU_10__LDS__SHIFT 0x8 13909#define SPI_RESOURCE_RESERVE_CU_10__WAVES__SHIFT 0xc 13910#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS__SHIFT 0xf 13911#define SPI_RESOURCE_RESERVE_CU_10__VGPR_MASK 0x0000000FL 13912#define SPI_RESOURCE_RESERVE_CU_10__SGPR_MASK 0x000000F0L 13913#define SPI_RESOURCE_RESERVE_CU_10__LDS_MASK 0x00000F00L 13914#define SPI_RESOURCE_RESERVE_CU_10__WAVES_MASK 0x00007000L 13915#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS_MASK 0x00078000L 13916//SPI_RESOURCE_RESERVE_CU_11 13917#define SPI_RESOURCE_RESERVE_CU_11__VGPR__SHIFT 0x0 13918#define SPI_RESOURCE_RESERVE_CU_11__SGPR__SHIFT 0x4 13919#define SPI_RESOURCE_RESERVE_CU_11__LDS__SHIFT 0x8 13920#define SPI_RESOURCE_RESERVE_CU_11__WAVES__SHIFT 0xc 13921#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS__SHIFT 0xf 13922#define SPI_RESOURCE_RESERVE_CU_11__VGPR_MASK 0x0000000FL 13923#define SPI_RESOURCE_RESERVE_CU_11__SGPR_MASK 0x000000F0L 13924#define SPI_RESOURCE_RESERVE_CU_11__LDS_MASK 0x00000F00L 13925#define SPI_RESOURCE_RESERVE_CU_11__WAVES_MASK 0x00007000L 13926#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS_MASK 0x00078000L 13927//SPI_RESOURCE_RESERVE_EN_CU_10 13928#define SPI_RESOURCE_RESERVE_EN_CU_10__EN__SHIFT 0x0 13929#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK__SHIFT 0x1 13930#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK__SHIFT 0x10 13931#define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY__SHIFT 0x18 13932#define SPI_RESOURCE_RESERVE_EN_CU_10__EN_MASK 0x00000001L 13933#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK_MASK 0x0000FFFEL 13934#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK_MASK 0x00FF0000L 13935#define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY_MASK 0x01000000L 13936//SPI_RESOURCE_RESERVE_EN_CU_11 13937#define SPI_RESOURCE_RESERVE_EN_CU_11__EN__SHIFT 0x0 13938#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK__SHIFT 0x1 13939#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK__SHIFT 0x10 13940#define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY__SHIFT 0x18 13941#define SPI_RESOURCE_RESERVE_EN_CU_11__EN_MASK 0x00000001L 13942#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK_MASK 0x0000FFFEL 13943#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK_MASK 0x00FF0000L 13944#define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY_MASK 0x01000000L 13945//SPI_RESOURCE_RESERVE_CU_12 13946#define SPI_RESOURCE_RESERVE_CU_12__VGPR__SHIFT 0x0 13947#define SPI_RESOURCE_RESERVE_CU_12__SGPR__SHIFT 0x4 13948#define SPI_RESOURCE_RESERVE_CU_12__LDS__SHIFT 0x8 13949#define SPI_RESOURCE_RESERVE_CU_12__WAVES__SHIFT 0xc 13950#define SPI_RESOURCE_RESERVE_CU_12__BARRIERS__SHIFT 0xf 13951#define SPI_RESOURCE_RESERVE_CU_12__VGPR_MASK 0x0000000FL 13952#define SPI_RESOURCE_RESERVE_CU_12__SGPR_MASK 0x000000F0L 13953#define SPI_RESOURCE_RESERVE_CU_12__LDS_MASK 0x00000F00L 13954#define SPI_RESOURCE_RESERVE_CU_12__WAVES_MASK 0x00007000L 13955#define SPI_RESOURCE_RESERVE_CU_12__BARRIERS_MASK 0x00078000L 13956//SPI_RESOURCE_RESERVE_CU_13 13957#define SPI_RESOURCE_RESERVE_CU_13__VGPR__SHIFT 0x0 13958#define SPI_RESOURCE_RESERVE_CU_13__SGPR__SHIFT 0x4 13959#define SPI_RESOURCE_RESERVE_CU_13__LDS__SHIFT 0x8 13960#define SPI_RESOURCE_RESERVE_CU_13__WAVES__SHIFT 0xc 13961#define SPI_RESOURCE_RESERVE_CU_13__BARRIERS__SHIFT 0xf 13962#define SPI_RESOURCE_RESERVE_CU_13__VGPR_MASK 0x0000000FL 13963#define SPI_RESOURCE_RESERVE_CU_13__SGPR_MASK 0x000000F0L 13964#define SPI_RESOURCE_RESERVE_CU_13__LDS_MASK 0x00000F00L 13965#define SPI_RESOURCE_RESERVE_CU_13__WAVES_MASK 0x00007000L 13966#define SPI_RESOURCE_RESERVE_CU_13__BARRIERS_MASK 0x00078000L 13967//SPI_RESOURCE_RESERVE_CU_14 13968#define SPI_RESOURCE_RESERVE_CU_14__VGPR__SHIFT 0x0 13969#define SPI_RESOURCE_RESERVE_CU_14__SGPR__SHIFT 0x4 13970#define SPI_RESOURCE_RESERVE_CU_14__LDS__SHIFT 0x8 13971#define SPI_RESOURCE_RESERVE_CU_14__WAVES__SHIFT 0xc 13972#define SPI_RESOURCE_RESERVE_CU_14__BARRIERS__SHIFT 0xf 13973#define SPI_RESOURCE_RESERVE_CU_14__VGPR_MASK 0x0000000FL 13974#define SPI_RESOURCE_RESERVE_CU_14__SGPR_MASK 0x000000F0L 13975#define SPI_RESOURCE_RESERVE_CU_14__LDS_MASK 0x00000F00L 13976#define SPI_RESOURCE_RESERVE_CU_14__WAVES_MASK 0x00007000L 13977#define SPI_RESOURCE_RESERVE_CU_14__BARRIERS_MASK 0x00078000L 13978//SPI_RESOURCE_RESERVE_CU_15 13979#define SPI_RESOURCE_RESERVE_CU_15__VGPR__SHIFT 0x0 13980#define SPI_RESOURCE_RESERVE_CU_15__SGPR__SHIFT 0x4 13981#define SPI_RESOURCE_RESERVE_CU_15__LDS__SHIFT 0x8 13982#define SPI_RESOURCE_RESERVE_CU_15__WAVES__SHIFT 0xc 13983#define SPI_RESOURCE_RESERVE_CU_15__BARRIERS__SHIFT 0xf 13984#define SPI_RESOURCE_RESERVE_CU_15__VGPR_MASK 0x0000000FL 13985#define SPI_RESOURCE_RESERVE_CU_15__SGPR_MASK 0x000000F0L 13986#define SPI_RESOURCE_RESERVE_CU_15__LDS_MASK 0x00000F00L 13987#define SPI_RESOURCE_RESERVE_CU_15__WAVES_MASK 0x00007000L 13988#define SPI_RESOURCE_RESERVE_CU_15__BARRIERS_MASK 0x00078000L 13989//SPI_RESOURCE_RESERVE_EN_CU_12 13990#define SPI_RESOURCE_RESERVE_EN_CU_12__EN__SHIFT 0x0 13991#define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK__SHIFT 0x1 13992#define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK__SHIFT 0x10 13993#define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY__SHIFT 0x18 13994#define SPI_RESOURCE_RESERVE_EN_CU_12__EN_MASK 0x00000001L 13995#define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK_MASK 0x0000FFFEL 13996#define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK_MASK 0x00FF0000L 13997#define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY_MASK 0x01000000L 13998//SPI_RESOURCE_RESERVE_EN_CU_13 13999#define SPI_RESOURCE_RESERVE_EN_CU_13__EN__SHIFT 0x0 14000#define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK__SHIFT 0x1
14001#define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK__SHIFT 0x10 14002#define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY__SHIFT 0x18 14003#define SPI_RESOURCE_RESERVE_EN_CU_13__EN_MASK 0x00000001L 14004#define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK_MASK 0x0000FFFEL 14005#define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK_MASK 0x00FF0000L 14006#define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY_MASK 0x01000000L 14007//SPI_RESOURCE_RESERVE_EN_CU_14 14008#define SPI_RESOURCE_RESERVE_EN_CU_14__EN__SHIFT 0x0 14009#define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK__SHIFT 0x1 14010#define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK__SHIFT 0x10 14011#define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY__SHIFT 0x18 14012#define SPI_RESOURCE_RESERVE_EN_CU_14__EN_MASK 0x00000001L 14013#define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK_MASK 0x0000FFFEL 14014#define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK_MASK 0x00FF0000L 14015#define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY_MASK 0x01000000L 14016//SPI_RESOURCE_RESERVE_EN_CU_15 14017#define SPI_RESOURCE_RESERVE_EN_CU_15__EN__SHIFT 0x0 14018#define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK__SHIFT 0x1 14019#define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK__SHIFT 0x10 14020#define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY__SHIFT 0x18 14021#define SPI_RESOURCE_RESERVE_EN_CU_15__EN_MASK 0x00000001L 14022#define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK_MASK 0x0000FFFEL 14023#define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK_MASK 0x00FF0000L 14024#define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY_MASK 0x01000000L 14025//SPI_COMPUTE_WF_CTX_SAVE 14026#define SPI_COMPUTE_WF_CTX_SAVE__INITIATE__SHIFT 0x0 14027#define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN__SHIFT 0x1 14028#define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN__SHIFT 0x2 14029#define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY__SHIFT 0x1e 14030#define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY__SHIFT 0x1f 14031#define SPI_COMPUTE_WF_CTX_SAVE__INITIATE_MASK 0x00000001L 14032#define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN_MASK 0x00000002L 14033#define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN_MASK 0x00000004L 14034#define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY_MASK 0x40000000L 14035#define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY_MASK 0x80000000L 14036//SPI_ARB_CNTL_0 14037#define SPI_ARB_CNTL_0__EXP_ARB_COL_WT__SHIFT 0x0 14038#define SPI_ARB_CNTL_0__EXP_ARB_POS_WT__SHIFT 0x4 14039#define SPI_ARB_CNTL_0__EXP_ARB_GDS_WT__SHIFT 0x8 14040#define SPI_ARB_CNTL_0__EXP_ARB_COL_WT_MASK 0x0000000FL 14041#define SPI_ARB_CNTL_0__EXP_ARB_POS_WT_MASK 0x000000F0L 14042#define SPI_ARB_CNTL_0__EXP_ARB_GDS_WT_MASK 0x00000F00L 14043 14044 14045// addressBlock: gc_cpphqddec 14046//CP_HQD_GFX_CONTROL 14047#define CP_HQD_GFX_CONTROL__MESSAGE__SHIFT 0x0 14048#define CP_HQD_GFX_CONTROL__MISC__SHIFT 0x4 14049#define CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT 0xf 14050#define CP_HQD_GFX_CONTROL__MESSAGE_MASK 0x0000000FL 14051#define CP_HQD_GFX_CONTROL__MISC_MASK 0x00007FF0L 14052#define CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN_MASK 0x00008000L 14053//CP_HQD_GFX_STATUS 14054#define CP_HQD_GFX_STATUS__STATUS__SHIFT 0x0 14055#define CP_HQD_GFX_STATUS__STATUS_MASK 0x0000FFFFL 14056//CP_HPD_ROQ_OFFSETS 14057#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT 0x0 14058#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET__SHIFT 0x8 14059#define CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT 0x10 14060#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET_MASK 0x00000007L 14061#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET_MASK 0x00003F00L 14062#define CP_HPD_ROQ_OFFSETS__IB_OFFSET_MASK 0x003F0000L 14063//CP_HPD_STATUS0 14064#define CP_HPD_STATUS0__QUEUE_STATE__SHIFT 0x0 14065#define CP_HPD_STATUS0__MAPPED_QUEUE__SHIFT 0x5 14066#define CP_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT 0x8 14067#define CP_HPD_STATUS0__FETCHING_MQD__SHIFT 0x10 14068#define CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB__SHIFT 0x11 14069#define CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ__SHIFT 0x12 14070#define CP_HPD_STATUS0__FORCE_QUEUE_STATE__SHIFT 0x14 14071#define CP_HPD_STATUS0__FORCE_QUEUE__SHIFT 0x1f 14072#define CP_HPD_STATUS0__QUEUE_STATE_MASK 0x0000001FL 14073#define CP_HPD_STATUS0__MAPPED_QUEUE_MASK 0x000000E0L 14074#define CP_HPD_STATUS0__QUEUE_AVAILABLE_MASK 0x0000FF00L 14075#define CP_HPD_STATUS0__FETCHING_MQD_MASK 0x00010000L 14076#define CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB_MASK 0x00020000L 14077#define CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ_MASK 0x00040000L 14078#define CP_HPD_STATUS0__FORCE_QUEUE_STATE_MASK 0x01F00000L 14079#define CP_HPD_STATUS0__FORCE_QUEUE_MASK 0x80000000L 14080//CP_HPD_UTCL1_CNTL 14081#define CP_HPD_UTCL1_CNTL__SELECT__SHIFT 0x0 14082#define CP_HPD_UTCL1_CNTL__SELECT_MASK 0x0000000FL 14083//CP_HPD_UTCL1_ERROR 14084#define CP_HPD_UTCL1_ERROR__ADDR_HI__SHIFT 0x0 14085#define CP_HPD_UTCL1_ERROR__TYPE__SHIFT 0x10 14086#define CP_HPD_UTCL1_ERROR__VMID__SHIFT 0x14 14087#define CP_HPD_UTCL1_ERROR__ADDR_HI_MASK 0x0000FFFFL 14088#define CP_HPD_UTCL1_ERROR__TYPE_MASK 0x00010000L 14089#define CP_HPD_UTCL1_ERROR__VMID_MASK 0x00F00000L 14090//CP_HPD_UTCL1_ERROR_ADDR 14091#define CP_HPD_UTCL1_ERROR_ADDR__ADDR__SHIFT 0xc 14092#define CP_HPD_UTCL1_ERROR_ADDR__ADDR_MASK 0xFFFFF000L 14093//CP_MQD_BASE_ADDR 14094#define CP_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2 14095#define CP_MQD_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFCL 14096//CP_MQD_BASE_ADDR_HI 14097#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 14098#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x0000FFFFL 14099//CP_HQD_ACTIVE 14100#define CP_HQD_ACTIVE__ACTIVE__SHIFT 0x0 14101#define CP_HQD_ACTIVE__BUSY_GATE__SHIFT 0x1 14102#define CP_HQD_ACTIVE__ACTIVE_MASK 0x00000001L 14103#define CP_HQD_ACTIVE__BUSY_GATE_MASK 0x00000002L 14104//CP_HQD_VMID 14105#define CP_HQD_VMID__VMID__SHIFT 0x0 14106#define CP_HQD_VMID__IB_VMID__SHIFT 0x8 14107#define CP_HQD_VMID__VQID__SHIFT 0x10 14108#define CP_HQD_VMID__VMID_MASK 0x0000000FL 14109#define CP_HQD_VMID__IB_VMID_MASK 0x00000F00L 14110#define CP_HQD_VMID__VQID_MASK 0x03FF0000L 14111//CP_HQD_PERSISTENT_STATE 14112#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ__SHIFT 0x0 14113#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT 0x8 14114#define CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN__SHIFT 0x15 14115#define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN__SHIFT 0x16 14116#define CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN__SHIFT 0x17 14117#define CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN__SHIFT 0x18 14118#define CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN__SHIFT 0x19 14119#define CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN__SHIFT 0x1a 14120#define CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN__SHIFT 0x1b 14121#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE__SHIFT 0x1c 14122#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES__SHIFT 0x1d 14123#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT 0x1e 14124#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE__SHIFT 0x1f 14125#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK 0x00000001L 14126#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE_MASK 0x0003FF00L 14127#define CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN_MASK 0x00200000L 14128#define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN_MASK 0x00400000L 14129#define CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN_MASK 0x00800000L 14130#define CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN_MASK 0x01000000L 14131#define CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN_MASK 0x02000000L 14132#define CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN_MASK 0x04000000L 14133#define CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN_MASK 0x08000000L 14134#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE_MASK 0x10000000L 14135#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES_MASK 0x20000000L 14136#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE_MASK 0x40000000L 14137#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE_MASK 0x80000000L 14138//CP_HQD_PIPE_PRIORITY 14139#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY__SHIFT 0x0 14140#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY_MASK 0x00000003L 14141//CP_HQD_QUEUE_PRIORITY 14142#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT 0x0 14143#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK 0x0000000FL 14144//CP_HQD_QUANTUM 14145#define CP_HQD_QUANTUM__QUANTUM_EN__SHIFT 0x0 14146#define CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT 0x4 14147#define CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT 0x8 14148#define CP_HQD_QUANTUM__QUANTUM_ACTIVE__SHIFT 0x1f 14149#define CP_HQD_QUANTUM__QUANTUM_EN_MASK 0x00000001L 14150#define CP_HQD_QUANTUM__QUANTUM_SCALE_MASK 0x00000010L 14151#define CP_HQD_QUANTUM__QUANTUM_DURATION_MASK 0x00003F00L 14152#define CP_HQD_QUANTUM__QUANTUM_ACTIVE_MASK 0x80000000L 14153//CP_HQD_PQ_BASE 14154#define CP_HQD_PQ_BASE__ADDR__SHIFT 0x0 14155#define CP_HQD_PQ_BASE__ADDR_MASK 0xFFFFFFFFL 14156//CP_HQD_PQ_BASE_HI 14157#define CP_HQD_PQ_BASE_HI__ADDR_HI__SHIFT 0x0 14158#define CP_HQD_PQ_BASE_HI__ADDR_HI_MASK 0x000000FFL 14159//CP_HQD_PQ_RPTR 14160#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET__SHIFT 0x0 14161#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET_MASK 0xFFFFFFFFL 14162//CP_HQD_PQ_RPTR_REPORT_ADDR 14163#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR__SHIFT 0x2 14164#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR_MASK 0xFFFFFFFCL 14165//CP_HQD_PQ_RPTR_REPORT_ADDR_HI 14166#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI__SHIFT 0x0 14167#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI_MASK 0x0000FFFFL 14168//CP_HQD_PQ_WPTR_POLL_ADDR 14169#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR__SHIFT 0x3 14170#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR_MASK 0xFFFFFFF8L 14171//CP_HQD_PQ_WPTR_POLL_ADDR_HI 14172#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI__SHIFT 0x0 14173#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK 0x0000FFFFL 14174//CP_HQD_PQ_DOORBELL_CONTROL 14175#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT 0x0 14176#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT 0x1 14177#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2 14178#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE__SHIFT 0x1c 14179#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT__SHIFT 0x1d 14180#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e 14181#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f 14182#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE_MASK 0x00000001L 14183#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK 0x00000002L 14184#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL 14185#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK 0x10000000L 14186#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT_MASK 0x20000000L 14187#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000L 14188#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000L 14189//CP_HQD_PQ_CONTROL 14190#define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT 0x0 14191#define CP_HQD_PQ_CONTROL__WPTR_CARRY__SHIFT 0x6 14192#define CP_HQD_PQ_CONTROL__RPTR_CARRY__SHIFT 0x7 14193#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT 0x8 14194#define CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT 0xe 14195#define CP_HQD_PQ_CONTROL__PQ_EMPTY__SHIFT 0xf 14196#define CP_HQD_PQ_CONTROL__WPP_CLAMP_EN__SHIFT 0x10 14197#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT 0x11 14198#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE__SHIFT 0x14 14199#define CP_HQD_PQ_CONTROL__EXE_DISABLE__SHIFT 0x17 14200#define CP_HQD_PQ_CONTROL__CACHE_POLICY__SHIFT 0x18 14201#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT 0x19 14202#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR__SHIFT 0x1b 14203#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH__SHIFT 0x1c 14204#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP__SHIFT 0x1d 14205#define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e 14206#define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT 0x1f 14207#define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK 0x0000003FL 14208#define CP_HQD_PQ_CONTROL__WPTR_CARRY_MASK 0x00000040L 14209#define CP_HQD_PQ_CONTROL__RPTR_CARRY_MASK 0x00000080L 14210#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK 0x00003F00L 14211#define CP_HQD_PQ_CONTROL__QUEUE_FULL_EN_MASK 0x00004000L 14212#define CP_HQD_PQ_CONTROL__PQ_EMPTY_MASK 0x00008000L 14213#define CP_HQD_PQ_CONTROL__WPP_CLAMP_EN_MASK 0x00010000L 14214#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP_MASK 0x00060000L 14215#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE_MASK 0x00300000L 14216#define CP_HQD_PQ_CONTROL__EXE_DISABLE_MASK 0x00800000L 14217#define CP_HQD_PQ_CONTROL__CACHE_POLICY_MASK 0x01000000L 14218#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK 0x06000000L 14219#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK 0x08000000L 14220#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK 0x10000000L 14221#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK 0x20000000L 14222#define CP_HQD_PQ_CONTROL__PRIV_STATE_MASK 0x40000000L 14223#define CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK 0x80000000L 14224//CP_HQD_IB_BASE_ADDR 14225#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR__SHIFT 0x2 14226#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR_MASK 0xFFFFFFFCL 14227//CP_HQD_IB_BASE_ADDR_HI 14228#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI__SHIFT 0x0 14229#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI_MASK 0x0000FFFFL 14230//CP_HQD_IB_RPTR 14231#define CP_HQD_IB_RPTR__CONSUMED_OFFSET__SHIFT 0x0 14232#define CP_HQD_IB_RPTR__CONSUMED_OFFSET_MASK 0x000FFFFFL 14233//CP_HQD_IB_CONTROL 14234#define CP_HQD_IB_CONTROL__IB_SIZE__SHIFT 0x0 14235#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT 0x14 14236#define CP_HQD_IB_CONTROL__IB_EXE_DISABLE__SHIFT 0x17 14237#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY__SHIFT 0x18 14238#define CP_HQD_IB_CONTROL__PROCESSING_IB__SHIFT 0x1f 14239#define CP_HQD_IB_CONTROL__IB_SIZE_MASK 0x000FFFFFL 14240#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE_MASK 0x00300000L 14241#define CP_HQD_IB_CONTROL__IB_EXE_DISABLE_MASK 0x00800000L 14242#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY_MASK 0x01000000L 14243#define CP_HQD_IB_CONTROL__PROCESSING_IB_MASK 0x80000000L 14244//CP_HQD_IQ_TIMER 14245#define CP_HQD_IQ_TIMER__WAIT_TIME__SHIFT 0x0 14246#define CP_HQD_IQ_TIMER__RETRY_TYPE__SHIFT 0x8 14247#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE__SHIFT 0xb 14248#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc 14249#define CP_HQD_IQ_TIMER__CLOCK_COUNT__SHIFT 0xe 14250#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE__SHIFT 0x10 14251#define CP_HQD_IQ_TIMER__QUANTUM_TIMER__SHIFT 0x16 14252#define CP_HQD_IQ_TIMER__EXE_DISABLE__SHIFT 0x17 14253#define CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT 0x18 14254#define CP_HQD_IQ_TIMER__QUEUE_TYPE__SHIFT 0x19 14255#define CP_HQD_IQ_TIMER__REARM_TIMER__SHIFT 0x1c 14256#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN__SHIFT 0x1d 14257#define CP_HQD_IQ_TIMER__PROCESSING_IQ__SHIFT 0x1e 14258#define CP_HQD_IQ_TIMER__ACTIVE__SHIFT 0x1f 14259#define CP_HQD_IQ_TIMER__WAIT_TIME_MASK 0x000000FFL 14260#define CP_HQD_IQ_TIMER__RETRY_TYPE_MASK 0x00000700L 14261#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE_MASK 0x00000800L 14262#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE_MASK 0x00003000L 14263#define CP_HQD_IQ_TIMER__CLOCK_COUNT_MASK 0x0000C000L 14264#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK 0x003F0000L 14265#define CP_HQD_IQ_TIMER__QUANTUM_TIMER_MASK 0x00400000L 14266#define CP_HQD_IQ_TIMER__EXE_DISABLE_MASK 0x00800000L 14267#define CP_HQD_IQ_TIMER__CACHE_POLICY_MASK 0x01000000L 14268#define CP_HQD_IQ_TIMER__QUEUE_TYPE_MASK 0x02000000L 14269#define CP_HQD_IQ_TIMER__REARM_TIMER_MASK 0x10000000L 14270#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN_MASK 0x20000000L 14271#define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK 0x40000000L 14272#define CP_HQD_IQ_TIMER__ACTIVE_MASK 0x80000000L 14273//CP_HQD_IQ_RPTR 14274#define CP_HQD_IQ_RPTR__OFFSET__SHIFT 0x0 14275#define CP_HQD_IQ_RPTR__OFFSET_MASK 0x0000003FL 14276//CP_HQD_DEQUEUE_REQUEST 14277#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT 0x0 14278#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT 0x4 14279#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT__SHIFT 0x8 14280#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN__SHIFT 0x9 14281#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT 0xa 14282#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK 0x00000007L 14283#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK 0x00000010L 14284#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT_MASK 0x00000100L 14285#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN_MASK 0x00000200L 14286#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN_MASK 0x00000400L 14287//CP_HQD_DMA_OFFLOAD 14288#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0 14289#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_MASK 0x00000001L 14290//CP_HQD_OFFLOAD 14291#define CP_HQD_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0 14292#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN__SHIFT 0x1 14293#define CP_HQD_OFFLOAD__AQL_OFFLOAD__SHIFT 0x2 14294#define CP_HQD_OFFLOAD__AQL_OFFLOAD_EN__SHIFT 0x3 14295#define CP_HQD_OFFLOAD__EOP_OFFLOAD__SHIFT 0x4 14296#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN__SHIFT 0x5 14297#define CP_HQD_OFFLOAD__DMA_OFFLOAD_MASK 0x00000001L 14298#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN_MASK 0x00000002L 14299#define CP_HQD_OFFLOAD__AQL_OFFLOAD_MASK 0x00000004L 14300#define CP_HQD_OFFLOAD__AQL_OFFLOAD_EN_MASK 0x00000008L 14301#define CP_HQD_OFFLOAD__EOP_OFFLOAD_MASK 0x00000010L 14302#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN_MASK 0x00000020L 14303//CP_HQD_SEMA_CMD 14304#define CP_HQD_SEMA_CMD__RETRY__SHIFT 0x0 14305#define CP_HQD_SEMA_CMD__RESULT__SHIFT 0x1 14306#define CP_HQD_SEMA_CMD__RETRY_MASK 0x00000001L 14307#define CP_HQD_SEMA_CMD__RESULT_MASK 0x00000006L 14308//CP_HQD_MSG_TYPE 14309#define CP_HQD_MSG_TYPE__ACTION__SHIFT 0x0 14310#define CP_HQD_MSG_TYPE__SAVE_STATE__SHIFT 0x4 14311#define CP_HQD_MSG_TYPE__ACTION_MASK 0x00000007L 14312#define CP_HQD_MSG_TYPE__SAVE_STATE_MASK 0x00000070L 14313//CP_HQD_ATOMIC0_PREOP_LO 14314#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO__SHIFT 0x0 14315#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL 14316//CP_HQD_ATOMIC0_PREOP_HI 14317#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI__SHIFT 0x0 14318#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL 14319//CP_HQD_ATOMIC1_PREOP_LO 14320#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO__SHIFT 0x0 14321#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL 14322//CP_HQD_ATOMIC1_PREOP_HI 14323#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI__SHIFT 0x0 14324#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL 14325//CP_HQD_HQ_SCHEDULER0 14326#define CP_HQD_HQ_SCHEDULER0__SCHEDULER__SHIFT 0x0 14327#define CP_HQD_HQ_SCHEDULER0__SCHEDULER_MASK 0xFFFFFFFFL 14328//CP_HQD_HQ_STATUS0 14329#define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS__SHIFT 0x0 14330#define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT__SHIFT 0x2 14331#define CP_HQD_HQ_STATUS0__RSV_6_4__SHIFT 0x4 14332#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT__SHIFT 0x7 14333#define CP_HQD_HQ_STATUS0__TCL2_DIRTY__SHIFT 0x8 14334#define CP_HQD_HQ_STATUS0__PG_ACTIVATED__SHIFT 0x9 14335#define CP_HQD_HQ_STATUS0__RSVR_29_10__SHIFT 0xa 14336#define CP_HQD_HQ_STATUS0__QUEUE_IDLE__SHIFT 0x1e 14337#define CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN__SHIFT 0x1f 14338#define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS_MASK 0x00000003L 14339#define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT_MASK 0x0000000CL 14340#define CP_HQD_HQ_STATUS0__RSV_6_4_MASK 0x00000070L 14341#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT_MASK 0x00000080L 14342#define CP_HQD_HQ_STATUS0__TCL2_DIRTY_MASK 0x00000100L 14343#define CP_HQD_HQ_STATUS0__PG_ACTIVATED_MASK 0x00000200L 14344#define CP_HQD_HQ_STATUS0__RSVR_29_10_MASK 0x3FFFFC00L 14345#define CP_HQD_HQ_STATUS0__QUEUE_IDLE_MASK 0x40000000L 14346#define CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN_MASK 0x80000000L 14347//CP_HQD_HQ_CONTROL0 14348#define CP_HQD_HQ_CONTROL0__CONTROL__SHIFT 0x0 14349#define CP_HQD_HQ_CONTROL0__CONTROL_MASK 0xFFFFFFFFL 14350//CP_HQD_HQ_SCHEDULER1 14351#define CP_HQD_HQ_SCHEDULER1__SCHEDULER__SHIFT 0x0 14352#define CP_HQD_HQ_SCHEDULER1__SCHEDULER_MASK 0xFFFFFFFFL 14353//CP_MQD_CONTROL 14354#define CP_MQD_CONTROL__VMID__SHIFT 0x0 14355#define CP_MQD_CONTROL__PRIV_STATE__SHIFT 0x8 14356#define CP_MQD_CONTROL__PROCESSING_MQD__SHIFT 0xc 14357#define CP_MQD_CONTROL__PROCESSING_MQD_EN__SHIFT 0xd 14358#define CP_MQD_CONTROL__EXE_DISABLE__SHIFT 0x17 14359#define CP_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18 14360#define CP_MQD_CONTROL__VMID_MASK 0x0000000FL 14361#define CP_MQD_CONTROL__PRIV_STATE_MASK 0x00000100L 14362#define CP_MQD_CONTROL__PROCESSING_MQD_MASK 0x00001000L 14363#define CP_MQD_CONTROL__PROCESSING_MQD_EN_MASK 0x00002000L 14364#define CP_MQD_CONTROL__EXE_DISABLE_MASK 0x00800000L 14365#define CP_MQD_CONTROL__CACHE_POLICY_MASK 0x01000000L 14366//CP_HQD_HQ_STATUS1 14367#define CP_HQD_HQ_STATUS1__STATUS__SHIFT 0x0 14368#define CP_HQD_HQ_STATUS1__STATUS_MASK 0xFFFFFFFFL 14369//CP_HQD_HQ_CONTROL1 14370#define CP_HQD_HQ_CONTROL1__CONTROL__SHIFT 0x0 14371#define CP_HQD_HQ_CONTROL1__CONTROL_MASK 0xFFFFFFFFL 14372//CP_HQD_EOP_BASE_ADDR 14373#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR__SHIFT 0x0 14374#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL 14375//CP_HQD_EOP_BASE_ADDR_HI 14376#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 14377#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x000000FFL 14378//CP_HQD_EOP_CONTROL 14379#define CP_HQD_EOP_CONTROL__EOP_SIZE__SHIFT 0x0 14380#define CP_HQD_EOP_CONTROL__PROCESSING_EOP__SHIFT 0x8 14381#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN__SHIFT 0xc 14382#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB__SHIFT 0xd 14383#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN__SHIFT 0xe 14384#define CP_HQD_EOP_CONTROL__HALT_FETCHER__SHIFT 0x15 14385#define CP_HQD_EOP_CONTROL__HALT_FETCHER_EN__SHIFT 0x16 14386#define CP_HQD_EOP_CONTROL__EXE_DISABLE__SHIFT 0x17 14387#define CP_HQD_EOP_CONTROL__CACHE_POLICY__SHIFT 0x18 14388#define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT__SHIFT 0x1d 14389#define CP_HQD_EOP_CONTROL__PEND_SIG_SEM__SHIFT 0x1f 14390#define CP_HQD_EOP_CONTROL__EOP_SIZE_MASK 0x0000003FL 14391#define CP_HQD_EOP_CONTROL__PROCESSING_EOP_MASK 0x00000100L 14392#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN_MASK 0x00001000L 14393#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB_MASK 0x00002000L 14394#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN_MASK 0x00004000L 14395#define CP_HQD_EOP_CONTROL__HALT_FETCHER_MASK 0x00200000L 14396#define CP_HQD_EOP_CONTROL__HALT_FETCHER_EN_MASK 0x00400000L 14397#define CP_HQD_EOP_CONTROL__EXE_DISABLE_MASK 0x00800000L 14398#define CP_HQD_EOP_CONTROL__CACHE_POLICY_MASK 0x01000000L 14399#define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT_MASK 0x60000000L 14400#define CP_HQD_EOP_CONTROL__PEND_SIG_SEM_MASK 0x80000000L 14401//CP_HQD_EOP_RPTR 14402#define CP_HQD_EOP_RPTR__RPTR__SHIFT 0x0 14403#define CP_HQD_EOP_RPTR__RESET_FETCHER__SHIFT 0x1c 14404#define CP_HQD_EOP_RPTR__DEQUEUE_PEND__SHIFT 0x1d 14405#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR__SHIFT 0x1e 14406#define CP_HQD_EOP_RPTR__INIT_FETCHER__SHIFT 0x1f 14407#define CP_HQD_EOP_RPTR__RPTR_MASK 0x00001FFFL 14408#define CP_HQD_EOP_RPTR__RESET_FETCHER_MASK 0x10000000L 14409#define CP_HQD_EOP_RPTR__DEQUEUE_PEND_MASK 0x20000000L 14410#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR_MASK 0x40000000L 14411#define CP_HQD_EOP_RPTR__INIT_FETCHER_MASK 0x80000000L 14412//CP_HQD_EOP_WPTR 14413#define CP_HQD_EOP_WPTR__WPTR__SHIFT 0x0 14414#define CP_HQD_EOP_WPTR__EOP_EMPTY__SHIFT 0xf 14415#define CP_HQD_EOP_WPTR__EOP_AVAIL__SHIFT 0x10 14416#define CP_HQD_EOP_WPTR__WPTR_MASK 0x00001FFFL 14417#define CP_HQD_EOP_WPTR__EOP_EMPTY_MASK 0x00008000L 14418#define CP_HQD_EOP_WPTR__EOP_AVAIL_MASK 0x1FFF0000L 14419//CP_HQD_EOP_EVENTS 14420#define CP_HQD_EOP_EVENTS__EVENT_COUNT__SHIFT 0x0 14421#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND__SHIFT 0x10 14422#define CP_HQD_EOP_EVENTS__EVENT_COUNT_MASK 0x00000FFFL 14423#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND_MASK 0x00010000L 14424//CP_HQD_CTX_SAVE_BASE_ADDR_LO 14425#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR__SHIFT 0xc 14426#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR_MASK 0xFFFFF000L 14427//CP_HQD_CTX_SAVE_BASE_ADDR_HI 14428#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 14429#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL 14430//CP_HQD_CTX_SAVE_CONTROL 14431#define CP_HQD_CTX_SAVE_CONTROL__POLICY__SHIFT 0x3 14432#define CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE__SHIFT 0x17 14433#define CP_HQD_CTX_SAVE_CONTROL__POLICY_MASK 0x00000008L 14434#define CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE_MASK 0x00800000L 14435//CP_HQD_CNTL_STACK_OFFSET 14436#define CP_HQD_CNTL_STACK_OFFSET__OFFSET__SHIFT 0x2 14437#define CP_HQD_CNTL_STACK_OFFSET__OFFSET_MASK 0x00007FFCL 14438//CP_HQD_CNTL_STACK_SIZE 14439#define CP_HQD_CNTL_STACK_SIZE__SIZE__SHIFT 0xc 14440#define CP_HQD_CNTL_STACK_SIZE__SIZE_MASK 0x00007000L 14441//CP_HQD_WG_STATE_OFFSET 14442#define CP_HQD_WG_STATE_OFFSET__OFFSET__SHIFT 0x2 14443#define CP_HQD_WG_STATE_OFFSET__OFFSET_MASK 0x01FFFFFCL 14444//CP_HQD_CTX_SAVE_SIZE 14445#define CP_HQD_CTX_SAVE_SIZE__SIZE__SHIFT 0xc 14446#define CP_HQD_CTX_SAVE_SIZE__SIZE_MASK 0x01FFF000L 14447//CP_HQD_GDS_RESOURCE_STATE 14448#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED__SHIFT 0x0 14449#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED__SHIFT 0x1 14450#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE__SHIFT 0x4 14451#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR__SHIFT 0xc 14452#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED_MASK 0x00000001L 14453#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED_MASK 0x00000002L 14454#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE_MASK 0x000003F0L 14455#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR_MASK 0x0003F000L 14456//CP_HQD_ERROR 14457#define CP_HQD_ERROR__EDC_ERROR_ID__SHIFT 0x0 14458#define CP_HQD_ERROR__SUA_ERROR__SHIFT 0x4 14459#define CP_HQD_ERROR__AQL_ERROR__SHIFT 0x5 14460#define CP_HQD_ERROR__PQ_UTCL1_ERROR__SHIFT 0x8 14461#define CP_HQD_ERROR__IB_UTCL1_ERROR__SHIFT 0x9 14462#define CP_HQD_ERROR__EOP_UTCL1_ERROR__SHIFT 0xa 14463#define CP_HQD_ERROR__IQ_UTCL1_ERROR__SHIFT 0xb 14464#define CP_HQD_ERROR__RRPT_UTCL1_ERROR__SHIFT 0xc 14465#define CP_HQD_ERROR__WPP_UTCL1_ERROR__SHIFT 0xd 14466#define CP_HQD_ERROR__SEM_UTCL1_ERROR__SHIFT 0xe 14467#define CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT 0xf 14468#define CP_HQD_ERROR__DMA_DST_UTCL1_ERROR__SHIFT 0x10 14469#define CP_HQD_ERROR__SR_UTCL1_ERROR__SHIFT 0x11 14470#define CP_HQD_ERROR__QU_UTCL1_ERROR__SHIFT 0x12 14471#define CP_HQD_ERROR__TC_UTCL1_ERROR__SHIFT 0x13 14472#define CP_HQD_ERROR__EDC_ERROR_ID_MASK 0x0000000FL 14473#define CP_HQD_ERROR__SUA_ERROR_MASK 0x00000010L 14474#define CP_HQD_ERROR__AQL_ERROR_MASK 0x00000020L 14475#define CP_HQD_ERROR__PQ_UTCL1_ERROR_MASK 0x00000100L 14476#define CP_HQD_ERROR__IB_UTCL1_ERROR_MASK 0x00000200L 14477#define CP_HQD_ERROR__EOP_UTCL1_ERROR_MASK 0x00000400L 14478#define CP_HQD_ERROR__IQ_UTCL1_ERROR_MASK 0x00000800L 14479#define CP_HQD_ERROR__RRPT_UTCL1_ERROR_MASK 0x00001000L 14480#define CP_HQD_ERROR__WPP_UTCL1_ERROR_MASK 0x00002000L 14481#define CP_HQD_ERROR__SEM_UTCL1_ERROR_MASK 0x00004000L 14482#define CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR_MASK 0x00008000L 14483#define CP_HQD_ERROR__DMA_DST_UTCL1_ERROR_MASK 0x00010000L 14484#define CP_HQD_ERROR__SR_UTCL1_ERROR_MASK 0x00020000L 14485#define CP_HQD_ERROR__QU_UTCL1_ERROR_MASK 0x00040000L 14486#define CP_HQD_ERROR__TC_UTCL1_ERROR_MASK 0x00080000L 14487//CP_HQD_EOP_WPTR_MEM 14488#define CP_HQD_EOP_WPTR_MEM__WPTR__SHIFT 0x0 14489#define CP_HQD_EOP_WPTR_MEM__WPTR_MASK 0x00001FFFL 14490//CP_HQD_AQL_CONTROL 14491#define CP_HQD_AQL_CONTROL__CONTROL0__SHIFT 0x0 14492#define CP_HQD_AQL_CONTROL__CONTROL0_EN__SHIFT 0xf 14493#define CP_HQD_AQL_CONTROL__CONTROL1__SHIFT 0x10 14494#define CP_HQD_AQL_CONTROL__CONTROL1_EN__SHIFT 0x1f 14495#define CP_HQD_AQL_CONTROL__CONTROL0_MASK 0x00007FFFL 14496#define CP_HQD_AQL_CONTROL__CONTROL0_EN_MASK 0x00008000L 14497#define CP_HQD_AQL_CONTROL__CONTROL1_MASK 0x7FFF0000L 14498#define CP_HQD_AQL_CONTROL__CONTROL1_EN_MASK 0x80000000L 14499//CP_HQD_PQ_WPTR_LO 14500#define CP_HQD_PQ_WPTR_LO__OFFSET__SHIFT 0x0 14501#define CP_HQD_PQ_WPTR_LO__OFFSET_MASK 0xFFFFFFFFL 14502//CP_HQD_PQ_WPTR_HI 14503#define CP_HQD_PQ_WPTR_HI__DATA__SHIFT 0x0 14504#define CP_HQD_PQ_WPTR_HI__DATA_MASK 0xFFFFFFFFL 14505 14506 14507// addressBlock: gc_didtdec 14508//DIDT_IND_INDEX 14509#define DIDT_IND_INDEX__DIDT_IND_INDEX__SHIFT 0x0 14510#define DIDT_IND_INDEX__DIDT_IND_INDEX_MASK 0xFFFFFFFFL 14511//DIDT_IND_DATA 14512#define DIDT_IND_DATA__DIDT_IND_DATA__SHIFT 0x0 14513#define DIDT_IND_DATA__DIDT_IND_DATA_MASK 0xFFFFFFFFL 14514 14515 14516// addressBlock: gc_gccacdec 14517//GC_CAC_CTRL_1 14518#define GC_CAC_CTRL_1__CAC_WINDOW__SHIFT 0x0 14519#define GC_CAC_CTRL_1__TDP_WINDOW__SHIFT 0x18 14520#define GC_CAC_CTRL_1__CAC_WINDOW_MASK 0x00FFFFFFL 14521#define GC_CAC_CTRL_1__TDP_WINDOW_MASK 0xFF000000L 14522//GC_CAC_CTRL_2 14523#define GC_CAC_CTRL_2__CAC_ENABLE__SHIFT 0x0 14524#define GC_CAC_CTRL_2__CAC_SOFT_CTRL_ENABLE__SHIFT 0x1 14525#define GC_CAC_CTRL_2__UNUSED_0__SHIFT 0x2 14526#define GC_CAC_CTRL_2__CAC_ENABLE_MASK 0x00000001L 14527#define GC_CAC_CTRL_2__CAC_SOFT_CTRL_ENABLE_MASK 0x00000002L 14528#define GC_CAC_CTRL_2__UNUSED_0_MASK 0xFFFFFFFCL 14529//GC_CAC_CGTT_CLK_CTRL 14530#define GC_CAC_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 14531#define GC_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 14532#define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e 14533#define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f 14534#define GC_CAC_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 14535#define GC_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 14536#define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L 14537#define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L 14538//GC_CAC_AGGR_LOWER 14539#define GC_CAC_AGGR_LOWER__AGGR_31_0__SHIFT 0x0 14540#define GC_CAC_AGGR_LOWER__AGGR_31_0_MASK 0xFFFFFFFFL 14541//GC_CAC_AGGR_UPPER 14542#define GC_CAC_AGGR_UPPER__AGGR_63_32__SHIFT 0x0 14543#define GC_CAC_AGGR_UPPER__AGGR_63_32_MASK 0xFFFFFFFFL 14544//GC_CAC_PG_AGGR_LOWER 14545#define GC_CAC_PG_AGGR_LOWER__LKG_AGGR_31_0__SHIFT 0x0 14546#define GC_CAC_PG_AGGR_LOWER__LKG_AGGR_31_0_MASK 0xFFFFFFFFL 14547//GC_CAC_PG_AGGR_UPPER 14548#define GC_CAC_PG_AGGR_UPPER__LKG_AGGR_63_32__SHIFT 0x0 14549#define GC_CAC_PG_AGGR_UPPER__LKG_AGGR_63_32_MASK 0xFFFFFFFFL 14550//GC_CAC_SOFT_CTRL 14551#define GC_CAC_SOFT_CTRL__SOFT_SNAP__SHIFT 0x0 14552#define GC_CAC_SOFT_CTRL__UNUSED__SHIFT 0x1 14553#define GC_CAC_SOFT_CTRL__SOFT_SNAP_MASK 0x00000001L 14554#define GC_CAC_SOFT_CTRL__UNUSED_MASK 0xFFFFFFFEL 14555//GC_DIDT_CTRL0 14556#define GC_DIDT_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 14557#define GC_DIDT_CTRL0__PHASE_OFFSET__SHIFT 0x1 14558#define GC_DIDT_CTRL0__DIDT_SW_RST__SHIFT 0x3 14559#define GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4 14560#define GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x5 14561#define GC_DIDT_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L 14562#define GC_DIDT_CTRL0__PHASE_OFFSET_MASK 0x00000006L 14563#define GC_DIDT_CTRL0__DIDT_SW_RST_MASK 0x00000008L 14564#define GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L 14565#define GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001E0L 14566//GC_DIDT_CTRL1 14567#define GC_DIDT_CTRL1__MIN_POWER__SHIFT 0x0 14568#define GC_DIDT_CTRL1__MAX_POWER__SHIFT 0x10 14569#define GC_DIDT_CTRL1__MIN_POWER_MASK 0x0000FFFFL 14570#define GC_DIDT_CTRL1__MAX_POWER_MASK 0xFFFF0000L 14571//GC_DIDT_CTRL2 14572#define GC_DIDT_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 14573#define GC_DIDT_CTRL2__UNUSED_0__SHIFT 0xe 14574#define GC_DIDT_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 14575#define GC_DIDT_CTRL2__UNUSED_1__SHIFT 0x1a 14576#define GC_DIDT_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b 14577#define GC_DIDT_CTRL2__UNUSED_2__SHIFT 0x1f 14578#define GC_DIDT_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL 14579#define GC_DIDT_CTRL2__UNUSED_0_MASK 0x0000C000L 14580#define GC_DIDT_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L 14581#define GC_DIDT_CTRL2__UNUSED_1_MASK 0x04000000L 14582#define GC_DIDT_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L 14583#define GC_DIDT_CTRL2__UNUSED_2_MASK 0x80000000L 14584//GC_DIDT_WEIGHT 14585#define GC_DIDT_WEIGHT__SQ_WEIGHT__SHIFT 0x0 14586#define GC_DIDT_WEIGHT__DB_WEIGHT__SHIFT 0x8 14587#define GC_DIDT_WEIGHT__TD_WEIGHT__SHIFT 0x10 14588#define GC_DIDT_WEIGHT__TCP_WEIGHT__SHIFT 0x18 14589#define GC_DIDT_WEIGHT__SQ_WEIGHT_MASK 0x000000FFL 14590#define GC_DIDT_WEIGHT__DB_WEIGHT_MASK 0x0000FF00L 14591#define GC_DIDT_WEIGHT__TD_WEIGHT_MASK 0x00FF0000L 14592#define GC_DIDT_WEIGHT__TCP_WEIGHT_MASK 0xFF000000L 14593//GC_EDC_CTRL 14594#define GC_EDC_CTRL__EDC_EN__SHIFT 0x0 14595#define GC_EDC_CTRL__EDC_SW_RST__SHIFT 0x1 14596#define GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2 14597#define GC_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3 14598#define GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 14599#define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x9 14600#define GC_EDC_CTRL__UNUSED_0__SHIFT 0xa 14601#define GC_EDC_CTRL__EDC_EN_MASK 0x00000001L 14602#define GC_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L 14603#define GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L 14604#define GC_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L 14605#define GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L 14606#define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00000200L 14607#define GC_EDC_CTRL__UNUSED_0_MASK 0xFFFFFC00L 14608//GC_EDC_THRESHOLD 14609#define GC_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0 14610#define GC_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL 14611//GC_EDC_STATUS 14612#define GC_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x0 14613#define GC_EDC_STATUS__EDC_ROLLING_DROOP_DELTA__SHIFT 0x3 14614#define GC_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x00000007L 14615#define GC_EDC_STATUS__EDC_ROLLING_DROOP_DELTA_MASK 0x03FFFFF8L 14616//GC_EDC_OVERFLOW 14617#define GC_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0 14618#define GC_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1 14619#define GC_EDC_OVERFLOW__EDC_DROOP_LEVEL_OVERFLOW__SHIFT 0x11 14620#define GC_EDC_OVERFLOW__PSM_COUNTER__SHIFT 0x12 14621#define GC_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L 14622#define GC_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL 14623#define GC_EDC_OVERFLOW__EDC_DROOP_LEVEL_OVERFLOW_MASK 0x00020000L 14624#define GC_EDC_OVERFLOW__PSM_COUNTER_MASK 0xFFFC0000L 14625//GC_EDC_ROLLING_POWER_DELTA 14626#define GC_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0 14627#define GC_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL 14628//GC_DIDT_DROOP_CTRL 14629#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_EN__SHIFT 0x0 14630#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_THRESHOLD__SHIFT 0x1 14631#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_INDEX__SHIFT 0xf 14632#define GC_DIDT_DROOP_CTRL__DIDT_LEVEL_SEL__SHIFT 0x13 14633#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_OVERFLOW__SHIFT 0x1f 14634#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_EN_MASK 0x00000001L 14635#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_THRESHOLD_MASK 0x00007FFEL 14636#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_INDEX_MASK 0x00078000L 14637#define GC_DIDT_DROOP_CTRL__DIDT_LEVEL_SEL_MASK 0x00080000L 14638#define GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_OVERFLOW_MASK 0x80000000L 14639//GC_EDC_DROOP_CTRL 14640#define GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_EN__SHIFT 0x0 14641#define GC_EDC_DROOP_CTRL__EDC_DROOP_THRESHOLD__SHIFT 0x1 14642#define GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_INDEX__SHIFT 0xf 14643#define GC_EDC_DROOP_CTRL__AVG_PSM_SEL__SHIFT 0x14 14644#define GC_EDC_DROOP_CTRL__EDC_LEVEL_SEL__SHIFT 0x15 14645#define GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_EN_MASK 0x00000001L 14646#define GC_EDC_DROOP_CTRL__EDC_DROOP_THRESHOLD_MASK 0x00007FFEL 14647#define GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_INDEX_MASK 0x000F8000L 14648#define GC_EDC_DROOP_CTRL__AVG_PSM_SEL_MASK 0x00100000L 14649#define GC_EDC_DROOP_CTRL__EDC_LEVEL_SEL_MASK 0x00200000L 14650//GC_CAC_IND_INDEX 14651#define GC_CAC_IND_INDEX__GC_CAC_IND_ADDR__SHIFT 0x0 14652#define GC_CAC_IND_INDEX__GC_CAC_IND_ADDR_MASK 0xFFFFFFFFL 14653//GC_CAC_IND_DATA 14654#define GC_CAC_IND_DATA__GC_CAC_IND_DATA__SHIFT 0x0 14655#define GC_CAC_IND_DATA__GC_CAC_IND_DATA_MASK 0xFFFFFFFFL 14656//SE_CAC_CGTT_CLK_CTRL 14657#define SE_CAC_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 14658#define SE_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 14659#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e 14660#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f 14661#define SE_CAC_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 14662#define SE_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 14663#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L 14664#define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L 14665//SE_CAC_IND_INDEX 14666#define SE_CAC_IND_INDEX__SE_CAC_IND_ADDR__SHIFT 0x0 14667#define SE_CAC_IND_INDEX__SE_CAC_IND_ADDR_MASK 0xFFFFFFFFL 14668//SE_CAC_IND_DATA 14669#define SE_CAC_IND_DATA__SE_CAC_IND_DATA__SHIFT 0x0 14670#define SE_CAC_IND_DATA__SE_CAC_IND_DATA_MASK 0xFFFFFFFFL 14671 14672 14673// addressBlock: gc_tcpdec 14674//TCP_WATCH0_ADDR_H 14675#define TCP_WATCH0_ADDR_H__ADDR__SHIFT 0x0 14676#define TCP_WATCH0_ADDR_H__ADDR_MASK 0x0000FFFFL 14677//TCP_WATCH0_ADDR_L 14678#define TCP_WATCH0_ADDR_L__ADDR__SHIFT 0x6 14679#define TCP_WATCH0_ADDR_L__ADDR_MASK 0xFFFFFFC0L 14680//TCP_WATCH0_CNTL 14681#define TCP_WATCH0_CNTL__MASK__SHIFT 0x0 14682#define TCP_WATCH0_CNTL__VMID__SHIFT 0x18 14683#define TCP_WATCH0_CNTL__ATC__SHIFT 0x1c 14684#define TCP_WATCH0_CNTL__MODE__SHIFT 0x1d 14685#define TCP_WATCH0_CNTL__VALID__SHIFT 0x1f 14686#define TCP_WATCH0_CNTL__MASK_MASK 0x00FFFFFFL 14687#define TCP_WATCH0_CNTL__VMID_MASK 0x0F000000L 14688#define TCP_WATCH0_CNTL__ATC_MASK 0x10000000L 14689#define TCP_WATCH0_CNTL__MODE_MASK 0x60000000L 14690#define TCP_WATCH0_CNTL__VALID_MASK 0x80000000L 14691//TCP_WATCH1_ADDR_H 14692#define TCP_WATCH1_ADDR_H__ADDR__SHIFT 0x0 14693#define TCP_WATCH1_ADDR_H__ADDR_MASK 0x0000FFFFL 14694//TCP_WATCH1_ADDR_L 14695#define TCP_WATCH1_ADDR_L__ADDR__SHIFT 0x6 14696#define TCP_WATCH1_ADDR_L__ADDR_MASK 0xFFFFFFC0L 14697//TCP_WATCH1_CNTL 14698#define TCP_WATCH1_CNTL__MASK__SHIFT 0x0 14699#define TCP_WATCH1_CNTL__VMID__SHIFT 0x18 14700#define TCP_WATCH1_CNTL__ATC__SHIFT 0x1c 14701#define TCP_WATCH1_CNTL__MODE__SHIFT 0x1d 14702#define TCP_WATCH1_CNTL__VALID__SHIFT 0x1f 14703#define TCP_WATCH1_CNTL__MASK_MASK 0x00FFFFFFL 14704#define TCP_WATCH1_CNTL__VMID_MASK 0x0F000000L 14705#define TCP_WATCH1_CNTL__ATC_MASK 0x10000000L 14706#define TCP_WATCH1_CNTL__MODE_MASK 0x60000000L 14707#define TCP_WATCH1_CNTL__VALID_MASK 0x80000000L 14708//TCP_WATCH2_ADDR_H 14709#define TCP_WATCH2_ADDR_H__ADDR__SHIFT 0x0 14710#define TCP_WATCH2_ADDR_H__ADDR_MASK 0x0000FFFFL 14711//TCP_WATCH2_ADDR_L 14712#define TCP_WATCH2_ADDR_L__ADDR__SHIFT 0x6 14713#define TCP_WATCH2_ADDR_L__ADDR_MASK 0xFFFFFFC0L 14714//TCP_WATCH2_CNTL 14715#define TCP_WATCH2_CNTL__MASK__SHIFT 0x0 14716#define TCP_WATCH2_CNTL__VMID__SHIFT 0x18 14717#define TCP_WATCH2_CNTL__ATC__SHIFT 0x1c 14718#define TCP_WATCH2_CNTL__MODE__SHIFT 0x1d 14719#define TCP_WATCH2_CNTL__VALID__SHIFT 0x1f 14720#define TCP_WATCH2_CNTL__MASK_MASK 0x00FFFFFFL 14721#define TCP_WATCH2_CNTL__VMID_MASK 0x0F000000L 14722#define TCP_WATCH2_CNTL__ATC_MASK 0x10000000L 14723#define TCP_WATCH2_CNTL__MODE_MASK 0x60000000L 14724#define TCP_WATCH2_CNTL__VALID_MASK 0x80000000L 14725//TCP_WATCH3_ADDR_H 14726#define TCP_WATCH3_ADDR_H__ADDR__SHIFT 0x0 14727#define TCP_WATCH3_ADDR_H__ADDR_MASK 0x0000FFFFL 14728//TCP_WATCH3_ADDR_L 14729#define TCP_WATCH3_ADDR_L__ADDR__SHIFT 0x6 14730#define TCP_WATCH3_ADDR_L__ADDR_MASK 0xFFFFFFC0L 14731//TCP_WATCH3_CNTL 14732#define TCP_WATCH3_CNTL__MASK__SHIFT 0x0 14733#define TCP_WATCH3_CNTL__VMID__SHIFT 0x18 14734#define TCP_WATCH3_CNTL__ATC__SHIFT 0x1c 14735#define TCP_WATCH3_CNTL__MODE__SHIFT 0x1d 14736#define TCP_WATCH3_CNTL__VALID__SHIFT 0x1f 14737#define TCP_WATCH3_CNTL__MASK_MASK 0x00FFFFFFL 14738#define TCP_WATCH3_CNTL__VMID_MASK 0x0F000000L 14739#define TCP_WATCH3_CNTL__ATC_MASK 0x10000000L 14740#define TCP_WATCH3_CNTL__MODE_MASK 0x60000000L 14741#define TCP_WATCH3_CNTL__VALID_MASK 0x80000000L 14742//TCP_GATCL1_CNTL 14743#define TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID__SHIFT 0x19 14744#define TCP_GATCL1_CNTL__FORCE_MISS__SHIFT 0x1a 14745#define TCP_GATCL1_CNTL__FORCE_IN_ORDER__SHIFT 0x1b 14746#define TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c 14747#define TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e 14748#define TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID_MASK 0x02000000L 14749#define TCP_GATCL1_CNTL__FORCE_MISS_MASK 0x04000000L 14750#define TCP_GATCL1_CNTL__FORCE_IN_ORDER_MASK 0x08000000L 14751#define TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L 14752#define TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L 14753//TCP_ATC_EDC_GATCL1_CNT 14754#define TCP_ATC_EDC_GATCL1_CNT__DATA_SEC__SHIFT 0x0 14755#define TCP_ATC_EDC_GATCL1_CNT__DATA_SEC_MASK 0x000000FFL 14756//TCP_GATCL1_DSM_CNTL 14757#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0__SHIFT 0x0 14758#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1__SHIFT 0x1 14759#define TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A__SHIFT 0x2 14760#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0_MASK 0x00000001L 14761#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1_MASK 0x00000002L 14762#define TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A_MASK 0x00000004L 14763//TCP_CNTL2 14764#define TCP_CNTL2__LS_DISABLE_CLOCKS__SHIFT 0x0 14765#define TCP_CNTL2__LS_DISABLE_CLOCKS_MASK 0x000000FFL 14766//TCP_UTCL1_CNTL1 14767#define TCP_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 14768#define TCP_UTCL1_CNTL1__GPUVM_64K_DEFAULT__SHIFT 0x1 14769#define TCP_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 14770#define TCP_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3 14771#define TCP_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 14772#define TCP_UTCL1_CNTL1__CLIENTID__SHIFT 0x7 14773#define TCP_UTCL1_CNTL1__REG_INV_VMID__SHIFT 0x13 14774#define TCP_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17 14775#define TCP_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT 0x18 14776#define TCP_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19 14777#define TCP_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a 14778#define TCP_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c 14779#define TCP_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e 14780#define TCP_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L 14781#define TCP_UTCL1_CNTL1__GPUVM_64K_DEFAULT_MASK 0x00000002L 14782#define TCP_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L 14783#define TCP_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L 14784#define TCP_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L 14785#define TCP_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L 14786#define TCP_UTCL1_CNTL1__REG_INV_VMID_MASK 0x00780000L 14787#define TCP_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L 14788#define TCP_UTCL1_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L 14789#define TCP_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L 14790#define TCP_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L 14791#define TCP_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L 14792#define TCP_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L 14793//TCP_UTCL1_CNTL2 14794#define TCP_UTCL1_CNTL2__SPARE__SHIFT 0x0 14795#define TCP_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 14796#define TCP_UTCL1_CNTL2__ANY_LINE_VALID__SHIFT 0xa 14797#define TCP_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc 14798#define TCP_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe 14799#define TCP_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf 14800#define TCP_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a 14801#define TCP_UTCL1_CNTL2__SPARE_MASK 0x000000FFL 14802#define TCP_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L 14803#define TCP_UTCL1_CNTL2__ANY_LINE_VALID_MASK 0x00000400L 14804#define TCP_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L 14805#define TCP_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L 14806#define TCP_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L 14807#define TCP_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L 14808//TCP_UTCL1_STATUS 14809#define TCP_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 14810#define TCP_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 14811#define TCP_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 14812#define TCP_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L 14813#define TCP_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L 14814#define TCP_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L 14815//TCP_PERFCOUNTER_FILTER 14816#define TCP_PERFCOUNTER_FILTER__BUFFER__SHIFT 0x0 14817#define TCP_PERFCOUNTER_FILTER__FLAT__SHIFT 0x1 14818#define TCP_PERFCOUNTER_FILTER__DIM__SHIFT 0x2 14819#define TCP_PERFCOUNTER_FILTER__DATA_FORMAT__SHIFT 0x5 14820#define TCP_PERFCOUNTER_FILTER__NUM_FORMAT__SHIFT 0xb 14821#define TCP_PERFCOUNTER_FILTER__SW_MODE__SHIFT 0xf 14822#define TCP_PERFCOUNTER_FILTER__NUM_SAMPLES__SHIFT 0x14 14823#define TCP_PERFCOUNTER_FILTER__OPCODE_TYPE__SHIFT 0x16 14824#define TCP_PERFCOUNTER_FILTER__GLC__SHIFT 0x19 14825#define TCP_PERFCOUNTER_FILTER__SLC__SHIFT 0x1a 14826#define TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE__SHIFT 0x1b 14827#define TCP_PERFCOUNTER_FILTER__ADDR_MODE__SHIFT 0x1c 14828#define TCP_PERFCOUNTER_FILTER__BUFFER_MASK 0x00000001L 14829#define TCP_PERFCOUNTER_FILTER__FLAT_MASK 0x00000002L 14830#define TCP_PERFCOUNTER_FILTER__DIM_MASK 0x0000001CL 14831#define TCP_PERFCOUNTER_FILTER__DATA_FORMAT_MASK 0x000007E0L 14832#define TCP_PERFCOUNTER_FILTER__NUM_FORMAT_MASK 0x00007800L 14833#define TCP_PERFCOUNTER_FILTER__SW_MODE_MASK 0x000F8000L 14834#define TCP_PERFCOUNTER_FILTER__NUM_SAMPLES_MASK 0x00300000L 14835#define TCP_PERFCOUNTER_FILTER__OPCODE_TYPE_MASK 0x01C00000L 14836#define TCP_PERFCOUNTER_FILTER__GLC_MASK 0x02000000L 14837#define TCP_PERFCOUNTER_FILTER__SLC_MASK 0x04000000L 14838#define TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE_MASK 0x08000000L 14839#define TCP_PERFCOUNTER_FILTER__ADDR_MODE_MASK 0x70000000L 14840//TCP_PERFCOUNTER_FILTER_EN 14841#define TCP_PERFCOUNTER_FILTER_EN__BUFFER__SHIFT 0x0 14842#define TCP_PERFCOUNTER_FILTER_EN__FLAT__SHIFT 0x1 14843#define TCP_PERFCOUNTER_FILTER_EN__DIM__SHIFT 0x2 14844#define TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT__SHIFT 0x3 14845#define TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT__SHIFT 0x4 14846#define TCP_PERFCOUNTER_FILTER_EN__SW_MODE__SHIFT 0x5 14847#define TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES__SHIFT 0x6 14848#define TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE__SHIFT 0x7 14849#define TCP_PERFCOUNTER_FILTER_EN__GLC__SHIFT 0x8 14850#define TCP_PERFCOUNTER_FILTER_EN__SLC__SHIFT 0x9 14851#define TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE__SHIFT 0xa 14852#define TCP_PERFCOUNTER_FILTER_EN__ADDR_MODE__SHIFT 0xb 14853#define TCP_PERFCOUNTER_FILTER_EN__BUFFER_MASK 0x00000001L 14854#define TCP_PERFCOUNTER_FILTER_EN__FLAT_MASK 0x00000002L 14855#define TCP_PERFCOUNTER_FILTER_EN__DIM_MASK 0x00000004L 14856#define TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT_MASK 0x00000008L 14857#define TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT_MASK 0x00000010L 14858#define TCP_PERFCOUNTER_FILTER_EN__SW_MODE_MASK 0x00000020L 14859#define TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES_MASK 0x00000040L 14860#define TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE_MASK 0x00000080L 14861#define TCP_PERFCOUNTER_FILTER_EN__GLC_MASK 0x00000100L 14862#define TCP_PERFCOUNTER_FILTER_EN__SLC_MASK 0x00000200L 14863#define TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE_MASK 0x00000400L 14864#define TCP_PERFCOUNTER_FILTER_EN__ADDR_MODE_MASK 0x00000800L 14865 14866 14867// addressBlock: gc_gdspdec 14868//GDS_VMID0_BASE 14869#define GDS_VMID0_BASE__BASE__SHIFT 0x0 14870#define GDS_VMID0_BASE__BASE_MASK 0x0000FFFFL 14871//GDS_VMID0_SIZE 14872#define GDS_VMID0_SIZE__SIZE__SHIFT 0x0 14873#define GDS_VMID0_SIZE__SIZE_MASK 0x0001FFFFL 14874//GDS_VMID1_BASE 14875#define GDS_VMID1_BASE__BASE__SHIFT 0x0 14876#define GDS_VMID1_BASE__BASE_MASK 0x0000FFFFL 14877//GDS_VMID1_SIZE 14878#define GDS_VMID1_SIZE__SIZE__SHIFT 0x0 14879#define GDS_VMID1_SIZE__SIZE_MASK 0x0001FFFFL 14880//GDS_VMID2_BASE 14881#define GDS_VMID2_BASE__BASE__SHIFT 0x0 14882#define GDS_VMID2_BASE__BASE_MASK 0x0000FFFFL 14883//GDS_VMID2_SIZE 14884#define GDS_VMID2_SIZE__SIZE__SHIFT 0x0 14885#define GDS_VMID2_SIZE__SIZE_MASK 0x0001FFFFL 14886//GDS_VMID3_BASE 14887#define GDS_VMID3_BASE__BASE__SHIFT 0x0 14888#define GDS_VMID3_BASE__BASE_MASK 0x0000FFFFL 14889//GDS_VMID3_SIZE 14890#define GDS_VMID3_SIZE__SIZE__SHIFT 0x0 14891#define GDS_VMID3_SIZE__SIZE_MASK 0x0001FFFFL 14892//GDS_VMID4_BASE 14893#define GDS_VMID4_BASE__BASE__SHIFT 0x0 14894#define GDS_VMID4_BASE__BASE_MASK 0x0000FFFFL 14895//GDS_VMID4_SIZE 14896#define GDS_VMID4_SIZE__SIZE__SHIFT 0x0 14897#define GDS_VMID4_SIZE__SIZE_MASK 0x0001FFFFL 14898//GDS_VMID5_BASE 14899#define GDS_VMID5_BASE__BASE__SHIFT 0x0 14900#define GDS_VMID5_BASE__BASE_MASK 0x0000FFFFL 14901//GDS_VMID5_SIZE 14902#define GDS_VMID5_SIZE__SIZE__SHIFT 0x0 14903#define GDS_VMID5_SIZE__SIZE_MASK 0x0001FFFFL 14904//GDS_VMID6_BASE 14905#define GDS_VMID6_BASE__BASE__SHIFT 0x0 14906#define GDS_VMID6_BASE__BASE_MASK 0x0000FFFFL 14907//GDS_VMID6_SIZE 14908#define GDS_VMID6_SIZE__SIZE__SHIFT 0x0 14909#define GDS_VMID6_SIZE__SIZE_MASK 0x0001FFFFL 14910//GDS_VMID7_BASE 14911#define GDS_VMID7_BASE__BASE__SHIFT 0x0 14912#define GDS_VMID7_BASE__BASE_MASK 0x0000FFFFL 14913//GDS_VMID7_SIZE 14914#define GDS_VMID7_SIZE__SIZE__SHIFT 0x0 14915#define GDS_VMID7_SIZE__SIZE_MASK 0x0001FFFFL 14916//GDS_VMID8_BASE 14917#define GDS_VMID8_BASE__BASE__SHIFT 0x0 14918#define GDS_VMID8_BASE__BASE_MASK 0x0000FFFFL 14919//GDS_VMID8_SIZE 14920#define GDS_VMID8_SIZE__SIZE__SHIFT 0x0 14921#define GDS_VMID8_SIZE__SIZE_MASK 0x0001FFFFL 14922//GDS_VMID9_BASE 14923#define GDS_VMID9_BASE__BASE__SHIFT 0x0 14924#define GDS_VMID9_BASE__BASE_MASK 0x0000FFFFL 14925//GDS_VMID9_SIZE 14926#define GDS_VMID9_SIZE__SIZE__SHIFT 0x0 14927#define GDS_VMID9_SIZE__SIZE_MASK 0x0001FFFFL 14928//GDS_VMID10_BASE 14929#define GDS_VMID10_BASE__BASE__SHIFT 0x0 14930#define GDS_VMID10_BASE__BASE_MASK 0x0000FFFFL 14931//GDS_VMID10_SIZE 14932#define GDS_VMID10_SIZE__SIZE__SHIFT 0x0 14933#define GDS_VMID10_SIZE__SIZE_MASK 0x0001FFFFL 14934//GDS_VMID11_BASE 14935#define GDS_VMID11_BASE__BASE__SHIFT 0x0 14936#define GDS_VMID11_BASE__BASE_MASK 0x0000FFFFL 14937//GDS_VMID11_SIZE 14938#define GDS_VMID11_SIZE__SIZE__SHIFT 0x0 14939#define GDS_VMID11_SIZE__SIZE_MASK 0x0001FFFFL 14940//GDS_VMID12_BASE 14941#define GDS_VMID12_BASE__BASE__SHIFT 0x0 14942#define GDS_VMID12_BASE__BASE_MASK 0x0000FFFFL 14943//GDS_VMID12_SIZE 14944#define GDS_VMID12_SIZE__SIZE__SHIFT 0x0 14945#define GDS_VMID12_SIZE__SIZE_MASK 0x0001FFFFL 14946//GDS_VMID13_BASE 14947#define GDS_VMID13_BASE__BASE__SHIFT 0x0 14948#define GDS_VMID13_BASE__BASE_MASK 0x0000FFFFL 14949//GDS_VMID13_SIZE 14950#define GDS_VMID13_SIZE__SIZE__SHIFT 0x0 14951#define GDS_VMID13_SIZE__SIZE_MASK 0x0001FFFFL 14952//GDS_VMID14_BASE 14953#define GDS_VMID14_BASE__BASE__SHIFT 0x0 14954#define GDS_VMID14_BASE__BASE_MASK 0x0000FFFFL 14955//GDS_VMID14_SIZE 14956#define GDS_VMID14_SIZE__SIZE__SHIFT 0x0 14957#define GDS_VMID14_SIZE__SIZE_MASK 0x0001FFFFL 14958//GDS_VMID15_BASE 14959#define GDS_VMID15_BASE__BASE__SHIFT 0x0 14960#define GDS_VMID15_BASE__BASE_MASK 0x0000FFFFL 14961//GDS_VMID15_SIZE 14962#define GDS_VMID15_SIZE__SIZE__SHIFT 0x0 14963#define GDS_VMID15_SIZE__SIZE_MASK 0x0001FFFFL 14964//GDS_GWS_VMID0 14965#define GDS_GWS_VMID0__BASE__SHIFT 0x0 14966#define GDS_GWS_VMID0__SIZE__SHIFT 0x10 14967#define GDS_GWS_VMID0__BASE_MASK 0x0000003FL 14968#define GDS_GWS_VMID0__SIZE_MASK 0x007F0000L 14969//GDS_GWS_VMID1 14970#define GDS_GWS_VMID1__BASE__SHIFT 0x0 14971#define GDS_GWS_VMID1__SIZE__SHIFT 0x10 14972#define GDS_GWS_VMID1__BASE_MASK 0x0000003FL 14973#define GDS_GWS_VMID1__SIZE_MASK 0x007F0000L 14974//GDS_GWS_VMID2 14975#define GDS_GWS_VMID2__BASE__SHIFT 0x0 14976#define GDS_GWS_VMID2__SIZE__SHIFT 0x10 14977#define GDS_GWS_VMID2__BASE_MASK 0x0000003FL 14978#define GDS_GWS_VMID2__SIZE_MASK 0x007F0000L 14979//GDS_GWS_VMID3 14980#define GDS_GWS_VMID3__BASE__SHIFT 0x0 14981#define GDS_GWS_VMID3__SIZE__SHIFT 0x10 14982#define GDS_GWS_VMID3__BASE_MASK 0x0000003FL 14983#define GDS_GWS_VMID3__SIZE_MASK 0x007F0000L 14984//GDS_GWS_VMID4 14985#define GDS_GWS_VMID4__BASE__SHIFT 0x0 14986#define GDS_GWS_VMID4__SIZE__SHIFT 0x10 14987#define GDS_GWS_VMID4__BASE_MASK 0x0000003FL 14988#define GDS_GWS_VMID4__SIZE_MASK 0x007F0000L 14989//GDS_GWS_VMID5 14990#define GDS_GWS_VMID5__BASE__SHIFT 0x0 14991#define GDS_GWS_VMID5__SIZE__SHIFT 0x10 14992#define GDS_GWS_VMID5__BASE_MASK 0x0000003FL 14993#define GDS_GWS_VMID5__SIZE_MASK 0x007F0000L 14994//GDS_GWS_VMID6 14995#define GDS_GWS_VMID6__BASE__SHIFT 0x0 14996#define GDS_GWS_VMID6__SIZE__SHIFT 0x10 14997#define GDS_GWS_VMID6__BASE_MASK 0x0000003FL 14998#define GDS_GWS_VMID6__SIZE_MASK 0x007F0000L 14999//GDS_GWS_VMID7 15000#define GDS_GWS_VMID7__BASE__SHIFT 0x0
15001#define GDS_GWS_VMID7__SIZE__SHIFT 0x10 15002#define GDS_GWS_VMID7__BASE_MASK 0x0000003FL 15003#define GDS_GWS_VMID7__SIZE_MASK 0x007F0000L 15004//GDS_GWS_VMID8 15005#define GDS_GWS_VMID8__BASE__SHIFT 0x0 15006#define GDS_GWS_VMID8__SIZE__SHIFT 0x10 15007#define GDS_GWS_VMID8__BASE_MASK 0x0000003FL 15008#define GDS_GWS_VMID8__SIZE_MASK 0x007F0000L 15009//GDS_GWS_VMID9 15010#define GDS_GWS_VMID9__BASE__SHIFT 0x0 15011#define GDS_GWS_VMID9__SIZE__SHIFT 0x10 15012#define GDS_GWS_VMID9__BASE_MASK 0x0000003FL 15013#define GDS_GWS_VMID9__SIZE_MASK 0x007F0000L 15014//GDS_GWS_VMID10 15015#define GDS_GWS_VMID10__BASE__SHIFT 0x0 15016#define GDS_GWS_VMID10__SIZE__SHIFT 0x10 15017#define GDS_GWS_VMID10__BASE_MASK 0x0000003FL 15018#define GDS_GWS_VMID10__SIZE_MASK 0x007F0000L 15019//GDS_GWS_VMID11 15020#define GDS_GWS_VMID11__BASE__SHIFT 0x0 15021#define GDS_GWS_VMID11__SIZE__SHIFT 0x10 15022#define GDS_GWS_VMID11__BASE_MASK 0x0000003FL 15023#define GDS_GWS_VMID11__SIZE_MASK 0x007F0000L 15024//GDS_GWS_VMID12 15025#define GDS_GWS_VMID12__BASE__SHIFT 0x0 15026#define GDS_GWS_VMID12__SIZE__SHIFT 0x10 15027#define GDS_GWS_VMID12__BASE_MASK 0x0000003FL 15028#define GDS_GWS_VMID12__SIZE_MASK 0x007F0000L 15029//GDS_GWS_VMID13 15030#define GDS_GWS_VMID13__BASE__SHIFT 0x0 15031#define GDS_GWS_VMID13__SIZE__SHIFT 0x10 15032#define GDS_GWS_VMID13__BASE_MASK 0x0000003FL 15033#define GDS_GWS_VMID13__SIZE_MASK 0x007F0000L 15034//GDS_GWS_VMID14 15035#define GDS_GWS_VMID14__BASE__SHIFT 0x0 15036#define GDS_GWS_VMID14__SIZE__SHIFT 0x10 15037#define GDS_GWS_VMID14__BASE_MASK 0x0000003FL 15038#define GDS_GWS_VMID14__SIZE_MASK 0x007F0000L 15039//GDS_GWS_VMID15 15040#define GDS_GWS_VMID15__BASE__SHIFT 0x0 15041#define GDS_GWS_VMID15__SIZE__SHIFT 0x10 15042#define GDS_GWS_VMID15__BASE_MASK 0x0000003FL 15043#define GDS_GWS_VMID15__SIZE_MASK 0x007F0000L 15044//GDS_OA_VMID0 15045#define GDS_OA_VMID0__MASK__SHIFT 0x0 15046#define GDS_OA_VMID0__UNUSED__SHIFT 0x10 15047#define GDS_OA_VMID0__MASK_MASK 0x0000FFFFL 15048#define GDS_OA_VMID0__UNUSED_MASK 0xFFFF0000L 15049//GDS_OA_VMID1 15050#define GDS_OA_VMID1__MASK__SHIFT 0x0 15051#define GDS_OA_VMID1__UNUSED__SHIFT 0x10 15052#define GDS_OA_VMID1__MASK_MASK 0x0000FFFFL 15053#define GDS_OA_VMID1__UNUSED_MASK 0xFFFF0000L 15054//GDS_OA_VMID2 15055#define GDS_OA_VMID2__MASK__SHIFT 0x0 15056#define GDS_OA_VMID2__UNUSED__SHIFT 0x10 15057#define GDS_OA_VMID2__MASK_MASK 0x0000FFFFL 15058#define GDS_OA_VMID2__UNUSED_MASK 0xFFFF0000L 15059//GDS_OA_VMID3 15060#define GDS_OA_VMID3__MASK__SHIFT 0x0 15061#define GDS_OA_VMID3__UNUSED__SHIFT 0x10 15062#define GDS_OA_VMID3__MASK_MASK 0x0000FFFFL 15063#define GDS_OA_VMID3__UNUSED_MASK 0xFFFF0000L 15064//GDS_OA_VMID4 15065#define GDS_OA_VMID4__MASK__SHIFT 0x0 15066#define GDS_OA_VMID4__UNUSED__SHIFT 0x10 15067#define GDS_OA_VMID4__MASK_MASK 0x0000FFFFL 15068#define GDS_OA_VMID4__UNUSED_MASK 0xFFFF0000L 15069//GDS_OA_VMID5 15070#define GDS_OA_VMID5__MASK__SHIFT 0x0 15071#define GDS_OA_VMID5__UNUSED__SHIFT 0x10 15072#define GDS_OA_VMID5__MASK_MASK 0x0000FFFFL 15073#define GDS_OA_VMID5__UNUSED_MASK 0xFFFF0000L 15074//GDS_OA_VMID6 15075#define GDS_OA_VMID6__MASK__SHIFT 0x0 15076#define GDS_OA_VMID6__UNUSED__SHIFT 0x10 15077#define GDS_OA_VMID6__MASK_MASK 0x0000FFFFL 15078#define GDS_OA_VMID6__UNUSED_MASK 0xFFFF0000L 15079//GDS_OA_VMID7 15080#define GDS_OA_VMID7__MASK__SHIFT 0x0 15081#define GDS_OA_VMID7__UNUSED__SHIFT 0x10 15082#define GDS_OA_VMID7__MASK_MASK 0x0000FFFFL 15083#define GDS_OA_VMID7__UNUSED_MASK 0xFFFF0000L 15084//GDS_OA_VMID8 15085#define GDS_OA_VMID8__MASK__SHIFT 0x0 15086#define GDS_OA_VMID8__UNUSED__SHIFT 0x10 15087#define GDS_OA_VMID8__MASK_MASK 0x0000FFFFL 15088#define GDS_OA_VMID8__UNUSED_MASK 0xFFFF0000L 15089//GDS_OA_VMID9 15090#define GDS_OA_VMID9__MASK__SHIFT 0x0 15091#define GDS_OA_VMID9__UNUSED__SHIFT 0x10 15092#define GDS_OA_VMID9__MASK_MASK 0x0000FFFFL 15093#define GDS_OA_VMID9__UNUSED_MASK 0xFFFF0000L 15094//GDS_OA_VMID10 15095#define GDS_OA_VMID10__MASK__SHIFT 0x0 15096#define GDS_OA_VMID10__UNUSED__SHIFT 0x10 15097#define GDS_OA_VMID10__MASK_MASK 0x0000FFFFL 15098#define GDS_OA_VMID10__UNUSED_MASK 0xFFFF0000L 15099//GDS_OA_VMID11 15100#define GDS_OA_VMID11__MASK__SHIFT 0x0 15101#define GDS_OA_VMID11__UNUSED__SHIFT 0x10 15102#define GDS_OA_VMID11__MASK_MASK 0x0000FFFFL 15103#define GDS_OA_VMID11__UNUSED_MASK 0xFFFF0000L 15104//GDS_OA_VMID12 15105#define GDS_OA_VMID12__MASK__SHIFT 0x0 15106#define GDS_OA_VMID12__UNUSED__SHIFT 0x10 15107#define GDS_OA_VMID12__MASK_MASK 0x0000FFFFL 15108#define GDS_OA_VMID12__UNUSED_MASK 0xFFFF0000L 15109//GDS_OA_VMID13 15110#define GDS_OA_VMID13__MASK__SHIFT 0x0 15111#define GDS_OA_VMID13__UNUSED__SHIFT 0x10 15112#define GDS_OA_VMID13__MASK_MASK 0x0000FFFFL 15113#define GDS_OA_VMID13__UNUSED_MASK 0xFFFF0000L 15114//GDS_OA_VMID14 15115#define GDS_OA_VMID14__MASK__SHIFT 0x0 15116#define GDS_OA_VMID14__UNUSED__SHIFT 0x10 15117#define GDS_OA_VMID14__MASK_MASK 0x0000FFFFL 15118#define GDS_OA_VMID14__UNUSED_MASK 0xFFFF0000L 15119//GDS_OA_VMID15 15120#define GDS_OA_VMID15__MASK__SHIFT 0x0 15121#define GDS_OA_VMID15__UNUSED__SHIFT 0x10 15122#define GDS_OA_VMID15__MASK_MASK 0x0000FFFFL 15123#define GDS_OA_VMID15__UNUSED_MASK 0xFFFF0000L 15124//GDS_GWS_RESET0 15125#define GDS_GWS_RESET0__RESOURCE0_RESET__SHIFT 0x0 15126#define GDS_GWS_RESET0__RESOURCE1_RESET__SHIFT 0x1 15127#define GDS_GWS_RESET0__RESOURCE2_RESET__SHIFT 0x2 15128#define GDS_GWS_RESET0__RESOURCE3_RESET__SHIFT 0x3 15129#define GDS_GWS_RESET0__RESOURCE4_RESET__SHIFT 0x4 15130#define GDS_GWS_RESET0__RESOURCE5_RESET__SHIFT 0x5 15131#define GDS_GWS_RESET0__RESOURCE6_RESET__SHIFT 0x6 15132#define GDS_GWS_RESET0__RESOURCE7_RESET__SHIFT 0x7 15133#define GDS_GWS_RESET0__RESOURCE8_RESET__SHIFT 0x8 15134#define GDS_GWS_RESET0__RESOURCE9_RESET__SHIFT 0x9 15135#define GDS_GWS_RESET0__RESOURCE10_RESET__SHIFT 0xa 15136#define GDS_GWS_RESET0__RESOURCE11_RESET__SHIFT 0xb 15137#define GDS_GWS_RESET0__RESOURCE12_RESET__SHIFT 0xc 15138#define GDS_GWS_RESET0__RESOURCE13_RESET__SHIFT 0xd 15139#define GDS_GWS_RESET0__RESOURCE14_RESET__SHIFT 0xe 15140#define GDS_GWS_RESET0__RESOURCE15_RESET__SHIFT 0xf 15141#define GDS_GWS_RESET0__RESOURCE16_RESET__SHIFT 0x10 15142#define GDS_GWS_RESET0__RESOURCE17_RESET__SHIFT 0x11 15143#define GDS_GWS_RESET0__RESOURCE18_RESET__SHIFT 0x12 15144#define GDS_GWS_RESET0__RESOURCE19_RESET__SHIFT 0x13 15145#define GDS_GWS_RESET0__RESOURCE20_RESET__SHIFT 0x14 15146#define GDS_GWS_RESET0__RESOURCE21_RESET__SHIFT 0x15 15147#define GDS_GWS_RESET0__RESOURCE22_RESET__SHIFT 0x16 15148#define GDS_GWS_RESET0__RESOURCE23_RESET__SHIFT 0x17 15149#define GDS_GWS_RESET0__RESOURCE24_RESET__SHIFT 0x18 15150#define GDS_GWS_RESET0__RESOURCE25_RESET__SHIFT 0x19 15151#define GDS_GWS_RESET0__RESOURCE26_RESET__SHIFT 0x1a 15152#define GDS_GWS_RESET0__RESOURCE27_RESET__SHIFT 0x1b 15153#define GDS_GWS_RESET0__RESOURCE28_RESET__SHIFT 0x1c 15154#define GDS_GWS_RESET0__RESOURCE29_RESET__SHIFT 0x1d 15155#define GDS_GWS_RESET0__RESOURCE30_RESET__SHIFT 0x1e 15156#define GDS_GWS_RESET0__RESOURCE31_RESET__SHIFT 0x1f 15157#define GDS_GWS_RESET0__RESOURCE0_RESET_MASK 0x00000001L 15158#define GDS_GWS_RESET0__RESOURCE1_RESET_MASK 0x00000002L 15159#define GDS_GWS_RESET0__RESOURCE2_RESET_MASK 0x00000004L 15160#define GDS_GWS_RESET0__RESOURCE3_RESET_MASK 0x00000008L 15161#define GDS_GWS_RESET0__RESOURCE4_RESET_MASK 0x00000010L 15162#define GDS_GWS_RESET0__RESOURCE5_RESET_MASK 0x00000020L 15163#define GDS_GWS_RESET0__RESOURCE6_RESET_MASK 0x00000040L 15164#define GDS_GWS_RESET0__RESOURCE7_RESET_MASK 0x00000080L 15165#define GDS_GWS_RESET0__RESOURCE8_RESET_MASK 0x00000100L 15166#define GDS_GWS_RESET0__RESOURCE9_RESET_MASK 0x00000200L 15167#define GDS_GWS_RESET0__RESOURCE10_RESET_MASK 0x00000400L 15168#define GDS_GWS_RESET0__RESOURCE11_RESET_MASK 0x00000800L 15169#define GDS_GWS_RESET0__RESOURCE12_RESET_MASK 0x00001000L 15170#define GDS_GWS_RESET0__RESOURCE13_RESET_MASK 0x00002000L 15171#define GDS_GWS_RESET0__RESOURCE14_RESET_MASK 0x00004000L 15172#define GDS_GWS_RESET0__RESOURCE15_RESET_MASK 0x00008000L 15173#define GDS_GWS_RESET0__RESOURCE16_RESET_MASK 0x00010000L 15174#define GDS_GWS_RESET0__RESOURCE17_RESET_MASK 0x00020000L 15175#define GDS_GWS_RESET0__RESOURCE18_RESET_MASK 0x00040000L 15176#define GDS_GWS_RESET0__RESOURCE19_RESET_MASK 0x00080000L 15177#define GDS_GWS_RESET0__RESOURCE20_RESET_MASK 0x00100000L 15178#define GDS_GWS_RESET0__RESOURCE21_RESET_MASK 0x00200000L 15179#define GDS_GWS_RESET0__RESOURCE22_RESET_MASK 0x00400000L 15180#define GDS_GWS_RESET0__RESOURCE23_RESET_MASK 0x00800000L 15181#define GDS_GWS_RESET0__RESOURCE24_RESET_MASK 0x01000000L 15182#define GDS_GWS_RESET0__RESOURCE25_RESET_MASK 0x02000000L 15183#define GDS_GWS_RESET0__RESOURCE26_RESET_MASK 0x04000000L 15184#define GDS_GWS_RESET0__RESOURCE27_RESET_MASK 0x08000000L 15185#define GDS_GWS_RESET0__RESOURCE28_RESET_MASK 0x10000000L 15186#define GDS_GWS_RESET0__RESOURCE29_RESET_MASK 0x20000000L 15187#define GDS_GWS_RESET0__RESOURCE30_RESET_MASK 0x40000000L 15188#define GDS_GWS_RESET0__RESOURCE31_RESET_MASK 0x80000000L 15189//GDS_GWS_RESET1 15190#define GDS_GWS_RESET1__RESOURCE32_RESET__SHIFT 0x0 15191#define GDS_GWS_RESET1__RESOURCE33_RESET__SHIFT 0x1 15192#define GDS_GWS_RESET1__RESOURCE34_RESET__SHIFT 0x2 15193#define GDS_GWS_RESET1__RESOURCE35_RESET__SHIFT 0x3 15194#define GDS_GWS_RESET1__RESOURCE36_RESET__SHIFT 0x4 15195#define GDS_GWS_RESET1__RESOURCE37_RESET__SHIFT 0x5 15196#define GDS_GWS_RESET1__RESOURCE38_RESET__SHIFT 0x6 15197#define GDS_GWS_RESET1__RESOURCE39_RESET__SHIFT 0x7 15198#define GDS_GWS_RESET1__RESOURCE40_RESET__SHIFT 0x8 15199#define GDS_GWS_RESET1__RESOURCE41_RESET__SHIFT 0x9 15200#define GDS_GWS_RESET1__RESOURCE42_RESET__SHIFT 0xa 15201#define GDS_GWS_RESET1__RESOURCE43_RESET__SHIFT 0xb 15202#define GDS_GWS_RESET1__RESOURCE44_RESET__SHIFT 0xc 15203#define GDS_GWS_RESET1__RESOURCE45_RESET__SHIFT 0xd 15204#define GDS_GWS_RESET1__RESOURCE46_RESET__SHIFT 0xe 15205#define GDS_GWS_RESET1__RESOURCE47_RESET__SHIFT 0xf 15206#define GDS_GWS_RESET1__RESOURCE48_RESET__SHIFT 0x10 15207#define GDS_GWS_RESET1__RESOURCE49_RESET__SHIFT 0x11 15208#define GDS_GWS_RESET1__RESOURCE50_RESET__SHIFT 0x12 15209#define GDS_GWS_RESET1__RESOURCE51_RESET__SHIFT 0x13 15210#define GDS_GWS_RESET1__RESOURCE52_RESET__SHIFT 0x14 15211#define GDS_GWS_RESET1__RESOURCE53_RESET__SHIFT 0x15 15212#define GDS_GWS_RESET1__RESOURCE54_RESET__SHIFT 0x16 15213#define GDS_GWS_RESET1__RESOURCE55_RESET__SHIFT 0x17 15214#define GDS_GWS_RESET1__RESOURCE56_RESET__SHIFT 0x18 15215#define GDS_GWS_RESET1__RESOURCE57_RESET__SHIFT 0x19 15216#define GDS_GWS_RESET1__RESOURCE58_RESET__SHIFT 0x1a 15217#define GDS_GWS_RESET1__RESOURCE59_RESET__SHIFT 0x1b 15218#define GDS_GWS_RESET1__RESOURCE60_RESET__SHIFT 0x1c 15219#define GDS_GWS_RESET1__RESOURCE61_RESET__SHIFT 0x1d 15220#define GDS_GWS_RESET1__RESOURCE62_RESET__SHIFT 0x1e 15221#define GDS_GWS_RESET1__RESOURCE63_RESET__SHIFT 0x1f 15222#define GDS_GWS_RESET1__RESOURCE32_RESET_MASK 0x00000001L 15223#define GDS_GWS_RESET1__RESOURCE33_RESET_MASK 0x00000002L 15224#define GDS_GWS_RESET1__RESOURCE34_RESET_MASK 0x00000004L 15225#define GDS_GWS_RESET1__RESOURCE35_RESET_MASK 0x00000008L 15226#define GDS_GWS_RESET1__RESOURCE36_RESET_MASK 0x00000010L 15227#define GDS_GWS_RESET1__RESOURCE37_RESET_MASK 0x00000020L 15228#define GDS_GWS_RESET1__RESOURCE38_RESET_MASK 0x00000040L 15229#define GDS_GWS_RESET1__RESOURCE39_RESET_MASK 0x00000080L 15230#define GDS_GWS_RESET1__RESOURCE40_RESET_MASK 0x00000100L 15231#define GDS_GWS_RESET1__RESOURCE41_RESET_MASK 0x00000200L 15232#define GDS_GWS_RESET1__RESOURCE42_RESET_MASK 0x00000400L 15233#define GDS_GWS_RESET1__RESOURCE43_RESET_MASK 0x00000800L 15234#define GDS_GWS_RESET1__RESOURCE44_RESET_MASK 0x00001000L 15235#define GDS_GWS_RESET1__RESOURCE45_RESET_MASK 0x00002000L 15236#define GDS_GWS_RESET1__RESOURCE46_RESET_MASK 0x00004000L 15237#define GDS_GWS_RESET1__RESOURCE47_RESET_MASK 0x00008000L 15238#define GDS_GWS_RESET1__RESOURCE48_RESET_MASK 0x00010000L 15239#define GDS_GWS_RESET1__RESOURCE49_RESET_MASK 0x00020000L 15240#define GDS_GWS_RESET1__RESOURCE50_RESET_MASK 0x00040000L 15241#define GDS_GWS_RESET1__RESOURCE51_RESET_MASK 0x00080000L 15242#define GDS_GWS_RESET1__RESOURCE52_RESET_MASK 0x00100000L 15243#define GDS_GWS_RESET1__RESOURCE53_RESET_MASK 0x00200000L 15244#define GDS_GWS_RESET1__RESOURCE54_RESET_MASK 0x00400000L 15245#define GDS_GWS_RESET1__RESOURCE55_RESET_MASK 0x00800000L 15246#define GDS_GWS_RESET1__RESOURCE56_RESET_MASK 0x01000000L 15247#define GDS_GWS_RESET1__RESOURCE57_RESET_MASK 0x02000000L 15248#define GDS_GWS_RESET1__RESOURCE58_RESET_MASK 0x04000000L 15249#define GDS_GWS_RESET1__RESOURCE59_RESET_MASK 0x08000000L 15250#define GDS_GWS_RESET1__RESOURCE60_RESET_MASK 0x10000000L 15251#define GDS_GWS_RESET1__RESOURCE61_RESET_MASK 0x20000000L 15252#define GDS_GWS_RESET1__RESOURCE62_RESET_MASK 0x40000000L 15253#define GDS_GWS_RESET1__RESOURCE63_RESET_MASK 0x80000000L 15254//GDS_GWS_RESOURCE_RESET 15255#define GDS_GWS_RESOURCE_RESET__RESET__SHIFT 0x0 15256#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID__SHIFT 0x8 15257#define GDS_GWS_RESOURCE_RESET__RESET_MASK 0x00000001L 15258#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID_MASK 0x0000FF00L 15259//GDS_COMPUTE_MAX_WAVE_ID 15260#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 15261#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL 15262//GDS_OA_RESET_MASK 15263#define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET__SHIFT 0x0 15264#define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET__SHIFT 0x1 15265#define GDS_OA_RESET_MASK__ME0_CS_RESET__SHIFT 0x2 15266#define GDS_OA_RESET_MASK__ME0_GFXHP3D_GS_RESET__SHIFT 0x3 15267#define GDS_OA_RESET_MASK__ME1_PIPE0_RESET__SHIFT 0x4 15268#define GDS_OA_RESET_MASK__ME1_PIPE1_RESET__SHIFT 0x5 15269#define GDS_OA_RESET_MASK__ME1_PIPE2_RESET__SHIFT 0x6 15270#define GDS_OA_RESET_MASK__ME1_PIPE3_RESET__SHIFT 0x7 15271#define GDS_OA_RESET_MASK__ME2_PIPE0_RESET__SHIFT 0x8 15272#define GDS_OA_RESET_MASK__ME2_PIPE1_RESET__SHIFT 0x9 15273#define GDS_OA_RESET_MASK__ME2_PIPE2_RESET__SHIFT 0xa 15274#define GDS_OA_RESET_MASK__ME2_PIPE3_RESET__SHIFT 0xb 15275#define GDS_OA_RESET_MASK__UNUSED1__SHIFT 0xc 15276#define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET_MASK 0x00000001L 15277#define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET_MASK 0x00000002L 15278#define GDS_OA_RESET_MASK__ME0_CS_RESET_MASK 0x00000004L 15279#define GDS_OA_RESET_MASK__ME0_GFXHP3D_GS_RESET_MASK 0x00000008L 15280#define GDS_OA_RESET_MASK__ME1_PIPE0_RESET_MASK 0x00000010L 15281#define GDS_OA_RESET_MASK__ME1_PIPE1_RESET_MASK 0x00000020L 15282#define GDS_OA_RESET_MASK__ME1_PIPE2_RESET_MASK 0x00000040L 15283#define GDS_OA_RESET_MASK__ME1_PIPE3_RESET_MASK 0x00000080L 15284#define GDS_OA_RESET_MASK__ME2_PIPE0_RESET_MASK 0x00000100L 15285#define GDS_OA_RESET_MASK__ME2_PIPE1_RESET_MASK 0x00000200L 15286#define GDS_OA_RESET_MASK__ME2_PIPE2_RESET_MASK 0x00000400L 15287#define GDS_OA_RESET_MASK__ME2_PIPE3_RESET_MASK 0x00000800L 15288#define GDS_OA_RESET_MASK__UNUSED1_MASK 0xFFFFF000L 15289//GDS_OA_RESET 15290#define GDS_OA_RESET__RESET__SHIFT 0x0 15291#define GDS_OA_RESET__PIPE_ID__SHIFT 0x8 15292#define GDS_OA_RESET__RESET_MASK 0x00000001L 15293#define GDS_OA_RESET__PIPE_ID_MASK 0x0000FF00L 15294//GDS_ENHANCE 15295#define GDS_ENHANCE__MISC__SHIFT 0x0 15296#define GDS_ENHANCE__AUTO_INC_INDEX__SHIFT 0x10 15297#define GDS_ENHANCE__CGPG_RESTORE__SHIFT 0x11 15298#define GDS_ENHANCE__RD_BUF_TAG_MISS__SHIFT 0x12 15299#define GDS_ENHANCE__GDSA_PC_CGTS_DIS__SHIFT 0x13 15300#define GDS_ENHANCE__GDSO_PC_CGTS_DIS__SHIFT 0x14 15301#define GDS_ENHANCE__WD_GDS_CSB_OVERRIDE__SHIFT 0x15 15302#define GDS_ENHANCE__UNUSED__SHIFT 0x16 15303#define GDS_ENHANCE__MISC_MASK 0x0000FFFFL 15304#define GDS_ENHANCE__AUTO_INC_INDEX_MASK 0x00010000L 15305#define GDS_ENHANCE__CGPG_RESTORE_MASK 0x00020000L 15306#define GDS_ENHANCE__RD_BUF_TAG_MISS_MASK 0x00040000L 15307#define GDS_ENHANCE__GDSA_PC_CGTS_DIS_MASK 0x00080000L 15308#define GDS_ENHANCE__GDSO_PC_CGTS_DIS_MASK 0x00100000L 15309#define GDS_ENHANCE__WD_GDS_CSB_OVERRIDE_MASK 0x00200000L 15310#define GDS_ENHANCE__UNUSED_MASK 0xFFC00000L 15311//GDS_OA_CGPG_RESTORE 15312#define GDS_OA_CGPG_RESTORE__VMID__SHIFT 0x0 15313#define GDS_OA_CGPG_RESTORE__MEID__SHIFT 0x8 15314#define GDS_OA_CGPG_RESTORE__PIPEID__SHIFT 0xc 15315#define GDS_OA_CGPG_RESTORE__QUEUEID__SHIFT 0x10 15316#define GDS_OA_CGPG_RESTORE__UNUSED__SHIFT 0x14 15317#define GDS_OA_CGPG_RESTORE__VMID_MASK 0x000000FFL 15318#define GDS_OA_CGPG_RESTORE__MEID_MASK 0x00000F00L 15319#define GDS_OA_CGPG_RESTORE__PIPEID_MASK 0x0000F000L 15320#define GDS_OA_CGPG_RESTORE__QUEUEID_MASK 0x000F0000L 15321#define GDS_OA_CGPG_RESTORE__UNUSED_MASK 0xFFF00000L 15322//GDS_CS_CTXSW_STATUS 15323#define GDS_CS_CTXSW_STATUS__R__SHIFT 0x0 15324#define GDS_CS_CTXSW_STATUS__W__SHIFT 0x1 15325#define GDS_CS_CTXSW_STATUS__UNUSED__SHIFT 0x2 15326#define GDS_CS_CTXSW_STATUS__R_MASK 0x00000001L 15327#define GDS_CS_CTXSW_STATUS__W_MASK 0x00000002L 15328#define GDS_CS_CTXSW_STATUS__UNUSED_MASK 0xFFFFFFFCL 15329//GDS_CS_CTXSW_CNT0 15330#define GDS_CS_CTXSW_CNT0__UPDN__SHIFT 0x0 15331#define GDS_CS_CTXSW_CNT0__PTR__SHIFT 0x10 15332#define GDS_CS_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL 15333#define GDS_CS_CTXSW_CNT0__PTR_MASK 0xFFFF0000L 15334//GDS_CS_CTXSW_CNT1 15335#define GDS_CS_CTXSW_CNT1__UPDN__SHIFT 0x0 15336#define GDS_CS_CTXSW_CNT1__PTR__SHIFT 0x10 15337#define GDS_CS_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL 15338#define GDS_CS_CTXSW_CNT1__PTR_MASK 0xFFFF0000L 15339//GDS_CS_CTXSW_CNT2 15340#define GDS_CS_CTXSW_CNT2__UPDN__SHIFT 0x0 15341#define GDS_CS_CTXSW_CNT2__PTR__SHIFT 0x10 15342#define GDS_CS_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL 15343#define GDS_CS_CTXSW_CNT2__PTR_MASK 0xFFFF0000L 15344//GDS_CS_CTXSW_CNT3 15345#define GDS_CS_CTXSW_CNT3__UPDN__SHIFT 0x0 15346#define GDS_CS_CTXSW_CNT3__PTR__SHIFT 0x10 15347#define GDS_CS_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL 15348#define GDS_CS_CTXSW_CNT3__PTR_MASK 0xFFFF0000L 15349//GDS_GFX_CTXSW_STATUS 15350#define GDS_GFX_CTXSW_STATUS__R__SHIFT 0x0 15351#define GDS_GFX_CTXSW_STATUS__W__SHIFT 0x1 15352#define GDS_GFX_CTXSW_STATUS__UNUSED__SHIFT 0x2 15353#define GDS_GFX_CTXSW_STATUS__R_MASK 0x00000001L 15354#define GDS_GFX_CTXSW_STATUS__W_MASK 0x00000002L 15355#define GDS_GFX_CTXSW_STATUS__UNUSED_MASK 0xFFFFFFFCL 15356//GDS_VS_CTXSW_CNT0 15357#define GDS_VS_CTXSW_CNT0__UPDN__SHIFT 0x0 15358#define GDS_VS_CTXSW_CNT0__PTR__SHIFT 0x10 15359#define GDS_VS_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL 15360#define GDS_VS_CTXSW_CNT0__PTR_MASK 0xFFFF0000L 15361//GDS_VS_CTXSW_CNT1 15362#define GDS_VS_CTXSW_CNT1__UPDN__SHIFT 0x0 15363#define GDS_VS_CTXSW_CNT1__PTR__SHIFT 0x10 15364#define GDS_VS_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL 15365#define GDS_VS_CTXSW_CNT1__PTR_MASK 0xFFFF0000L 15366//GDS_VS_CTXSW_CNT2 15367#define GDS_VS_CTXSW_CNT2__UPDN__SHIFT 0x0 15368#define GDS_VS_CTXSW_CNT2__PTR__SHIFT 0x10 15369#define GDS_VS_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL 15370#define GDS_VS_CTXSW_CNT2__PTR_MASK 0xFFFF0000L 15371//GDS_VS_CTXSW_CNT3 15372#define GDS_VS_CTXSW_CNT3__UPDN__SHIFT 0x0 15373#define GDS_VS_CTXSW_CNT3__PTR__SHIFT 0x10 15374#define GDS_VS_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL 15375#define GDS_VS_CTXSW_CNT3__PTR_MASK 0xFFFF0000L 15376//GDS_PS0_CTXSW_CNT0 15377#define GDS_PS0_CTXSW_CNT0__UPDN__SHIFT 0x0 15378#define GDS_PS0_CTXSW_CNT0__PTR__SHIFT 0x10 15379#define GDS_PS0_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL 15380#define GDS_PS0_CTXSW_CNT0__PTR_MASK 0xFFFF0000L 15381//GDS_PS0_CTXSW_CNT1 15382#define GDS_PS0_CTXSW_CNT1__UPDN__SHIFT 0x0 15383#define GDS_PS0_CTXSW_CNT1__PTR__SHIFT 0x10 15384#define GDS_PS0_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL 15385#define GDS_PS0_CTXSW_CNT1__PTR_MASK 0xFFFF0000L 15386//GDS_PS0_CTXSW_CNT2 15387#define GDS_PS0_CTXSW_CNT2__UPDN__SHIFT 0x0 15388#define GDS_PS0_CTXSW_CNT2__PTR__SHIFT 0x10 15389#define GDS_PS0_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL 15390#define GDS_PS0_CTXSW_CNT2__PTR_MASK 0xFFFF0000L 15391//GDS_PS0_CTXSW_CNT3 15392#define GDS_PS0_CTXSW_CNT3__UPDN__SHIFT 0x0 15393#define GDS_PS0_CTXSW_CNT3__PTR__SHIFT 0x10 15394#define GDS_PS0_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL 15395#define GDS_PS0_CTXSW_CNT3__PTR_MASK 0xFFFF0000L 15396//GDS_PS1_CTXSW_CNT0 15397#define GDS_PS1_CTXSW_CNT0__UPDN__SHIFT 0x0 15398#define GDS_PS1_CTXSW_CNT0__PTR__SHIFT 0x10 15399#define GDS_PS1_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL 15400#define GDS_PS1_CTXSW_CNT0__PTR_MASK 0xFFFF0000L 15401//GDS_PS1_CTXSW_CNT1 15402#define GDS_PS1_CTXSW_CNT1__UPDN__SHIFT 0x0 15403#define GDS_PS1_CTXSW_CNT1__PTR__SHIFT 0x10 15404#define GDS_PS1_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL 15405#define GDS_PS1_CTXSW_CNT1__PTR_MASK 0xFFFF0000L 15406//GDS_PS1_CTXSW_CNT2 15407#define GDS_PS1_CTXSW_CNT2__UPDN__SHIFT 0x0 15408#define GDS_PS1_CTXSW_CNT2__PTR__SHIFT 0x10 15409#define GDS_PS1_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL 15410#define GDS_PS1_CTXSW_CNT2__PTR_MASK 0xFFFF0000L 15411//GDS_PS1_CTXSW_CNT3 15412#define GDS_PS1_CTXSW_CNT3__UPDN__SHIFT 0x0 15413#define GDS_PS1_CTXSW_CNT3__PTR__SHIFT 0x10 15414#define GDS_PS1_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL 15415#define GDS_PS1_CTXSW_CNT3__PTR_MASK 0xFFFF0000L 15416//GDS_PS2_CTXSW_CNT0 15417#define GDS_PS2_CTXSW_CNT0__UPDN__SHIFT 0x0 15418#define GDS_PS2_CTXSW_CNT0__PTR__SHIFT 0x10 15419#define GDS_PS2_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL 15420#define GDS_PS2_CTXSW_CNT0__PTR_MASK 0xFFFF0000L 15421//GDS_PS2_CTXSW_CNT1 15422#define GDS_PS2_CTXSW_CNT1__UPDN__SHIFT 0x0 15423#define GDS_PS2_CTXSW_CNT1__PTR__SHIFT 0x10 15424#define GDS_PS2_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL 15425#define GDS_PS2_CTXSW_CNT1__PTR_MASK 0xFFFF0000L 15426//GDS_PS2_CTXSW_CNT2 15427#define GDS_PS2_CTXSW_CNT2__UPDN__SHIFT 0x0 15428#define GDS_PS2_CTXSW_CNT2__PTR__SHIFT 0x10 15429#define GDS_PS2_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL 15430#define GDS_PS2_CTXSW_CNT2__PTR_MASK 0xFFFF0000L 15431//GDS_PS2_CTXSW_CNT3 15432#define GDS_PS2_CTXSW_CNT3__UPDN__SHIFT 0x0 15433#define GDS_PS2_CTXSW_CNT3__PTR__SHIFT 0x10 15434#define GDS_PS2_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL 15435#define GDS_PS2_CTXSW_CNT3__PTR_MASK 0xFFFF0000L 15436//GDS_PS3_CTXSW_CNT0 15437#define GDS_PS3_CTXSW_CNT0__UPDN__SHIFT 0x0 15438#define GDS_PS3_CTXSW_CNT0__PTR__SHIFT 0x10 15439#define GDS_PS3_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL 15440#define GDS_PS3_CTXSW_CNT0__PTR_MASK 0xFFFF0000L 15441//GDS_PS3_CTXSW_CNT1 15442#define GDS_PS3_CTXSW_CNT1__UPDN__SHIFT 0x0 15443#define GDS_PS3_CTXSW_CNT1__PTR__SHIFT 0x10 15444#define GDS_PS3_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL 15445#define GDS_PS3_CTXSW_CNT1__PTR_MASK 0xFFFF0000L 15446//GDS_PS3_CTXSW_CNT2 15447#define GDS_PS3_CTXSW_CNT2__UPDN__SHIFT 0x0 15448#define GDS_PS3_CTXSW_CNT2__PTR__SHIFT 0x10 15449#define GDS_PS3_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL 15450#define GDS_PS3_CTXSW_CNT2__PTR_MASK 0xFFFF0000L 15451//GDS_PS3_CTXSW_CNT3 15452#define GDS_PS3_CTXSW_CNT3__UPDN__SHIFT 0x0 15453#define GDS_PS3_CTXSW_CNT3__PTR__SHIFT 0x10 15454#define GDS_PS3_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL 15455#define GDS_PS3_CTXSW_CNT3__PTR_MASK 0xFFFF0000L 15456//GDS_PS4_CTXSW_CNT0 15457#define GDS_PS4_CTXSW_CNT0__UPDN__SHIFT 0x0 15458#define GDS_PS4_CTXSW_CNT0__PTR__SHIFT 0x10 15459#define GDS_PS4_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL 15460#define GDS_PS4_CTXSW_CNT0__PTR_MASK 0xFFFF0000L 15461//GDS_PS4_CTXSW_CNT1 15462#define GDS_PS4_CTXSW_CNT1__UPDN__SHIFT 0x0 15463#define GDS_PS4_CTXSW_CNT1__PTR__SHIFT 0x10 15464#define GDS_PS4_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL 15465#define GDS_PS4_CTXSW_CNT1__PTR_MASK 0xFFFF0000L 15466//GDS_PS4_CTXSW_CNT2 15467#define GDS_PS4_CTXSW_CNT2__UPDN__SHIFT 0x0 15468#define GDS_PS4_CTXSW_CNT2__PTR__SHIFT 0x10 15469#define GDS_PS4_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL 15470#define GDS_PS4_CTXSW_CNT2__PTR_MASK 0xFFFF0000L 15471//GDS_PS4_CTXSW_CNT3 15472#define GDS_PS4_CTXSW_CNT3__UPDN__SHIFT 0x0 15473#define GDS_PS4_CTXSW_CNT3__PTR__SHIFT 0x10 15474#define GDS_PS4_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL 15475#define GDS_PS4_CTXSW_CNT3__PTR_MASK 0xFFFF0000L 15476//GDS_PS5_CTXSW_CNT0 15477#define GDS_PS5_CTXSW_CNT0__UPDN__SHIFT 0x0 15478#define GDS_PS5_CTXSW_CNT0__PTR__SHIFT 0x10 15479#define GDS_PS5_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL 15480#define GDS_PS5_CTXSW_CNT0__PTR_MASK 0xFFFF0000L 15481//GDS_PS5_CTXSW_CNT1 15482#define GDS_PS5_CTXSW_CNT1__UPDN__SHIFT 0x0 15483#define GDS_PS5_CTXSW_CNT1__PTR__SHIFT 0x10 15484#define GDS_PS5_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL 15485#define GDS_PS5_CTXSW_CNT1__PTR_MASK 0xFFFF0000L 15486//GDS_PS5_CTXSW_CNT2 15487#define GDS_PS5_CTXSW_CNT2__UPDN__SHIFT 0x0 15488#define GDS_PS5_CTXSW_CNT2__PTR__SHIFT 0x10 15489#define GDS_PS5_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL 15490#define GDS_PS5_CTXSW_CNT2__PTR_MASK 0xFFFF0000L 15491//GDS_PS5_CTXSW_CNT3 15492#define GDS_PS5_CTXSW_CNT3__UPDN__SHIFT 0x0 15493#define GDS_PS5_CTXSW_CNT3__PTR__SHIFT 0x10 15494#define GDS_PS5_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL 15495#define GDS_PS5_CTXSW_CNT3__PTR_MASK 0xFFFF0000L 15496//GDS_PS6_CTXSW_CNT0 15497#define GDS_PS6_CTXSW_CNT0__UPDN__SHIFT 0x0 15498#define GDS_PS6_CTXSW_CNT0__PTR__SHIFT 0x10 15499#define GDS_PS6_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL 15500#define GDS_PS6_CTXSW_CNT0__PTR_MASK 0xFFFF0000L 15501//GDS_PS6_CTXSW_CNT1 15502#define GDS_PS6_CTXSW_CNT1__UPDN__SHIFT 0x0 15503#define GDS_PS6_CTXSW_CNT1__PTR__SHIFT 0x10 15504#define GDS_PS6_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL 15505#define GDS_PS6_CTXSW_CNT1__PTR_MASK 0xFFFF0000L 15506//GDS_PS6_CTXSW_CNT2 15507#define GDS_PS6_CTXSW_CNT2__UPDN__SHIFT 0x0 15508#define GDS_PS6_CTXSW_CNT2__PTR__SHIFT 0x10 15509#define GDS_PS6_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL 15510#define GDS_PS6_CTXSW_CNT2__PTR_MASK 0xFFFF0000L 15511//GDS_PS6_CTXSW_CNT3 15512#define GDS_PS6_CTXSW_CNT3__UPDN__SHIFT 0x0 15513#define GDS_PS6_CTXSW_CNT3__PTR__SHIFT 0x10 15514#define GDS_PS6_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL 15515#define GDS_PS6_CTXSW_CNT3__PTR_MASK 0xFFFF0000L 15516//GDS_PS7_CTXSW_CNT0 15517#define GDS_PS7_CTXSW_CNT0__UPDN__SHIFT 0x0 15518#define GDS_PS7_CTXSW_CNT0__PTR__SHIFT 0x10 15519#define GDS_PS7_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL 15520#define GDS_PS7_CTXSW_CNT0__PTR_MASK 0xFFFF0000L 15521//GDS_PS7_CTXSW_CNT1 15522#define GDS_PS7_CTXSW_CNT1__UPDN__SHIFT 0x0 15523#define GDS_PS7_CTXSW_CNT1__PTR__SHIFT 0x10 15524#define GDS_PS7_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL 15525#define GDS_PS7_CTXSW_CNT1__PTR_MASK 0xFFFF0000L 15526//GDS_PS7_CTXSW_CNT2 15527#define GDS_PS7_CTXSW_CNT2__UPDN__SHIFT 0x0 15528#define GDS_PS7_CTXSW_CNT2__PTR__SHIFT 0x10 15529#define GDS_PS7_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL 15530#define GDS_PS7_CTXSW_CNT2__PTR_MASK 0xFFFF0000L 15531//GDS_PS7_CTXSW_CNT3 15532#define GDS_PS7_CTXSW_CNT3__UPDN__SHIFT 0x0 15533#define GDS_PS7_CTXSW_CNT3__PTR__SHIFT 0x10 15534#define GDS_PS7_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL 15535#define GDS_PS7_CTXSW_CNT3__PTR_MASK 0xFFFF0000L 15536//GDS_GS_CTXSW_CNT0 15537#define GDS_GS_CTXSW_CNT0__UPDN__SHIFT 0x0 15538#define GDS_GS_CTXSW_CNT0__PTR__SHIFT 0x10 15539#define GDS_GS_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL 15540#define GDS_GS_CTXSW_CNT0__PTR_MASK 0xFFFF0000L 15541//GDS_GS_CTXSW_CNT1 15542#define GDS_GS_CTXSW_CNT1__UPDN__SHIFT 0x0 15543#define GDS_GS_CTXSW_CNT1__PTR__SHIFT 0x10 15544#define GDS_GS_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL 15545#define GDS_GS_CTXSW_CNT1__PTR_MASK 0xFFFF0000L 15546//GDS_GS_CTXSW_CNT2 15547#define GDS_GS_CTXSW_CNT2__UPDN__SHIFT 0x0 15548#define GDS_GS_CTXSW_CNT2__PTR__SHIFT 0x10 15549#define GDS_GS_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL 15550#define GDS_GS_CTXSW_CNT2__PTR_MASK 0xFFFF0000L 15551//GDS_GS_CTXSW_CNT3 15552#define GDS_GS_CTXSW_CNT3__UPDN__SHIFT 0x0 15553#define GDS_GS_CTXSW_CNT3__PTR__SHIFT 0x10 15554#define GDS_GS_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL 15555#define GDS_GS_CTXSW_CNT3__PTR_MASK 0xFFFF0000L 15556 15557 15558// addressBlock: gc_rasdec 15559//RAS_SIGNATURE_CONTROL 15560#define RAS_SIGNATURE_CONTROL__ENABLE__SHIFT 0x0 15561#define RAS_SIGNATURE_CONTROL__ENABLE_MASK 0x00000001L 15562//RAS_SIGNATURE_MASK 15563#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK__SHIFT 0x0 15564#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK_MASK 0xFFFFFFFFL 15565//RAS_SX_SIGNATURE0 15566#define RAS_SX_SIGNATURE0__SIGNATURE__SHIFT 0x0 15567#define RAS_SX_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL 15568//RAS_SX_SIGNATURE1 15569#define RAS_SX_SIGNATURE1__SIGNATURE__SHIFT 0x0 15570#define RAS_SX_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL 15571//RAS_SX_SIGNATURE2 15572#define RAS_SX_SIGNATURE2__SIGNATURE__SHIFT 0x0 15573#define RAS_SX_SIGNATURE2__SIGNATURE_MASK 0xFFFFFFFFL 15574//RAS_SX_SIGNATURE3 15575#define RAS_SX_SIGNATURE3__SIGNATURE__SHIFT 0x0 15576#define RAS_SX_SIGNATURE3__SIGNATURE_MASK 0xFFFFFFFFL 15577//RAS_DB_SIGNATURE0 15578#define RAS_DB_SIGNATURE0__SIGNATURE__SHIFT 0x0 15579#define RAS_DB_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL 15580//RAS_PA_SIGNATURE0 15581#define RAS_PA_SIGNATURE0__SIGNATURE__SHIFT 0x0 15582#define RAS_PA_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL 15583//RAS_VGT_SIGNATURE0 15584#define RAS_VGT_SIGNATURE0__SIGNATURE__SHIFT 0x0 15585#define RAS_VGT_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL 15586//RAS_SQ_SIGNATURE0 15587#define RAS_SQ_SIGNATURE0__SIGNATURE__SHIFT 0x0 15588#define RAS_SQ_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL 15589//RAS_SC_SIGNATURE0 15590#define RAS_SC_SIGNATURE0__SIGNATURE__SHIFT 0x0 15591#define RAS_SC_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL 15592//RAS_SC_SIGNATURE1 15593#define RAS_SC_SIGNATURE1__SIGNATURE__SHIFT 0x0 15594#define RAS_SC_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL 15595//RAS_SC_SIGNATURE2 15596#define RAS_SC_SIGNATURE2__SIGNATURE__SHIFT 0x0 15597#define RAS_SC_SIGNATURE2__SIGNATURE_MASK 0xFFFFFFFFL 15598//RAS_SC_SIGNATURE3 15599#define RAS_SC_SIGNATURE3__SIGNATURE__SHIFT 0x0 15600#define RAS_SC_SIGNATURE3__SIGNATURE_MASK 0xFFFFFFFFL 15601//RAS_SC_SIGNATURE4 15602#define RAS_SC_SIGNATURE4__SIGNATURE__SHIFT 0x0 15603#define RAS_SC_SIGNATURE4__SIGNATURE_MASK 0xFFFFFFFFL 15604//RAS_SC_SIGNATURE5 15605#define RAS_SC_SIGNATURE5__SIGNATURE__SHIFT 0x0 15606#define RAS_SC_SIGNATURE5__SIGNATURE_MASK 0xFFFFFFFFL 15607//RAS_SC_SIGNATURE6 15608#define RAS_SC_SIGNATURE6__SIGNATURE__SHIFT 0x0 15609#define RAS_SC_SIGNATURE6__SIGNATURE_MASK 0xFFFFFFFFL 15610//RAS_SC_SIGNATURE7 15611#define RAS_SC_SIGNATURE7__SIGNATURE__SHIFT 0x0 15612#define RAS_SC_SIGNATURE7__SIGNATURE_MASK 0xFFFFFFFFL 15613//RAS_IA_SIGNATURE0 15614#define RAS_IA_SIGNATURE0__SIGNATURE__SHIFT 0x0 15615#define RAS_IA_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL 15616//RAS_IA_SIGNATURE1 15617#define RAS_IA_SIGNATURE1__SIGNATURE__SHIFT 0x0 15618#define RAS_IA_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL 15619//RAS_SPI_SIGNATURE0 15620#define RAS_SPI_SIGNATURE0__SIGNATURE__SHIFT 0x0 15621#define RAS_SPI_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL 15622//RAS_SPI_SIGNATURE1 15623#define RAS_SPI_SIGNATURE1__SIGNATURE__SHIFT 0x0 15624#define RAS_SPI_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL 15625//RAS_TA_SIGNATURE0 15626#define RAS_TA_SIGNATURE0__SIGNATURE__SHIFT 0x0 15627#define RAS_TA_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL 15628//RAS_TD_SIGNATURE0 15629#define RAS_TD_SIGNATURE0__SIGNATURE__SHIFT 0x0 15630#define RAS_TD_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL 15631//RAS_CB_SIGNATURE0 15632#define RAS_CB_SIGNATURE0__SIGNATURE__SHIFT 0x0 15633#define RAS_CB_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL 15634//RAS_BCI_SIGNATURE0 15635#define RAS_BCI_SIGNATURE0__SIGNATURE__SHIFT 0x0 15636#define RAS_BCI_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL 15637//RAS_BCI_SIGNATURE1 15638#define RAS_BCI_SIGNATURE1__SIGNATURE__SHIFT 0x0 15639#define RAS_BCI_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL 15640//RAS_TA_SIGNATURE1 15641#define RAS_TA_SIGNATURE1__SIGNATURE__SHIFT 0x0 15642#define RAS_TA_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL 15643 15644 15645// addressBlock: gc_gfxdec0 15646//DB_RENDER_CONTROL 15647#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT 0x0 15648#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE__SHIFT 0x1 15649#define DB_RENDER_CONTROL__DEPTH_COPY__SHIFT 0x2 15650#define DB_RENDER_CONTROL__STENCIL_COPY__SHIFT 0x3 15651#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE__SHIFT 0x4 15652#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE__SHIFT 0x5 15653#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE__SHIFT 0x6 15654#define DB_RENDER_CONTROL__COPY_CENTROID__SHIFT 0x7 15655#define DB_RENDER_CONTROL__COPY_SAMPLE__SHIFT 0x8 15656#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE__SHIFT 0xc 15657#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE_MASK 0x00000001L 15658#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE_MASK 0x00000002L 15659#define DB_RENDER_CONTROL__DEPTH_COPY_MASK 0x00000004L 15660#define DB_RENDER_CONTROL__STENCIL_COPY_MASK 0x00000008L 15661#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE_MASK 0x00000010L 15662#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE_MASK 0x00000020L 15663#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE_MASK 0x00000040L 15664#define DB_RENDER_CONTROL__COPY_CENTROID_MASK 0x00000080L 15665#define DB_RENDER_CONTROL__COPY_SAMPLE_MASK 0x00000F00L 15666#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE_MASK 0x00001000L 15667//DB_COUNT_CONTROL 15668#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE__SHIFT 0x0 15669#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS__SHIFT 0x1 15670#define DB_COUNT_CONTROL__SAMPLE_RATE__SHIFT 0x4 15671#define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT 0x8 15672#define DB_COUNT_CONTROL__ZFAIL_ENABLE__SHIFT 0xc 15673#define DB_COUNT_CONTROL__SFAIL_ENABLE__SHIFT 0x10 15674#define DB_COUNT_CONTROL__DBFAIL_ENABLE__SHIFT 0x14 15675#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x18 15676#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x1c 15677#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE_MASK 0x00000001L 15678#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_MASK 0x00000002L 15679#define DB_COUNT_CONTROL__SAMPLE_RATE_MASK 0x00000070L 15680#define DB_COUNT_CONTROL__ZPASS_ENABLE_MASK 0x00000F00L 15681#define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK 0x0000F000L 15682#define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 0x000F0000L 15683#define DB_COUNT_CONTROL__DBFAIL_ENABLE_MASK 0x00F00000L 15684#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x0F000000L 15685#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE_MASK 0xF0000000L 15686//DB_DEPTH_VIEW 15687#define DB_DEPTH_VIEW__SLICE_START__SHIFT 0x0 15688#define DB_DEPTH_VIEW__SLICE_MAX__SHIFT 0xd 15689#define DB_DEPTH_VIEW__Z_READ_ONLY__SHIFT 0x18 15690#define DB_DEPTH_VIEW__STENCIL_READ_ONLY__SHIFT 0x19 15691#define DB_DEPTH_VIEW__MIPID__SHIFT 0x1a 15692#define DB_DEPTH_VIEW__SLICE_START_MASK 0x000007FFL 15693#define DB_DEPTH_VIEW__SLICE_MAX_MASK 0x00FFE000L 15694#define DB_DEPTH_VIEW__Z_READ_ONLY_MASK 0x01000000L 15695#define DB_DEPTH_VIEW__STENCIL_READ_ONLY_MASK 0x02000000L 15696#define DB_DEPTH_VIEW__MIPID_MASK 0x3C000000L 15697//DB_RENDER_OVERRIDE 15698#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE__SHIFT 0x0 15699#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0__SHIFT 0x2 15700#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1__SHIFT 0x4 15701#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER__SHIFT 0x6 15702#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE__SHIFT 0x7 15703#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE__SHIFT 0x8 15704#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE__SHIFT 0x9 15705#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT 0xa 15706#define DB_RENDER_OVERRIDE__FORCE_Z_READ__SHIFT 0xb 15707#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ__SHIFT 0xc 15708#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE__SHIFT 0xd 15709#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT__SHIFT 0xf 15710#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP__SHIFT 0x10 15711#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE__SHIFT 0x11 15712#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED__SHIFT 0x12 15713#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM__SHIFT 0x13 15714#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT__SHIFT 0x15 15715#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES__SHIFT 0x1a 15716#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY__SHIFT 0x1b 15717#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY__SHIFT 0x1c 15718#define DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT 0x1d 15719#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID__SHIFT 0x1e 15720#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION__SHIFT 0x1f 15721#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE_MASK 0x00000003L 15722#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0_MASK 0x0000000CL 15723#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1_MASK 0x00000030L 15724#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER_MASK 0x00000040L 15725#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE_MASK 0x00000080L 15726#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE_MASK 0x00000100L 15727#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE_MASK 0x00000200L 15728#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL_MASK 0x00000400L 15729#define DB_RENDER_OVERRIDE__FORCE_Z_READ_MASK 0x00000800L 15730#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ_MASK 0x00001000L 15731#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE_MASK 0x00006000L 15732#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT_MASK 0x00008000L 15733#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP_MASK 0x00010000L 15734#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE_MASK 0x00020000L 15735#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED_MASK 0x00040000L 15736#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM_MASK 0x00180000L 15737#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT_MASK 0x03E00000L 15738#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES_MASK 0x04000000L 15739#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY_MASK 0x08000000L 15740#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY_MASK 0x10000000L 15741#define DB_RENDER_OVERRIDE__FORCE_Z_VALID_MASK 0x20000000L 15742#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID_MASK 0x40000000L 15743#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION_MASK 0x80000000L 15744//DB_RENDER_OVERRIDE2 15745#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL__SHIFT 0x0 15746#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN__SHIFT 0x2 15747#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION__SHIFT 0x5 15748#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION__SHIFT 0x6 15749#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION__SHIFT 0x7 15750#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH__SHIFT 0x8 15751#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP__SHIFT 0x9 15752#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT 0xa 15753#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE__SHIFT 0xb 15754#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC__SHIFT 0xc 15755#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF__SHIFT 0xf 15756#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF__SHIFT 0x12 15757#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE__SHIFT 0x15 15758#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS__SHIFT 0x16 15759#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS__SHIFT 0x17 15760#define DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL__SHIFT 0x19 15761#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL_MASK 0x00000003L 15762#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN_MASK 0x0000001CL 15763#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION_MASK 0x00000020L 15764#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION_MASK 0x00000040L 15765#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION_MASK 0x00000080L 15766#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH_MASK 0x00000100L 15767#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP_MASK 0x00000200L 15768#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE_MASK 0x00000400L 15769#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE_MASK 0x00000800L 15770#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC_MASK 0x00007000L 15771#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF_MASK 0x00038000L 15772#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF_MASK 0x001C0000L 15773#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE_MASK 0x00200000L 15774#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS_MASK 0x00400000L 15775#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS_MASK 0x00800000L 15776#define DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL_MASK 0x02000000L 15777//DB_HTILE_DATA_BASE 15778#define DB_HTILE_DATA_BASE__BASE_256B__SHIFT 0x0 15779#define DB_HTILE_DATA_BASE__BASE_256B_MASK 0xFFFFFFFFL 15780//DB_HTILE_DATA_BASE_HI 15781#define DB_HTILE_DATA_BASE_HI__BASE_HI__SHIFT 0x0 15782#define DB_HTILE_DATA_BASE_HI__BASE_HI_MASK 0x000000FFL 15783//DB_DEPTH_SIZE 15784#define DB_DEPTH_SIZE__X_MAX__SHIFT 0x0 15785#define DB_DEPTH_SIZE__Y_MAX__SHIFT 0x10 15786#define DB_DEPTH_SIZE__X_MAX_MASK 0x00003FFFL 15787#define DB_DEPTH_SIZE__Y_MAX_MASK 0x3FFF0000L 15788//DB_DEPTH_BOUNDS_MIN 15789#define DB_DEPTH_BOUNDS_MIN__MIN__SHIFT 0x0 15790#define DB_DEPTH_BOUNDS_MIN__MIN_MASK 0xFFFFFFFFL 15791//DB_DEPTH_BOUNDS_MAX 15792#define DB_DEPTH_BOUNDS_MAX__MAX__SHIFT 0x0 15793#define DB_DEPTH_BOUNDS_MAX__MAX_MASK 0xFFFFFFFFL 15794//DB_STENCIL_CLEAR 15795#define DB_STENCIL_CLEAR__CLEAR__SHIFT 0x0 15796#define DB_STENCIL_CLEAR__CLEAR_MASK 0x000000FFL 15797//DB_DEPTH_CLEAR 15798#define DB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT 0x0 15799#define DB_DEPTH_CLEAR__DEPTH_CLEAR_MASK 0xFFFFFFFFL 15800//PA_SC_SCREEN_SCISSOR_TL 15801#define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT 0x0 15802#define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT 0x10 15803#define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK 0x0000FFFFL 15804#define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK 0xFFFF0000L 15805//PA_SC_SCREEN_SCISSOR_BR 15806#define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT 0x0 15807#define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT 0x10 15808#define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK 0x0000FFFFL 15809#define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK 0xFFFF0000L 15810//DB_Z_INFO 15811#define DB_Z_INFO__FORMAT__SHIFT 0x0 15812#define DB_Z_INFO__NUM_SAMPLES__SHIFT 0x2 15813#define DB_Z_INFO__SW_MODE__SHIFT 0x4 15814#define DB_Z_INFO__PARTIALLY_RESIDENT__SHIFT 0xc 15815#define DB_Z_INFO__FAULT_BEHAVIOR__SHIFT 0xd 15816#define DB_Z_INFO__ITERATE_FLUSH__SHIFT 0xf 15817#define DB_Z_INFO__MAXMIP__SHIFT 0x10 15818#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES__SHIFT 0x17 15819#define DB_Z_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b 15820#define DB_Z_INFO__READ_SIZE__SHIFT 0x1c 15821#define DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT 0x1d 15822#define DB_Z_INFO__CLEAR_DISALLOWED__SHIFT 0x1e 15823#define DB_Z_INFO__ZRANGE_PRECISION__SHIFT 0x1f 15824#define DB_Z_INFO__FORMAT_MASK 0x00000003L 15825#define DB_Z_INFO__NUM_SAMPLES_MASK 0x0000000CL 15826#define DB_Z_INFO__SW_MODE_MASK 0x000001F0L 15827#define DB_Z_INFO__PARTIALLY_RESIDENT_MASK 0x00001000L 15828#define DB_Z_INFO__FAULT_BEHAVIOR_MASK 0x00006000L 15829#define DB_Z_INFO__ITERATE_FLUSH_MASK 0x00008000L 15830#define DB_Z_INFO__MAXMIP_MASK 0x000F0000L 15831#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES_MASK 0x07800000L 15832#define DB_Z_INFO__ALLOW_EXPCLEAR_MASK 0x08000000L 15833#define DB_Z_INFO__READ_SIZE_MASK 0x10000000L 15834#define DB_Z_INFO__TILE_SURFACE_ENABLE_MASK 0x20000000L 15835#define DB_Z_INFO__CLEAR_DISALLOWED_MASK 0x40000000L 15836#define DB_Z_INFO__ZRANGE_PRECISION_MASK 0x80000000L 15837//DB_STENCIL_INFO 15838#define DB_STENCIL_INFO__FORMAT__SHIFT 0x0 15839#define DB_STENCIL_INFO__SW_MODE__SHIFT 0x4 15840#define DB_STENCIL_INFO__PARTIALLY_RESIDENT__SHIFT 0xc 15841#define DB_STENCIL_INFO__FAULT_BEHAVIOR__SHIFT 0xd 15842#define DB_STENCIL_INFO__ITERATE_FLUSH__SHIFT 0xf 15843#define DB_STENCIL_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b 15844#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT 0x1d 15845#define DB_STENCIL_INFO__CLEAR_DISALLOWED__SHIFT 0x1e 15846#define DB_STENCIL_INFO__FORMAT_MASK 0x00000001L 15847#define DB_STENCIL_INFO__SW_MODE_MASK 0x000001F0L 15848#define DB_STENCIL_INFO__PARTIALLY_RESIDENT_MASK 0x00001000L 15849#define DB_STENCIL_INFO__FAULT_BEHAVIOR_MASK 0x00006000L 15850#define DB_STENCIL_INFO__ITERATE_FLUSH_MASK 0x00008000L 15851#define DB_STENCIL_INFO__ALLOW_EXPCLEAR_MASK 0x08000000L 15852#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE_MASK 0x20000000L 15853#define DB_STENCIL_INFO__CLEAR_DISALLOWED_MASK 0x40000000L 15854//DB_Z_READ_BASE 15855#define DB_Z_READ_BASE__BASE_256B__SHIFT 0x0 15856#define DB_Z_READ_BASE__BASE_256B_MASK 0xFFFFFFFFL 15857//DB_Z_READ_BASE_HI 15858#define DB_Z_READ_BASE_HI__BASE_HI__SHIFT 0x0 15859#define DB_Z_READ_BASE_HI__BASE_HI_MASK 0x000000FFL 15860//DB_STENCIL_READ_BASE 15861#define DB_STENCIL_READ_BASE__BASE_256B__SHIFT 0x0 15862#define DB_STENCIL_READ_BASE__BASE_256B_MASK 0xFFFFFFFFL 15863//DB_STENCIL_READ_BASE_HI 15864#define DB_STENCIL_READ_BASE_HI__BASE_HI__SHIFT 0x0 15865#define DB_STENCIL_READ_BASE_HI__BASE_HI_MASK 0x000000FFL 15866//DB_Z_WRITE_BASE 15867#define DB_Z_WRITE_BASE__BASE_256B__SHIFT 0x0 15868#define DB_Z_WRITE_BASE__BASE_256B_MASK 0xFFFFFFFFL 15869//DB_Z_WRITE_BASE_HI 15870#define DB_Z_WRITE_BASE_HI__BASE_HI__SHIFT 0x0 15871#define DB_Z_WRITE_BASE_HI__BASE_HI_MASK 0x000000FFL 15872//DB_STENCIL_WRITE_BASE 15873#define DB_STENCIL_WRITE_BASE__BASE_256B__SHIFT 0x0 15874#define DB_STENCIL_WRITE_BASE__BASE_256B_MASK 0xFFFFFFFFL 15875//DB_STENCIL_WRITE_BASE_HI 15876#define DB_STENCIL_WRITE_BASE_HI__BASE_HI__SHIFT 0x0 15877#define DB_STENCIL_WRITE_BASE_HI__BASE_HI_MASK 0x000000FFL 15878//DB_DFSM_CONTROL 15879#define DB_DFSM_CONTROL__PUNCHOUT_MODE__SHIFT 0x0 15880#define DB_DFSM_CONTROL__POPS_DRAIN_PS_ON_OVERLAP__SHIFT 0x2 15881#define DB_DFSM_CONTROL__DISALLOW_OVERFLOW__SHIFT 0x3 15882#define DB_DFSM_CONTROL__PUNCHOUT_MODE_MASK 0x00000003L 15883#define DB_DFSM_CONTROL__POPS_DRAIN_PS_ON_OVERLAP_MASK 0x00000004L 15884#define DB_DFSM_CONTROL__DISALLOW_OVERFLOW_MASK 0x00000008L 15885//DB_Z_INFO2 15886#define DB_Z_INFO2__EPITCH__SHIFT 0x0 15887#define DB_Z_INFO2__EPITCH_MASK 0x0000FFFFL 15888//DB_STENCIL_INFO2 15889#define DB_STENCIL_INFO2__EPITCH__SHIFT 0x0 15890#define DB_STENCIL_INFO2__EPITCH_MASK 0x0000FFFFL 15891//TA_BC_BASE_ADDR 15892#define TA_BC_BASE_ADDR__ADDRESS__SHIFT 0x0 15893#define TA_BC_BASE_ADDR__ADDRESS_MASK 0xFFFFFFFFL 15894//TA_BC_BASE_ADDR_HI 15895#define TA_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0 15896#define TA_BC_BASE_ADDR_HI__ADDRESS_MASK 0x000000FFL 15897//COHER_DEST_BASE_HI_0 15898#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B__SHIFT 0x0 15899#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B_MASK 0x000000FFL 15900//COHER_DEST_BASE_HI_1 15901#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B__SHIFT 0x0 15902#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B_MASK 0x000000FFL 15903//COHER_DEST_BASE_HI_2 15904#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B__SHIFT 0x0 15905#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B_MASK 0x000000FFL 15906//COHER_DEST_BASE_HI_3 15907#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B__SHIFT 0x0 15908#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B_MASK 0x000000FFL 15909//COHER_DEST_BASE_2 15910#define COHER_DEST_BASE_2__DEST_BASE_256B__SHIFT 0x0 15911#define COHER_DEST_BASE_2__DEST_BASE_256B_MASK 0xFFFFFFFFL 15912//COHER_DEST_BASE_3 15913#define COHER_DEST_BASE_3__DEST_BASE_256B__SHIFT 0x0 15914#define COHER_DEST_BASE_3__DEST_BASE_256B_MASK 0xFFFFFFFFL 15915//PA_SC_WINDOW_OFFSET 15916#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT 0x0 15917#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT 0x10 15918#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK 0x0000FFFFL 15919#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK 0xFFFF0000L 15920//PA_SC_WINDOW_SCISSOR_TL 15921#define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT 0x0 15922#define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT 0x10 15923#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f 15924#define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK 0x00007FFFL 15925#define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK 0x7FFF0000L 15926#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L 15927//PA_SC_WINDOW_SCISSOR_BR 15928#define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT 0x0 15929#define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT 0x10 15930#define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK 0x00007FFFL 15931#define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK 0x7FFF0000L 15932//PA_SC_CLIPRECT_RULE 15933#define PA_SC_CLIPRECT_RULE__CLIP_RULE__SHIFT 0x0 15934#define PA_SC_CLIPRECT_RULE__CLIP_RULE_MASK 0x0000FFFFL 15935//PA_SC_CLIPRECT_0_TL 15936#define PA_SC_CLIPRECT_0_TL__TL_X__SHIFT 0x0 15937#define PA_SC_CLIPRECT_0_TL__TL_Y__SHIFT 0x10 15938#define PA_SC_CLIPRECT_0_TL__TL_X_MASK 0x00007FFFL 15939#define PA_SC_CLIPRECT_0_TL__TL_Y_MASK 0x7FFF0000L 15940//PA_SC_CLIPRECT_0_BR 15941#define PA_SC_CLIPRECT_0_BR__BR_X__SHIFT 0x0 15942#define PA_SC_CLIPRECT_0_BR__BR_Y__SHIFT 0x10 15943#define PA_SC_CLIPRECT_0_BR__BR_X_MASK 0x00007FFFL 15944#define PA_SC_CLIPRECT_0_BR__BR_Y_MASK 0x7FFF0000L 15945//PA_SC_CLIPRECT_1_TL 15946#define PA_SC_CLIPRECT_1_TL__TL_X__SHIFT 0x0 15947#define PA_SC_CLIPRECT_1_TL__TL_Y__SHIFT 0x10 15948#define PA_SC_CLIPRECT_1_TL__TL_X_MASK 0x00007FFFL 15949#define PA_SC_CLIPRECT_1_TL__TL_Y_MASK 0x7FFF0000L 15950//PA_SC_CLIPRECT_1_BR 15951#define PA_SC_CLIPRECT_1_BR__BR_X__SHIFT 0x0 15952#define PA_SC_CLIPRECT_1_BR__BR_Y__SHIFT 0x10 15953#define PA_SC_CLIPRECT_1_BR__BR_X_MASK 0x00007FFFL 15954#define PA_SC_CLIPRECT_1_BR__BR_Y_MASK 0x7FFF0000L 15955//PA_SC_CLIPRECT_2_TL 15956#define PA_SC_CLIPRECT_2_TL__TL_X__SHIFT 0x0 15957#define PA_SC_CLIPRECT_2_TL__TL_Y__SHIFT 0x10 15958#define PA_SC_CLIPRECT_2_TL__TL_X_MASK 0x00007FFFL 15959#define PA_SC_CLIPRECT_2_TL__TL_Y_MASK 0x7FFF0000L 15960//PA_SC_CLIPRECT_2_BR 15961#define PA_SC_CLIPRECT_2_BR__BR_X__SHIFT 0x0 15962#define PA_SC_CLIPRECT_2_BR__BR_Y__SHIFT 0x10 15963#define PA_SC_CLIPRECT_2_BR__BR_X_MASK 0x00007FFFL 15964#define PA_SC_CLIPRECT_2_BR__BR_Y_MASK 0x7FFF0000L 15965//PA_SC_CLIPRECT_3_TL 15966#define PA_SC_CLIPRECT_3_TL__TL_X__SHIFT 0x0 15967#define PA_SC_CLIPRECT_3_TL__TL_Y__SHIFT 0x10 15968#define PA_SC_CLIPRECT_3_TL__TL_X_MASK 0x00007FFFL 15969#define PA_SC_CLIPRECT_3_TL__TL_Y_MASK 0x7FFF0000L 15970//PA_SC_CLIPRECT_3_BR 15971#define PA_SC_CLIPRECT_3_BR__BR_X__SHIFT 0x0 15972#define PA_SC_CLIPRECT_3_BR__BR_Y__SHIFT 0x10 15973#define PA_SC_CLIPRECT_3_BR__BR_X_MASK 0x00007FFFL 15974#define PA_SC_CLIPRECT_3_BR__BR_Y_MASK 0x7FFF0000L 15975//PA_SC_EDGERULE 15976#define PA_SC_EDGERULE__ER_TRI__SHIFT 0x0 15977#define PA_SC_EDGERULE__ER_POINT__SHIFT 0x4 15978#define PA_SC_EDGERULE__ER_RECT__SHIFT 0x8 15979#define PA_SC_EDGERULE__ER_LINE_LR__SHIFT 0xc 15980#define PA_SC_EDGERULE__ER_LINE_RL__SHIFT 0x12 15981#define PA_SC_EDGERULE__ER_LINE_TB__SHIFT 0x18 15982#define PA_SC_EDGERULE__ER_LINE_BT__SHIFT 0x1c 15983#define PA_SC_EDGERULE__ER_TRI_MASK 0x0000000FL 15984#define PA_SC_EDGERULE__ER_POINT_MASK 0x000000F0L 15985#define PA_SC_EDGERULE__ER_RECT_MASK 0x00000F00L 15986#define PA_SC_EDGERULE__ER_LINE_LR_MASK 0x0003F000L 15987#define PA_SC_EDGERULE__ER_LINE_RL_MASK 0x00FC0000L 15988#define PA_SC_EDGERULE__ER_LINE_TB_MASK 0x0F000000L 15989#define PA_SC_EDGERULE__ER_LINE_BT_MASK 0xF0000000L 15990//PA_SU_HARDWARE_SCREEN_OFFSET 15991#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X__SHIFT 0x0 15992#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y__SHIFT 0x10 15993#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X_MASK 0x000001FFL 15994#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y_MASK 0x01FF0000L 15995//CB_TARGET_MASK 15996#define CB_TARGET_MASK__TARGET0_ENABLE__SHIFT 0x0 15997#define CB_TARGET_MASK__TARGET1_ENABLE__SHIFT 0x4 15998#define CB_TARGET_MASK__TARGET2_ENABLE__SHIFT 0x8 15999#define CB_TARGET_MASK__TARGET3_ENABLE__SHIFT 0xc 16000#define CB_TARGET_MASK__TARGET4_ENABLE__SHIFT 0x10
16001#define CB_TARGET_MASK__TARGET5_ENABLE__SHIFT 0x14 16002#define CB_TARGET_MASK__TARGET6_ENABLE__SHIFT 0x18 16003#define CB_TARGET_MASK__TARGET7_ENABLE__SHIFT 0x1c 16004#define CB_TARGET_MASK__TARGET0_ENABLE_MASK 0x0000000FL 16005#define CB_TARGET_MASK__TARGET1_ENABLE_MASK 0x000000F0L 16006#define CB_TARGET_MASK__TARGET2_ENABLE_MASK 0x00000F00L 16007#define CB_TARGET_MASK__TARGET3_ENABLE_MASK 0x0000F000L 16008#define CB_TARGET_MASK__TARGET4_ENABLE_MASK 0x000F0000L 16009#define CB_TARGET_MASK__TARGET5_ENABLE_MASK 0x00F00000L 16010#define CB_TARGET_MASK__TARGET6_ENABLE_MASK 0x0F000000L 16011#define CB_TARGET_MASK__TARGET7_ENABLE_MASK 0xF0000000L 16012//CB_SHADER_MASK 16013#define CB_SHADER_MASK__OUTPUT0_ENABLE__SHIFT 0x0 16014#define CB_SHADER_MASK__OUTPUT1_ENABLE__SHIFT 0x4 16015#define CB_SHADER_MASK__OUTPUT2_ENABLE__SHIFT 0x8 16016#define CB_SHADER_MASK__OUTPUT3_ENABLE__SHIFT 0xc 16017#define CB_SHADER_MASK__OUTPUT4_ENABLE__SHIFT 0x10 16018#define CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT 0x14 16019#define CB_SHADER_MASK__OUTPUT6_ENABLE__SHIFT 0x18 16020#define CB_SHADER_MASK__OUTPUT7_ENABLE__SHIFT 0x1c 16021#define CB_SHADER_MASK__OUTPUT0_ENABLE_MASK 0x0000000FL 16022#define CB_SHADER_MASK__OUTPUT1_ENABLE_MASK 0x000000F0L 16023#define CB_SHADER_MASK__OUTPUT2_ENABLE_MASK 0x00000F00L 16024#define CB_SHADER_MASK__OUTPUT3_ENABLE_MASK 0x0000F000L 16025#define CB_SHADER_MASK__OUTPUT4_ENABLE_MASK 0x000F0000L 16026#define CB_SHADER_MASK__OUTPUT5_ENABLE_MASK 0x00F00000L 16027#define CB_SHADER_MASK__OUTPUT6_ENABLE_MASK 0x0F000000L 16028#define CB_SHADER_MASK__OUTPUT7_ENABLE_MASK 0xF0000000L 16029//PA_SC_GENERIC_SCISSOR_TL 16030#define PA_SC_GENERIC_SCISSOR_TL__TL_X__SHIFT 0x0 16031#define PA_SC_GENERIC_SCISSOR_TL__TL_Y__SHIFT 0x10 16032#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f 16033#define PA_SC_GENERIC_SCISSOR_TL__TL_X_MASK 0x00007FFFL 16034#define PA_SC_GENERIC_SCISSOR_TL__TL_Y_MASK 0x7FFF0000L 16035#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L 16036//PA_SC_GENERIC_SCISSOR_BR 16037#define PA_SC_GENERIC_SCISSOR_BR__BR_X__SHIFT 0x0 16038#define PA_SC_GENERIC_SCISSOR_BR__BR_Y__SHIFT 0x10 16039#define PA_SC_GENERIC_SCISSOR_BR__BR_X_MASK 0x00007FFFL 16040#define PA_SC_GENERIC_SCISSOR_BR__BR_Y_MASK 0x7FFF0000L 16041//COHER_DEST_BASE_0 16042#define COHER_DEST_BASE_0__DEST_BASE_256B__SHIFT 0x0 16043#define COHER_DEST_BASE_0__DEST_BASE_256B_MASK 0xFFFFFFFFL 16044//COHER_DEST_BASE_1 16045#define COHER_DEST_BASE_1__DEST_BASE_256B__SHIFT 0x0 16046#define COHER_DEST_BASE_1__DEST_BASE_256B_MASK 0xFFFFFFFFL 16047//PA_SC_VPORT_SCISSOR_0_TL 16048#define PA_SC_VPORT_SCISSOR_0_TL__TL_X__SHIFT 0x0 16049#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y__SHIFT 0x10 16050#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f 16051#define PA_SC_VPORT_SCISSOR_0_TL__TL_X_MASK 0x00007FFFL 16052#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y_MASK 0x7FFF0000L 16053#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L 16054//PA_SC_VPORT_SCISSOR_0_BR 16055#define PA_SC_VPORT_SCISSOR_0_BR__BR_X__SHIFT 0x0 16056#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y__SHIFT 0x10 16057#define PA_SC_VPORT_SCISSOR_0_BR__BR_X_MASK 0x00007FFFL 16058#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y_MASK 0x7FFF0000L 16059//PA_SC_VPORT_SCISSOR_1_TL 16060#define PA_SC_VPORT_SCISSOR_1_TL__TL_X__SHIFT 0x0 16061#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y__SHIFT 0x10 16062#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f 16063#define PA_SC_VPORT_SCISSOR_1_TL__TL_X_MASK 0x00007FFFL 16064#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y_MASK 0x7FFF0000L 16065#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L 16066//PA_SC_VPORT_SCISSOR_1_BR 16067#define PA_SC_VPORT_SCISSOR_1_BR__BR_X__SHIFT 0x0 16068#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y__SHIFT 0x10 16069#define PA_SC_VPORT_SCISSOR_1_BR__BR_X_MASK 0x00007FFFL 16070#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y_MASK 0x7FFF0000L 16071//PA_SC_VPORT_SCISSOR_2_TL 16072#define PA_SC_VPORT_SCISSOR_2_TL__TL_X__SHIFT 0x0 16073#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y__SHIFT 0x10 16074#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f 16075#define PA_SC_VPORT_SCISSOR_2_TL__TL_X_MASK 0x00007FFFL 16076#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y_MASK 0x7FFF0000L 16077#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L 16078//PA_SC_VPORT_SCISSOR_2_BR 16079#define PA_SC_VPORT_SCISSOR_2_BR__BR_X__SHIFT 0x0 16080#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y__SHIFT 0x10 16081#define PA_SC_VPORT_SCISSOR_2_BR__BR_X_MASK 0x00007FFFL 16082#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y_MASK 0x7FFF0000L 16083//PA_SC_VPORT_SCISSOR_3_TL 16084#define PA_SC_VPORT_SCISSOR_3_TL__TL_X__SHIFT 0x0 16085#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y__SHIFT 0x10 16086#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f 16087#define PA_SC_VPORT_SCISSOR_3_TL__TL_X_MASK 0x00007FFFL 16088#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y_MASK 0x7FFF0000L 16089#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L 16090//PA_SC_VPORT_SCISSOR_3_BR 16091#define PA_SC_VPORT_SCISSOR_3_BR__BR_X__SHIFT 0x0 16092#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y__SHIFT 0x10 16093#define PA_SC_VPORT_SCISSOR_3_BR__BR_X_MASK 0x00007FFFL 16094#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y_MASK 0x7FFF0000L 16095//PA_SC_VPORT_SCISSOR_4_TL 16096#define PA_SC_VPORT_SCISSOR_4_TL__TL_X__SHIFT 0x0 16097#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y__SHIFT 0x10 16098#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f 16099#define PA_SC_VPORT_SCISSOR_4_TL__TL_X_MASK 0x00007FFFL 16100#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y_MASK 0x7FFF0000L 16101#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L 16102//PA_SC_VPORT_SCISSOR_4_BR 16103#define PA_SC_VPORT_SCISSOR_4_BR__BR_X__SHIFT 0x0 16104#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y__SHIFT 0x10 16105#define PA_SC_VPORT_SCISSOR_4_BR__BR_X_MASK 0x00007FFFL 16106#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y_MASK 0x7FFF0000L 16107//PA_SC_VPORT_SCISSOR_5_TL 16108#define PA_SC_VPORT_SCISSOR_5_TL__TL_X__SHIFT 0x0 16109#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y__SHIFT 0x10 16110#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f 16111#define PA_SC_VPORT_SCISSOR_5_TL__TL_X_MASK 0x00007FFFL 16112#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y_MASK 0x7FFF0000L 16113#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L 16114//PA_SC_VPORT_SCISSOR_5_BR 16115#define PA_SC_VPORT_SCISSOR_5_BR__BR_X__SHIFT 0x0 16116#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y__SHIFT 0x10 16117#define PA_SC_VPORT_SCISSOR_5_BR__BR_X_MASK 0x00007FFFL 16118#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y_MASK 0x7FFF0000L 16119//PA_SC_VPORT_SCISSOR_6_TL 16120#define PA_SC_VPORT_SCISSOR_6_TL__TL_X__SHIFT 0x0 16121#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y__SHIFT 0x10 16122#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f 16123#define PA_SC_VPORT_SCISSOR_6_TL__TL_X_MASK 0x00007FFFL 16124#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y_MASK 0x7FFF0000L 16125#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L 16126//PA_SC_VPORT_SCISSOR_6_BR 16127#define PA_SC_VPORT_SCISSOR_6_BR__BR_X__SHIFT 0x0 16128#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y__SHIFT 0x10 16129#define PA_SC_VPORT_SCISSOR_6_BR__BR_X_MASK 0x00007FFFL 16130#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y_MASK 0x7FFF0000L 16131//PA_SC_VPORT_SCISSOR_7_TL 16132#define PA_SC_VPORT_SCISSOR_7_TL__TL_X__SHIFT 0x0 16133#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y__SHIFT 0x10 16134#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f 16135#define PA_SC_VPORT_SCISSOR_7_TL__TL_X_MASK 0x00007FFFL 16136#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y_MASK 0x7FFF0000L 16137#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L 16138//PA_SC_VPORT_SCISSOR_7_BR 16139#define PA_SC_VPORT_SCISSOR_7_BR__BR_X__SHIFT 0x0 16140#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y__SHIFT 0x10 16141#define PA_SC_VPORT_SCISSOR_7_BR__BR_X_MASK 0x00007FFFL 16142#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y_MASK 0x7FFF0000L 16143//PA_SC_VPORT_SCISSOR_8_TL 16144#define PA_SC_VPORT_SCISSOR_8_TL__TL_X__SHIFT 0x0 16145#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y__SHIFT 0x10 16146#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f 16147#define PA_SC_VPORT_SCISSOR_8_TL__TL_X_MASK 0x00007FFFL 16148#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y_MASK 0x7FFF0000L 16149#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L 16150//PA_SC_VPORT_SCISSOR_8_BR 16151#define PA_SC_VPORT_SCISSOR_8_BR__BR_X__SHIFT 0x0 16152#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y__SHIFT 0x10 16153#define PA_SC_VPORT_SCISSOR_8_BR__BR_X_MASK 0x00007FFFL 16154#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y_MASK 0x7FFF0000L 16155//PA_SC_VPORT_SCISSOR_9_TL 16156#define PA_SC_VPORT_SCISSOR_9_TL__TL_X__SHIFT 0x0 16157#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y__SHIFT 0x10 16158#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f 16159#define PA_SC_VPORT_SCISSOR_9_TL__TL_X_MASK 0x00007FFFL 16160#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y_MASK 0x7FFF0000L 16161#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L 16162//PA_SC_VPORT_SCISSOR_9_BR 16163#define PA_SC_VPORT_SCISSOR_9_BR__BR_X__SHIFT 0x0 16164#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y__SHIFT 0x10 16165#define PA_SC_VPORT_SCISSOR_9_BR__BR_X_MASK 0x00007FFFL 16166#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y_MASK 0x7FFF0000L 16167//PA_SC_VPORT_SCISSOR_10_TL 16168#define PA_SC_VPORT_SCISSOR_10_TL__TL_X__SHIFT 0x0 16169#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y__SHIFT 0x10 16170#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f 16171#define PA_SC_VPORT_SCISSOR_10_TL__TL_X_MASK 0x00007FFFL 16172#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y_MASK 0x7FFF0000L 16173#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L 16174//PA_SC_VPORT_SCISSOR_10_BR 16175#define PA_SC_VPORT_SCISSOR_10_BR__BR_X__SHIFT 0x0 16176#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y__SHIFT 0x10 16177#define PA_SC_VPORT_SCISSOR_10_BR__BR_X_MASK 0x00007FFFL 16178#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y_MASK 0x7FFF0000L 16179//PA_SC_VPORT_SCISSOR_11_TL 16180#define PA_SC_VPORT_SCISSOR_11_TL__TL_X__SHIFT 0x0 16181#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y__SHIFT 0x10 16182#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f 16183#define PA_SC_VPORT_SCISSOR_11_TL__TL_X_MASK 0x00007FFFL 16184#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y_MASK 0x7FFF0000L 16185#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L 16186//PA_SC_VPORT_SCISSOR_11_BR 16187#define PA_SC_VPORT_SCISSOR_11_BR__BR_X__SHIFT 0x0 16188#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y__SHIFT 0x10 16189#define PA_SC_VPORT_SCISSOR_11_BR__BR_X_MASK 0x00007FFFL 16190#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y_MASK 0x7FFF0000L 16191//PA_SC_VPORT_SCISSOR_12_TL 16192#define PA_SC_VPORT_SCISSOR_12_TL__TL_X__SHIFT 0x0 16193#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y__SHIFT 0x10 16194#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f 16195#define PA_SC_VPORT_SCISSOR_12_TL__TL_X_MASK 0x00007FFFL 16196#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y_MASK 0x7FFF0000L 16197#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L 16198//PA_SC_VPORT_SCISSOR_12_BR 16199#define PA_SC_VPORT_SCISSOR_12_BR__BR_X__SHIFT 0x0 16200#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y__SHIFT 0x10 16201#define PA_SC_VPORT_SCISSOR_12_BR__BR_X_MASK 0x00007FFFL 16202#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y_MASK 0x7FFF0000L 16203//PA_SC_VPORT_SCISSOR_13_TL 16204#define PA_SC_VPORT_SCISSOR_13_TL__TL_X__SHIFT 0x0 16205#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y__SHIFT 0x10 16206#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f 16207#define PA_SC_VPORT_SCISSOR_13_TL__TL_X_MASK 0x00007FFFL 16208#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y_MASK 0x7FFF0000L 16209#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L 16210//PA_SC_VPORT_SCISSOR_13_BR 16211#define PA_SC_VPORT_SCISSOR_13_BR__BR_X__SHIFT 0x0 16212#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y__SHIFT 0x10 16213#define PA_SC_VPORT_SCISSOR_13_BR__BR_X_MASK 0x00007FFFL 16214#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y_MASK 0x7FFF0000L 16215//PA_SC_VPORT_SCISSOR_14_TL 16216#define PA_SC_VPORT_SCISSOR_14_TL__TL_X__SHIFT 0x0 16217#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y__SHIFT 0x10 16218#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f 16219#define PA_SC_VPORT_SCISSOR_14_TL__TL_X_MASK 0x00007FFFL 16220#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y_MASK 0x7FFF0000L 16221#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L 16222//PA_SC_VPORT_SCISSOR_14_BR 16223#define PA_SC_VPORT_SCISSOR_14_BR__BR_X__SHIFT 0x0 16224#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y__SHIFT 0x10 16225#define PA_SC_VPORT_SCISSOR_14_BR__BR_X_MASK 0x00007FFFL 16226#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y_MASK 0x7FFF0000L 16227//PA_SC_VPORT_SCISSOR_15_TL 16228#define PA_SC_VPORT_SCISSOR_15_TL__TL_X__SHIFT 0x0 16229#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y__SHIFT 0x10 16230#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f 16231#define PA_SC_VPORT_SCISSOR_15_TL__TL_X_MASK 0x00007FFFL 16232#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y_MASK 0x7FFF0000L 16233#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L 16234//PA_SC_VPORT_SCISSOR_15_BR 16235#define PA_SC_VPORT_SCISSOR_15_BR__BR_X__SHIFT 0x0 16236#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y__SHIFT 0x10 16237#define PA_SC_VPORT_SCISSOR_15_BR__BR_X_MASK 0x00007FFFL 16238#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y_MASK 0x7FFF0000L 16239//PA_SC_VPORT_ZMIN_0 16240#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN__SHIFT 0x0 16241#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN_MASK 0xFFFFFFFFL 16242//PA_SC_VPORT_ZMAX_0 16243#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX__SHIFT 0x0 16244#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX_MASK 0xFFFFFFFFL 16245//PA_SC_VPORT_ZMIN_1 16246#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN__SHIFT 0x0 16247#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN_MASK 0xFFFFFFFFL 16248//PA_SC_VPORT_ZMAX_1 16249#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX__SHIFT 0x0 16250#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX_MASK 0xFFFFFFFFL 16251//PA_SC_VPORT_ZMIN_2 16252#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN__SHIFT 0x0 16253#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN_MASK 0xFFFFFFFFL 16254//PA_SC_VPORT_ZMAX_2 16255#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX__SHIFT 0x0 16256#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX_MASK 0xFFFFFFFFL 16257//PA_SC_VPORT_ZMIN_3 16258#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN__SHIFT 0x0 16259#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN_MASK 0xFFFFFFFFL 16260//PA_SC_VPORT_ZMAX_3 16261#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX__SHIFT 0x0 16262#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX_MASK 0xFFFFFFFFL 16263//PA_SC_VPORT_ZMIN_4 16264#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN__SHIFT 0x0 16265#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN_MASK 0xFFFFFFFFL 16266//PA_SC_VPORT_ZMAX_4 16267#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX__SHIFT 0x0 16268#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX_MASK 0xFFFFFFFFL 16269//PA_SC_VPORT_ZMIN_5 16270#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN__SHIFT 0x0 16271#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN_MASK 0xFFFFFFFFL 16272//PA_SC_VPORT_ZMAX_5 16273#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX__SHIFT 0x0 16274#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX_MASK 0xFFFFFFFFL 16275//PA_SC_VPORT_ZMIN_6 16276#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN__SHIFT 0x0 16277#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN_MASK 0xFFFFFFFFL 16278//PA_SC_VPORT_ZMAX_6 16279#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX__SHIFT 0x0 16280#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX_MASK 0xFFFFFFFFL 16281//PA_SC_VPORT_ZMIN_7 16282#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN__SHIFT 0x0 16283#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN_MASK 0xFFFFFFFFL 16284//PA_SC_VPORT_ZMAX_7 16285#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX__SHIFT 0x0 16286#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX_MASK 0xFFFFFFFFL 16287//PA_SC_VPORT_ZMIN_8 16288#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN__SHIFT 0x0 16289#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN_MASK 0xFFFFFFFFL 16290//PA_SC_VPORT_ZMAX_8 16291#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX__SHIFT 0x0 16292#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX_MASK 0xFFFFFFFFL 16293//PA_SC_VPORT_ZMIN_9 16294#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN__SHIFT 0x0 16295#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN_MASK 0xFFFFFFFFL 16296//PA_SC_VPORT_ZMAX_9 16297#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX__SHIFT 0x0 16298#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX_MASK 0xFFFFFFFFL 16299//PA_SC_VPORT_ZMIN_10 16300#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN__SHIFT 0x0 16301#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN_MASK 0xFFFFFFFFL 16302//PA_SC_VPORT_ZMAX_10 16303#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX__SHIFT 0x0 16304#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX_MASK 0xFFFFFFFFL 16305//PA_SC_VPORT_ZMIN_11 16306#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN__SHIFT 0x0 16307#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN_MASK 0xFFFFFFFFL 16308//PA_SC_VPORT_ZMAX_11 16309#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX__SHIFT 0x0 16310#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX_MASK 0xFFFFFFFFL 16311//PA_SC_VPORT_ZMIN_12 16312#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN__SHIFT 0x0 16313#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN_MASK 0xFFFFFFFFL 16314//PA_SC_VPORT_ZMAX_12 16315#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX__SHIFT 0x0 16316#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX_MASK 0xFFFFFFFFL 16317//PA_SC_VPORT_ZMIN_13 16318#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN__SHIFT 0x0 16319#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN_MASK 0xFFFFFFFFL 16320//PA_SC_VPORT_ZMAX_13 16321#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX__SHIFT 0x0 16322#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX_MASK 0xFFFFFFFFL 16323//PA_SC_VPORT_ZMIN_14 16324#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN__SHIFT 0x0 16325#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN_MASK 0xFFFFFFFFL 16326//PA_SC_VPORT_ZMAX_14 16327#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX__SHIFT 0x0 16328#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX_MASK 0xFFFFFFFFL 16329//PA_SC_VPORT_ZMIN_15 16330#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN__SHIFT 0x0 16331#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN_MASK 0xFFFFFFFFL 16332//PA_SC_VPORT_ZMAX_15 16333#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX__SHIFT 0x0 16334#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX_MASK 0xFFFFFFFFL 16335//PA_SC_RASTER_CONFIG 16336#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT 0x0 16337#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT 0x2 16338#define PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT 0x4 16339#define PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT 0x6 16340#define PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT 0x7 16341#define PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT 0x8 16342#define PA_SC_RASTER_CONFIG__PKR_XSEL__SHIFT 0xa 16343#define PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT 0xc 16344#define PA_SC_RASTER_CONFIG__PKR_XSEL2__SHIFT 0xe 16345#define PA_SC_RASTER_CONFIG__SC_MAP__SHIFT 0x10 16346#define PA_SC_RASTER_CONFIG__SC_XSEL__SHIFT 0x12 16347#define PA_SC_RASTER_CONFIG__SC_YSEL__SHIFT 0x14 16348#define PA_SC_RASTER_CONFIG__SE_MAP__SHIFT 0x18 16349#define PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT 0x1a 16350#define PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT 0x1d 16351#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK 0x00000003L 16352#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK 0x0000000CL 16353#define PA_SC_RASTER_CONFIG__RB_XSEL2_MASK 0x00000030L 16354#define PA_SC_RASTER_CONFIG__RB_XSEL_MASK 0x00000040L 16355#define PA_SC_RASTER_CONFIG__RB_YSEL_MASK 0x00000080L 16356#define PA_SC_RASTER_CONFIG__PKR_MAP_MASK 0x00000300L 16357#define PA_SC_RASTER_CONFIG__PKR_XSEL_MASK 0x00000C00L 16358#define PA_SC_RASTER_CONFIG__PKR_YSEL_MASK 0x00003000L 16359#define PA_SC_RASTER_CONFIG__PKR_XSEL2_MASK 0x0000C000L 16360#define PA_SC_RASTER_CONFIG__SC_MAP_MASK 0x00030000L 16361#define PA_SC_RASTER_CONFIG__SC_XSEL_MASK 0x000C0000L 16362#define PA_SC_RASTER_CONFIG__SC_YSEL_MASK 0x00300000L 16363#define PA_SC_RASTER_CONFIG__SE_MAP_MASK 0x03000000L 16364#define PA_SC_RASTER_CONFIG__SE_XSEL_MASK 0x1C000000L 16365#define PA_SC_RASTER_CONFIG__SE_YSEL_MASK 0xE0000000L 16366//PA_SC_RASTER_CONFIG_1 16367#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP__SHIFT 0x0 16368#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL__SHIFT 0x2 16369#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL__SHIFT 0x5 16370#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP_MASK 0x00000003L 16371#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL_MASK 0x0000001CL 16372#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL_MASK 0x000000E0L 16373//PA_SC_SCREEN_EXTENT_CONTROL 16374#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x0 16375#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x2 16376#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x00000003L 16377#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE_MASK 0x0000000CL 16378//PA_SC_TILE_STEERING_OVERRIDE 16379#define PA_SC_TILE_STEERING_OVERRIDE__ENABLE__SHIFT 0x0 16380#define PA_SC_TILE_STEERING_OVERRIDE__NUM_SE__SHIFT 0x1 16381#define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE__SHIFT 0x5 16382#define PA_SC_TILE_STEERING_OVERRIDE__DISABLE_SRBSL_DB_OPTIMIZED_PACKING__SHIFT 0x8 16383#define PA_SC_TILE_STEERING_OVERRIDE__ENABLE_MASK 0x00000001L 16384#define PA_SC_TILE_STEERING_OVERRIDE__NUM_SE_MASK 0x00000006L 16385#define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE_MASK 0x00000060L 16386#define PA_SC_TILE_STEERING_OVERRIDE__DISABLE_SRBSL_DB_OPTIMIZED_PACKING_MASK 0x00000100L 16387//CP_PERFMON_CNTX_CNTL 16388#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT 0x1f 16389#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK 0x80000000L 16390//CP_PIPEID 16391#define CP_PIPEID__PIPE_ID__SHIFT 0x0 16392#define CP_PIPEID__PIPE_ID_MASK 0x00000003L 16393//CP_RINGID 16394#define CP_RINGID__RINGID__SHIFT 0x0 16395#define CP_RINGID__RINGID_MASK 0x00000003L 16396//CP_VMID 16397#define CP_VMID__VMID__SHIFT 0x0 16398#define CP_VMID__VMID_MASK 0x0000000FL 16399//PA_SC_RIGHT_VERT_GRID 16400#define PA_SC_RIGHT_VERT_GRID__LEFT_QTR__SHIFT 0x0 16401#define PA_SC_RIGHT_VERT_GRID__LEFT_HALF__SHIFT 0x8 16402#define PA_SC_RIGHT_VERT_GRID__RIGHT_HALF__SHIFT 0x10 16403#define PA_SC_RIGHT_VERT_GRID__RIGHT_QTR__SHIFT 0x18 16404#define PA_SC_RIGHT_VERT_GRID__LEFT_QTR_MASK 0x000000FFL 16405#define PA_SC_RIGHT_VERT_GRID__LEFT_HALF_MASK 0x0000FF00L 16406#define PA_SC_RIGHT_VERT_GRID__RIGHT_HALF_MASK 0x00FF0000L 16407#define PA_SC_RIGHT_VERT_GRID__RIGHT_QTR_MASK 0xFF000000L 16408//PA_SC_LEFT_VERT_GRID 16409#define PA_SC_LEFT_VERT_GRID__LEFT_QTR__SHIFT 0x0 16410#define PA_SC_LEFT_VERT_GRID__LEFT_HALF__SHIFT 0x8 16411#define PA_SC_LEFT_VERT_GRID__RIGHT_HALF__SHIFT 0x10 16412#define PA_SC_LEFT_VERT_GRID__RIGHT_QTR__SHIFT 0x18 16413#define PA_SC_LEFT_VERT_GRID__LEFT_QTR_MASK 0x000000FFL 16414#define PA_SC_LEFT_VERT_GRID__LEFT_HALF_MASK 0x0000FF00L 16415#define PA_SC_LEFT_VERT_GRID__RIGHT_HALF_MASK 0x00FF0000L 16416#define PA_SC_LEFT_VERT_GRID__RIGHT_QTR_MASK 0xFF000000L 16417//PA_SC_HORIZ_GRID 16418#define PA_SC_HORIZ_GRID__TOP_QTR__SHIFT 0x0 16419#define PA_SC_HORIZ_GRID__TOP_HALF__SHIFT 0x8 16420#define PA_SC_HORIZ_GRID__BOT_HALF__SHIFT 0x10 16421#define PA_SC_HORIZ_GRID__BOT_QTR__SHIFT 0x18 16422#define PA_SC_HORIZ_GRID__TOP_QTR_MASK 0x000000FFL 16423#define PA_SC_HORIZ_GRID__TOP_HALF_MASK 0x0000FF00L 16424#define PA_SC_HORIZ_GRID__BOT_HALF_MASK 0x00FF0000L 16425#define PA_SC_HORIZ_GRID__BOT_QTR_MASK 0xFF000000L 16426//VGT_MULTI_PRIM_IB_RESET_INDX 16427#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT 0x0 16428#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK 0xFFFFFFFFL 16429//CB_BLEND_RED 16430#define CB_BLEND_RED__BLEND_RED__SHIFT 0x0 16431#define CB_BLEND_RED__BLEND_RED_MASK 0xFFFFFFFFL 16432//CB_BLEND_GREEN 16433#define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0 16434#define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xFFFFFFFFL 16435//CB_BLEND_BLUE 16436#define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0 16437#define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xFFFFFFFFL 16438//CB_BLEND_ALPHA 16439#define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0 16440#define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xFFFFFFFFL 16441//CB_DCC_CONTROL 16442#define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 16443#define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE__SHIFT 0x1 16444#define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK__SHIFT 0x2 16445#define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L 16446#define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE_MASK 0x00000002L 16447#define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK_MASK 0x0000007CL 16448//DB_STENCIL_CONTROL 16449#define DB_STENCIL_CONTROL__STENCILFAIL__SHIFT 0x0 16450#define DB_STENCIL_CONTROL__STENCILZPASS__SHIFT 0x4 16451#define DB_STENCIL_CONTROL__STENCILZFAIL__SHIFT 0x8 16452#define DB_STENCIL_CONTROL__STENCILFAIL_BF__SHIFT 0xc 16453#define DB_STENCIL_CONTROL__STENCILZPASS_BF__SHIFT 0x10 16454#define DB_STENCIL_CONTROL__STENCILZFAIL_BF__SHIFT 0x14 16455#define DB_STENCIL_CONTROL__STENCILFAIL_MASK 0x0000000FL 16456#define DB_STENCIL_CONTROL__STENCILZPASS_MASK 0x000000F0L 16457#define DB_STENCIL_CONTROL__STENCILZFAIL_MASK 0x00000F00L 16458#define DB_STENCIL_CONTROL__STENCILFAIL_BF_MASK 0x0000F000L 16459#define DB_STENCIL_CONTROL__STENCILZPASS_BF_MASK 0x000F0000L 16460#define DB_STENCIL_CONTROL__STENCILZFAIL_BF_MASK 0x00F00000L 16461//DB_STENCILREFMASK 16462#define DB_STENCILREFMASK__STENCILTESTVAL__SHIFT 0x0 16463#define DB_STENCILREFMASK__STENCILMASK__SHIFT 0x8 16464#define DB_STENCILREFMASK__STENCILWRITEMASK__SHIFT 0x10 16465#define DB_STENCILREFMASK__STENCILOPVAL__SHIFT 0x18 16466#define DB_STENCILREFMASK__STENCILTESTVAL_MASK 0x000000FFL 16467#define DB_STENCILREFMASK__STENCILMASK_MASK 0x0000FF00L 16468#define DB_STENCILREFMASK__STENCILWRITEMASK_MASK 0x00FF0000L 16469#define DB_STENCILREFMASK__STENCILOPVAL_MASK 0xFF000000L 16470//DB_STENCILREFMASK_BF 16471#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF__SHIFT 0x0 16472#define DB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT 0x8 16473#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT 0x10 16474#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF__SHIFT 0x18 16475#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF_MASK 0x000000FFL 16476#define DB_STENCILREFMASK_BF__STENCILMASK_BF_MASK 0x0000FF00L 16477#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK 0x00FF0000L 16478#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF_MASK 0xFF000000L 16479//PA_CL_VPORT_XSCALE 16480#define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT 0x0 16481#define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK 0xFFFFFFFFL 16482//PA_CL_VPORT_XOFFSET 16483#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT 0x0 16484#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK 0xFFFFFFFFL 16485//PA_CL_VPORT_YSCALE 16486#define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT 0x0 16487#define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK 0xFFFFFFFFL 16488//PA_CL_VPORT_YOFFSET 16489#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT 0x0 16490#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK 0xFFFFFFFFL 16491//PA_CL_VPORT_ZSCALE 16492#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT 0x0 16493#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK 0xFFFFFFFFL 16494//PA_CL_VPORT_ZOFFSET 16495#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT 0x0 16496#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK 0xFFFFFFFFL 16497//PA_CL_VPORT_XSCALE_1 16498#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE__SHIFT 0x0 16499#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE_MASK 0xFFFFFFFFL 16500//PA_CL_VPORT_XOFFSET_1 16501#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET__SHIFT 0x0 16502#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET_MASK 0xFFFFFFFFL 16503//PA_CL_VPORT_YSCALE_1 16504#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE__SHIFT 0x0 16505#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE_MASK 0xFFFFFFFFL 16506//PA_CL_VPORT_YOFFSET_1 16507#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET__SHIFT 0x0 16508#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET_MASK 0xFFFFFFFFL 16509//PA_CL_VPORT_ZSCALE_1 16510#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE__SHIFT 0x0 16511#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE_MASK 0xFFFFFFFFL 16512//PA_CL_VPORT_ZOFFSET_1 16513#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET__SHIFT 0x0 16514#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET_MASK 0xFFFFFFFFL 16515//PA_CL_VPORT_XSCALE_2 16516#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE__SHIFT 0x0 16517#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE_MASK 0xFFFFFFFFL 16518//PA_CL_VPORT_XOFFSET_2 16519#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET__SHIFT 0x0 16520#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET_MASK 0xFFFFFFFFL 16521//PA_CL_VPORT_YSCALE_2 16522#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE__SHIFT 0x0 16523#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE_MASK 0xFFFFFFFFL 16524//PA_CL_VPORT_YOFFSET_2 16525#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET__SHIFT 0x0 16526#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET_MASK 0xFFFFFFFFL 16527//PA_CL_VPORT_ZSCALE_2 16528#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE__SHIFT 0x0 16529#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE_MASK 0xFFFFFFFFL 16530//PA_CL_VPORT_ZOFFSET_2 16531#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET__SHIFT 0x0 16532#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET_MASK 0xFFFFFFFFL 16533//PA_CL_VPORT_XSCALE_3 16534#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE__SHIFT 0x0 16535#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE_MASK 0xFFFFFFFFL 16536//PA_CL_VPORT_XOFFSET_3 16537#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET__SHIFT 0x0 16538#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET_MASK 0xFFFFFFFFL 16539//PA_CL_VPORT_YSCALE_3 16540#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE__SHIFT 0x0 16541#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE_MASK 0xFFFFFFFFL 16542//PA_CL_VPORT_YOFFSET_3 16543#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET__SHIFT 0x0 16544#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET_MASK 0xFFFFFFFFL 16545//PA_CL_VPORT_ZSCALE_3 16546#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE__SHIFT 0x0 16547#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE_MASK 0xFFFFFFFFL 16548//PA_CL_VPORT_ZOFFSET_3 16549#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET__SHIFT 0x0 16550#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET_MASK 0xFFFFFFFFL 16551//PA_CL_VPORT_XSCALE_4 16552#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE__SHIFT 0x0 16553#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE_MASK 0xFFFFFFFFL 16554//PA_CL_VPORT_XOFFSET_4 16555#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET__SHIFT 0x0 16556#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET_MASK 0xFFFFFFFFL 16557//PA_CL_VPORT_YSCALE_4 16558#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE__SHIFT 0x0 16559#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE_MASK 0xFFFFFFFFL 16560//PA_CL_VPORT_YOFFSET_4 16561#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET__SHIFT 0x0 16562#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET_MASK 0xFFFFFFFFL 16563//PA_CL_VPORT_ZSCALE_4 16564#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE__SHIFT 0x0 16565#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE_MASK 0xFFFFFFFFL 16566//PA_CL_VPORT_ZOFFSET_4 16567#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET__SHIFT 0x0 16568#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET_MASK 0xFFFFFFFFL 16569//PA_CL_VPORT_XSCALE_5 16570#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE__SHIFT 0x0 16571#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE_MASK 0xFFFFFFFFL 16572//PA_CL_VPORT_XOFFSET_5 16573#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET__SHIFT 0x0 16574#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET_MASK 0xFFFFFFFFL 16575//PA_CL_VPORT_YSCALE_5 16576#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE__SHIFT 0x0 16577#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE_MASK 0xFFFFFFFFL 16578//PA_CL_VPORT_YOFFSET_5 16579#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET__SHIFT 0x0 16580#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET_MASK 0xFFFFFFFFL 16581//PA_CL_VPORT_ZSCALE_5 16582#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE__SHIFT 0x0 16583#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE_MASK 0xFFFFFFFFL 16584//PA_CL_VPORT_ZOFFSET_5 16585#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET__SHIFT 0x0 16586#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET_MASK 0xFFFFFFFFL 16587//PA_CL_VPORT_XSCALE_6 16588#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE__SHIFT 0x0 16589#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE_MASK 0xFFFFFFFFL 16590//PA_CL_VPORT_XOFFSET_6 16591#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET__SHIFT 0x0 16592#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET_MASK 0xFFFFFFFFL 16593//PA_CL_VPORT_YSCALE_6 16594#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE__SHIFT 0x0 16595#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE_MASK 0xFFFFFFFFL 16596//PA_CL_VPORT_YOFFSET_6 16597#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET__SHIFT 0x0 16598#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET_MASK 0xFFFFFFFFL 16599//PA_CL_VPORT_ZSCALE_6 16600#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE__SHIFT 0x0 16601#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE_MASK 0xFFFFFFFFL 16602//PA_CL_VPORT_ZOFFSET_6 16603#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET__SHIFT 0x0 16604#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET_MASK 0xFFFFFFFFL 16605//PA_CL_VPORT_XSCALE_7 16606#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE__SHIFT 0x0 16607#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE_MASK 0xFFFFFFFFL 16608//PA_CL_VPORT_XOFFSET_7 16609#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET__SHIFT 0x0 16610#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET_MASK 0xFFFFFFFFL 16611//PA_CL_VPORT_YSCALE_7 16612#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE__SHIFT 0x0 16613#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE_MASK 0xFFFFFFFFL 16614//PA_CL_VPORT_YOFFSET_7 16615#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET__SHIFT 0x0 16616#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET_MASK 0xFFFFFFFFL 16617//PA_CL_VPORT_ZSCALE_7 16618#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE__SHIFT 0x0 16619#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE_MASK 0xFFFFFFFFL 16620//PA_CL_VPORT_ZOFFSET_7 16621#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET__SHIFT 0x0 16622#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET_MASK 0xFFFFFFFFL 16623//PA_CL_VPORT_XSCALE_8 16624#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE__SHIFT 0x0 16625#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE_MASK 0xFFFFFFFFL 16626//PA_CL_VPORT_XOFFSET_8 16627#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET__SHIFT 0x0 16628#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET_MASK 0xFFFFFFFFL 16629//PA_CL_VPORT_YSCALE_8 16630#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE__SHIFT 0x0 16631#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE_MASK 0xFFFFFFFFL 16632//PA_CL_VPORT_YOFFSET_8 16633#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET__SHIFT 0x0 16634#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET_MASK 0xFFFFFFFFL 16635//PA_CL_VPORT_ZSCALE_8 16636#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE__SHIFT 0x0 16637#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE_MASK 0xFFFFFFFFL 16638//PA_CL_VPORT_ZOFFSET_8 16639#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET__SHIFT 0x0 16640#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET_MASK 0xFFFFFFFFL 16641//PA_CL_VPORT_XSCALE_9 16642#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE__SHIFT 0x0 16643#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE_MASK 0xFFFFFFFFL 16644//PA_CL_VPORT_XOFFSET_9 16645#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET__SHIFT 0x0 16646#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET_MASK 0xFFFFFFFFL 16647//PA_CL_VPORT_YSCALE_9 16648#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE__SHIFT 0x0 16649#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE_MASK 0xFFFFFFFFL 16650//PA_CL_VPORT_YOFFSET_9 16651#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET__SHIFT 0x0 16652#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET_MASK 0xFFFFFFFFL 16653//PA_CL_VPORT_ZSCALE_9 16654#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE__SHIFT 0x0 16655#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE_MASK 0xFFFFFFFFL 16656//PA_CL_VPORT_ZOFFSET_9 16657#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET__SHIFT 0x0 16658#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET_MASK 0xFFFFFFFFL 16659//PA_CL_VPORT_XSCALE_10 16660#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE__SHIFT 0x0 16661#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE_MASK 0xFFFFFFFFL 16662//PA_CL_VPORT_XOFFSET_10 16663#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET__SHIFT 0x0 16664#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET_MASK 0xFFFFFFFFL 16665//PA_CL_VPORT_YSCALE_10 16666#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE__SHIFT 0x0 16667#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE_MASK 0xFFFFFFFFL 16668//PA_CL_VPORT_YOFFSET_10 16669#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET__SHIFT 0x0 16670#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET_MASK 0xFFFFFFFFL 16671//PA_CL_VPORT_ZSCALE_10 16672#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE__SHIFT 0x0 16673#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE_MASK 0xFFFFFFFFL 16674//PA_CL_VPORT_ZOFFSET_10 16675#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET__SHIFT 0x0 16676#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET_MASK 0xFFFFFFFFL 16677//PA_CL_VPORT_XSCALE_11 16678#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE__SHIFT 0x0 16679#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE_MASK 0xFFFFFFFFL 16680//PA_CL_VPORT_XOFFSET_11 16681#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET__SHIFT 0x0 16682#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET_MASK 0xFFFFFFFFL 16683//PA_CL_VPORT_YSCALE_11 16684#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE__SHIFT 0x0 16685#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE_MASK 0xFFFFFFFFL 16686//PA_CL_VPORT_YOFFSET_11 16687#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET__SHIFT 0x0 16688#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET_MASK 0xFFFFFFFFL 16689//PA_CL_VPORT_ZSCALE_11 16690#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE__SHIFT 0x0 16691#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE_MASK 0xFFFFFFFFL 16692//PA_CL_VPORT_ZOFFSET_11 16693#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET__SHIFT 0x0 16694#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET_MASK 0xFFFFFFFFL 16695//PA_CL_VPORT_XSCALE_12 16696#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE__SHIFT 0x0 16697#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE_MASK 0xFFFFFFFFL 16698//PA_CL_VPORT_XOFFSET_12 16699#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET__SHIFT 0x0 16700#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET_MASK 0xFFFFFFFFL 16701//PA_CL_VPORT_YSCALE_12 16702#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE__SHIFT 0x0 16703#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE_MASK 0xFFFFFFFFL 16704//PA_CL_VPORT_YOFFSET_12 16705#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET__SHIFT 0x0 16706#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET_MASK 0xFFFFFFFFL 16707//PA_CL_VPORT_ZSCALE_12 16708#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE__SHIFT 0x0 16709#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE_MASK 0xFFFFFFFFL 16710//PA_CL_VPORT_ZOFFSET_12 16711#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET__SHIFT 0x0 16712#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET_MASK 0xFFFFFFFFL 16713//PA_CL_VPORT_XSCALE_13 16714#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE__SHIFT 0x0 16715#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE_MASK 0xFFFFFFFFL 16716//PA_CL_VPORT_XOFFSET_13 16717#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET__SHIFT 0x0 16718#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET_MASK 0xFFFFFFFFL 16719//PA_CL_VPORT_YSCALE_13 16720#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE__SHIFT 0x0 16721#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE_MASK 0xFFFFFFFFL 16722//PA_CL_VPORT_YOFFSET_13 16723#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET__SHIFT 0x0 16724#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET_MASK 0xFFFFFFFFL 16725//PA_CL_VPORT_ZSCALE_13 16726#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE__SHIFT 0x0 16727#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE_MASK 0xFFFFFFFFL 16728//PA_CL_VPORT_ZOFFSET_13 16729#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET__SHIFT 0x0 16730#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET_MASK 0xFFFFFFFFL 16731//PA_CL_VPORT_XSCALE_14 16732#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE__SHIFT 0x0 16733#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE_MASK 0xFFFFFFFFL 16734//PA_CL_VPORT_XOFFSET_14 16735#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET__SHIFT 0x0 16736#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET_MASK 0xFFFFFFFFL 16737//PA_CL_VPORT_YSCALE_14 16738#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE__SHIFT 0x0 16739#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE_MASK 0xFFFFFFFFL 16740//PA_CL_VPORT_YOFFSET_14 16741#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET__SHIFT 0x0 16742#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET_MASK 0xFFFFFFFFL 16743//PA_CL_VPORT_ZSCALE_14 16744#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE__SHIFT 0x0 16745#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE_MASK 0xFFFFFFFFL 16746//PA_CL_VPORT_ZOFFSET_14 16747#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET__SHIFT 0x0 16748#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET_MASK 0xFFFFFFFFL 16749//PA_CL_VPORT_XSCALE_15 16750#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE__SHIFT 0x0 16751#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE_MASK 0xFFFFFFFFL 16752//PA_CL_VPORT_XOFFSET_15 16753#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET__SHIFT 0x0 16754#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET_MASK 0xFFFFFFFFL 16755//PA_CL_VPORT_YSCALE_15 16756#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE__SHIFT 0x0 16757#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE_MASK 0xFFFFFFFFL 16758//PA_CL_VPORT_YOFFSET_15 16759#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET__SHIFT 0x0 16760#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET_MASK 0xFFFFFFFFL 16761//PA_CL_VPORT_ZSCALE_15 16762#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE__SHIFT 0x0 16763#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE_MASK 0xFFFFFFFFL 16764//PA_CL_VPORT_ZOFFSET_15 16765#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET__SHIFT 0x0 16766#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET_MASK 0xFFFFFFFFL 16767//PA_CL_UCP_0_X 16768#define PA_CL_UCP_0_X__DATA_REGISTER__SHIFT 0x0 16769#define PA_CL_UCP_0_X__DATA_REGISTER_MASK 0xFFFFFFFFL 16770//PA_CL_UCP_0_Y 16771#define PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT 0x0 16772#define PA_CL_UCP_0_Y__DATA_REGISTER_MASK 0xFFFFFFFFL 16773//PA_CL_UCP_0_Z 16774#define PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT 0x0 16775#define PA_CL_UCP_0_Z__DATA_REGISTER_MASK 0xFFFFFFFFL 16776//PA_CL_UCP_0_W 16777#define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT 0x0 16778#define PA_CL_UCP_0_W__DATA_REGISTER_MASK 0xFFFFFFFFL 16779//PA_CL_UCP_1_X 16780#define PA_CL_UCP_1_X__DATA_REGISTER__SHIFT 0x0 16781#define PA_CL_UCP_1_X__DATA_REGISTER_MASK 0xFFFFFFFFL 16782//PA_CL_UCP_1_Y 16783#define PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT 0x0 16784#define PA_CL_UCP_1_Y__DATA_REGISTER_MASK 0xFFFFFFFFL 16785//PA_CL_UCP_1_Z 16786#define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT 0x0 16787#define PA_CL_UCP_1_Z__DATA_REGISTER_MASK 0xFFFFFFFFL 16788//PA_CL_UCP_1_W 16789#define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT 0x0 16790#define PA_CL_UCP_1_W__DATA_REGISTER_MASK 0xFFFFFFFFL 16791//PA_CL_UCP_2_X 16792#define PA_CL_UCP_2_X__DATA_REGISTER__SHIFT 0x0 16793#define PA_CL_UCP_2_X__DATA_REGISTER_MASK 0xFFFFFFFFL 16794//PA_CL_UCP_2_Y 16795#define PA_CL_UCP_2_Y__DATA_REGISTER__SHIFT 0x0 16796#define PA_CL_UCP_2_Y__DATA_REGISTER_MASK 0xFFFFFFFFL 16797//PA_CL_UCP_2_Z 16798#define PA_CL_UCP_2_Z__DATA_REGISTER__SHIFT 0x0 16799#define PA_CL_UCP_2_Z__DATA_REGISTER_MASK 0xFFFFFFFFL 16800//PA_CL_UCP_2_W 16801#define PA_CL_UCP_2_W__DATA_REGISTER__SHIFT 0x0 16802#define PA_CL_UCP_2_W__DATA_REGISTER_MASK 0xFFFFFFFFL 16803//PA_CL_UCP_3_X 16804#define PA_CL_UCP_3_X__DATA_REGISTER__SHIFT 0x0 16805#define PA_CL_UCP_3_X__DATA_REGISTER_MASK 0xFFFFFFFFL 16806//PA_CL_UCP_3_Y 16807#define PA_CL_UCP_3_Y__DATA_REGISTER__SHIFT 0x0 16808#define PA_CL_UCP_3_Y__DATA_REGISTER_MASK 0xFFFFFFFFL 16809//PA_CL_UCP_3_Z 16810#define PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT 0x0 16811#define PA_CL_UCP_3_Z__DATA_REGISTER_MASK 0xFFFFFFFFL 16812//PA_CL_UCP_3_W 16813#define PA_CL_UCP_3_W__DATA_REGISTER__SHIFT 0x0 16814#define PA_CL_UCP_3_W__DATA_REGISTER_MASK 0xFFFFFFFFL 16815//PA_CL_UCP_4_X 16816#define PA_CL_UCP_4_X__DATA_REGISTER__SHIFT 0x0 16817#define PA_CL_UCP_4_X__DATA_REGISTER_MASK 0xFFFFFFFFL 16818//PA_CL_UCP_4_Y 16819#define PA_CL_UCP_4_Y__DATA_REGISTER__SHIFT 0x0 16820#define PA_CL_UCP_4_Y__DATA_REGISTER_MASK 0xFFFFFFFFL 16821//PA_CL_UCP_4_Z 16822#define PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT 0x0 16823#define PA_CL_UCP_4_Z__DATA_REGISTER_MASK 0xFFFFFFFFL 16824//PA_CL_UCP_4_W 16825#define PA_CL_UCP_4_W__DATA_REGISTER__SHIFT 0x0 16826#define PA_CL_UCP_4_W__DATA_REGISTER_MASK 0xFFFFFFFFL 16827//PA_CL_UCP_5_X 16828#define PA_CL_UCP_5_X__DATA_REGISTER__SHIFT 0x0 16829#define PA_CL_UCP_5_X__DATA_REGISTER_MASK 0xFFFFFFFFL 16830//PA_CL_UCP_5_Y 16831#define PA_CL_UCP_5_Y__DATA_REGISTER__SHIFT 0x0 16832#define PA_CL_UCP_5_Y__DATA_REGISTER_MASK 0xFFFFFFFFL 16833//PA_CL_UCP_5_Z 16834#define PA_CL_UCP_5_Z__DATA_REGISTER__SHIFT 0x0 16835#define PA_CL_UCP_5_Z__DATA_REGISTER_MASK 0xFFFFFFFFL 16836//PA_CL_UCP_5_W 16837#define PA_CL_UCP_5_W__DATA_REGISTER__SHIFT 0x0 16838#define PA_CL_UCP_5_W__DATA_REGISTER_MASK 0xFFFFFFFFL 16839//SPI_PS_INPUT_CNTL_0 16840#define SPI_PS_INPUT_CNTL_0__OFFSET__SHIFT 0x0 16841#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL__SHIFT 0x8 16842#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE__SHIFT 0xa 16843#define SPI_PS_INPUT_CNTL_0__CYL_WRAP__SHIFT 0xd 16844#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX__SHIFT 0x11 16845#define SPI_PS_INPUT_CNTL_0__DUP__SHIFT 0x12 16846#define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE__SHIFT 0x13 16847#define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1__SHIFT 0x14 16848#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1__SHIFT 0x15 16849#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 16850#define SPI_PS_INPUT_CNTL_0__ATTR0_VALID__SHIFT 0x18 16851#define SPI_PS_INPUT_CNTL_0__ATTR1_VALID__SHIFT 0x19 16852#define SPI_PS_INPUT_CNTL_0__OFFSET_MASK 0x0000003FL 16853#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK 0x00000300L 16854#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE_MASK 0x00000400L 16855#define SPI_PS_INPUT_CNTL_0__CYL_WRAP_MASK 0x0001E000L 16856#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_MASK 0x00020000L 16857#define SPI_PS_INPUT_CNTL_0__DUP_MASK 0x00040000L 16858#define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE_MASK 0x00080000L 16859#define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1_MASK 0x00100000L 16860#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1_MASK 0x00600000L 16861#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L 16862#define SPI_PS_INPUT_CNTL_0__ATTR0_VALID_MASK 0x01000000L 16863#define SPI_PS_INPUT_CNTL_0__ATTR1_VALID_MASK 0x02000000L 16864//SPI_PS_INPUT_CNTL_1 16865#define SPI_PS_INPUT_CNTL_1__OFFSET__SHIFT 0x0 16866#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL__SHIFT 0x8 16867#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE__SHIFT 0xa 16868#define SPI_PS_INPUT_CNTL_1__CYL_WRAP__SHIFT 0xd 16869#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX__SHIFT 0x11 16870#define SPI_PS_INPUT_CNTL_1__DUP__SHIFT 0x12 16871#define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE__SHIFT 0x13 16872#define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1__SHIFT 0x14 16873#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1__SHIFT 0x15 16874#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 16875#define SPI_PS_INPUT_CNTL_1__ATTR0_VALID__SHIFT 0x18 16876#define SPI_PS_INPUT_CNTL_1__ATTR1_VALID__SHIFT 0x19 16877#define SPI_PS_INPUT_CNTL_1__OFFSET_MASK 0x0000003FL 16878#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_MASK 0x00000300L 16879#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE_MASK 0x00000400L 16880#define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK 0x0001E000L 16881#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_MASK 0x00020000L 16882#define SPI_PS_INPUT_CNTL_1__DUP_MASK 0x00040000L 16883#define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE_MASK 0x00080000L 16884#define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1_MASK 0x00100000L 16885#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1_MASK 0x00600000L 16886#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L 16887#define SPI_PS_INPUT_CNTL_1__ATTR0_VALID_MASK 0x01000000L 16888#define SPI_PS_INPUT_CNTL_1__ATTR1_VALID_MASK 0x02000000L 16889//SPI_PS_INPUT_CNTL_2 16890#define SPI_PS_INPUT_CNTL_2__OFFSET__SHIFT 0x0 16891#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL__SHIFT 0x8 16892#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE__SHIFT 0xa 16893#define SPI_PS_INPUT_CNTL_2__CYL_WRAP__SHIFT 0xd 16894#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX__SHIFT 0x11 16895#define SPI_PS_INPUT_CNTL_2__DUP__SHIFT 0x12 16896#define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE__SHIFT 0x13 16897#define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1__SHIFT 0x14 16898#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1__SHIFT 0x15 16899#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 16900#define SPI_PS_INPUT_CNTL_2__ATTR0_VALID__SHIFT 0x18 16901#define SPI_PS_INPUT_CNTL_2__ATTR1_VALID__SHIFT 0x19 16902#define SPI_PS_INPUT_CNTL_2__OFFSET_MASK 0x0000003FL 16903#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_MASK 0x00000300L 16904#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE_MASK 0x00000400L 16905#define SPI_PS_INPUT_CNTL_2__CYL_WRAP_MASK 0x0001E000L 16906#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_MASK 0x00020000L 16907#define SPI_PS_INPUT_CNTL_2__DUP_MASK 0x00040000L 16908#define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE_MASK 0x00080000L 16909#define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1_MASK 0x00100000L 16910#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1_MASK 0x00600000L 16911#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L 16912#define SPI_PS_INPUT_CNTL_2__ATTR0_VALID_MASK 0x01000000L 16913#define SPI_PS_INPUT_CNTL_2__ATTR1_VALID_MASK 0x02000000L 16914//SPI_PS_INPUT_CNTL_3 16915#define SPI_PS_INPUT_CNTL_3__OFFSET__SHIFT 0x0 16916#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL__SHIFT 0x8 16917#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE__SHIFT 0xa 16918#define SPI_PS_INPUT_CNTL_3__CYL_WRAP__SHIFT 0xd 16919#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX__SHIFT 0x11 16920#define SPI_PS_INPUT_CNTL_3__DUP__SHIFT 0x12 16921#define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE__SHIFT 0x13 16922#define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1__SHIFT 0x14 16923#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1__SHIFT 0x15 16924#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 16925#define SPI_PS_INPUT_CNTL_3__ATTR0_VALID__SHIFT 0x18 16926#define SPI_PS_INPUT_CNTL_3__ATTR1_VALID__SHIFT 0x19 16927#define SPI_PS_INPUT_CNTL_3__OFFSET_MASK 0x0000003FL 16928#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_MASK 0x00000300L 16929#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE_MASK 0x00000400L 16930#define SPI_PS_INPUT_CNTL_3__CYL_WRAP_MASK 0x0001E000L 16931#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_MASK 0x00020000L 16932#define SPI_PS_INPUT_CNTL_3__DUP_MASK 0x00040000L 16933#define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE_MASK 0x00080000L 16934#define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1_MASK 0x00100000L 16935#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1_MASK 0x00600000L 16936#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L 16937#define SPI_PS_INPUT_CNTL_3__ATTR0_VALID_MASK 0x01000000L 16938#define SPI_PS_INPUT_CNTL_3__ATTR1_VALID_MASK 0x02000000L 16939//SPI_PS_INPUT_CNTL_4 16940#define SPI_PS_INPUT_CNTL_4__OFFSET__SHIFT 0x0 16941#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL__SHIFT 0x8 16942#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE__SHIFT 0xa 16943#define SPI_PS_INPUT_CNTL_4__CYL_WRAP__SHIFT 0xd 16944#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX__SHIFT 0x11 16945#define SPI_PS_INPUT_CNTL_4__DUP__SHIFT 0x12 16946#define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE__SHIFT 0x13 16947#define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1__SHIFT 0x14 16948#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1__SHIFT 0x15 16949#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 16950#define SPI_PS_INPUT_CNTL_4__ATTR0_VALID__SHIFT 0x18 16951#define SPI_PS_INPUT_CNTL_4__ATTR1_VALID__SHIFT 0x19 16952#define SPI_PS_INPUT_CNTL_4__OFFSET_MASK 0x0000003FL 16953#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK 0x00000300L 16954#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE_MASK 0x00000400L 16955#define SPI_PS_INPUT_CNTL_4__CYL_WRAP_MASK 0x0001E000L 16956#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_MASK 0x00020000L 16957#define SPI_PS_INPUT_CNTL_4__DUP_MASK 0x00040000L 16958#define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE_MASK 0x00080000L 16959#define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1_MASK 0x00100000L 16960#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1_MASK 0x00600000L 16961#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L 16962#define SPI_PS_INPUT_CNTL_4__ATTR0_VALID_MASK 0x01000000L 16963#define SPI_PS_INPUT_CNTL_4__ATTR1_VALID_MASK 0x02000000L 16964//SPI_PS_INPUT_CNTL_5 16965#define SPI_PS_INPUT_CNTL_5__OFFSET__SHIFT 0x0 16966#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL__SHIFT 0x8 16967#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE__SHIFT 0xa 16968#define SPI_PS_INPUT_CNTL_5__CYL_WRAP__SHIFT 0xd 16969#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX__SHIFT 0x11 16970#define SPI_PS_INPUT_CNTL_5__DUP__SHIFT 0x12 16971#define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE__SHIFT 0x13 16972#define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1__SHIFT 0x14 16973#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1__SHIFT 0x15 16974#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 16975#define SPI_PS_INPUT_CNTL_5__ATTR0_VALID__SHIFT 0x18 16976#define SPI_PS_INPUT_CNTL_5__ATTR1_VALID__SHIFT 0x19 16977#define SPI_PS_INPUT_CNTL_5__OFFSET_MASK 0x0000003FL 16978#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_MASK 0x00000300L 16979#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE_MASK 0x00000400L 16980#define SPI_PS_INPUT_CNTL_5__CYL_WRAP_MASK 0x0001E000L 16981#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_MASK 0x00020000L 16982#define SPI_PS_INPUT_CNTL_5__DUP_MASK 0x00040000L 16983#define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE_MASK 0x00080000L 16984#define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1_MASK 0x00100000L 16985#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1_MASK 0x00600000L 16986#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L 16987#define SPI_PS_INPUT_CNTL_5__ATTR0_VALID_MASK 0x01000000L 16988#define SPI_PS_INPUT_CNTL_5__ATTR1_VALID_MASK 0x02000000L 16989//SPI_PS_INPUT_CNTL_6 16990#define SPI_PS_INPUT_CNTL_6__OFFSET__SHIFT 0x0 16991#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL__SHIFT 0x8 16992#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE__SHIFT 0xa 16993#define SPI_PS_INPUT_CNTL_6__CYL_WRAP__SHIFT 0xd 16994#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX__SHIFT 0x11 16995#define SPI_PS_INPUT_CNTL_6__DUP__SHIFT 0x12 16996#define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE__SHIFT 0x13 16997#define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1__SHIFT 0x14 16998#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1__SHIFT 0x15 16999#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 17000#define SPI_PS_INPUT_CNTL_6__ATTR0_VALID__SHIFT 0x18
17001#define SPI_PS_INPUT_CNTL_6__ATTR1_VALID__SHIFT 0x19 17002#define SPI_PS_INPUT_CNTL_6__OFFSET_MASK 0x0000003FL 17003#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_MASK 0x00000300L 17004#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE_MASK 0x00000400L 17005#define SPI_PS_INPUT_CNTL_6__CYL_WRAP_MASK 0x0001E000L 17006#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_MASK 0x00020000L 17007#define SPI_PS_INPUT_CNTL_6__DUP_MASK 0x00040000L 17008#define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE_MASK 0x00080000L 17009#define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1_MASK 0x00100000L 17010#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1_MASK 0x00600000L 17011#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L 17012#define SPI_PS_INPUT_CNTL_6__ATTR0_VALID_MASK 0x01000000L 17013#define SPI_PS_INPUT_CNTL_6__ATTR1_VALID_MASK 0x02000000L 17014//SPI_PS_INPUT_CNTL_7 17015#define SPI_PS_INPUT_CNTL_7__OFFSET__SHIFT 0x0 17016#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL__SHIFT 0x8 17017#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE__SHIFT 0xa 17018#define SPI_PS_INPUT_CNTL_7__CYL_WRAP__SHIFT 0xd 17019#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX__SHIFT 0x11 17020#define SPI_PS_INPUT_CNTL_7__DUP__SHIFT 0x12 17021#define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE__SHIFT 0x13 17022#define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1__SHIFT 0x14 17023#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1__SHIFT 0x15 17024#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 17025#define SPI_PS_INPUT_CNTL_7__ATTR0_VALID__SHIFT 0x18 17026#define SPI_PS_INPUT_CNTL_7__ATTR1_VALID__SHIFT 0x19 17027#define SPI_PS_INPUT_CNTL_7__OFFSET_MASK 0x0000003FL 17028#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_MASK 0x00000300L 17029#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE_MASK 0x00000400L 17030#define SPI_PS_INPUT_CNTL_7__CYL_WRAP_MASK 0x0001E000L 17031#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_MASK 0x00020000L 17032#define SPI_PS_INPUT_CNTL_7__DUP_MASK 0x00040000L 17033#define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE_MASK 0x00080000L 17034#define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1_MASK 0x00100000L 17035#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1_MASK 0x00600000L 17036#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L 17037#define SPI_PS_INPUT_CNTL_7__ATTR0_VALID_MASK 0x01000000L 17038#define SPI_PS_INPUT_CNTL_7__ATTR1_VALID_MASK 0x02000000L 17039//SPI_PS_INPUT_CNTL_8 17040#define SPI_PS_INPUT_CNTL_8__OFFSET__SHIFT 0x0 17041#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL__SHIFT 0x8 17042#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE__SHIFT 0xa 17043#define SPI_PS_INPUT_CNTL_8__CYL_WRAP__SHIFT 0xd 17044#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX__SHIFT 0x11 17045#define SPI_PS_INPUT_CNTL_8__DUP__SHIFT 0x12 17046#define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE__SHIFT 0x13 17047#define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1__SHIFT 0x14 17048#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1__SHIFT 0x15 17049#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 17050#define SPI_PS_INPUT_CNTL_8__ATTR0_VALID__SHIFT 0x18 17051#define SPI_PS_INPUT_CNTL_8__ATTR1_VALID__SHIFT 0x19 17052#define SPI_PS_INPUT_CNTL_8__OFFSET_MASK 0x0000003FL 17053#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_MASK 0x00000300L 17054#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE_MASK 0x00000400L 17055#define SPI_PS_INPUT_CNTL_8__CYL_WRAP_MASK 0x0001E000L 17056#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_MASK 0x00020000L 17057#define SPI_PS_INPUT_CNTL_8__DUP_MASK 0x00040000L 17058#define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE_MASK 0x00080000L 17059#define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1_MASK 0x00100000L 17060#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1_MASK 0x00600000L 17061#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L 17062#define SPI_PS_INPUT_CNTL_8__ATTR0_VALID_MASK 0x01000000L 17063#define SPI_PS_INPUT_CNTL_8__ATTR1_VALID_MASK 0x02000000L 17064//SPI_PS_INPUT_CNTL_9 17065#define SPI_PS_INPUT_CNTL_9__OFFSET__SHIFT 0x0 17066#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL__SHIFT 0x8 17067#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE__SHIFT 0xa 17068#define SPI_PS_INPUT_CNTL_9__CYL_WRAP__SHIFT 0xd 17069#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX__SHIFT 0x11 17070#define SPI_PS_INPUT_CNTL_9__DUP__SHIFT 0x12 17071#define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE__SHIFT 0x13 17072#define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1__SHIFT 0x14 17073#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1__SHIFT 0x15 17074#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 17075#define SPI_PS_INPUT_CNTL_9__ATTR0_VALID__SHIFT 0x18 17076#define SPI_PS_INPUT_CNTL_9__ATTR1_VALID__SHIFT 0x19 17077#define SPI_PS_INPUT_CNTL_9__OFFSET_MASK 0x0000003FL 17078#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_MASK 0x00000300L 17079#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE_MASK 0x00000400L 17080#define SPI_PS_INPUT_CNTL_9__CYL_WRAP_MASK 0x0001E000L 17081#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_MASK 0x00020000L 17082#define SPI_PS_INPUT_CNTL_9__DUP_MASK 0x00040000L 17083#define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE_MASK 0x00080000L 17084#define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1_MASK 0x00100000L 17085#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1_MASK 0x00600000L 17086#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L 17087#define SPI_PS_INPUT_CNTL_9__ATTR0_VALID_MASK 0x01000000L 17088#define SPI_PS_INPUT_CNTL_9__ATTR1_VALID_MASK 0x02000000L 17089//SPI_PS_INPUT_CNTL_10 17090#define SPI_PS_INPUT_CNTL_10__OFFSET__SHIFT 0x0 17091#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL__SHIFT 0x8 17092#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE__SHIFT 0xa 17093#define SPI_PS_INPUT_CNTL_10__CYL_WRAP__SHIFT 0xd 17094#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX__SHIFT 0x11 17095#define SPI_PS_INPUT_CNTL_10__DUP__SHIFT 0x12 17096#define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE__SHIFT 0x13 17097#define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1__SHIFT 0x14 17098#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1__SHIFT 0x15 17099#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 17100#define SPI_PS_INPUT_CNTL_10__ATTR0_VALID__SHIFT 0x18 17101#define SPI_PS_INPUT_CNTL_10__ATTR1_VALID__SHIFT 0x19 17102#define SPI_PS_INPUT_CNTL_10__OFFSET_MASK 0x0000003FL 17103#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_MASK 0x00000300L 17104#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE_MASK 0x00000400L 17105#define SPI_PS_INPUT_CNTL_10__CYL_WRAP_MASK 0x0001E000L 17106#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_MASK 0x00020000L 17107#define SPI_PS_INPUT_CNTL_10__DUP_MASK 0x00040000L 17108#define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE_MASK 0x00080000L 17109#define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1_MASK 0x00100000L 17110#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1_MASK 0x00600000L 17111#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L 17112#define SPI_PS_INPUT_CNTL_10__ATTR0_VALID_MASK 0x01000000L 17113#define SPI_PS_INPUT_CNTL_10__ATTR1_VALID_MASK 0x02000000L 17114//SPI_PS_INPUT_CNTL_11 17115#define SPI_PS_INPUT_CNTL_11__OFFSET__SHIFT 0x0 17116#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL__SHIFT 0x8 17117#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE__SHIFT 0xa 17118#define SPI_PS_INPUT_CNTL_11__CYL_WRAP__SHIFT 0xd 17119#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX__SHIFT 0x11 17120#define SPI_PS_INPUT_CNTL_11__DUP__SHIFT 0x12 17121#define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE__SHIFT 0x13 17122#define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1__SHIFT 0x14 17123#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1__SHIFT 0x15 17124#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 17125#define SPI_PS_INPUT_CNTL_11__ATTR0_VALID__SHIFT 0x18 17126#define SPI_PS_INPUT_CNTL_11__ATTR1_VALID__SHIFT 0x19 17127#define SPI_PS_INPUT_CNTL_11__OFFSET_MASK 0x0000003FL 17128#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_MASK 0x00000300L 17129#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE_MASK 0x00000400L 17130#define SPI_PS_INPUT_CNTL_11__CYL_WRAP_MASK 0x0001E000L 17131#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_MASK 0x00020000L 17132#define SPI_PS_INPUT_CNTL_11__DUP_MASK 0x00040000L 17133#define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE_MASK 0x00080000L 17134#define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1_MASK 0x00100000L 17135#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1_MASK 0x00600000L 17136#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L 17137#define SPI_PS_INPUT_CNTL_11__ATTR0_VALID_MASK 0x01000000L 17138#define SPI_PS_INPUT_CNTL_11__ATTR1_VALID_MASK 0x02000000L 17139//SPI_PS_INPUT_CNTL_12 17140#define SPI_PS_INPUT_CNTL_12__OFFSET__SHIFT 0x0 17141#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL__SHIFT 0x8 17142#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE__SHIFT 0xa 17143#define SPI_PS_INPUT_CNTL_12__CYL_WRAP__SHIFT 0xd 17144#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX__SHIFT 0x11 17145#define SPI_PS_INPUT_CNTL_12__DUP__SHIFT 0x12 17146#define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE__SHIFT 0x13 17147#define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1__SHIFT 0x14 17148#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1__SHIFT 0x15 17149#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 17150#define SPI_PS_INPUT_CNTL_12__ATTR0_VALID__SHIFT 0x18 17151#define SPI_PS_INPUT_CNTL_12__ATTR1_VALID__SHIFT 0x19 17152#define SPI_PS_INPUT_CNTL_12__OFFSET_MASK 0x0000003FL 17153#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_MASK 0x00000300L 17154#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE_MASK 0x00000400L 17155#define SPI_PS_INPUT_CNTL_12__CYL_WRAP_MASK 0x0001E000L 17156#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_MASK 0x00020000L 17157#define SPI_PS_INPUT_CNTL_12__DUP_MASK 0x00040000L 17158#define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE_MASK 0x00080000L 17159#define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1_MASK 0x00100000L 17160#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1_MASK 0x00600000L 17161#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L 17162#define SPI_PS_INPUT_CNTL_12__ATTR0_VALID_MASK 0x01000000L 17163#define SPI_PS_INPUT_CNTL_12__ATTR1_VALID_MASK 0x02000000L 17164//SPI_PS_INPUT_CNTL_13 17165#define SPI_PS_INPUT_CNTL_13__OFFSET__SHIFT 0x0 17166#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL__SHIFT 0x8 17167#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE__SHIFT 0xa 17168#define SPI_PS_INPUT_CNTL_13__CYL_WRAP__SHIFT 0xd 17169#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX__SHIFT 0x11 17170#define SPI_PS_INPUT_CNTL_13__DUP__SHIFT 0x12 17171#define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE__SHIFT 0x13 17172#define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1__SHIFT 0x14 17173#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1__SHIFT 0x15 17174#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 17175#define SPI_PS_INPUT_CNTL_13__ATTR0_VALID__SHIFT 0x18 17176#define SPI_PS_INPUT_CNTL_13__ATTR1_VALID__SHIFT 0x19 17177#define SPI_PS_INPUT_CNTL_13__OFFSET_MASK 0x0000003FL 17178#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_MASK 0x00000300L 17179#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE_MASK 0x00000400L 17180#define SPI_PS_INPUT_CNTL_13__CYL_WRAP_MASK 0x0001E000L 17181#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_MASK 0x00020000L 17182#define SPI_PS_INPUT_CNTL_13__DUP_MASK 0x00040000L 17183#define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE_MASK 0x00080000L 17184#define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1_MASK 0x00100000L 17185#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1_MASK 0x00600000L 17186#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L 17187#define SPI_PS_INPUT_CNTL_13__ATTR0_VALID_MASK 0x01000000L 17188#define SPI_PS_INPUT_CNTL_13__ATTR1_VALID_MASK 0x02000000L 17189//SPI_PS_INPUT_CNTL_14 17190#define SPI_PS_INPUT_CNTL_14__OFFSET__SHIFT 0x0 17191#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL__SHIFT 0x8 17192#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE__SHIFT 0xa 17193#define SPI_PS_INPUT_CNTL_14__CYL_WRAP__SHIFT 0xd 17194#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX__SHIFT 0x11 17195#define SPI_PS_INPUT_CNTL_14__DUP__SHIFT 0x12 17196#define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE__SHIFT 0x13 17197#define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1__SHIFT 0x14 17198#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1__SHIFT 0x15 17199#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 17200#define SPI_PS_INPUT_CNTL_14__ATTR0_VALID__SHIFT 0x18 17201#define SPI_PS_INPUT_CNTL_14__ATTR1_VALID__SHIFT 0x19 17202#define SPI_PS_INPUT_CNTL_14__OFFSET_MASK 0x0000003FL 17203#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_MASK 0x00000300L 17204#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE_MASK 0x00000400L 17205#define SPI_PS_INPUT_CNTL_14__CYL_WRAP_MASK 0x0001E000L 17206#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_MASK 0x00020000L 17207#define SPI_PS_INPUT_CNTL_14__DUP_MASK 0x00040000L 17208#define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE_MASK 0x00080000L 17209#define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1_MASK 0x00100000L 17210#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1_MASK 0x00600000L 17211#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L 17212#define SPI_PS_INPUT_CNTL_14__ATTR0_VALID_MASK 0x01000000L 17213#define SPI_PS_INPUT_CNTL_14__ATTR1_VALID_MASK 0x02000000L 17214//SPI_PS_INPUT_CNTL_15 17215#define SPI_PS_INPUT_CNTL_15__OFFSET__SHIFT 0x0 17216#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL__SHIFT 0x8 17217#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE__SHIFT 0xa 17218#define SPI_PS_INPUT_CNTL_15__CYL_WRAP__SHIFT 0xd 17219#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX__SHIFT 0x11 17220#define SPI_PS_INPUT_CNTL_15__DUP__SHIFT 0x12 17221#define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE__SHIFT 0x13 17222#define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1__SHIFT 0x14 17223#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1__SHIFT 0x15 17224#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 17225#define SPI_PS_INPUT_CNTL_15__ATTR0_VALID__SHIFT 0x18 17226#define SPI_PS_INPUT_CNTL_15__ATTR1_VALID__SHIFT 0x19 17227#define SPI_PS_INPUT_CNTL_15__OFFSET_MASK 0x0000003FL 17228#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_MASK 0x00000300L 17229#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE_MASK 0x00000400L 17230#define SPI_PS_INPUT_CNTL_15__CYL_WRAP_MASK 0x0001E000L 17231#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_MASK 0x00020000L 17232#define SPI_PS_INPUT_CNTL_15__DUP_MASK 0x00040000L 17233#define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE_MASK 0x00080000L 17234#define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1_MASK 0x00100000L 17235#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1_MASK 0x00600000L 17236#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L 17237#define SPI_PS_INPUT_CNTL_15__ATTR0_VALID_MASK 0x01000000L 17238#define SPI_PS_INPUT_CNTL_15__ATTR1_VALID_MASK 0x02000000L 17239//SPI_PS_INPUT_CNTL_16 17240#define SPI_PS_INPUT_CNTL_16__OFFSET__SHIFT 0x0 17241#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL__SHIFT 0x8 17242#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE__SHIFT 0xa 17243#define SPI_PS_INPUT_CNTL_16__CYL_WRAP__SHIFT 0xd 17244#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX__SHIFT 0x11 17245#define SPI_PS_INPUT_CNTL_16__DUP__SHIFT 0x12 17246#define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE__SHIFT 0x13 17247#define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1__SHIFT 0x14 17248#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1__SHIFT 0x15 17249#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 17250#define SPI_PS_INPUT_CNTL_16__ATTR0_VALID__SHIFT 0x18 17251#define SPI_PS_INPUT_CNTL_16__ATTR1_VALID__SHIFT 0x19 17252#define SPI_PS_INPUT_CNTL_16__OFFSET_MASK 0x0000003FL 17253#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_MASK 0x00000300L 17254#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE_MASK 0x00000400L 17255#define SPI_PS_INPUT_CNTL_16__CYL_WRAP_MASK 0x0001E000L 17256#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_MASK 0x00020000L 17257#define SPI_PS_INPUT_CNTL_16__DUP_MASK 0x00040000L 17258#define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE_MASK 0x00080000L 17259#define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1_MASK 0x00100000L 17260#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1_MASK 0x00600000L 17261#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L 17262#define SPI_PS_INPUT_CNTL_16__ATTR0_VALID_MASK 0x01000000L 17263#define SPI_PS_INPUT_CNTL_16__ATTR1_VALID_MASK 0x02000000L 17264//SPI_PS_INPUT_CNTL_17 17265#define SPI_PS_INPUT_CNTL_17__OFFSET__SHIFT 0x0 17266#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL__SHIFT 0x8 17267#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE__SHIFT 0xa 17268#define SPI_PS_INPUT_CNTL_17__CYL_WRAP__SHIFT 0xd 17269#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX__SHIFT 0x11 17270#define SPI_PS_INPUT_CNTL_17__DUP__SHIFT 0x12 17271#define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE__SHIFT 0x13 17272#define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1__SHIFT 0x14 17273#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1__SHIFT 0x15 17274#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 17275#define SPI_PS_INPUT_CNTL_17__ATTR0_VALID__SHIFT 0x18 17276#define SPI_PS_INPUT_CNTL_17__ATTR1_VALID__SHIFT 0x19 17277#define SPI_PS_INPUT_CNTL_17__OFFSET_MASK 0x0000003FL 17278#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_MASK 0x00000300L 17279#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE_MASK 0x00000400L 17280#define SPI_PS_INPUT_CNTL_17__CYL_WRAP_MASK 0x0001E000L 17281#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_MASK 0x00020000L 17282#define SPI_PS_INPUT_CNTL_17__DUP_MASK 0x00040000L 17283#define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE_MASK 0x00080000L 17284#define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1_MASK 0x00100000L 17285#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1_MASK 0x00600000L 17286#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L 17287#define SPI_PS_INPUT_CNTL_17__ATTR0_VALID_MASK 0x01000000L 17288#define SPI_PS_INPUT_CNTL_17__ATTR1_VALID_MASK 0x02000000L 17289//SPI_PS_INPUT_CNTL_18 17290#define SPI_PS_INPUT_CNTL_18__OFFSET__SHIFT 0x0 17291#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL__SHIFT 0x8 17292#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE__SHIFT 0xa 17293#define SPI_PS_INPUT_CNTL_18__CYL_WRAP__SHIFT 0xd 17294#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX__SHIFT 0x11 17295#define SPI_PS_INPUT_CNTL_18__DUP__SHIFT 0x12 17296#define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE__SHIFT 0x13 17297#define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1__SHIFT 0x14 17298#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1__SHIFT 0x15 17299#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 17300#define SPI_PS_INPUT_CNTL_18__ATTR0_VALID__SHIFT 0x18 17301#define SPI_PS_INPUT_CNTL_18__ATTR1_VALID__SHIFT 0x19 17302#define SPI_PS_INPUT_CNTL_18__OFFSET_MASK 0x0000003FL 17303#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_MASK 0x00000300L 17304#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE_MASK 0x00000400L 17305#define SPI_PS_INPUT_CNTL_18__CYL_WRAP_MASK 0x0001E000L 17306#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_MASK 0x00020000L 17307#define SPI_PS_INPUT_CNTL_18__DUP_MASK 0x00040000L 17308#define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE_MASK 0x00080000L 17309#define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1_MASK 0x00100000L 17310#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1_MASK 0x00600000L 17311#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L 17312#define SPI_PS_INPUT_CNTL_18__ATTR0_VALID_MASK 0x01000000L 17313#define SPI_PS_INPUT_CNTL_18__ATTR1_VALID_MASK 0x02000000L 17314//SPI_PS_INPUT_CNTL_19 17315#define SPI_PS_INPUT_CNTL_19__OFFSET__SHIFT 0x0 17316#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL__SHIFT 0x8 17317#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE__SHIFT 0xa 17318#define SPI_PS_INPUT_CNTL_19__CYL_WRAP__SHIFT 0xd 17319#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX__SHIFT 0x11 17320#define SPI_PS_INPUT_CNTL_19__DUP__SHIFT 0x12 17321#define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE__SHIFT 0x13 17322#define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1__SHIFT 0x14 17323#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1__SHIFT 0x15 17324#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 17325#define SPI_PS_INPUT_CNTL_19__ATTR0_VALID__SHIFT 0x18 17326#define SPI_PS_INPUT_CNTL_19__ATTR1_VALID__SHIFT 0x19 17327#define SPI_PS_INPUT_CNTL_19__OFFSET_MASK 0x0000003FL 17328#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_MASK 0x00000300L 17329#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE_MASK 0x00000400L 17330#define SPI_PS_INPUT_CNTL_19__CYL_WRAP_MASK 0x0001E000L 17331#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_MASK 0x00020000L 17332#define SPI_PS_INPUT_CNTL_19__DUP_MASK 0x00040000L 17333#define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE_MASK 0x00080000L 17334#define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1_MASK 0x00100000L 17335#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1_MASK 0x00600000L 17336#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L 17337#define SPI_PS_INPUT_CNTL_19__ATTR0_VALID_MASK 0x01000000L 17338#define SPI_PS_INPUT_CNTL_19__ATTR1_VALID_MASK 0x02000000L 17339//SPI_PS_INPUT_CNTL_20 17340#define SPI_PS_INPUT_CNTL_20__OFFSET__SHIFT 0x0 17341#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL__SHIFT 0x8 17342#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE__SHIFT 0xa 17343#define SPI_PS_INPUT_CNTL_20__DUP__SHIFT 0x12 17344#define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE__SHIFT 0x13 17345#define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1__SHIFT 0x14 17346#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1__SHIFT 0x15 17347#define SPI_PS_INPUT_CNTL_20__ATTR0_VALID__SHIFT 0x18 17348#define SPI_PS_INPUT_CNTL_20__ATTR1_VALID__SHIFT 0x19 17349#define SPI_PS_INPUT_CNTL_20__OFFSET_MASK 0x0000003FL 17350#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_MASK 0x00000300L 17351#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE_MASK 0x00000400L 17352#define SPI_PS_INPUT_CNTL_20__DUP_MASK 0x00040000L 17353#define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE_MASK 0x00080000L 17354#define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1_MASK 0x00100000L 17355#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1_MASK 0x00600000L 17356#define SPI_PS_INPUT_CNTL_20__ATTR0_VALID_MASK 0x01000000L 17357#define SPI_PS_INPUT_CNTL_20__ATTR1_VALID_MASK 0x02000000L 17358//SPI_PS_INPUT_CNTL_21 17359#define SPI_PS_INPUT_CNTL_21__OFFSET__SHIFT 0x0 17360#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL__SHIFT 0x8 17361#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE__SHIFT 0xa 17362#define SPI_PS_INPUT_CNTL_21__DUP__SHIFT 0x12 17363#define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE__SHIFT 0x13 17364#define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1__SHIFT 0x14 17365#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1__SHIFT 0x15 17366#define SPI_PS_INPUT_CNTL_21__ATTR0_VALID__SHIFT 0x18 17367#define SPI_PS_INPUT_CNTL_21__ATTR1_VALID__SHIFT 0x19 17368#define SPI_PS_INPUT_CNTL_21__OFFSET_MASK 0x0000003FL 17369#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_MASK 0x00000300L 17370#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE_MASK 0x00000400L 17371#define SPI_PS_INPUT_CNTL_21__DUP_MASK 0x00040000L 17372#define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE_MASK 0x00080000L 17373#define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1_MASK 0x00100000L 17374#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1_MASK 0x00600000L 17375#define SPI_PS_INPUT_CNTL_21__ATTR0_VALID_MASK 0x01000000L 17376#define SPI_PS_INPUT_CNTL_21__ATTR1_VALID_MASK 0x02000000L 17377//SPI_PS_INPUT_CNTL_22 17378#define SPI_PS_INPUT_CNTL_22__OFFSET__SHIFT 0x0 17379#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL__SHIFT 0x8 17380#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE__SHIFT 0xa 17381#define SPI_PS_INPUT_CNTL_22__DUP__SHIFT 0x12 17382#define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE__SHIFT 0x13 17383#define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1__SHIFT 0x14 17384#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1__SHIFT 0x15 17385#define SPI_PS_INPUT_CNTL_22__ATTR0_VALID__SHIFT 0x18 17386#define SPI_PS_INPUT_CNTL_22__ATTR1_VALID__SHIFT 0x19 17387#define SPI_PS_INPUT_CNTL_22__OFFSET_MASK 0x0000003FL 17388#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_MASK 0x00000300L 17389#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE_MASK 0x00000400L 17390#define SPI_PS_INPUT_CNTL_22__DUP_MASK 0x00040000L 17391#define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE_MASK 0x00080000L 17392#define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1_MASK 0x00100000L 17393#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1_MASK 0x00600000L 17394#define SPI_PS_INPUT_CNTL_22__ATTR0_VALID_MASK 0x01000000L 17395#define SPI_PS_INPUT_CNTL_22__ATTR1_VALID_MASK 0x02000000L 17396//SPI_PS_INPUT_CNTL_23 17397#define SPI_PS_INPUT_CNTL_23__OFFSET__SHIFT 0x0 17398#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL__SHIFT 0x8 17399#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE__SHIFT 0xa 17400#define SPI_PS_INPUT_CNTL_23__DUP__SHIFT 0x12 17401#define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE__SHIFT 0x13 17402#define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1__SHIFT 0x14 17403#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1__SHIFT 0x15 17404#define SPI_PS_INPUT_CNTL_23__ATTR0_VALID__SHIFT 0x18 17405#define SPI_PS_INPUT_CNTL_23__ATTR1_VALID__SHIFT 0x19 17406#define SPI_PS_INPUT_CNTL_23__OFFSET_MASK 0x0000003FL 17407#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_MASK 0x00000300L 17408#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE_MASK 0x00000400L 17409#define SPI_PS_INPUT_CNTL_23__DUP_MASK 0x00040000L 17410#define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE_MASK 0x00080000L 17411#define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1_MASK 0x00100000L 17412#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1_MASK 0x00600000L 17413#define SPI_PS_INPUT_CNTL_23__ATTR0_VALID_MASK 0x01000000L 17414#define SPI_PS_INPUT_CNTL_23__ATTR1_VALID_MASK 0x02000000L 17415//SPI_PS_INPUT_CNTL_24 17416#define SPI_PS_INPUT_CNTL_24__OFFSET__SHIFT 0x0 17417#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL__SHIFT 0x8 17418#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE__SHIFT 0xa 17419#define SPI_PS_INPUT_CNTL_24__DUP__SHIFT 0x12 17420#define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE__SHIFT 0x13 17421#define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1__SHIFT 0x14 17422#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1__SHIFT 0x15 17423#define SPI_PS_INPUT_CNTL_24__ATTR0_VALID__SHIFT 0x18 17424#define SPI_PS_INPUT_CNTL_24__ATTR1_VALID__SHIFT 0x19 17425#define SPI_PS_INPUT_CNTL_24__OFFSET_MASK 0x0000003FL 17426#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_MASK 0x00000300L 17427#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE_MASK 0x00000400L 17428#define SPI_PS_INPUT_CNTL_24__DUP_MASK 0x00040000L 17429#define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE_MASK 0x00080000L 17430#define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1_MASK 0x00100000L 17431#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1_MASK 0x00600000L 17432#define SPI_PS_INPUT_CNTL_24__ATTR0_VALID_MASK 0x01000000L 17433#define SPI_PS_INPUT_CNTL_24__ATTR1_VALID_MASK 0x02000000L 17434//SPI_PS_INPUT_CNTL_25 17435#define SPI_PS_INPUT_CNTL_25__OFFSET__SHIFT 0x0 17436#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL__SHIFT 0x8 17437#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE__SHIFT 0xa 17438#define SPI_PS_INPUT_CNTL_25__DUP__SHIFT 0x12 17439#define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE__SHIFT 0x13 17440#define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1__SHIFT 0x14 17441#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1__SHIFT 0x15 17442#define SPI_PS_INPUT_CNTL_25__ATTR0_VALID__SHIFT 0x18 17443#define SPI_PS_INPUT_CNTL_25__ATTR1_VALID__SHIFT 0x19 17444#define SPI_PS_INPUT_CNTL_25__OFFSET_MASK 0x0000003FL 17445#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_MASK 0x00000300L 17446#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE_MASK 0x00000400L 17447#define SPI_PS_INPUT_CNTL_25__DUP_MASK 0x00040000L 17448#define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE_MASK 0x00080000L 17449#define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1_MASK 0x00100000L 17450#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1_MASK 0x00600000L 17451#define SPI_PS_INPUT_CNTL_25__ATTR0_VALID_MASK 0x01000000L 17452#define SPI_PS_INPUT_CNTL_25__ATTR1_VALID_MASK 0x02000000L 17453//SPI_PS_INPUT_CNTL_26 17454#define SPI_PS_INPUT_CNTL_26__OFFSET__SHIFT 0x0 17455#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL__SHIFT 0x8 17456#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE__SHIFT 0xa 17457#define SPI_PS_INPUT_CNTL_26__DUP__SHIFT 0x12 17458#define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE__SHIFT 0x13 17459#define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1__SHIFT 0x14 17460#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1__SHIFT 0x15 17461#define SPI_PS_INPUT_CNTL_26__ATTR0_VALID__SHIFT 0x18 17462#define SPI_PS_INPUT_CNTL_26__ATTR1_VALID__SHIFT 0x19 17463#define SPI_PS_INPUT_CNTL_26__OFFSET_MASK 0x0000003FL 17464#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_MASK 0x00000300L 17465#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE_MASK 0x00000400L 17466#define SPI_PS_INPUT_CNTL_26__DUP_MASK 0x00040000L 17467#define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE_MASK 0x00080000L 17468#define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1_MASK 0x00100000L 17469#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1_MASK 0x00600000L 17470#define SPI_PS_INPUT_CNTL_26__ATTR0_VALID_MASK 0x01000000L 17471#define SPI_PS_INPUT_CNTL_26__ATTR1_VALID_MASK 0x02000000L 17472//SPI_PS_INPUT_CNTL_27 17473#define SPI_PS_INPUT_CNTL_27__OFFSET__SHIFT 0x0 17474#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL__SHIFT 0x8 17475#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE__SHIFT 0xa 17476#define SPI_PS_INPUT_CNTL_27__DUP__SHIFT 0x12 17477#define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE__SHIFT 0x13 17478#define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1__SHIFT 0x14 17479#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1__SHIFT 0x15 17480#define SPI_PS_INPUT_CNTL_27__ATTR0_VALID__SHIFT 0x18 17481#define SPI_PS_INPUT_CNTL_27__ATTR1_VALID__SHIFT 0x19 17482#define SPI_PS_INPUT_CNTL_27__OFFSET_MASK 0x0000003FL 17483#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_MASK 0x00000300L 17484#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE_MASK 0x00000400L 17485#define SPI_PS_INPUT_CNTL_27__DUP_MASK 0x00040000L 17486#define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE_MASK 0x00080000L 17487#define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1_MASK 0x00100000L 17488#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1_MASK 0x00600000L 17489#define SPI_PS_INPUT_CNTL_27__ATTR0_VALID_MASK 0x01000000L 17490#define SPI_PS_INPUT_CNTL_27__ATTR1_VALID_MASK 0x02000000L 17491//SPI_PS_INPUT_CNTL_28 17492#define SPI_PS_INPUT_CNTL_28__OFFSET__SHIFT 0x0 17493#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL__SHIFT 0x8 17494#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE__SHIFT 0xa 17495#define SPI_PS_INPUT_CNTL_28__DUP__SHIFT 0x12 17496#define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE__SHIFT 0x13 17497#define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1__SHIFT 0x14 17498#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1__SHIFT 0x15 17499#define SPI_PS_INPUT_CNTL_28__ATTR0_VALID__SHIFT 0x18 17500#define SPI_PS_INPUT_CNTL_28__ATTR1_VALID__SHIFT 0x19 17501#define SPI_PS_INPUT_CNTL_28__OFFSET_MASK 0x0000003FL 17502#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_MASK 0x00000300L 17503#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE_MASK 0x00000400L 17504#define SPI_PS_INPUT_CNTL_28__DUP_MASK 0x00040000L 17505#define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE_MASK 0x00080000L 17506#define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1_MASK 0x00100000L 17507#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1_MASK 0x00600000L 17508#define SPI_PS_INPUT_CNTL_28__ATTR0_VALID_MASK 0x01000000L 17509#define SPI_PS_INPUT_CNTL_28__ATTR1_VALID_MASK 0x02000000L 17510//SPI_PS_INPUT_CNTL_29 17511#define SPI_PS_INPUT_CNTL_29__OFFSET__SHIFT 0x0 17512#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL__SHIFT 0x8 17513#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE__SHIFT 0xa 17514#define SPI_PS_INPUT_CNTL_29__DUP__SHIFT 0x12 17515#define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE__SHIFT 0x13 17516#define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1__SHIFT 0x14 17517#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1__SHIFT 0x15 17518#define SPI_PS_INPUT_CNTL_29__ATTR0_VALID__SHIFT 0x18 17519#define SPI_PS_INPUT_CNTL_29__ATTR1_VALID__SHIFT 0x19 17520#define SPI_PS_INPUT_CNTL_29__OFFSET_MASK 0x0000003FL 17521#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_MASK 0x00000300L 17522#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE_MASK 0x00000400L 17523#define SPI_PS_INPUT_CNTL_29__DUP_MASK 0x00040000L 17524#define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE_MASK 0x00080000L 17525#define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1_MASK 0x00100000L 17526#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1_MASK 0x00600000L 17527#define SPI_PS_INPUT_CNTL_29__ATTR0_VALID_MASK 0x01000000L 17528#define SPI_PS_INPUT_CNTL_29__ATTR1_VALID_MASK 0x02000000L 17529//SPI_PS_INPUT_CNTL_30 17530#define SPI_PS_INPUT_CNTL_30__OFFSET__SHIFT 0x0 17531#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL__SHIFT 0x8 17532#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE__SHIFT 0xa 17533#define SPI_PS_INPUT_CNTL_30__DUP__SHIFT 0x12 17534#define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE__SHIFT 0x13 17535#define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1__SHIFT 0x14 17536#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1__SHIFT 0x15 17537#define SPI_PS_INPUT_CNTL_30__ATTR0_VALID__SHIFT 0x18 17538#define SPI_PS_INPUT_CNTL_30__ATTR1_VALID__SHIFT 0x19 17539#define SPI_PS_INPUT_CNTL_30__OFFSET_MASK 0x0000003FL 17540#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_MASK 0x00000300L 17541#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE_MASK 0x00000400L 17542#define SPI_PS_INPUT_CNTL_30__DUP_MASK 0x00040000L 17543#define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE_MASK 0x00080000L 17544#define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1_MASK 0x00100000L 17545#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1_MASK 0x00600000L 17546#define SPI_PS_INPUT_CNTL_30__ATTR0_VALID_MASK 0x01000000L 17547#define SPI_PS_INPUT_CNTL_30__ATTR1_VALID_MASK 0x02000000L 17548//SPI_PS_INPUT_CNTL_31 17549#define SPI_PS_INPUT_CNTL_31__OFFSET__SHIFT 0x0 17550#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL__SHIFT 0x8 17551#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE__SHIFT 0xa 17552#define SPI_PS_INPUT_CNTL_31__DUP__SHIFT 0x12 17553#define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE__SHIFT 0x13 17554#define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1__SHIFT 0x14 17555#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1__SHIFT 0x15 17556#define SPI_PS_INPUT_CNTL_31__ATTR0_VALID__SHIFT 0x18 17557#define SPI_PS_INPUT_CNTL_31__ATTR1_VALID__SHIFT 0x19 17558#define SPI_PS_INPUT_CNTL_31__OFFSET_MASK 0x0000003FL 17559#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_MASK 0x00000300L 17560#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE_MASK 0x00000400L 17561#define SPI_PS_INPUT_CNTL_31__DUP_MASK 0x00040000L 17562#define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE_MASK 0x00080000L 17563#define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1_MASK 0x00100000L 17564#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1_MASK 0x00600000L 17565#define SPI_PS_INPUT_CNTL_31__ATTR0_VALID_MASK 0x01000000L 17566#define SPI_PS_INPUT_CNTL_31__ATTR1_VALID_MASK 0x02000000L 17567//SPI_VS_OUT_CONFIG 17568#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT__SHIFT 0x1 17569#define SPI_VS_OUT_CONFIG__VS_HALF_PACK__SHIFT 0x6 17570#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT_MASK 0x0000003EL 17571#define SPI_VS_OUT_CONFIG__VS_HALF_PACK_MASK 0x00000040L 17572//SPI_PS_INPUT_ENA 17573#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA__SHIFT 0x0 17574#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA__SHIFT 0x1 17575#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA__SHIFT 0x2 17576#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA__SHIFT 0x3 17577#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA__SHIFT 0x4 17578#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA__SHIFT 0x5 17579#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA__SHIFT 0x6 17580#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA__SHIFT 0x7 17581#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA__SHIFT 0x8 17582#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA__SHIFT 0x9 17583#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA__SHIFT 0xa 17584#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA__SHIFT 0xb 17585#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA__SHIFT 0xc 17586#define SPI_PS_INPUT_ENA__ANCILLARY_ENA__SHIFT 0xd 17587#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA__SHIFT 0xe 17588#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA__SHIFT 0xf 17589#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA_MASK 0x00000001L 17590#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA_MASK 0x00000002L 17591#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA_MASK 0x00000004L 17592#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA_MASK 0x00000008L 17593#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA_MASK 0x00000010L 17594#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA_MASK 0x00000020L 17595#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA_MASK 0x00000040L 17596#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA_MASK 0x00000080L 17597#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA_MASK 0x00000100L 17598#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA_MASK 0x00000200L 17599#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA_MASK 0x00000400L 17600#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA_MASK 0x00000800L 17601#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA_MASK 0x00001000L 17602#define SPI_PS_INPUT_ENA__ANCILLARY_ENA_MASK 0x00002000L 17603#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA_MASK 0x00004000L 17604#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA_MASK 0x00008000L 17605//SPI_PS_INPUT_ADDR 17606#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA__SHIFT 0x0 17607#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA__SHIFT 0x1 17608#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA__SHIFT 0x2 17609#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA__SHIFT 0x3 17610#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA__SHIFT 0x4 17611#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA__SHIFT 0x5 17612#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA__SHIFT 0x6 17613#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA__SHIFT 0x7 17614#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA__SHIFT 0x8 17615#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA__SHIFT 0x9 17616#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA__SHIFT 0xa 17617#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA__SHIFT 0xb 17618#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA__SHIFT 0xc 17619#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA__SHIFT 0xd 17620#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA__SHIFT 0xe 17621#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA__SHIFT 0xf 17622#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA_MASK 0x00000001L 17623#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA_MASK 0x00000002L 17624#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA_MASK 0x00000004L 17625#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA_MASK 0x00000008L 17626#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA_MASK 0x00000010L 17627#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA_MASK 0x00000020L 17628#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA_MASK 0x00000040L 17629#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA_MASK 0x00000080L 17630#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA_MASK 0x00000100L 17631#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA_MASK 0x00000200L 17632#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA_MASK 0x00000400L 17633#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA_MASK 0x00000800L 17634#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA_MASK 0x00001000L 17635#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA_MASK 0x00002000L 17636#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA_MASK 0x00004000L 17637#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA_MASK 0x00008000L 17638//SPI_INTERP_CONTROL_0 17639#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT 0x0 17640#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA__SHIFT 0x1 17641#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X__SHIFT 0x2 17642#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y__SHIFT 0x5 17643#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z__SHIFT 0x8 17644#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W__SHIFT 0xb 17645#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1__SHIFT 0xe 17646#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA_MASK 0x00000001L 17647#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA_MASK 0x00000002L 17648#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X_MASK 0x0000001CL 17649#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y_MASK 0x000000E0L 17650#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z_MASK 0x00000700L 17651#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W_MASK 0x00003800L 17652#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1_MASK 0x00004000L 17653//SPI_PS_IN_CONTROL 17654#define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT 0x0 17655#define SPI_PS_IN_CONTROL__PARAM_GEN__SHIFT 0x6 17656#define SPI_PS_IN_CONTROL__OFFCHIP_PARAM_EN__SHIFT 0x7 17657#define SPI_PS_IN_CONTROL__LATE_PC_DEALLOC__SHIFT 0x8 17658#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE__SHIFT 0xe 17659#define SPI_PS_IN_CONTROL__NUM_INTERP_MASK 0x0000003FL 17660#define SPI_PS_IN_CONTROL__PARAM_GEN_MASK 0x00000040L 17661#define SPI_PS_IN_CONTROL__OFFCHIP_PARAM_EN_MASK 0x00000080L 17662#define SPI_PS_IN_CONTROL__LATE_PC_DEALLOC_MASK 0x00000100L 17663#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE_MASK 0x00004000L 17664//SPI_BARYC_CNTL 17665#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL__SHIFT 0x0 17666#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL__SHIFT 0x4 17667#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL__SHIFT 0x8 17668#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL__SHIFT 0xc 17669#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION__SHIFT 0x10 17670#define SPI_BARYC_CNTL__POS_FLOAT_ULC__SHIFT 0x14 17671#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS__SHIFT 0x18 17672#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL_MASK 0x00000001L 17673#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL_MASK 0x00000010L 17674#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL_MASK 0x00000100L 17675#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL_MASK 0x00001000L 17676#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION_MASK 0x00030000L 17677#define SPI_BARYC_CNTL__POS_FLOAT_ULC_MASK 0x00100000L 17678#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS_MASK 0x01000000L 17679//SPI_TMPRING_SIZE 17680#define SPI_TMPRING_SIZE__WAVES__SHIFT 0x0 17681#define SPI_TMPRING_SIZE__WAVESIZE__SHIFT 0xc 17682#define SPI_TMPRING_SIZE__WAVES_MASK 0x00000FFFL 17683#define SPI_TMPRING_SIZE__WAVESIZE_MASK 0x01FFF000L 17684//SPI_SHADER_POS_FORMAT 17685#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT__SHIFT 0x0 17686#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT__SHIFT 0x4 17687#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT__SHIFT 0x8 17688#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT__SHIFT 0xc 17689#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT_MASK 0x0000000FL 17690#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT_MASK 0x000000F0L 17691#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT_MASK 0x00000F00L 17692#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT_MASK 0x0000F000L 17693//SPI_SHADER_Z_FORMAT 17694#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT__SHIFT 0x0 17695#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT_MASK 0x0000000FL 17696//SPI_SHADER_COL_FORMAT 17697#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT__SHIFT 0x0 17698#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT__SHIFT 0x4 17699#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT__SHIFT 0x8 17700#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT__SHIFT 0xc 17701#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT__SHIFT 0x10 17702#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT__SHIFT 0x14 17703#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT__SHIFT 0x18 17704#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT__SHIFT 0x1c 17705#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT_MASK 0x0000000FL 17706#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT_MASK 0x000000F0L 17707#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT_MASK 0x00000F00L 17708#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT_MASK 0x0000F000L 17709#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT_MASK 0x000F0000L 17710#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT_MASK 0x00F00000L 17711#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT_MASK 0x0F000000L 17712#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT_MASK 0xF0000000L 17713//SX_PS_DOWNCONVERT 17714#define SX_PS_DOWNCONVERT__MRT0__SHIFT 0x0 17715#define SX_PS_DOWNCONVERT__MRT1__SHIFT 0x4 17716#define SX_PS_DOWNCONVERT__MRT2__SHIFT 0x8 17717#define SX_PS_DOWNCONVERT__MRT3__SHIFT 0xc 17718#define SX_PS_DOWNCONVERT__MRT4__SHIFT 0x10 17719#define SX_PS_DOWNCONVERT__MRT5__SHIFT 0x14 17720#define SX_PS_DOWNCONVERT__MRT6__SHIFT 0x18 17721#define SX_PS_DOWNCONVERT__MRT7__SHIFT 0x1c 17722#define SX_PS_DOWNCONVERT__MRT0_MASK 0x0000000FL 17723#define SX_PS_DOWNCONVERT__MRT1_MASK 0x000000F0L 17724#define SX_PS_DOWNCONVERT__MRT2_MASK 0x00000F00L 17725#define SX_PS_DOWNCONVERT__MRT3_MASK 0x0000F000L 17726#define SX_PS_DOWNCONVERT__MRT4_MASK 0x000F0000L 17727#define SX_PS_DOWNCONVERT__MRT5_MASK 0x00F00000L 17728#define SX_PS_DOWNCONVERT__MRT6_MASK 0x0F000000L 17729#define SX_PS_DOWNCONVERT__MRT7_MASK 0xF0000000L 17730//SX_BLEND_OPT_EPSILON 17731#define SX_BLEND_OPT_EPSILON__MRT0_EPSILON__SHIFT 0x0 17732#define SX_BLEND_OPT_EPSILON__MRT1_EPSILON__SHIFT 0x4 17733#define SX_BLEND_OPT_EPSILON__MRT2_EPSILON__SHIFT 0x8 17734#define SX_BLEND_OPT_EPSILON__MRT3_EPSILON__SHIFT 0xc 17735#define SX_BLEND_OPT_EPSILON__MRT4_EPSILON__SHIFT 0x10 17736#define SX_BLEND_OPT_EPSILON__MRT5_EPSILON__SHIFT 0x14 17737#define SX_BLEND_OPT_EPSILON__MRT6_EPSILON__SHIFT 0x18 17738#define SX_BLEND_OPT_EPSILON__MRT7_EPSILON__SHIFT 0x1c 17739#define SX_BLEND_OPT_EPSILON__MRT0_EPSILON_MASK 0x0000000FL 17740#define SX_BLEND_OPT_EPSILON__MRT1_EPSILON_MASK 0x000000F0L 17741#define SX_BLEND_OPT_EPSILON__MRT2_EPSILON_MASK 0x00000F00L 17742#define SX_BLEND_OPT_EPSILON__MRT3_EPSILON_MASK 0x0000F000L 17743#define SX_BLEND_OPT_EPSILON__MRT4_EPSILON_MASK 0x000F0000L 17744#define SX_BLEND_OPT_EPSILON__MRT5_EPSILON_MASK 0x00F00000L 17745#define SX_BLEND_OPT_EPSILON__MRT6_EPSILON_MASK 0x0F000000L 17746#define SX_BLEND_OPT_EPSILON__MRT7_EPSILON_MASK 0xF0000000L 17747//SX_BLEND_OPT_CONTROL 17748#define SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE__SHIFT 0x0 17749#define SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE__SHIFT 0x1 17750#define SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE__SHIFT 0x4 17751#define SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE__SHIFT 0x5 17752#define SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE__SHIFT 0x8 17753#define SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE__SHIFT 0x9 17754#define SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE__SHIFT 0xc 17755#define SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE__SHIFT 0xd 17756#define SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE__SHIFT 0x10 17757#define SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE__SHIFT 0x11 17758#define SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE__SHIFT 0x14 17759#define SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE__SHIFT 0x15 17760#define SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE__SHIFT 0x18 17761#define SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE__SHIFT 0x19 17762#define SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE__SHIFT 0x1c 17763#define SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE__SHIFT 0x1d 17764#define SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE__SHIFT 0x1f 17765#define SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE_MASK 0x00000001L 17766#define SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE_MASK 0x00000002L 17767#define SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE_MASK 0x00000010L 17768#define SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE_MASK 0x00000020L 17769#define SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE_MASK 0x00000100L 17770#define SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE_MASK 0x00000200L 17771#define SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE_MASK 0x00001000L 17772#define SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE_MASK 0x00002000L 17773#define SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE_MASK 0x00010000L 17774#define SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE_MASK 0x00020000L 17775#define SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE_MASK 0x00100000L 17776#define SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE_MASK 0x00200000L 17777#define SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE_MASK 0x01000000L 17778#define SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE_MASK 0x02000000L 17779#define SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE_MASK 0x10000000L 17780#define SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE_MASK 0x20000000L 17781#define SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE_MASK 0x80000000L 17782//SX_MRT0_BLEND_OPT 17783#define SX_MRT0_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 17784#define SX_MRT0_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 17785#define SX_MRT0_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 17786#define SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 17787#define SX_MRT0_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 17788#define SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 17789#define SX_MRT0_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L 17790#define SX_MRT0_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L 17791#define SX_MRT0_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L 17792#define SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L 17793#define SX_MRT0_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L 17794#define SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L 17795//SX_MRT1_BLEND_OPT 17796#define SX_MRT1_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 17797#define SX_MRT1_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 17798#define SX_MRT1_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 17799#define SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 17800#define SX_MRT1_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 17801#define SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 17802#define SX_MRT1_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L 17803#define SX_MRT1_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L 17804#define SX_MRT1_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L 17805#define SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L 17806#define SX_MRT1_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L 17807#define SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L 17808//SX_MRT2_BLEND_OPT 17809#define SX_MRT2_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 17810#define SX_MRT2_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 17811#define SX_MRT2_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 17812#define SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 17813#define SX_MRT2_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 17814#define SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 17815#define SX_MRT2_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L 17816#define SX_MRT2_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L 17817#define SX_MRT2_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L 17818#define SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L 17819#define SX_MRT2_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L 17820#define SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L 17821//SX_MRT3_BLEND_OPT 17822#define SX_MRT3_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 17823#define SX_MRT3_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 17824#define SX_MRT3_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 17825#define SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 17826#define SX_MRT3_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 17827#define SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 17828#define SX_MRT3_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L 17829#define SX_MRT3_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L 17830#define SX_MRT3_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L 17831#define SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L 17832#define SX_MRT3_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L 17833#define SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L 17834//SX_MRT4_BLEND_OPT 17835#define SX_MRT4_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 17836#define SX_MRT4_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 17837#define SX_MRT4_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 17838#define SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 17839#define SX_MRT4_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 17840#define SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 17841#define SX_MRT4_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L 17842#define SX_MRT4_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L 17843#define SX_MRT4_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L 17844#define SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L 17845#define SX_MRT4_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L 17846#define SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L 17847//SX_MRT5_BLEND_OPT 17848#define SX_MRT5_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 17849#define SX_MRT5_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 17850#define SX_MRT5_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 17851#define SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 17852#define SX_MRT5_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 17853#define SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 17854#define SX_MRT5_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L 17855#define SX_MRT5_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L 17856#define SX_MRT5_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L 17857#define SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L 17858#define SX_MRT5_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L 17859#define SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L 17860//SX_MRT6_BLEND_OPT 17861#define SX_MRT6_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 17862#define SX_MRT6_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 17863#define SX_MRT6_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 17864#define SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 17865#define SX_MRT6_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 17866#define SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 17867#define SX_MRT6_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L 17868#define SX_MRT6_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L 17869#define SX_MRT6_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L 17870#define SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L 17871#define SX_MRT6_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L 17872#define SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L 17873//SX_MRT7_BLEND_OPT 17874#define SX_MRT7_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 17875#define SX_MRT7_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 17876#define SX_MRT7_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 17877#define SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 17878#define SX_MRT7_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 17879#define SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 17880#define SX_MRT7_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L 17881#define SX_MRT7_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L 17882#define SX_MRT7_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L 17883#define SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L 17884#define SX_MRT7_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L 17885#define SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L 17886//CB_BLEND0_CONTROL 17887#define CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 17888#define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 17889#define CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 17890#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 17891#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 17892#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 17893#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d 17894#define CB_BLEND0_CONTROL__ENABLE__SHIFT 0x1e 17895#define CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT 0x1f 17896#define CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL 17897#define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L 17898#define CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L 17899#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L 17900#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L 17901#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L 17902#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L 17903#define CB_BLEND0_CONTROL__ENABLE_MASK 0x40000000L 17904#define CB_BLEND0_CONTROL__DISABLE_ROP3_MASK 0x80000000L 17905//CB_BLEND1_CONTROL 17906#define CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 17907#define CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 17908#define CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 17909#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 17910#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 17911#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 17912#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d 17913#define CB_BLEND1_CONTROL__ENABLE__SHIFT 0x1e 17914#define CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT 0x1f 17915#define CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL 17916#define CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L 17917#define CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L 17918#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L 17919#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L 17920#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L 17921#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L 17922#define CB_BLEND1_CONTROL__ENABLE_MASK 0x40000000L 17923#define CB_BLEND1_CONTROL__DISABLE_ROP3_MASK 0x80000000L 17924//CB_BLEND2_CONTROL 17925#define CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 17926#define CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 17927#define CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 17928#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 17929#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 17930#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 17931#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d 17932#define CB_BLEND2_CONTROL__ENABLE__SHIFT 0x1e 17933#define CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT 0x1f 17934#define CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL 17935#define CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L 17936#define CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L 17937#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L 17938#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L 17939#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L 17940#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L 17941#define CB_BLEND2_CONTROL__ENABLE_MASK 0x40000000L 17942#define CB_BLEND2_CONTROL__DISABLE_ROP3_MASK 0x80000000L 17943//CB_BLEND3_CONTROL 17944#define CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 17945#define CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 17946#define CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 17947#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 17948#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 17949#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 17950#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d 17951#define CB_BLEND3_CONTROL__ENABLE__SHIFT 0x1e 17952#define CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT 0x1f 17953#define CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL 17954#define CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L 17955#define CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L 17956#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L 17957#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L 17958#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L 17959#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L 17960#define CB_BLEND3_CONTROL__ENABLE_MASK 0x40000000L 17961#define CB_BLEND3_CONTROL__DISABLE_ROP3_MASK 0x80000000L 17962//CB_BLEND4_CONTROL 17963#define CB_BLEND4_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 17964#define CB_BLEND4_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 17965#define CB_BLEND4_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 17966#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 17967#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 17968#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 17969#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d 17970#define CB_BLEND4_CONTROL__ENABLE__SHIFT 0x1e 17971#define CB_BLEND4_CONTROL__DISABLE_ROP3__SHIFT 0x1f 17972#define CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL 17973#define CB_BLEND4_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L 17974#define CB_BLEND4_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L 17975#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L 17976#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L 17977#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L 17978#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L 17979#define CB_BLEND4_CONTROL__ENABLE_MASK 0x40000000L 17980#define CB_BLEND4_CONTROL__DISABLE_ROP3_MASK 0x80000000L 17981//CB_BLEND5_CONTROL 17982#define CB_BLEND5_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 17983#define CB_BLEND5_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 17984#define CB_BLEND5_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 17985#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 17986#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 17987#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 17988#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d 17989#define CB_BLEND5_CONTROL__ENABLE__SHIFT 0x1e 17990#define CB_BLEND5_CONTROL__DISABLE_ROP3__SHIFT 0x1f 17991#define CB_BLEND5_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL 17992#define CB_BLEND5_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L 17993#define CB_BLEND5_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L 17994#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L 17995#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L 17996#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L 17997#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L 17998#define CB_BLEND5_CONTROL__ENABLE_MASK 0x40000000L 17999#define CB_BLEND5_CONTROL__DISABLE_ROP3_MASK 0x80000000L 18000//CB_BLEND6_CONTROL
18001#define CB_BLEND6_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 18002#define CB_BLEND6_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 18003#define CB_BLEND6_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 18004#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 18005#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 18006#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 18007#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d 18008#define CB_BLEND6_CONTROL__ENABLE__SHIFT 0x1e 18009#define CB_BLEND6_CONTROL__DISABLE_ROP3__SHIFT 0x1f 18010#define CB_BLEND6_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL 18011#define CB_BLEND6_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L 18012#define CB_BLEND6_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L 18013#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L 18014#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L 18015#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L 18016#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L 18017#define CB_BLEND6_CONTROL__ENABLE_MASK 0x40000000L 18018#define CB_BLEND6_CONTROL__DISABLE_ROP3_MASK 0x80000000L 18019//CB_BLEND7_CONTROL 18020#define CB_BLEND7_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 18021#define CB_BLEND7_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 18022#define CB_BLEND7_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 18023#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 18024#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 18025#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 18026#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d 18027#define CB_BLEND7_CONTROL__ENABLE__SHIFT 0x1e 18028#define CB_BLEND7_CONTROL__DISABLE_ROP3__SHIFT 0x1f 18029#define CB_BLEND7_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL 18030#define CB_BLEND7_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L 18031#define CB_BLEND7_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L 18032#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L 18033#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L 18034#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L 18035#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L 18036#define CB_BLEND7_CONTROL__ENABLE_MASK 0x40000000L 18037#define CB_BLEND7_CONTROL__DISABLE_ROP3_MASK 0x80000000L 18038//CB_MRT0_EPITCH 18039#define CB_MRT0_EPITCH__EPITCH__SHIFT 0x0 18040#define CB_MRT0_EPITCH__EPITCH_MASK 0x0000FFFFL 18041//CB_MRT1_EPITCH 18042#define CB_MRT1_EPITCH__EPITCH__SHIFT 0x0 18043#define CB_MRT1_EPITCH__EPITCH_MASK 0x0000FFFFL 18044//CB_MRT2_EPITCH 18045#define CB_MRT2_EPITCH__EPITCH__SHIFT 0x0 18046#define CB_MRT2_EPITCH__EPITCH_MASK 0x0000FFFFL 18047//CB_MRT3_EPITCH 18048#define CB_MRT3_EPITCH__EPITCH__SHIFT 0x0 18049#define CB_MRT3_EPITCH__EPITCH_MASK 0x0000FFFFL 18050//CB_MRT4_EPITCH 18051#define CB_MRT4_EPITCH__EPITCH__SHIFT 0x0 18052#define CB_MRT4_EPITCH__EPITCH_MASK 0x0000FFFFL 18053//CB_MRT5_EPITCH 18054#define CB_MRT5_EPITCH__EPITCH__SHIFT 0x0 18055#define CB_MRT5_EPITCH__EPITCH_MASK 0x0000FFFFL 18056//CB_MRT6_EPITCH 18057#define CB_MRT6_EPITCH__EPITCH__SHIFT 0x0 18058#define CB_MRT6_EPITCH__EPITCH_MASK 0x0000FFFFL 18059//CB_MRT7_EPITCH 18060#define CB_MRT7_EPITCH__EPITCH__SHIFT 0x0 18061#define CB_MRT7_EPITCH__EPITCH_MASK 0x0000FFFFL 18062//CS_COPY_STATE 18063#define CS_COPY_STATE__SRC_STATE_ID__SHIFT 0x0 18064#define CS_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L 18065//GFX_COPY_STATE 18066#define GFX_COPY_STATE__SRC_STATE_ID__SHIFT 0x0 18067#define GFX_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L 18068//PA_CL_POINT_X_RAD 18069#define PA_CL_POINT_X_RAD__DATA_REGISTER__SHIFT 0x0 18070#define PA_CL_POINT_X_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL 18071//PA_CL_POINT_Y_RAD 18072#define PA_CL_POINT_Y_RAD__DATA_REGISTER__SHIFT 0x0 18073#define PA_CL_POINT_Y_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL 18074//PA_CL_POINT_SIZE 18075#define PA_CL_POINT_SIZE__DATA_REGISTER__SHIFT 0x0 18076#define PA_CL_POINT_SIZE__DATA_REGISTER_MASK 0xFFFFFFFFL 18077//PA_CL_POINT_CULL_RAD 18078#define PA_CL_POINT_CULL_RAD__DATA_REGISTER__SHIFT 0x0 18079#define PA_CL_POINT_CULL_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL 18080//VGT_DMA_BASE_HI 18081#define VGT_DMA_BASE_HI__BASE_ADDR__SHIFT 0x0 18082#define VGT_DMA_BASE_HI__BASE_ADDR_MASK 0x0000FFFFL 18083//VGT_DMA_BASE 18084#define VGT_DMA_BASE__BASE_ADDR__SHIFT 0x0 18085#define VGT_DMA_BASE__BASE_ADDR_MASK 0xFFFFFFFFL 18086//VGT_DRAW_INITIATOR 18087#define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT 0x0 18088#define VGT_DRAW_INITIATOR__MAJOR_MODE__SHIFT 0x2 18089#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX__SHIFT 0x4 18090#define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT 0x5 18091#define VGT_DRAW_INITIATOR__USE_OPAQUE__SHIFT 0x6 18092#define VGT_DRAW_INITIATOR__UNROLLED_INST__SHIFT 0x7 18093#define VGT_DRAW_INITIATOR__GRBM_SKEW_NO_DEC__SHIFT 0x8 18094#define VGT_DRAW_INITIATOR__REG_RT_INDEX__SHIFT 0x1d 18095#define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK 0x00000003L 18096#define VGT_DRAW_INITIATOR__MAJOR_MODE_MASK 0x0000000CL 18097#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX_MASK 0x00000010L 18098#define VGT_DRAW_INITIATOR__NOT_EOP_MASK 0x00000020L 18099#define VGT_DRAW_INITIATOR__USE_OPAQUE_MASK 0x00000040L 18100#define VGT_DRAW_INITIATOR__UNROLLED_INST_MASK 0x00000080L 18101#define VGT_DRAW_INITIATOR__GRBM_SKEW_NO_DEC_MASK 0x00000100L 18102#define VGT_DRAW_INITIATOR__REG_RT_INDEX_MASK 0xE0000000L 18103//VGT_IMMED_DATA 18104#define VGT_IMMED_DATA__DATA__SHIFT 0x0 18105#define VGT_IMMED_DATA__DATA_MASK 0xFFFFFFFFL 18106//VGT_EVENT_ADDRESS_REG 18107#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW__SHIFT 0x0 18108#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW_MASK 0x0FFFFFFFL 18109//DB_DEPTH_CONTROL 18110#define DB_DEPTH_CONTROL__STENCIL_ENABLE__SHIFT 0x0 18111#define DB_DEPTH_CONTROL__Z_ENABLE__SHIFT 0x1 18112#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE__SHIFT 0x2 18113#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE__SHIFT 0x3 18114#define DB_DEPTH_CONTROL__ZFUNC__SHIFT 0x4 18115#define DB_DEPTH_CONTROL__BACKFACE_ENABLE__SHIFT 0x7 18116#define DB_DEPTH_CONTROL__STENCILFUNC__SHIFT 0x8 18117#define DB_DEPTH_CONTROL__STENCILFUNC_BF__SHIFT 0x14 18118#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL__SHIFT 0x1e 18119#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS__SHIFT 0x1f 18120#define DB_DEPTH_CONTROL__STENCIL_ENABLE_MASK 0x00000001L 18121#define DB_DEPTH_CONTROL__Z_ENABLE_MASK 0x00000002L 18122#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE_MASK 0x00000004L 18123#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE_MASK 0x00000008L 18124#define DB_DEPTH_CONTROL__ZFUNC_MASK 0x00000070L 18125#define DB_DEPTH_CONTROL__BACKFACE_ENABLE_MASK 0x00000080L 18126#define DB_DEPTH_CONTROL__STENCILFUNC_MASK 0x00000700L 18127#define DB_DEPTH_CONTROL__STENCILFUNC_BF_MASK 0x00700000L 18128#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_MASK 0x40000000L 18129#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS_MASK 0x80000000L 18130//DB_EQAA 18131#define DB_EQAA__MAX_ANCHOR_SAMPLES__SHIFT 0x0 18132#define DB_EQAA__PS_ITER_SAMPLES__SHIFT 0x4 18133#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES__SHIFT 0x8 18134#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES__SHIFT 0xc 18135#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS__SHIFT 0x10 18136#define DB_EQAA__INCOHERENT_EQAA_READS__SHIFT 0x11 18137#define DB_EQAA__INTERPOLATE_COMP_Z__SHIFT 0x12 18138#define DB_EQAA__INTERPOLATE_SRC_Z__SHIFT 0x13 18139#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS__SHIFT 0x14 18140#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE__SHIFT 0x15 18141#define DB_EQAA__OVERRASTERIZATION_AMOUNT__SHIFT 0x18 18142#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION__SHIFT 0x1b 18143#define DB_EQAA__MAX_ANCHOR_SAMPLES_MASK 0x00000007L 18144#define DB_EQAA__PS_ITER_SAMPLES_MASK 0x00000070L 18145#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES_MASK 0x00000700L 18146#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES_MASK 0x00007000L 18147#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS_MASK 0x00010000L 18148#define DB_EQAA__INCOHERENT_EQAA_READS_MASK 0x00020000L 18149#define DB_EQAA__INTERPOLATE_COMP_Z_MASK 0x00040000L 18150#define DB_EQAA__INTERPOLATE_SRC_Z_MASK 0x00080000L 18151#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS_MASK 0x00100000L 18152#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE_MASK 0x00200000L 18153#define DB_EQAA__OVERRASTERIZATION_AMOUNT_MASK 0x07000000L 18154#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION_MASK 0x08000000L 18155//CB_COLOR_CONTROL 18156#define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD__SHIFT 0x0 18157#define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3 18158#define CB_COLOR_CONTROL__MODE__SHIFT 0x4 18159#define CB_COLOR_CONTROL__ROP3__SHIFT 0x10 18160#define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD_MASK 0x00000001L 18161#define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x00000008L 18162#define CB_COLOR_CONTROL__MODE_MASK 0x00000070L 18163#define CB_COLOR_CONTROL__ROP3_MASK 0x00FF0000L 18164//DB_SHADER_CONTROL 18165#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE__SHIFT 0x0 18166#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE__SHIFT 0x1 18167#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE__SHIFT 0x2 18168#define DB_SHADER_CONTROL__Z_ORDER__SHIFT 0x4 18169#define DB_SHADER_CONTROL__KILL_ENABLE__SHIFT 0x6 18170#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE__SHIFT 0x7 18171#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE__SHIFT 0x8 18172#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL__SHIFT 0x9 18173#define DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT 0xa 18174#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE__SHIFT 0xb 18175#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER__SHIFT 0xc 18176#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT__SHIFT 0xd 18177#define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE__SHIFT 0xf 18178#define DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER__SHIFT 0x10 18179#define DB_SHADER_CONTROL__EXEC_IF_OVERLAPPED__SHIFT 0x11 18180#define DB_SHADER_CONTROL__POPS_OVERLAP_NUM_SAMPLES__SHIFT 0x14 18181#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE_MASK 0x00000001L 18182#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE_MASK 0x00000002L 18183#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE_MASK 0x00000004L 18184#define DB_SHADER_CONTROL__Z_ORDER_MASK 0x00000030L 18185#define DB_SHADER_CONTROL__KILL_ENABLE_MASK 0x00000040L 18186#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE_MASK 0x00000080L 18187#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE_MASK 0x00000100L 18188#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL_MASK 0x00000200L 18189#define DB_SHADER_CONTROL__EXEC_ON_NOOP_MASK 0x00000400L 18190#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE_MASK 0x00000800L 18191#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER_MASK 0x00001000L 18192#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT_MASK 0x00006000L 18193#define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE_MASK 0x00008000L 18194#define DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER_MASK 0x00010000L 18195#define DB_SHADER_CONTROL__EXEC_IF_OVERLAPPED_MASK 0x00020000L 18196#define DB_SHADER_CONTROL__POPS_OVERLAP_NUM_SAMPLES_MASK 0x00700000L 18197//PA_CL_CLIP_CNTL 18198#define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT 0x0 18199#define PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT 0x1 18200#define PA_CL_CLIP_CNTL__UCP_ENA_2__SHIFT 0x2 18201#define PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT 0x3 18202#define PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT 0x4 18203#define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT 0x5 18204#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG__SHIFT 0xd 18205#define PA_CL_CLIP_CNTL__PS_UCP_MODE__SHIFT 0xe 18206#define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT 0x10 18207#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA__SHIFT 0x11 18208#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT 0x12 18209#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT 0x13 18210#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT 0x14 18211#define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT 0x15 18212#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL__SHIFT 0x16 18213#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA__SHIFT 0x18 18214#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE__SHIFT 0x19 18215#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE__SHIFT 0x1a 18216#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE__SHIFT 0x1b 18217#define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK 0x00000001L 18218#define PA_CL_CLIP_CNTL__UCP_ENA_1_MASK 0x00000002L 18219#define PA_CL_CLIP_CNTL__UCP_ENA_2_MASK 0x00000004L 18220#define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK 0x00000008L 18221#define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK 0x00000010L 18222#define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK 0x00000020L 18223#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG_MASK 0x00002000L 18224#define PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK 0x0000C000L 18225#define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK 0x00010000L 18226#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK 0x00020000L 18227#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK 0x00040000L 18228#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK 0x00080000L 18229#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK 0x00100000L 18230#define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK 0x00200000L 18231#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL_MASK 0x00400000L 18232#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA_MASK 0x01000000L 18233#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE_MASK 0x02000000L 18234#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE_MASK 0x04000000L 18235#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE_MASK 0x08000000L 18236//PA_SU_SC_MODE_CNTL 18237#define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT 0x0 18238#define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT 0x1 18239#define PA_SU_SC_MODE_CNTL__FACE__SHIFT 0x2 18240#define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT 0x3 18241#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT 0x5 18242#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT 0x8 18243#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0xb 18244#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0xc 18245#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0xd 18246#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x10 18247#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT 0x13 18248#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT 0x14 18249#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x15 18250#define PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF__SHIFT 0x16 18251#define PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION__SHIFT 0x17 18252#define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK 0x00000001L 18253#define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK 0x00000002L 18254#define PA_SU_SC_MODE_CNTL__FACE_MASK 0x00000004L 18255#define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK 0x00000018L 18256#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK 0x000000E0L 18257#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK 0x00000700L 18258#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK 0x00000800L 18259#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK 0x00001000L 18260#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK 0x00002000L 18261#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK 0x00010000L 18262#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK 0x00080000L 18263#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK 0x00100000L 18264#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK 0x00200000L 18265#define PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF_MASK 0x00400000L 18266#define PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION_MASK 0x00800000L 18267//PA_CL_VTE_CNTL 18268#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT 0x0 18269#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT 0x1 18270#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT 0x2 18271#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT 0x3 18272#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT 0x4 18273#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT 0x5 18274#define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT 0x8 18275#define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT 0x9 18276#define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT 0xa 18277#define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT 0xb 18278#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK 0x00000001L 18279#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK 0x00000002L 18280#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK 0x00000004L 18281#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK 0x00000008L 18282#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK 0x00000010L 18283#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK 0x00000020L 18284#define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100L 18285#define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200L 18286#define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK 0x00000400L 18287#define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK 0x00000800L 18288//PA_CL_VS_OUT_CNTL 18289#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0__SHIFT 0x0 18290#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1__SHIFT 0x1 18291#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2__SHIFT 0x2 18292#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3__SHIFT 0x3 18293#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4__SHIFT 0x4 18294#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5__SHIFT 0x5 18295#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6__SHIFT 0x6 18296#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7__SHIFT 0x7 18297#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0__SHIFT 0x8 18298#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1__SHIFT 0x9 18299#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2__SHIFT 0xa 18300#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3__SHIFT 0xb 18301#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4__SHIFT 0xc 18302#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5__SHIFT 0xd 18303#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6__SHIFT 0xe 18304#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7__SHIFT 0xf 18305#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE__SHIFT 0x10 18306#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG__SHIFT 0x11 18307#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX__SHIFT 0x12 18308#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX__SHIFT 0x13 18309#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG__SHIFT 0x14 18310#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA__SHIFT 0x15 18311#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA__SHIFT 0x16 18312#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA__SHIFT 0x17 18313#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA__SHIFT 0x18 18314#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG__SHIFT 0x19 18315#define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH__SHIFT 0x1a 18316#define PA_CL_VS_OUT_CNTL__USE_VTX_SHD_OBJPRIM_ID__SHIFT 0x1b 18317#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0_MASK 0x00000001L 18318#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1_MASK 0x00000002L 18319#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2_MASK 0x00000004L 18320#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3_MASK 0x00000008L 18321#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4_MASK 0x00000010L 18322#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5_MASK 0x00000020L 18323#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6_MASK 0x00000040L 18324#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7_MASK 0x00000080L 18325#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0_MASK 0x00000100L 18326#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1_MASK 0x00000200L 18327#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2_MASK 0x00000400L 18328#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3_MASK 0x00000800L 18329#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4_MASK 0x00001000L 18330#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5_MASK 0x00002000L 18331#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6_MASK 0x00004000L 18332#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7_MASK 0x00008000L 18333#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE_MASK 0x00010000L 18334#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG_MASK 0x00020000L 18335#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX_MASK 0x00040000L 18336#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX_MASK 0x00080000L 18337#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG_MASK 0x00100000L 18338#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA_MASK 0x00200000L 18339#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA_MASK 0x00400000L 18340#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA_MASK 0x00800000L 18341#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA_MASK 0x01000000L 18342#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG_MASK 0x02000000L 18343#define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH_MASK 0x04000000L 18344#define PA_CL_VS_OUT_CNTL__USE_VTX_SHD_OBJPRIM_ID_MASK 0x08000000L 18345//PA_CL_NANINF_CNTL 18346#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT 0x0 18347#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT 0x1 18348#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT 0x2 18349#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0__SHIFT 0x3 18350#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN__SHIFT 0x4 18351#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN__SHIFT 0x5 18352#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN__SHIFT 0x6 18353#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0__SHIFT 0x7 18354#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF__SHIFT 0x8 18355#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN__SHIFT 0x9 18356#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF__SHIFT 0xa 18357#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN__SHIFT 0xb 18358#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF__SHIFT 0xc 18359#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN__SHIFT 0xd 18360#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD__SHIFT 0xe 18361#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0__SHIFT 0x14 18362#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD_MASK 0x00000001L 18363#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD_MASK 0x00000002L 18364#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD_MASK 0x00000004L 18365#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0_MASK 0x00000008L 18366#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN_MASK 0x00000010L 18367#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN_MASK 0x00000020L 18368#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN_MASK 0x00000040L 18369#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0_MASK 0x00000080L 18370#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF_MASK 0x00000100L 18371#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN_MASK 0x00000200L 18372#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF_MASK 0x00000400L 18373#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN_MASK 0x00000800L 18374#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF_MASK 0x00001000L 18375#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN_MASK 0x00002000L 18376#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD_MASK 0x00004000L 18377#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0_MASK 0x00100000L 18378//PA_SU_LINE_STIPPLE_CNTL 18379#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET__SHIFT 0x0 18380#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH__SHIFT 0x2 18381#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM__SHIFT 0x3 18382#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST__SHIFT 0x4 18383#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET_MASK 0x00000003L 18384#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH_MASK 0x00000004L 18385#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM_MASK 0x00000008L 18386#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST_MASK 0x00000010L 18387//PA_SU_LINE_STIPPLE_SCALE 18388#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE__SHIFT 0x0 18389#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE_MASK 0xFFFFFFFFL 18390//PA_SU_PRIM_FILTER_CNTL 18391#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x0 18392#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x1 18393#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x2 18394#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x3 18395#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA__SHIFT 0x4 18396#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA__SHIFT 0x5 18397#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA__SHIFT 0x6 18398#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA__SHIFT 0x7 18399#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT__SHIFT 0x8 18400#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION__SHIFT 0x1e 18401#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION__SHIFT 0x1f 18402#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x00000001L 18403#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x00000002L 18404#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x00000004L 18405#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x00000008L 18406#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA_MASK 0x00000010L 18407#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA_MASK 0x00000020L 18408#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA_MASK 0x00000040L 18409#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA_MASK 0x00000080L 18410#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT_MASK 0x0000FF00L 18411#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION_MASK 0x40000000L 18412#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION_MASK 0x80000000L 18413//PA_SU_SMALL_PRIM_FILTER_CNTL 18414#define PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE__SHIFT 0x0 18415#define PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x1 18416#define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x2 18417#define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x3 18418#define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x4 18419#define PA_SU_SMALL_PRIM_FILTER_CNTL__SRBSL_ENABLE__SHIFT 0x5 18420#define PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE_MASK 0x00000001L 18421#define PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x00000002L 18422#define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x00000004L 18423#define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x00000008L 18424#define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x00000010L 18425#define PA_SU_SMALL_PRIM_FILTER_CNTL__SRBSL_ENABLE_MASK 0x00000020L 18426//PA_CL_OBJPRIM_ID_CNTL 18427#define PA_CL_OBJPRIM_ID_CNTL__OBJ_ID_SEL__SHIFT 0x0 18428#define PA_CL_OBJPRIM_ID_CNTL__ADD_PIPED_PRIM_ID__SHIFT 0x1 18429#define PA_CL_OBJPRIM_ID_CNTL__EN_32BIT_OBJPRIMID__SHIFT 0x2 18430#define PA_CL_OBJPRIM_ID_CNTL__OBJ_ID_SEL_MASK 0x00000001L 18431#define PA_CL_OBJPRIM_ID_CNTL__ADD_PIPED_PRIM_ID_MASK 0x00000002L 18432#define PA_CL_OBJPRIM_ID_CNTL__EN_32BIT_OBJPRIMID_MASK 0x00000004L 18433//PA_CL_NGG_CNTL 18434#define PA_CL_NGG_CNTL__VERTEX_REUSE_OFF__SHIFT 0x0 18435#define PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA__SHIFT 0x1 18436#define PA_CL_NGG_CNTL__VERTEX_REUSE_OFF_MASK 0x00000001L 18437#define PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA_MASK 0x00000002L 18438//PA_SU_OVER_RASTERIZATION_CNTL 18439#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES__SHIFT 0x0 18440#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES__SHIFT 0x1 18441#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS__SHIFT 0x2 18442#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES__SHIFT 0x3 18443#define PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW__SHIFT 0x4 18444#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES_MASK 0x00000001L 18445#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES_MASK 0x00000002L 18446#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS_MASK 0x00000004L 18447#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES_MASK 0x00000008L 18448#define PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW_MASK 0x00000010L 18449//PA_SU_POINT_SIZE 18450#define PA_SU_POINT_SIZE__HEIGHT__SHIFT 0x0 18451#define PA_SU_POINT_SIZE__WIDTH__SHIFT 0x10 18452#define PA_SU_POINT_SIZE__HEIGHT_MASK 0x0000FFFFL 18453#define PA_SU_POINT_SIZE__WIDTH_MASK 0xFFFF0000L 18454//PA_SU_POINT_MINMAX 18455#define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT 0x0 18456#define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT 0x10 18457#define PA_SU_POINT_MINMAX__MIN_SIZE_MASK 0x0000FFFFL 18458#define PA_SU_POINT_MINMAX__MAX_SIZE_MASK 0xFFFF0000L 18459//PA_SU_LINE_CNTL 18460#define PA_SU_LINE_CNTL__WIDTH__SHIFT 0x0 18461#define PA_SU_LINE_CNTL__WIDTH_MASK 0x0000FFFFL 18462//PA_SC_LINE_STIPPLE 18463#define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT 0x0 18464#define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT 0x10 18465#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT 0x1c 18466#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT 0x1d 18467#define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK 0x0000FFFFL 18468#define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK 0x00FF0000L 18469#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK 0x10000000L 18470#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK 0x60000000L 18471//VGT_OUTPUT_PATH_CNTL 18472#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT__SHIFT 0x0 18473#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT_MASK 0x00000007L 18474//VGT_HOS_CNTL 18475#define VGT_HOS_CNTL__TESS_MODE__SHIFT 0x0 18476#define VGT_HOS_CNTL__TESS_MODE_MASK 0x00000003L 18477//VGT_HOS_MAX_TESS_LEVEL 18478#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS__SHIFT 0x0 18479#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS_MASK 0xFFFFFFFFL 18480//VGT_HOS_MIN_TESS_LEVEL 18481#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS__SHIFT 0x0 18482#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS_MASK 0xFFFFFFFFL 18483//VGT_HOS_REUSE_DEPTH 18484#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH__SHIFT 0x0 18485#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH_MASK 0x000000FFL 18486//VGT_GROUP_PRIM_TYPE 18487#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE__SHIFT 0x0 18488#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER__SHIFT 0xe 18489#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS__SHIFT 0xf 18490#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER__SHIFT 0x10 18491#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE_MASK 0x0000001FL 18492#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER_MASK 0x00004000L 18493#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS_MASK 0x00008000L 18494#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER_MASK 0x00070000L 18495//VGT_GROUP_FIRST_DECR 18496#define VGT_GROUP_FIRST_DECR__FIRST_DECR__SHIFT 0x0 18497#define VGT_GROUP_FIRST_DECR__FIRST_DECR_MASK 0x0000000FL 18498//VGT_GROUP_DECR 18499#define VGT_GROUP_DECR__DECR__SHIFT 0x0 18500#define VGT_GROUP_DECR__DECR_MASK 0x0000000FL 18501//VGT_GROUP_VECT_0_CNTL 18502#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN__SHIFT 0x0 18503#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN__SHIFT 0x1 18504#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN__SHIFT 0x2 18505#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN__SHIFT 0x3 18506#define VGT_GROUP_VECT_0_CNTL__STRIDE__SHIFT 0x8 18507#define VGT_GROUP_VECT_0_CNTL__SHIFT__SHIFT 0x10 18508#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN_MASK 0x00000001L 18509#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN_MASK 0x00000002L 18510#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN_MASK 0x00000004L 18511#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN_MASK 0x00000008L 18512#define VGT_GROUP_VECT_0_CNTL__STRIDE_MASK 0x0000FF00L 18513#define VGT_GROUP_VECT_0_CNTL__SHIFT_MASK 0x00FF0000L 18514//VGT_GROUP_VECT_1_CNTL 18515#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN__SHIFT 0x0 18516#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN__SHIFT 0x1 18517#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN__SHIFT 0x2 18518#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN__SHIFT 0x3 18519#define VGT_GROUP_VECT_1_CNTL__STRIDE__SHIFT 0x8 18520#define VGT_GROUP_VECT_1_CNTL__SHIFT__SHIFT 0x10 18521#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN_MASK 0x00000001L 18522#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN_MASK 0x00000002L 18523#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN_MASK 0x00000004L 18524#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN_MASK 0x00000008L 18525#define VGT_GROUP_VECT_1_CNTL__STRIDE_MASK 0x0000FF00L 18526#define VGT_GROUP_VECT_1_CNTL__SHIFT_MASK 0x00FF0000L 18527//VGT_GROUP_VECT_0_FMT_CNTL 18528#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV__SHIFT 0x0 18529#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET__SHIFT 0x4 18530#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV__SHIFT 0x8 18531#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET__SHIFT 0xc 18532#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV__SHIFT 0x10 18533#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET__SHIFT 0x14 18534#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV__SHIFT 0x18 18535#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET__SHIFT 0x1c 18536#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV_MASK 0x0000000FL 18537#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET_MASK 0x000000F0L 18538#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV_MASK 0x00000F00L 18539#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET_MASK 0x0000F000L 18540#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV_MASK 0x000F0000L 18541#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET_MASK 0x00F00000L 18542#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV_MASK 0x0F000000L 18543#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET_MASK 0xF0000000L 18544//VGT_GROUP_VECT_1_FMT_CNTL 18545#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV__SHIFT 0x0 18546#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET__SHIFT 0x4 18547#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV__SHIFT 0x8 18548#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET__SHIFT 0xc 18549#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV__SHIFT 0x10 18550#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET__SHIFT 0x14 18551#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV__SHIFT 0x18 18552#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET__SHIFT 0x1c 18553#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV_MASK 0x0000000FL 18554#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET_MASK 0x000000F0L 18555#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV_MASK 0x00000F00L 18556#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET_MASK 0x0000F000L 18557#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV_MASK 0x000F0000L 18558#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET_MASK 0x00F00000L 18559#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV_MASK 0x0F000000L 18560#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET_MASK 0xF0000000L 18561//VGT_GS_MODE 18562#define VGT_GS_MODE__MODE__SHIFT 0x0 18563#define VGT_GS_MODE__RESERVED_0__SHIFT 0x3 18564#define VGT_GS_MODE__CUT_MODE__SHIFT 0x4 18565#define VGT_GS_MODE__RESERVED_1__SHIFT 0x6 18566#define VGT_GS_MODE__GS_C_PACK_EN__SHIFT 0xb 18567#define VGT_GS_MODE__RESERVED_2__SHIFT 0xc 18568#define VGT_GS_MODE__ES_PASSTHRU__SHIFT 0xd 18569#define VGT_GS_MODE__RESERVED_3__SHIFT 0xe 18570#define VGT_GS_MODE__RESERVED_4__SHIFT 0xf 18571#define VGT_GS_MODE__RESERVED_5__SHIFT 0x10 18572#define VGT_GS_MODE__PARTIAL_THD_AT_EOI__SHIFT 0x11 18573#define VGT_GS_MODE__SUPPRESS_CUTS__SHIFT 0x12 18574#define VGT_GS_MODE__ES_WRITE_OPTIMIZE__SHIFT 0x13 18575#define VGT_GS_MODE__GS_WRITE_OPTIMIZE__SHIFT 0x14 18576#define VGT_GS_MODE__ONCHIP__SHIFT 0x15 18577#define VGT_GS_MODE__MODE_MASK 0x00000007L 18578#define VGT_GS_MODE__RESERVED_0_MASK 0x00000008L 18579#define VGT_GS_MODE__CUT_MODE_MASK 0x00000030L 18580#define VGT_GS_MODE__RESERVED_1_MASK 0x000007C0L 18581#define VGT_GS_MODE__GS_C_PACK_EN_MASK 0x00000800L 18582#define VGT_GS_MODE__RESERVED_2_MASK 0x00001000L 18583#define VGT_GS_MODE__ES_PASSTHRU_MASK 0x00002000L 18584#define VGT_GS_MODE__RESERVED_3_MASK 0x00004000L 18585#define VGT_GS_MODE__RESERVED_4_MASK 0x00008000L 18586#define VGT_GS_MODE__RESERVED_5_MASK 0x00010000L 18587#define VGT_GS_MODE__PARTIAL_THD_AT_EOI_MASK 0x00020000L 18588#define VGT_GS_MODE__SUPPRESS_CUTS_MASK 0x00040000L 18589#define VGT_GS_MODE__ES_WRITE_OPTIMIZE_MASK 0x00080000L 18590#define VGT_GS_MODE__GS_WRITE_OPTIMIZE_MASK 0x00100000L 18591#define VGT_GS_MODE__ONCHIP_MASK 0x00600000L 18592//VGT_GS_ONCHIP_CNTL 18593#define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP__SHIFT 0x0 18594#define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP__SHIFT 0xb 18595#define VGT_GS_ONCHIP_CNTL__GS_INST_PRIMS_IN_SUBGRP__SHIFT 0x16 18596#define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP_MASK 0x000007FFL 18597#define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP_MASK 0x003FF800L 18598#define VGT_GS_ONCHIP_CNTL__GS_INST_PRIMS_IN_SUBGRP_MASK 0xFFC00000L 18599//PA_SC_MODE_CNTL_0 18600#define PA_SC_MODE_CNTL_0__MSAA_ENABLE__SHIFT 0x0 18601#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE__SHIFT 0x1 18602#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE__SHIFT 0x2 18603#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR__SHIFT 0x3 18604#define PA_SC_MODE_CNTL_0__SCALE_LINE_WIDTH_PAD__SHIFT 0x4 18605#define PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE__SHIFT 0x5 18606#define PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB__SHIFT 0x6 18607#define PA_SC_MODE_CNTL_0__MSAA_ENABLE_MASK 0x00000001L 18608#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE_MASK 0x00000002L 18609#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE_MASK 0x00000004L 18610#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR_MASK 0x00000008L 18611#define PA_SC_MODE_CNTL_0__SCALE_LINE_WIDTH_PAD_MASK 0x00000010L 18612#define PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE_MASK 0x00000020L 18613#define PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB_MASK 0x00000040L 18614//PA_SC_MODE_CNTL_1 18615#define PA_SC_MODE_CNTL_1__WALK_SIZE__SHIFT 0x0 18616#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT__SHIFT 0x1 18617#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST__SHIFT 0x2 18618#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE__SHIFT 0x3 18619#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE__SHIFT 0x4 18620#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE__SHIFT 0x7 18621#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE__SHIFT 0x8 18622#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE__SHIFT 0x9 18623#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR__SHIFT 0xa 18624#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT__SHIFT 0xb 18625#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET__SHIFT 0xc 18626#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT__SHIFT 0xd 18627#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z__SHIFT 0xe 18628#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK__SHIFT 0xf 18629#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE__SHIFT 0x10 18630#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE__SHIFT 0x11 18631#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE__SHIFT 0x12 18632#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE__SHIFT 0x13 18633#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE__SHIFT 0x14 18634#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE__SHIFT 0x18 18635#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE__SHIFT 0x19 18636#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE__SHIFT 0x1a 18637#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE__SHIFT 0x1b 18638#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK__SHIFT 0x1c 18639#define PA_SC_MODE_CNTL_1__WALK_SIZE_MASK 0x00000001L 18640#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT_MASK 0x00000002L 18641#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST_MASK 0x00000004L 18642#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE_MASK 0x00000008L 18643#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE_MASK 0x00000070L 18644#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE_MASK 0x00000080L 18645#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE_MASK 0x00000100L 18646#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE_MASK 0x00000200L 18647#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR_MASK 0x00000400L 18648#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT_MASK 0x00000800L 18649#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET_MASK 0x00001000L 18650#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT_MASK 0x00002000L 18651#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z_MASK 0x00004000L 18652#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK_MASK 0x00008000L 18653#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE_MASK 0x00010000L 18654#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE_MASK 0x00020000L 18655#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE_MASK 0x00040000L 18656#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE_MASK 0x00080000L 18657#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_MASK 0x00F00000L 18658#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE_MASK 0x01000000L 18659#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE_MASK 0x02000000L 18660#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK 0x04000000L 18661#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE_MASK 0x08000000L 18662#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK_MASK 0x70000000L 18663//VGT_ENHANCE 18664#define VGT_ENHANCE__MISC__SHIFT 0x0 18665#define VGT_ENHANCE__MISC_MASK 0xFFFFFFFFL 18666//VGT_GS_PER_ES 18667#define VGT_GS_PER_ES__GS_PER_ES__SHIFT 0x0 18668#define VGT_GS_PER_ES__GS_PER_ES_MASK 0x000007FFL 18669//VGT_ES_PER_GS 18670#define VGT_ES_PER_GS__ES_PER_GS__SHIFT 0x0 18671#define VGT_ES_PER_GS__ES_PER_GS_MASK 0x000007FFL 18672//VGT_GS_PER_VS 18673#define VGT_GS_PER_VS__GS_PER_VS__SHIFT 0x0 18674#define VGT_GS_PER_VS__GS_PER_VS_MASK 0x0000000FL 18675//VGT_GSVS_RING_OFFSET_1 18676#define VGT_GSVS_RING_OFFSET_1__OFFSET__SHIFT 0x0 18677#define VGT_GSVS_RING_OFFSET_1__OFFSET_MASK 0x00007FFFL 18678//VGT_GSVS_RING_OFFSET_2 18679#define VGT_GSVS_RING_OFFSET_2__OFFSET__SHIFT 0x0 18680#define VGT_GSVS_RING_OFFSET_2__OFFSET_MASK 0x00007FFFL 18681//VGT_GSVS_RING_OFFSET_3 18682#define VGT_GSVS_RING_OFFSET_3__OFFSET__SHIFT 0x0 18683#define VGT_GSVS_RING_OFFSET_3__OFFSET_MASK 0x00007FFFL 18684//VGT_GS_OUT_PRIM_TYPE 18685#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE__SHIFT 0x0 18686#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1__SHIFT 0x8 18687#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2__SHIFT 0x10 18688#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3__SHIFT 0x16 18689#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM__SHIFT 0x1f 18690#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_MASK 0x0000003FL 18691#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1_MASK 0x00003F00L 18692#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2_MASK 0x003F0000L 18693#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3_MASK 0x0FC00000L 18694#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM_MASK 0x80000000L 18695//IA_ENHANCE 18696#define IA_ENHANCE__MISC__SHIFT 0x0 18697#define IA_ENHANCE__MISC_MASK 0xFFFFFFFFL 18698//VGT_DMA_SIZE 18699#define VGT_DMA_SIZE__NUM_INDICES__SHIFT 0x0 18700#define VGT_DMA_SIZE__NUM_INDICES_MASK 0xFFFFFFFFL 18701//VGT_DMA_MAX_SIZE 18702#define VGT_DMA_MAX_SIZE__MAX_SIZE__SHIFT 0x0 18703#define VGT_DMA_MAX_SIZE__MAX_SIZE_MASK 0xFFFFFFFFL 18704//VGT_DMA_INDEX_TYPE 18705#define VGT_DMA_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0 18706#define VGT_DMA_INDEX_TYPE__SWAP_MODE__SHIFT 0x2 18707#define VGT_DMA_INDEX_TYPE__BUF_TYPE__SHIFT 0x4 18708#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY__SHIFT 0x6 18709#define VGT_DMA_INDEX_TYPE__PRIMGEN_EN__SHIFT 0x8 18710#define VGT_DMA_INDEX_TYPE__NOT_EOP__SHIFT 0x9 18711#define VGT_DMA_INDEX_TYPE__REQ_PATH__SHIFT 0xa 18712#define VGT_DMA_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L 18713#define VGT_DMA_INDEX_TYPE__SWAP_MODE_MASK 0x0000000CL 18714#define VGT_DMA_INDEX_TYPE__BUF_TYPE_MASK 0x00000030L 18715#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY_MASK 0x00000040L 18716#define VGT_DMA_INDEX_TYPE__PRIMGEN_EN_MASK 0x00000100L 18717#define VGT_DMA_INDEX_TYPE__NOT_EOP_MASK 0x00000200L 18718#define VGT_DMA_INDEX_TYPE__REQ_PATH_MASK 0x00000400L 18719//WD_ENHANCE 18720#define WD_ENHANCE__MISC__SHIFT 0x0 18721#define WD_ENHANCE__MISC_MASK 0xFFFFFFFFL 18722//VGT_PRIMITIVEID_EN 18723#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN__SHIFT 0x0 18724#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI__SHIFT 0x1 18725#define VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE__SHIFT 0x2 18726#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN_MASK 0x00000001L 18727#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI_MASK 0x00000002L 18728#define VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE_MASK 0x00000004L 18729//VGT_DMA_NUM_INSTANCES 18730#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0 18731#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES_MASK 0xFFFFFFFFL 18732//VGT_PRIMITIVEID_RESET 18733#define VGT_PRIMITIVEID_RESET__VALUE__SHIFT 0x0 18734#define VGT_PRIMITIVEID_RESET__VALUE_MASK 0xFFFFFFFFL 18735//VGT_EVENT_INITIATOR 18736#define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x0 18737#define VGT_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0xa 18738#define VGT_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT 0x1b 18739#define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK 0x0000003FL 18740#define VGT_EVENT_INITIATOR__ADDRESS_HI_MASK 0x07FFFC00L 18741#define VGT_EVENT_INITIATOR__EXTENDED_EVENT_MASK 0x08000000L 18742//VGT_GS_MAX_PRIMS_PER_SUBGROUP 18743#define VGT_GS_MAX_PRIMS_PER_SUBGROUP__MAX_PRIMS_PER_SUBGROUP__SHIFT 0x0 18744#define VGT_GS_MAX_PRIMS_PER_SUBGROUP__MAX_PRIMS_PER_SUBGROUP_MASK 0x0000FFFFL 18745//VGT_DRAW_PAYLOAD_CNTL 18746#define VGT_DRAW_PAYLOAD_CNTL__OBJPRIM_ID_EN__SHIFT 0x0 18747#define VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX__SHIFT 0x1 18748#define VGT_DRAW_PAYLOAD_CNTL__EN_PIPELINE_PRIMID__SHIFT 0x2 18749#define VGT_DRAW_PAYLOAD_CNTL__OBJECT_ID_INST_EN__SHIFT 0x3 18750#define VGT_DRAW_PAYLOAD_CNTL__OBJPRIM_ID_EN_MASK 0x00000001L 18751#define VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX_MASK 0x00000002L 18752#define VGT_DRAW_PAYLOAD_CNTL__EN_PIPELINE_PRIMID_MASK 0x00000004L 18753#define VGT_DRAW_PAYLOAD_CNTL__OBJECT_ID_INST_EN_MASK 0x00000008L 18754//VGT_INSTANCE_STEP_RATE_0 18755#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE__SHIFT 0x0 18756#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE_MASK 0xFFFFFFFFL 18757//VGT_INSTANCE_STEP_RATE_1 18758#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE__SHIFT 0x0 18759#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE_MASK 0xFFFFFFFFL 18760//VGT_ESGS_RING_ITEMSIZE 18761#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0 18762#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE_MASK 0x00007FFFL 18763//VGT_GSVS_RING_ITEMSIZE 18764#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0 18765#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE_MASK 0x00007FFFL 18766//VGT_REUSE_OFF 18767#define VGT_REUSE_OFF__REUSE_OFF__SHIFT 0x0 18768#define VGT_REUSE_OFF__REUSE_OFF_MASK 0x00000001L 18769//VGT_VTX_CNT_EN 18770#define VGT_VTX_CNT_EN__VTX_CNT_EN__SHIFT 0x0 18771#define VGT_VTX_CNT_EN__VTX_CNT_EN_MASK 0x00000001L 18772//DB_HTILE_SURFACE 18773#define DB_HTILE_SURFACE__FULL_CACHE__SHIFT 0x1 18774#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN__SHIFT 0x2 18775#define DB_HTILE_SURFACE__PRELOAD__SHIFT 0x3 18776#define DB_HTILE_SURFACE__PREFETCH_WIDTH__SHIFT 0x4 18777#define DB_HTILE_SURFACE__PREFETCH_HEIGHT__SHIFT 0xa 18778#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE__SHIFT 0x10 18779#define DB_HTILE_SURFACE__PIPE_ALIGNED__SHIFT 0x12 18780#define DB_HTILE_SURFACE__RB_ALIGNED__SHIFT 0x13 18781#define DB_HTILE_SURFACE__FULL_CACHE_MASK 0x00000002L 18782#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN_MASK 0x00000004L 18783#define DB_HTILE_SURFACE__PRELOAD_MASK 0x00000008L 18784#define DB_HTILE_SURFACE__PREFETCH_WIDTH_MASK 0x000003F0L 18785#define DB_HTILE_SURFACE__PREFETCH_HEIGHT_MASK 0x0000FC00L 18786#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE_MASK 0x00010000L 18787#define DB_HTILE_SURFACE__PIPE_ALIGNED_MASK 0x00040000L 18788#define DB_HTILE_SURFACE__RB_ALIGNED_MASK 0x00080000L 18789//DB_SRESULTS_COMPARE_STATE0 18790#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0__SHIFT 0x0 18791#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0__SHIFT 0x4 18792#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0__SHIFT 0xc 18793#define DB_SRESULTS_COMPARE_STATE0__ENABLE0__SHIFT 0x18 18794#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0_MASK 0x00000007L 18795#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0_MASK 0x00000FF0L 18796#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0_MASK 0x000FF000L 18797#define DB_SRESULTS_COMPARE_STATE0__ENABLE0_MASK 0x01000000L 18798//DB_SRESULTS_COMPARE_STATE1 18799#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1__SHIFT 0x0 18800#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1__SHIFT 0x4 18801#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1__SHIFT 0xc 18802#define DB_SRESULTS_COMPARE_STATE1__ENABLE1__SHIFT 0x18 18803#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1_MASK 0x00000007L 18804#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1_MASK 0x00000FF0L 18805#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1_MASK 0x000FF000L 18806#define DB_SRESULTS_COMPARE_STATE1__ENABLE1_MASK 0x01000000L 18807//DB_PRELOAD_CONTROL 18808#define DB_PRELOAD_CONTROL__START_X__SHIFT 0x0 18809#define DB_PRELOAD_CONTROL__START_Y__SHIFT 0x8 18810#define DB_PRELOAD_CONTROL__MAX_X__SHIFT 0x10 18811#define DB_PRELOAD_CONTROL__MAX_Y__SHIFT 0x18 18812#define DB_PRELOAD_CONTROL__START_X_MASK 0x000000FFL 18813#define DB_PRELOAD_CONTROL__START_Y_MASK 0x0000FF00L 18814#define DB_PRELOAD_CONTROL__MAX_X_MASK 0x00FF0000L 18815#define DB_PRELOAD_CONTROL__MAX_Y_MASK 0xFF000000L 18816//VGT_STRMOUT_BUFFER_SIZE_0 18817#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE__SHIFT 0x0 18818#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE_MASK 0xFFFFFFFFL 18819//VGT_STRMOUT_VTX_STRIDE_0 18820#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE__SHIFT 0x0 18821#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE_MASK 0x000003FFL 18822//VGT_STRMOUT_BUFFER_OFFSET_0 18823#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET__SHIFT 0x0 18824#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET_MASK 0xFFFFFFFFL 18825//VGT_STRMOUT_BUFFER_SIZE_1 18826#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE__SHIFT 0x0 18827#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE_MASK 0xFFFFFFFFL 18828//VGT_STRMOUT_VTX_STRIDE_1 18829#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE__SHIFT 0x0 18830#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE_MASK 0x000003FFL 18831//VGT_STRMOUT_BUFFER_OFFSET_1 18832#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET__SHIFT 0x0 18833#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET_MASK 0xFFFFFFFFL 18834//VGT_STRMOUT_BUFFER_SIZE_2 18835#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE__SHIFT 0x0 18836#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE_MASK 0xFFFFFFFFL 18837//VGT_STRMOUT_VTX_STRIDE_2 18838#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE__SHIFT 0x0 18839#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE_MASK 0x000003FFL 18840//VGT_STRMOUT_BUFFER_OFFSET_2 18841#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET__SHIFT 0x0 18842#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET_MASK 0xFFFFFFFFL 18843//VGT_STRMOUT_BUFFER_SIZE_3 18844#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE__SHIFT 0x0 18845#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE_MASK 0xFFFFFFFFL 18846//VGT_STRMOUT_VTX_STRIDE_3 18847#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE__SHIFT 0x0 18848#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE_MASK 0x000003FFL 18849//VGT_STRMOUT_BUFFER_OFFSET_3 18850#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET__SHIFT 0x0 18851#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET_MASK 0xFFFFFFFFL 18852//VGT_STRMOUT_DRAW_OPAQUE_OFFSET 18853#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET__SHIFT 0x0 18854#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET_MASK 0xFFFFFFFFL 18855//VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE 18856#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE__SHIFT 0x0 18857#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE_MASK 0xFFFFFFFFL 18858//VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE 18859#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE__SHIFT 0x0 18860#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE_MASK 0x000001FFL 18861//VGT_GS_MAX_VERT_OUT 18862#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT__SHIFT 0x0 18863#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT_MASK 0x000007FFL 18864//VGT_TESS_DISTRIBUTION 18865#define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE__SHIFT 0x0 18866#define VGT_TESS_DISTRIBUTION__ACCUM_TRI__SHIFT 0x8 18867#define VGT_TESS_DISTRIBUTION__ACCUM_QUAD__SHIFT 0x10 18868#define VGT_TESS_DISTRIBUTION__DONUT_SPLIT__SHIFT 0x18 18869#define VGT_TESS_DISTRIBUTION__TRAP_SPLIT__SHIFT 0x1d 18870#define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE_MASK 0x000000FFL 18871#define VGT_TESS_DISTRIBUTION__ACCUM_TRI_MASK 0x0000FF00L 18872#define VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK 0x00FF0000L 18873#define VGT_TESS_DISTRIBUTION__DONUT_SPLIT_MASK 0x1F000000L 18874#define VGT_TESS_DISTRIBUTION__TRAP_SPLIT_MASK 0xE0000000L 18875//VGT_SHADER_STAGES_EN 18876#define VGT_SHADER_STAGES_EN__LS_EN__SHIFT 0x0 18877#define VGT_SHADER_STAGES_EN__HS_EN__SHIFT 0x2 18878#define VGT_SHADER_STAGES_EN__ES_EN__SHIFT 0x3 18879#define VGT_SHADER_STAGES_EN__GS_EN__SHIFT 0x5 18880#define VGT_SHADER_STAGES_EN__VS_EN__SHIFT 0x6 18881#define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN__SHIFT 0x9 18882#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0__SHIFT 0xa 18883#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1__SHIFT 0xb 18884#define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN__SHIFT 0xc 18885#define VGT_SHADER_STAGES_EN__PRIMGEN_EN__SHIFT 0xd 18886#define VGT_SHADER_STAGES_EN__ORDERED_ID_MODE__SHIFT 0xe 18887#define VGT_SHADER_STAGES_EN__MAX_PRIMGRP_IN_WAVE__SHIFT 0xf 18888#define VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH__SHIFT 0x13 18889#define VGT_SHADER_STAGES_EN__LS_EN_MASK 0x00000003L 18890#define VGT_SHADER_STAGES_EN__HS_EN_MASK 0x00000004L 18891#define VGT_SHADER_STAGES_EN__ES_EN_MASK 0x00000018L 18892#define VGT_SHADER_STAGES_EN__GS_EN_MASK 0x00000020L 18893#define VGT_SHADER_STAGES_EN__VS_EN_MASK 0x000000C0L 18894#define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN_MASK 0x00000200L 18895#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0_MASK 0x00000400L 18896#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1_MASK 0x00000800L 18897#define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN_MASK 0x00001000L 18898#define VGT_SHADER_STAGES_EN__PRIMGEN_EN_MASK 0x00002000L 18899#define VGT_SHADER_STAGES_EN__ORDERED_ID_MODE_MASK 0x00004000L 18900#define VGT_SHADER_STAGES_EN__MAX_PRIMGRP_IN_WAVE_MASK 0x00078000L 18901#define VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH_MASK 0x00080000L 18902//VGT_LS_HS_CONFIG 18903#define VGT_LS_HS_CONFIG__NUM_PATCHES__SHIFT 0x0 18904#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8 18905#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP__SHIFT 0xe 18906#define VGT_LS_HS_CONFIG__NUM_PATCHES_MASK 0x000000FFL 18907#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x00003F00L 18908#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP_MASK 0x000FC000L 18909//VGT_GS_VERT_ITEMSIZE 18910#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE__SHIFT 0x0 18911#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE_MASK 0x00007FFFL 18912//VGT_GS_VERT_ITEMSIZE_1 18913#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE__SHIFT 0x0 18914#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE_MASK 0x00007FFFL 18915//VGT_GS_VERT_ITEMSIZE_2 18916#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE__SHIFT 0x0 18917#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE_MASK 0x00007FFFL 18918//VGT_GS_VERT_ITEMSIZE_3 18919#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE__SHIFT 0x0 18920#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE_MASK 0x00007FFFL 18921//VGT_TF_PARAM 18922#define VGT_TF_PARAM__TYPE__SHIFT 0x0 18923#define VGT_TF_PARAM__PARTITIONING__SHIFT 0x2 18924#define VGT_TF_PARAM__TOPOLOGY__SHIFT 0x5 18925#define VGT_TF_PARAM__RESERVED_REDUC_AXIS__SHIFT 0x8 18926#define VGT_TF_PARAM__DEPRECATED__SHIFT 0x9 18927#define VGT_TF_PARAM__DISABLE_DONUTS__SHIFT 0xe 18928#define VGT_TF_PARAM__RDREQ_POLICY__SHIFT 0xf 18929#define VGT_TF_PARAM__DISTRIBUTION_MODE__SHIFT 0x11 18930#define VGT_TF_PARAM__TYPE_MASK 0x00000003L 18931#define VGT_TF_PARAM__PARTITIONING_MASK 0x0000001CL 18932#define VGT_TF_PARAM__TOPOLOGY_MASK 0x000000E0L 18933#define VGT_TF_PARAM__RESERVED_REDUC_AXIS_MASK 0x00000100L 18934#define VGT_TF_PARAM__DEPRECATED_MASK 0x00000200L 18935#define VGT_TF_PARAM__DISABLE_DONUTS_MASK 0x00004000L 18936#define VGT_TF_PARAM__RDREQ_POLICY_MASK 0x00008000L 18937#define VGT_TF_PARAM__DISTRIBUTION_MODE_MASK 0x00060000L 18938//DB_ALPHA_TO_MASK 18939#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE__SHIFT 0x0 18940#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0__SHIFT 0x8 18941#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT 0xa 18942#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2__SHIFT 0xc 18943#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3__SHIFT 0xe 18944#define DB_ALPHA_TO_MASK__OFFSET_ROUND__SHIFT 0x10 18945#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE_MASK 0x00000001L 18946#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0_MASK 0x00000300L 18947#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1_MASK 0x00000C00L 18948#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2_MASK 0x00003000L 18949#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3_MASK 0x0000C000L 18950#define DB_ALPHA_TO_MASK__OFFSET_ROUND_MASK 0x00010000L 18951//VGT_DISPATCH_DRAW_INDEX 18952#define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX__SHIFT 0x0 18953#define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX_MASK 0xFFFFFFFFL 18954//PA_SU_POLY_OFFSET_DB_FMT_CNTL 18955#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS__SHIFT 0x0 18956#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT__SHIFT 0x8 18957#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS_MASK 0x000000FFL 18958#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT_MASK 0x00000100L 18959//PA_SU_POLY_OFFSET_CLAMP 18960#define PA_SU_POLY_OFFSET_CLAMP__CLAMP__SHIFT 0x0 18961#define PA_SU_POLY_OFFSET_CLAMP__CLAMP_MASK 0xFFFFFFFFL 18962//PA_SU_POLY_OFFSET_FRONT_SCALE 18963#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT 0x0 18964#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK 0xFFFFFFFFL 18965//PA_SU_POLY_OFFSET_FRONT_OFFSET 18966#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT 0x0 18967#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK 0xFFFFFFFFL 18968//PA_SU_POLY_OFFSET_BACK_SCALE 18969#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT 0x0 18970#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK 0xFFFFFFFFL 18971//PA_SU_POLY_OFFSET_BACK_OFFSET 18972#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT 0x0 18973#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK 0xFFFFFFFFL 18974//VGT_GS_INSTANCE_CNT 18975#define VGT_GS_INSTANCE_CNT__ENABLE__SHIFT 0x0 18976#define VGT_GS_INSTANCE_CNT__CNT__SHIFT 0x2 18977#define VGT_GS_INSTANCE_CNT__ENABLE_MASK 0x00000001L 18978#define VGT_GS_INSTANCE_CNT__CNT_MASK 0x000001FCL 18979//VGT_STRMOUT_CONFIG 18980#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN__SHIFT 0x0 18981#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN__SHIFT 0x1 18982#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN__SHIFT 0x2 18983#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN__SHIFT 0x3 18984#define VGT_STRMOUT_CONFIG__RAST_STREAM__SHIFT 0x4 18985#define VGT_STRMOUT_CONFIG__EN_PRIMS_NEEDED_CNT__SHIFT 0x7 18986#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK__SHIFT 0x8 18987#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK__SHIFT 0x1f 18988#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN_MASK 0x00000001L 18989#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN_MASK 0x00000002L 18990#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN_MASK 0x00000004L 18991#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN_MASK 0x00000008L 18992#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK 0x00000070L 18993#define VGT_STRMOUT_CONFIG__EN_PRIMS_NEEDED_CNT_MASK 0x00000080L 18994#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK_MASK 0x00000F00L 18995#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK_MASK 0x80000000L 18996//VGT_STRMOUT_BUFFER_CONFIG 18997#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN__SHIFT 0x0 18998#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN__SHIFT 0x4 18999#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN__SHIFT 0x8 19000#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN__SHIFT 0xc
19001#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN_MASK 0x0000000FL 19002#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN_MASK 0x000000F0L 19003#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN_MASK 0x00000F00L 19004#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN_MASK 0x0000F000L 19005//VGT_DMA_EVENT_INITIATOR 19006#define VGT_DMA_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x0 19007#define VGT_DMA_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0xa 19008#define VGT_DMA_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT 0x1b 19009#define VGT_DMA_EVENT_INITIATOR__EVENT_TYPE_MASK 0x0000003FL 19010#define VGT_DMA_EVENT_INITIATOR__ADDRESS_HI_MASK 0x07FFFC00L 19011#define VGT_DMA_EVENT_INITIATOR__EXTENDED_EVENT_MASK 0x08000000L 19012//PA_SC_CENTROID_PRIORITY_0 19013#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0__SHIFT 0x0 19014#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1__SHIFT 0x4 19015#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2__SHIFT 0x8 19016#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3__SHIFT 0xc 19017#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4__SHIFT 0x10 19018#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5__SHIFT 0x14 19019#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6__SHIFT 0x18 19020#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7__SHIFT 0x1c 19021#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0_MASK 0x0000000FL 19022#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1_MASK 0x000000F0L 19023#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2_MASK 0x00000F00L 19024#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3_MASK 0x0000F000L 19025#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4_MASK 0x000F0000L 19026#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5_MASK 0x00F00000L 19027#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6_MASK 0x0F000000L 19028#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7_MASK 0xF0000000L 19029//PA_SC_CENTROID_PRIORITY_1 19030#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8__SHIFT 0x0 19031#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9__SHIFT 0x4 19032#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10__SHIFT 0x8 19033#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11__SHIFT 0xc 19034#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12__SHIFT 0x10 19035#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13__SHIFT 0x14 19036#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14__SHIFT 0x18 19037#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15__SHIFT 0x1c 19038#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8_MASK 0x0000000FL 19039#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9_MASK 0x000000F0L 19040#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10_MASK 0x00000F00L 19041#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11_MASK 0x0000F000L 19042#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12_MASK 0x000F0000L 19043#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13_MASK 0x00F00000L 19044#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14_MASK 0x0F000000L 19045#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15_MASK 0xF0000000L 19046//PA_SC_LINE_CNTL 19047#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT 0x9 19048#define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT 0xa 19049#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA__SHIFT 0xb 19050#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA__SHIFT 0xc 19051#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK 0x00000200L 19052#define PA_SC_LINE_CNTL__LAST_PIXEL_MASK 0x00000400L 19053#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA_MASK 0x00000800L 19054#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA_MASK 0x00001000L 19055//PA_SC_AA_CONFIG 19056#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT 0x0 19057#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN__SHIFT 0x4 19058#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT 0xd 19059#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES__SHIFT 0x14 19060#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE__SHIFT 0x18 19061#define PA_SC_AA_CONFIG__COVERAGE_TO_SHADER_SELECT__SHIFT 0x1a 19062#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK 0x00000007L 19063#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN_MASK 0x00000010L 19064#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK 0x0001E000L 19065#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES_MASK 0x00700000L 19066#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE_MASK 0x03000000L 19067#define PA_SC_AA_CONFIG__COVERAGE_TO_SHADER_SELECT_MASK 0x0C000000L 19068//PA_SU_VTX_CNTL 19069#define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT 0x0 19070#define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT 0x1 19071#define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT 0x3 19072#define PA_SU_VTX_CNTL__PIX_CENTER_MASK 0x00000001L 19073#define PA_SU_VTX_CNTL__ROUND_MODE_MASK 0x00000006L 19074#define PA_SU_VTX_CNTL__QUANT_MODE_MASK 0x00000038L 19075//PA_CL_GB_VERT_CLIP_ADJ 19076#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0 19077#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL 19078//PA_CL_GB_VERT_DISC_ADJ 19079#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT 0x0 19080#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL 19081//PA_CL_GB_HORZ_CLIP_ADJ 19082#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0 19083#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL 19084//PA_CL_GB_HORZ_DISC_ADJ 19085#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT 0x0 19086#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL 19087//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 19088#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X__SHIFT 0x0 19089#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y__SHIFT 0x4 19090#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X__SHIFT 0x8 19091#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y__SHIFT 0xc 19092#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X__SHIFT 0x10 19093#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y__SHIFT 0x14 19094#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X__SHIFT 0x18 19095#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y__SHIFT 0x1c 19096#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X_MASK 0x0000000FL 19097#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y_MASK 0x000000F0L 19098#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X_MASK 0x00000F00L 19099#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y_MASK 0x0000F000L 19100#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X_MASK 0x000F0000L 19101#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y_MASK 0x00F00000L 19102#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X_MASK 0x0F000000L 19103#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y_MASK 0xF0000000L 19104//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 19105#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X__SHIFT 0x0 19106#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y__SHIFT 0x4 19107#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X__SHIFT 0x8 19108#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y__SHIFT 0xc 19109#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X__SHIFT 0x10 19110#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y__SHIFT 0x14 19111#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X__SHIFT 0x18 19112#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y__SHIFT 0x1c 19113#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X_MASK 0x0000000FL 19114#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y_MASK 0x000000F0L 19115#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X_MASK 0x00000F00L 19116#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y_MASK 0x0000F000L 19117#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X_MASK 0x000F0000L 19118#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y_MASK 0x00F00000L 19119#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X_MASK 0x0F000000L 19120#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y_MASK 0xF0000000L 19121//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 19122#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X__SHIFT 0x0 19123#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y__SHIFT 0x4 19124#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X__SHIFT 0x8 19125#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y__SHIFT 0xc 19126#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X__SHIFT 0x10 19127#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y__SHIFT 0x14 19128#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X__SHIFT 0x18 19129#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y__SHIFT 0x1c 19130#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X_MASK 0x0000000FL 19131#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y_MASK 0x000000F0L 19132#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X_MASK 0x00000F00L 19133#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y_MASK 0x0000F000L 19134#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X_MASK 0x000F0000L 19135#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y_MASK 0x00F00000L 19136#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X_MASK 0x0F000000L 19137#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y_MASK 0xF0000000L 19138//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 19139#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X__SHIFT 0x0 19140#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y__SHIFT 0x4 19141#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X__SHIFT 0x8 19142#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y__SHIFT 0xc 19143#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X__SHIFT 0x10 19144#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y__SHIFT 0x14 19145#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X__SHIFT 0x18 19146#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y__SHIFT 0x1c 19147#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X_MASK 0x0000000FL 19148#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y_MASK 0x000000F0L 19149#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X_MASK 0x00000F00L 19150#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y_MASK 0x0000F000L 19151#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X_MASK 0x000F0000L 19152#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y_MASK 0x00F00000L 19153#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X_MASK 0x0F000000L 19154#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y_MASK 0xF0000000L 19155//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 19156#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X__SHIFT 0x0 19157#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y__SHIFT 0x4 19158#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X__SHIFT 0x8 19159#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y__SHIFT 0xc 19160#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X__SHIFT 0x10 19161#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y__SHIFT 0x14 19162#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X__SHIFT 0x18 19163#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y__SHIFT 0x1c 19164#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X_MASK 0x0000000FL 19165#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y_MASK 0x000000F0L 19166#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X_MASK 0x00000F00L 19167#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y_MASK 0x0000F000L 19168#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X_MASK 0x000F0000L 19169#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y_MASK 0x00F00000L 19170#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X_MASK 0x0F000000L 19171#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y_MASK 0xF0000000L 19172//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 19173#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X__SHIFT 0x0 19174#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y__SHIFT 0x4 19175#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X__SHIFT 0x8 19176#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y__SHIFT 0xc 19177#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X__SHIFT 0x10 19178#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y__SHIFT 0x14 19179#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X__SHIFT 0x18 19180#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y__SHIFT 0x1c 19181#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X_MASK 0x0000000FL 19182#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y_MASK 0x000000F0L 19183#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X_MASK 0x00000F00L 19184#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y_MASK 0x0000F000L 19185#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X_MASK 0x000F0000L 19186#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y_MASK 0x00F00000L 19187#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X_MASK 0x0F000000L 19188#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y_MASK 0xF0000000L 19189//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 19190#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X__SHIFT 0x0 19191#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y__SHIFT 0x4 19192#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X__SHIFT 0x8 19193#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y__SHIFT 0xc 19194#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X__SHIFT 0x10 19195#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y__SHIFT 0x14 19196#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X__SHIFT 0x18 19197#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y__SHIFT 0x1c 19198#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X_MASK 0x0000000FL 19199#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y_MASK 0x000000F0L 19200#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X_MASK 0x00000F00L 19201#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y_MASK 0x0000F000L 19202#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X_MASK 0x000F0000L 19203#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y_MASK 0x00F00000L 19204#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X_MASK 0x0F000000L 19205#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y_MASK 0xF0000000L 19206//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 19207#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X__SHIFT 0x0 19208#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y__SHIFT 0x4 19209#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X__SHIFT 0x8 19210#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y__SHIFT 0xc 19211#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X__SHIFT 0x10 19212#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y__SHIFT 0x14 19213#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X__SHIFT 0x18 19214#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y__SHIFT 0x1c 19215#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X_MASK 0x0000000FL 19216#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y_MASK 0x000000F0L 19217#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X_MASK 0x00000F00L 19218#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y_MASK 0x0000F000L 19219#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X_MASK 0x000F0000L 19220#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y_MASK 0x00F00000L 19221#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X_MASK 0x0F000000L 19222#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y_MASK 0xF0000000L 19223//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 19224#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X__SHIFT 0x0 19225#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y__SHIFT 0x4 19226#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X__SHIFT 0x8 19227#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y__SHIFT 0xc 19228#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X__SHIFT 0x10 19229#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y__SHIFT 0x14 19230#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X__SHIFT 0x18 19231#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y__SHIFT 0x1c 19232#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X_MASK 0x0000000FL 19233#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y_MASK 0x000000F0L 19234#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X_MASK 0x00000F00L 19235#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y_MASK 0x0000F000L 19236#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X_MASK 0x000F0000L 19237#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y_MASK 0x00F00000L 19238#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X_MASK 0x0F000000L 19239#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y_MASK 0xF0000000L 19240//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 19241#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X__SHIFT 0x0 19242#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y__SHIFT 0x4 19243#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X__SHIFT 0x8 19244#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y__SHIFT 0xc 19245#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X__SHIFT 0x10 19246#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y__SHIFT 0x14 19247#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X__SHIFT 0x18 19248#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y__SHIFT 0x1c 19249#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X_MASK 0x0000000FL 19250#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y_MASK 0x000000F0L 19251#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X_MASK 0x00000F00L 19252#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y_MASK 0x0000F000L 19253#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X_MASK 0x000F0000L 19254#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y_MASK 0x00F00000L 19255#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X_MASK 0x0F000000L 19256#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y_MASK 0xF0000000L 19257//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 19258#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X__SHIFT 0x0 19259#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y__SHIFT 0x4 19260#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X__SHIFT 0x8 19261#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y__SHIFT 0xc 19262#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X__SHIFT 0x10 19263#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y__SHIFT 0x14 19264#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X__SHIFT 0x18 19265#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y__SHIFT 0x1c 19266#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X_MASK 0x0000000FL 19267#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y_MASK 0x000000F0L 19268#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X_MASK 0x00000F00L 19269#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y_MASK 0x0000F000L 19270#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X_MASK 0x000F0000L 19271#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y_MASK 0x00F00000L 19272#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X_MASK 0x0F000000L 19273#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y_MASK 0xF0000000L 19274//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 19275#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X__SHIFT 0x0 19276#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y__SHIFT 0x4 19277#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X__SHIFT 0x8 19278#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y__SHIFT 0xc 19279#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X__SHIFT 0x10 19280#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y__SHIFT 0x14 19281#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X__SHIFT 0x18 19282#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y__SHIFT 0x1c 19283#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X_MASK 0x0000000FL 19284#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y_MASK 0x000000F0L 19285#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X_MASK 0x00000F00L 19286#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y_MASK 0x0000F000L 19287#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X_MASK 0x000F0000L 19288#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y_MASK 0x00F00000L 19289#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X_MASK 0x0F000000L 19290#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y_MASK 0xF0000000L 19291//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 19292#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X__SHIFT 0x0 19293#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y__SHIFT 0x4 19294#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X__SHIFT 0x8 19295#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y__SHIFT 0xc 19296#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X__SHIFT 0x10 19297#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y__SHIFT 0x14 19298#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X__SHIFT 0x18 19299#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y__SHIFT 0x1c 19300#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X_MASK 0x0000000FL 19301#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y_MASK 0x000000F0L 19302#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X_MASK 0x00000F00L 19303#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y_MASK 0x0000F000L 19304#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X_MASK 0x000F0000L 19305#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y_MASK 0x00F00000L 19306#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X_MASK 0x0F000000L 19307#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y_MASK 0xF0000000L 19308//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 19309#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X__SHIFT 0x0 19310#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y__SHIFT 0x4 19311#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X__SHIFT 0x8 19312#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y__SHIFT 0xc 19313#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X__SHIFT 0x10 19314#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y__SHIFT 0x14 19315#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X__SHIFT 0x18 19316#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y__SHIFT 0x1c 19317#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X_MASK 0x0000000FL 19318#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y_MASK 0x000000F0L 19319#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X_MASK 0x00000F00L 19320#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y_MASK 0x0000F000L 19321#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X_MASK 0x000F0000L 19322#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y_MASK 0x00F00000L 19323#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X_MASK 0x0F000000L 19324#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y_MASK 0xF0000000L 19325//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 19326#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X__SHIFT 0x0 19327#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y__SHIFT 0x4 19328#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X__SHIFT 0x8 19329#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y__SHIFT 0xc 19330#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X__SHIFT 0x10 19331#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y__SHIFT 0x14 19332#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X__SHIFT 0x18 19333#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y__SHIFT 0x1c 19334#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X_MASK 0x0000000FL 19335#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y_MASK 0x000000F0L 19336#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X_MASK 0x00000F00L 19337#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y_MASK 0x0000F000L 19338#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X_MASK 0x000F0000L 19339#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y_MASK 0x00F00000L 19340#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X_MASK 0x0F000000L 19341#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y_MASK 0xF0000000L 19342//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 19343#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X__SHIFT 0x0 19344#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y__SHIFT 0x4 19345#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X__SHIFT 0x8 19346#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y__SHIFT 0xc 19347#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X__SHIFT 0x10 19348#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y__SHIFT 0x14 19349#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X__SHIFT 0x18 19350#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y__SHIFT 0x1c 19351#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X_MASK 0x0000000FL 19352#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y_MASK 0x000000F0L 19353#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X_MASK 0x00000F00L 19354#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y_MASK 0x0000F000L 19355#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X_MASK 0x000F0000L 19356#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y_MASK 0x00F00000L 19357#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X_MASK 0x0F000000L 19358#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y_MASK 0xF0000000L 19359//PA_SC_AA_MASK_X0Y0_X1Y0 19360#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0__SHIFT 0x0 19361#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0__SHIFT 0x10 19362#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0_MASK 0x0000FFFFL 19363#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0_MASK 0xFFFF0000L 19364//PA_SC_AA_MASK_X0Y1_X1Y1 19365#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1__SHIFT 0x0 19366#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1__SHIFT 0x10 19367#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1_MASK 0x0000FFFFL 19368#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1_MASK 0xFFFF0000L 19369//PA_SC_SHADER_CONTROL 19370#define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES__SHIFT 0x0 19371#define PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID__SHIFT 0x2 19372#define PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION__SHIFT 0x3 19373#define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES_MASK 0x00000003L 19374#define PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID_MASK 0x00000004L 19375#define PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION_MASK 0x00000008L 19376//PA_SC_BINNER_CNTL_0 19377#define PA_SC_BINNER_CNTL_0__BINNING_MODE__SHIFT 0x0 19378#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X__SHIFT 0x2 19379#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y__SHIFT 0x3 19380#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND__SHIFT 0x4 19381#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND__SHIFT 0x7 19382#define PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN__SHIFT 0xa 19383#define PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN__SHIFT 0xd 19384#define PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM__SHIFT 0x12 19385#define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH__SHIFT 0x13 19386#define PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION__SHIFT 0x1b 19387#define PA_SC_BINNER_CNTL_0__BINNING_MODE_MASK 0x00000003L 19388#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_MASK 0x00000004L 19389#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_MASK 0x00000008L 19390#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND_MASK 0x00000070L 19391#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND_MASK 0x00000380L 19392#define PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN_MASK 0x00001C00L 19393#define PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN_MASK 0x0003E000L 19394#define PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM_MASK 0x00040000L 19395#define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH_MASK 0x07F80000L 19396#define PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION_MASK 0x08000000L 19397//PA_SC_BINNER_CNTL_1 19398#define PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT__SHIFT 0x0 19399#define PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH__SHIFT 0x10 19400#define PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT_MASK 0x0000FFFFL 19401#define PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH_MASK 0xFFFF0000L 19402//PA_SC_CONSERVATIVE_RASTERIZATION_CNTL 19403#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE__SHIFT 0x0 19404#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT__SHIFT 0x1 19405#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE__SHIFT 0x5 19406#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT__SHIFT 0x6 19407#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE__SHIFT 0xa 19408#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT__SHIFT 0xb 19409#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET__SHIFT 0xc 19410#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL__SHIFT 0xd 19411#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL__SHIFT 0xe 19412#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE__SHIFT 0xf 19413#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE__SHIFT 0x10 19414#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT 0x12 19415#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT 0x13 19416#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE__SHIFT 0x14 19417#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE__SHIFT 0x15 19418#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE__SHIFT 0x16 19419#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE__SHIFT 0x17 19420#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE__SHIFT 0x18 19421#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE_MASK 0x00000001L 19422#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT_MASK 0x0000001EL 19423#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE_MASK 0x00000020L 19424#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT_MASK 0x000003C0L 19425#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE_MASK 0x00000400L 19426#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT_MASK 0x00000800L 19427#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET_MASK 0x00001000L 19428#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL_MASK 0x00002000L 19429#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL_MASK 0x00004000L 19430#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE_MASK 0x00008000L 19431#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE_MASK 0x00030000L 19432#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK 0x00040000L 19433#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK 0x00080000L 19434#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE_MASK 0x00100000L 19435#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE_MASK 0x00200000L 19436#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE_MASK 0x00400000L 19437#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE_MASK 0x00800000L 19438#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE_MASK 0x01000000L 19439//PA_SC_NGG_MODE_CNTL 19440#define PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE__SHIFT 0x0 19441#define PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE_MASK 0x000007FFL 19442//VGT_VERTEX_REUSE_BLOCK_CNTL 19443#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT 0x0 19444#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK 0x000000FFL 19445//VGT_OUT_DEALLOC_CNTL 19446#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT 0x0 19447#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK 0x0000007FL 19448//CB_COLOR0_BASE 19449#define CB_COLOR0_BASE__BASE_256B__SHIFT 0x0 19450#define CB_COLOR0_BASE__BASE_256B_MASK 0xFFFFFFFFL 19451//CB_COLOR0_BASE_EXT 19452#define CB_COLOR0_BASE_EXT__BASE_256B__SHIFT 0x0 19453#define CB_COLOR0_BASE_EXT__BASE_256B_MASK 0x000000FFL 19454//CB_COLOR0_ATTRIB2 19455#define CB_COLOR0_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 19456#define CB_COLOR0_ATTRIB2__MIP0_WIDTH__SHIFT 0xe 19457#define CB_COLOR0_ATTRIB2__MAX_MIP__SHIFT 0x1c 19458#define CB_COLOR0_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL 19459#define CB_COLOR0_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L 19460#define CB_COLOR0_ATTRIB2__MAX_MIP_MASK 0xF0000000L 19461//CB_COLOR0_VIEW 19462#define CB_COLOR0_VIEW__SLICE_START__SHIFT 0x0 19463#define CB_COLOR0_VIEW__SLICE_MAX__SHIFT 0xd 19464#define CB_COLOR0_VIEW__MIP_LEVEL__SHIFT 0x18 19465#define CB_COLOR0_VIEW__SLICE_START_MASK 0x000007FFL 19466#define CB_COLOR0_VIEW__SLICE_MAX_MASK 0x00FFE000L 19467#define CB_COLOR0_VIEW__MIP_LEVEL_MASK 0x0F000000L 19468//CB_COLOR0_INFO 19469#define CB_COLOR0_INFO__ENDIAN__SHIFT 0x0 19470#define CB_COLOR0_INFO__FORMAT__SHIFT 0x2 19471#define CB_COLOR0_INFO__NUMBER_TYPE__SHIFT 0x8 19472#define CB_COLOR0_INFO__COMP_SWAP__SHIFT 0xb 19473#define CB_COLOR0_INFO__FAST_CLEAR__SHIFT 0xd 19474#define CB_COLOR0_INFO__COMPRESSION__SHIFT 0xe 19475#define CB_COLOR0_INFO__BLEND_CLAMP__SHIFT 0xf 19476#define CB_COLOR0_INFO__BLEND_BYPASS__SHIFT 0x10 19477#define CB_COLOR0_INFO__SIMPLE_FLOAT__SHIFT 0x11 19478#define CB_COLOR0_INFO__ROUND_MODE__SHIFT 0x12 19479#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 19480#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 19481#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a 19482#define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b 19483#define CB_COLOR0_INFO__DCC_ENABLE__SHIFT 0x1c 19484#define CB_COLOR0_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d 19485#define CB_COLOR0_INFO__ENDIAN_MASK 0x00000003L 19486#define CB_COLOR0_INFO__FORMAT_MASK 0x0000007CL 19487#define CB_COLOR0_INFO__NUMBER_TYPE_MASK 0x00000700L 19488#define CB_COLOR0_INFO__COMP_SWAP_MASK 0x00001800L 19489#define CB_COLOR0_INFO__FAST_CLEAR_MASK 0x00002000L 19490#define CB_COLOR0_INFO__COMPRESSION_MASK 0x00004000L 19491#define CB_COLOR0_INFO__BLEND_CLAMP_MASK 0x00008000L 19492#define CB_COLOR0_INFO__BLEND_BYPASS_MASK 0x00010000L 19493#define CB_COLOR0_INFO__SIMPLE_FLOAT_MASK 0x00020000L 19494#define CB_COLOR0_INFO__ROUND_MODE_MASK 0x00040000L 19495#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L 19496#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L 19497#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L 19498#define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L 19499#define CB_COLOR0_INFO__DCC_ENABLE_MASK 0x10000000L 19500#define CB_COLOR0_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L 19501//CB_COLOR0_ATTRIB 19502#define CB_COLOR0_ATTRIB__MIP0_DEPTH__SHIFT 0x0 19503#define CB_COLOR0_ATTRIB__META_LINEAR__SHIFT 0xb 19504#define CB_COLOR0_ATTRIB__NUM_SAMPLES__SHIFT 0xc 19505#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf 19506#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 19507#define CB_COLOR0_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 19508#define CB_COLOR0_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 19509#define CB_COLOR0_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c 19510#define CB_COLOR0_ATTRIB__RB_ALIGNED__SHIFT 0x1e 19511#define CB_COLOR0_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f 19512#define CB_COLOR0_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL 19513#define CB_COLOR0_ATTRIB__META_LINEAR_MASK 0x00000800L 19514#define CB_COLOR0_ATTRIB__NUM_SAMPLES_MASK 0x00007000L 19515#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L 19516#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L 19517#define CB_COLOR0_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L 19518#define CB_COLOR0_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L 19519#define CB_COLOR0_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L 19520#define CB_COLOR0_ATTRIB__RB_ALIGNED_MASK 0x40000000L 19521#define CB_COLOR0_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L 19522//CB_COLOR0_DCC_CONTROL 19523#define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 19524#define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 19525#define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 19526#define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 19527#define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 19528#define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 19529#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 19530#define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa 19531#define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe 19532#define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L 19533#define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L 19534#define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL 19535#define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L 19536#define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L 19537#define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L 19538#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L 19539#define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L 19540#define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L 19541//CB_COLOR0_CMASK 19542#define CB_COLOR0_CMASK__BASE_256B__SHIFT 0x0 19543#define CB_COLOR0_CMASK__BASE_256B_MASK 0xFFFFFFFFL 19544//CB_COLOR0_CMASK_BASE_EXT 19545#define CB_COLOR0_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 19546#define CB_COLOR0_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL 19547//CB_COLOR0_FMASK 19548#define CB_COLOR0_FMASK__BASE_256B__SHIFT 0x0 19549#define CB_COLOR0_FMASK__BASE_256B_MASK 0xFFFFFFFFL 19550//CB_COLOR0_FMASK_BASE_EXT 19551#define CB_COLOR0_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 19552#define CB_COLOR0_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL 19553//CB_COLOR0_CLEAR_WORD0 19554#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 19555#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL 19556//CB_COLOR0_CLEAR_WORD1 19557#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 19558#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL 19559//CB_COLOR0_DCC_BASE 19560#define CB_COLOR0_DCC_BASE__BASE_256B__SHIFT 0x0 19561#define CB_COLOR0_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL 19562//CB_COLOR0_DCC_BASE_EXT 19563#define CB_COLOR0_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 19564#define CB_COLOR0_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL 19565//CB_COLOR1_BASE 19566#define CB_COLOR1_BASE__BASE_256B__SHIFT 0x0 19567#define CB_COLOR1_BASE__BASE_256B_MASK 0xFFFFFFFFL 19568//CB_COLOR1_BASE_EXT 19569#define CB_COLOR1_BASE_EXT__BASE_256B__SHIFT 0x0 19570#define CB_COLOR1_BASE_EXT__BASE_256B_MASK 0x000000FFL 19571//CB_COLOR1_ATTRIB2 19572#define CB_COLOR1_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 19573#define CB_COLOR1_ATTRIB2__MIP0_WIDTH__SHIFT 0xe 19574#define CB_COLOR1_ATTRIB2__MAX_MIP__SHIFT 0x1c 19575#define CB_COLOR1_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL 19576#define CB_COLOR1_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L 19577#define CB_COLOR1_ATTRIB2__MAX_MIP_MASK 0xF0000000L 19578//CB_COLOR1_VIEW 19579#define CB_COLOR1_VIEW__SLICE_START__SHIFT 0x0 19580#define CB_COLOR1_VIEW__SLICE_MAX__SHIFT 0xd 19581#define CB_COLOR1_VIEW__MIP_LEVEL__SHIFT 0x18 19582#define CB_COLOR1_VIEW__SLICE_START_MASK 0x000007FFL 19583#define CB_COLOR1_VIEW__SLICE_MAX_MASK 0x00FFE000L 19584#define CB_COLOR1_VIEW__MIP_LEVEL_MASK 0x0F000000L 19585//CB_COLOR1_INFO 19586#define CB_COLOR1_INFO__ENDIAN__SHIFT 0x0 19587#define CB_COLOR1_INFO__FORMAT__SHIFT 0x2 19588#define CB_COLOR1_INFO__NUMBER_TYPE__SHIFT 0x8 19589#define CB_COLOR1_INFO__COMP_SWAP__SHIFT 0xb 19590#define CB_COLOR1_INFO__FAST_CLEAR__SHIFT 0xd 19591#define CB_COLOR1_INFO__COMPRESSION__SHIFT 0xe 19592#define CB_COLOR1_INFO__BLEND_CLAMP__SHIFT 0xf 19593#define CB_COLOR1_INFO__BLEND_BYPASS__SHIFT 0x10 19594#define CB_COLOR1_INFO__SIMPLE_FLOAT__SHIFT 0x11 19595#define CB_COLOR1_INFO__ROUND_MODE__SHIFT 0x12 19596#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 19597#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 19598#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a 19599#define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b 19600#define CB_COLOR1_INFO__DCC_ENABLE__SHIFT 0x1c 19601#define CB_COLOR1_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d 19602#define CB_COLOR1_INFO__ENDIAN_MASK 0x00000003L 19603#define CB_COLOR1_INFO__FORMAT_MASK 0x0000007CL 19604#define CB_COLOR1_INFO__NUMBER_TYPE_MASK 0x00000700L 19605#define CB_COLOR1_INFO__COMP_SWAP_MASK 0x00001800L 19606#define CB_COLOR1_INFO__FAST_CLEAR_MASK 0x00002000L 19607#define CB_COLOR1_INFO__COMPRESSION_MASK 0x00004000L 19608#define CB_COLOR1_INFO__BLEND_CLAMP_MASK 0x00008000L 19609#define CB_COLOR1_INFO__BLEND_BYPASS_MASK 0x00010000L 19610#define CB_COLOR1_INFO__SIMPLE_FLOAT_MASK 0x00020000L 19611#define CB_COLOR1_INFO__ROUND_MODE_MASK 0x00040000L 19612#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L 19613#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L 19614#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L 19615#define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L 19616#define CB_COLOR1_INFO__DCC_ENABLE_MASK 0x10000000L 19617#define CB_COLOR1_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L 19618//CB_COLOR1_ATTRIB 19619#define CB_COLOR1_ATTRIB__MIP0_DEPTH__SHIFT 0x0 19620#define CB_COLOR1_ATTRIB__META_LINEAR__SHIFT 0xb 19621#define CB_COLOR1_ATTRIB__NUM_SAMPLES__SHIFT 0xc 19622#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf 19623#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 19624#define CB_COLOR1_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 19625#define CB_COLOR1_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 19626#define CB_COLOR1_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c 19627#define CB_COLOR1_ATTRIB__RB_ALIGNED__SHIFT 0x1e 19628#define CB_COLOR1_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f 19629#define CB_COLOR1_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL 19630#define CB_COLOR1_ATTRIB__META_LINEAR_MASK 0x00000800L 19631#define CB_COLOR1_ATTRIB__NUM_SAMPLES_MASK 0x00007000L 19632#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L 19633#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L 19634#define CB_COLOR1_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L 19635#define CB_COLOR1_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L 19636#define CB_COLOR1_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L 19637#define CB_COLOR1_ATTRIB__RB_ALIGNED_MASK 0x40000000L 19638#define CB_COLOR1_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L 19639//CB_COLOR1_DCC_CONTROL 19640#define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 19641#define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 19642#define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 19643#define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 19644#define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 19645#define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 19646#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 19647#define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa 19648#define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe 19649#define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L 19650#define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L 19651#define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL 19652#define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L 19653#define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L 19654#define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L 19655#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L 19656#define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L 19657#define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L 19658//CB_COLOR1_CMASK 19659#define CB_COLOR1_CMASK__BASE_256B__SHIFT 0x0 19660#define CB_COLOR1_CMASK__BASE_256B_MASK 0xFFFFFFFFL 19661//CB_COLOR1_CMASK_BASE_EXT 19662#define CB_COLOR1_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 19663#define CB_COLOR1_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL 19664//CB_COLOR1_FMASK 19665#define CB_COLOR1_FMASK__BASE_256B__SHIFT 0x0 19666#define CB_COLOR1_FMASK__BASE_256B_MASK 0xFFFFFFFFL 19667//CB_COLOR1_FMASK_BASE_EXT 19668#define CB_COLOR1_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 19669#define CB_COLOR1_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL 19670//CB_COLOR1_CLEAR_WORD0 19671#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 19672#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL 19673//CB_COLOR1_CLEAR_WORD1 19674#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 19675#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL 19676//CB_COLOR1_DCC_BASE 19677#define CB_COLOR1_DCC_BASE__BASE_256B__SHIFT 0x0 19678#define CB_COLOR1_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL 19679//CB_COLOR1_DCC_BASE_EXT 19680#define CB_COLOR1_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 19681#define CB_COLOR1_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL 19682//CB_COLOR2_BASE 19683#define CB_COLOR2_BASE__BASE_256B__SHIFT 0x0 19684#define CB_COLOR2_BASE__BASE_256B_MASK 0xFFFFFFFFL 19685//CB_COLOR2_BASE_EXT 19686#define CB_COLOR2_BASE_EXT__BASE_256B__SHIFT 0x0 19687#define CB_COLOR2_BASE_EXT__BASE_256B_MASK 0x000000FFL 19688//CB_COLOR2_ATTRIB2 19689#define CB_COLOR2_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 19690#define CB_COLOR2_ATTRIB2__MIP0_WIDTH__SHIFT 0xe 19691#define CB_COLOR2_ATTRIB2__MAX_MIP__SHIFT 0x1c 19692#define CB_COLOR2_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL 19693#define CB_COLOR2_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L 19694#define CB_COLOR2_ATTRIB2__MAX_MIP_MASK 0xF0000000L 19695//CB_COLOR2_VIEW 19696#define CB_COLOR2_VIEW__SLICE_START__SHIFT 0x0 19697#define CB_COLOR2_VIEW__SLICE_MAX__SHIFT 0xd 19698#define CB_COLOR2_VIEW__MIP_LEVEL__SHIFT 0x18 19699#define CB_COLOR2_VIEW__SLICE_START_MASK 0x000007FFL 19700#define CB_COLOR2_VIEW__SLICE_MAX_MASK 0x00FFE000L 19701#define CB_COLOR2_VIEW__MIP_LEVEL_MASK 0x0F000000L 19702//CB_COLOR2_INFO 19703#define CB_COLOR2_INFO__ENDIAN__SHIFT 0x0 19704#define CB_COLOR2_INFO__FORMAT__SHIFT 0x2 19705#define CB_COLOR2_INFO__NUMBER_TYPE__SHIFT 0x8 19706#define CB_COLOR2_INFO__COMP_SWAP__SHIFT 0xb 19707#define CB_COLOR2_INFO__FAST_CLEAR__SHIFT 0xd 19708#define CB_COLOR2_INFO__COMPRESSION__SHIFT 0xe 19709#define CB_COLOR2_INFO__BLEND_CLAMP__SHIFT 0xf 19710#define CB_COLOR2_INFO__BLEND_BYPASS__SHIFT 0x10 19711#define CB_COLOR2_INFO__SIMPLE_FLOAT__SHIFT 0x11 19712#define CB_COLOR2_INFO__ROUND_MODE__SHIFT 0x12 19713#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 19714#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 19715#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a 19716#define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b 19717#define CB_COLOR2_INFO__DCC_ENABLE__SHIFT 0x1c 19718#define CB_COLOR2_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d 19719#define CB_COLOR2_INFO__ENDIAN_MASK 0x00000003L 19720#define CB_COLOR2_INFO__FORMAT_MASK 0x0000007CL 19721#define CB_COLOR2_INFO__NUMBER_TYPE_MASK 0x00000700L 19722#define CB_COLOR2_INFO__COMP_SWAP_MASK 0x00001800L 19723#define CB_COLOR2_INFO__FAST_CLEAR_MASK 0x00002000L 19724#define CB_COLOR2_INFO__COMPRESSION_MASK 0x00004000L 19725#define CB_COLOR2_INFO__BLEND_CLAMP_MASK 0x00008000L 19726#define CB_COLOR2_INFO__BLEND_BYPASS_MASK 0x00010000L 19727#define CB_COLOR2_INFO__SIMPLE_FLOAT_MASK 0x00020000L 19728#define CB_COLOR2_INFO__ROUND_MODE_MASK 0x00040000L 19729#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L 19730#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L 19731#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L 19732#define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L 19733#define CB_COLOR2_INFO__DCC_ENABLE_MASK 0x10000000L 19734#define CB_COLOR2_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L 19735//CB_COLOR2_ATTRIB 19736#define CB_COLOR2_ATTRIB__MIP0_DEPTH__SHIFT 0x0 19737#define CB_COLOR2_ATTRIB__META_LINEAR__SHIFT 0xb 19738#define CB_COLOR2_ATTRIB__NUM_SAMPLES__SHIFT 0xc 19739#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf 19740#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 19741#define CB_COLOR2_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 19742#define CB_COLOR2_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 19743#define CB_COLOR2_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c 19744#define CB_COLOR2_ATTRIB__RB_ALIGNED__SHIFT 0x1e 19745#define CB_COLOR2_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f 19746#define CB_COLOR2_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL 19747#define CB_COLOR2_ATTRIB__META_LINEAR_MASK 0x00000800L 19748#define CB_COLOR2_ATTRIB__NUM_SAMPLES_MASK 0x00007000L 19749#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L 19750#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L 19751#define CB_COLOR2_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L 19752#define CB_COLOR2_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L 19753#define CB_COLOR2_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L 19754#define CB_COLOR2_ATTRIB__RB_ALIGNED_MASK 0x40000000L 19755#define CB_COLOR2_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L 19756//CB_COLOR2_DCC_CONTROL 19757#define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 19758#define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 19759#define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 19760#define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 19761#define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 19762#define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 19763#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 19764#define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa 19765#define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe 19766#define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L 19767#define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L 19768#define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL 19769#define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L 19770#define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L 19771#define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L 19772#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L 19773#define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L 19774#define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L 19775//CB_COLOR2_CMASK 19776#define CB_COLOR2_CMASK__BASE_256B__SHIFT 0x0 19777#define CB_COLOR2_CMASK__BASE_256B_MASK 0xFFFFFFFFL 19778//CB_COLOR2_CMASK_BASE_EXT 19779#define CB_COLOR2_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 19780#define CB_COLOR2_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL 19781//CB_COLOR2_FMASK 19782#define CB_COLOR2_FMASK__BASE_256B__SHIFT 0x0 19783#define CB_COLOR2_FMASK__BASE_256B_MASK 0xFFFFFFFFL 19784//CB_COLOR2_FMASK_BASE_EXT 19785#define CB_COLOR2_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 19786#define CB_COLOR2_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL 19787//CB_COLOR2_CLEAR_WORD0 19788#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 19789#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL 19790//CB_COLOR2_CLEAR_WORD1 19791#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 19792#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL 19793//CB_COLOR2_DCC_BASE 19794#define CB_COLOR2_DCC_BASE__BASE_256B__SHIFT 0x0 19795#define CB_COLOR2_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL 19796//CB_COLOR2_DCC_BASE_EXT 19797#define CB_COLOR2_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 19798#define CB_COLOR2_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL 19799//CB_COLOR3_BASE 19800#define CB_COLOR3_BASE__BASE_256B__SHIFT 0x0 19801#define CB_COLOR3_BASE__BASE_256B_MASK 0xFFFFFFFFL 19802//CB_COLOR3_BASE_EXT 19803#define CB_COLOR3_BASE_EXT__BASE_256B__SHIFT 0x0 19804#define CB_COLOR3_BASE_EXT__BASE_256B_MASK 0x000000FFL 19805//CB_COLOR3_ATTRIB2 19806#define CB_COLOR3_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 19807#define CB_COLOR3_ATTRIB2__MIP0_WIDTH__SHIFT 0xe 19808#define CB_COLOR3_ATTRIB2__MAX_MIP__SHIFT 0x1c 19809#define CB_COLOR3_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL 19810#define CB_COLOR3_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L 19811#define CB_COLOR3_ATTRIB2__MAX_MIP_MASK 0xF0000000L 19812//CB_COLOR3_VIEW 19813#define CB_COLOR3_VIEW__SLICE_START__SHIFT 0x0 19814#define CB_COLOR3_VIEW__SLICE_MAX__SHIFT 0xd 19815#define CB_COLOR3_VIEW__MIP_LEVEL__SHIFT 0x18 19816#define CB_COLOR3_VIEW__SLICE_START_MASK 0x000007FFL 19817#define CB_COLOR3_VIEW__SLICE_MAX_MASK 0x00FFE000L 19818#define CB_COLOR3_VIEW__MIP_LEVEL_MASK 0x0F000000L 19819//CB_COLOR3_INFO 19820#define CB_COLOR3_INFO__ENDIAN__SHIFT 0x0 19821#define CB_COLOR3_INFO__FORMAT__SHIFT 0x2 19822#define CB_COLOR3_INFO__NUMBER_TYPE__SHIFT 0x8 19823#define CB_COLOR3_INFO__COMP_SWAP__SHIFT 0xb 19824#define CB_COLOR3_INFO__FAST_CLEAR__SHIFT 0xd 19825#define CB_COLOR3_INFO__COMPRESSION__SHIFT 0xe 19826#define CB_COLOR3_INFO__BLEND_CLAMP__SHIFT 0xf 19827#define CB_COLOR3_INFO__BLEND_BYPASS__SHIFT 0x10 19828#define CB_COLOR3_INFO__SIMPLE_FLOAT__SHIFT 0x11 19829#define CB_COLOR3_INFO__ROUND_MODE__SHIFT 0x12 19830#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 19831#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 19832#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a 19833#define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b 19834#define CB_COLOR3_INFO__DCC_ENABLE__SHIFT 0x1c 19835#define CB_COLOR3_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d 19836#define CB_COLOR3_INFO__ENDIAN_MASK 0x00000003L 19837#define CB_COLOR3_INFO__FORMAT_MASK 0x0000007CL 19838#define CB_COLOR3_INFO__NUMBER_TYPE_MASK 0x00000700L 19839#define CB_COLOR3_INFO__COMP_SWAP_MASK 0x00001800L 19840#define CB_COLOR3_INFO__FAST_CLEAR_MASK 0x00002000L 19841#define CB_COLOR3_INFO__COMPRESSION_MASK 0x00004000L 19842#define CB_COLOR3_INFO__BLEND_CLAMP_MASK 0x00008000L 19843#define CB_COLOR3_INFO__BLEND_BYPASS_MASK 0x00010000L 19844#define CB_COLOR3_INFO__SIMPLE_FLOAT_MASK 0x00020000L 19845#define CB_COLOR3_INFO__ROUND_MODE_MASK 0x00040000L 19846#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L 19847#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L 19848#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L 19849#define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L 19850#define CB_COLOR3_INFO__DCC_ENABLE_MASK 0x10000000L 19851#define CB_COLOR3_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L 19852//CB_COLOR3_ATTRIB 19853#define CB_COLOR3_ATTRIB__MIP0_DEPTH__SHIFT 0x0 19854#define CB_COLOR3_ATTRIB__META_LINEAR__SHIFT 0xb 19855#define CB_COLOR3_ATTRIB__NUM_SAMPLES__SHIFT 0xc 19856#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf 19857#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 19858#define CB_COLOR3_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 19859#define CB_COLOR3_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 19860#define CB_COLOR3_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c 19861#define CB_COLOR3_ATTRIB__RB_ALIGNED__SHIFT 0x1e 19862#define CB_COLOR3_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f 19863#define CB_COLOR3_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL 19864#define CB_COLOR3_ATTRIB__META_LINEAR_MASK 0x00000800L 19865#define CB_COLOR3_ATTRIB__NUM_SAMPLES_MASK 0x00007000L 19866#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L 19867#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L 19868#define CB_COLOR3_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L 19869#define CB_COLOR3_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L 19870#define CB_COLOR3_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L 19871#define CB_COLOR3_ATTRIB__RB_ALIGNED_MASK 0x40000000L 19872#define CB_COLOR3_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L 19873//CB_COLOR3_DCC_CONTROL 19874#define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 19875#define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 19876#define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 19877#define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 19878#define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 19879#define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 19880#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 19881#define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa 19882#define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe 19883#define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L 19884#define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L 19885#define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL 19886#define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L 19887#define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L 19888#define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L 19889#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L 19890#define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L 19891#define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L 19892//CB_COLOR3_CMASK 19893#define CB_COLOR3_CMASK__BASE_256B__SHIFT 0x0 19894#define CB_COLOR3_CMASK__BASE_256B_MASK 0xFFFFFFFFL 19895//CB_COLOR3_CMASK_BASE_EXT 19896#define CB_COLOR3_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 19897#define CB_COLOR3_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL 19898//CB_COLOR3_FMASK 19899#define CB_COLOR3_FMASK__BASE_256B__SHIFT 0x0 19900#define CB_COLOR3_FMASK__BASE_256B_MASK 0xFFFFFFFFL 19901//CB_COLOR3_FMASK_BASE_EXT 19902#define CB_COLOR3_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 19903#define CB_COLOR3_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL 19904//CB_COLOR3_CLEAR_WORD0 19905#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 19906#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL 19907//CB_COLOR3_CLEAR_WORD1 19908#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 19909#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL 19910//CB_COLOR3_DCC_BASE 19911#define CB_COLOR3_DCC_BASE__BASE_256B__SHIFT 0x0 19912#define CB_COLOR3_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL 19913//CB_COLOR3_DCC_BASE_EXT 19914#define CB_COLOR3_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 19915#define CB_COLOR3_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL 19916//CB_COLOR4_BASE 19917#define CB_COLOR4_BASE__BASE_256B__SHIFT 0x0 19918#define CB_COLOR4_BASE__BASE_256B_MASK 0xFFFFFFFFL 19919//CB_COLOR4_BASE_EXT 19920#define CB_COLOR4_BASE_EXT__BASE_256B__SHIFT 0x0 19921#define CB_COLOR4_BASE_EXT__BASE_256B_MASK 0x000000FFL 19922//CB_COLOR4_ATTRIB2 19923#define CB_COLOR4_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 19924#define CB_COLOR4_ATTRIB2__MIP0_WIDTH__SHIFT 0xe 19925#define CB_COLOR4_ATTRIB2__MAX_MIP__SHIFT 0x1c 19926#define CB_COLOR4_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL 19927#define CB_COLOR4_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L 19928#define CB_COLOR4_ATTRIB2__MAX_MIP_MASK 0xF0000000L 19929//CB_COLOR4_VIEW 19930#define CB_COLOR4_VIEW__SLICE_START__SHIFT 0x0 19931#define CB_COLOR4_VIEW__SLICE_MAX__SHIFT 0xd 19932#define CB_COLOR4_VIEW__MIP_LEVEL__SHIFT 0x18 19933#define CB_COLOR4_VIEW__SLICE_START_MASK 0x000007FFL 19934#define CB_COLOR4_VIEW__SLICE_MAX_MASK 0x00FFE000L 19935#define CB_COLOR4_VIEW__MIP_LEVEL_MASK 0x0F000000L 19936//CB_COLOR4_INFO 19937#define CB_COLOR4_INFO__ENDIAN__SHIFT 0x0 19938#define CB_COLOR4_INFO__FORMAT__SHIFT 0x2 19939#define CB_COLOR4_INFO__NUMBER_TYPE__SHIFT 0x8 19940#define CB_COLOR4_INFO__COMP_SWAP__SHIFT 0xb 19941#define CB_COLOR4_INFO__FAST_CLEAR__SHIFT 0xd 19942#define CB_COLOR4_INFO__COMPRESSION__SHIFT 0xe 19943#define CB_COLOR4_INFO__BLEND_CLAMP__SHIFT 0xf 19944#define CB_COLOR4_INFO__BLEND_BYPASS__SHIFT 0x10 19945#define CB_COLOR4_INFO__SIMPLE_FLOAT__SHIFT 0x11 19946#define CB_COLOR4_INFO__ROUND_MODE__SHIFT 0x12 19947#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 19948#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 19949#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a 19950#define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b 19951#define CB_COLOR4_INFO__DCC_ENABLE__SHIFT 0x1c 19952#define CB_COLOR4_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d 19953#define CB_COLOR4_INFO__ENDIAN_MASK 0x00000003L 19954#define CB_COLOR4_INFO__FORMAT_MASK 0x0000007CL 19955#define CB_COLOR4_INFO__NUMBER_TYPE_MASK 0x00000700L 19956#define CB_COLOR4_INFO__COMP_SWAP_MASK 0x00001800L 19957#define CB_COLOR4_INFO__FAST_CLEAR_MASK 0x00002000L 19958#define CB_COLOR4_INFO__COMPRESSION_MASK 0x00004000L 19959#define CB_COLOR4_INFO__BLEND_CLAMP_MASK 0x00008000L 19960#define CB_COLOR4_INFO__BLEND_BYPASS_MASK 0x00010000L 19961#define CB_COLOR4_INFO__SIMPLE_FLOAT_MASK 0x00020000L 19962#define CB_COLOR4_INFO__ROUND_MODE_MASK 0x00040000L 19963#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L 19964#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L 19965#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L 19966#define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L 19967#define CB_COLOR4_INFO__DCC_ENABLE_MASK 0x10000000L 19968#define CB_COLOR4_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L 19969//CB_COLOR4_ATTRIB 19970#define CB_COLOR4_ATTRIB__MIP0_DEPTH__SHIFT 0x0 19971#define CB_COLOR4_ATTRIB__META_LINEAR__SHIFT 0xb 19972#define CB_COLOR4_ATTRIB__NUM_SAMPLES__SHIFT 0xc 19973#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf 19974#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 19975#define CB_COLOR4_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 19976#define CB_COLOR4_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 19977#define CB_COLOR4_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c 19978#define CB_COLOR4_ATTRIB__RB_ALIGNED__SHIFT 0x1e 19979#define CB_COLOR4_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f 19980#define CB_COLOR4_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL 19981#define CB_COLOR4_ATTRIB__META_LINEAR_MASK 0x00000800L 19982#define CB_COLOR4_ATTRIB__NUM_SAMPLES_MASK 0x00007000L 19983#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L 19984#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L 19985#define CB_COLOR4_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L 19986#define CB_COLOR4_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L 19987#define CB_COLOR4_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L 19988#define CB_COLOR4_ATTRIB__RB_ALIGNED_MASK 0x40000000L 19989#define CB_COLOR4_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L 19990//CB_COLOR4_DCC_CONTROL 19991#define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 19992#define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 19993#define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 19994#define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 19995#define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 19996#define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 19997#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 19998#define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa 19999#define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe 20000#define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L
20001#define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L 20002#define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL 20003#define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L 20004#define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L 20005#define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L 20006#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L 20007#define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L 20008#define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L 20009//CB_COLOR4_CMASK 20010#define CB_COLOR4_CMASK__BASE_256B__SHIFT 0x0 20011#define CB_COLOR4_CMASK__BASE_256B_MASK 0xFFFFFFFFL 20012//CB_COLOR4_CMASK_BASE_EXT 20013#define CB_COLOR4_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 20014#define CB_COLOR4_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL 20015//CB_COLOR4_FMASK 20016#define CB_COLOR4_FMASK__BASE_256B__SHIFT 0x0 20017#define CB_COLOR4_FMASK__BASE_256B_MASK 0xFFFFFFFFL 20018//CB_COLOR4_FMASK_BASE_EXT 20019#define CB_COLOR4_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 20020#define CB_COLOR4_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL 20021//CB_COLOR4_CLEAR_WORD0 20022#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 20023#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL 20024//CB_COLOR4_CLEAR_WORD1 20025#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 20026#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL 20027//CB_COLOR4_DCC_BASE 20028#define CB_COLOR4_DCC_BASE__BASE_256B__SHIFT 0x0 20029#define CB_COLOR4_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL 20030//CB_COLOR4_DCC_BASE_EXT 20031#define CB_COLOR4_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 20032#define CB_COLOR4_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL 20033//CB_COLOR5_BASE 20034#define CB_COLOR5_BASE__BASE_256B__SHIFT 0x0 20035#define CB_COLOR5_BASE__BASE_256B_MASK 0xFFFFFFFFL 20036//CB_COLOR5_BASE_EXT 20037#define CB_COLOR5_BASE_EXT__BASE_256B__SHIFT 0x0 20038#define CB_COLOR5_BASE_EXT__BASE_256B_MASK 0x000000FFL 20039//CB_COLOR5_ATTRIB2 20040#define CB_COLOR5_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 20041#define CB_COLOR5_ATTRIB2__MIP0_WIDTH__SHIFT 0xe 20042#define CB_COLOR5_ATTRIB2__MAX_MIP__SHIFT 0x1c 20043#define CB_COLOR5_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL 20044#define CB_COLOR5_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L 20045#define CB_COLOR5_ATTRIB2__MAX_MIP_MASK 0xF0000000L 20046//CB_COLOR5_VIEW 20047#define CB_COLOR5_VIEW__SLICE_START__SHIFT 0x0 20048#define CB_COLOR5_VIEW__SLICE_MAX__SHIFT 0xd 20049#define CB_COLOR5_VIEW__MIP_LEVEL__SHIFT 0x18 20050#define CB_COLOR5_VIEW__SLICE_START_MASK 0x000007FFL 20051#define CB_COLOR5_VIEW__SLICE_MAX_MASK 0x00FFE000L 20052#define CB_COLOR5_VIEW__MIP_LEVEL_MASK 0x0F000000L 20053//CB_COLOR5_INFO 20054#define CB_COLOR5_INFO__ENDIAN__SHIFT 0x0 20055#define CB_COLOR5_INFO__FORMAT__SHIFT 0x2 20056#define CB_COLOR5_INFO__NUMBER_TYPE__SHIFT 0x8 20057#define CB_COLOR5_INFO__COMP_SWAP__SHIFT 0xb 20058#define CB_COLOR5_INFO__FAST_CLEAR__SHIFT 0xd 20059#define CB_COLOR5_INFO__COMPRESSION__SHIFT 0xe 20060#define CB_COLOR5_INFO__BLEND_CLAMP__SHIFT 0xf 20061#define CB_COLOR5_INFO__BLEND_BYPASS__SHIFT 0x10 20062#define CB_COLOR5_INFO__SIMPLE_FLOAT__SHIFT 0x11 20063#define CB_COLOR5_INFO__ROUND_MODE__SHIFT 0x12 20064#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 20065#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 20066#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a 20067#define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b 20068#define CB_COLOR5_INFO__DCC_ENABLE__SHIFT 0x1c 20069#define CB_COLOR5_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d 20070#define CB_COLOR5_INFO__ENDIAN_MASK 0x00000003L 20071#define CB_COLOR5_INFO__FORMAT_MASK 0x0000007CL 20072#define CB_COLOR5_INFO__NUMBER_TYPE_MASK 0x00000700L 20073#define CB_COLOR5_INFO__COMP_SWAP_MASK 0x00001800L 20074#define CB_COLOR5_INFO__FAST_CLEAR_MASK 0x00002000L 20075#define CB_COLOR5_INFO__COMPRESSION_MASK 0x00004000L 20076#define CB_COLOR5_INFO__BLEND_CLAMP_MASK 0x00008000L 20077#define CB_COLOR5_INFO__BLEND_BYPASS_MASK 0x00010000L 20078#define CB_COLOR5_INFO__SIMPLE_FLOAT_MASK 0x00020000L 20079#define CB_COLOR5_INFO__ROUND_MODE_MASK 0x00040000L 20080#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L 20081#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L 20082#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L 20083#define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L 20084#define CB_COLOR5_INFO__DCC_ENABLE_MASK 0x10000000L 20085#define CB_COLOR5_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L 20086//CB_COLOR5_ATTRIB 20087#define CB_COLOR5_ATTRIB__MIP0_DEPTH__SHIFT 0x0 20088#define CB_COLOR5_ATTRIB__META_LINEAR__SHIFT 0xb 20089#define CB_COLOR5_ATTRIB__NUM_SAMPLES__SHIFT 0xc 20090#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf 20091#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 20092#define CB_COLOR5_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 20093#define CB_COLOR5_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 20094#define CB_COLOR5_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c 20095#define CB_COLOR5_ATTRIB__RB_ALIGNED__SHIFT 0x1e 20096#define CB_COLOR5_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f 20097#define CB_COLOR5_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL 20098#define CB_COLOR5_ATTRIB__META_LINEAR_MASK 0x00000800L 20099#define CB_COLOR5_ATTRIB__NUM_SAMPLES_MASK 0x00007000L 20100#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L 20101#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L 20102#define CB_COLOR5_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L 20103#define CB_COLOR5_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L 20104#define CB_COLOR5_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L 20105#define CB_COLOR5_ATTRIB__RB_ALIGNED_MASK 0x40000000L 20106#define CB_COLOR5_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L 20107//CB_COLOR5_DCC_CONTROL 20108#define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 20109#define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 20110#define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 20111#define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 20112#define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 20113#define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 20114#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 20115#define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa 20116#define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe 20117#define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L 20118#define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L 20119#define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL 20120#define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L 20121#define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L 20122#define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L 20123#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L 20124#define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L 20125#define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L 20126//CB_COLOR5_CMASK 20127#define CB_COLOR5_CMASK__BASE_256B__SHIFT 0x0 20128#define CB_COLOR5_CMASK__BASE_256B_MASK 0xFFFFFFFFL 20129//CB_COLOR5_CMASK_BASE_EXT 20130#define CB_COLOR5_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 20131#define CB_COLOR5_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL 20132//CB_COLOR5_FMASK 20133#define CB_COLOR5_FMASK__BASE_256B__SHIFT 0x0 20134#define CB_COLOR5_FMASK__BASE_256B_MASK 0xFFFFFFFFL 20135//CB_COLOR5_FMASK_BASE_EXT 20136#define CB_COLOR5_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 20137#define CB_COLOR5_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL 20138//CB_COLOR5_CLEAR_WORD0 20139#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 20140#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL 20141//CB_COLOR5_CLEAR_WORD1 20142#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 20143#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL 20144//CB_COLOR5_DCC_BASE 20145#define CB_COLOR5_DCC_BASE__BASE_256B__SHIFT 0x0 20146#define CB_COLOR5_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL 20147//CB_COLOR5_DCC_BASE_EXT 20148#define CB_COLOR5_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 20149#define CB_COLOR5_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL 20150//CB_COLOR6_BASE 20151#define CB_COLOR6_BASE__BASE_256B__SHIFT 0x0 20152#define CB_COLOR6_BASE__BASE_256B_MASK 0xFFFFFFFFL 20153//CB_COLOR6_BASE_EXT 20154#define CB_COLOR6_BASE_EXT__BASE_256B__SHIFT 0x0 20155#define CB_COLOR6_BASE_EXT__BASE_256B_MASK 0x000000FFL 20156//CB_COLOR6_ATTRIB2 20157#define CB_COLOR6_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 20158#define CB_COLOR6_ATTRIB2__MIP0_WIDTH__SHIFT 0xe 20159#define CB_COLOR6_ATTRIB2__MAX_MIP__SHIFT 0x1c 20160#define CB_COLOR6_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL 20161#define CB_COLOR6_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L 20162#define CB_COLOR6_ATTRIB2__MAX_MIP_MASK 0xF0000000L 20163//CB_COLOR6_VIEW 20164#define CB_COLOR6_VIEW__SLICE_START__SHIFT 0x0 20165#define CB_COLOR6_VIEW__SLICE_MAX__SHIFT 0xd 20166#define CB_COLOR6_VIEW__MIP_LEVEL__SHIFT 0x18 20167#define CB_COLOR6_VIEW__SLICE_START_MASK 0x000007FFL 20168#define CB_COLOR6_VIEW__SLICE_MAX_MASK 0x00FFE000L 20169#define CB_COLOR6_VIEW__MIP_LEVEL_MASK 0x0F000000L 20170//CB_COLOR6_INFO 20171#define CB_COLOR6_INFO__ENDIAN__SHIFT 0x0 20172#define CB_COLOR6_INFO__FORMAT__SHIFT 0x2 20173#define CB_COLOR6_INFO__NUMBER_TYPE__SHIFT 0x8 20174#define CB_COLOR6_INFO__COMP_SWAP__SHIFT 0xb 20175#define CB_COLOR6_INFO__FAST_CLEAR__SHIFT 0xd 20176#define CB_COLOR6_INFO__COMPRESSION__SHIFT 0xe 20177#define CB_COLOR6_INFO__BLEND_CLAMP__SHIFT 0xf 20178#define CB_COLOR6_INFO__BLEND_BYPASS__SHIFT 0x10 20179#define CB_COLOR6_INFO__SIMPLE_FLOAT__SHIFT 0x11 20180#define CB_COLOR6_INFO__ROUND_MODE__SHIFT 0x12 20181#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 20182#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 20183#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a 20184#define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b 20185#define CB_COLOR6_INFO__DCC_ENABLE__SHIFT 0x1c 20186#define CB_COLOR6_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d 20187#define CB_COLOR6_INFO__ENDIAN_MASK 0x00000003L 20188#define CB_COLOR6_INFO__FORMAT_MASK 0x0000007CL 20189#define CB_COLOR6_INFO__NUMBER_TYPE_MASK 0x00000700L 20190#define CB_COLOR6_INFO__COMP_SWAP_MASK 0x00001800L 20191#define CB_COLOR6_INFO__FAST_CLEAR_MASK 0x00002000L 20192#define CB_COLOR6_INFO__COMPRESSION_MASK 0x00004000L 20193#define CB_COLOR6_INFO__BLEND_CLAMP_MASK 0x00008000L 20194#define CB_COLOR6_INFO__BLEND_BYPASS_MASK 0x00010000L 20195#define CB_COLOR6_INFO__SIMPLE_FLOAT_MASK 0x00020000L 20196#define CB_COLOR6_INFO__ROUND_MODE_MASK 0x00040000L 20197#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L 20198#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L 20199#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L 20200#define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L 20201#define CB_COLOR6_INFO__DCC_ENABLE_MASK 0x10000000L 20202#define CB_COLOR6_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L 20203//CB_COLOR6_ATTRIB 20204#define CB_COLOR6_ATTRIB__MIP0_DEPTH__SHIFT 0x0 20205#define CB_COLOR6_ATTRIB__META_LINEAR__SHIFT 0xb 20206#define CB_COLOR6_ATTRIB__NUM_SAMPLES__SHIFT 0xc 20207#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf 20208#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 20209#define CB_COLOR6_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 20210#define CB_COLOR6_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 20211#define CB_COLOR6_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c 20212#define CB_COLOR6_ATTRIB__RB_ALIGNED__SHIFT 0x1e 20213#define CB_COLOR6_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f 20214#define CB_COLOR6_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL 20215#define CB_COLOR6_ATTRIB__META_LINEAR_MASK 0x00000800L 20216#define CB_COLOR6_ATTRIB__NUM_SAMPLES_MASK 0x00007000L 20217#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L 20218#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L 20219#define CB_COLOR6_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L 20220#define CB_COLOR6_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L 20221#define CB_COLOR6_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L 20222#define CB_COLOR6_ATTRIB__RB_ALIGNED_MASK 0x40000000L 20223#define CB_COLOR6_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L 20224//CB_COLOR6_DCC_CONTROL 20225#define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 20226#define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 20227#define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 20228#define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 20229#define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 20230#define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 20231#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 20232#define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa 20233#define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe 20234#define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L 20235#define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L 20236#define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL 20237#define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L 20238#define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L 20239#define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L 20240#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L 20241#define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L 20242#define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L 20243//CB_COLOR6_CMASK 20244#define CB_COLOR6_CMASK__BASE_256B__SHIFT 0x0 20245#define CB_COLOR6_CMASK__BASE_256B_MASK 0xFFFFFFFFL 20246//CB_COLOR6_CMASK_BASE_EXT 20247#define CB_COLOR6_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 20248#define CB_COLOR6_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL 20249//CB_COLOR6_FMASK 20250#define CB_COLOR6_FMASK__BASE_256B__SHIFT 0x0 20251#define CB_COLOR6_FMASK__BASE_256B_MASK 0xFFFFFFFFL 20252//CB_COLOR6_FMASK_BASE_EXT 20253#define CB_COLOR6_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 20254#define CB_COLOR6_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL 20255//CB_COLOR6_CLEAR_WORD0 20256#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 20257#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL 20258//CB_COLOR6_CLEAR_WORD1 20259#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 20260#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL 20261//CB_COLOR6_DCC_BASE 20262#define CB_COLOR6_DCC_BASE__BASE_256B__SHIFT 0x0 20263#define CB_COLOR6_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL 20264//CB_COLOR6_DCC_BASE_EXT 20265#define CB_COLOR6_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 20266#define CB_COLOR6_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL 20267//CB_COLOR7_BASE 20268#define CB_COLOR7_BASE__BASE_256B__SHIFT 0x0 20269#define CB_COLOR7_BASE__BASE_256B_MASK 0xFFFFFFFFL 20270//CB_COLOR7_BASE_EXT 20271#define CB_COLOR7_BASE_EXT__BASE_256B__SHIFT 0x0 20272#define CB_COLOR7_BASE_EXT__BASE_256B_MASK 0x000000FFL 20273//CB_COLOR7_ATTRIB2 20274#define CB_COLOR7_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 20275#define CB_COLOR7_ATTRIB2__MIP0_WIDTH__SHIFT 0xe 20276#define CB_COLOR7_ATTRIB2__MAX_MIP__SHIFT 0x1c 20277#define CB_COLOR7_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL 20278#define CB_COLOR7_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L 20279#define CB_COLOR7_ATTRIB2__MAX_MIP_MASK 0xF0000000L 20280//CB_COLOR7_VIEW 20281#define CB_COLOR7_VIEW__SLICE_START__SHIFT 0x0 20282#define CB_COLOR7_VIEW__SLICE_MAX__SHIFT 0xd 20283#define CB_COLOR7_VIEW__MIP_LEVEL__SHIFT 0x18 20284#define CB_COLOR7_VIEW__SLICE_START_MASK 0x000007FFL 20285#define CB_COLOR7_VIEW__SLICE_MAX_MASK 0x00FFE000L 20286#define CB_COLOR7_VIEW__MIP_LEVEL_MASK 0x0F000000L 20287//CB_COLOR7_INFO 20288#define CB_COLOR7_INFO__ENDIAN__SHIFT 0x0 20289#define CB_COLOR7_INFO__FORMAT__SHIFT 0x2 20290#define CB_COLOR7_INFO__NUMBER_TYPE__SHIFT 0x8 20291#define CB_COLOR7_INFO__COMP_SWAP__SHIFT 0xb 20292#define CB_COLOR7_INFO__FAST_CLEAR__SHIFT 0xd 20293#define CB_COLOR7_INFO__COMPRESSION__SHIFT 0xe 20294#define CB_COLOR7_INFO__BLEND_CLAMP__SHIFT 0xf 20295#define CB_COLOR7_INFO__BLEND_BYPASS__SHIFT 0x10 20296#define CB_COLOR7_INFO__SIMPLE_FLOAT__SHIFT 0x11 20297#define CB_COLOR7_INFO__ROUND_MODE__SHIFT 0x12 20298#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 20299#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 20300#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a 20301#define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b 20302#define CB_COLOR7_INFO__DCC_ENABLE__SHIFT 0x1c 20303#define CB_COLOR7_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d 20304#define CB_COLOR7_INFO__ENDIAN_MASK 0x00000003L 20305#define CB_COLOR7_INFO__FORMAT_MASK 0x0000007CL 20306#define CB_COLOR7_INFO__NUMBER_TYPE_MASK 0x00000700L 20307#define CB_COLOR7_INFO__COMP_SWAP_MASK 0x00001800L 20308#define CB_COLOR7_INFO__FAST_CLEAR_MASK 0x00002000L 20309#define CB_COLOR7_INFO__COMPRESSION_MASK 0x00004000L 20310#define CB_COLOR7_INFO__BLEND_CLAMP_MASK 0x00008000L 20311#define CB_COLOR7_INFO__BLEND_BYPASS_MASK 0x00010000L 20312#define CB_COLOR7_INFO__SIMPLE_FLOAT_MASK 0x00020000L 20313#define CB_COLOR7_INFO__ROUND_MODE_MASK 0x00040000L 20314#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L 20315#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L 20316#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x04000000L 20317#define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x08000000L 20318#define CB_COLOR7_INFO__DCC_ENABLE_MASK 0x10000000L 20319#define CB_COLOR7_INFO__CMASK_ADDR_TYPE_MASK 0x60000000L 20320//CB_COLOR7_ATTRIB 20321#define CB_COLOR7_ATTRIB__MIP0_DEPTH__SHIFT 0x0 20322#define CB_COLOR7_ATTRIB__META_LINEAR__SHIFT 0xb 20323#define CB_COLOR7_ATTRIB__NUM_SAMPLES__SHIFT 0xc 20324#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf 20325#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 20326#define CB_COLOR7_ATTRIB__COLOR_SW_MODE__SHIFT 0x12 20327#define CB_COLOR7_ATTRIB__FMASK_SW_MODE__SHIFT 0x17 20328#define CB_COLOR7_ATTRIB__RESOURCE_TYPE__SHIFT 0x1c 20329#define CB_COLOR7_ATTRIB__RB_ALIGNED__SHIFT 0x1e 20330#define CB_COLOR7_ATTRIB__PIPE_ALIGNED__SHIFT 0x1f 20331#define CB_COLOR7_ATTRIB__MIP0_DEPTH_MASK 0x000007FFL 20332#define CB_COLOR7_ATTRIB__META_LINEAR_MASK 0x00000800L 20333#define CB_COLOR7_ATTRIB__NUM_SAMPLES_MASK 0x00007000L 20334#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS_MASK 0x00018000L 20335#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00020000L 20336#define CB_COLOR7_ATTRIB__COLOR_SW_MODE_MASK 0x007C0000L 20337#define CB_COLOR7_ATTRIB__FMASK_SW_MODE_MASK 0x0F800000L 20338#define CB_COLOR7_ATTRIB__RESOURCE_TYPE_MASK 0x30000000L 20339#define CB_COLOR7_ATTRIB__RB_ALIGNED_MASK 0x40000000L 20340#define CB_COLOR7_ATTRIB__PIPE_ALIGNED_MASK 0x80000000L 20341//CB_COLOR7_DCC_CONTROL 20342#define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 20343#define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 20344#define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 20345#define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 20346#define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 20347#define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 20348#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 20349#define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa 20350#define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe 20351#define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x00000001L 20352#define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x00000002L 20353#define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL 20354#define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L 20355#define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L 20356#define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L 20357#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L 20358#define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x00003C00L 20359#define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x0003C000L 20360//CB_COLOR7_CMASK 20361#define CB_COLOR7_CMASK__BASE_256B__SHIFT 0x0 20362#define CB_COLOR7_CMASK__BASE_256B_MASK 0xFFFFFFFFL 20363//CB_COLOR7_CMASK_BASE_EXT 20364#define CB_COLOR7_CMASK_BASE_EXT__BASE_256B__SHIFT 0x0 20365#define CB_COLOR7_CMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL 20366//CB_COLOR7_FMASK 20367#define CB_COLOR7_FMASK__BASE_256B__SHIFT 0x0 20368#define CB_COLOR7_FMASK__BASE_256B_MASK 0xFFFFFFFFL 20369//CB_COLOR7_FMASK_BASE_EXT 20370#define CB_COLOR7_FMASK_BASE_EXT__BASE_256B__SHIFT 0x0 20371#define CB_COLOR7_FMASK_BASE_EXT__BASE_256B_MASK 0x000000FFL 20372//CB_COLOR7_CLEAR_WORD0 20373#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 20374#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0_MASK 0xFFFFFFFFL 20375//CB_COLOR7_CLEAR_WORD1 20376#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 20377#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1_MASK 0xFFFFFFFFL 20378//CB_COLOR7_DCC_BASE 20379#define CB_COLOR7_DCC_BASE__BASE_256B__SHIFT 0x0 20380#define CB_COLOR7_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL 20381//CB_COLOR7_DCC_BASE_EXT 20382#define CB_COLOR7_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 20383#define CB_COLOR7_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL 20384 20385 20386// addressBlock: gc_gfxudec 20387//CP_EOP_DONE_ADDR_LO 20388#define CP_EOP_DONE_ADDR_LO__ADDR_LO__SHIFT 0x2 20389#define CP_EOP_DONE_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFCL 20390//CP_EOP_DONE_ADDR_HI 20391#define CP_EOP_DONE_ADDR_HI__ADDR_HI__SHIFT 0x0 20392#define CP_EOP_DONE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL 20393//CP_EOP_DONE_DATA_LO 20394#define CP_EOP_DONE_DATA_LO__DATA_LO__SHIFT 0x0 20395#define CP_EOP_DONE_DATA_LO__DATA_LO_MASK 0xFFFFFFFFL 20396//CP_EOP_DONE_DATA_HI 20397#define CP_EOP_DONE_DATA_HI__DATA_HI__SHIFT 0x0 20398#define CP_EOP_DONE_DATA_HI__DATA_HI_MASK 0xFFFFFFFFL 20399//CP_EOP_LAST_FENCE_LO 20400#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO__SHIFT 0x0 20401#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO_MASK 0xFFFFFFFFL 20402//CP_EOP_LAST_FENCE_HI 20403#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI__SHIFT 0x0 20404#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI_MASK 0xFFFFFFFFL 20405//CP_STREAM_OUT_ADDR_LO 20406#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO__SHIFT 0x2 20407#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO_MASK 0xFFFFFFFCL 20408//CP_STREAM_OUT_ADDR_HI 20409#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI__SHIFT 0x0 20410#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI_MASK 0x0000FFFFL 20411//CP_NUM_PRIM_WRITTEN_COUNT0_LO 20412#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO__SHIFT 0x0 20413#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO_MASK 0xFFFFFFFFL 20414//CP_NUM_PRIM_WRITTEN_COUNT0_HI 20415#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI__SHIFT 0x0 20416#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI_MASK 0xFFFFFFFFL 20417//CP_NUM_PRIM_NEEDED_COUNT0_LO 20418#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO__SHIFT 0x0 20419#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO_MASK 0xFFFFFFFFL 20420//CP_NUM_PRIM_NEEDED_COUNT0_HI 20421#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI__SHIFT 0x0 20422#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI_MASK 0xFFFFFFFFL 20423//CP_NUM_PRIM_WRITTEN_COUNT1_LO 20424#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO__SHIFT 0x0 20425#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO_MASK 0xFFFFFFFFL 20426//CP_NUM_PRIM_WRITTEN_COUNT1_HI 20427#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI__SHIFT 0x0 20428#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI_MASK 0xFFFFFFFFL 20429//CP_NUM_PRIM_NEEDED_COUNT1_LO 20430#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO__SHIFT 0x0 20431#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO_MASK 0xFFFFFFFFL 20432//CP_NUM_PRIM_NEEDED_COUNT1_HI 20433#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI__SHIFT 0x0 20434#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI_MASK 0xFFFFFFFFL 20435//CP_NUM_PRIM_WRITTEN_COUNT2_LO 20436#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO__SHIFT 0x0 20437#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO_MASK 0xFFFFFFFFL 20438//CP_NUM_PRIM_WRITTEN_COUNT2_HI 20439#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI__SHIFT 0x0 20440#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI_MASK 0xFFFFFFFFL 20441//CP_NUM_PRIM_NEEDED_COUNT2_LO 20442#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO__SHIFT 0x0 20443#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO_MASK 0xFFFFFFFFL 20444//CP_NUM_PRIM_NEEDED_COUNT2_HI 20445#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI__SHIFT 0x0 20446#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI_MASK 0xFFFFFFFFL 20447//CP_NUM_PRIM_WRITTEN_COUNT3_LO 20448#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO__SHIFT 0x0 20449#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO_MASK 0xFFFFFFFFL 20450//CP_NUM_PRIM_WRITTEN_COUNT3_HI 20451#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI__SHIFT 0x0 20452#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI_MASK 0xFFFFFFFFL 20453//CP_NUM_PRIM_NEEDED_COUNT3_LO 20454#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO__SHIFT 0x0 20455#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO_MASK 0xFFFFFFFFL 20456//CP_NUM_PRIM_NEEDED_COUNT3_HI 20457#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI__SHIFT 0x0 20458#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI_MASK 0xFFFFFFFFL 20459//CP_PIPE_STATS_ADDR_LO 20460#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO__SHIFT 0x2 20461#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO_MASK 0xFFFFFFFCL 20462//CP_PIPE_STATS_ADDR_HI 20463#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI__SHIFT 0x0 20464#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI_MASK 0x0000FFFFL 20465//CP_VGT_IAVERT_COUNT_LO 20466#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO__SHIFT 0x0 20467#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO_MASK 0xFFFFFFFFL 20468//CP_VGT_IAVERT_COUNT_HI 20469#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI__SHIFT 0x0 20470#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI_MASK 0xFFFFFFFFL 20471//CP_VGT_IAPRIM_COUNT_LO 20472#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO__SHIFT 0x0 20473#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO_MASK 0xFFFFFFFFL 20474//CP_VGT_IAPRIM_COUNT_HI 20475#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI__SHIFT 0x0 20476#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI_MASK 0xFFFFFFFFL 20477//CP_VGT_GSPRIM_COUNT_LO 20478#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO__SHIFT 0x0 20479#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO_MASK 0xFFFFFFFFL 20480//CP_VGT_GSPRIM_COUNT_HI 20481#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI__SHIFT 0x0 20482#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI_MASK 0xFFFFFFFFL 20483//CP_VGT_VSINVOC_COUNT_LO 20484#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO__SHIFT 0x0 20485#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO_MASK 0xFFFFFFFFL 20486//CP_VGT_VSINVOC_COUNT_HI 20487#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI__SHIFT 0x0 20488#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI_MASK 0xFFFFFFFFL 20489//CP_VGT_GSINVOC_COUNT_LO 20490#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO__SHIFT 0x0 20491#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO_MASK 0xFFFFFFFFL 20492//CP_VGT_GSINVOC_COUNT_HI 20493#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI__SHIFT 0x0 20494#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI_MASK 0xFFFFFFFFL 20495//CP_VGT_HSINVOC_COUNT_LO 20496#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO__SHIFT 0x0 20497#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO_MASK 0xFFFFFFFFL 20498//CP_VGT_HSINVOC_COUNT_HI 20499#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI__SHIFT 0x0 20500#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI_MASK 0xFFFFFFFFL 20501//CP_VGT_DSINVOC_COUNT_LO 20502#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO__SHIFT 0x0 20503#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO_MASK 0xFFFFFFFFL 20504//CP_VGT_DSINVOC_COUNT_HI 20505#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI__SHIFT 0x0 20506#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI_MASK 0xFFFFFFFFL 20507//CP_PA_CINVOC_COUNT_LO 20508#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO__SHIFT 0x0 20509#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO_MASK 0xFFFFFFFFL 20510//CP_PA_CINVOC_COUNT_HI 20511#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI__SHIFT 0x0 20512#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI_MASK 0xFFFFFFFFL 20513//CP_PA_CPRIM_COUNT_LO 20514#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO__SHIFT 0x0 20515#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO_MASK 0xFFFFFFFFL 20516//CP_PA_CPRIM_COUNT_HI 20517#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI__SHIFT 0x0 20518#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI_MASK 0xFFFFFFFFL 20519//CP_SC_PSINVOC_COUNT0_LO 20520#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO__SHIFT 0x0 20521#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO_MASK 0xFFFFFFFFL 20522//CP_SC_PSINVOC_COUNT0_HI 20523#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT 0x0 20524#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI_MASK 0xFFFFFFFFL 20525//CP_SC_PSINVOC_COUNT1_LO 20526#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE__SHIFT 0x0 20527#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE_MASK 0xFFFFFFFFL 20528//CP_SC_PSINVOC_COUNT1_HI 20529#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE__SHIFT 0x0 20530#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE_MASK 0xFFFFFFFFL 20531//CP_VGT_CSINVOC_COUNT_LO 20532#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO__SHIFT 0x0 20533#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO_MASK 0xFFFFFFFFL 20534//CP_VGT_CSINVOC_COUNT_HI 20535#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI__SHIFT 0x0 20536#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI_MASK 0xFFFFFFFFL 20537//CP_PIPE_STATS_CONTROL 20538#define CP_PIPE_STATS_CONTROL__CACHE_POLICY__SHIFT 0x19 20539#define CP_PIPE_STATS_CONTROL__CACHE_POLICY_MASK 0x02000000L 20540//CP_STREAM_OUT_CONTROL 20541#define CP_STREAM_OUT_CONTROL__CACHE_POLICY__SHIFT 0x19 20542#define CP_STREAM_OUT_CONTROL__CACHE_POLICY_MASK 0x02000000L 20543//CP_STRMOUT_CNTL 20544#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE__SHIFT 0x0 20545#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE_MASK 0x00000001L 20546//SCRATCH_REG0 20547#define SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0 20548#define SCRATCH_REG0__SCRATCH_REG0_MASK 0xFFFFFFFFL 20549//SCRATCH_REG1 20550#define SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0 20551#define SCRATCH_REG1__SCRATCH_REG1_MASK 0xFFFFFFFFL 20552//SCRATCH_REG2 20553#define SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0 20554#define SCRATCH_REG2__SCRATCH_REG2_MASK 0xFFFFFFFFL 20555//SCRATCH_REG3 20556#define SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0 20557#define SCRATCH_REG3__SCRATCH_REG3_MASK 0xFFFFFFFFL 20558//SCRATCH_REG4 20559#define SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0 20560#define SCRATCH_REG4__SCRATCH_REG4_MASK 0xFFFFFFFFL 20561//SCRATCH_REG5 20562#define SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0 20563#define SCRATCH_REG5__SCRATCH_REG5_MASK 0xFFFFFFFFL 20564//SCRATCH_REG6 20565#define SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0 20566#define SCRATCH_REG6__SCRATCH_REG6_MASK 0xFFFFFFFFL 20567//SCRATCH_REG7 20568#define SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0 20569#define SCRATCH_REG7__SCRATCH_REG7_MASK 0xFFFFFFFFL 20570//CP_APPEND_DATA_HI 20571#define CP_APPEND_DATA_HI__DATA__SHIFT 0x0 20572#define CP_APPEND_DATA_HI__DATA_MASK 0xFFFFFFFFL 20573//CP_APPEND_LAST_CS_FENCE_HI 20574#define CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE__SHIFT 0x0 20575#define CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE_MASK 0xFFFFFFFFL 20576//CP_APPEND_LAST_PS_FENCE_HI 20577#define CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE__SHIFT 0x0 20578#define CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE_MASK 0xFFFFFFFFL 20579//SCRATCH_UMSK 20580#define SCRATCH_UMSK__OBSOLETE_UMSK__SHIFT 0x0 20581#define SCRATCH_UMSK__OBSOLETE_SWAP__SHIFT 0x10 20582#define SCRATCH_UMSK__OBSOLETE_UMSK_MASK 0x000000FFL 20583#define SCRATCH_UMSK__OBSOLETE_SWAP_MASK 0x00030000L 20584//SCRATCH_ADDR 20585#define SCRATCH_ADDR__OBSOLETE_ADDR__SHIFT 0x0 20586#define SCRATCH_ADDR__OBSOLETE_ADDR_MASK 0xFFFFFFFFL 20587//CP_PFP_ATOMIC_PREOP_LO 20588#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 20589#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL 20590//CP_PFP_ATOMIC_PREOP_HI 20591#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 20592#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL 20593//CP_PFP_GDS_ATOMIC0_PREOP_LO 20594#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0 20595#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL 20596//CP_PFP_GDS_ATOMIC0_PREOP_HI 20597#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0 20598#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL 20599//CP_PFP_GDS_ATOMIC1_PREOP_LO 20600#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0 20601#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL 20602//CP_PFP_GDS_ATOMIC1_PREOP_HI 20603#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0 20604#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL 20605//CP_APPEND_ADDR_LO 20606#define CP_APPEND_ADDR_LO__MEM_ADDR_LO__SHIFT 0x2 20607#define CP_APPEND_ADDR_LO__MEM_ADDR_LO_MASK 0xFFFFFFFCL 20608//CP_APPEND_ADDR_HI 20609#define CP_APPEND_ADDR_HI__MEM_ADDR_HI__SHIFT 0x0 20610#define CP_APPEND_ADDR_HI__CS_PS_SEL__SHIFT 0x10 20611#define CP_APPEND_ADDR_HI__CACHE_POLICY__SHIFT 0x19 20612#define CP_APPEND_ADDR_HI__COMMAND__SHIFT 0x1d 20613#define CP_APPEND_ADDR_HI__MEM_ADDR_HI_MASK 0x0000FFFFL 20614#define CP_APPEND_ADDR_HI__CS_PS_SEL_MASK 0x00010000L 20615#define CP_APPEND_ADDR_HI__CACHE_POLICY_MASK 0x02000000L 20616#define CP_APPEND_ADDR_HI__COMMAND_MASK 0xE0000000L 20617//CP_APPEND_DATA_LO 20618#define CP_APPEND_DATA_LO__DATA__SHIFT 0x0 20619#define CP_APPEND_DATA_LO__DATA_MASK 0xFFFFFFFFL 20620//CP_APPEND_LAST_CS_FENCE_LO 20621#define CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE__SHIFT 0x0 20622#define CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE_MASK 0xFFFFFFFFL 20623//CP_APPEND_LAST_PS_FENCE_LO 20624#define CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE__SHIFT 0x0 20625#define CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE_MASK 0xFFFFFFFFL 20626//CP_ATOMIC_PREOP_LO 20627#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 20628#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL 20629//CP_ME_ATOMIC_PREOP_LO 20630#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 20631#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL 20632//CP_ATOMIC_PREOP_HI 20633#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 20634#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL 20635//CP_ME_ATOMIC_PREOP_HI 20636#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 20637#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL 20638//CP_GDS_ATOMIC0_PREOP_LO 20639#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0 20640#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL 20641//CP_ME_GDS_ATOMIC0_PREOP_LO 20642#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0 20643#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL 20644//CP_GDS_ATOMIC0_PREOP_HI 20645#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0 20646#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL 20647//CP_ME_GDS_ATOMIC0_PREOP_HI 20648#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0 20649#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL 20650//CP_GDS_ATOMIC1_PREOP_LO 20651#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0 20652#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL 20653//CP_ME_GDS_ATOMIC1_PREOP_LO 20654#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0 20655#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL 20656//CP_GDS_ATOMIC1_PREOP_HI 20657#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0 20658#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL 20659//CP_ME_GDS_ATOMIC1_PREOP_HI 20660#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0 20661#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL 20662//CP_ME_MC_WADDR_LO 20663#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO__SHIFT 0x2 20664#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO_MASK 0xFFFFFFFCL 20665//CP_ME_MC_WADDR_HI 20666#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI__SHIFT 0x0 20667#define CP_ME_MC_WADDR_HI__CACHE_POLICY__SHIFT 0x16 20668#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI_MASK 0x0000FFFFL 20669#define CP_ME_MC_WADDR_HI__CACHE_POLICY_MASK 0x00400000L 20670//CP_ME_MC_WDATA_LO 20671#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO__SHIFT 0x0 20672#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO_MASK 0xFFFFFFFFL 20673//CP_ME_MC_WDATA_HI 20674#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI__SHIFT 0x0 20675#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI_MASK 0xFFFFFFFFL 20676//CP_ME_MC_RADDR_LO 20677#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO__SHIFT 0x2 20678#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO_MASK 0xFFFFFFFCL 20679//CP_ME_MC_RADDR_HI 20680#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI__SHIFT 0x0 20681#define CP_ME_MC_RADDR_HI__CACHE_POLICY__SHIFT 0x16 20682#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI_MASK 0x0000FFFFL 20683#define CP_ME_MC_RADDR_HI__CACHE_POLICY_MASK 0x00400000L 20684//CP_SEM_WAIT_TIMER 20685#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER__SHIFT 0x0 20686#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER_MASK 0xFFFFFFFFL 20687//CP_SIG_SEM_ADDR_LO 20688#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0 20689#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3 20690#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x00000003L 20691#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xFFFFFFF8L 20692//CP_SIG_SEM_ADDR_HI 20693#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0 20694#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10 20695#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14 20696#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18 20697#define CP_SIG_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d 20698#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0x0000FFFFL 20699#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x00010000L 20700#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x00100000L 20701#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x03000000L 20702#define CP_SIG_SEM_ADDR_HI__SEM_SELECT_MASK 0xE0000000L 20703//CP_WAIT_REG_MEM_TIMEOUT 20704#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT__SHIFT 0x0 20705#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT_MASK 0xFFFFFFFFL 20706//CP_WAIT_SEM_ADDR_LO 20707#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0 20708#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3 20709#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x00000003L 20710#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xFFFFFFF8L 20711//CP_WAIT_SEM_ADDR_HI 20712#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0 20713#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10 20714#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14 20715#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18 20716#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d 20717#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0x0000FFFFL 20718#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x00010000L 20719#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x00100000L 20720#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x03000000L 20721#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK 0xE0000000L 20722//CP_DMA_PFP_CONTROL 20723#define CP_DMA_PFP_CONTROL__MEMLOG_CLEAR__SHIFT 0xa 20724#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd 20725#define CP_DMA_PFP_CONTROL__DST_SELECT__SHIFT 0x14 20726#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY__SHIFT 0x19 20727#define CP_DMA_PFP_CONTROL__SRC_SELECT__SHIFT 0x1d 20728#define CP_DMA_PFP_CONTROL__MEMLOG_CLEAR_MASK 0x00000400L 20729#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY_MASK 0x00002000L 20730#define CP_DMA_PFP_CONTROL__DST_SELECT_MASK 0x00300000L 20731#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY_MASK 0x02000000L 20732#define CP_DMA_PFP_CONTROL__SRC_SELECT_MASK 0x60000000L 20733//CP_DMA_ME_CONTROL 20734#define CP_DMA_ME_CONTROL__MEMLOG_CLEAR__SHIFT 0xa 20735#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd 20736#define CP_DMA_ME_CONTROL__DST_SELECT__SHIFT 0x14 20737#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT 0x19 20738#define CP_DMA_ME_CONTROL__SRC_SELECT__SHIFT 0x1d 20739#define CP_DMA_ME_CONTROL__MEMLOG_CLEAR_MASK 0x00000400L 20740#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK 0x00002000L 20741#define CP_DMA_ME_CONTROL__DST_SELECT_MASK 0x00300000L 20742#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY_MASK 0x02000000L 20743#define CP_DMA_ME_CONTROL__SRC_SELECT_MASK 0x60000000L 20744//CP_COHER_BASE_HI 20745#define CP_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x0 20746#define CP_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0x000000FFL 20747//CP_COHER_START_DELAY 20748#define CP_COHER_START_DELAY__START_DELAY_COUNT__SHIFT 0x0 20749#define CP_COHER_START_DELAY__START_DELAY_COUNT_MASK 0x0000003FL 20750//CP_COHER_CNTL 20751#define CP_COHER_CNTL__TC_NC_ACTION_ENA__SHIFT 0x3 20752#define CP_COHER_CNTL__TC_WC_ACTION_ENA__SHIFT 0x4 20753#define CP_COHER_CNTL__TC_INV_METADATA_ACTION_ENA__SHIFT 0x5 20754#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA__SHIFT 0xf 20755#define CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT 0x12 20756#define CP_COHER_CNTL__TCL1_ACTION_ENA__SHIFT 0x16 20757#define CP_COHER_CNTL__TC_ACTION_ENA__SHIFT 0x17 20758#define CP_COHER_CNTL__CB_ACTION_ENA__SHIFT 0x19 20759#define CP_COHER_CNTL__DB_ACTION_ENA__SHIFT 0x1a 20760#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA__SHIFT 0x1b 20761#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA__SHIFT 0x1c 20762#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA__SHIFT 0x1d 20763#define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA__SHIFT 0x1e 20764#define CP_COHER_CNTL__TC_NC_ACTION_ENA_MASK 0x00000008L 20765#define CP_COHER_CNTL__TC_WC_ACTION_ENA_MASK 0x00000010L 20766#define CP_COHER_CNTL__TC_INV_METADATA_ACTION_ENA_MASK 0x00000020L 20767#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA_MASK 0x00008000L 20768#define CP_COHER_CNTL__TC_WB_ACTION_ENA_MASK 0x00040000L 20769#define CP_COHER_CNTL__TCL1_ACTION_ENA_MASK 0x00400000L 20770#define CP_COHER_CNTL__TC_ACTION_ENA_MASK 0x00800000L 20771#define CP_COHER_CNTL__CB_ACTION_ENA_MASK 0x02000000L 20772#define CP_COHER_CNTL__DB_ACTION_ENA_MASK 0x04000000L 20773#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA_MASK 0x08000000L 20774#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA_MASK 0x10000000L 20775#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA_MASK 0x20000000L 20776#define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA_MASK 0x40000000L 20777//CP_COHER_SIZE 20778#define CP_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x0 20779#define CP_COHER_SIZE__COHER_SIZE_256B_MASK 0xFFFFFFFFL 20780//CP_COHER_BASE 20781#define CP_COHER_BASE__COHER_BASE_256B__SHIFT 0x0 20782#define CP_COHER_BASE__COHER_BASE_256B_MASK 0xFFFFFFFFL 20783//CP_COHER_STATUS 20784#define CP_COHER_STATUS__MEID__SHIFT 0x18 20785#define CP_COHER_STATUS__STATUS__SHIFT 0x1f 20786#define CP_COHER_STATUS__MEID_MASK 0x03000000L 20787#define CP_COHER_STATUS__STATUS_MASK 0x80000000L 20788//CP_DMA_ME_SRC_ADDR 20789#define CP_DMA_ME_SRC_ADDR__SRC_ADDR__SHIFT 0x0 20790#define CP_DMA_ME_SRC_ADDR__SRC_ADDR_MASK 0xFFFFFFFFL 20791//CP_DMA_ME_SRC_ADDR_HI 20792#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0 20793#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0x0000FFFFL 20794//CP_DMA_ME_DST_ADDR 20795#define CP_DMA_ME_DST_ADDR__DST_ADDR__SHIFT 0x0 20796#define CP_DMA_ME_DST_ADDR__DST_ADDR_MASK 0xFFFFFFFFL 20797//CP_DMA_ME_DST_ADDR_HI 20798#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0 20799#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI_MASK 0x0000FFFFL 20800//CP_DMA_ME_COMMAND 20801#define CP_DMA_ME_COMMAND__BYTE_COUNT__SHIFT 0x0 20802#define CP_DMA_ME_COMMAND__SAS__SHIFT 0x1a 20803#define CP_DMA_ME_COMMAND__DAS__SHIFT 0x1b 20804#define CP_DMA_ME_COMMAND__SAIC__SHIFT 0x1c 20805#define CP_DMA_ME_COMMAND__DAIC__SHIFT 0x1d 20806#define CP_DMA_ME_COMMAND__RAW_WAIT__SHIFT 0x1e 20807#define CP_DMA_ME_COMMAND__DIS_WC__SHIFT 0x1f 20808#define CP_DMA_ME_COMMAND__BYTE_COUNT_MASK 0x03FFFFFFL 20809#define CP_DMA_ME_COMMAND__SAS_MASK 0x04000000L 20810#define CP_DMA_ME_COMMAND__DAS_MASK 0x08000000L 20811#define CP_DMA_ME_COMMAND__SAIC_MASK 0x10000000L 20812#define CP_DMA_ME_COMMAND__DAIC_MASK 0x20000000L 20813#define CP_DMA_ME_COMMAND__RAW_WAIT_MASK 0x40000000L 20814#define CP_DMA_ME_COMMAND__DIS_WC_MASK 0x80000000L 20815//CP_DMA_PFP_SRC_ADDR 20816#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR__SHIFT 0x0 20817#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR_MASK 0xFFFFFFFFL 20818//CP_DMA_PFP_SRC_ADDR_HI 20819#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0 20820#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0x0000FFFFL 20821//CP_DMA_PFP_DST_ADDR 20822#define CP_DMA_PFP_DST_ADDR__DST_ADDR__SHIFT 0x0 20823#define CP_DMA_PFP_DST_ADDR__DST_ADDR_MASK 0xFFFFFFFFL 20824//CP_DMA_PFP_DST_ADDR_HI 20825#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0 20826#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI_MASK 0x0000FFFFL 20827//CP_DMA_PFP_COMMAND 20828#define CP_DMA_PFP_COMMAND__BYTE_COUNT__SHIFT 0x0 20829#define CP_DMA_PFP_COMMAND__SAS__SHIFT 0x1a 20830#define CP_DMA_PFP_COMMAND__DAS__SHIFT 0x1b 20831#define CP_DMA_PFP_COMMAND__SAIC__SHIFT 0x1c 20832#define CP_DMA_PFP_COMMAND__DAIC__SHIFT 0x1d 20833#define CP_DMA_PFP_COMMAND__RAW_WAIT__SHIFT 0x1e 20834#define CP_DMA_PFP_COMMAND__DIS_WC__SHIFT 0x1f 20835#define CP_DMA_PFP_COMMAND__BYTE_COUNT_MASK 0x03FFFFFFL 20836#define CP_DMA_PFP_COMMAND__SAS_MASK 0x04000000L 20837#define CP_DMA_PFP_COMMAND__DAS_MASK 0x08000000L 20838#define CP_DMA_PFP_COMMAND__SAIC_MASK 0x10000000L 20839#define CP_DMA_PFP_COMMAND__DAIC_MASK 0x20000000L 20840#define CP_DMA_PFP_COMMAND__RAW_WAIT_MASK 0x40000000L 20841#define CP_DMA_PFP_COMMAND__DIS_WC_MASK 0x80000000L 20842//CP_DMA_CNTL 20843#define CP_DMA_CNTL__UTCL1_FAULT_CONTROL__SHIFT 0x0 20844#define CP_DMA_CNTL__MIN_AVAILSZ__SHIFT 0x4 20845#define CP_DMA_CNTL__BUFFER_DEPTH__SHIFT 0x10 20846#define CP_DMA_CNTL__PIO_FIFO_EMPTY__SHIFT 0x1c 20847#define CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT 0x1d 20848#define CP_DMA_CNTL__PIO_COUNT__SHIFT 0x1e 20849#define CP_DMA_CNTL__UTCL1_FAULT_CONTROL_MASK 0x00000001L 20850#define CP_DMA_CNTL__MIN_AVAILSZ_MASK 0x00000030L 20851#define CP_DMA_CNTL__BUFFER_DEPTH_MASK 0x000F0000L 20852#define CP_DMA_CNTL__PIO_FIFO_EMPTY_MASK 0x10000000L 20853#define CP_DMA_CNTL__PIO_FIFO_FULL_MASK 0x20000000L 20854#define CP_DMA_CNTL__PIO_COUNT_MASK 0xC0000000L 20855//CP_DMA_READ_TAGS 20856#define CP_DMA_READ_TAGS__DMA_READ_TAG__SHIFT 0x0 20857#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID__SHIFT 0x1c 20858#define CP_DMA_READ_TAGS__DMA_READ_TAG_MASK 0x03FFFFFFL 20859#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID_MASK 0x10000000L 20860//CP_COHER_SIZE_HI 20861#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x0 20862#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0x000000FFL 20863//CP_PFP_IB_CONTROL 20864#define CP_PFP_IB_CONTROL__IB_EN__SHIFT 0x0 20865#define CP_PFP_IB_CONTROL__IB_EN_MASK 0x000000FFL 20866//CP_PFP_LOAD_CONTROL 20867#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN__SHIFT 0x0 20868#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN__SHIFT 0x1 20869#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT 0x10 20870#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN__SHIFT 0x18 20871#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN_MASK 0x00000001L 20872#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN_MASK 0x00000002L 20873#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN_MASK 0x00010000L 20874#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN_MASK 0x01000000L 20875//CP_SCRATCH_INDEX 20876#define CP_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0 20877#define CP_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000000FFL 20878//CP_SCRATCH_DATA 20879#define CP_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0 20880#define CP_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL 20881//CP_RB_OFFSET 20882#define CP_RB_OFFSET__RB_OFFSET__SHIFT 0x0 20883#define CP_RB_OFFSET__RB_OFFSET_MASK 0x000FFFFFL 20884//CP_IB1_OFFSET 20885#define CP_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0 20886#define CP_IB1_OFFSET__IB1_OFFSET_MASK 0x000FFFFFL 20887//CP_IB2_OFFSET 20888#define CP_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0 20889#define CP_IB2_OFFSET__IB2_OFFSET_MASK 0x000FFFFFL 20890//CP_IB1_PREAMBLE_BEGIN 20891#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN__SHIFT 0x0 20892#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN_MASK 0x000FFFFFL 20893//CP_IB1_PREAMBLE_END 20894#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END__SHIFT 0x0 20895#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END_MASK 0x000FFFFFL 20896//CP_IB2_PREAMBLE_BEGIN 20897#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN__SHIFT 0x0 20898#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN_MASK 0x000FFFFFL 20899//CP_IB2_PREAMBLE_END 20900#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END__SHIFT 0x0 20901#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END_MASK 0x000FFFFFL 20902//CP_CE_IB1_OFFSET 20903#define CP_CE_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0 20904#define CP_CE_IB1_OFFSET__IB1_OFFSET_MASK 0x000FFFFFL 20905//CP_CE_IB2_OFFSET 20906#define CP_CE_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0 20907#define CP_CE_IB2_OFFSET__IB2_OFFSET_MASK 0x000FFFFFL 20908//CP_CE_COUNTER 20909#define CP_CE_COUNTER__CONST_ENGINE_COUNT__SHIFT 0x0 20910#define CP_CE_COUNTER__CONST_ENGINE_COUNT_MASK 0xFFFFFFFFL 20911//CP_CE_RB_OFFSET 20912#define CP_CE_RB_OFFSET__RB_OFFSET__SHIFT 0x0 20913#define CP_CE_RB_OFFSET__RB_OFFSET_MASK 0x000FFFFFL 20914//CP_CE_INIT_CMD_BUFSZ 20915#define CP_CE_INIT_CMD_BUFSZ__INIT_CMD_REQSZ__SHIFT 0x0 20916#define CP_CE_INIT_CMD_BUFSZ__INIT_CMD_REQSZ_MASK 0x00000FFFL 20917//CP_CE_IB1_CMD_BUFSZ 20918#define CP_CE_IB1_CMD_BUFSZ__IB1_CMD_REQSZ__SHIFT 0x0 20919#define CP_CE_IB1_CMD_BUFSZ__IB1_CMD_REQSZ_MASK 0x000FFFFFL 20920//CP_CE_IB2_CMD_BUFSZ 20921#define CP_CE_IB2_CMD_BUFSZ__IB2_CMD_REQSZ__SHIFT 0x0 20922#define CP_CE_IB2_CMD_BUFSZ__IB2_CMD_REQSZ_MASK 0x000FFFFFL 20923//CP_IB1_CMD_BUFSZ 20924#define CP_IB1_CMD_BUFSZ__IB1_CMD_REQSZ__SHIFT 0x0 20925#define CP_IB1_CMD_BUFSZ__IB1_CMD_REQSZ_MASK 0x000FFFFFL 20926//CP_IB2_CMD_BUFSZ 20927#define CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ__SHIFT 0x0 20928#define CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ_MASK 0x000FFFFFL 20929//CP_ST_CMD_BUFSZ 20930#define CP_ST_CMD_BUFSZ__ST_CMD_REQSZ__SHIFT 0x0 20931#define CP_ST_CMD_BUFSZ__ST_CMD_REQSZ_MASK 0x000FFFFFL 20932//CP_CE_INIT_BASE_LO 20933#define CP_CE_INIT_BASE_LO__INIT_BASE_LO__SHIFT 0x5 20934#define CP_CE_INIT_BASE_LO__INIT_BASE_LO_MASK 0xFFFFFFE0L 20935//CP_CE_INIT_BASE_HI 20936#define CP_CE_INIT_BASE_HI__INIT_BASE_HI__SHIFT 0x0 20937#define CP_CE_INIT_BASE_HI__INIT_BASE_HI_MASK 0x0000FFFFL 20938//CP_CE_INIT_BUFSZ 20939#define CP_CE_INIT_BUFSZ__INIT_BUFSZ__SHIFT 0x0 20940#define CP_CE_INIT_BUFSZ__INIT_BUFSZ_MASK 0x00000FFFL 20941//CP_CE_IB1_BASE_LO 20942#define CP_CE_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2 20943#define CP_CE_IB1_BASE_LO__IB1_BASE_LO_MASK 0xFFFFFFFCL 20944//CP_CE_IB1_BASE_HI 20945#define CP_CE_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0 20946#define CP_CE_IB1_BASE_HI__IB1_BASE_HI_MASK 0x0000FFFFL 20947//CP_CE_IB1_BUFSZ 20948#define CP_CE_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0 20949#define CP_CE_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000FFFFFL 20950//CP_CE_IB2_BASE_LO 20951#define CP_CE_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2 20952#define CP_CE_IB2_BASE_LO__IB2_BASE_LO_MASK 0xFFFFFFFCL 20953//CP_CE_IB2_BASE_HI 20954#define CP_CE_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0 20955#define CP_CE_IB2_BASE_HI__IB2_BASE_HI_MASK 0x0000FFFFL 20956//CP_CE_IB2_BUFSZ 20957#define CP_CE_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0 20958#define CP_CE_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000FFFFFL 20959//CP_IB1_BASE_LO 20960#define CP_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2 20961#define CP_IB1_BASE_LO__IB1_BASE_LO_MASK 0xFFFFFFFCL 20962//CP_IB1_BASE_HI 20963#define CP_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0 20964#define CP_IB1_BASE_HI__IB1_BASE_HI_MASK 0x0000FFFFL 20965//CP_IB1_BUFSZ 20966#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0 20967#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000FFFFFL 20968//CP_IB2_BASE_LO 20969#define CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2 20970#define CP_IB2_BASE_LO__IB2_BASE_LO_MASK 0xFFFFFFFCL 20971//CP_IB2_BASE_HI 20972#define CP_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0 20973#define CP_IB2_BASE_HI__IB2_BASE_HI_MASK 0x0000FFFFL 20974//CP_IB2_BUFSZ 20975#define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0 20976#define CP_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000FFFFFL 20977//CP_ST_BASE_LO 20978#define CP_ST_BASE_LO__ST_BASE_LO__SHIFT 0x2 20979#define CP_ST_BASE_LO__ST_BASE_LO_MASK 0xFFFFFFFCL 20980//CP_ST_BASE_HI 20981#define CP_ST_BASE_HI__ST_BASE_HI__SHIFT 0x0 20982#define CP_ST_BASE_HI__ST_BASE_HI_MASK 0x0000FFFFL 20983//CP_ST_BUFSZ 20984#define CP_ST_BUFSZ__ST_BUFSZ__SHIFT 0x0 20985#define CP_ST_BUFSZ__ST_BUFSZ_MASK 0x000FFFFFL 20986//CP_EOP_DONE_EVENT_CNTL 20987#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP__SHIFT 0x0 20988#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA__SHIFT 0xc 20989#define CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY__SHIFT 0x19 20990#define CP_EOP_DONE_EVENT_CNTL__EXECUTE__SHIFT 0x1c 20991#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP_MASK 0x0000007FL 20992#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA_MASK 0x0003F000L 20993#define CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY_MASK 0x02000000L 20994#define CP_EOP_DONE_EVENT_CNTL__EXECUTE_MASK 0x10000000L 20995//CP_EOP_DONE_DATA_CNTL 20996#define CP_EOP_DONE_DATA_CNTL__DST_SEL__SHIFT 0x10 20997#define CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT 0x18 20998#define CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT 0x1d 20999#define CP_EOP_DONE_DATA_CNTL__DST_SEL_MASK 0x00030000L 21000#define CP_EOP_DONE_DATA_CNTL__INT_SEL_MASK 0x07000000L
21001#define CP_EOP_DONE_DATA_CNTL__DATA_SEL_MASK 0xE0000000L 21002//CP_EOP_DONE_CNTX_ID 21003#define CP_EOP_DONE_CNTX_ID__CNTX_ID__SHIFT 0x0 21004#define CP_EOP_DONE_CNTX_ID__CNTX_ID_MASK 0xFFFFFFFFL 21005//CP_PFP_COMPLETION_STATUS 21006#define CP_PFP_COMPLETION_STATUS__STATUS__SHIFT 0x0 21007#define CP_PFP_COMPLETION_STATUS__STATUS_MASK 0x00000003L 21008//CP_CE_COMPLETION_STATUS 21009#define CP_CE_COMPLETION_STATUS__STATUS__SHIFT 0x0 21010#define CP_CE_COMPLETION_STATUS__STATUS_MASK 0x00000003L 21011//CP_PRED_NOT_VISIBLE 21012#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE__SHIFT 0x0 21013#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE_MASK 0x00000001L 21014//CP_PFP_METADATA_BASE_ADDR 21015#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0 21016#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO_MASK 0xFFFFFFFFL 21017//CP_PFP_METADATA_BASE_ADDR_HI 21018#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 21019#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL 21020//CP_CE_METADATA_BASE_ADDR 21021#define CP_CE_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0 21022#define CP_CE_METADATA_BASE_ADDR__ADDR_LO_MASK 0xFFFFFFFFL 21023//CP_CE_METADATA_BASE_ADDR_HI 21024#define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 21025#define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL 21026//CP_DRAW_INDX_INDR_ADDR 21027#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO__SHIFT 0x0 21028#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO_MASK 0xFFFFFFFFL 21029//CP_DRAW_INDX_INDR_ADDR_HI 21030#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0 21031#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL 21032//CP_DISPATCH_INDR_ADDR 21033#define CP_DISPATCH_INDR_ADDR__ADDR_LO__SHIFT 0x0 21034#define CP_DISPATCH_INDR_ADDR__ADDR_LO_MASK 0xFFFFFFFFL 21035//CP_DISPATCH_INDR_ADDR_HI 21036#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0 21037#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL 21038//CP_INDEX_BASE_ADDR 21039#define CP_INDEX_BASE_ADDR__ADDR_LO__SHIFT 0x0 21040#define CP_INDEX_BASE_ADDR__ADDR_LO_MASK 0xFFFFFFFFL 21041//CP_INDEX_BASE_ADDR_HI 21042#define CP_INDEX_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 21043#define CP_INDEX_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL 21044//CP_INDEX_TYPE 21045#define CP_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0 21046#define CP_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L 21047//CP_GDS_BKUP_ADDR 21048#define CP_GDS_BKUP_ADDR__ADDR_LO__SHIFT 0x0 21049#define CP_GDS_BKUP_ADDR__ADDR_LO_MASK 0xFFFFFFFFL 21050//CP_GDS_BKUP_ADDR_HI 21051#define CP_GDS_BKUP_ADDR_HI__ADDR_HI__SHIFT 0x0 21052#define CP_GDS_BKUP_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL 21053//CP_SAMPLE_STATUS 21054#define CP_SAMPLE_STATUS__Z_PASS_ACITVE__SHIFT 0x0 21055#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE__SHIFT 0x1 21056#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE__SHIFT 0x2 21057#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE__SHIFT 0x3 21058#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE__SHIFT 0x4 21059#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE__SHIFT 0x5 21060#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE__SHIFT 0x6 21061#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE__SHIFT 0x7 21062#define CP_SAMPLE_STATUS__Z_PASS_ACITVE_MASK 0x00000001L 21063#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE_MASK 0x00000002L 21064#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE_MASK 0x00000004L 21065#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE_MASK 0x00000008L 21066#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE_MASK 0x00000010L 21067#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE_MASK 0x00000020L 21068#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE_MASK 0x00000040L 21069#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE_MASK 0x00000080L 21070//CP_ME_COHER_CNTL 21071#define CP_ME_COHER_CNTL__DEST_BASE_0_ENA__SHIFT 0x0 21072#define CP_ME_COHER_CNTL__DEST_BASE_1_ENA__SHIFT 0x1 21073#define CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA__SHIFT 0x6 21074#define CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA__SHIFT 0x7 21075#define CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA__SHIFT 0x8 21076#define CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA__SHIFT 0x9 21077#define CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT 0xa 21078#define CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA__SHIFT 0xb 21079#define CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA__SHIFT 0xc 21080#define CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA__SHIFT 0xd 21081#define CP_ME_COHER_CNTL__DB_DEST_BASE_ENA__SHIFT 0xe 21082#define CP_ME_COHER_CNTL__DEST_BASE_2_ENA__SHIFT 0x13 21083#define CP_ME_COHER_CNTL__DEST_BASE_3_ENA__SHIFT 0x15 21084#define CP_ME_COHER_CNTL__DEST_BASE_0_ENA_MASK 0x00000001L 21085#define CP_ME_COHER_CNTL__DEST_BASE_1_ENA_MASK 0x00000002L 21086#define CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA_MASK 0x00000040L 21087#define CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA_MASK 0x00000080L 21088#define CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA_MASK 0x00000100L 21089#define CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA_MASK 0x00000200L 21090#define CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA_MASK 0x00000400L 21091#define CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA_MASK 0x00000800L 21092#define CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA_MASK 0x00001000L 21093#define CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA_MASK 0x00002000L 21094#define CP_ME_COHER_CNTL__DB_DEST_BASE_ENA_MASK 0x00004000L 21095#define CP_ME_COHER_CNTL__DEST_BASE_2_ENA_MASK 0x00080000L 21096#define CP_ME_COHER_CNTL__DEST_BASE_3_ENA_MASK 0x00200000L 21097//CP_ME_COHER_SIZE 21098#define CP_ME_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x0 21099#define CP_ME_COHER_SIZE__COHER_SIZE_256B_MASK 0xFFFFFFFFL 21100//CP_ME_COHER_SIZE_HI 21101#define CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x0 21102#define CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0x000000FFL 21103//CP_ME_COHER_BASE 21104#define CP_ME_COHER_BASE__COHER_BASE_256B__SHIFT 0x0 21105#define CP_ME_COHER_BASE__COHER_BASE_256B_MASK 0xFFFFFFFFL 21106//CP_ME_COHER_BASE_HI 21107#define CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x0 21108#define CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0x000000FFL 21109//CP_ME_COHER_STATUS 21110#define CP_ME_COHER_STATUS__MATCHING_GFX_CNTX__SHIFT 0x0 21111#define CP_ME_COHER_STATUS__STATUS__SHIFT 0x1f 21112#define CP_ME_COHER_STATUS__MATCHING_GFX_CNTX_MASK 0x000000FFL 21113#define CP_ME_COHER_STATUS__STATUS_MASK 0x80000000L 21114//RLC_GPM_PERF_COUNT_0 21115#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL__SHIFT 0x0 21116#define RLC_GPM_PERF_COUNT_0__SE_INDEX__SHIFT 0x4 21117#define RLC_GPM_PERF_COUNT_0__SH_INDEX__SHIFT 0x8 21118#define RLC_GPM_PERF_COUNT_0__CU_INDEX__SHIFT 0xc 21119#define RLC_GPM_PERF_COUNT_0__EVENT_SEL__SHIFT 0x10 21120#define RLC_GPM_PERF_COUNT_0__UNUSED__SHIFT 0x12 21121#define RLC_GPM_PERF_COUNT_0__ENABLE__SHIFT 0x14 21122#define RLC_GPM_PERF_COUNT_0__RESERVED__SHIFT 0x15 21123#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL_MASK 0x0000000FL 21124#define RLC_GPM_PERF_COUNT_0__SE_INDEX_MASK 0x000000F0L 21125#define RLC_GPM_PERF_COUNT_0__SH_INDEX_MASK 0x00000F00L 21126#define RLC_GPM_PERF_COUNT_0__CU_INDEX_MASK 0x0000F000L 21127#define RLC_GPM_PERF_COUNT_0__EVENT_SEL_MASK 0x00030000L 21128#define RLC_GPM_PERF_COUNT_0__UNUSED_MASK 0x000C0000L 21129#define RLC_GPM_PERF_COUNT_0__ENABLE_MASK 0x00100000L 21130#define RLC_GPM_PERF_COUNT_0__RESERVED_MASK 0xFFE00000L 21131//RLC_GPM_PERF_COUNT_1 21132#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL__SHIFT 0x0 21133#define RLC_GPM_PERF_COUNT_1__SE_INDEX__SHIFT 0x4 21134#define RLC_GPM_PERF_COUNT_1__SH_INDEX__SHIFT 0x8 21135#define RLC_GPM_PERF_COUNT_1__CU_INDEX__SHIFT 0xc 21136#define RLC_GPM_PERF_COUNT_1__EVENT_SEL__SHIFT 0x10 21137#define RLC_GPM_PERF_COUNT_1__UNUSED__SHIFT 0x12 21138#define RLC_GPM_PERF_COUNT_1__ENABLE__SHIFT 0x14 21139#define RLC_GPM_PERF_COUNT_1__RESERVED__SHIFT 0x15 21140#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL_MASK 0x0000000FL 21141#define RLC_GPM_PERF_COUNT_1__SE_INDEX_MASK 0x000000F0L 21142#define RLC_GPM_PERF_COUNT_1__SH_INDEX_MASK 0x00000F00L 21143#define RLC_GPM_PERF_COUNT_1__CU_INDEX_MASK 0x0000F000L 21144#define RLC_GPM_PERF_COUNT_1__EVENT_SEL_MASK 0x00030000L 21145#define RLC_GPM_PERF_COUNT_1__UNUSED_MASK 0x000C0000L 21146#define RLC_GPM_PERF_COUNT_1__ENABLE_MASK 0x00100000L 21147#define RLC_GPM_PERF_COUNT_1__RESERVED_MASK 0xFFE00000L 21148//GRBM_GFX_INDEX 21149#define GRBM_GFX_INDEX__INSTANCE_INDEX__SHIFT 0x0 21150#define GRBM_GFX_INDEX__SH_INDEX__SHIFT 0x8 21151#define GRBM_GFX_INDEX__SE_INDEX__SHIFT 0x10 21152#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES__SHIFT 0x1d 21153#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e 21154#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT 0x1f 21155#define GRBM_GFX_INDEX__INSTANCE_INDEX_MASK 0x000000FFL 21156#define GRBM_GFX_INDEX__SH_INDEX_MASK 0x0000FF00L 21157#define GRBM_GFX_INDEX__SE_INDEX_MASK 0x00FF0000L 21158#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK 0x20000000L 21159#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK 0x40000000L 21160#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK 0x80000000L 21161//VGT_GSVS_RING_SIZE 21162#define VGT_GSVS_RING_SIZE__MEM_SIZE__SHIFT 0x0 21163#define VGT_GSVS_RING_SIZE__MEM_SIZE_MASK 0xFFFFFFFFL 21164//VGT_PRIMITIVE_TYPE 21165#define VGT_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0 21166#define VGT_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x0000003FL 21167//VGT_INDEX_TYPE 21168#define VGT_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0 21169#define VGT_INDEX_TYPE__PRIMGEN_EN__SHIFT 0x8 21170#define VGT_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L 21171#define VGT_INDEX_TYPE__PRIMGEN_EN_MASK 0x00000100L 21172//VGT_STRMOUT_BUFFER_FILLED_SIZE_0 21173#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE__SHIFT 0x0 21174#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE_MASK 0xFFFFFFFFL 21175//VGT_STRMOUT_BUFFER_FILLED_SIZE_1 21176#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE__SHIFT 0x0 21177#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE_MASK 0xFFFFFFFFL 21178//VGT_STRMOUT_BUFFER_FILLED_SIZE_2 21179#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE__SHIFT 0x0 21180#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE_MASK 0xFFFFFFFFL 21181//VGT_STRMOUT_BUFFER_FILLED_SIZE_3 21182#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE__SHIFT 0x0 21183#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE_MASK 0xFFFFFFFFL 21184//VGT_MAX_VTX_INDX 21185#define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT 0x0 21186#define VGT_MAX_VTX_INDX__MAX_INDX_MASK 0xFFFFFFFFL 21187//VGT_MIN_VTX_INDX 21188#define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT 0x0 21189#define VGT_MIN_VTX_INDX__MIN_INDX_MASK 0xFFFFFFFFL 21190//VGT_INDX_OFFSET 21191#define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT 0x0 21192#define VGT_INDX_OFFSET__INDX_OFFSET_MASK 0xFFFFFFFFL 21193//VGT_MULTI_PRIM_IB_RESET_EN 21194#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN__SHIFT 0x0 21195#define VGT_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS__SHIFT 0x1 21196#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN_MASK 0x00000001L 21197#define VGT_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS_MASK 0x00000002L 21198//VGT_NUM_INDICES 21199#define VGT_NUM_INDICES__NUM_INDICES__SHIFT 0x0 21200#define VGT_NUM_INDICES__NUM_INDICES_MASK 0xFFFFFFFFL 21201//VGT_NUM_INSTANCES 21202#define VGT_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0 21203#define VGT_NUM_INSTANCES__NUM_INSTANCES_MASK 0xFFFFFFFFL 21204//VGT_TF_RING_SIZE 21205#define VGT_TF_RING_SIZE__SIZE__SHIFT 0x0 21206#define VGT_TF_RING_SIZE__SIZE_MASK 0x0000FFFFL 21207//VGT_HS_OFFCHIP_PARAM 21208#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING__SHIFT 0x0 21209#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY__SHIFT 0x9 21210#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING_MASK 0x000001FFL 21211#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY_MASK 0x00000600L 21212//VGT_TF_MEMORY_BASE 21213#define VGT_TF_MEMORY_BASE__BASE__SHIFT 0x0 21214#define VGT_TF_MEMORY_BASE__BASE_MASK 0xFFFFFFFFL 21215//VGT_TF_MEMORY_BASE_HI 21216#define VGT_TF_MEMORY_BASE_HI__BASE_HI__SHIFT 0x0 21217#define VGT_TF_MEMORY_BASE_HI__BASE_HI_MASK 0x000000FFL 21218//WD_POS_BUF_BASE 21219#define WD_POS_BUF_BASE__BASE__SHIFT 0x0 21220#define WD_POS_BUF_BASE__BASE_MASK 0xFFFFFFFFL 21221//WD_POS_BUF_BASE_HI 21222#define WD_POS_BUF_BASE_HI__BASE_HI__SHIFT 0x0 21223#define WD_POS_BUF_BASE_HI__BASE_HI_MASK 0x000000FFL 21224//WD_CNTL_SB_BUF_BASE 21225#define WD_CNTL_SB_BUF_BASE__BASE__SHIFT 0x0 21226#define WD_CNTL_SB_BUF_BASE__BASE_MASK 0xFFFFFFFFL 21227//WD_CNTL_SB_BUF_BASE_HI 21228#define WD_CNTL_SB_BUF_BASE_HI__BASE_HI__SHIFT 0x0 21229#define WD_CNTL_SB_BUF_BASE_HI__BASE_HI_MASK 0x000000FFL 21230//WD_INDEX_BUF_BASE 21231#define WD_INDEX_BUF_BASE__BASE__SHIFT 0x0 21232#define WD_INDEX_BUF_BASE__BASE_MASK 0xFFFFFFFFL 21233//WD_INDEX_BUF_BASE_HI 21234#define WD_INDEX_BUF_BASE_HI__BASE_HI__SHIFT 0x0 21235#define WD_INDEX_BUF_BASE_HI__BASE_HI_MASK 0x000000FFL 21236//IA_MULTI_VGT_PARAM 21237#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE__SHIFT 0x0 21238#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON__SHIFT 0x10 21239#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP__SHIFT 0x11 21240#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON__SHIFT 0x12 21241#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI__SHIFT 0x13 21242#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP__SHIFT 0x14 21243#define IA_MULTI_VGT_PARAM__EN_INST_OPT_BASIC__SHIFT 0x15 21244#define IA_MULTI_VGT_PARAM__EN_INST_OPT_ADV__SHIFT 0x16 21245#define IA_MULTI_VGT_PARAM__HW_USE_ONLY__SHIFT 0x17 21246#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE_MASK 0x0000FFFFL 21247#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON_MASK 0x00010000L 21248#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP_MASK 0x00020000L 21249#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON_MASK 0x00040000L 21250#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI_MASK 0x00080000L 21251#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP_MASK 0x00100000L 21252#define IA_MULTI_VGT_PARAM__EN_INST_OPT_BASIC_MASK 0x00200000L 21253#define IA_MULTI_VGT_PARAM__EN_INST_OPT_ADV_MASK 0x00400000L 21254#define IA_MULTI_VGT_PARAM__HW_USE_ONLY_MASK 0x00800000L 21255//VGT_INSTANCE_BASE_ID 21256#define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID__SHIFT 0x0 21257#define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID_MASK 0xFFFFFFFFL 21258//PA_SU_LINE_STIPPLE_VALUE 21259#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE__SHIFT 0x0 21260#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE_MASK 0x00FFFFFFL 21261//PA_SC_LINE_STIPPLE_STATE 21262#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT 0x0 21263#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT 0x8 21264#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK 0x0000000FL 21265#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK 0x0000FF00L 21266//PA_SC_SCREEN_EXTENT_MIN_0 21267#define PA_SC_SCREEN_EXTENT_MIN_0__X__SHIFT 0x0 21268#define PA_SC_SCREEN_EXTENT_MIN_0__Y__SHIFT 0x10 21269#define PA_SC_SCREEN_EXTENT_MIN_0__X_MASK 0x0000FFFFL 21270#define PA_SC_SCREEN_EXTENT_MIN_0__Y_MASK 0xFFFF0000L 21271//PA_SC_SCREEN_EXTENT_MAX_0 21272#define PA_SC_SCREEN_EXTENT_MAX_0__X__SHIFT 0x0 21273#define PA_SC_SCREEN_EXTENT_MAX_0__Y__SHIFT 0x10 21274#define PA_SC_SCREEN_EXTENT_MAX_0__X_MASK 0x0000FFFFL 21275#define PA_SC_SCREEN_EXTENT_MAX_0__Y_MASK 0xFFFF0000L 21276//PA_SC_SCREEN_EXTENT_MIN_1 21277#define PA_SC_SCREEN_EXTENT_MIN_1__X__SHIFT 0x0 21278#define PA_SC_SCREEN_EXTENT_MIN_1__Y__SHIFT 0x10 21279#define PA_SC_SCREEN_EXTENT_MIN_1__X_MASK 0x0000FFFFL 21280#define PA_SC_SCREEN_EXTENT_MIN_1__Y_MASK 0xFFFF0000L 21281//PA_SC_SCREEN_EXTENT_MAX_1 21282#define PA_SC_SCREEN_EXTENT_MAX_1__X__SHIFT 0x0 21283#define PA_SC_SCREEN_EXTENT_MAX_1__Y__SHIFT 0x10 21284#define PA_SC_SCREEN_EXTENT_MAX_1__X_MASK 0x0000FFFFL 21285#define PA_SC_SCREEN_EXTENT_MAX_1__Y_MASK 0xFFFF0000L 21286//PA_SC_P3D_TRAP_SCREEN_HV_EN 21287#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 21288#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 21289#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L 21290#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L 21291//PA_SC_P3D_TRAP_SCREEN_H 21292#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 21293#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD_MASK 0x00003FFFL 21294//PA_SC_P3D_TRAP_SCREEN_V 21295#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 21296#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD_MASK 0x00003FFFL 21297//PA_SC_P3D_TRAP_SCREEN_OCCURRENCE 21298#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 21299#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL 21300//PA_SC_P3D_TRAP_SCREEN_COUNT 21301#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 21302#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL 21303//PA_SC_HP3D_TRAP_SCREEN_HV_EN 21304#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 21305#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 21306#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L 21307#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L 21308//PA_SC_HP3D_TRAP_SCREEN_H 21309#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 21310#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD_MASK 0x00003FFFL 21311//PA_SC_HP3D_TRAP_SCREEN_V 21312#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 21313#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD_MASK 0x00003FFFL 21314//PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE 21315#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 21316#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL 21317//PA_SC_HP3D_TRAP_SCREEN_COUNT 21318#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 21319#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL 21320//PA_SC_TRAP_SCREEN_HV_EN 21321#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 21322#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 21323#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L 21324#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L 21325//PA_SC_TRAP_SCREEN_H 21326#define PA_SC_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 21327#define PA_SC_TRAP_SCREEN_H__X_COORD_MASK 0x00003FFFL 21328//PA_SC_TRAP_SCREEN_V 21329#define PA_SC_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 21330#define PA_SC_TRAP_SCREEN_V__Y_COORD_MASK 0x00003FFFL 21331//PA_SC_TRAP_SCREEN_OCCURRENCE 21332#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 21333#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL 21334//PA_SC_TRAP_SCREEN_COUNT 21335#define PA_SC_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 21336#define PA_SC_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL 21337//SQ_THREAD_TRACE_BASE 21338#define SQ_THREAD_TRACE_BASE__ADDR__SHIFT 0x0 21339#define SQ_THREAD_TRACE_BASE__ADDR_MASK 0xFFFFFFFFL 21340//SQ_THREAD_TRACE_SIZE 21341#define SQ_THREAD_TRACE_SIZE__SIZE__SHIFT 0x0 21342#define SQ_THREAD_TRACE_SIZE__SIZE_MASK 0x003FFFFFL 21343//SQ_THREAD_TRACE_MASK 21344#define SQ_THREAD_TRACE_MASK__CU_SEL__SHIFT 0x0 21345#define SQ_THREAD_TRACE_MASK__SH_SEL__SHIFT 0x5 21346#define SQ_THREAD_TRACE_MASK__REG_STALL_EN__SHIFT 0x7 21347#define SQ_THREAD_TRACE_MASK__SIMD_EN__SHIFT 0x8 21348#define SQ_THREAD_TRACE_MASK__VM_ID_MASK__SHIFT 0xc 21349#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN__SHIFT 0xe 21350#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN__SHIFT 0xf 21351#define SQ_THREAD_TRACE_MASK__CU_SEL_MASK 0x0000001FL 21352#define SQ_THREAD_TRACE_MASK__SH_SEL_MASK 0x00000020L 21353#define SQ_THREAD_TRACE_MASK__REG_STALL_EN_MASK 0x00000080L 21354#define SQ_THREAD_TRACE_MASK__SIMD_EN_MASK 0x00000F00L 21355#define SQ_THREAD_TRACE_MASK__VM_ID_MASK_MASK 0x00003000L 21356#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN_MASK 0x00004000L 21357#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN_MASK 0x00008000L 21358//SQ_THREAD_TRACE_TOKEN_MASK 21359#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK__SHIFT 0x0 21360#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK__SHIFT 0x10 21361#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL__SHIFT 0x18 21362#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK_MASK 0x0000FFFFL 21363#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK_MASK 0x00FF0000L 21364#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL_MASK 0x01000000L 21365//SQ_THREAD_TRACE_PERF_MASK 21366#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK__SHIFT 0x0 21367#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK__SHIFT 0x10 21368#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK_MASK 0x0000FFFFL 21369#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK_MASK 0xFFFF0000L 21370//SQ_THREAD_TRACE_CTRL 21371#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER__SHIFT 0x1f 21372#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER_MASK 0x80000000L 21373//SQ_THREAD_TRACE_MODE 21374#define SQ_THREAD_TRACE_MODE__MASK_PS__SHIFT 0x0 21375#define SQ_THREAD_TRACE_MODE__MASK_VS__SHIFT 0x3 21376#define SQ_THREAD_TRACE_MODE__MASK_GS__SHIFT 0x6 21377#define SQ_THREAD_TRACE_MODE__MASK_ES__SHIFT 0x9 21378#define SQ_THREAD_TRACE_MODE__MASK_HS__SHIFT 0xc 21379#define SQ_THREAD_TRACE_MODE__MASK_LS__SHIFT 0xf 21380#define SQ_THREAD_TRACE_MODE__MASK_CS__SHIFT 0x12 21381#define SQ_THREAD_TRACE_MODE__MODE__SHIFT 0x15 21382#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE__SHIFT 0x17 21383#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN__SHIFT 0x19 21384#define SQ_THREAD_TRACE_MODE__TC_PERF_EN__SHIFT 0x1a 21385#define SQ_THREAD_TRACE_MODE__ISSUE_MASK__SHIFT 0x1b 21386#define SQ_THREAD_TRACE_MODE__TEST_MODE__SHIFT 0x1d 21387#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN__SHIFT 0x1e 21388#define SQ_THREAD_TRACE_MODE__WRAP__SHIFT 0x1f 21389#define SQ_THREAD_TRACE_MODE__MASK_PS_MASK 0x00000007L 21390#define SQ_THREAD_TRACE_MODE__MASK_VS_MASK 0x00000038L 21391#define SQ_THREAD_TRACE_MODE__MASK_GS_MASK 0x000001C0L 21392#define SQ_THREAD_TRACE_MODE__MASK_ES_MASK 0x00000E00L 21393#define SQ_THREAD_TRACE_MODE__MASK_HS_MASK 0x00007000L 21394#define SQ_THREAD_TRACE_MODE__MASK_LS_MASK 0x00038000L 21395#define SQ_THREAD_TRACE_MODE__MASK_CS_MASK 0x001C0000L 21396#define SQ_THREAD_TRACE_MODE__MODE_MASK 0x00600000L 21397#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE_MASK 0x01800000L 21398#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN_MASK 0x02000000L 21399#define SQ_THREAD_TRACE_MODE__TC_PERF_EN_MASK 0x04000000L 21400#define SQ_THREAD_TRACE_MODE__ISSUE_MASK_MASK 0x18000000L 21401#define SQ_THREAD_TRACE_MODE__TEST_MODE_MASK 0x20000000L 21402#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN_MASK 0x40000000L 21403#define SQ_THREAD_TRACE_MODE__WRAP_MASK 0x80000000L 21404//SQ_THREAD_TRACE_BASE2 21405#define SQ_THREAD_TRACE_BASE2__ADDR_HI__SHIFT 0x0 21406#define SQ_THREAD_TRACE_BASE2__ADDR_HI_MASK 0x0000000FL 21407//SQ_THREAD_TRACE_TOKEN_MASK2 21408#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK__SHIFT 0x0 21409#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK_MASK 0xFFFFFFFFL 21410//SQ_THREAD_TRACE_WPTR 21411#define SQ_THREAD_TRACE_WPTR__WPTR__SHIFT 0x0 21412#define SQ_THREAD_TRACE_WPTR__READ_OFFSET__SHIFT 0x1e 21413#define SQ_THREAD_TRACE_WPTR__WPTR_MASK 0x3FFFFFFFL 21414#define SQ_THREAD_TRACE_WPTR__READ_OFFSET_MASK 0xC0000000L 21415//SQ_THREAD_TRACE_STATUS 21416#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING__SHIFT 0x0 21417#define SQ_THREAD_TRACE_STATUS__FINISH_DONE__SHIFT 0x10 21418#define SQ_THREAD_TRACE_STATUS__UTC_ERROR__SHIFT 0x1c 21419#define SQ_THREAD_TRACE_STATUS__NEW_BUF__SHIFT 0x1d 21420#define SQ_THREAD_TRACE_STATUS__BUSY__SHIFT 0x1e 21421#define SQ_THREAD_TRACE_STATUS__FULL__SHIFT 0x1f 21422#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING_MASK 0x000003FFL 21423#define SQ_THREAD_TRACE_STATUS__FINISH_DONE_MASK 0x03FF0000L 21424#define SQ_THREAD_TRACE_STATUS__UTC_ERROR_MASK 0x10000000L 21425#define SQ_THREAD_TRACE_STATUS__NEW_BUF_MASK 0x20000000L 21426#define SQ_THREAD_TRACE_STATUS__BUSY_MASK 0x40000000L 21427#define SQ_THREAD_TRACE_STATUS__FULL_MASK 0x80000000L 21428//SQ_THREAD_TRACE_HIWATER 21429#define SQ_THREAD_TRACE_HIWATER__HIWATER__SHIFT 0x0 21430#define SQ_THREAD_TRACE_HIWATER__HIWATER_MASK 0x00000007L 21431//SQ_THREAD_TRACE_CNTR 21432#define SQ_THREAD_TRACE_CNTR__CNTR__SHIFT 0x0 21433#define SQ_THREAD_TRACE_CNTR__CNTR_MASK 0xFFFFFFFFL 21434//SQ_THREAD_TRACE_USERDATA_0 21435#define SQ_THREAD_TRACE_USERDATA_0__DATA__SHIFT 0x0 21436#define SQ_THREAD_TRACE_USERDATA_0__DATA_MASK 0xFFFFFFFFL 21437//SQ_THREAD_TRACE_USERDATA_1 21438#define SQ_THREAD_TRACE_USERDATA_1__DATA__SHIFT 0x0 21439#define SQ_THREAD_TRACE_USERDATA_1__DATA_MASK 0xFFFFFFFFL 21440//SQ_THREAD_TRACE_USERDATA_2 21441#define SQ_THREAD_TRACE_USERDATA_2__DATA__SHIFT 0x0 21442#define SQ_THREAD_TRACE_USERDATA_2__DATA_MASK 0xFFFFFFFFL 21443//SQ_THREAD_TRACE_USERDATA_3 21444#define SQ_THREAD_TRACE_USERDATA_3__DATA__SHIFT 0x0 21445#define SQ_THREAD_TRACE_USERDATA_3__DATA_MASK 0xFFFFFFFFL 21446//SQC_CACHES 21447#define SQC_CACHES__TARGET_INST__SHIFT 0x0 21448#define SQC_CACHES__TARGET_DATA__SHIFT 0x1 21449#define SQC_CACHES__INVALIDATE__SHIFT 0x2 21450#define SQC_CACHES__WRITEBACK__SHIFT 0x3 21451#define SQC_CACHES__VOL__SHIFT 0x4 21452#define SQC_CACHES__COMPLETE__SHIFT 0x10 21453#define SQC_CACHES__TARGET_INST_MASK 0x00000001L 21454#define SQC_CACHES__TARGET_DATA_MASK 0x00000002L 21455#define SQC_CACHES__INVALIDATE_MASK 0x00000004L 21456#define SQC_CACHES__WRITEBACK_MASK 0x00000008L 21457#define SQC_CACHES__VOL_MASK 0x00000010L 21458#define SQC_CACHES__COMPLETE_MASK 0x00010000L 21459//SQC_WRITEBACK 21460#define SQC_WRITEBACK__DWB__SHIFT 0x0 21461#define SQC_WRITEBACK__DIRTY__SHIFT 0x1 21462#define SQC_WRITEBACK__DWB_MASK 0x00000001L 21463#define SQC_WRITEBACK__DIRTY_MASK 0x00000002L 21464//TA_CS_BC_BASE_ADDR 21465#define TA_CS_BC_BASE_ADDR__ADDRESS__SHIFT 0x0 21466#define TA_CS_BC_BASE_ADDR__ADDRESS_MASK 0xFFFFFFFFL 21467//TA_CS_BC_BASE_ADDR_HI 21468#define TA_CS_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0 21469#define TA_CS_BC_BASE_ADDR_HI__ADDRESS_MASK 0x000000FFL 21470//DB_OCCLUSION_COUNT0_LOW 21471#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW__SHIFT 0x0 21472#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW_MASK 0xFFFFFFFFL 21473//DB_OCCLUSION_COUNT0_HI 21474#define DB_OCCLUSION_COUNT0_HI__COUNT_HI__SHIFT 0x0 21475#define DB_OCCLUSION_COUNT0_HI__COUNT_HI_MASK 0x7FFFFFFFL 21476//DB_OCCLUSION_COUNT1_LOW 21477#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW__SHIFT 0x0 21478#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW_MASK 0xFFFFFFFFL 21479//DB_OCCLUSION_COUNT1_HI 21480#define DB_OCCLUSION_COUNT1_HI__COUNT_HI__SHIFT 0x0 21481#define DB_OCCLUSION_COUNT1_HI__COUNT_HI_MASK 0x7FFFFFFFL 21482//DB_OCCLUSION_COUNT2_LOW 21483#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW__SHIFT 0x0 21484#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW_MASK 0xFFFFFFFFL 21485//DB_OCCLUSION_COUNT2_HI 21486#define DB_OCCLUSION_COUNT2_HI__COUNT_HI__SHIFT 0x0 21487#define DB_OCCLUSION_COUNT2_HI__COUNT_HI_MASK 0x7FFFFFFFL 21488//DB_OCCLUSION_COUNT3_LOW 21489#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW__SHIFT 0x0 21490#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW_MASK 0xFFFFFFFFL 21491//DB_OCCLUSION_COUNT3_HI 21492#define DB_OCCLUSION_COUNT3_HI__COUNT_HI__SHIFT 0x0 21493#define DB_OCCLUSION_COUNT3_HI__COUNT_HI_MASK 0x7FFFFFFFL 21494//DB_ZPASS_COUNT_LOW 21495#define DB_ZPASS_COUNT_LOW__COUNT_LOW__SHIFT 0x0 21496#define DB_ZPASS_COUNT_LOW__COUNT_LOW_MASK 0xFFFFFFFFL 21497//DB_ZPASS_COUNT_HI 21498#define DB_ZPASS_COUNT_HI__COUNT_HI__SHIFT 0x0 21499#define DB_ZPASS_COUNT_HI__COUNT_HI_MASK 0x7FFFFFFFL 21500//GDS_RD_ADDR 21501#define GDS_RD_ADDR__READ_ADDR__SHIFT 0x0 21502#define GDS_RD_ADDR__READ_ADDR_MASK 0xFFFFFFFFL 21503//GDS_RD_DATA 21504#define GDS_RD_DATA__READ_DATA__SHIFT 0x0 21505#define GDS_RD_DATA__READ_DATA_MASK 0xFFFFFFFFL 21506//GDS_RD_BURST_ADDR 21507#define GDS_RD_BURST_ADDR__BURST_ADDR__SHIFT 0x0 21508#define GDS_RD_BURST_ADDR__BURST_ADDR_MASK 0xFFFFFFFFL 21509//GDS_RD_BURST_COUNT 21510#define GDS_RD_BURST_COUNT__BURST_COUNT__SHIFT 0x0 21511#define GDS_RD_BURST_COUNT__BURST_COUNT_MASK 0xFFFFFFFFL 21512//GDS_RD_BURST_DATA 21513#define GDS_RD_BURST_DATA__BURST_DATA__SHIFT 0x0 21514#define GDS_RD_BURST_DATA__BURST_DATA_MASK 0xFFFFFFFFL 21515//GDS_WR_ADDR 21516#define GDS_WR_ADDR__WRITE_ADDR__SHIFT 0x0 21517#define GDS_WR_ADDR__WRITE_ADDR_MASK 0xFFFFFFFFL 21518//GDS_WR_DATA 21519#define GDS_WR_DATA__WRITE_DATA__SHIFT 0x0 21520#define GDS_WR_DATA__WRITE_DATA_MASK 0xFFFFFFFFL 21521//GDS_WR_BURST_ADDR 21522#define GDS_WR_BURST_ADDR__WRITE_ADDR__SHIFT 0x0 21523#define GDS_WR_BURST_ADDR__WRITE_ADDR_MASK 0xFFFFFFFFL 21524//GDS_WR_BURST_DATA 21525#define GDS_WR_BURST_DATA__WRITE_DATA__SHIFT 0x0 21526#define GDS_WR_BURST_DATA__WRITE_DATA_MASK 0xFFFFFFFFL 21527//GDS_WRITE_COMPLETE 21528#define GDS_WRITE_COMPLETE__WRITE_COMPLETE__SHIFT 0x0 21529#define GDS_WRITE_COMPLETE__WRITE_COMPLETE_MASK 0xFFFFFFFFL 21530//GDS_ATOM_CNTL 21531#define GDS_ATOM_CNTL__AINC__SHIFT 0x0 21532#define GDS_ATOM_CNTL__UNUSED1__SHIFT 0x6 21533#define GDS_ATOM_CNTL__DMODE__SHIFT 0x8 21534#define GDS_ATOM_CNTL__UNUSED2__SHIFT 0xa 21535#define GDS_ATOM_CNTL__AINC_MASK 0x0000003FL 21536#define GDS_ATOM_CNTL__UNUSED1_MASK 0x000000C0L 21537#define GDS_ATOM_CNTL__DMODE_MASK 0x00000300L 21538#define GDS_ATOM_CNTL__UNUSED2_MASK 0xFFFFFC00L 21539//GDS_ATOM_COMPLETE 21540#define GDS_ATOM_COMPLETE__COMPLETE__SHIFT 0x0 21541#define GDS_ATOM_COMPLETE__UNUSED__SHIFT 0x1 21542#define GDS_ATOM_COMPLETE__COMPLETE_MASK 0x00000001L 21543#define GDS_ATOM_COMPLETE__UNUSED_MASK 0xFFFFFFFEL 21544//GDS_ATOM_BASE 21545#define GDS_ATOM_BASE__BASE__SHIFT 0x0 21546#define GDS_ATOM_BASE__UNUSED__SHIFT 0x10 21547#define GDS_ATOM_BASE__BASE_MASK 0x0000FFFFL 21548#define GDS_ATOM_BASE__UNUSED_MASK 0xFFFF0000L 21549//GDS_ATOM_SIZE 21550#define GDS_ATOM_SIZE__SIZE__SHIFT 0x0 21551#define GDS_ATOM_SIZE__UNUSED__SHIFT 0x10 21552#define GDS_ATOM_SIZE__SIZE_MASK 0x0000FFFFL 21553#define GDS_ATOM_SIZE__UNUSED_MASK 0xFFFF0000L 21554//GDS_ATOM_OFFSET0 21555#define GDS_ATOM_OFFSET0__OFFSET0__SHIFT 0x0 21556#define GDS_ATOM_OFFSET0__UNUSED__SHIFT 0x8 21557#define GDS_ATOM_OFFSET0__OFFSET0_MASK 0x000000FFL 21558#define GDS_ATOM_OFFSET0__UNUSED_MASK 0xFFFFFF00L 21559//GDS_ATOM_OFFSET1 21560#define GDS_ATOM_OFFSET1__OFFSET1__SHIFT 0x0 21561#define GDS_ATOM_OFFSET1__UNUSED__SHIFT 0x8 21562#define GDS_ATOM_OFFSET1__OFFSET1_MASK 0x000000FFL 21563#define GDS_ATOM_OFFSET1__UNUSED_MASK 0xFFFFFF00L 21564//GDS_ATOM_DST 21565#define GDS_ATOM_DST__DST__SHIFT 0x0 21566#define GDS_ATOM_DST__DST_MASK 0xFFFFFFFFL 21567//GDS_ATOM_OP 21568#define GDS_ATOM_OP__OP__SHIFT 0x0 21569#define GDS_ATOM_OP__UNUSED__SHIFT 0x8 21570#define GDS_ATOM_OP__OP_MASK 0x000000FFL 21571#define GDS_ATOM_OP__UNUSED_MASK 0xFFFFFF00L 21572//GDS_ATOM_SRC0 21573#define GDS_ATOM_SRC0__DATA__SHIFT 0x0 21574#define GDS_ATOM_SRC0__DATA_MASK 0xFFFFFFFFL 21575//GDS_ATOM_SRC0_U 21576#define GDS_ATOM_SRC0_U__DATA__SHIFT 0x0 21577#define GDS_ATOM_SRC0_U__DATA_MASK 0xFFFFFFFFL 21578//GDS_ATOM_SRC1 21579#define GDS_ATOM_SRC1__DATA__SHIFT 0x0 21580#define GDS_ATOM_SRC1__DATA_MASK 0xFFFFFFFFL 21581//GDS_ATOM_SRC1_U 21582#define GDS_ATOM_SRC1_U__DATA__SHIFT 0x0 21583#define GDS_ATOM_SRC1_U__DATA_MASK 0xFFFFFFFFL 21584//GDS_ATOM_READ0 21585#define GDS_ATOM_READ0__DATA__SHIFT 0x0 21586#define GDS_ATOM_READ0__DATA_MASK 0xFFFFFFFFL 21587//GDS_ATOM_READ0_U 21588#define GDS_ATOM_READ0_U__DATA__SHIFT 0x0 21589#define GDS_ATOM_READ0_U__DATA_MASK 0xFFFFFFFFL 21590//GDS_ATOM_READ1 21591#define GDS_ATOM_READ1__DATA__SHIFT 0x0 21592#define GDS_ATOM_READ1__DATA_MASK 0xFFFFFFFFL 21593//GDS_ATOM_READ1_U 21594#define GDS_ATOM_READ1_U__DATA__SHIFT 0x0 21595#define GDS_ATOM_READ1_U__DATA_MASK 0xFFFFFFFFL 21596//GDS_GWS_RESOURCE_CNTL 21597#define GDS_GWS_RESOURCE_CNTL__INDEX__SHIFT 0x0 21598#define GDS_GWS_RESOURCE_CNTL__UNUSED__SHIFT 0x6 21599#define GDS_GWS_RESOURCE_CNTL__INDEX_MASK 0x0000003FL 21600#define GDS_GWS_RESOURCE_CNTL__UNUSED_MASK 0xFFFFFFC0L 21601//GDS_GWS_RESOURCE 21602#define GDS_GWS_RESOURCE__FLAG__SHIFT 0x0 21603#define GDS_GWS_RESOURCE__COUNTER__SHIFT 0x1 21604#define GDS_GWS_RESOURCE__TYPE__SHIFT 0xd 21605#define GDS_GWS_RESOURCE__DED__SHIFT 0xe 21606#define GDS_GWS_RESOURCE__RELEASE_ALL__SHIFT 0xf 21607#define GDS_GWS_RESOURCE__HEAD_QUEUE__SHIFT 0x10 21608#define GDS_GWS_RESOURCE__HEAD_VALID__SHIFT 0x1c 21609#define GDS_GWS_RESOURCE__HEAD_FLAG__SHIFT 0x1d 21610#define GDS_GWS_RESOURCE__HALTED__SHIFT 0x1e 21611#define GDS_GWS_RESOURCE__UNUSED1__SHIFT 0x1f 21612#define GDS_GWS_RESOURCE__FLAG_MASK 0x00000001L 21613#define GDS_GWS_RESOURCE__COUNTER_MASK 0x00001FFEL 21614#define GDS_GWS_RESOURCE__TYPE_MASK 0x00002000L 21615#define GDS_GWS_RESOURCE__DED_MASK 0x00004000L 21616#define GDS_GWS_RESOURCE__RELEASE_ALL_MASK 0x00008000L 21617#define GDS_GWS_RESOURCE__HEAD_QUEUE_MASK 0x0FFF0000L 21618#define GDS_GWS_RESOURCE__HEAD_VALID_MASK 0x10000000L 21619#define GDS_GWS_RESOURCE__HEAD_FLAG_MASK 0x20000000L 21620#define GDS_GWS_RESOURCE__HALTED_MASK 0x40000000L 21621#define GDS_GWS_RESOURCE__UNUSED1_MASK 0x80000000L 21622//GDS_GWS_RESOURCE_CNT 21623#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT__SHIFT 0x0 21624#define GDS_GWS_RESOURCE_CNT__UNUSED__SHIFT 0x10 21625#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT_MASK 0x0000FFFFL 21626#define GDS_GWS_RESOURCE_CNT__UNUSED_MASK 0xFFFF0000L 21627//GDS_OA_CNTL 21628#define GDS_OA_CNTL__INDEX__SHIFT 0x0 21629#define GDS_OA_CNTL__UNUSED__SHIFT 0x4 21630#define GDS_OA_CNTL__INDEX_MASK 0x0000000FL 21631#define GDS_OA_CNTL__UNUSED_MASK 0xFFFFFFF0L 21632//GDS_OA_COUNTER 21633#define GDS_OA_COUNTER__SPACE_AVAILABLE__SHIFT 0x0 21634#define GDS_OA_COUNTER__SPACE_AVAILABLE_MASK 0xFFFFFFFFL 21635//GDS_OA_ADDRESS 21636#define GDS_OA_ADDRESS__DS_ADDRESS__SHIFT 0x0 21637#define GDS_OA_ADDRESS__CRAWLER__SHIFT 0x10 21638#define GDS_OA_ADDRESS__CRAWLER_TYPE__SHIFT 0x14 21639#define GDS_OA_ADDRESS__UNUSED__SHIFT 0x16 21640#define GDS_OA_ADDRESS__NO_ALLOC__SHIFT 0x1e 21641#define GDS_OA_ADDRESS__ENABLE__SHIFT 0x1f 21642#define GDS_OA_ADDRESS__DS_ADDRESS_MASK 0x0000FFFFL 21643#define GDS_OA_ADDRESS__CRAWLER_MASK 0x000F0000L 21644#define GDS_OA_ADDRESS__CRAWLER_TYPE_MASK 0x00300000L 21645#define GDS_OA_ADDRESS__UNUSED_MASK 0x3FC00000L 21646#define GDS_OA_ADDRESS__NO_ALLOC_MASK 0x40000000L 21647#define GDS_OA_ADDRESS__ENABLE_MASK 0x80000000L 21648//GDS_OA_INCDEC 21649#define GDS_OA_INCDEC__VALUE__SHIFT 0x0 21650#define GDS_OA_INCDEC__INCDEC__SHIFT 0x1f 21651#define GDS_OA_INCDEC__VALUE_MASK 0x7FFFFFFFL 21652#define GDS_OA_INCDEC__INCDEC_MASK 0x80000000L 21653//GDS_OA_RING_SIZE 21654#define GDS_OA_RING_SIZE__RING_SIZE__SHIFT 0x0 21655#define GDS_OA_RING_SIZE__RING_SIZE_MASK 0xFFFFFFFFL 21656//SPI_CONFIG_CNTL 21657#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY__SHIFT 0x0 21658#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER__SHIFT 0x15 21659#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS__SHIFT 0x18 21660#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS__SHIFT 0x19 21661#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET__SHIFT 0x1a 21662#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL__SHIFT 0x1b 21663#define SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA__SHIFT 0x1c 21664#define SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA__SHIFT 0x1d 21665#define SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL__SHIFT 0x1e 21666#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY_MASK 0x001FFFFFL 21667#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER_MASK 0x00E00000L 21668#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS_MASK 0x01000000L 21669#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS_MASK 0x02000000L 21670#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET_MASK 0x04000000L 21671#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL_MASK 0x08000000L 21672#define SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA_MASK 0x10000000L 21673#define SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA_MASK 0x20000000L 21674#define SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL_MASK 0xC0000000L 21675//SPI_CONFIG_CNTL_1 21676#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT 0x0 21677#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW__SHIFT 0x4 21678#define SPI_CONFIG_CNTL_1__BATON_RESET_DISABLE__SHIFT 0x5 21679#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE__SHIFT 0x6 21680#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT__SHIFT 0x7 21681#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE__SHIFT 0x8 21682#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE__SHIFT 0x9 21683#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT__SHIFT 0xa 21684#define SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE__SHIFT 0xe 21685#define SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE__SHIFT 0xf 21686#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE__SHIFT 0x10 21687#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_MASK 0x0000000FL 21688#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK 0x00000010L 21689#define SPI_CONFIG_CNTL_1__BATON_RESET_DISABLE_MASK 0x00000020L 21690#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK 0x00000040L 21691#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT_MASK 0x00000080L 21692#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE_MASK 0x00000100L 21693#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE_MASK 0x00000200L 21694#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT_MASK 0x00003C00L 21695#define SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE_MASK 0x00004000L 21696#define SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE_MASK 0x00008000L 21697#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE_MASK 0xFFFF0000L 21698//SPI_CONFIG_CNTL_2 21699#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD__SHIFT 0x0 21700#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD__SHIFT 0x4 21701#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD_MASK 0x0000000FL 21702#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD_MASK 0x000000F0L 21703 21704 21705// addressBlock: gc_perfddec 21706//CPG_PERFCOUNTER1_LO 21707#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 21708#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 21709//CPG_PERFCOUNTER1_HI 21710#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 21711#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 21712//CPG_PERFCOUNTER0_LO 21713#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 21714#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 21715//CPG_PERFCOUNTER0_HI 21716#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 21717#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 21718//CPC_PERFCOUNTER1_LO 21719#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 21720#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 21721//CPC_PERFCOUNTER1_HI 21722#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 21723#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 21724//CPC_PERFCOUNTER0_LO 21725#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 21726#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 21727//CPC_PERFCOUNTER0_HI 21728#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 21729#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 21730//CPF_PERFCOUNTER1_LO 21731#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 21732#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 21733//CPF_PERFCOUNTER1_HI 21734#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 21735#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 21736//CPF_PERFCOUNTER0_LO 21737#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 21738#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 21739//CPF_PERFCOUNTER0_HI 21740#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 21741#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 21742//CPF_LATENCY_STATS_DATA 21743#define CPF_LATENCY_STATS_DATA__DATA__SHIFT 0x0 21744#define CPF_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL 21745//CPG_LATENCY_STATS_DATA 21746#define CPG_LATENCY_STATS_DATA__DATA__SHIFT 0x0 21747#define CPG_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL 21748//CPC_LATENCY_STATS_DATA 21749#define CPC_LATENCY_STATS_DATA__DATA__SHIFT 0x0 21750#define CPC_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL 21751//GRBM_PERFCOUNTER0_LO 21752#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 21753#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 21754//GRBM_PERFCOUNTER0_HI 21755#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 21756#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 21757//GRBM_PERFCOUNTER1_LO 21758#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 21759#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 21760//GRBM_PERFCOUNTER1_HI 21761#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 21762#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 21763//GRBM_SE0_PERFCOUNTER_LO 21764#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 21765#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 21766//GRBM_SE0_PERFCOUNTER_HI 21767#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 21768#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 21769//GRBM_SE1_PERFCOUNTER_LO 21770#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 21771#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 21772//GRBM_SE1_PERFCOUNTER_HI 21773#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 21774#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 21775//GRBM_SE2_PERFCOUNTER_LO 21776#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 21777#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 21778//GRBM_SE2_PERFCOUNTER_HI 21779#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 21780#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 21781//GRBM_SE3_PERFCOUNTER_LO 21782#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 21783#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 21784//GRBM_SE3_PERFCOUNTER_HI 21785#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 21786#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 21787//WD_PERFCOUNTER0_LO 21788#define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 21789#define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 21790//WD_PERFCOUNTER0_HI 21791#define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 21792#define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 21793//WD_PERFCOUNTER1_LO 21794#define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 21795#define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 21796//WD_PERFCOUNTER1_HI 21797#define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 21798#define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 21799//WD_PERFCOUNTER2_LO 21800#define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 21801#define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 21802//WD_PERFCOUNTER2_HI 21803#define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 21804#define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 21805//WD_PERFCOUNTER3_LO 21806#define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 21807#define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 21808//WD_PERFCOUNTER3_HI 21809#define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 21810#define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 21811//IA_PERFCOUNTER0_LO 21812#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 21813#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 21814//IA_PERFCOUNTER0_HI 21815#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 21816#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 21817//IA_PERFCOUNTER1_LO 21818#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 21819#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 21820//IA_PERFCOUNTER1_HI 21821#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 21822#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 21823//IA_PERFCOUNTER2_LO 21824#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 21825#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 21826//IA_PERFCOUNTER2_HI 21827#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 21828#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 21829//IA_PERFCOUNTER3_LO 21830#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 21831#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 21832//IA_PERFCOUNTER3_HI 21833#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 21834#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 21835//VGT_PERFCOUNTER0_LO 21836#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 21837#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 21838//VGT_PERFCOUNTER0_HI 21839#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 21840#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 21841//VGT_PERFCOUNTER1_LO 21842#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 21843#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 21844//VGT_PERFCOUNTER1_HI 21845#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 21846#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 21847//VGT_PERFCOUNTER2_LO 21848#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 21849#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 21850//VGT_PERFCOUNTER2_HI 21851#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 21852#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 21853//VGT_PERFCOUNTER3_LO 21854#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 21855#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 21856//VGT_PERFCOUNTER3_HI 21857#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 21858#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 21859//PA_SU_PERFCOUNTER0_LO 21860#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 21861#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 21862//PA_SU_PERFCOUNTER0_HI 21863#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 21864#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL 21865//PA_SU_PERFCOUNTER1_LO 21866#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 21867#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 21868//PA_SU_PERFCOUNTER1_HI 21869#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 21870#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL 21871//PA_SU_PERFCOUNTER2_LO 21872#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 21873#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 21874//PA_SU_PERFCOUNTER2_HI 21875#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 21876#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL 21877//PA_SU_PERFCOUNTER3_LO 21878#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 21879#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 21880//PA_SU_PERFCOUNTER3_HI 21881#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 21882#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0x0000FFFFL 21883//PA_SC_PERFCOUNTER0_LO 21884#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 21885#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 21886//PA_SC_PERFCOUNTER0_HI 21887#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 21888#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 21889//PA_SC_PERFCOUNTER1_LO 21890#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 21891#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 21892//PA_SC_PERFCOUNTER1_HI 21893#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 21894#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 21895//PA_SC_PERFCOUNTER2_LO 21896#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 21897#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 21898//PA_SC_PERFCOUNTER2_HI 21899#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 21900#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 21901//PA_SC_PERFCOUNTER3_LO 21902#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 21903#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 21904//PA_SC_PERFCOUNTER3_HI 21905#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 21906#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 21907//PA_SC_PERFCOUNTER4_LO 21908#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 21909#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 21910//PA_SC_PERFCOUNTER4_HI 21911#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 21912#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 21913//PA_SC_PERFCOUNTER5_LO 21914#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 21915#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 21916//PA_SC_PERFCOUNTER5_HI 21917#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 21918#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 21919//PA_SC_PERFCOUNTER6_LO 21920#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0 21921#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 21922//PA_SC_PERFCOUNTER6_HI 21923#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0 21924#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 21925//PA_SC_PERFCOUNTER7_LO 21926#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0 21927#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 21928//PA_SC_PERFCOUNTER7_HI 21929#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0 21930#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 21931//SPI_PERFCOUNTER0_HI 21932#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 21933#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 21934//SPI_PERFCOUNTER0_LO 21935#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 21936#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 21937//SPI_PERFCOUNTER1_HI 21938#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 21939#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 21940//SPI_PERFCOUNTER1_LO 21941#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 21942#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 21943//SPI_PERFCOUNTER2_HI 21944#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 21945#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 21946//SPI_PERFCOUNTER2_LO 21947#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 21948#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 21949//SPI_PERFCOUNTER3_HI 21950#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 21951#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 21952//SPI_PERFCOUNTER3_LO 21953#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 21954#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 21955//SPI_PERFCOUNTER4_HI 21956#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 21957#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 21958//SPI_PERFCOUNTER4_LO 21959#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 21960#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 21961//SPI_PERFCOUNTER5_HI 21962#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 21963#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 21964//SPI_PERFCOUNTER5_LO 21965#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 21966#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 21967//SQ_PERFCOUNTER0_LO 21968#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 21969#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 21970//SQ_PERFCOUNTER0_HI 21971#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 21972#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 21973//SQ_PERFCOUNTER1_LO 21974#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 21975#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 21976//SQ_PERFCOUNTER1_HI 21977#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 21978#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 21979//SQ_PERFCOUNTER2_LO 21980#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 21981#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 21982//SQ_PERFCOUNTER2_HI 21983#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 21984#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 21985//SQ_PERFCOUNTER3_LO 21986#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 21987#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 21988//SQ_PERFCOUNTER3_HI 21989#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 21990#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 21991//SQ_PERFCOUNTER4_LO 21992#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 21993#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 21994//SQ_PERFCOUNTER4_HI 21995#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 21996#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 21997//SQ_PERFCOUNTER5_LO 21998#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 21999#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 22000//SQ_PERFCOUNTER5_HI
22001#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 22002#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 22003//SQ_PERFCOUNTER6_LO 22004#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0 22005#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 22006//SQ_PERFCOUNTER6_HI 22007#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0 22008#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 22009//SQ_PERFCOUNTER7_LO 22010#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0 22011#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 22012//SQ_PERFCOUNTER7_HI 22013#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0 22014#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 22015//SQ_PERFCOUNTER8_LO 22016#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO__SHIFT 0x0 22017#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 22018//SQ_PERFCOUNTER8_HI 22019#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT 0x0 22020#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 22021//SQ_PERFCOUNTER9_LO 22022#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO__SHIFT 0x0 22023#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 22024//SQ_PERFCOUNTER9_HI 22025#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT 0x0 22026#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 22027//SQ_PERFCOUNTER10_LO 22028#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO__SHIFT 0x0 22029#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 22030//SQ_PERFCOUNTER10_HI 22031#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT 0x0 22032#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 22033//SQ_PERFCOUNTER11_LO 22034#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO__SHIFT 0x0 22035#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 22036//SQ_PERFCOUNTER11_HI 22037#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT 0x0 22038#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 22039//SQ_PERFCOUNTER12_LO 22040#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO__SHIFT 0x0 22041#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 22042//SQ_PERFCOUNTER12_HI 22043#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI__SHIFT 0x0 22044#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 22045//SQ_PERFCOUNTER13_LO 22046#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO__SHIFT 0x0 22047#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 22048//SQ_PERFCOUNTER13_HI 22049#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI__SHIFT 0x0 22050#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 22051//SQ_PERFCOUNTER14_LO 22052#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO__SHIFT 0x0 22053#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 22054//SQ_PERFCOUNTER14_HI 22055#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI__SHIFT 0x0 22056#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 22057//SQ_PERFCOUNTER15_LO 22058#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO__SHIFT 0x0 22059#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 22060//SQ_PERFCOUNTER15_HI 22061#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI__SHIFT 0x0 22062#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 22063//SX_PERFCOUNTER0_LO 22064#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 22065#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 22066//SX_PERFCOUNTER0_HI 22067#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 22068#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 22069//SX_PERFCOUNTER1_LO 22070#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 22071#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 22072//SX_PERFCOUNTER1_HI 22073#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 22074#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 22075//SX_PERFCOUNTER2_LO 22076#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 22077#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 22078//SX_PERFCOUNTER2_HI 22079#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 22080#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 22081//SX_PERFCOUNTER3_LO 22082#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 22083#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 22084//SX_PERFCOUNTER3_HI 22085#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 22086#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 22087//GDS_PERFCOUNTER0_LO 22088#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 22089#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 22090//GDS_PERFCOUNTER0_HI 22091#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 22092#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 22093//GDS_PERFCOUNTER1_LO 22094#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 22095#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 22096//GDS_PERFCOUNTER1_HI 22097#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 22098#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 22099//GDS_PERFCOUNTER2_LO 22100#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 22101#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 22102//GDS_PERFCOUNTER2_HI 22103#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 22104#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 22105//GDS_PERFCOUNTER3_LO 22106#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 22107#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 22108//GDS_PERFCOUNTER3_HI 22109#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 22110#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 22111//TA_PERFCOUNTER0_LO 22112#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 22113#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 22114//TA_PERFCOUNTER0_HI 22115#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 22116#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 22117//TA_PERFCOUNTER1_LO 22118#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 22119#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 22120//TA_PERFCOUNTER1_HI 22121#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 22122#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 22123//TD_PERFCOUNTER0_LO 22124#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 22125#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 22126//TD_PERFCOUNTER0_HI 22127#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 22128#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 22129//TD_PERFCOUNTER1_LO 22130#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 22131#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 22132//TD_PERFCOUNTER1_HI 22133#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 22134#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 22135//TCP_PERFCOUNTER0_LO 22136#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 22137#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 22138//TCP_PERFCOUNTER0_HI 22139#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 22140#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 22141//TCP_PERFCOUNTER1_LO 22142#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 22143#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 22144//TCP_PERFCOUNTER1_HI 22145#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 22146#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 22147//TCP_PERFCOUNTER2_LO 22148#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 22149#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 22150//TCP_PERFCOUNTER2_HI 22151#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 22152#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 22153//TCP_PERFCOUNTER3_LO 22154#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 22155#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 22156//TCP_PERFCOUNTER3_HI 22157#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 22158#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 22159//TCC_PERFCOUNTER0_LO 22160#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 22161#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 22162//TCC_PERFCOUNTER0_HI 22163#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 22164#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 22165//TCC_PERFCOUNTER1_LO 22166#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 22167#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 22168//TCC_PERFCOUNTER1_HI 22169#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 22170#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 22171//TCC_PERFCOUNTER2_LO 22172#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 22173#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 22174//TCC_PERFCOUNTER2_HI 22175#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 22176#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 22177//TCC_PERFCOUNTER3_LO 22178#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 22179#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 22180//TCC_PERFCOUNTER3_HI 22181#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 22182#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 22183//TCA_PERFCOUNTER0_LO 22184#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 22185#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 22186//TCA_PERFCOUNTER0_HI 22187#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 22188#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 22189//TCA_PERFCOUNTER1_LO 22190#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 22191#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 22192//TCA_PERFCOUNTER1_HI 22193#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 22194#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 22195//TCA_PERFCOUNTER2_LO 22196#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 22197#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 22198//TCA_PERFCOUNTER2_HI 22199#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 22200#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 22201//TCA_PERFCOUNTER3_LO 22202#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 22203#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 22204//TCA_PERFCOUNTER3_HI 22205#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 22206#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 22207//CB_PERFCOUNTER0_LO 22208#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 22209#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 22210//CB_PERFCOUNTER0_HI 22211#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 22212#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 22213//CB_PERFCOUNTER1_LO 22214#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 22215#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 22216//CB_PERFCOUNTER1_HI 22217#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 22218#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 22219//CB_PERFCOUNTER2_LO 22220#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 22221#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 22222//CB_PERFCOUNTER2_HI 22223#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 22224#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 22225//CB_PERFCOUNTER3_LO 22226#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 22227#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 22228//CB_PERFCOUNTER3_HI 22229#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 22230#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 22231//DB_PERFCOUNTER0_LO 22232#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 22233#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 22234//DB_PERFCOUNTER0_HI 22235#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 22236#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 22237//DB_PERFCOUNTER1_LO 22238#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 22239#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 22240//DB_PERFCOUNTER1_HI 22241#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 22242#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 22243//DB_PERFCOUNTER2_LO 22244#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 22245#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 22246//DB_PERFCOUNTER2_HI 22247#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 22248#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 22249//DB_PERFCOUNTER3_LO 22250#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 22251#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 22252//DB_PERFCOUNTER3_HI 22253#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 22254#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 22255//RLC_PERFCOUNTER0_LO 22256#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 22257#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 22258//RLC_PERFCOUNTER0_HI 22259#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 22260#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 22261//RLC_PERFCOUNTER1_LO 22262#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 22263#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 22264//RLC_PERFCOUNTER1_HI 22265#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 22266#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 22267//RMI_PERFCOUNTER0_LO 22268#define RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 22269#define RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 22270//RMI_PERFCOUNTER0_HI 22271#define RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 22272#define RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 22273//RMI_PERFCOUNTER1_LO 22274#define RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 22275#define RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 22276//RMI_PERFCOUNTER1_HI 22277#define RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 22278#define RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 22279//RMI_PERFCOUNTER2_LO 22280#define RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 22281#define RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 22282//RMI_PERFCOUNTER2_HI 22283#define RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 22284#define RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 22285//RMI_PERFCOUNTER3_LO 22286#define RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 22287#define RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL 22288//RMI_PERFCOUNTER3_HI 22289#define RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 22290#define RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL 22291 22292 22293// addressBlock: gc_utcl2_atcl2pfcntrdec 22294//ATC_L2_PERFCOUNTER_LO 22295#define ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 22296#define ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 22297//ATC_L2_PERFCOUNTER_HI 22298#define ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 22299#define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 22300#define ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 22301#define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 22302 22303 22304// addressBlock: gc_utcl2_vml2prdec 22305//MC_VM_L2_PERFCOUNTER_LO 22306#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 22307#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 22308//MC_VM_L2_PERFCOUNTER_HI 22309#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 22310#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 22311#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 22312#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 22313 22314 22315// addressBlock: gc_perfsdec 22316//CPG_PERFCOUNTER1_SELECT 22317#define CPG_PERFCOUNTER1_SELECT__CNTR_SEL0__SHIFT 0x0 22318#define CPG_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT 0xa 22319#define CPG_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 22320#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT 0x18 22321#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT 0x1c 22322#define CPG_PERFCOUNTER1_SELECT__CNTR_SEL0_MASK 0x000003FFL 22323#define CPG_PERFCOUNTER1_SELECT__CNTR_SEL1_MASK 0x000FFC00L 22324#define CPG_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L 22325#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK 0x0F000000L 22326#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK 0xF0000000L 22327//CPG_PERFCOUNTER0_SELECT1 22328#define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL2__SHIFT 0x0 22329#define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT 0xa 22330#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18 22331#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c 22332#define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL2_MASK 0x000003FFL 22333#define CPG_PERFCOUNTER0_SELECT1__CNTR_SEL3_MASK 0x000FFC00L 22334#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L 22335#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L 22336//CPG_PERFCOUNTER0_SELECT 22337#define CPG_PERFCOUNTER0_SELECT__CNTR_SEL0__SHIFT 0x0 22338#define CPG_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT 0xa 22339#define CPG_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 22340#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18 22341#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c 22342#define CPG_PERFCOUNTER0_SELECT__CNTR_SEL0_MASK 0x000003FFL 22343#define CPG_PERFCOUNTER0_SELECT__CNTR_SEL1_MASK 0x000FFC00L 22344#define CPG_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L 22345#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L 22346#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L 22347//CPC_PERFCOUNTER1_SELECT 22348#define CPC_PERFCOUNTER1_SELECT__CNTR_SEL0__SHIFT 0x0 22349#define CPC_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT 0xa 22350#define CPC_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 22351#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT 0x18 22352#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT 0x1c 22353#define CPC_PERFCOUNTER1_SELECT__CNTR_SEL0_MASK 0x000003FFL 22354#define CPC_PERFCOUNTER1_SELECT__CNTR_SEL1_MASK 0x000FFC00L 22355#define CPC_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L 22356#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK 0x0F000000L 22357#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK 0xF0000000L 22358//CPC_PERFCOUNTER0_SELECT1 22359#define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL2__SHIFT 0x0 22360#define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT 0xa 22361#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18 22362#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c 22363#define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL2_MASK 0x000003FFL 22364#define CPC_PERFCOUNTER0_SELECT1__CNTR_SEL3_MASK 0x000FFC00L 22365#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L 22366#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L 22367//CPF_PERFCOUNTER1_SELECT 22368#define CPF_PERFCOUNTER1_SELECT__CNTR_SEL0__SHIFT 0x0 22369#define CPF_PERFCOUNTER1_SELECT__CNTR_SEL1__SHIFT 0xa 22370#define CPF_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 22371#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT 0x18 22372#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT 0x1c 22373#define CPF_PERFCOUNTER1_SELECT__CNTR_SEL0_MASK 0x000003FFL 22374#define CPF_PERFCOUNTER1_SELECT__CNTR_SEL1_MASK 0x000FFC00L 22375#define CPF_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L 22376#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK 0x0F000000L 22377#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK 0xF0000000L 22378//CPF_PERFCOUNTER0_SELECT1 22379#define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL2__SHIFT 0x0 22380#define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL3__SHIFT 0xa 22381#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18 22382#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c 22383#define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL2_MASK 0x000003FFL 22384#define CPF_PERFCOUNTER0_SELECT1__CNTR_SEL3_MASK 0x000FFC00L 22385#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L 22386#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L 22387//CPF_PERFCOUNTER0_SELECT 22388#define CPF_PERFCOUNTER0_SELECT__CNTR_SEL0__SHIFT 0x0 22389#define CPF_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT 0xa 22390#define CPF_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 22391#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18 22392#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c 22393#define CPF_PERFCOUNTER0_SELECT__CNTR_SEL0_MASK 0x000003FFL 22394#define CPF_PERFCOUNTER0_SELECT__CNTR_SEL1_MASK 0x000FFC00L 22395#define CPF_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L 22396#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L 22397#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L 22398//CP_PERFMON_CNTL 22399#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 22400#define CP_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT 0x4 22401#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8 22402#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa 22403#define CP_PERFMON_CNTL__PERFMON_STATE_MASK 0x0000000FL 22404#define CP_PERFMON_CNTL__SPM_PERFMON_STATE_MASK 0x000000F0L 22405#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x00000300L 22406#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L 22407//CPC_PERFCOUNTER0_SELECT 22408#define CPC_PERFCOUNTER0_SELECT__CNTR_SEL0__SHIFT 0x0 22409#define CPC_PERFCOUNTER0_SELECT__CNTR_SEL1__SHIFT 0xa 22410#define CPC_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 22411#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18 22412#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c 22413#define CPC_PERFCOUNTER0_SELECT__CNTR_SEL0_MASK 0x000003FFL 22414#define CPC_PERFCOUNTER0_SELECT__CNTR_SEL1_MASK 0x000FFC00L 22415#define CPC_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L 22416#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L 22417#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L 22418//CPF_TC_PERF_COUNTER_WINDOW_SELECT 22419#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT 0x0 22420#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT 0x1e 22421#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT 0x1f 22422#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK 0x00000007L 22423#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK 0x40000000L 22424#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK 0x80000000L 22425//CPG_TC_PERF_COUNTER_WINDOW_SELECT 22426#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT 0x0 22427#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT 0x1e 22428#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT 0x1f 22429#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK 0x0000001FL 22430#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK 0x40000000L 22431#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK 0x80000000L 22432//CPF_LATENCY_STATS_SELECT 22433#define CPF_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0 22434#define CPF_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e 22435#define CPF_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f 22436#define CPF_LATENCY_STATS_SELECT__INDEX_MASK 0x0000000FL 22437#define CPF_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L 22438#define CPF_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L 22439//CPG_LATENCY_STATS_SELECT 22440#define CPG_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0 22441#define CPG_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e 22442#define CPG_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f 22443#define CPG_LATENCY_STATS_SELECT__INDEX_MASK 0x0000001FL 22444#define CPG_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L 22445#define CPG_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L 22446//CPC_LATENCY_STATS_SELECT 22447#define CPC_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0 22448#define CPC_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e 22449#define CPC_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f 22450#define CPC_LATENCY_STATS_SELECT__INDEX_MASK 0x00000007L 22451#define CPC_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L 22452#define CPC_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L 22453//CP_DRAW_OBJECT 22454#define CP_DRAW_OBJECT__OBJECT__SHIFT 0x0 22455#define CP_DRAW_OBJECT__OBJECT_MASK 0xFFFFFFFFL 22456//CP_DRAW_OBJECT_COUNTER 22457#define CP_DRAW_OBJECT_COUNTER__COUNT__SHIFT 0x0 22458#define CP_DRAW_OBJECT_COUNTER__COUNT_MASK 0x0000FFFFL 22459//CP_DRAW_WINDOW_MASK_HI 22460#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI__SHIFT 0x0 22461#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI_MASK 0xFFFFFFFFL 22462//CP_DRAW_WINDOW_HI 22463#define CP_DRAW_WINDOW_HI__WINDOW_HI__SHIFT 0x0 22464#define CP_DRAW_WINDOW_HI__WINDOW_HI_MASK 0xFFFFFFFFL 22465//CP_DRAW_WINDOW_LO 22466#define CP_DRAW_WINDOW_LO__MIN__SHIFT 0x0 22467#define CP_DRAW_WINDOW_LO__MAX__SHIFT 0x10 22468#define CP_DRAW_WINDOW_LO__MIN_MASK 0x0000FFFFL 22469#define CP_DRAW_WINDOW_LO__MAX_MASK 0xFFFF0000L 22470//CP_DRAW_WINDOW_CNTL 22471#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX__SHIFT 0x0 22472#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN__SHIFT 0x1 22473#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI__SHIFT 0x2 22474#define CP_DRAW_WINDOW_CNTL__MODE__SHIFT 0x8 22475#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX_MASK 0x00000001L 22476#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN_MASK 0x00000002L 22477#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI_MASK 0x00000004L 22478#define CP_DRAW_WINDOW_CNTL__MODE_MASK 0x00000100L 22479//GRBM_PERFCOUNTER0_SELECT 22480#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 22481#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa 22482#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb 22483#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc 22484#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd 22485#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe 22486#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10 22487#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11 22488#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12 22489#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13 22490#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14 22491#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15 22492#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16 22493#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17 22494#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18 22495#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19 22496#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a 22497#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b 22498#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c 22499#define GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT 0x1d 22500#define GRBM_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT 0x1e 22501#define GRBM_PERFCOUNTER0_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x1f 22502#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x0000003FL 22503#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L 22504#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L 22505#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00001000L 22506#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L 22507#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L 22508#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00010000L 22509#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00020000L 22510#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00040000L 22511#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x00080000L 22512#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L 22513#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L 22514#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x00400000L 22515#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x00800000L 22516#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x01000000L 22517#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L 22518#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L 22519#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x08000000L 22520#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000L 22521#define GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK 0x20000000L 22522#define GRBM_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK 0x40000000L 22523#define GRBM_PERFCOUNTER0_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x80000000L 22524//GRBM_PERFCOUNTER1_SELECT 22525#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 22526#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa 22527#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb 22528#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc 22529#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd 22530#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe 22531#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10 22532#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11 22533#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12 22534#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13 22535#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14 22536#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15 22537#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16 22538#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17 22539#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18 22540#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19 22541#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a 22542#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b 22543#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c 22544#define GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT 0x1d 22545#define GRBM_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT 0x1e 22546#define GRBM_PERFCOUNTER1_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x1f 22547#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x0000003FL 22548#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L 22549#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L 22550#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00001000L 22551#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L 22552#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L 22553#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00010000L 22554#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00020000L 22555#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00040000L 22556#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x00080000L 22557#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L 22558#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L 22559#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x00400000L 22560#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x00800000L 22561#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x01000000L 22562#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L 22563#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L 22564#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x08000000L 22565#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000L 22566#define GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK 0x20000000L 22567#define GRBM_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK 0x40000000L 22568#define GRBM_PERFCOUNTER1_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x80000000L 22569//GRBM_SE0_PERFCOUNTER_SELECT 22570#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 22571#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa 22572#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb 22573#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc 22574#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd 22575#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf 22576#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 22577#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 22578#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 22579#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13 22580#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 22581#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 22582#define GRBM_SE0_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16 22583#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL 22584#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L 22585#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L 22586#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L 22587#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L 22588#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L 22589#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L 22590#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L 22591#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L 22592#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L 22593#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L 22594#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L 22595#define GRBM_SE0_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L 22596//GRBM_SE1_PERFCOUNTER_SELECT 22597#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 22598#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa 22599#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb 22600#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc 22601#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd 22602#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf 22603#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 22604#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 22605#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 22606#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13 22607#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 22608#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 22609#define GRBM_SE1_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16 22610#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL 22611#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L 22612#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L 22613#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L 22614#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L 22615#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L 22616#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L 22617#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L 22618#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L 22619#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L 22620#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L 22621#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L 22622#define GRBM_SE1_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L 22623//GRBM_SE2_PERFCOUNTER_SELECT 22624#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 22625#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa 22626#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb 22627#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc 22628#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd 22629#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf 22630#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 22631#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 22632#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 22633#define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13 22634#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 22635#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 22636#define GRBM_SE2_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16 22637#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL 22638#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L 22639#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L 22640#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L 22641#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L 22642#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L 22643#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L 22644#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L 22645#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L 22646#define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L 22647#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L 22648#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L 22649#define GRBM_SE2_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L 22650//GRBM_SE3_PERFCOUNTER_SELECT 22651#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 22652#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa 22653#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb 22654#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc 22655#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd 22656#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf 22657#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 22658#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 22659#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 22660#define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13 22661#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 22662#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 22663#define GRBM_SE3_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16 22664#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL 22665#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L 22666#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L 22667#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L 22668#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L 22669#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L 22670#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L 22671#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L 22672#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L 22673#define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x00080000L 22674#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L 22675#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L 22676#define GRBM_SE3_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L 22677//WD_PERFCOUNTER0_SELECT 22678#define WD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 22679#define WD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c 22680#define WD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000FFL 22681#define WD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L 22682//WD_PERFCOUNTER1_SELECT 22683#define WD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 22684#define WD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c 22685#define WD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000FFL 22686#define WD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L 22687//WD_PERFCOUNTER2_SELECT 22688#define WD_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 22689#define WD_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c 22690#define WD_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000FFL 22691#define WD_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L 22692//WD_PERFCOUNTER3_SELECT 22693#define WD_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 22694#define WD_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c 22695#define WD_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000FFL 22696#define WD_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L 22697//IA_PERFCOUNTER0_SELECT 22698#define IA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 22699#define IA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa 22700#define IA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 22701#define IA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 22702#define IA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c 22703#define IA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL 22704#define IA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L 22705#define IA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L 22706#define IA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L 22707#define IA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L 22708//IA_PERFCOUNTER1_SELECT 22709#define IA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 22710#define IA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c 22711#define IA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000FFL 22712#define IA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L 22713//IA_PERFCOUNTER2_SELECT 22714#define IA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 22715#define IA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c 22716#define IA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000FFL 22717#define IA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L 22718//IA_PERFCOUNTER3_SELECT 22719#define IA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 22720#define IA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c 22721#define IA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000FFL 22722#define IA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L 22723//IA_PERFCOUNTER0_SELECT1 22724#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 22725#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa 22726#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 22727#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c 22728#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL 22729#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L 22730#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L 22731#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L 22732//VGT_PERFCOUNTER0_SELECT 22733#define VGT_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 22734#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa 22735#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 22736#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 22737#define VGT_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c 22738#define VGT_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL 22739#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L 22740#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L 22741#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L 22742#define VGT_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L 22743//VGT_PERFCOUNTER1_SELECT 22744#define VGT_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 22745#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa 22746#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 22747#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 22748#define VGT_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c 22749#define VGT_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL 22750#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L 22751#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L 22752#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L 22753#define VGT_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L 22754//VGT_PERFCOUNTER2_SELECT 22755#define VGT_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 22756#define VGT_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c 22757#define VGT_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000000FFL 22758#define VGT_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L 22759//VGT_PERFCOUNTER3_SELECT 22760#define VGT_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 22761#define VGT_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c 22762#define VGT_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000000FFL 22763#define VGT_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L 22764//VGT_PERFCOUNTER0_SELECT1 22765#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 22766#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa 22767#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 22768#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c 22769#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL 22770#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L 22771#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L 22772#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L 22773//VGT_PERFCOUNTER1_SELECT1 22774#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 22775#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa 22776#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 22777#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c 22778#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL 22779#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L 22780#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L 22781#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L 22782//VGT_PERFCOUNTER_SEID_MASK 22783#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK__SHIFT 0x0 22784#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK_MASK 0x000000FFL 22785//PA_SU_PERFCOUNTER0_SELECT 22786#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 22787#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa 22788#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 22789#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL 22790#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L 22791#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L 22792//PA_SU_PERFCOUNTER0_SELECT1 22793#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 22794#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa 22795#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL 22796#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L 22797//PA_SU_PERFCOUNTER1_SELECT 22798#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 22799#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa 22800#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 22801#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL 22802#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L 22803#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L 22804//PA_SU_PERFCOUNTER1_SELECT1 22805#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 22806#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa 22807#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL 22808#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L 22809//PA_SU_PERFCOUNTER2_SELECT 22810#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 22811#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 22812#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL 22813#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L 22814//PA_SU_PERFCOUNTER3_SELECT 22815#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 22816#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 22817#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL 22818#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L 22819//PA_SC_PERFCOUNTER0_SELECT 22820#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 22821#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa 22822#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 22823#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL 22824#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L 22825#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L 22826//PA_SC_PERFCOUNTER0_SELECT1 22827#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 22828#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa 22829#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL 22830#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L 22831//PA_SC_PERFCOUNTER1_SELECT 22832#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 22833#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL 22834//PA_SC_PERFCOUNTER2_SELECT 22835#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 22836#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL 22837//PA_SC_PERFCOUNTER3_SELECT 22838#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 22839#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL 22840//PA_SC_PERFCOUNTER4_SELECT 22841#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 22842#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000003FFL 22843//PA_SC_PERFCOUNTER5_SELECT 22844#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 22845#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000003FFL 22846//PA_SC_PERFCOUNTER6_SELECT 22847#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0 22848#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000003FFL 22849//PA_SC_PERFCOUNTER7_SELECT 22850#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0 22851#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000003FFL 22852//SPI_PERFCOUNTER0_SELECT 22853#define SPI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 22854#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa 22855#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 22856#define SPI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 22857#define SPI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c 22858#define SPI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL 22859#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L 22860#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L 22861#define SPI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L 22862#define SPI_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L 22863//SPI_PERFCOUNTER1_SELECT 22864#define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 22865#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa 22866#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 22867#define SPI_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 22868#define SPI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c 22869#define SPI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL 22870#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L 22871#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L 22872#define SPI_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L 22873#define SPI_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L 22874//SPI_PERFCOUNTER2_SELECT 22875#define SPI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 22876#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa 22877#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 22878#define SPI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 22879#define SPI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c 22880#define SPI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL 22881#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L 22882#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L 22883#define SPI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L 22884#define SPI_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L 22885//SPI_PERFCOUNTER3_SELECT 22886#define SPI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 22887#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa 22888#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 22889#define SPI_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 22890#define SPI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c 22891#define SPI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL 22892#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L 22893#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L 22894#define SPI_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L 22895#define SPI_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L 22896//SPI_PERFCOUNTER0_SELECT1 22897#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 22898#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa 22899#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 22900#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c 22901#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL 22902#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L 22903#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L 22904#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L 22905//SPI_PERFCOUNTER1_SELECT1 22906#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 22907#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa 22908#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 22909#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c 22910#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL 22911#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L 22912#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L 22913#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L 22914//SPI_PERFCOUNTER2_SELECT1 22915#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 22916#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa 22917#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 22918#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c 22919#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL 22920#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L 22921#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L 22922#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L 22923//SPI_PERFCOUNTER3_SELECT1 22924#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 22925#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa 22926#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 22927#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c 22928#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL 22929#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L 22930#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L 22931#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L 22932//SPI_PERFCOUNTER4_SELECT 22933#define SPI_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 22934#define SPI_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000000FFL 22935//SPI_PERFCOUNTER5_SELECT 22936#define SPI_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 22937#define SPI_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000000FFL 22938//SPI_PERFCOUNTER_BINS 22939#define SPI_PERFCOUNTER_BINS__BIN0_MIN__SHIFT 0x0 22940#define SPI_PERFCOUNTER_BINS__BIN0_MAX__SHIFT 0x4 22941#define SPI_PERFCOUNTER_BINS__BIN1_MIN__SHIFT 0x8 22942#define SPI_PERFCOUNTER_BINS__BIN1_MAX__SHIFT 0xc 22943#define SPI_PERFCOUNTER_BINS__BIN2_MIN__SHIFT 0x10 22944#define SPI_PERFCOUNTER_BINS__BIN2_MAX__SHIFT 0x14 22945#define SPI_PERFCOUNTER_BINS__BIN3_MIN__SHIFT 0x18 22946#define SPI_PERFCOUNTER_BINS__BIN3_MAX__SHIFT 0x1c 22947#define SPI_PERFCOUNTER_BINS__BIN0_MIN_MASK 0x0000000FL 22948#define SPI_PERFCOUNTER_BINS__BIN0_MAX_MASK 0x000000F0L 22949#define SPI_PERFCOUNTER_BINS__BIN1_MIN_MASK 0x00000F00L 22950#define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK 0x0000F000L 22951#define SPI_PERFCOUNTER_BINS__BIN2_MIN_MASK 0x000F0000L 22952#define SPI_PERFCOUNTER_BINS__BIN2_MAX_MASK 0x00F00000L 22953#define SPI_PERFCOUNTER_BINS__BIN3_MIN_MASK 0x0F000000L 22954#define SPI_PERFCOUNTER_BINS__BIN3_MAX_MASK 0xF0000000L 22955//SQ_PERFCOUNTER0_SELECT 22956#define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 22957#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK__SHIFT 0xc 22958#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 22959#define SQ_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 22960#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK__SHIFT 0x18 22961#define SQ_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c 22962#define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001FFL 22963#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK_MASK 0x0000F000L 22964#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L 22965#define SQ_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L 22966#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK_MASK 0x0F000000L 22967#define SQ_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L 22968//SQ_PERFCOUNTER1_SELECT 22969#define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 22970#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK__SHIFT 0xc 22971#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 22972#define SQ_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 22973#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK__SHIFT 0x18 22974#define SQ_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c 22975#define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001FFL 22976#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK_MASK 0x0000F000L 22977#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L 22978#define SQ_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L 22979#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK_MASK 0x0F000000L 22980#define SQ_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L 22981//SQ_PERFCOUNTER2_SELECT 22982#define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 22983#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK__SHIFT 0xc 22984#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 22985#define SQ_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT 0x14 22986#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK__SHIFT 0x18 22987#define SQ_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c 22988#define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001FFL 22989#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK_MASK 0x0000F000L 22990#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L 22991#define SQ_PERFCOUNTER2_SELECT__SPM_MODE_MASK 0x00F00000L 22992#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK_MASK 0x0F000000L 22993#define SQ_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L 22994//SQ_PERFCOUNTER3_SELECT 22995#define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 22996#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK__SHIFT 0xc 22997#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 22998#define SQ_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT 0x14 22999#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK__SHIFT 0x18 23000#define SQ_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
23001#define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001FFL 23002#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK_MASK 0x0000F000L 23003#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L 23004#define SQ_PERFCOUNTER3_SELECT__SPM_MODE_MASK 0x00F00000L 23005#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK_MASK 0x0F000000L 23006#define SQ_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L 23007//SQ_PERFCOUNTER4_SELECT 23008#define SQ_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 23009#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK__SHIFT 0xc 23010#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 23011#define SQ_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT 0x14 23012#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK__SHIFT 0x18 23013#define SQ_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT 0x1c 23014#define SQ_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000001FFL 23015#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK_MASK 0x0000F000L 23016#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L 23017#define SQ_PERFCOUNTER4_SELECT__SPM_MODE_MASK 0x00F00000L 23018#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK_MASK 0x0F000000L 23019#define SQ_PERFCOUNTER4_SELECT__PERF_MODE_MASK 0xF0000000L 23020//SQ_PERFCOUNTER5_SELECT 23021#define SQ_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 23022#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK__SHIFT 0xc 23023#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 23024#define SQ_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT 0x14 23025#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK__SHIFT 0x18 23026#define SQ_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT 0x1c 23027#define SQ_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000001FFL 23028#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK_MASK 0x0000F000L 23029#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L 23030#define SQ_PERFCOUNTER5_SELECT__SPM_MODE_MASK 0x00F00000L 23031#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK_MASK 0x0F000000L 23032#define SQ_PERFCOUNTER5_SELECT__PERF_MODE_MASK 0xF0000000L 23033//SQ_PERFCOUNTER6_SELECT 23034#define SQ_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0 23035#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK__SHIFT 0xc 23036#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 23037#define SQ_PERFCOUNTER6_SELECT__SPM_MODE__SHIFT 0x14 23038#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK__SHIFT 0x18 23039#define SQ_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT 0x1c 23040#define SQ_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000001FFL 23041#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK_MASK 0x0000F000L 23042#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L 23043#define SQ_PERFCOUNTER6_SELECT__SPM_MODE_MASK 0x00F00000L 23044#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK_MASK 0x0F000000L 23045#define SQ_PERFCOUNTER6_SELECT__PERF_MODE_MASK 0xF0000000L 23046//SQ_PERFCOUNTER7_SELECT 23047#define SQ_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0 23048#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK__SHIFT 0xc 23049#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 23050#define SQ_PERFCOUNTER7_SELECT__SPM_MODE__SHIFT 0x14 23051#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK__SHIFT 0x18 23052#define SQ_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT 0x1c 23053#define SQ_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000001FFL 23054#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK_MASK 0x0000F000L 23055#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L 23056#define SQ_PERFCOUNTER7_SELECT__SPM_MODE_MASK 0x00F00000L 23057#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK_MASK 0x0F000000L 23058#define SQ_PERFCOUNTER7_SELECT__PERF_MODE_MASK 0xF0000000L 23059//SQ_PERFCOUNTER8_SELECT 23060#define SQ_PERFCOUNTER8_SELECT__PERF_SEL__SHIFT 0x0 23061#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK__SHIFT 0xc 23062#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 23063#define SQ_PERFCOUNTER8_SELECT__SPM_MODE__SHIFT 0x14 23064#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK__SHIFT 0x18 23065#define SQ_PERFCOUNTER8_SELECT__PERF_MODE__SHIFT 0x1c 23066#define SQ_PERFCOUNTER8_SELECT__PERF_SEL_MASK 0x000001FFL 23067#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK_MASK 0x0000F000L 23068#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L 23069#define SQ_PERFCOUNTER8_SELECT__SPM_MODE_MASK 0x00F00000L 23070#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK_MASK 0x0F000000L 23071#define SQ_PERFCOUNTER8_SELECT__PERF_MODE_MASK 0xF0000000L 23072//SQ_PERFCOUNTER9_SELECT 23073#define SQ_PERFCOUNTER9_SELECT__PERF_SEL__SHIFT 0x0 23074#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK__SHIFT 0xc 23075#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 23076#define SQ_PERFCOUNTER9_SELECT__SPM_MODE__SHIFT 0x14 23077#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK__SHIFT 0x18 23078#define SQ_PERFCOUNTER9_SELECT__PERF_MODE__SHIFT 0x1c 23079#define SQ_PERFCOUNTER9_SELECT__PERF_SEL_MASK 0x000001FFL 23080#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK_MASK 0x0000F000L 23081#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L 23082#define SQ_PERFCOUNTER9_SELECT__SPM_MODE_MASK 0x00F00000L 23083#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK_MASK 0x0F000000L 23084#define SQ_PERFCOUNTER9_SELECT__PERF_MODE_MASK 0xF0000000L 23085//SQ_PERFCOUNTER10_SELECT 23086#define SQ_PERFCOUNTER10_SELECT__PERF_SEL__SHIFT 0x0 23087#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK__SHIFT 0xc 23088#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 23089#define SQ_PERFCOUNTER10_SELECT__SPM_MODE__SHIFT 0x14 23090#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK__SHIFT 0x18 23091#define SQ_PERFCOUNTER10_SELECT__PERF_MODE__SHIFT 0x1c 23092#define SQ_PERFCOUNTER10_SELECT__PERF_SEL_MASK 0x000001FFL 23093#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK_MASK 0x0000F000L 23094#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L 23095#define SQ_PERFCOUNTER10_SELECT__SPM_MODE_MASK 0x00F00000L 23096#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK_MASK 0x0F000000L 23097#define SQ_PERFCOUNTER10_SELECT__PERF_MODE_MASK 0xF0000000L 23098//SQ_PERFCOUNTER11_SELECT 23099#define SQ_PERFCOUNTER11_SELECT__PERF_SEL__SHIFT 0x0 23100#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK__SHIFT 0xc 23101#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 23102#define SQ_PERFCOUNTER11_SELECT__SPM_MODE__SHIFT 0x14 23103#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK__SHIFT 0x18 23104#define SQ_PERFCOUNTER11_SELECT__PERF_MODE__SHIFT 0x1c 23105#define SQ_PERFCOUNTER11_SELECT__PERF_SEL_MASK 0x000001FFL 23106#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK_MASK 0x0000F000L 23107#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L 23108#define SQ_PERFCOUNTER11_SELECT__SPM_MODE_MASK 0x00F00000L 23109#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK_MASK 0x0F000000L 23110#define SQ_PERFCOUNTER11_SELECT__PERF_MODE_MASK 0xF0000000L 23111//SQ_PERFCOUNTER12_SELECT 23112#define SQ_PERFCOUNTER12_SELECT__PERF_SEL__SHIFT 0x0 23113#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK__SHIFT 0xc 23114#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 23115#define SQ_PERFCOUNTER12_SELECT__SPM_MODE__SHIFT 0x14 23116#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK__SHIFT 0x18 23117#define SQ_PERFCOUNTER12_SELECT__PERF_MODE__SHIFT 0x1c 23118#define SQ_PERFCOUNTER12_SELECT__PERF_SEL_MASK 0x000001FFL 23119#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK_MASK 0x0000F000L 23120#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L 23121#define SQ_PERFCOUNTER12_SELECT__SPM_MODE_MASK 0x00F00000L 23122#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK_MASK 0x0F000000L 23123#define SQ_PERFCOUNTER12_SELECT__PERF_MODE_MASK 0xF0000000L 23124//SQ_PERFCOUNTER13_SELECT 23125#define SQ_PERFCOUNTER13_SELECT__PERF_SEL__SHIFT 0x0 23126#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK__SHIFT 0xc 23127#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 23128#define SQ_PERFCOUNTER13_SELECT__SPM_MODE__SHIFT 0x14 23129#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK__SHIFT 0x18 23130#define SQ_PERFCOUNTER13_SELECT__PERF_MODE__SHIFT 0x1c 23131#define SQ_PERFCOUNTER13_SELECT__PERF_SEL_MASK 0x000001FFL 23132#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK_MASK 0x0000F000L 23133#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L 23134#define SQ_PERFCOUNTER13_SELECT__SPM_MODE_MASK 0x00F00000L 23135#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK_MASK 0x0F000000L 23136#define SQ_PERFCOUNTER13_SELECT__PERF_MODE_MASK 0xF0000000L 23137//SQ_PERFCOUNTER14_SELECT 23138#define SQ_PERFCOUNTER14_SELECT__PERF_SEL__SHIFT 0x0 23139#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK__SHIFT 0xc 23140#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 23141#define SQ_PERFCOUNTER14_SELECT__SPM_MODE__SHIFT 0x14 23142#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK__SHIFT 0x18 23143#define SQ_PERFCOUNTER14_SELECT__PERF_MODE__SHIFT 0x1c 23144#define SQ_PERFCOUNTER14_SELECT__PERF_SEL_MASK 0x000001FFL 23145#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK_MASK 0x0000F000L 23146#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L 23147#define SQ_PERFCOUNTER14_SELECT__SPM_MODE_MASK 0x00F00000L 23148#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK_MASK 0x0F000000L 23149#define SQ_PERFCOUNTER14_SELECT__PERF_MODE_MASK 0xF0000000L 23150//SQ_PERFCOUNTER15_SELECT 23151#define SQ_PERFCOUNTER15_SELECT__PERF_SEL__SHIFT 0x0 23152#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK__SHIFT 0xc 23153#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 23154#define SQ_PERFCOUNTER15_SELECT__SPM_MODE__SHIFT 0x14 23155#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK__SHIFT 0x18 23156#define SQ_PERFCOUNTER15_SELECT__PERF_MODE__SHIFT 0x1c 23157#define SQ_PERFCOUNTER15_SELECT__PERF_SEL_MASK 0x000001FFL 23158#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK_MASK 0x0000F000L 23159#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK_MASK 0x000F0000L 23160#define SQ_PERFCOUNTER15_SELECT__SPM_MODE_MASK 0x00F00000L 23161#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK_MASK 0x0F000000L 23162#define SQ_PERFCOUNTER15_SELECT__PERF_MODE_MASK 0xF0000000L 23163//SQ_PERFCOUNTER_CTRL 23164#define SQ_PERFCOUNTER_CTRL__PS_EN__SHIFT 0x0 23165#define SQ_PERFCOUNTER_CTRL__VS_EN__SHIFT 0x1 23166#define SQ_PERFCOUNTER_CTRL__GS_EN__SHIFT 0x2 23167#define SQ_PERFCOUNTER_CTRL__ES_EN__SHIFT 0x3 23168#define SQ_PERFCOUNTER_CTRL__HS_EN__SHIFT 0x4 23169#define SQ_PERFCOUNTER_CTRL__LS_EN__SHIFT 0x5 23170#define SQ_PERFCOUNTER_CTRL__CS_EN__SHIFT 0x6 23171#define SQ_PERFCOUNTER_CTRL__CNTR_RATE__SHIFT 0x8 23172#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH__SHIFT 0xd 23173#define SQ_PERFCOUNTER_CTRL__PS_EN_MASK 0x00000001L 23174#define SQ_PERFCOUNTER_CTRL__VS_EN_MASK 0x00000002L 23175#define SQ_PERFCOUNTER_CTRL__GS_EN_MASK 0x00000004L 23176#define SQ_PERFCOUNTER_CTRL__ES_EN_MASK 0x00000008L 23177#define SQ_PERFCOUNTER_CTRL__HS_EN_MASK 0x00000010L 23178#define SQ_PERFCOUNTER_CTRL__LS_EN_MASK 0x00000020L 23179#define SQ_PERFCOUNTER_CTRL__CS_EN_MASK 0x00000040L 23180#define SQ_PERFCOUNTER_CTRL__CNTR_RATE_MASK 0x00001F00L 23181#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH_MASK 0x00002000L 23182//SQ_PERFCOUNTER_MASK 23183#define SQ_PERFCOUNTER_MASK__SH0_MASK__SHIFT 0x0 23184#define SQ_PERFCOUNTER_MASK__SH1_MASK__SHIFT 0x10 23185#define SQ_PERFCOUNTER_MASK__SH0_MASK_MASK 0x0000FFFFL 23186#define SQ_PERFCOUNTER_MASK__SH1_MASK_MASK 0xFFFF0000L 23187//SQ_PERFCOUNTER_CTRL2 23188#define SQ_PERFCOUNTER_CTRL2__FORCE_EN__SHIFT 0x0 23189#define SQ_PERFCOUNTER_CTRL2__FORCE_EN_MASK 0x00000001L 23190//SX_PERFCOUNTER0_SELECT 23191#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 23192#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa 23193#define SX_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 23194#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL 23195#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L 23196#define SX_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L 23197//SX_PERFCOUNTER1_SELECT 23198#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 23199#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa 23200#define SX_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 23201#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL 23202#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L 23203#define SX_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L 23204//SX_PERFCOUNTER2_SELECT 23205#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 23206#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa 23207#define SX_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 23208#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL 23209#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L 23210#define SX_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L 23211//SX_PERFCOUNTER3_SELECT 23212#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 23213#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa 23214#define SX_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 23215#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL 23216#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L 23217#define SX_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L 23218//SX_PERFCOUNTER0_SELECT1 23219#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0 23220#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa 23221#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK 0x000003FFL 23222#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK 0x000FFC00L 23223//SX_PERFCOUNTER1_SELECT1 23224#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0 23225#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa 23226#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2_MASK 0x000003FFL 23227#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3_MASK 0x000FFC00L 23228//GDS_PERFCOUNTER0_SELECT 23229#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 23230#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa 23231#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 23232#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL 23233#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L 23234#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L 23235//GDS_PERFCOUNTER1_SELECT 23236#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 23237#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa 23238#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 23239#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL 23240#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L 23241#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L 23242//GDS_PERFCOUNTER2_SELECT 23243#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 23244#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa 23245#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 23246#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL 23247#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L 23248#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L 23249//GDS_PERFCOUNTER3_SELECT 23250#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 23251#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa 23252#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 23253#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x000003FFL 23254#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK 0x000FFC00L 23255#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L 23256//GDS_PERFCOUNTER0_SELECT1 23257#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0 23258#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa 23259#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK 0x000003FFL 23260#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK 0x000FFC00L 23261//TA_PERFCOUNTER0_SELECT 23262#define TA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 23263#define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa 23264#define TA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 23265#define TA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 23266#define TA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c 23267#define TA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000FFL 23268#define TA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0003FC00L 23269#define TA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L 23270#define TA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L 23271#define TA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L 23272//TA_PERFCOUNTER0_SELECT1 23273#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 23274#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa 23275#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 23276#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c 23277#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000000FFL 23278#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0003FC00L 23279#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L 23280#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L 23281//TA_PERFCOUNTER1_SELECT 23282#define TA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 23283#define TA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa 23284#define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 23285#define TA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 23286#define TA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c 23287#define TA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000FFL 23288#define TA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x0003FC00L 23289#define TA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L 23290#define TA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L 23291#define TA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L 23292//TD_PERFCOUNTER0_SELECT 23293#define TD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 23294#define TD_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa 23295#define TD_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 23296#define TD_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 23297#define TD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c 23298#define TD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000000FFL 23299#define TD_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0003FC00L 23300#define TD_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L 23301#define TD_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L 23302#define TD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L 23303//TD_PERFCOUNTER0_SELECT1 23304#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 23305#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa 23306#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 23307#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c 23308#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000000FFL 23309#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0003FC00L 23310#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L 23311#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L 23312//TD_PERFCOUNTER1_SELECT 23313#define TD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 23314#define TD_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa 23315#define TD_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 23316#define TD_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 23317#define TD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c 23318#define TD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000000FFL 23319#define TD_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x0003FC00L 23320#define TD_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L 23321#define TD_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L 23322#define TD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L 23323//TCP_PERFCOUNTER0_SELECT 23324#define TCP_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 23325#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa 23326#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 23327#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 23328#define TCP_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c 23329#define TCP_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL 23330#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L 23331#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L 23332#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L 23333#define TCP_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L 23334//TCP_PERFCOUNTER0_SELECT1 23335#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 23336#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa 23337#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 23338#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c 23339#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL 23340#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L 23341#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L 23342#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L 23343//TCP_PERFCOUNTER1_SELECT 23344#define TCP_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 23345#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa 23346#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 23347#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 23348#define TCP_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c 23349#define TCP_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL 23350#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L 23351#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L 23352#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L 23353#define TCP_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L 23354//TCP_PERFCOUNTER1_SELECT1 23355#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 23356#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa 23357#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 23358#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c 23359#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL 23360#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L 23361#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L 23362#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L 23363//TCP_PERFCOUNTER2_SELECT 23364#define TCP_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 23365#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 23366#define TCP_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c 23367#define TCP_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL 23368#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L 23369#define TCP_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L 23370//TCP_PERFCOUNTER3_SELECT 23371#define TCP_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 23372#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 23373#define TCP_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c 23374#define TCP_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL 23375#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L 23376#define TCP_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L 23377//TCC_PERFCOUNTER0_SELECT 23378#define TCC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 23379#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa 23380#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 23381#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 23382#define TCC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c 23383#define TCC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL 23384#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L 23385#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L 23386#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L 23387#define TCC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L 23388//TCC_PERFCOUNTER0_SELECT1 23389#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 23390#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa 23391#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 23392#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c 23393#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL 23394#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L 23395#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L 23396#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L 23397//TCC_PERFCOUNTER1_SELECT 23398#define TCC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 23399#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa 23400#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 23401#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 23402#define TCC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c 23403#define TCC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL 23404#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L 23405#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L 23406#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L 23407#define TCC_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L 23408//TCC_PERFCOUNTER1_SELECT1 23409#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 23410#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa 23411#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18 23412#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c 23413#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL 23414#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L 23415#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0x0F000000L 23416#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xF0000000L 23417//TCC_PERFCOUNTER2_SELECT 23418#define TCC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 23419#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 23420#define TCC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c 23421#define TCC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL 23422#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L 23423#define TCC_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L 23424//TCC_PERFCOUNTER3_SELECT 23425#define TCC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 23426#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 23427#define TCC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c 23428#define TCC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL 23429#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L 23430#define TCC_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L 23431//TCA_PERFCOUNTER0_SELECT 23432#define TCA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 23433#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa 23434#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 23435#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 23436#define TCA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c 23437#define TCA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL 23438#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L 23439#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L 23440#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L 23441#define TCA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L 23442//TCA_PERFCOUNTER0_SELECT1 23443#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 23444#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa 23445#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 23446#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c 23447#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL 23448#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L 23449#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L 23450#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L 23451//TCA_PERFCOUNTER1_SELECT 23452#define TCA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 23453#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa 23454#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 23455#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 23456#define TCA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c 23457#define TCA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL 23458#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L 23459#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L 23460#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L 23461#define TCA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L 23462//TCA_PERFCOUNTER1_SELECT1 23463#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 23464#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa 23465#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18 23466#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c 23467#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL 23468#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L 23469#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0x0F000000L 23470#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xF0000000L 23471//TCA_PERFCOUNTER2_SELECT 23472#define TCA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 23473#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 23474#define TCA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c 23475#define TCA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL 23476#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L 23477#define TCA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L 23478//TCA_PERFCOUNTER3_SELECT 23479#define TCA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 23480#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 23481#define TCA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c 23482#define TCA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL 23483#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L 23484#define TCA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L 23485//CB_PERFCOUNTER_FILTER 23486#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE__SHIFT 0x0 23487#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL__SHIFT 0x1 23488#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE__SHIFT 0x4 23489#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL__SHIFT 0x5 23490#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE__SHIFT 0xa 23491#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL__SHIFT 0xb 23492#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE__SHIFT 0xc 23493#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL__SHIFT 0xd 23494#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE__SHIFT 0x11 23495#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL__SHIFT 0x12 23496#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE__SHIFT 0x15 23497#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL__SHIFT 0x16 23498#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE_MASK 0x00000001L 23499#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL_MASK 0x0000000EL 23500#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE_MASK 0x00000010L 23501#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL_MASK 0x000003E0L 23502#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE_MASK 0x00000400L 23503#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL_MASK 0x00000800L 23504#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE_MASK 0x00001000L 23505#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL_MASK 0x0000E000L 23506#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE_MASK 0x00020000L 23507#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL_MASK 0x001C0000L 23508#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE_MASK 0x00200000L 23509#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL_MASK 0x00C00000L 23510//CB_PERFCOUNTER0_SELECT 23511#define CB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 23512#define CB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa 23513#define CB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 23514#define CB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 23515#define CB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c 23516#define CB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001FFL 23517#define CB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0007FC00L 23518#define CB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L 23519#define CB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L 23520#define CB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L 23521//CB_PERFCOUNTER0_SELECT1 23522#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 23523#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa 23524#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 23525#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c 23526#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000001FFL 23527#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0007FC00L 23528#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L 23529#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L 23530//CB_PERFCOUNTER1_SELECT 23531#define CB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 23532#define CB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c 23533#define CB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001FFL 23534#define CB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L 23535//CB_PERFCOUNTER2_SELECT 23536#define CB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 23537#define CB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c 23538#define CB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001FFL 23539#define CB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L 23540//CB_PERFCOUNTER3_SELECT 23541#define CB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 23542#define CB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c 23543#define CB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001FFL 23544#define CB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L 23545//DB_PERFCOUNTER0_SELECT 23546#define DB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 23547#define DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa 23548#define DB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 23549#define DB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 23550#define DB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c 23551#define DB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL 23552#define DB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L 23553#define DB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L 23554#define DB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L 23555#define DB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L 23556//DB_PERFCOUNTER0_SELECT1 23557#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 23558#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa 23559#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 23560#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c 23561#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL 23562#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L 23563#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L 23564#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L 23565//DB_PERFCOUNTER1_SELECT 23566#define DB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 23567#define DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa 23568#define DB_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 23569#define DB_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 23570#define DB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c 23571#define DB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL 23572#define DB_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L 23573#define DB_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L 23574#define DB_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L 23575#define DB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L 23576//DB_PERFCOUNTER1_SELECT1 23577#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 23578#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa 23579#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 23580#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c 23581#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL 23582#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L 23583#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L 23584#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L 23585//DB_PERFCOUNTER2_SELECT 23586#define DB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 23587#define DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa 23588#define DB_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 23589#define DB_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 23590#define DB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c 23591#define DB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL 23592#define DB_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L 23593#define DB_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L 23594#define DB_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L 23595#define DB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L 23596//DB_PERFCOUNTER3_SELECT 23597#define DB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 23598#define DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa 23599#define DB_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 23600#define DB_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 23601#define DB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c 23602#define DB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL 23603#define DB_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L 23604#define DB_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L 23605#define DB_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L 23606#define DB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L 23607//RLC_SPM_PERFMON_CNTL 23608#define RLC_SPM_PERFMON_CNTL__RESERVED1__SHIFT 0x2 23609#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE__SHIFT 0xc 23610#define RLC_SPM_PERFMON_CNTL__RESERVED__SHIFT 0xe 23611#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL__SHIFT 0x10 23612#define RLC_SPM_PERFMON_CNTL__RESERVED1_MASK 0x00000FFCL 23613#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK 0x00003000L 23614#define RLC_SPM_PERFMON_CNTL__RESERVED_MASK 0x0000C000L 23615#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL_MASK 0xFFFF0000L 23616//RLC_SPM_PERFMON_RING_BASE_LO 23617#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO__SHIFT 0x0 23618#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO_MASK 0xFFFFFFFFL 23619//RLC_SPM_PERFMON_RING_BASE_HI 23620#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI__SHIFT 0x0 23621#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED__SHIFT 0x10 23622#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI_MASK 0x0000FFFFL 23623#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED_MASK 0xFFFF0000L 23624//RLC_SPM_PERFMON_RING_SIZE 23625#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE__SHIFT 0x0 23626#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE_MASK 0xFFFFFFFFL 23627//RLC_SPM_PERFMON_SEGMENT_SIZE 23628#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE__SHIFT 0x0 23629#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1__SHIFT 0x8 23630#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE__SHIFT 0xb 23631#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE__SHIFT 0x10 23632#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE__SHIFT 0x15 23633#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE__SHIFT 0x1a 23634#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED__SHIFT 0x1f 23635#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE_MASK 0x000000FFL 23636#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1_MASK 0x00000700L 23637#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE_MASK 0x0000F800L 23638#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE_MASK 0x001F0000L 23639#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE_MASK 0x03E00000L 23640#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE_MASK 0x7C000000L 23641#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED_MASK 0x80000000L 23642//RLC_SPM_SE_MUXSEL_ADDR 23643#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0 23644#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xFFFFFFFFL 23645//RLC_SPM_SE_MUXSEL_DATA 23646#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0 23647#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xFFFFFFFFL 23648//RLC_SPM_CPG_PERFMON_SAMPLE_DELAY 23649#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 23650#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 23651#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL 23652#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L 23653//RLC_SPM_CPC_PERFMON_SAMPLE_DELAY 23654#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 23655#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 23656#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL 23657#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L 23658//RLC_SPM_CPF_PERFMON_SAMPLE_DELAY 23659#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 23660#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 23661#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL 23662#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L 23663//RLC_SPM_CB_PERFMON_SAMPLE_DELAY 23664#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 23665#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 23666#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL 23667#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L 23668//RLC_SPM_DB_PERFMON_SAMPLE_DELAY 23669#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 23670#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 23671#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL 23672#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L 23673//RLC_SPM_PA_PERFMON_SAMPLE_DELAY 23674#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 23675#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 23676#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL 23677#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L 23678//RLC_SPM_GDS_PERFMON_SAMPLE_DELAY 23679#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 23680#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 23681#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL 23682#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L 23683//RLC_SPM_IA_PERFMON_SAMPLE_DELAY 23684#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 23685#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 23686#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL 23687#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L 23688//RLC_SPM_SC_PERFMON_SAMPLE_DELAY 23689#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 23690#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 23691#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL 23692#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L 23693//RLC_SPM_TCC_PERFMON_SAMPLE_DELAY 23694#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 23695#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 23696#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL 23697#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L 23698//RLC_SPM_TCA_PERFMON_SAMPLE_DELAY 23699#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 23700#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 23701#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL 23702#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L 23703//RLC_SPM_TCP_PERFMON_SAMPLE_DELAY 23704#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 23705#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 23706#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL 23707#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L 23708//RLC_SPM_TA_PERFMON_SAMPLE_DELAY 23709#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 23710#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 23711#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL 23712#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L 23713//RLC_SPM_TD_PERFMON_SAMPLE_DELAY 23714#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 23715#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 23716#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL 23717#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L 23718//RLC_SPM_VGT_PERFMON_SAMPLE_DELAY 23719#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 23720#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 23721#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL 23722#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L 23723//RLC_SPM_SPI_PERFMON_SAMPLE_DELAY 23724#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 23725#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 23726#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL 23727#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L 23728//RLC_SPM_SQG_PERFMON_SAMPLE_DELAY 23729#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 23730#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 23731#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL 23732#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L 23733//RLC_SPM_SX_PERFMON_SAMPLE_DELAY 23734#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 23735#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 23736#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL 23737#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L 23738//RLC_SPM_GLOBAL_MUXSEL_ADDR 23739#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0 23740#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xFFFFFFFFL 23741//RLC_SPM_GLOBAL_MUXSEL_DATA 23742#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0 23743#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xFFFFFFFFL 23744//RLC_SPM_RING_RDPTR 23745#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR__SHIFT 0x0 23746#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR_MASK 0xFFFFFFFFL 23747//RLC_SPM_SEGMENT_THRESHOLD 23748#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD__SHIFT 0x0 23749#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD_MASK 0xFFFFFFFFL 23750//RLC_SPM_RMI_PERFMON_SAMPLE_DELAY 23751#define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 23752#define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 23753#define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0x000000FFL 23754#define RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xFFFFFF00L 23755//RLC_PERFMON_CLK_CNTL 23756#define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE__SHIFT 0x0 23757#define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK 0x00000001L 23758//RLC_PERFMON_CNTL 23759#define RLC_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 23760#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa 23761#define RLC_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000007L 23762#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L 23763//RLC_PERFCOUNTER0_SELECT 23764#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 23765#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x00FFL 23766//RLC_PERFCOUNTER1_SELECT 23767#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 23768#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x00FFL 23769//RLC_GPU_IOV_PERF_CNT_CNTL 23770#define RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE__SHIFT 0x0 23771#define RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT__SHIFT 0x1 23772#define RLC_GPU_IOV_PERF_CNT_CNTL__RESET__SHIFT 0x2 23773#define RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED__SHIFT 0x3 23774#define RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE_MASK 0x00000001L 23775#define RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT_MASK 0x00000002L 23776#define RLC_GPU_IOV_PERF_CNT_CNTL__RESET_MASK 0x00000004L 23777#define RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED_MASK 0xFFFFFFF8L 23778//RLC_GPU_IOV_PERF_CNT_WR_ADDR 23779#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID__SHIFT 0x0 23780#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID__SHIFT 0x4 23781#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED__SHIFT 0x6 23782#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID_MASK 0x0000000FL 23783#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID_MASK 0x00000030L 23784#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED_MASK 0xFFFFFFC0L 23785//RLC_GPU_IOV_PERF_CNT_WR_DATA 23786#define RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA__SHIFT 0x0 23787#define RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA_MASK 0x0000000FL 23788//RLC_GPU_IOV_PERF_CNT_RD_ADDR 23789#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID__SHIFT 0x0 23790#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID__SHIFT 0x4 23791#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED__SHIFT 0x6 23792#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID_MASK 0x0000000FL 23793#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID_MASK 0x00000030L 23794#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED_MASK 0xFFFFFFC0L 23795//RLC_GPU_IOV_PERF_CNT_RD_DATA 23796#define RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA__SHIFT 0x0 23797#define RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA_MASK 0x0000000FL 23798//RMI_PERFCOUNTER0_SELECT 23799#define RMI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 23800#define RMI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa 23801#define RMI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 23802#define RMI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 23803#define RMI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c 23804#define RMI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001FFL 23805#define RMI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x0007FC00L 23806#define RMI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L 23807#define RMI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L 23808#define RMI_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L 23809//RMI_PERFCOUNTER0_SELECT1 23810#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 23811#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa 23812#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 23813#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c 23814#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000001FFL 23815#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x0007FC00L 23816#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L 23817#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L 23818//RMI_PERFCOUNTER1_SELECT 23819#define RMI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 23820#define RMI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c 23821#define RMI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001FFL 23822#define RMI_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L 23823//RMI_PERFCOUNTER2_SELECT 23824#define RMI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 23825#define RMI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa 23826#define RMI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 23827#define RMI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 23828#define RMI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c 23829#define RMI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001FFL 23830#define RMI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x0007FC00L 23831#define RMI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L 23832#define RMI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L 23833#define RMI_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L 23834//RMI_PERFCOUNTER2_SELECT1 23835#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 23836#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa 23837#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 23838#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c 23839#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000001FFL 23840#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x0007FC00L 23841#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L 23842#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L 23843//RMI_PERFCOUNTER3_SELECT 23844#define RMI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 23845#define RMI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c 23846#define RMI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001FFL 23847#define RMI_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L 23848//RMI_PERF_COUNTER_CNTL 23849#define RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL__SHIFT 0x0 23850#define RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL__SHIFT 0x2 23851#define RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL__SHIFT 0x4 23852#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0__SHIFT 0x6 23853#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1__SHIFT 0x8 23854#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID__SHIFT 0xa 23855#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID__SHIFT 0xe 23856#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD__SHIFT 0x13 23857#define RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET__SHIFT 0x19 23858#define RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL__SHIFT 0x1a 23859#define RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL_MASK 0x00000003L 23860#define RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL_MASK 0x0000000CL 23861#define RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL_MASK 0x00000030L 23862#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0_MASK 0x000000C0L 23863#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1_MASK 0x00000300L 23864#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID_MASK 0x00003C00L 23865#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID_MASK 0x0007C000L 23866#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD_MASK 0x01F80000L 23867#define RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET_MASK 0x02000000L 23868#define RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL_MASK 0x04000000L 23869 23870 23871// addressBlock: gc_utcl2_atcl2pfcntldec 23872//ATC_L2_PERFCOUNTER0_CFG 23873#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 23874#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 23875#define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 23876#define ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 23877#define ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 23878#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 23879#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 23880#define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 23881#define ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 23882#define ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 23883//ATC_L2_PERFCOUNTER1_CFG 23884#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 23885#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 23886#define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 23887#define ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 23888#define ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 23889#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 23890#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 23891#define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 23892#define ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 23893#define ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 23894//ATC_L2_PERFCOUNTER_RSLT_CNTL 23895#define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 23896#define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 23897#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 23898#define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 23899#define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 23900#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 23901#define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 23902#define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 23903#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 23904#define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 23905#define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 23906#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 23907 23908 23909// addressBlock: gc_utcl2_vml2pldec 23910//MC_VM_L2_PERFCOUNTER0_CFG 23911#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 23912#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 23913#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 23914#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 23915#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 23916#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 23917#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 23918#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 23919#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 23920#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 23921//MC_VM_L2_PERFCOUNTER1_CFG 23922#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 23923#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 23924#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 23925#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 23926#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 23927#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 23928#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 23929#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 23930#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 23931#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 23932//MC_VM_L2_PERFCOUNTER2_CFG 23933#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 23934#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 23935#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 23936#define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 23937#define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 23938#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 23939#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 23940#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 23941#define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 23942#define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 23943//MC_VM_L2_PERFCOUNTER3_CFG 23944#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 23945#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 23946#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 23947#define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 23948#define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 23949#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL 23950#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L 23951#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L 23952#define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L 23953#define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L 23954//MC_VM_L2_PERFCOUNTER4_CFG 23955#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x0 23956#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x8 23957#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x18 23958#define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x1c 23959#define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x1d 23960#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000FFL 23961#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000FF00L 23962#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0F000000L 23963#define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L 23964#define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L 23965//MC_VM_L2_PERFCOUNTER5_CFG 23966#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x0 23967#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x8 23968#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x18 23969#define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x1c 23970#define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x1d 23971#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000FFL 23972#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000FF00L 23973#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0F000000L 23974#define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L 23975#define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L 23976//MC_VM_L2_PERFCOUNTER6_CFG 23977#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x0 23978#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x8 23979#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x18 23980#define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x1c 23981#define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x1d 23982#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000FFL 23983#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000FF00L 23984#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0F000000L 23985#define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L 23986#define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L 23987//MC_VM_L2_PERFCOUNTER7_CFG 23988#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x0 23989#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x8 23990#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x18 23991#define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x1c 23992#define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x1d 23993#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000FFL 23994#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000FF00L 23995#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0F000000L 23996#define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L 23997#define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L 23998//MC_VM_L2_PERFCOUNTER_RSLT_CNTL 23999#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 24000#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
24001#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 24002#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 24003#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 24004#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 24005#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 24006#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 24007#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 24008#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 24009#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 24010#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 24011 24012 24013// addressBlock: gc_rlcpdec 24014//RLC_CNTL 24015#define RLC_CNTL__RLC_ENABLE_F32__SHIFT 0x0 24016#define RLC_CNTL__FORCE_RETRY__SHIFT 0x1 24017#define RLC_CNTL__READ_CACHE_DISABLE__SHIFT 0x2 24018#define RLC_CNTL__RLC_STEP_F32__SHIFT 0x3 24019#define RLC_CNTL__RESERVED__SHIFT 0x4 24020#define RLC_CNTL__RLC_ENABLE_F32_MASK 0x00000001L 24021#define RLC_CNTL__FORCE_RETRY_MASK 0x00000002L 24022#define RLC_CNTL__READ_CACHE_DISABLE_MASK 0x00000004L 24023#define RLC_CNTL__RLC_STEP_F32_MASK 0x00000008L 24024#define RLC_CNTL__RESERVED_MASK 0xFFFFFFF0L 24025//RLC_STAT 24026#define RLC_STAT__RLC_BUSY__SHIFT 0x0 24027#define RLC_STAT__RLC_GPM_BUSY__SHIFT 0x1 24028#define RLC_STAT__RLC_SPM_BUSY__SHIFT 0x2 24029#define RLC_STAT__RLC_SRM_BUSY__SHIFT 0x3 24030#define RLC_STAT__MC_BUSY__SHIFT 0x4 24031#define RLC_STAT__RLC_THREAD_0_BUSY__SHIFT 0x5 24032#define RLC_STAT__RLC_THREAD_1_BUSY__SHIFT 0x6 24033#define RLC_STAT__RLC_THREAD_2_BUSY__SHIFT 0x7 24034#define RLC_STAT__RESERVED__SHIFT 0x8 24035#define RLC_STAT__RLC_BUSY_MASK 0x00000001L 24036#define RLC_STAT__RLC_GPM_BUSY_MASK 0x00000002L 24037#define RLC_STAT__RLC_SPM_BUSY_MASK 0x00000004L 24038#define RLC_STAT__RLC_SRM_BUSY_MASK 0x00000008L 24039#define RLC_STAT__MC_BUSY_MASK 0x00000010L 24040#define RLC_STAT__RLC_THREAD_0_BUSY_MASK 0x00000020L 24041#define RLC_STAT__RLC_THREAD_1_BUSY_MASK 0x00000040L 24042#define RLC_STAT__RLC_THREAD_2_BUSY_MASK 0x00000080L 24043#define RLC_STAT__RESERVED_MASK 0xFFFFFF00L 24044//RLC_SAFE_MODE 24045#define RLC_SAFE_MODE__CMD__SHIFT 0x0 24046#define RLC_SAFE_MODE__MESSAGE__SHIFT 0x1 24047#define RLC_SAFE_MODE__RESERVED1__SHIFT 0x5 24048#define RLC_SAFE_MODE__RESPONSE__SHIFT 0x8 24049#define RLC_SAFE_MODE__RESERVED__SHIFT 0xc 24050#define RLC_SAFE_MODE__CMD_MASK 0x00000001L 24051#define RLC_SAFE_MODE__MESSAGE_MASK 0x0000001EL 24052#define RLC_SAFE_MODE__RESERVED1_MASK 0x000000E0L 24053#define RLC_SAFE_MODE__RESPONSE_MASK 0x00000F00L 24054#define RLC_SAFE_MODE__RESERVED_MASK 0xFFFFF000L 24055//RLC_MEM_SLP_CNTL 24056#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN__SHIFT 0x0 24057#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN__SHIFT 0x1 24058#define RLC_MEM_SLP_CNTL__RESERVED__SHIFT 0x2 24059#define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE__SHIFT 0x7 24060#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY__SHIFT 0x8 24061#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY__SHIFT 0x10 24062#define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18 24063#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK 0x00000001L 24064#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK 0x00000002L 24065#define RLC_MEM_SLP_CNTL__RESERVED_MASK 0x0000007CL 24066#define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE_MASK 0x00000080L 24067#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY_MASK 0x0000FF00L 24068#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY_MASK 0x00FF0000L 24069#define RLC_MEM_SLP_CNTL__RESERVED1_MASK 0xFF000000L 24070//SMU_RLC_RESPONSE 24071#define SMU_RLC_RESPONSE__RESP__SHIFT 0x0 24072#define SMU_RLC_RESPONSE__RESP_MASK 0xFFFFFFFFL 24073//RLC_RLCV_SAFE_MODE 24074#define RLC_RLCV_SAFE_MODE__CMD__SHIFT 0x0 24075#define RLC_RLCV_SAFE_MODE__MESSAGE__SHIFT 0x1 24076#define RLC_RLCV_SAFE_MODE__RESERVED1__SHIFT 0x5 24077#define RLC_RLCV_SAFE_MODE__RESPONSE__SHIFT 0x8 24078#define RLC_RLCV_SAFE_MODE__RESERVED__SHIFT 0xc 24079#define RLC_RLCV_SAFE_MODE__CMD_MASK 0x00000001L 24080#define RLC_RLCV_SAFE_MODE__MESSAGE_MASK 0x0000001EL 24081#define RLC_RLCV_SAFE_MODE__RESERVED1_MASK 0x000000E0L 24082#define RLC_RLCV_SAFE_MODE__RESPONSE_MASK 0x00000F00L 24083#define RLC_RLCV_SAFE_MODE__RESERVED_MASK 0xFFFFF000L 24084//RLC_SMU_SAFE_MODE 24085#define RLC_SMU_SAFE_MODE__CMD__SHIFT 0x0 24086#define RLC_SMU_SAFE_MODE__MESSAGE__SHIFT 0x1 24087#define RLC_SMU_SAFE_MODE__RESERVED1__SHIFT 0x5 24088#define RLC_SMU_SAFE_MODE__RESPONSE__SHIFT 0x8 24089#define RLC_SMU_SAFE_MODE__RESERVED__SHIFT 0xc 24090#define RLC_SMU_SAFE_MODE__CMD_MASK 0x00000001L 24091#define RLC_SMU_SAFE_MODE__MESSAGE_MASK 0x0000001EL 24092#define RLC_SMU_SAFE_MODE__RESERVED1_MASK 0x000000E0L 24093#define RLC_SMU_SAFE_MODE__RESPONSE_MASK 0x00000F00L 24094#define RLC_SMU_SAFE_MODE__RESERVED_MASK 0xFFFFF000L 24095//RLC_RLCV_COMMAND 24096#define RLC_RLCV_COMMAND__CMD__SHIFT 0x0 24097#define RLC_RLCV_COMMAND__RESERVED__SHIFT 0x4 24098#define RLC_RLCV_COMMAND__CMD_MASK 0x0000000FL 24099#define RLC_RLCV_COMMAND__RESERVED_MASK 0xFFFFFFF0L 24100//RLC_REFCLOCK_TIMESTAMP_LSB 24101#define RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB__SHIFT 0x0 24102#define RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB_MASK 0xFFFFFFFFL 24103//RLC_REFCLOCK_TIMESTAMP_MSB 24104#define RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB__SHIFT 0x0 24105#define RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB_MASK 0xFFFFFFFFL 24106//RLC_GPM_TIMER_INT_0 24107#define RLC_GPM_TIMER_INT_0__TIMER__SHIFT 0x0 24108#define RLC_GPM_TIMER_INT_0__TIMER_MASK 0xFFFFFFFFL 24109//RLC_GPM_TIMER_INT_1 24110#define RLC_GPM_TIMER_INT_1__TIMER__SHIFT 0x0 24111#define RLC_GPM_TIMER_INT_1__TIMER_MASK 0xFFFFFFFFL 24112//RLC_GPM_TIMER_INT_2 24113#define RLC_GPM_TIMER_INT_2__TIMER__SHIFT 0x0 24114#define RLC_GPM_TIMER_INT_2__TIMER_MASK 0xFFFFFFFFL 24115//RLC_GPM_TIMER_CTRL 24116#define RLC_GPM_TIMER_CTRL__TIMER_0_EN__SHIFT 0x0 24117#define RLC_GPM_TIMER_CTRL__TIMER_1_EN__SHIFT 0x1 24118#define RLC_GPM_TIMER_CTRL__TIMER_2_EN__SHIFT 0x2 24119#define RLC_GPM_TIMER_CTRL__TIMER_3_EN__SHIFT 0x3 24120#define RLC_GPM_TIMER_CTRL__RESERVED__SHIFT 0x4 24121#define RLC_GPM_TIMER_CTRL__TIMER_0_EN_MASK 0x00000001L 24122#define RLC_GPM_TIMER_CTRL__TIMER_1_EN_MASK 0x00000002L 24123#define RLC_GPM_TIMER_CTRL__TIMER_2_EN_MASK 0x00000004L 24124#define RLC_GPM_TIMER_CTRL__TIMER_3_EN_MASK 0x00000008L 24125#define RLC_GPM_TIMER_CTRL__RESERVED_MASK 0xFFFFFFF0L 24126//RLC_LB_CNTR_MAX 24127#define RLC_LB_CNTR_MAX__LB_CNTR_MAX__SHIFT 0x0 24128#define RLC_LB_CNTR_MAX__LB_CNTR_MAX_MASK 0xFFFFFFFFL 24129//RLC_GPM_TIMER_STAT 24130#define RLC_GPM_TIMER_STAT__TIMER_0_STAT__SHIFT 0x0 24131#define RLC_GPM_TIMER_STAT__TIMER_1_STAT__SHIFT 0x1 24132#define RLC_GPM_TIMER_STAT__TIMER_2_STAT__SHIFT 0x2 24133#define RLC_GPM_TIMER_STAT__TIMER_3_STAT__SHIFT 0x3 24134#define RLC_GPM_TIMER_STAT__RESERVED__SHIFT 0x4 24135#define RLC_GPM_TIMER_STAT__TIMER_0_STAT_MASK 0x00000001L 24136#define RLC_GPM_TIMER_STAT__TIMER_1_STAT_MASK 0x00000002L 24137#define RLC_GPM_TIMER_STAT__TIMER_2_STAT_MASK 0x00000004L 24138#define RLC_GPM_TIMER_STAT__TIMER_3_STAT_MASK 0x00000008L 24139#define RLC_GPM_TIMER_STAT__RESERVED_MASK 0xFFFFFFF0L 24140//RLC_GPM_TIMER_INT_3 24141#define RLC_GPM_TIMER_INT_3__TIMER__SHIFT 0x0 24142#define RLC_GPM_TIMER_INT_3__TIMER_MASK 0xFFFFFFFFL 24143//RLC_SERDES_WR_NONCU_MASTER_MASK_1 24144#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SE_MASTER_MASK_1__SHIFT 0x0 24145#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_MASTER_MASK_1__SHIFT 0x10 24146#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_GFX_MASTER_MASK_1__SHIFT 0x11 24147#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__TC0_1_MASTER_MASK__SHIFT 0x12 24148#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_1__SHIFT 0x13 24149#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE4_MASTER_MASK__SHIFT 0x14 24150#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE5_MASTER_MASK__SHIFT 0x15 24151#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE6_MASTER_MASK__SHIFT 0x16 24152#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE7_MASTER_MASK__SHIFT 0x17 24153#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__EA_1_MASTER_MASK__SHIFT 0x18 24154#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED__SHIFT 0x19 24155#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SE_MASTER_MASK_1_MASK 0x0000FFFFL 24156#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_MASTER_MASK_1_MASK 0x00010000L 24157#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_GFX_MASTER_MASK_1_MASK 0x00020000L 24158#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__TC0_1_MASTER_MASK_MASK 0x00040000L 24159#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_1_MASK 0x00080000L 24160#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE4_MASTER_MASK_MASK 0x00100000L 24161#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE5_MASTER_MASK_MASK 0x00200000L 24162#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE6_MASTER_MASK_MASK 0x00400000L 24163#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE7_MASTER_MASK_MASK 0x00800000L 24164#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__EA_1_MASTER_MASK_MASK 0x01000000L 24165#define RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_MASK 0xFE000000L 24166//RLC_SERDES_NONCU_MASTER_BUSY_1 24167#define RLC_SERDES_NONCU_MASTER_BUSY_1__SE_MASTER_BUSY_1__SHIFT 0x0 24168#define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_MASTER_BUSY_1__SHIFT 0x10 24169#define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_GFX_MASTER_BUSY_1__SHIFT 0x11 24170#define RLC_SERDES_NONCU_MASTER_BUSY_1__TC0_MASTER_BUSY_1__SHIFT 0x12 24171#define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_1__SHIFT 0x13 24172#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE4_MASTER_BUSY__SHIFT 0x14 24173#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE5_MASTER_BUSY__SHIFT 0x15 24174#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE6_MASTER_BUSY__SHIFT 0x16 24175#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE7_MASTER_BUSY__SHIFT 0x17 24176#define RLC_SERDES_NONCU_MASTER_BUSY_1__EA_1_MASTER_BUSY__SHIFT 0x18 24177#define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED__SHIFT 0x19 24178#define RLC_SERDES_NONCU_MASTER_BUSY_1__SE_MASTER_BUSY_1_MASK 0x0000FFFFL 24179#define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_MASTER_BUSY_1_MASK 0x00010000L 24180#define RLC_SERDES_NONCU_MASTER_BUSY_1__GC_GFX_MASTER_BUSY_1_MASK 0x00020000L 24181#define RLC_SERDES_NONCU_MASTER_BUSY_1__TC0_MASTER_BUSY_1_MASK 0x00040000L 24182#define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_1_MASK 0x00080000L 24183#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE4_MASTER_BUSY_MASK 0x00100000L 24184#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE5_MASTER_BUSY_MASK 0x00200000L 24185#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE6_MASTER_BUSY_MASK 0x00400000L 24186#define RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE7_MASTER_BUSY_MASK 0x00800000L 24187#define RLC_SERDES_NONCU_MASTER_BUSY_1__EA_1_MASTER_BUSY_MASK 0x01000000L 24188#define RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_MASK 0xFE000000L 24189//RLC_INT_STAT 24190#define RLC_INT_STAT__LAST_CP_RLC_INT_ID__SHIFT 0x0 24191#define RLC_INT_STAT__CP_RLC_INT_PENDING__SHIFT 0x8 24192#define RLC_INT_STAT__RESERVED__SHIFT 0x9 24193#define RLC_INT_STAT__LAST_CP_RLC_INT_ID_MASK 0x000000FFL 24194#define RLC_INT_STAT__CP_RLC_INT_PENDING_MASK 0x00000100L 24195#define RLC_INT_STAT__RESERVED_MASK 0xFFFFFE00L 24196//RLC_LB_CNTL 24197#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE__SHIFT 0x0 24198#define RLC_LB_CNTL__LB_CNT_CP_BUSY__SHIFT 0x1 24199#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE__SHIFT 0x2 24200#define RLC_LB_CNTL__LB_CNT_REG_INC__SHIFT 0x3 24201#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST__SHIFT 0x4 24202#define RLC_LB_CNTL__RESERVED__SHIFT 0xc 24203#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK 0x00000001L 24204#define RLC_LB_CNTL__LB_CNT_CP_BUSY_MASK 0x00000002L 24205#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK 0x00000004L 24206#define RLC_LB_CNTL__LB_CNT_REG_INC_MASK 0x00000008L 24207#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST_MASK 0x00000FF0L 24208#define RLC_LB_CNTL__RESERVED_MASK 0xFFFFF000L 24209//RLC_MGCG_CTRL 24210#define RLC_MGCG_CTRL__MGCG_EN__SHIFT 0x0 24211#define RLC_MGCG_CTRL__SILICON_EN__SHIFT 0x1 24212#define RLC_MGCG_CTRL__SIMULATION_EN__SHIFT 0x2 24213#define RLC_MGCG_CTRL__ON_DELAY__SHIFT 0x3 24214#define RLC_MGCG_CTRL__OFF_HYSTERESIS__SHIFT 0x7 24215#define RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL__SHIFT 0xf 24216#define RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL__SHIFT 0x10 24217#define RLC_MGCG_CTRL__SPARE__SHIFT 0x11 24218#define RLC_MGCG_CTRL__MGCG_EN_MASK 0x00000001L 24219#define RLC_MGCG_CTRL__SILICON_EN_MASK 0x00000002L 24220#define RLC_MGCG_CTRL__SIMULATION_EN_MASK 0x00000004L 24221#define RLC_MGCG_CTRL__ON_DELAY_MASK 0x00000078L 24222#define RLC_MGCG_CTRL__OFF_HYSTERESIS_MASK 0x00007F80L 24223#define RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL_MASK 0x00008000L 24224#define RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL_MASK 0x00010000L 24225#define RLC_MGCG_CTRL__SPARE_MASK 0xFFFE0000L 24226//RLC_LB_CNTR_INIT 24227#define RLC_LB_CNTR_INIT__LB_CNTR_INIT__SHIFT 0x0 24228#define RLC_LB_CNTR_INIT__LB_CNTR_INIT_MASK 0xFFFFFFFFL 24229//RLC_LOAD_BALANCE_CNTR 24230#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR__SHIFT 0x0 24231#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR_MASK 0xFFFFFFFFL 24232//RLC_JUMP_TABLE_RESTORE 24233#define RLC_JUMP_TABLE_RESTORE__ADDR__SHIFT 0x0 24234#define RLC_JUMP_TABLE_RESTORE__ADDR_MASK 0xFFFFFFFFL 24235//RLC_PG_DELAY_2 24236#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE__SHIFT 0x0 24237#define RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT 0x8 24238#define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE__SHIFT 0x10 24239#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE_MASK 0x000000FFL 24240#define RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK 0x0000FF00L 24241#define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE_MASK 0xFFFF0000L 24242//RLC_GPU_CLOCK_COUNT_LSB 24243#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB__SHIFT 0x0 24244#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB_MASK 0xFFFFFFFFL 24245//RLC_GPU_CLOCK_COUNT_MSB 24246#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB__SHIFT 0x0 24247#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB_MASK 0xFFFFFFFFL 24248//RLC_CAPTURE_GPU_CLOCK_COUNT 24249#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE__SHIFT 0x0 24250#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED__SHIFT 0x1 24251#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE_MASK 0x00000001L 24252#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED_MASK 0xFFFFFFFEL 24253//RLC_UCODE_CNTL 24254#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS__SHIFT 0x0 24255#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS_MASK 0xFFFFFFFFL 24256//RLC_GPM_THREAD_RESET 24257#define RLC_GPM_THREAD_RESET__THREAD0_RESET__SHIFT 0x0 24258#define RLC_GPM_THREAD_RESET__THREAD1_RESET__SHIFT 0x1 24259#define RLC_GPM_THREAD_RESET__THREAD2_RESET__SHIFT 0x2 24260#define RLC_GPM_THREAD_RESET__THREAD3_RESET__SHIFT 0x3 24261#define RLC_GPM_THREAD_RESET__RESERVED__SHIFT 0x4 24262#define RLC_GPM_THREAD_RESET__THREAD0_RESET_MASK 0x00000001L 24263#define RLC_GPM_THREAD_RESET__THREAD1_RESET_MASK 0x00000002L 24264#define RLC_GPM_THREAD_RESET__THREAD2_RESET_MASK 0x00000004L 24265#define RLC_GPM_THREAD_RESET__THREAD3_RESET_MASK 0x00000008L 24266#define RLC_GPM_THREAD_RESET__RESERVED_MASK 0xFFFFFFF0L 24267//RLC_GPM_CP_DMA_COMPLETE_T0 24268#define RLC_GPM_CP_DMA_COMPLETE_T0__DATA__SHIFT 0x0 24269#define RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED__SHIFT 0x1 24270#define RLC_GPM_CP_DMA_COMPLETE_T0__DATA_MASK 0x00000001L 24271#define RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED_MASK 0xFFFFFFFEL 24272//RLC_GPM_CP_DMA_COMPLETE_T1 24273#define RLC_GPM_CP_DMA_COMPLETE_T1__DATA__SHIFT 0x0 24274#define RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED__SHIFT 0x1 24275#define RLC_GPM_CP_DMA_COMPLETE_T1__DATA_MASK 0x00000001L 24276#define RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED_MASK 0xFFFFFFFEL 24277//RLC_FIREWALL_VIOLATION 24278#define RLC_FIREWALL_VIOLATION__ADDR__SHIFT 0x0 24279#define RLC_FIREWALL_VIOLATION__ADDR_MASK 0xFFFFFFFFL 24280//RLC_GPM_STAT 24281#define RLC_GPM_STAT__RLC_BUSY__SHIFT 0x0 24282#define RLC_GPM_STAT__GFX_POWER_STATUS__SHIFT 0x1 24283#define RLC_GPM_STAT__GFX_CLOCK_STATUS__SHIFT 0x2 24284#define RLC_GPM_STAT__GFX_LS_STATUS__SHIFT 0x3 24285#define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS__SHIFT 0x4 24286#define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED__SHIFT 0x5 24287#define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED__SHIFT 0x6 24288#define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED__SHIFT 0x7 24289#define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED__SHIFT 0x8 24290#define RLC_GPM_STAT__SAVING_REGISTERS__SHIFT 0x9 24291#define RLC_GPM_STAT__RESTORING_REGISTERS__SHIFT 0xa 24292#define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xb 24293#define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xc 24294#define RLC_GPM_STAT__STATIC_CU_POWERING_UP__SHIFT 0xd 24295#define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN__SHIFT 0xe 24296#define RLC_GPM_STAT__DYN_CU_POWERING_UP__SHIFT 0xf 24297#define RLC_GPM_STAT__DYN_CU_POWERING_DOWN__SHIFT 0x10 24298#define RLC_GPM_STAT__ABORTED_PD_SEQUENCE__SHIFT 0x11 24299#define RLC_GPM_STAT__CMP_power_status__SHIFT 0x12 24300#define RLC_GPM_STAT__GFX_LS_STATUS_3D__SHIFT 0x13 24301#define RLC_GPM_STAT__GFX_CLOCK_STATUS_3D__SHIFT 0x14 24302#define RLC_GPM_STAT__MGCG_OVERRIDE_STATUS__SHIFT 0x15 24303#define RLC_GPM_STAT__RLC_EXEC_ROM_CODE__SHIFT 0x16 24304#define RLC_GPM_STAT__RESERVED__SHIFT 0x17 24305#define RLC_GPM_STAT__PG_ERROR_STATUS__SHIFT 0x18 24306#define RLC_GPM_STAT__RLC_BUSY_MASK 0x00000001L 24307#define RLC_GPM_STAT__GFX_POWER_STATUS_MASK 0x00000002L 24308#define RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK 0x00000004L 24309#define RLC_GPM_STAT__GFX_LS_STATUS_MASK 0x00000008L 24310#define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK 0x00000010L 24311#define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED_MASK 0x00000020L 24312#define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED_MASK 0x00000040L 24313#define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED_MASK 0x00000080L 24314#define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED_MASK 0x00000100L 24315#define RLC_GPM_STAT__SAVING_REGISTERS_MASK 0x00000200L 24316#define RLC_GPM_STAT__RESTORING_REGISTERS_MASK 0x00000400L 24317#define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE_MASK 0x00000800L 24318#define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE_MASK 0x00001000L 24319#define RLC_GPM_STAT__STATIC_CU_POWERING_UP_MASK 0x00002000L 24320#define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN_MASK 0x00004000L 24321#define RLC_GPM_STAT__DYN_CU_POWERING_UP_MASK 0x00008000L 24322#define RLC_GPM_STAT__DYN_CU_POWERING_DOWN_MASK 0x00010000L 24323#define RLC_GPM_STAT__ABORTED_PD_SEQUENCE_MASK 0x00020000L 24324#define RLC_GPM_STAT__CMP_power_status_MASK 0x00040000L 24325#define RLC_GPM_STAT__GFX_LS_STATUS_3D_MASK 0x00080000L 24326#define RLC_GPM_STAT__GFX_CLOCK_STATUS_3D_MASK 0x00100000L 24327#define RLC_GPM_STAT__MGCG_OVERRIDE_STATUS_MASK 0x00200000L 24328#define RLC_GPM_STAT__RLC_EXEC_ROM_CODE_MASK 0x00400000L 24329#define RLC_GPM_STAT__RESERVED_MASK 0x00800000L 24330#define RLC_GPM_STAT__PG_ERROR_STATUS_MASK 0xFF000000L 24331//RLC_GPU_CLOCK_32_RES_SEL 24332#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT 0x0 24333#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED__SHIFT 0x6 24334#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK 0x0000003FL 24335#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED_MASK 0xFFFFFFC0L 24336//RLC_GPU_CLOCK_32 24337#define RLC_GPU_CLOCK_32__GPU_CLOCK_32__SHIFT 0x0 24338#define RLC_GPU_CLOCK_32__GPU_CLOCK_32_MASK 0xFFFFFFFFL 24339//RLC_PG_CNTL 24340#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE__SHIFT 0x0 24341#define RLC_PG_CNTL__GFX_POWER_GATING_SRC__SHIFT 0x1 24342#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE__SHIFT 0x2 24343#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE__SHIFT 0x3 24344#define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE__SHIFT 0x4 24345#define RLC_PG_CNTL__RESERVED__SHIFT 0x5 24346#define RLC_PG_CNTL__PG_OVERRIDE__SHIFT 0xe 24347#define RLC_PG_CNTL__CP_PG_DISABLE__SHIFT 0xf 24348#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE__SHIFT 0x10 24349#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE__SHIFT 0x11 24350#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE__SHIFT 0x12 24351#define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE__SHIFT 0x13 24352#define RLC_PG_CNTL__RESERVED1__SHIFT 0x14 24353#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x00000001L 24354#define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK 0x00000002L 24355#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK 0x00000004L 24356#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK 0x00000008L 24357#define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK 0x00000010L 24358#define RLC_PG_CNTL__RESERVED_MASK 0x00003FE0L 24359#define RLC_PG_CNTL__PG_OVERRIDE_MASK 0x00004000L 24360#define RLC_PG_CNTL__CP_PG_DISABLE_MASK 0x00008000L 24361#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE_MASK 0x00010000L 24362#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK 0x00020000L 24363#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK 0x00040000L 24364#define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE_MASK 0x00080000L 24365#define RLC_PG_CNTL__RESERVED1_MASK 0x00F00000L 24366//RLC_GPM_THREAD_PRIORITY 24367#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY__SHIFT 0x0 24368#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY__SHIFT 0x8 24369#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY__SHIFT 0x10 24370#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY__SHIFT 0x18 24371#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY_MASK 0x000000FFL 24372#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY_MASK 0x0000FF00L 24373#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY_MASK 0x00FF0000L 24374#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY_MASK 0xFF000000L 24375//RLC_GPM_THREAD_ENABLE 24376#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE__SHIFT 0x0 24377#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE__SHIFT 0x1 24378#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE__SHIFT 0x2 24379#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE__SHIFT 0x3 24380#define RLC_GPM_THREAD_ENABLE__RESERVED__SHIFT 0x4 24381#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE_MASK 0x00000001L 24382#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE_MASK 0x00000002L 24383#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE_MASK 0x00000004L 24384#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE_MASK 0x00000008L 24385#define RLC_GPM_THREAD_ENABLE__RESERVED_MASK 0xFFFFFFF0L 24386//RLC_CGTT_MGCG_OVERRIDE 24387#define RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE__SHIFT 0x0 24388#define RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE__SHIFT 0x1 24389#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE__SHIFT 0x2 24390#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE__SHIFT 0x3 24391#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE__SHIFT 0x4 24392#define RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE__SHIFT 0x5 24393#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE__SHIFT 0x6 24394#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE__SHIFT 0x7 24395#define RLC_CGTT_MGCG_OVERRIDE__RESERVED__SHIFT 0x8 24396#define RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK 0x00000001L 24397#define RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK 0x00000002L 24398#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK 0x00000004L 24399#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK 0x00000008L 24400#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK 0x00000010L 24401#define RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK 0x00000020L 24402#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK 0x00000040L 24403#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK 0x00000080L 24404#define RLC_CGTT_MGCG_OVERRIDE__RESERVED_MASK 0xFFFFFF00L 24405//RLC_CGCG_CGLS_CTRL 24406#define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT 0x0 24407#define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT 0x1 24408#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT 0x2 24409#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT 0x8 24410#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER__SHIFT 0x1b 24411#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL__SHIFT 0x1c 24412#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE__SHIFT 0x1d 24413#define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN__SHIFT 0x1f 24414#define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x00000001L 24415#define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK 0x00000002L 24416#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK 0x000000FCL 24417#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK 0x07FFFF00L 24418#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER_MASK 0x08000000L 24419#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK 0x10000000L 24420#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE_MASK 0x60000000L 24421#define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN_MASK 0x80000000L 24422//RLC_CGCG_RAMP_CTRL 24423#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT__SHIFT 0x0 24424#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT__SHIFT 0x4 24425#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT__SHIFT 0x8 24426#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT__SHIFT 0xc 24427#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT__SHIFT 0x10 24428#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT__SHIFT 0x1c 24429#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT_MASK 0x0000000FL 24430#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT_MASK 0x000000F0L 24431#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT_MASK 0x00000F00L 24432#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT_MASK 0x0000F000L 24433#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT_MASK 0x0FFF0000L 24434#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT_MASK 0xF0000000L 24435//RLC_DYN_PG_STATUS 24436#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0 24437#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xFFFFFFFFL 24438//RLC_DYN_PG_REQUEST 24439#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK__SHIFT 0x0 24440#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK_MASK 0xFFFFFFFFL 24441//RLC_PG_DELAY 24442#define RLC_PG_DELAY__POWER_UP_DELAY__SHIFT 0x0 24443#define RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT 0x8 24444#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT 0x10 24445#define RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT 0x18 24446#define RLC_PG_DELAY__POWER_UP_DELAY_MASK 0x000000FFL 24447#define RLC_PG_DELAY__POWER_DOWN_DELAY_MASK 0x0000FF00L 24448#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY_MASK 0x00FF0000L 24449#define RLC_PG_DELAY__MEM_SLEEP_DELAY_MASK 0xFF000000L 24450//RLC_CU_STATUS 24451#define RLC_CU_STATUS__WORK_PENDING__SHIFT 0x0 24452#define RLC_CU_STATUS__WORK_PENDING_MASK 0xFFFFFFFFL 24453//RLC_LB_INIT_CU_MASK 24454#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK__SHIFT 0x0 24455#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK_MASK 0xFFFFFFFFL 24456//RLC_LB_ALWAYS_ACTIVE_CU_MASK 24457#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK__SHIFT 0x0 24458#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK_MASK 0xFFFFFFFFL 24459//RLC_LB_PARAMS 24460#define RLC_LB_PARAMS__SKIP_L2_CHECK__SHIFT 0x0 24461#define RLC_LB_PARAMS__FIFO_SAMPLES__SHIFT 0x1 24462#define RLC_LB_PARAMS__PG_IDLE_SAMPLES__SHIFT 0x8 24463#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL__SHIFT 0x10 24464#define RLC_LB_PARAMS__SKIP_L2_CHECK_MASK 0x00000001L 24465#define RLC_LB_PARAMS__FIFO_SAMPLES_MASK 0x000000FEL 24466#define RLC_LB_PARAMS__PG_IDLE_SAMPLES_MASK 0x0000FF00L 24467#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL_MASK 0xFFFF0000L 24468//RLC_THREAD1_DELAY 24469#define RLC_THREAD1_DELAY__CU_IDEL_DELAY__SHIFT 0x0 24470#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY__SHIFT 0x8 24471#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY__SHIFT 0x10 24472#define RLC_THREAD1_DELAY__SPARE__SHIFT 0x18 24473#define RLC_THREAD1_DELAY__CU_IDEL_DELAY_MASK 0x000000FFL 24474#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY_MASK 0x0000FF00L 24475#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY_MASK 0x00FF0000L 24476#define RLC_THREAD1_DELAY__SPARE_MASK 0xFF000000L 24477//RLC_PG_ALWAYS_ON_CU_MASK 24478#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK__SHIFT 0x0 24479#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK_MASK 0xFFFFFFFFL 24480//RLC_MAX_PG_CU 24481#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT 0x0 24482#define RLC_MAX_PG_CU__SPARE__SHIFT 0x8 24483#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK 0x000000FFL 24484#define RLC_MAX_PG_CU__SPARE_MASK 0xFFFFFF00L 24485//RLC_AUTO_PG_CTRL 24486#define RLC_AUTO_PG_CTRL__AUTO_PG_EN__SHIFT 0x0 24487#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN__SHIFT 0x1 24488#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN__SHIFT 0x2 24489#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT 0x3 24490#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD__SHIFT 0x13 24491#define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK 0x00000001L 24492#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN_MASK 0x00000002L 24493#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK 0x00000004L 24494#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK 0x0007FFF8L 24495#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK 0xFFF80000L 24496//RLC_SMU_GRBM_REG_SAVE_CTRL 24497#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE__SHIFT 0x0 24498#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE__SHIFT 0x1 24499#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE_MASK 0x00000001L 24500#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE_MASK 0xFFFFFFFEL 24501//RLC_SERDES_RD_MASTER_INDEX 24502#define RLC_SERDES_RD_MASTER_INDEX__CU_ID__SHIFT 0x0 24503#define RLC_SERDES_RD_MASTER_INDEX__SH_ID__SHIFT 0x4 24504#define RLC_SERDES_RD_MASTER_INDEX__SE_ID__SHIFT 0x6 24505#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID__SHIFT 0x9 24506#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU__SHIFT 0xc 24507#define RLC_SERDES_RD_MASTER_INDEX__NON_SE__SHIFT 0xd 24508#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID__SHIFT 0x11 24509#define RLC_SERDES_RD_MASTER_INDEX__SPARE__SHIFT 0x13 24510#define RLC_SERDES_RD_MASTER_INDEX__CU_ID_MASK 0x0000000FL 24511#define RLC_SERDES_RD_MASTER_INDEX__SH_ID_MASK 0x00000030L 24512#define RLC_SERDES_RD_MASTER_INDEX__SE_ID_MASK 0x000001C0L 24513#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID_MASK 0x00000E00L 24514#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_MASK 0x00001000L 24515#define RLC_SERDES_RD_MASTER_INDEX__NON_SE_MASK 0x0001E000L 24516#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID_MASK 0x00060000L 24517#define RLC_SERDES_RD_MASTER_INDEX__SPARE_MASK 0xFFF80000L 24518//RLC_SERDES_RD_DATA_0 24519#define RLC_SERDES_RD_DATA_0__DATA__SHIFT 0x0 24520#define RLC_SERDES_RD_DATA_0__DATA_MASK 0xFFFFFFFFL 24521//RLC_SERDES_RD_DATA_1 24522#define RLC_SERDES_RD_DATA_1__DATA__SHIFT 0x0 24523#define RLC_SERDES_RD_DATA_1__DATA_MASK 0xFFFFFFFFL 24524//RLC_SERDES_RD_DATA_2 24525#define RLC_SERDES_RD_DATA_2__DATA__SHIFT 0x0 24526#define RLC_SERDES_RD_DATA_2__DATA_MASK 0xFFFFFFFFL 24527//RLC_SERDES_WR_CU_MASTER_MASK 24528#define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK__SHIFT 0x0 24529#define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK_MASK 0xFFFFFFFFL 24530//RLC_SERDES_WR_NONCU_MASTER_MASK 24531#define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK__SHIFT 0x0 24532#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK__SHIFT 0x10 24533#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK__SHIFT 0x11 24534#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK__SHIFT 0x12 24535#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK__SHIFT 0x13 24536#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK__SHIFT 0x14 24537#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK__SHIFT 0x15 24538#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK__SHIFT 0x16 24539#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK__SHIFT 0x17 24540#define RLC_SERDES_WR_NONCU_MASTER_MASK__EA_0_MASTER_MASK__SHIFT 0x18 24541#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC2_MASTER_MASK__SHIFT 0x19 24542#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED__SHIFT 0x1a 24543#define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK_MASK 0x0000FFFFL 24544#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK_MASK 0x00010000L 24545#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK_MASK 0x00020000L 24546#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK_MASK 0x00040000L 24547#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK_MASK 0x00080000L 24548#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK_MASK 0x00100000L 24549#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK_MASK 0x00200000L 24550#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK_MASK 0x00400000L 24551#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK_MASK 0x00800000L 24552#define RLC_SERDES_WR_NONCU_MASTER_MASK__EA_0_MASTER_MASK_MASK 0x01000000L 24553#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC2_MASTER_MASK_MASK 0x02000000L 24554#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED_MASK 0xFC000000L 24555//RLC_SERDES_WR_CTRL 24556#define RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT 0x0 24557#define RLC_SERDES_WR_CTRL__POWER_DOWN__SHIFT 0x8 24558#define RLC_SERDES_WR_CTRL__POWER_UP__SHIFT 0x9 24559#define RLC_SERDES_WR_CTRL__P1_SELECT__SHIFT 0xa 24560#define RLC_SERDES_WR_CTRL__P2_SELECT__SHIFT 0xb 24561#define RLC_SERDES_WR_CTRL__WRITE_COMMAND__SHIFT 0xc 24562#define RLC_SERDES_WR_CTRL__READ_COMMAND__SHIFT 0xd 24563#define RLC_SERDES_WR_CTRL__RDDATA_RESET__SHIFT 0xe 24564#define RLC_SERDES_WR_CTRL__SHORT_FORMAT__SHIFT 0xf 24565#define RLC_SERDES_WR_CTRL__BPM_DATA__SHIFT 0x10 24566#define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE__SHIFT 0x1a 24567#define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR__SHIFT 0x1b 24568#define RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT 0x1c 24569#define RLC_SERDES_WR_CTRL__BPM_ADDR_MASK 0x000000FFL 24570#define RLC_SERDES_WR_CTRL__POWER_DOWN_MASK 0x00000100L 24571#define RLC_SERDES_WR_CTRL__POWER_UP_MASK 0x00000200L 24572#define RLC_SERDES_WR_CTRL__P1_SELECT_MASK 0x00000400L 24573#define RLC_SERDES_WR_CTRL__P2_SELECT_MASK 0x00000800L 24574#define RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK 0x00001000L 24575#define RLC_SERDES_WR_CTRL__READ_COMMAND_MASK 0x00002000L 24576#define RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK 0x00004000L 24577#define RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK 0x00008000L 24578#define RLC_SERDES_WR_CTRL__BPM_DATA_MASK 0x03FF0000L 24579#define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK 0x04000000L 24580#define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR_MASK 0x08000000L 24581#define RLC_SERDES_WR_CTRL__REG_ADDR_MASK 0xF0000000L 24582//RLC_SERDES_WR_DATA 24583#define RLC_SERDES_WR_DATA__DATA__SHIFT 0x0 24584#define RLC_SERDES_WR_DATA__DATA_MASK 0xFFFFFFFFL 24585//RLC_SERDES_CU_MASTER_BUSY 24586#define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY__SHIFT 0x0 24587#define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY_MASK 0xFFFFFFFFL 24588//RLC_SERDES_NONCU_MASTER_BUSY 24589#define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY__SHIFT 0x0 24590#define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY__SHIFT 0x10 24591#define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY__SHIFT 0x11 24592#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY__SHIFT 0x12 24593#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY__SHIFT 0x13 24594#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY__SHIFT 0x14 24595#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY__SHIFT 0x15 24596#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY__SHIFT 0x16 24597#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY__SHIFT 0x17 24598#define RLC_SERDES_NONCU_MASTER_BUSY__EA_0_MASTER_BUSY__SHIFT 0x18 24599#define RLC_SERDES_NONCU_MASTER_BUSY__TC2_MASTER_BUSY__SHIFT 0x19 24600#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED__SHIFT 0x1a 24601#define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK 0x0000FFFFL 24602#define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK 0x00010000L 24603#define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY_MASK 0x00020000L 24604#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK 0x00040000L 24605#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK 0x00080000L 24606#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY_MASK 0x00100000L 24607#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY_MASK 0x00200000L 24608#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY_MASK 0x00400000L 24609#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY_MASK 0x00800000L 24610#define RLC_SERDES_NONCU_MASTER_BUSY__EA_0_MASTER_BUSY_MASK 0x01000000L 24611#define RLC_SERDES_NONCU_MASTER_BUSY__TC2_MASTER_BUSY_MASK 0x02000000L 24612#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED_MASK 0xFC000000L 24613//RLC_GPM_GENERAL_0 24614#define RLC_GPM_GENERAL_0__DATA__SHIFT 0x0 24615#define RLC_GPM_GENERAL_0__DATA_MASK 0xFFFFFFFFL 24616//RLC_GPM_GENERAL_1 24617#define RLC_GPM_GENERAL_1__DATA__SHIFT 0x0 24618#define RLC_GPM_GENERAL_1__DATA_MASK 0xFFFFFFFFL 24619//RLC_GPM_GENERAL_2 24620#define RLC_GPM_GENERAL_2__DATA__SHIFT 0x0 24621#define RLC_GPM_GENERAL_2__DATA_MASK 0xFFFFFFFFL 24622//RLC_GPM_GENERAL_3 24623#define RLC_GPM_GENERAL_3__DATA__SHIFT 0x0 24624#define RLC_GPM_GENERAL_3__DATA_MASK 0xFFFFFFFFL 24625//RLC_GPM_GENERAL_4 24626#define RLC_GPM_GENERAL_4__DATA__SHIFT 0x0 24627#define RLC_GPM_GENERAL_4__DATA_MASK 0xFFFFFFFFL 24628//RLC_GPM_GENERAL_5 24629#define RLC_GPM_GENERAL_5__DATA__SHIFT 0x0 24630#define RLC_GPM_GENERAL_5__DATA_MASK 0xFFFFFFFFL 24631//RLC_GPM_GENERAL_6 24632#define RLC_GPM_GENERAL_6__DATA__SHIFT 0x0 24633#define RLC_GPM_GENERAL_6__DATA_MASK 0xFFFFFFFFL 24634//RLC_GPM_GENERAL_7 24635#define RLC_GPM_GENERAL_7__DATA__SHIFT 0x0 24636#define RLC_GPM_GENERAL_7__DATA_MASK 0xFFFFFFFFL 24637//RLC_GPM_SCRATCH_ADDR 24638#define RLC_GPM_SCRATCH_ADDR__ADDR__SHIFT 0x0 24639#define RLC_GPM_SCRATCH_ADDR__RESERVED__SHIFT 0x9 24640#define RLC_GPM_SCRATCH_ADDR__ADDR_MASK 0x000001FFL 24641#define RLC_GPM_SCRATCH_ADDR__RESERVED_MASK 0xFFFFFE00L 24642//RLC_GPM_SCRATCH_DATA 24643#define RLC_GPM_SCRATCH_DATA__DATA__SHIFT 0x0 24644#define RLC_GPM_SCRATCH_DATA__DATA_MASK 0xFFFFFFFFL 24645//RLC_STATIC_PG_STATUS 24646#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0 24647#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xFFFFFFFFL 24648//RLC_SPM_MC_CNTL 24649#define RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT 0x0 24650#define RLC_SPM_MC_CNTL__RLC_SPM_POLICY__SHIFT 0x4 24651#define RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR__SHIFT 0x5 24652#define RLC_SPM_MC_CNTL__RLC_SPM_FED__SHIFT 0x6 24653#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER__SHIFT 0x7 24654#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE__SHIFT 0x8 24655#define RLC_SPM_MC_CNTL__RESERVED__SHIFT 0xa 24656#define RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK 0x0000000FL 24657#define RLC_SPM_MC_CNTL__RLC_SPM_POLICY_MASK 0x00000010L 24658#define RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR_MASK 0x00000020L 24659#define RLC_SPM_MC_CNTL__RLC_SPM_FED_MASK 0x00000040L 24660#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER_MASK 0x00000080L 24661#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_MASK 0x00000300L 24662#define RLC_SPM_MC_CNTL__RESERVED_MASK 0xFFFFFC00L 24663//RLC_SPM_INT_CNTL 24664#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL__SHIFT 0x0 24665#define RLC_SPM_INT_CNTL__RESERVED__SHIFT 0x1 24666#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL_MASK 0x00000001L 24667#define RLC_SPM_INT_CNTL__RESERVED_MASK 0xFFFFFFFEL 24668//RLC_SPM_INT_STATUS 24669#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS__SHIFT 0x0 24670#define RLC_SPM_INT_STATUS__RESERVED__SHIFT 0x1 24671#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS_MASK 0x00000001L 24672#define RLC_SPM_INT_STATUS__RESERVED_MASK 0xFFFFFFFEL 24673//RLC_SMU_MESSAGE 24674#define RLC_SMU_MESSAGE__CMD__SHIFT 0x0 24675#define RLC_SMU_MESSAGE__CMD_MASK 0xFFFFFFFFL 24676//RLC_GPM_LOG_SIZE 24677#define RLC_GPM_LOG_SIZE__SIZE__SHIFT 0x0 24678#define RLC_GPM_LOG_SIZE__SIZE_MASK 0xFFFFFFFFL 24679//RLC_PG_DELAY_3 24680#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT 0x0 24681#define RLC_PG_DELAY_3__RESERVED__SHIFT 0x8 24682#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK 0x000000FFL 24683#define RLC_PG_DELAY_3__RESERVED_MASK 0xFFFFFF00L 24684//RLC_GPR_REG1 24685#define RLC_GPR_REG1__DATA__SHIFT 0x0 24686#define RLC_GPR_REG1__DATA_MASK 0xFFFFFFFFL 24687//RLC_GPR_REG2 24688#define RLC_GPR_REG2__DATA__SHIFT 0x0 24689#define RLC_GPR_REG2__DATA_MASK 0xFFFFFFFFL 24690//RLC_GPM_LOG_CONT 24691#define RLC_GPM_LOG_CONT__CONT__SHIFT 0x0 24692#define RLC_GPM_LOG_CONT__CONT_MASK 0xFFFFFFFFL 24693//RLC_GPM_INT_DISABLE_TH0 24694#define RLC_GPM_INT_DISABLE_TH0__DISABLE__SHIFT 0x0 24695#define RLC_GPM_INT_DISABLE_TH0__DISABLE_MASK 0xFFFFFFFFL 24696//RLC_GPM_INT_DISABLE_TH1 24697#define RLC_GPM_INT_DISABLE_TH1__DISABLE__SHIFT 0x0 24698#define RLC_GPM_INT_DISABLE_TH1__DISABLE_MASK 0xFFFFFFFFL 24699//RLC_GPM_INT_FORCE_TH0 24700#define RLC_GPM_INT_FORCE_TH0__FORCE__SHIFT 0x0 24701#define RLC_GPM_INT_FORCE_TH0__FORCE_MASK 0xFFFFFFFFL 24702//RLC_GPM_INT_FORCE_TH1 24703#define RLC_GPM_INT_FORCE_TH1__FORCE__SHIFT 0x0 24704#define RLC_GPM_INT_FORCE_TH1__FORCE_MASK 0xFFFFFFFFL 24705//RLC_SRM_CNTL 24706#define RLC_SRM_CNTL__SRM_ENABLE__SHIFT 0x0 24707#define RLC_SRM_CNTL__AUTO_INCR_ADDR__SHIFT 0x1 24708#define RLC_SRM_CNTL__RESERVED__SHIFT 0x2 24709#define RLC_SRM_CNTL__SRM_ENABLE_MASK 0x00000001L 24710#define RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK 0x00000002L 24711#define RLC_SRM_CNTL__RESERVED_MASK 0xFFFFFFFCL 24712//RLC_SRM_ARAM_ADDR 24713#define RLC_SRM_ARAM_ADDR__ADDR__SHIFT 0x0 24714#define RLC_SRM_ARAM_ADDR__RESERVED__SHIFT 0xc 24715#define RLC_SRM_ARAM_ADDR__ADDR_MASK 0x00000FFFL 24716#define RLC_SRM_ARAM_ADDR__RESERVED_MASK 0xFFFFF000L 24717//RLC_SRM_ARAM_DATA 24718#define RLC_SRM_ARAM_DATA__DATA__SHIFT 0x0 24719#define RLC_SRM_ARAM_DATA__DATA_MASK 0xFFFFFFFFL 24720//RLC_SRM_DRAM_ADDR 24721#define RLC_SRM_DRAM_ADDR__ADDR__SHIFT 0x0 24722#define RLC_SRM_DRAM_ADDR__RESERVED__SHIFT 0xc 24723#define RLC_SRM_DRAM_ADDR__ADDR_MASK 0x00000FFFL 24724#define RLC_SRM_DRAM_ADDR__RESERVED_MASK 0xFFFFF000L 24725//RLC_SRM_DRAM_DATA 24726#define RLC_SRM_DRAM_DATA__DATA__SHIFT 0x0 24727#define RLC_SRM_DRAM_DATA__DATA_MASK 0xFFFFFFFFL 24728//RLC_SRM_GPM_COMMAND 24729#define RLC_SRM_GPM_COMMAND__OP__SHIFT 0x0 24730#define RLC_SRM_GPM_COMMAND__INDEX_CNTL__SHIFT 0x1 24731#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM__SHIFT 0x2 24732#define RLC_SRM_GPM_COMMAND__SIZE__SHIFT 0x5 24733#define RLC_SRM_GPM_COMMAND__START_OFFSET__SHIFT 0x11 24734#define RLC_SRM_GPM_COMMAND__RESERVED1__SHIFT 0x1d 24735#define RLC_SRM_GPM_COMMAND__DEST_MEMORY__SHIFT 0x1f 24736#define RLC_SRM_GPM_COMMAND__OP_MASK 0x00000001L 24737#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_MASK 0x00000002L 24738#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM_MASK 0x0000001CL 24739#define RLC_SRM_GPM_COMMAND__SIZE_MASK 0x0001FFE0L 24740#define RLC_SRM_GPM_COMMAND__START_OFFSET_MASK 0x1FFE0000L 24741#define RLC_SRM_GPM_COMMAND__RESERVED1_MASK 0x60000000L 24742#define RLC_SRM_GPM_COMMAND__DEST_MEMORY_MASK 0x80000000L 24743//RLC_SRM_GPM_COMMAND_STATUS 24744#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0 24745#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1 24746#define RLC_SRM_GPM_COMMAND_STATUS__RESERVED__SHIFT 0x2 24747#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY_MASK 0x00000001L 24748#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL_MASK 0x00000002L 24749#define RLC_SRM_GPM_COMMAND_STATUS__RESERVED_MASK 0xFFFFFFFCL 24750//RLC_SRM_RLCV_COMMAND 24751#define RLC_SRM_RLCV_COMMAND__OP__SHIFT 0x0 24752#define RLC_SRM_RLCV_COMMAND__RESERVED__SHIFT 0x1 24753#define RLC_SRM_RLCV_COMMAND__SIZE__SHIFT 0x4 24754#define RLC_SRM_RLCV_COMMAND__START_OFFSET__SHIFT 0x10 24755#define RLC_SRM_RLCV_COMMAND__RESERVED1__SHIFT 0x1c 24756#define RLC_SRM_RLCV_COMMAND__DEST_MEMORY__SHIFT 0x1f 24757#define RLC_SRM_RLCV_COMMAND__OP_MASK 0x00000001L 24758#define RLC_SRM_RLCV_COMMAND__RESERVED_MASK 0x0000000EL 24759#define RLC_SRM_RLCV_COMMAND__SIZE_MASK 0x0000FFF0L 24760#define RLC_SRM_RLCV_COMMAND__START_OFFSET_MASK 0x0FFF0000L 24761#define RLC_SRM_RLCV_COMMAND__RESERVED1_MASK 0x70000000L 24762#define RLC_SRM_RLCV_COMMAND__DEST_MEMORY_MASK 0x80000000L 24763//RLC_SRM_RLCV_COMMAND_STATUS 24764#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0 24765#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1 24766#define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED__SHIFT 0x2 24767#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY_MASK 0x00000001L 24768#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL_MASK 0x00000002L 24769#define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED_MASK 0xFFFFFFFCL 24770//RLC_SRM_INDEX_CNTL_ADDR_0 24771#define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS__SHIFT 0x0 24772#define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED__SHIFT 0x10 24773#define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS_MASK 0x0000FFFFL 24774#define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED_MASK 0xFFFF0000L 24775//RLC_SRM_INDEX_CNTL_ADDR_1 24776#define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS__SHIFT 0x0 24777#define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED__SHIFT 0x10 24778#define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS_MASK 0x0000FFFFL 24779#define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED_MASK 0xFFFF0000L 24780//RLC_SRM_INDEX_CNTL_ADDR_2 24781#define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS__SHIFT 0x0 24782#define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED__SHIFT 0x10 24783#define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS_MASK 0x0000FFFFL 24784#define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED_MASK 0xFFFF0000L 24785//RLC_SRM_INDEX_CNTL_ADDR_3 24786#define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS__SHIFT 0x0 24787#define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED__SHIFT 0x10 24788#define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS_MASK 0x0000FFFFL 24789#define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED_MASK 0xFFFF0000L 24790//RLC_SRM_INDEX_CNTL_ADDR_4 24791#define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS__SHIFT 0x0 24792#define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED__SHIFT 0x10 24793#define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS_MASK 0x0000FFFFL 24794#define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED_MASK 0xFFFF0000L 24795//RLC_SRM_INDEX_CNTL_ADDR_5 24796#define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS__SHIFT 0x0 24797#define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED__SHIFT 0x10 24798#define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS_MASK 0x0000FFFFL 24799#define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED_MASK 0xFFFF0000L 24800//RLC_SRM_INDEX_CNTL_ADDR_6 24801#define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS__SHIFT 0x0 24802#define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED__SHIFT 0x10 24803#define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS_MASK 0x0000FFFFL 24804#define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED_MASK 0xFFFF0000L 24805//RLC_SRM_INDEX_CNTL_ADDR_7 24806#define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS__SHIFT 0x0 24807#define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED__SHIFT 0x10 24808#define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS_MASK 0x0000FFFFL 24809#define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED_MASK 0xFFFF0000L 24810//RLC_SRM_INDEX_CNTL_DATA_0 24811#define RLC_SRM_INDEX_CNTL_DATA_0__DATA__SHIFT 0x0 24812#define RLC_SRM_INDEX_CNTL_DATA_0__DATA_MASK 0xFFFFFFFFL 24813//RLC_SRM_INDEX_CNTL_DATA_1 24814#define RLC_SRM_INDEX_CNTL_DATA_1__DATA__SHIFT 0x0 24815#define RLC_SRM_INDEX_CNTL_DATA_1__DATA_MASK 0xFFFFFFFFL 24816//RLC_SRM_INDEX_CNTL_DATA_2 24817#define RLC_SRM_INDEX_CNTL_DATA_2__DATA__SHIFT 0x0 24818#define RLC_SRM_INDEX_CNTL_DATA_2__DATA_MASK 0xFFFFFFFFL 24819//RLC_SRM_INDEX_CNTL_DATA_3 24820#define RLC_SRM_INDEX_CNTL_DATA_3__DATA__SHIFT 0x0 24821#define RLC_SRM_INDEX_CNTL_DATA_3__DATA_MASK 0xFFFFFFFFL 24822//RLC_SRM_INDEX_CNTL_DATA_4 24823#define RLC_SRM_INDEX_CNTL_DATA_4__DATA__SHIFT 0x0 24824#define RLC_SRM_INDEX_CNTL_DATA_4__DATA_MASK 0xFFFFFFFFL 24825//RLC_SRM_INDEX_CNTL_DATA_5 24826#define RLC_SRM_INDEX_CNTL_DATA_5__DATA__SHIFT 0x0 24827#define RLC_SRM_INDEX_CNTL_DATA_5__DATA_MASK 0xFFFFFFFFL 24828//RLC_SRM_INDEX_CNTL_DATA_6 24829#define RLC_SRM_INDEX_CNTL_DATA_6__DATA__SHIFT 0x0 24830#define RLC_SRM_INDEX_CNTL_DATA_6__DATA_MASK 0xFFFFFFFFL 24831//RLC_SRM_INDEX_CNTL_DATA_7 24832#define RLC_SRM_INDEX_CNTL_DATA_7__DATA__SHIFT 0x0 24833#define RLC_SRM_INDEX_CNTL_DATA_7__DATA_MASK 0xFFFFFFFFL 24834//RLC_SRM_STAT 24835#define RLC_SRM_STAT__SRM_BUSY__SHIFT 0x0 24836#define RLC_SRM_STAT__SRM_BUSY_DELAY__SHIFT 0x1 24837#define RLC_SRM_STAT__RESERVED__SHIFT 0x2 24838#define RLC_SRM_STAT__SRM_BUSY_MASK 0x00000001L 24839#define RLC_SRM_STAT__SRM_BUSY_DELAY_MASK 0x00000002L 24840#define RLC_SRM_STAT__RESERVED_MASK 0xFFFFFFFCL 24841//RLC_SRM_GPM_ABORT 24842#define RLC_SRM_GPM_ABORT__ABORT__SHIFT 0x0 24843#define RLC_SRM_GPM_ABORT__RESERVED__SHIFT 0x1 24844#define RLC_SRM_GPM_ABORT__ABORT_MASK 0x00000001L 24845#define RLC_SRM_GPM_ABORT__RESERVED_MASK 0xFFFFFFFEL 24846//RLC_CSIB_ADDR_LO 24847#define RLC_CSIB_ADDR_LO__ADDRESS__SHIFT 0x0 24848#define RLC_CSIB_ADDR_LO__ADDRESS_MASK 0xFFFFFFFFL 24849//RLC_CSIB_ADDR_HI 24850#define RLC_CSIB_ADDR_HI__ADDRESS__SHIFT 0x0 24851#define RLC_CSIB_ADDR_HI__ADDRESS_MASK 0x0000FFFFL 24852//RLC_CSIB_LENGTH 24853#define RLC_CSIB_LENGTH__LENGTH__SHIFT 0x0 24854#define RLC_CSIB_LENGTH__LENGTH_MASK 0xFFFFFFFFL 24855//RLC_SMU_COMMAND 24856#define RLC_SMU_COMMAND__CMD__SHIFT 0x0 24857#define RLC_SMU_COMMAND__CMD_MASK 0xFFFFFFFFL 24858//RLC_CP_SCHEDULERS 24859#define RLC_CP_SCHEDULERS__scheduler0__SHIFT 0x0 24860#define RLC_CP_SCHEDULERS__scheduler1__SHIFT 0x8 24861#define RLC_CP_SCHEDULERS__scheduler2__SHIFT 0x10 24862#define RLC_CP_SCHEDULERS__scheduler3__SHIFT 0x18 24863#define RLC_CP_SCHEDULERS__scheduler0_MASK 0x000000FFL 24864#define RLC_CP_SCHEDULERS__scheduler1_MASK 0x0000FF00L 24865#define RLC_CP_SCHEDULERS__scheduler2_MASK 0x00FF0000L 24866#define RLC_CP_SCHEDULERS__scheduler3_MASK 0xFF000000L 24867//RLC_SMU_ARGUMENT_1 24868#define RLC_SMU_ARGUMENT_1__ARG__SHIFT 0x0 24869#define RLC_SMU_ARGUMENT_1__ARG_MASK 0xFFFFFFFFL 24870//RLC_SMU_ARGUMENT_2 24871#define RLC_SMU_ARGUMENT_2__ARG__SHIFT 0x0 24872#define RLC_SMU_ARGUMENT_2__ARG_MASK 0xFFFFFFFFL 24873//RLC_GPM_GENERAL_8 24874#define RLC_GPM_GENERAL_8__DATA__SHIFT 0x0 24875#define RLC_GPM_GENERAL_8__DATA_MASK 0xFFFFFFFFL 24876//RLC_GPM_GENERAL_9 24877#define RLC_GPM_GENERAL_9__DATA__SHIFT 0x0 24878#define RLC_GPM_GENERAL_9__DATA_MASK 0xFFFFFFFFL 24879//RLC_GPM_GENERAL_10 24880#define RLC_GPM_GENERAL_10__DATA__SHIFT 0x0 24881#define RLC_GPM_GENERAL_10__DATA_MASK 0xFFFFFFFFL 24882//RLC_GPM_GENERAL_11 24883#define RLC_GPM_GENERAL_11__DATA__SHIFT 0x0 24884#define RLC_GPM_GENERAL_11__DATA_MASK 0xFFFFFFFFL 24885//RLC_GPM_GENERAL_12 24886#define RLC_GPM_GENERAL_12__DATA__SHIFT 0x0 24887#define RLC_GPM_GENERAL_12__DATA_MASK 0xFFFFFFFFL 24888//RLC_GPM_UTCL1_CNTL_0 24889#define RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT__SHIFT 0x0 24890#define RLC_GPM_UTCL1_CNTL_0__DROP_MODE__SHIFT 0x18 24891#define RLC_GPM_UTCL1_CNTL_0__BYPASS__SHIFT 0x19 24892#define RLC_GPM_UTCL1_CNTL_0__INVALIDATE__SHIFT 0x1a 24893#define RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE__SHIFT 0x1b 24894#define RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP__SHIFT 0x1c 24895#define RLC_GPM_UTCL1_CNTL_0__FORCE_SD_VMID_DIRTY__SHIFT 0x1d 24896#define RLC_GPM_UTCL1_CNTL_0__RESERVED__SHIFT 0x1e 24897#define RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL 24898#define RLC_GPM_UTCL1_CNTL_0__DROP_MODE_MASK 0x01000000L 24899#define RLC_GPM_UTCL1_CNTL_0__BYPASS_MASK 0x02000000L 24900#define RLC_GPM_UTCL1_CNTL_0__INVALIDATE_MASK 0x04000000L 24901#define RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE_MASK 0x08000000L 24902#define RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP_MASK 0x10000000L 24903#define RLC_GPM_UTCL1_CNTL_0__FORCE_SD_VMID_DIRTY_MASK 0x20000000L 24904#define RLC_GPM_UTCL1_CNTL_0__RESERVED_MASK 0xC0000000L 24905//RLC_GPM_UTCL1_CNTL_1 24906#define RLC_GPM_UTCL1_CNTL_1__XNACK_REDO_TIMER_CNT__SHIFT 0x0 24907#define RLC_GPM_UTCL1_CNTL_1__DROP_MODE__SHIFT 0x18 24908#define RLC_GPM_UTCL1_CNTL_1__BYPASS__SHIFT 0x19 24909#define RLC_GPM_UTCL1_CNTL_1__INVALIDATE__SHIFT 0x1a 24910#define RLC_GPM_UTCL1_CNTL_1__FRAG_LIMIT_MODE__SHIFT 0x1b 24911#define RLC_GPM_UTCL1_CNTL_1__FORCE_SNOOP__SHIFT 0x1c 24912#define RLC_GPM_UTCL1_CNTL_1__FORCE_SD_VMID_DIRTY__SHIFT 0x1d 24913#define RLC_GPM_UTCL1_CNTL_1__RESERVED__SHIFT 0x1e 24914#define RLC_GPM_UTCL1_CNTL_1__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL 24915#define RLC_GPM_UTCL1_CNTL_1__DROP_MODE_MASK 0x01000000L 24916#define RLC_GPM_UTCL1_CNTL_1__BYPASS_MASK 0x02000000L 24917#define RLC_GPM_UTCL1_CNTL_1__INVALIDATE_MASK 0x04000000L 24918#define RLC_GPM_UTCL1_CNTL_1__FRAG_LIMIT_MODE_MASK 0x08000000L 24919#define RLC_GPM_UTCL1_CNTL_1__FORCE_SNOOP_MASK 0x10000000L 24920#define RLC_GPM_UTCL1_CNTL_1__FORCE_SD_VMID_DIRTY_MASK 0x20000000L 24921#define RLC_GPM_UTCL1_CNTL_1__RESERVED_MASK 0xC0000000L 24922//RLC_GPM_UTCL1_CNTL_2 24923#define RLC_GPM_UTCL1_CNTL_2__XNACK_REDO_TIMER_CNT__SHIFT 0x0 24924#define RLC_GPM_UTCL1_CNTL_2__DROP_MODE__SHIFT 0x18 24925#define RLC_GPM_UTCL1_CNTL_2__BYPASS__SHIFT 0x19 24926#define RLC_GPM_UTCL1_CNTL_2__INVALIDATE__SHIFT 0x1a 24927#define RLC_GPM_UTCL1_CNTL_2__FRAG_LIMIT_MODE__SHIFT 0x1b 24928#define RLC_GPM_UTCL1_CNTL_2__FORCE_SNOOP__SHIFT 0x1c 24929#define RLC_GPM_UTCL1_CNTL_2__FORCE_SD_VMID_DIRTY__SHIFT 0x1d 24930#define RLC_GPM_UTCL1_CNTL_2__RESERVED__SHIFT 0x1e 24931#define RLC_GPM_UTCL1_CNTL_2__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL 24932#define RLC_GPM_UTCL1_CNTL_2__DROP_MODE_MASK 0x01000000L 24933#define RLC_GPM_UTCL1_CNTL_2__BYPASS_MASK 0x02000000L 24934#define RLC_GPM_UTCL1_CNTL_2__INVALIDATE_MASK 0x04000000L 24935#define RLC_GPM_UTCL1_CNTL_2__FRAG_LIMIT_MODE_MASK 0x08000000L 24936#define RLC_GPM_UTCL1_CNTL_2__FORCE_SNOOP_MASK 0x10000000L 24937#define RLC_GPM_UTCL1_CNTL_2__FORCE_SD_VMID_DIRTY_MASK 0x20000000L 24938#define RLC_GPM_UTCL1_CNTL_2__RESERVED_MASK 0xC0000000L 24939//RLC_SPM_UTCL1_CNTL 24940#define RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 24941#define RLC_SPM_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 24942#define RLC_SPM_UTCL1_CNTL__BYPASS__SHIFT 0x19 24943#define RLC_SPM_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a 24944#define RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b 24945#define RLC_SPM_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c 24946#define RLC_SPM_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d 24947#define RLC_SPM_UTCL1_CNTL__RESERVED__SHIFT 0x1e 24948#define RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL 24949#define RLC_SPM_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L 24950#define RLC_SPM_UTCL1_CNTL__BYPASS_MASK 0x02000000L 24951#define RLC_SPM_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L 24952#define RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L 24953#define RLC_SPM_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L 24954#define RLC_SPM_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L 24955#define RLC_SPM_UTCL1_CNTL__RESERVED_MASK 0xC0000000L 24956//RLC_UTCL1_STATUS_2 24957#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY__SHIFT 0x0 24958#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY__SHIFT 0x1 24959#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY__SHIFT 0x2 24960#define RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY__SHIFT 0x3 24961#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_BUSY__SHIFT 0x4 24962#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans__SHIFT 0x5 24963#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans__SHIFT 0x6 24964#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans__SHIFT 0x7 24965#define RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans__SHIFT 0x8 24966#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_StallOnTrans__SHIFT 0x9 24967#define RLC_UTCL1_STATUS_2__RESERVED__SHIFT 0xa 24968#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY_MASK 0x00000001L 24969#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY_MASK 0x00000002L 24970#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY_MASK 0x00000004L 24971#define RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY_MASK 0x00000008L 24972#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_BUSY_MASK 0x00000010L 24973#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans_MASK 0x00000020L 24974#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans_MASK 0x00000040L 24975#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans_MASK 0x00000080L 24976#define RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans_MASK 0x00000100L 24977#define RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_StallOnTrans_MASK 0x00000200L 24978#define RLC_UTCL1_STATUS_2__RESERVED_MASK 0xFFFFFC00L 24979//RLC_LB_THR_CONFIG_2 24980#define RLC_LB_THR_CONFIG_2__DATA__SHIFT 0x0 24981#define RLC_LB_THR_CONFIG_2__DATA_MASK 0xFFFFFFFFL 24982//RLC_LB_THR_CONFIG_3 24983#define RLC_LB_THR_CONFIG_3__DATA__SHIFT 0x0 24984#define RLC_LB_THR_CONFIG_3__DATA_MASK 0xFFFFFFFFL 24985//RLC_LB_THR_CONFIG_4 24986#define RLC_LB_THR_CONFIG_4__DATA__SHIFT 0x0 24987#define RLC_LB_THR_CONFIG_4__DATA_MASK 0xFFFFFFFFL 24988//RLC_SPM_UTCL1_ERROR_1 24989#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqError__SHIFT 0x0 24990#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2 24991#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6 24992#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqError_MASK 0x00000003L 24993#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL 24994#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L 24995//RLC_SPM_UTCL1_ERROR_2 24996#define RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0 24997#define RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL 24998//RLC_GPM_UTCL1_TH0_ERROR_1 24999#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError__SHIFT 0x0 25000#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2
25001#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6 25002#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError_MASK 0x00000003L 25003#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL 25004#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L 25005//RLC_LB_THR_CONFIG_1 25006#define RLC_LB_THR_CONFIG_1__DATA__SHIFT 0x0 25007#define RLC_LB_THR_CONFIG_1__DATA_MASK 0xFFFFFFFFL 25008//RLC_GPM_UTCL1_TH0_ERROR_2 25009#define RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0 25010#define RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL 25011//RLC_GPM_UTCL1_TH1_ERROR_1 25012#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqError__SHIFT 0x0 25013#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2 25014#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6 25015#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqError_MASK 0x00000003L 25016#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL 25017#define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L 25018//RLC_GPM_UTCL1_TH1_ERROR_2 25019#define RLC_GPM_UTCL1_TH1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0 25020#define RLC_GPM_UTCL1_TH1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL 25021//RLC_GPM_UTCL1_TH2_ERROR_1 25022#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqError__SHIFT 0x0 25023#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2 25024#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6 25025#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqError_MASK 0x00000003L 25026#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL 25027#define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L 25028//RLC_GPM_UTCL1_TH2_ERROR_2 25029#define RLC_GPM_UTCL1_TH2_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0 25030#define RLC_GPM_UTCL1_TH2_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL 25031//RLC_CGCG_CGLS_CTRL_3D 25032#define RLC_CGCG_CGLS_CTRL_3D__CGCG_EN__SHIFT 0x0 25033#define RLC_CGCG_CGLS_CTRL_3D__CGLS_EN__SHIFT 0x1 25034#define RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT 0x2 25035#define RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT 0x8 25036#define RLC_CGCG_CGLS_CTRL_3D__CGCG_CONTROLLER__SHIFT 0x1b 25037#define RLC_CGCG_CGLS_CTRL_3D__CGCG_REG_CTRL__SHIFT 0x1c 25038#define RLC_CGCG_CGLS_CTRL_3D__SLEEP_MODE__SHIFT 0x1d 25039#define RLC_CGCG_CGLS_CTRL_3D__SIM_SILICON_EN__SHIFT 0x1f 25040#define RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK 0x00000001L 25041#define RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK 0x00000002L 25042#define RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK 0x000000FCL 25043#define RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK 0x07FFFF00L 25044#define RLC_CGCG_CGLS_CTRL_3D__CGCG_CONTROLLER_MASK 0x08000000L 25045#define RLC_CGCG_CGLS_CTRL_3D__CGCG_REG_CTRL_MASK 0x10000000L 25046#define RLC_CGCG_CGLS_CTRL_3D__SLEEP_MODE_MASK 0x60000000L 25047#define RLC_CGCG_CGLS_CTRL_3D__SIM_SILICON_EN_MASK 0x80000000L 25048//RLC_CGCG_RAMP_CTRL_3D 25049#define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_START_UNIT__SHIFT 0x0 25050#define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_STEP_UNIT__SHIFT 0x4 25051#define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_START_UNIT__SHIFT 0x8 25052#define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_STEP_UNIT__SHIFT 0xc 25053#define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_CNT__SHIFT 0x10 25054#define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_UNIT__SHIFT 0x1c 25055#define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_START_UNIT_MASK 0x0000000FL 25056#define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_STEP_UNIT_MASK 0x000000F0L 25057#define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_START_UNIT_MASK 0x00000F00L 25058#define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_STEP_UNIT_MASK 0x0000F000L 25059#define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_CNT_MASK 0x0FFF0000L 25060#define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_UNIT_MASK 0xF0000000L 25061//RLC_SEMAPHORE_0 25062#define RLC_SEMAPHORE_0__CLIENT_ID__SHIFT 0x0 25063#define RLC_SEMAPHORE_0__RESERVED__SHIFT 0x5 25064#define RLC_SEMAPHORE_0__CLIENT_ID_MASK 0x0000001FL 25065#define RLC_SEMAPHORE_0__RESERVED_MASK 0xFFFFFFE0L 25066//RLC_SEMAPHORE_1 25067#define RLC_SEMAPHORE_1__CLIENT_ID__SHIFT 0x0 25068#define RLC_SEMAPHORE_1__RESERVED__SHIFT 0x5 25069#define RLC_SEMAPHORE_1__CLIENT_ID_MASK 0x0000001FL 25070#define RLC_SEMAPHORE_1__RESERVED_MASK 0xFFFFFFE0L 25071//RLC_CP_EOF_INT 25072#define RLC_CP_EOF_INT__INTERRUPT__SHIFT 0x0 25073#define RLC_CP_EOF_INT__RESERVED__SHIFT 0x1 25074#define RLC_CP_EOF_INT__INTERRUPT_MASK 0x00000001L 25075#define RLC_CP_EOF_INT__RESERVED_MASK 0xFFFFFFFEL 25076//RLC_CP_EOF_INT_CNT 25077#define RLC_CP_EOF_INT_CNT__CNT__SHIFT 0x0 25078#define RLC_CP_EOF_INT_CNT__CNT_MASK 0xFFFFFFFFL 25079//RLC_SPARE_INT 25080#define RLC_SPARE_INT__INTERRUPT__SHIFT 0x0 25081#define RLC_SPARE_INT__RESERVED__SHIFT 0x1 25082#define RLC_SPARE_INT__INTERRUPT_MASK 0x00000001L 25083#define RLC_SPARE_INT__RESERVED_MASK 0xFFFFFFFEL 25084//RLC_PREWALKER_UTCL1_CNTL 25085#define RLC_PREWALKER_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 25086#define RLC_PREWALKER_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 25087#define RLC_PREWALKER_UTCL1_CNTL__BYPASS__SHIFT 0x19 25088#define RLC_PREWALKER_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a 25089#define RLC_PREWALKER_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b 25090#define RLC_PREWALKER_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c 25091#define RLC_PREWALKER_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d 25092#define RLC_PREWALKER_UTCL1_CNTL__RESERVED__SHIFT 0x1e 25093#define RLC_PREWALKER_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL 25094#define RLC_PREWALKER_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L 25095#define RLC_PREWALKER_UTCL1_CNTL__BYPASS_MASK 0x02000000L 25096#define RLC_PREWALKER_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L 25097#define RLC_PREWALKER_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L 25098#define RLC_PREWALKER_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L 25099#define RLC_PREWALKER_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L 25100#define RLC_PREWALKER_UTCL1_CNTL__RESERVED_MASK 0xC0000000L 25101//RLC_PREWALKER_UTCL1_TRIG 25102#define RLC_PREWALKER_UTCL1_TRIG__VALID__SHIFT 0x0 25103#define RLC_PREWALKER_UTCL1_TRIG__VMID__SHIFT 0x1 25104#define RLC_PREWALKER_UTCL1_TRIG__PRIME_MODE__SHIFT 0x5 25105#define RLC_PREWALKER_UTCL1_TRIG__READ_PERM__SHIFT 0x6 25106#define RLC_PREWALKER_UTCL1_TRIG__WRITE_PERM__SHIFT 0x7 25107#define RLC_PREWALKER_UTCL1_TRIG__EXEC_PERM__SHIFT 0x8 25108#define RLC_PREWALKER_UTCL1_TRIG__RESERVED__SHIFT 0x9 25109#define RLC_PREWALKER_UTCL1_TRIG__READY__SHIFT 0x1f 25110#define RLC_PREWALKER_UTCL1_TRIG__VALID_MASK 0x00000001L 25111#define RLC_PREWALKER_UTCL1_TRIG__VMID_MASK 0x0000001EL 25112#define RLC_PREWALKER_UTCL1_TRIG__PRIME_MODE_MASK 0x00000020L 25113#define RLC_PREWALKER_UTCL1_TRIG__READ_PERM_MASK 0x00000040L 25114#define RLC_PREWALKER_UTCL1_TRIG__WRITE_PERM_MASK 0x00000080L 25115#define RLC_PREWALKER_UTCL1_TRIG__EXEC_PERM_MASK 0x00000100L 25116#define RLC_PREWALKER_UTCL1_TRIG__RESERVED_MASK 0x7FFFFE00L 25117#define RLC_PREWALKER_UTCL1_TRIG__READY_MASK 0x80000000L 25118//RLC_PREWALKER_UTCL1_ADDR_LSB 25119#define RLC_PREWALKER_UTCL1_ADDR_LSB__ADDR_LSB__SHIFT 0x0 25120#define RLC_PREWALKER_UTCL1_ADDR_LSB__ADDR_LSB_MASK 0xFFFFFFFFL 25121//RLC_PREWALKER_UTCL1_ADDR_MSB 25122#define RLC_PREWALKER_UTCL1_ADDR_MSB__ADDR_MSB__SHIFT 0x0 25123#define RLC_PREWALKER_UTCL1_ADDR_MSB__ADDR_MSB_MASK 0x0000FFFFL 25124//RLC_PREWALKER_UTCL1_SIZE_LSB 25125#define RLC_PREWALKER_UTCL1_SIZE_LSB__SIZE_LSB__SHIFT 0x0 25126#define RLC_PREWALKER_UTCL1_SIZE_LSB__SIZE_LSB_MASK 0xFFFFFFFFL 25127//RLC_PREWALKER_UTCL1_SIZE_MSB 25128#define RLC_PREWALKER_UTCL1_SIZE_MSB__SIZE_MSB__SHIFT 0x0 25129#define RLC_PREWALKER_UTCL1_SIZE_MSB__SIZE_MSB_MASK 0x00000003L 25130//RLC_DSM_TRIG 25131//RLC_UTCL1_STATUS 25132#define RLC_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 25133#define RLC_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 25134#define RLC_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 25135#define RLC_UTCL1_STATUS__RESERVED__SHIFT 0x3 25136#define RLC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 25137#define RLC_UTCL1_STATUS__RESERVED_1__SHIFT 0xe 25138#define RLC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 25139#define RLC_UTCL1_STATUS__RESERVED_2__SHIFT 0x16 25140#define RLC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 25141#define RLC_UTCL1_STATUS__RESERVED_3__SHIFT 0x1e 25142#define RLC_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L 25143#define RLC_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L 25144#define RLC_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L 25145#define RLC_UTCL1_STATUS__RESERVED_MASK 0x000000F8L 25146#define RLC_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L 25147#define RLC_UTCL1_STATUS__RESERVED_1_MASK 0x0000C000L 25148#define RLC_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L 25149#define RLC_UTCL1_STATUS__RESERVED_2_MASK 0x00C00000L 25150#define RLC_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L 25151#define RLC_UTCL1_STATUS__RESERVED_3_MASK 0xC0000000L 25152//RLC_R2I_CNTL_0 25153#define RLC_R2I_CNTL_0__Data__SHIFT 0x0 25154#define RLC_R2I_CNTL_0__Data_MASK 0xFFFFFFFFL 25155//RLC_R2I_CNTL_1 25156#define RLC_R2I_CNTL_1__Data__SHIFT 0x0 25157#define RLC_R2I_CNTL_1__Data_MASK 0xFFFFFFFFL 25158//RLC_R2I_CNTL_2 25159#define RLC_R2I_CNTL_2__Data__SHIFT 0x0 25160#define RLC_R2I_CNTL_2__Data_MASK 0xFFFFFFFFL 25161//RLC_R2I_CNTL_3 25162#define RLC_R2I_CNTL_3__Data__SHIFT 0x0 25163#define RLC_R2I_CNTL_3__Data_MASK 0xFFFFFFFFL 25164//RLC_UTCL2_CNTL 25165#define RLC_UTCL2_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x0 25166#define RLC_UTCL2_CNTL__RESERVED__SHIFT 0x1 25167#define RLC_UTCL2_CNTL__MTYPE_NO_PTE_MODE_MASK 0x00000001L 25168#define RLC_UTCL2_CNTL__RESERVED_MASK 0xFFFFFFFEL 25169//RLC_LBPW_CU_STAT 25170#define RLC_LBPW_CU_STAT__MAX_CU__SHIFT 0x0 25171#define RLC_LBPW_CU_STAT__ON_CU__SHIFT 0x10 25172#define RLC_LBPW_CU_STAT__MAX_CU_MASK 0x0000FFFFL 25173#define RLC_LBPW_CU_STAT__ON_CU_MASK 0xFFFF0000L 25174//RLC_DS_CNTL 25175#define RLC_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK__SHIFT 0x0 25176#define RLC_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK__SHIFT 0x1 25177#define RLC_DS_CNTL__RESRVED__SHIFT 0x2 25178#define RLC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK__SHIFT 0x10 25179#define RLC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK__SHIFT 0x11 25180#define RLC_DS_CNTL__RESRVED_1__SHIFT 0x12 25181#define RLC_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK_MASK 0x00000001L 25182#define RLC_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK_MASK 0x00000002L 25183#define RLC_DS_CNTL__RESRVED_MASK 0x0000FFFCL 25184#define RLC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK_MASK 0x00010000L 25185#define RLC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK_MASK 0x00020000L 25186#define RLC_DS_CNTL__RESRVED_1_MASK 0xFFFC0000L 25187//RLC_RLCV_SPARE_INT 25188#define RLC_RLCV_SPARE_INT__INTERRUPT__SHIFT 0x0 25189#define RLC_RLCV_SPARE_INT__RESERVED__SHIFT 0x1 25190#define RLC_RLCV_SPARE_INT__INTERRUPT_MASK 0x00000001L 25191#define RLC_RLCV_SPARE_INT__RESERVED_MASK 0xFFFFFFFEL 25192 25193 25194// addressBlock: gc_pwrdec 25195//CGTS_SM_CTRL_REG 25196#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY__SHIFT 0x0 25197#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY__SHIFT 0x4 25198#define CGTS_SM_CTRL_REG__MGCG_ENABLED__SHIFT 0xc 25199#define CGTS_SM_CTRL_REG__BASE_MODE__SHIFT 0x10 25200#define CGTS_SM_CTRL_REG__SM_MODE__SHIFT 0x11 25201#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE__SHIFT 0x14 25202#define CGTS_SM_CTRL_REG__OVERRIDE__SHIFT 0x15 25203#define CGTS_SM_CTRL_REG__LS_OVERRIDE__SHIFT 0x16 25204#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN__SHIFT 0x17 25205#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT 0x18 25206#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY_MASK 0x0000000FL 25207#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY_MASK 0x00000FF0L 25208#define CGTS_SM_CTRL_REG__MGCG_ENABLED_MASK 0x00001000L 25209#define CGTS_SM_CTRL_REG__BASE_MODE_MASK 0x00010000L 25210#define CGTS_SM_CTRL_REG__SM_MODE_MASK 0x000E0000L 25211#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK 0x00100000L 25212#define CGTS_SM_CTRL_REG__OVERRIDE_MASK 0x00200000L 25213#define CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK 0x00400000L 25214#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK 0x00800000L 25215#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK 0xFF000000L 25216//CGTS_RD_CTRL_REG 25217#define CGTS_RD_CTRL_REG__ROW_MUX_SEL__SHIFT 0x0 25218#define CGTS_RD_CTRL_REG__REG_MUX_SEL__SHIFT 0x8 25219#define CGTS_RD_CTRL_REG__ROW_MUX_SEL_MASK 0x0000001FL 25220#define CGTS_RD_CTRL_REG__REG_MUX_SEL_MASK 0x00001F00L 25221//CGTS_RD_REG 25222#define CGTS_RD_REG__READ_DATA__SHIFT 0x0 25223#define CGTS_RD_REG__READ_DATA_MASK 0x00003FFFL 25224//CGTS_TCC_DISABLE 25225#define CGTS_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10 25226#define CGTS_TCC_DISABLE__TCC_DISABLE_MASK 0xFFFF0000L 25227//CGTS_USER_TCC_DISABLE 25228#define CGTS_USER_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10 25229#define CGTS_USER_TCC_DISABLE__TCC_DISABLE_MASK 0xFFFF0000L 25230//CGTS_CU0_SP0_CTRL_REG 25231#define CGTS_CU0_SP0_CTRL_REG__SP00__SHIFT 0x0 25232#define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 25233#define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 25234#define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa 25235#define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb 25236#define CGTS_CU0_SP0_CTRL_REG__SP01__SHIFT 0x10 25237#define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 25238#define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 25239#define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a 25240#define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b 25241#define CGTS_CU0_SP0_CTRL_REG__SP00_MASK 0x0000007FL 25242#define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L 25243#define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L 25244#define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L 25245#define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L 25246#define CGTS_CU0_SP0_CTRL_REG__SP01_MASK 0x007F0000L 25247#define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L 25248#define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L 25249#define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L 25250#define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L 25251//CGTS_CU0_LDS_SQ_CTRL_REG 25252#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 25253#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 25254#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 25255#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa 25256#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb 25257#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 25258#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 25259#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 25260#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a 25261#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b 25262#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL 25263#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L 25264#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L 25265#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L 25266#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L 25267#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L 25268#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L 25269#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L 25270#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L 25271#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L 25272//CGTS_CU0_TA_SQC_CTRL_REG 25273#define CGTS_CU0_TA_SQC_CTRL_REG__TA__SHIFT 0x0 25274#define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 25275#define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 25276#define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa 25277#define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb 25278#define CGTS_CU0_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 25279#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 25280#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 25281#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a 25282#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b 25283#define CGTS_CU0_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL 25284#define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L 25285#define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L 25286#define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L 25287#define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L 25288#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L 25289#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L 25290#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L 25291#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L 25292#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L 25293//CGTS_CU0_SP1_CTRL_REG 25294#define CGTS_CU0_SP1_CTRL_REG__SP10__SHIFT 0x0 25295#define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 25296#define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 25297#define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa 25298#define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb 25299#define CGTS_CU0_SP1_CTRL_REG__SP11__SHIFT 0x10 25300#define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 25301#define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 25302#define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a 25303#define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b 25304#define CGTS_CU0_SP1_CTRL_REG__SP10_MASK 0x0000007FL 25305#define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L 25306#define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L 25307#define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L 25308#define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L 25309#define CGTS_CU0_SP1_CTRL_REG__SP11_MASK 0x007F0000L 25310#define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L 25311#define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L 25312#define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L 25313#define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L 25314//CGTS_CU0_TD_TCP_CTRL_REG 25315#define CGTS_CU0_TD_TCP_CTRL_REG__TD__SHIFT 0x0 25316#define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 25317#define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 25318#define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa 25319#define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb 25320#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 25321#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 25322#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 25323#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a 25324#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b 25325#define CGTS_CU0_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL 25326#define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L 25327#define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L 25328#define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L 25329#define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L 25330#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L 25331#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L 25332#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L 25333#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L 25334#define CGTS_CU0_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L 25335//CGTS_CU1_SP0_CTRL_REG 25336#define CGTS_CU1_SP0_CTRL_REG__SP00__SHIFT 0x0 25337#define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 25338#define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 25339#define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa 25340#define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb 25341#define CGTS_CU1_SP0_CTRL_REG__SP01__SHIFT 0x10 25342#define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 25343#define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 25344#define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a 25345#define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b 25346#define CGTS_CU1_SP0_CTRL_REG__SP00_MASK 0x0000007FL 25347#define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L 25348#define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L 25349#define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L 25350#define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L 25351#define CGTS_CU1_SP0_CTRL_REG__SP01_MASK 0x007F0000L 25352#define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L 25353#define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L 25354#define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L 25355#define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L 25356//CGTS_CU1_LDS_SQ_CTRL_REG 25357#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 25358#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 25359#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 25360#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa 25361#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb 25362#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 25363#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 25364#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 25365#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a 25366#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b 25367#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL 25368#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L 25369#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L 25370#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L 25371#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L 25372#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L 25373#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L 25374#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L 25375#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L 25376#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L 25377//CGTS_CU1_TA_SQC_CTRL_REG 25378#define CGTS_CU1_TA_SQC_CTRL_REG__TA__SHIFT 0x0 25379#define CGTS_CU1_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 25380#define CGTS_CU1_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 25381#define CGTS_CU1_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa 25382#define CGTS_CU1_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb 25383#define CGTS_CU1_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL 25384#define CGTS_CU1_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L 25385#define CGTS_CU1_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L 25386#define CGTS_CU1_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L 25387#define CGTS_CU1_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L 25388//CGTS_CU1_SP1_CTRL_REG 25389#define CGTS_CU1_SP1_CTRL_REG__SP10__SHIFT 0x0 25390#define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 25391#define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 25392#define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa 25393#define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb 25394#define CGTS_CU1_SP1_CTRL_REG__SP11__SHIFT 0x10 25395#define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 25396#define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 25397#define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a 25398#define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b 25399#define CGTS_CU1_SP1_CTRL_REG__SP10_MASK 0x0000007FL 25400#define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L 25401#define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L 25402#define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L 25403#define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L 25404#define CGTS_CU1_SP1_CTRL_REG__SP11_MASK 0x007F0000L 25405#define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L 25406#define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L 25407#define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L 25408#define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L 25409//CGTS_CU1_TD_TCP_CTRL_REG 25410#define CGTS_CU1_TD_TCP_CTRL_REG__TD__SHIFT 0x0 25411#define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 25412#define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 25413#define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa 25414#define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb 25415#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 25416#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 25417#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 25418#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a 25419#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b 25420#define CGTS_CU1_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL 25421#define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L 25422#define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L 25423#define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L 25424#define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L 25425#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L 25426#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L 25427#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L 25428#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L 25429#define CGTS_CU1_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L 25430//CGTS_CU2_SP0_CTRL_REG 25431#define CGTS_CU2_SP0_CTRL_REG__SP00__SHIFT 0x0 25432#define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 25433#define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 25434#define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa 25435#define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb 25436#define CGTS_CU2_SP0_CTRL_REG__SP01__SHIFT 0x10 25437#define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 25438#define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 25439#define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a 25440#define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b 25441#define CGTS_CU2_SP0_CTRL_REG__SP00_MASK 0x0000007FL 25442#define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L 25443#define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L 25444#define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L 25445#define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L 25446#define CGTS_CU2_SP0_CTRL_REG__SP01_MASK 0x007F0000L 25447#define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L 25448#define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L 25449#define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L 25450#define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L 25451//CGTS_CU2_LDS_SQ_CTRL_REG 25452#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 25453#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 25454#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 25455#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa 25456#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb 25457#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 25458#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 25459#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 25460#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a 25461#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b 25462#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL 25463#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L 25464#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L 25465#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L 25466#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L 25467#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L 25468#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L 25469#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L 25470#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L 25471#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L 25472//CGTS_CU2_TA_SQC_CTRL_REG 25473#define CGTS_CU2_TA_SQC_CTRL_REG__TA__SHIFT 0x0 25474#define CGTS_CU2_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 25475#define CGTS_CU2_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 25476#define CGTS_CU2_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa 25477#define CGTS_CU2_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb 25478#define CGTS_CU2_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL 25479#define CGTS_CU2_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L 25480#define CGTS_CU2_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L 25481#define CGTS_CU2_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L 25482#define CGTS_CU2_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L 25483//CGTS_CU2_SP1_CTRL_REG 25484#define CGTS_CU2_SP1_CTRL_REG__SP10__SHIFT 0x0 25485#define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 25486#define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 25487#define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa 25488#define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb 25489#define CGTS_CU2_SP1_CTRL_REG__SP11__SHIFT 0x10 25490#define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 25491#define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 25492#define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a 25493#define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b 25494#define CGTS_CU2_SP1_CTRL_REG__SP10_MASK 0x0000007FL 25495#define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L 25496#define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L 25497#define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L 25498#define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L 25499#define CGTS_CU2_SP1_CTRL_REG__SP11_MASK 0x007F0000L 25500#define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L 25501#define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L 25502#define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L 25503#define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L 25504//CGTS_CU2_TD_TCP_CTRL_REG 25505#define CGTS_CU2_TD_TCP_CTRL_REG__TD__SHIFT 0x0 25506#define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 25507#define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 25508#define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa 25509#define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb 25510#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 25511#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 25512#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 25513#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a 25514#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b 25515#define CGTS_CU2_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL 25516#define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L 25517#define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L 25518#define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L 25519#define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L 25520#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L 25521#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L 25522#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L 25523#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L 25524#define CGTS_CU2_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L 25525//CGTS_CU3_SP0_CTRL_REG 25526#define CGTS_CU3_SP0_CTRL_REG__SP00__SHIFT 0x0 25527#define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 25528#define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 25529#define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa 25530#define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb 25531#define CGTS_CU3_SP0_CTRL_REG__SP01__SHIFT 0x10 25532#define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 25533#define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 25534#define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a 25535#define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b 25536#define CGTS_CU3_SP0_CTRL_REG__SP00_MASK 0x0000007FL 25537#define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L 25538#define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L 25539#define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L 25540#define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L 25541#define CGTS_CU3_SP0_CTRL_REG__SP01_MASK 0x007F0000L 25542#define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L 25543#define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L 25544#define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L 25545#define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L 25546//CGTS_CU3_LDS_SQ_CTRL_REG 25547#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 25548#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 25549#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 25550#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa 25551#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb 25552#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 25553#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 25554#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 25555#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a 25556#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b 25557#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL 25558#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L 25559#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L 25560#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L 25561#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L 25562#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L 25563#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L 25564#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L 25565#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L 25566#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L 25567//CGTS_CU3_TA_SQC_CTRL_REG 25568#define CGTS_CU3_TA_SQC_CTRL_REG__TA__SHIFT 0x0 25569#define CGTS_CU3_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 25570#define CGTS_CU3_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 25571#define CGTS_CU3_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa 25572#define CGTS_CU3_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb 25573#define CGTS_CU3_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 25574#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 25575#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 25576#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a 25577#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b 25578#define CGTS_CU3_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL 25579#define CGTS_CU3_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L 25580#define CGTS_CU3_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L 25581#define CGTS_CU3_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L 25582#define CGTS_CU3_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L 25583#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L 25584#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L 25585#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L 25586#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L 25587#define CGTS_CU3_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L 25588//CGTS_CU3_SP1_CTRL_REG 25589#define CGTS_CU3_SP1_CTRL_REG__SP10__SHIFT 0x0 25590#define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 25591#define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 25592#define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa 25593#define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb 25594#define CGTS_CU3_SP1_CTRL_REG__SP11__SHIFT 0x10 25595#define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 25596#define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 25597#define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a 25598#define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b 25599#define CGTS_CU3_SP1_CTRL_REG__SP10_MASK 0x0000007FL 25600#define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L 25601#define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L 25602#define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L 25603#define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L 25604#define CGTS_CU3_SP1_CTRL_REG__SP11_MASK 0x007F0000L 25605#define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L 25606#define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L 25607#define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L 25608#define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L 25609//CGTS_CU3_TD_TCP_CTRL_REG 25610#define CGTS_CU3_TD_TCP_CTRL_REG__TD__SHIFT 0x0 25611#define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 25612#define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 25613#define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa 25614#define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb 25615#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 25616#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 25617#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 25618#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a 25619#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b 25620#define CGTS_CU3_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL 25621#define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L 25622#define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L 25623#define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L 25624#define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L 25625#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L 25626#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L 25627#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L 25628#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L 25629#define CGTS_CU3_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L 25630//CGTS_CU4_SP0_CTRL_REG 25631#define CGTS_CU4_SP0_CTRL_REG__SP00__SHIFT 0x0 25632#define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 25633#define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 25634#define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa 25635#define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb 25636#define CGTS_CU4_SP0_CTRL_REG__SP01__SHIFT 0x10 25637#define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 25638#define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 25639#define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a 25640#define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b 25641#define CGTS_CU4_SP0_CTRL_REG__SP00_MASK 0x0000007FL 25642#define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L 25643#define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L 25644#define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L 25645#define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L 25646#define CGTS_CU4_SP0_CTRL_REG__SP01_MASK 0x007F0000L 25647#define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L 25648#define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L 25649#define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L 25650#define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L 25651//CGTS_CU4_LDS_SQ_CTRL_REG 25652#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 25653#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 25654#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 25655#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa 25656#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb 25657#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 25658#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 25659#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 25660#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a 25661#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b 25662#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL 25663#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L 25664#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L 25665#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L 25666#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L 25667#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L 25668#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L 25669#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L 25670#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L 25671#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L 25672//CGTS_CU4_TA_SQC_CTRL_REG 25673#define CGTS_CU4_TA_SQC_CTRL_REG__TA__SHIFT 0x0 25674#define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 25675#define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 25676#define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa 25677#define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb 25678#define CGTS_CU4_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL 25679#define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L 25680#define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L 25681#define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L 25682#define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L 25683//CGTS_CU4_SP1_CTRL_REG 25684#define CGTS_CU4_SP1_CTRL_REG__SP10__SHIFT 0x0 25685#define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 25686#define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 25687#define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa 25688#define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb 25689#define CGTS_CU4_SP1_CTRL_REG__SP11__SHIFT 0x10 25690#define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 25691#define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 25692#define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a 25693#define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b 25694#define CGTS_CU4_SP1_CTRL_REG__SP10_MASK 0x0000007FL 25695#define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L 25696#define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L 25697#define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L 25698#define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L 25699#define CGTS_CU4_SP1_CTRL_REG__SP11_MASK 0x007F0000L 25700#define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L 25701#define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L 25702#define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L 25703#define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L 25704//CGTS_CU4_TD_TCP_CTRL_REG 25705#define CGTS_CU4_TD_TCP_CTRL_REG__TD__SHIFT 0x0 25706#define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 25707#define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 25708#define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa 25709#define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb 25710#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 25711#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 25712#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 25713#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a 25714#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b 25715#define CGTS_CU4_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL 25716#define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L 25717#define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L 25718#define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L 25719#define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L 25720#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L 25721#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L 25722#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L 25723#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L 25724#define CGTS_CU4_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L 25725//CGTS_CU5_SP0_CTRL_REG 25726#define CGTS_CU5_SP0_CTRL_REG__SP00__SHIFT 0x0 25727#define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 25728#define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 25729#define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa 25730#define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb 25731#define CGTS_CU5_SP0_CTRL_REG__SP01__SHIFT 0x10 25732#define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 25733#define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 25734#define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a 25735#define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b 25736#define CGTS_CU5_SP0_CTRL_REG__SP00_MASK 0x0000007FL 25737#define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L 25738#define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L 25739#define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L 25740#define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L 25741#define CGTS_CU5_SP0_CTRL_REG__SP01_MASK 0x007F0000L 25742#define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L 25743#define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L 25744#define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L 25745#define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L 25746//CGTS_CU5_LDS_SQ_CTRL_REG 25747#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 25748#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 25749#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 25750#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa 25751#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb 25752#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 25753#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 25754#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 25755#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a 25756#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b 25757#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL 25758#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L 25759#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L 25760#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L 25761#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L 25762#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L 25763#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L 25764#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L 25765#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L 25766#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L 25767//CGTS_CU5_TA_SQC_CTRL_REG 25768#define CGTS_CU5_TA_SQC_CTRL_REG__TA__SHIFT 0x0 25769#define CGTS_CU5_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 25770#define CGTS_CU5_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 25771#define CGTS_CU5_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa 25772#define CGTS_CU5_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb 25773#define CGTS_CU5_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL 25774#define CGTS_CU5_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L 25775#define CGTS_CU5_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L 25776#define CGTS_CU5_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L 25777#define CGTS_CU5_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L 25778//CGTS_CU5_SP1_CTRL_REG 25779#define CGTS_CU5_SP1_CTRL_REG__SP10__SHIFT 0x0 25780#define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 25781#define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 25782#define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa 25783#define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb 25784#define CGTS_CU5_SP1_CTRL_REG__SP11__SHIFT 0x10 25785#define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 25786#define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 25787#define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a 25788#define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b 25789#define CGTS_CU5_SP1_CTRL_REG__SP10_MASK 0x0000007FL 25790#define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L 25791#define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L 25792#define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L 25793#define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L 25794#define CGTS_CU5_SP1_CTRL_REG__SP11_MASK 0x007F0000L 25795#define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L 25796#define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L 25797#define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L 25798#define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L 25799//CGTS_CU5_TD_TCP_CTRL_REG 25800#define CGTS_CU5_TD_TCP_CTRL_REG__TD__SHIFT 0x0 25801#define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 25802#define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 25803#define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa 25804#define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb 25805#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 25806#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 25807#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 25808#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a 25809#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b 25810#define CGTS_CU5_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL 25811#define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L 25812#define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L 25813#define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L 25814#define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L 25815#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L 25816#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L 25817#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L 25818#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L 25819#define CGTS_CU5_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L 25820//CGTS_CU6_SP0_CTRL_REG 25821#define CGTS_CU6_SP0_CTRL_REG__SP00__SHIFT 0x0 25822#define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 25823#define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 25824#define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa 25825#define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb 25826#define CGTS_CU6_SP0_CTRL_REG__SP01__SHIFT 0x10 25827#define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 25828#define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 25829#define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a 25830#define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b 25831#define CGTS_CU6_SP0_CTRL_REG__SP00_MASK 0x0000007FL 25832#define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L 25833#define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L 25834#define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L 25835#define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L 25836#define CGTS_CU6_SP0_CTRL_REG__SP01_MASK 0x007F0000L 25837#define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L 25838#define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L 25839#define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L 25840#define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L 25841//CGTS_CU6_LDS_SQ_CTRL_REG 25842#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 25843#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 25844#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 25845#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa 25846#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb 25847#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 25848#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 25849#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 25850#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a 25851#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b 25852#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL 25853#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L 25854#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L 25855#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L 25856#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L 25857#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L 25858#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L 25859#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L 25860#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L 25861#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L 25862//CGTS_CU6_TA_SQC_CTRL_REG 25863#define CGTS_CU6_TA_SQC_CTRL_REG__TA__SHIFT 0x0 25864#define CGTS_CU6_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 25865#define CGTS_CU6_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 25866#define CGTS_CU6_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa 25867#define CGTS_CU6_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb 25868#define CGTS_CU6_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 25869#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 25870#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 25871#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a 25872#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b 25873#define CGTS_CU6_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL 25874#define CGTS_CU6_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L 25875#define CGTS_CU6_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L 25876#define CGTS_CU6_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L 25877#define CGTS_CU6_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L 25878#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L 25879#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L 25880#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L 25881#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L 25882#define CGTS_CU6_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L 25883//CGTS_CU6_SP1_CTRL_REG 25884#define CGTS_CU6_SP1_CTRL_REG__SP10__SHIFT 0x0 25885#define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 25886#define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 25887#define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa 25888#define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb 25889#define CGTS_CU6_SP1_CTRL_REG__SP11__SHIFT 0x10 25890#define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 25891#define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 25892#define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a 25893#define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b 25894#define CGTS_CU6_SP1_CTRL_REG__SP10_MASK 0x0000007FL 25895#define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L 25896#define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L 25897#define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L 25898#define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L 25899#define CGTS_CU6_SP1_CTRL_REG__SP11_MASK 0x007F0000L 25900#define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L 25901#define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L 25902#define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L 25903#define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L 25904//CGTS_CU6_TD_TCP_CTRL_REG 25905#define CGTS_CU6_TD_TCP_CTRL_REG__TD__SHIFT 0x0 25906#define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 25907#define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 25908#define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa 25909#define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb 25910#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 25911#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 25912#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 25913#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a 25914#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b 25915#define CGTS_CU6_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL 25916#define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L 25917#define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L 25918#define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L 25919#define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L 25920#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L 25921#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L 25922#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L 25923#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L 25924#define CGTS_CU6_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L 25925//CGTS_CU7_SP0_CTRL_REG 25926#define CGTS_CU7_SP0_CTRL_REG__SP00__SHIFT 0x0 25927#define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 25928#define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 25929#define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa 25930#define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb 25931#define CGTS_CU7_SP0_CTRL_REG__SP01__SHIFT 0x10 25932#define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 25933#define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 25934#define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a 25935#define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b 25936#define CGTS_CU7_SP0_CTRL_REG__SP00_MASK 0x0000007FL 25937#define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L 25938#define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L 25939#define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L 25940#define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L 25941#define CGTS_CU7_SP0_CTRL_REG__SP01_MASK 0x007F0000L 25942#define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L 25943#define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L 25944#define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L 25945#define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L 25946//CGTS_CU7_LDS_SQ_CTRL_REG 25947#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 25948#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 25949#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 25950#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa 25951#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb 25952#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 25953#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 25954#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 25955#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a 25956#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b 25957#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL 25958#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L 25959#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L 25960#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L 25961#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L 25962#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L 25963#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L 25964#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L 25965#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L 25966#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L 25967//CGTS_CU7_TA_SQC_CTRL_REG 25968#define CGTS_CU7_TA_SQC_CTRL_REG__TA__SHIFT 0x0 25969#define CGTS_CU7_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 25970#define CGTS_CU7_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 25971#define CGTS_CU7_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa 25972#define CGTS_CU7_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb 25973#define CGTS_CU7_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL 25974#define CGTS_CU7_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L 25975#define CGTS_CU7_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L 25976#define CGTS_CU7_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L 25977#define CGTS_CU7_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L 25978//CGTS_CU7_SP1_CTRL_REG 25979#define CGTS_CU7_SP1_CTRL_REG__SP10__SHIFT 0x0 25980#define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 25981#define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 25982#define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa 25983#define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb 25984#define CGTS_CU7_SP1_CTRL_REG__SP11__SHIFT 0x10 25985#define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 25986#define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 25987#define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a 25988#define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b 25989#define CGTS_CU7_SP1_CTRL_REG__SP10_MASK 0x0000007FL 25990#define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L 25991#define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L 25992#define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L 25993#define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L 25994#define CGTS_CU7_SP1_CTRL_REG__SP11_MASK 0x007F0000L 25995#define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L 25996#define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L 25997#define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L 25998#define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L 25999//CGTS_CU7_TD_TCP_CTRL_REG 26000#define CGTS_CU7_TD_TCP_CTRL_REG__TD__SHIFT 0x0
26001#define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 26002#define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 26003#define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa 26004#define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb 26005#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 26006#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 26007#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 26008#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a 26009#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b 26010#define CGTS_CU7_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL 26011#define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L 26012#define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L 26013#define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L 26014#define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L 26015#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L 26016#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L 26017#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L 26018#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L 26019#define CGTS_CU7_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L 26020//CGTS_CU8_SP0_CTRL_REG 26021#define CGTS_CU8_SP0_CTRL_REG__SP00__SHIFT 0x0 26022#define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 26023#define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 26024#define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa 26025#define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb 26026#define CGTS_CU8_SP0_CTRL_REG__SP01__SHIFT 0x10 26027#define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 26028#define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 26029#define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a 26030#define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b 26031#define CGTS_CU8_SP0_CTRL_REG__SP00_MASK 0x0000007FL 26032#define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L 26033#define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L 26034#define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L 26035#define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L 26036#define CGTS_CU8_SP0_CTRL_REG__SP01_MASK 0x007F0000L 26037#define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L 26038#define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L 26039#define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L 26040#define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L 26041//CGTS_CU8_LDS_SQ_CTRL_REG 26042#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 26043#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 26044#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 26045#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa 26046#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb 26047#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 26048#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 26049#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 26050#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a 26051#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b 26052#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL 26053#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L 26054#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L 26055#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L 26056#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L 26057#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L 26058#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L 26059#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L 26060#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L 26061#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L 26062//CGTS_CU8_TA_SQC_CTRL_REG 26063#define CGTS_CU8_TA_SQC_CTRL_REG__TA__SHIFT 0x0 26064#define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 26065#define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 26066#define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa 26067#define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb 26068#define CGTS_CU8_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL 26069#define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L 26070#define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L 26071#define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L 26072#define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L 26073//CGTS_CU8_SP1_CTRL_REG 26074#define CGTS_CU8_SP1_CTRL_REG__SP10__SHIFT 0x0 26075#define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 26076#define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 26077#define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa 26078#define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb 26079#define CGTS_CU8_SP1_CTRL_REG__SP11__SHIFT 0x10 26080#define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 26081#define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 26082#define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a 26083#define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b 26084#define CGTS_CU8_SP1_CTRL_REG__SP10_MASK 0x0000007FL 26085#define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L 26086#define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L 26087#define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L 26088#define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L 26089#define CGTS_CU8_SP1_CTRL_REG__SP11_MASK 0x007F0000L 26090#define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L 26091#define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L 26092#define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L 26093#define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L 26094//CGTS_CU8_TD_TCP_CTRL_REG 26095#define CGTS_CU8_TD_TCP_CTRL_REG__TD__SHIFT 0x0 26096#define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 26097#define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 26098#define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa 26099#define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb 26100#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 26101#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 26102#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 26103#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a 26104#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b 26105#define CGTS_CU8_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL 26106#define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L 26107#define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L 26108#define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L 26109#define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L 26110#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L 26111#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L 26112#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L 26113#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L 26114#define CGTS_CU8_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L 26115//CGTS_CU9_SP0_CTRL_REG 26116#define CGTS_CU9_SP0_CTRL_REG__SP00__SHIFT 0x0 26117#define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 26118#define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 26119#define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa 26120#define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb 26121#define CGTS_CU9_SP0_CTRL_REG__SP01__SHIFT 0x10 26122#define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 26123#define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 26124#define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a 26125#define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b 26126#define CGTS_CU9_SP0_CTRL_REG__SP00_MASK 0x0000007FL 26127#define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L 26128#define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L 26129#define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L 26130#define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L 26131#define CGTS_CU9_SP0_CTRL_REG__SP01_MASK 0x007F0000L 26132#define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L 26133#define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L 26134#define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L 26135#define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L 26136//CGTS_CU9_LDS_SQ_CTRL_REG 26137#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 26138#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 26139#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 26140#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa 26141#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb 26142#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 26143#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 26144#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 26145#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a 26146#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b 26147#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL 26148#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L 26149#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L 26150#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L 26151#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L 26152#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L 26153#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L 26154#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L 26155#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L 26156#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L 26157//CGTS_CU9_TA_SQC_CTRL_REG 26158#define CGTS_CU9_TA_SQC_CTRL_REG__TA__SHIFT 0x0 26159#define CGTS_CU9_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 26160#define CGTS_CU9_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 26161#define CGTS_CU9_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa 26162#define CGTS_CU9_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb 26163#define CGTS_CU9_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 26164#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 26165#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 26166#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a 26167#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b 26168#define CGTS_CU9_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL 26169#define CGTS_CU9_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L 26170#define CGTS_CU9_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L 26171#define CGTS_CU9_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L 26172#define CGTS_CU9_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L 26173#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L 26174#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L 26175#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L 26176#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L 26177#define CGTS_CU9_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L 26178//CGTS_CU9_SP1_CTRL_REG 26179#define CGTS_CU9_SP1_CTRL_REG__SP10__SHIFT 0x0 26180#define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 26181#define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 26182#define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa 26183#define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb 26184#define CGTS_CU9_SP1_CTRL_REG__SP11__SHIFT 0x10 26185#define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 26186#define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 26187#define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a 26188#define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b 26189#define CGTS_CU9_SP1_CTRL_REG__SP10_MASK 0x0000007FL 26190#define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L 26191#define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L 26192#define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L 26193#define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L 26194#define CGTS_CU9_SP1_CTRL_REG__SP11_MASK 0x007F0000L 26195#define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L 26196#define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L 26197#define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L 26198#define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L 26199//CGTS_CU9_TD_TCP_CTRL_REG 26200#define CGTS_CU9_TD_TCP_CTRL_REG__TD__SHIFT 0x0 26201#define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 26202#define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 26203#define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa 26204#define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb 26205#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 26206#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 26207#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 26208#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a 26209#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b 26210#define CGTS_CU9_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL 26211#define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L 26212#define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L 26213#define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L 26214#define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L 26215#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L 26216#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L 26217#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L 26218#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L 26219#define CGTS_CU9_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L 26220//CGTS_CU10_SP0_CTRL_REG 26221#define CGTS_CU10_SP0_CTRL_REG__SP00__SHIFT 0x0 26222#define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 26223#define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 26224#define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa 26225#define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb 26226#define CGTS_CU10_SP0_CTRL_REG__SP01__SHIFT 0x10 26227#define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 26228#define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 26229#define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a 26230#define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b 26231#define CGTS_CU10_SP0_CTRL_REG__SP00_MASK 0x0000007FL 26232#define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L 26233#define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L 26234#define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L 26235#define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L 26236#define CGTS_CU10_SP0_CTRL_REG__SP01_MASK 0x007F0000L 26237#define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L 26238#define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L 26239#define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L 26240#define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L 26241//CGTS_CU10_LDS_SQ_CTRL_REG 26242#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 26243#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 26244#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 26245#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa 26246#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb 26247#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 26248#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 26249#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 26250#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a 26251#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b 26252#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL 26253#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L 26254#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L 26255#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L 26256#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L 26257#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L 26258#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L 26259#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L 26260#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L 26261#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L 26262//CGTS_CU10_TA_SQC_CTRL_REG 26263#define CGTS_CU10_TA_SQC_CTRL_REG__TA__SHIFT 0x0 26264#define CGTS_CU10_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 26265#define CGTS_CU10_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 26266#define CGTS_CU10_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa 26267#define CGTS_CU10_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb 26268#define CGTS_CU10_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL 26269#define CGTS_CU10_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L 26270#define CGTS_CU10_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L 26271#define CGTS_CU10_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L 26272#define CGTS_CU10_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L 26273//CGTS_CU10_SP1_CTRL_REG 26274#define CGTS_CU10_SP1_CTRL_REG__SP10__SHIFT 0x0 26275#define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 26276#define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 26277#define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa 26278#define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb 26279#define CGTS_CU10_SP1_CTRL_REG__SP11__SHIFT 0x10 26280#define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 26281#define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 26282#define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a 26283#define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b 26284#define CGTS_CU10_SP1_CTRL_REG__SP10_MASK 0x0000007FL 26285#define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L 26286#define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L 26287#define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L 26288#define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L 26289#define CGTS_CU10_SP1_CTRL_REG__SP11_MASK 0x007F0000L 26290#define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L 26291#define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L 26292#define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L 26293#define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L 26294//CGTS_CU10_TD_TCP_CTRL_REG 26295#define CGTS_CU10_TD_TCP_CTRL_REG__TD__SHIFT 0x0 26296#define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 26297#define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 26298#define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa 26299#define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb 26300#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 26301#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 26302#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 26303#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a 26304#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b 26305#define CGTS_CU10_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL 26306#define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L 26307#define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L 26308#define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L 26309#define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L 26310#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L 26311#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L 26312#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L 26313#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L 26314#define CGTS_CU10_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L 26315//CGTS_CU11_SP0_CTRL_REG 26316#define CGTS_CU11_SP0_CTRL_REG__SP00__SHIFT 0x0 26317#define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 26318#define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 26319#define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa 26320#define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb 26321#define CGTS_CU11_SP0_CTRL_REG__SP01__SHIFT 0x10 26322#define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 26323#define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 26324#define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a 26325#define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b 26326#define CGTS_CU11_SP0_CTRL_REG__SP00_MASK 0x0000007FL 26327#define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L 26328#define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L 26329#define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L 26330#define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L 26331#define CGTS_CU11_SP0_CTRL_REG__SP01_MASK 0x007F0000L 26332#define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L 26333#define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L 26334#define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L 26335#define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L 26336//CGTS_CU11_LDS_SQ_CTRL_REG 26337#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 26338#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 26339#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 26340#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa 26341#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb 26342#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 26343#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 26344#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 26345#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a 26346#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b 26347#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL 26348#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L 26349#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L 26350#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L 26351#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L 26352#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L 26353#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L 26354#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L 26355#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L 26356#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L 26357//CGTS_CU11_TA_SQC_CTRL_REG 26358#define CGTS_CU11_TA_SQC_CTRL_REG__TA__SHIFT 0x0 26359#define CGTS_CU11_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 26360#define CGTS_CU11_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 26361#define CGTS_CU11_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa 26362#define CGTS_CU11_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb 26363#define CGTS_CU11_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL 26364#define CGTS_CU11_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L 26365#define CGTS_CU11_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L 26366#define CGTS_CU11_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L 26367#define CGTS_CU11_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L 26368//CGTS_CU11_SP1_CTRL_REG 26369#define CGTS_CU11_SP1_CTRL_REG__SP10__SHIFT 0x0 26370#define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 26371#define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 26372#define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa 26373#define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb 26374#define CGTS_CU11_SP1_CTRL_REG__SP11__SHIFT 0x10 26375#define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 26376#define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 26377#define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a 26378#define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b 26379#define CGTS_CU11_SP1_CTRL_REG__SP10_MASK 0x0000007FL 26380#define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L 26381#define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L 26382#define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L 26383#define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L 26384#define CGTS_CU11_SP1_CTRL_REG__SP11_MASK 0x007F0000L 26385#define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L 26386#define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L 26387#define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L 26388#define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L 26389//CGTS_CU11_TD_TCP_CTRL_REG 26390#define CGTS_CU11_TD_TCP_CTRL_REG__TD__SHIFT 0x0 26391#define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 26392#define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 26393#define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa 26394#define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb 26395#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 26396#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 26397#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 26398#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a 26399#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b 26400#define CGTS_CU11_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL 26401#define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L 26402#define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L 26403#define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L 26404#define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L 26405#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L 26406#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L 26407#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L 26408#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L 26409#define CGTS_CU11_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L 26410//CGTS_CU12_SP0_CTRL_REG 26411#define CGTS_CU12_SP0_CTRL_REG__SP00__SHIFT 0x0 26412#define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 26413#define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 26414#define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa 26415#define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb 26416#define CGTS_CU12_SP0_CTRL_REG__SP01__SHIFT 0x10 26417#define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 26418#define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 26419#define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a 26420#define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b 26421#define CGTS_CU12_SP0_CTRL_REG__SP00_MASK 0x0000007FL 26422#define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L 26423#define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L 26424#define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L 26425#define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L 26426#define CGTS_CU12_SP0_CTRL_REG__SP01_MASK 0x007F0000L 26427#define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L 26428#define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L 26429#define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L 26430#define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L 26431//CGTS_CU12_LDS_SQ_CTRL_REG 26432#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 26433#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 26434#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 26435#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa 26436#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb 26437#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 26438#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 26439#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 26440#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a 26441#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b 26442#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL 26443#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L 26444#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L 26445#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L 26446#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L 26447#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L 26448#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L 26449#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L 26450#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L 26451#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L 26452//CGTS_CU12_TA_SQC_CTRL_REG 26453#define CGTS_CU12_TA_SQC_CTRL_REG__TA__SHIFT 0x0 26454#define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 26455#define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 26456#define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa 26457#define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb 26458#define CGTS_CU12_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 26459#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 26460#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 26461#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a 26462#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b 26463#define CGTS_CU12_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL 26464#define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L 26465#define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L 26466#define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L 26467#define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L 26468#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L 26469#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L 26470#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L 26471#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L 26472#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L 26473//CGTS_CU12_SP1_CTRL_REG 26474#define CGTS_CU12_SP1_CTRL_REG__SP10__SHIFT 0x0 26475#define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 26476#define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 26477#define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa 26478#define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb 26479#define CGTS_CU12_SP1_CTRL_REG__SP11__SHIFT 0x10 26480#define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 26481#define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 26482#define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a 26483#define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b 26484#define CGTS_CU12_SP1_CTRL_REG__SP10_MASK 0x0000007FL 26485#define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L 26486#define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L 26487#define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L 26488#define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L 26489#define CGTS_CU12_SP1_CTRL_REG__SP11_MASK 0x007F0000L 26490#define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L 26491#define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L 26492#define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L 26493#define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L 26494//CGTS_CU12_TD_TCP_CTRL_REG 26495#define CGTS_CU12_TD_TCP_CTRL_REG__TD__SHIFT 0x0 26496#define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 26497#define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 26498#define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa 26499#define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb 26500#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 26501#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 26502#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 26503#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a 26504#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b 26505#define CGTS_CU12_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL 26506#define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L 26507#define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L 26508#define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L 26509#define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L 26510#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L 26511#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L 26512#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L 26513#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L 26514#define CGTS_CU12_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L 26515//CGTS_CU13_SP0_CTRL_REG 26516#define CGTS_CU13_SP0_CTRL_REG__SP00__SHIFT 0x0 26517#define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 26518#define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 26519#define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa 26520#define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb 26521#define CGTS_CU13_SP0_CTRL_REG__SP01__SHIFT 0x10 26522#define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 26523#define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 26524#define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a 26525#define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b 26526#define CGTS_CU13_SP0_CTRL_REG__SP00_MASK 0x0000007FL 26527#define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L 26528#define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L 26529#define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L 26530#define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L 26531#define CGTS_CU13_SP0_CTRL_REG__SP01_MASK 0x007F0000L 26532#define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L 26533#define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L 26534#define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L 26535#define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L 26536//CGTS_CU13_LDS_SQ_CTRL_REG 26537#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 26538#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 26539#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 26540#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa 26541#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb 26542#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 26543#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 26544#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 26545#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a 26546#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b 26547#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL 26548#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L 26549#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L 26550#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L 26551#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L 26552#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L 26553#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L 26554#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L 26555#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L 26556#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L 26557//CGTS_CU13_TA_SQC_CTRL_REG 26558#define CGTS_CU13_TA_SQC_CTRL_REG__TA__SHIFT 0x0 26559#define CGTS_CU13_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 26560#define CGTS_CU13_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 26561#define CGTS_CU13_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa 26562#define CGTS_CU13_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb 26563#define CGTS_CU13_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL 26564#define CGTS_CU13_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L 26565#define CGTS_CU13_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L 26566#define CGTS_CU13_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L 26567#define CGTS_CU13_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L 26568//CGTS_CU13_SP1_CTRL_REG 26569#define CGTS_CU13_SP1_CTRL_REG__SP10__SHIFT 0x0 26570#define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 26571#define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 26572#define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa 26573#define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb 26574#define CGTS_CU13_SP1_CTRL_REG__SP11__SHIFT 0x10 26575#define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 26576#define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 26577#define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a 26578#define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b 26579#define CGTS_CU13_SP1_CTRL_REG__SP10_MASK 0x0000007FL 26580#define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L 26581#define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L 26582#define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L 26583#define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L 26584#define CGTS_CU13_SP1_CTRL_REG__SP11_MASK 0x007F0000L 26585#define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L 26586#define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L 26587#define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L 26588#define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L 26589//CGTS_CU13_TD_TCP_CTRL_REG 26590#define CGTS_CU13_TD_TCP_CTRL_REG__TD__SHIFT 0x0 26591#define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 26592#define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 26593#define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa 26594#define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb 26595#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 26596#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 26597#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 26598#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a 26599#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b 26600#define CGTS_CU13_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL 26601#define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L 26602#define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L 26603#define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L 26604#define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L 26605#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L 26606#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L 26607#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L 26608#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L 26609#define CGTS_CU13_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L 26610//CGTS_CU14_SP0_CTRL_REG 26611#define CGTS_CU14_SP0_CTRL_REG__SP00__SHIFT 0x0 26612#define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 26613#define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 26614#define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa 26615#define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb 26616#define CGTS_CU14_SP0_CTRL_REG__SP01__SHIFT 0x10 26617#define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 26618#define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 26619#define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a 26620#define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b 26621#define CGTS_CU14_SP0_CTRL_REG__SP00_MASK 0x0000007FL 26622#define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L 26623#define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L 26624#define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L 26625#define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L 26626#define CGTS_CU14_SP0_CTRL_REG__SP01_MASK 0x007F0000L 26627#define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L 26628#define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L 26629#define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L 26630#define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L 26631//CGTS_CU14_LDS_SQ_CTRL_REG 26632#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 26633#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 26634#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 26635#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa 26636#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb 26637#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 26638#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 26639#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 26640#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a 26641#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b 26642#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL 26643#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L 26644#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L 26645#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L 26646#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L 26647#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L 26648#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L 26649#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L 26650#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L 26651#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L 26652//CGTS_CU14_TA_SQC_CTRL_REG 26653#define CGTS_CU14_TA_SQC_CTRL_REG__TA__SHIFT 0x0 26654#define CGTS_CU14_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 26655#define CGTS_CU14_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 26656#define CGTS_CU14_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa 26657#define CGTS_CU14_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb 26658#define CGTS_CU14_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL 26659#define CGTS_CU14_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L 26660#define CGTS_CU14_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L 26661#define CGTS_CU14_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L 26662#define CGTS_CU14_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L 26663//CGTS_CU14_SP1_CTRL_REG 26664#define CGTS_CU14_SP1_CTRL_REG__SP10__SHIFT 0x0 26665#define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 26666#define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 26667#define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa 26668#define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb 26669#define CGTS_CU14_SP1_CTRL_REG__SP11__SHIFT 0x10 26670#define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 26671#define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 26672#define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a 26673#define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b 26674#define CGTS_CU14_SP1_CTRL_REG__SP10_MASK 0x0000007FL 26675#define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L 26676#define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L 26677#define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L 26678#define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L 26679#define CGTS_CU14_SP1_CTRL_REG__SP11_MASK 0x007F0000L 26680#define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L 26681#define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L 26682#define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L 26683#define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L 26684//CGTS_CU14_TD_TCP_CTRL_REG 26685#define CGTS_CU14_TD_TCP_CTRL_REG__TD__SHIFT 0x0 26686#define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 26687#define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 26688#define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa 26689#define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb 26690#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 26691#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 26692#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 26693#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a 26694#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b 26695#define CGTS_CU14_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL 26696#define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L 26697#define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L 26698#define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L 26699#define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L 26700#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L 26701#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L 26702#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L 26703#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L 26704#define CGTS_CU14_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L 26705//CGTS_CU15_SP0_CTRL_REG 26706#define CGTS_CU15_SP0_CTRL_REG__SP00__SHIFT 0x0 26707#define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 26708#define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 26709#define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa 26710#define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb 26711#define CGTS_CU15_SP0_CTRL_REG__SP01__SHIFT 0x10 26712#define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 26713#define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 26714#define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a 26715#define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b 26716#define CGTS_CU15_SP0_CTRL_REG__SP00_MASK 0x0000007FL 26717#define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x00000080L 26718#define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x00000300L 26719#define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x00000400L 26720#define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x00000800L 26721#define CGTS_CU15_SP0_CTRL_REG__SP01_MASK 0x007F0000L 26722#define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x00800000L 26723#define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x03000000L 26724#define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x04000000L 26725#define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x08000000L 26726//CGTS_CU15_LDS_SQ_CTRL_REG 26727#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 26728#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 26729#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 26730#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa 26731#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb 26732#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 26733#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 26734#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 26735#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a 26736#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b 26737#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_MASK 0x0000007FL 26738#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x00000080L 26739#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x00000300L 26740#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x00000400L 26741#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x00000800L 26742#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_MASK 0x007F0000L 26743#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x00800000L 26744#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x03000000L 26745#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x04000000L 26746#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x08000000L 26747//CGTS_CU15_TA_SQC_CTRL_REG 26748#define CGTS_CU15_TA_SQC_CTRL_REG__TA__SHIFT 0x0 26749#define CGTS_CU15_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 26750#define CGTS_CU15_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 26751#define CGTS_CU15_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa 26752#define CGTS_CU15_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb 26753#define CGTS_CU15_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 26754#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 26755#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 26756#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a 26757#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b 26758#define CGTS_CU15_TA_SQC_CTRL_REG__TA_MASK 0x0000007FL 26759#define CGTS_CU15_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x00000080L 26760#define CGTS_CU15_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x00000300L 26761#define CGTS_CU15_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x00000400L 26762#define CGTS_CU15_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x00000800L 26763#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_MASK 0x007F0000L 26764#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x00800000L 26765#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x03000000L 26766#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x04000000L 26767#define CGTS_CU15_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x08000000L 26768//CGTS_CU15_SP1_CTRL_REG 26769#define CGTS_CU15_SP1_CTRL_REG__SP10__SHIFT 0x0 26770#define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 26771#define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 26772#define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa 26773#define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb 26774#define CGTS_CU15_SP1_CTRL_REG__SP11__SHIFT 0x10 26775#define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 26776#define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 26777#define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a 26778#define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b 26779#define CGTS_CU15_SP1_CTRL_REG__SP10_MASK 0x0000007FL 26780#define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x00000080L 26781#define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x00000300L 26782#define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x00000400L 26783#define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x00000800L 26784#define CGTS_CU15_SP1_CTRL_REG__SP11_MASK 0x007F0000L 26785#define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x00800000L 26786#define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x03000000L 26787#define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x04000000L 26788#define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x08000000L 26789//CGTS_CU15_TD_TCP_CTRL_REG 26790#define CGTS_CU15_TD_TCP_CTRL_REG__TD__SHIFT 0x0 26791#define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 26792#define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 26793#define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa 26794#define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb 26795#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF__SHIFT 0x10 26796#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_OVERRIDE__SHIFT 0x17 26797#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE__SHIFT 0x18 26798#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE__SHIFT 0x1a 26799#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE__SHIFT 0x1b 26800#define CGTS_CU15_TD_TCP_CTRL_REG__TD_MASK 0x0000007FL 26801#define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x00000080L 26802#define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x00000300L 26803#define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x00000400L 26804#define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x00000800L 26805#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_MASK 0x007F0000L 26806#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_OVERRIDE_MASK 0x00800000L 26807#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_BUSY_OVERRIDE_MASK 0x03000000L 26808#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_LS_OVERRIDE_MASK 0x04000000L 26809#define CGTS_CU15_TD_TCP_CTRL_REG__TCPF_SIMDBUSY_OVERRIDE_MASK 0x08000000L 26810//CGTS_CU0_TCPI_CTRL_REG 26811#define CGTS_CU0_TCPI_CTRL_REG__TCPI__SHIFT 0x0 26812#define CGTS_CU0_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 26813#define CGTS_CU0_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 26814#define CGTS_CU0_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa 26815#define CGTS_CU0_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb 26816#define CGTS_CU0_TCPI_CTRL_REG__RESERVED__SHIFT 0xc 26817#define CGTS_CU0_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL 26818#define CGTS_CU0_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L 26819#define CGTS_CU0_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L 26820#define CGTS_CU0_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L 26821#define CGTS_CU0_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L 26822#define CGTS_CU0_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L 26823//CGTS_CU1_TCPI_CTRL_REG 26824#define CGTS_CU1_TCPI_CTRL_REG__TCPI__SHIFT 0x0 26825#define CGTS_CU1_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 26826#define CGTS_CU1_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 26827#define CGTS_CU1_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa 26828#define CGTS_CU1_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb 26829#define CGTS_CU1_TCPI_CTRL_REG__RESERVED__SHIFT 0xc 26830#define CGTS_CU1_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL 26831#define CGTS_CU1_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L 26832#define CGTS_CU1_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L 26833#define CGTS_CU1_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L 26834#define CGTS_CU1_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L 26835#define CGTS_CU1_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L 26836//CGTS_CU2_TCPI_CTRL_REG 26837#define CGTS_CU2_TCPI_CTRL_REG__TCPI__SHIFT 0x0 26838#define CGTS_CU2_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 26839#define CGTS_CU2_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 26840#define CGTS_CU2_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa 26841#define CGTS_CU2_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb 26842#define CGTS_CU2_TCPI_CTRL_REG__RESERVED__SHIFT 0xc 26843#define CGTS_CU2_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL 26844#define CGTS_CU2_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L 26845#define CGTS_CU2_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L 26846#define CGTS_CU2_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L 26847#define CGTS_CU2_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L 26848#define CGTS_CU2_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L 26849//CGTS_CU3_TCPI_CTRL_REG 26850#define CGTS_CU3_TCPI_CTRL_REG__TCPI__SHIFT 0x0 26851#define CGTS_CU3_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 26852#define CGTS_CU3_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 26853#define CGTS_CU3_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa 26854#define CGTS_CU3_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb 26855#define CGTS_CU3_TCPI_CTRL_REG__RESERVED__SHIFT 0xc 26856#define CGTS_CU3_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL 26857#define CGTS_CU3_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L 26858#define CGTS_CU3_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L 26859#define CGTS_CU3_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L 26860#define CGTS_CU3_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L 26861#define CGTS_CU3_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L 26862//CGTS_CU4_TCPI_CTRL_REG 26863#define CGTS_CU4_TCPI_CTRL_REG__TCPI__SHIFT 0x0 26864#define CGTS_CU4_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 26865#define CGTS_CU4_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 26866#define CGTS_CU4_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa 26867#define CGTS_CU4_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb 26868#define CGTS_CU4_TCPI_CTRL_REG__RESERVED__SHIFT 0xc 26869#define CGTS_CU4_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL 26870#define CGTS_CU4_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L 26871#define CGTS_CU4_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L 26872#define CGTS_CU4_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L 26873#define CGTS_CU4_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L 26874#define CGTS_CU4_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L 26875//CGTS_CU5_TCPI_CTRL_REG 26876#define CGTS_CU5_TCPI_CTRL_REG__TCPI__SHIFT 0x0 26877#define CGTS_CU5_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 26878#define CGTS_CU5_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 26879#define CGTS_CU5_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa 26880#define CGTS_CU5_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb 26881#define CGTS_CU5_TCPI_CTRL_REG__RESERVED__SHIFT 0xc 26882#define CGTS_CU5_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL 26883#define CGTS_CU5_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L 26884#define CGTS_CU5_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L 26885#define CGTS_CU5_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L 26886#define CGTS_CU5_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L 26887#define CGTS_CU5_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L 26888//CGTS_CU6_TCPI_CTRL_REG 26889#define CGTS_CU6_TCPI_CTRL_REG__TCPI__SHIFT 0x0 26890#define CGTS_CU6_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 26891#define CGTS_CU6_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 26892#define CGTS_CU6_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa 26893#define CGTS_CU6_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb 26894#define CGTS_CU6_TCPI_CTRL_REG__RESERVED__SHIFT 0xc 26895#define CGTS_CU6_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL 26896#define CGTS_CU6_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L 26897#define CGTS_CU6_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L 26898#define CGTS_CU6_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L 26899#define CGTS_CU6_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L 26900#define CGTS_CU6_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L 26901//CGTS_CU7_TCPI_CTRL_REG 26902#define CGTS_CU7_TCPI_CTRL_REG__TCPI__SHIFT 0x0 26903#define CGTS_CU7_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 26904#define CGTS_CU7_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 26905#define CGTS_CU7_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa 26906#define CGTS_CU7_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb 26907#define CGTS_CU7_TCPI_CTRL_REG__RESERVED__SHIFT 0xc 26908#define CGTS_CU7_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL 26909#define CGTS_CU7_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L 26910#define CGTS_CU7_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L 26911#define CGTS_CU7_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L 26912#define CGTS_CU7_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L 26913#define CGTS_CU7_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L 26914//CGTS_CU8_TCPI_CTRL_REG 26915#define CGTS_CU8_TCPI_CTRL_REG__TCPI__SHIFT 0x0 26916#define CGTS_CU8_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 26917#define CGTS_CU8_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 26918#define CGTS_CU8_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa 26919#define CGTS_CU8_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb 26920#define CGTS_CU8_TCPI_CTRL_REG__RESERVED__SHIFT 0xc 26921#define CGTS_CU8_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL 26922#define CGTS_CU8_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L 26923#define CGTS_CU8_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L 26924#define CGTS_CU8_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L 26925#define CGTS_CU8_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L 26926#define CGTS_CU8_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L 26927//CGTS_CU9_TCPI_CTRL_REG 26928#define CGTS_CU9_TCPI_CTRL_REG__TCPI__SHIFT 0x0 26929#define CGTS_CU9_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 26930#define CGTS_CU9_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 26931#define CGTS_CU9_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa 26932#define CGTS_CU9_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb 26933#define CGTS_CU9_TCPI_CTRL_REG__RESERVED__SHIFT 0xc 26934#define CGTS_CU9_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL 26935#define CGTS_CU9_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L 26936#define CGTS_CU9_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L 26937#define CGTS_CU9_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L 26938#define CGTS_CU9_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L 26939#define CGTS_CU9_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L 26940//CGTS_CU10_TCPI_CTRL_REG 26941#define CGTS_CU10_TCPI_CTRL_REG__TCPI__SHIFT 0x0 26942#define CGTS_CU10_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 26943#define CGTS_CU10_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 26944#define CGTS_CU10_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa 26945#define CGTS_CU10_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb 26946#define CGTS_CU10_TCPI_CTRL_REG__RESERVED__SHIFT 0xc 26947#define CGTS_CU10_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL 26948#define CGTS_CU10_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L 26949#define CGTS_CU10_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L 26950#define CGTS_CU10_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L 26951#define CGTS_CU10_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L 26952#define CGTS_CU10_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L 26953//CGTS_CU11_TCPI_CTRL_REG 26954#define CGTS_CU11_TCPI_CTRL_REG__TCPI__SHIFT 0x0 26955#define CGTS_CU11_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 26956#define CGTS_CU11_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 26957#define CGTS_CU11_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa 26958#define CGTS_CU11_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb 26959#define CGTS_CU11_TCPI_CTRL_REG__RESERVED__SHIFT 0xc 26960#define CGTS_CU11_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL 26961#define CGTS_CU11_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L 26962#define CGTS_CU11_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L 26963#define CGTS_CU11_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L 26964#define CGTS_CU11_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L 26965#define CGTS_CU11_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L 26966//CGTS_CU12_TCPI_CTRL_REG 26967#define CGTS_CU12_TCPI_CTRL_REG__TCPI__SHIFT 0x0 26968#define CGTS_CU12_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 26969#define CGTS_CU12_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 26970#define CGTS_CU12_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa 26971#define CGTS_CU12_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb 26972#define CGTS_CU12_TCPI_CTRL_REG__RESERVED__SHIFT 0xc 26973#define CGTS_CU12_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL 26974#define CGTS_CU12_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L 26975#define CGTS_CU12_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L 26976#define CGTS_CU12_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L 26977#define CGTS_CU12_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L 26978#define CGTS_CU12_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L 26979//CGTS_CU13_TCPI_CTRL_REG 26980#define CGTS_CU13_TCPI_CTRL_REG__TCPI__SHIFT 0x0 26981#define CGTS_CU13_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 26982#define CGTS_CU13_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 26983#define CGTS_CU13_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa 26984#define CGTS_CU13_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb 26985#define CGTS_CU13_TCPI_CTRL_REG__RESERVED__SHIFT 0xc 26986#define CGTS_CU13_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL 26987#define CGTS_CU13_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L 26988#define CGTS_CU13_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L 26989#define CGTS_CU13_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L 26990#define CGTS_CU13_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L 26991#define CGTS_CU13_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L 26992//CGTS_CU14_TCPI_CTRL_REG 26993#define CGTS_CU14_TCPI_CTRL_REG__TCPI__SHIFT 0x0 26994#define CGTS_CU14_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 26995#define CGTS_CU14_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 26996#define CGTS_CU14_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa 26997#define CGTS_CU14_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb 26998#define CGTS_CU14_TCPI_CTRL_REG__RESERVED__SHIFT 0xc 26999#define CGTS_CU14_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL 27000#define CGTS_CU14_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L
27001#define CGTS_CU14_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L 27002#define CGTS_CU14_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L 27003#define CGTS_CU14_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L 27004#define CGTS_CU14_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L 27005//CGTS_CU15_TCPI_CTRL_REG 27006#define CGTS_CU15_TCPI_CTRL_REG__TCPI__SHIFT 0x0 27007#define CGTS_CU15_TCPI_CTRL_REG__TCPI_OVERRIDE__SHIFT 0x7 27008#define CGTS_CU15_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE__SHIFT 0x8 27009#define CGTS_CU15_TCPI_CTRL_REG__TCPI_LS_OVERRIDE__SHIFT 0xa 27010#define CGTS_CU15_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE__SHIFT 0xb 27011#define CGTS_CU15_TCPI_CTRL_REG__RESERVED__SHIFT 0xc 27012#define CGTS_CU15_TCPI_CTRL_REG__TCPI_MASK 0x0000007FL 27013#define CGTS_CU15_TCPI_CTRL_REG__TCPI_OVERRIDE_MASK 0x00000080L 27014#define CGTS_CU15_TCPI_CTRL_REG__TCPI_BUSY_OVERRIDE_MASK 0x00000300L 27015#define CGTS_CU15_TCPI_CTRL_REG__TCPI_LS_OVERRIDE_MASK 0x00000400L 27016#define CGTS_CU15_TCPI_CTRL_REG__TCPI_SIMDBUSY_OVERRIDE_MASK 0x00000800L 27017#define CGTS_CU15_TCPI_CTRL_REG__RESERVED_MASK 0xFFFFF000L 27018//CGTT_SPI_CLK_CTRL 27019#define CGTT_SPI_CLK_CTRL__ON_DELAY__SHIFT 0x0 27020#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 27021#define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x12 27022#define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x18 27023#define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE__SHIFT 0x1a 27024#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE__SHIFT 0x1b 27025#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE__SHIFT 0x1c 27026#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x1d 27027#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE__SHIFT 0x1e 27028#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f 27029#define CGTT_SPI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 27030#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 27031#define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0x00FC0000L 27032#define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x01000000L 27033#define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE_MASK 0x04000000L 27034#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE_MASK 0x08000000L 27035#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE_MASK 0x10000000L 27036#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE_MASK 0x20000000L 27037#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE_MASK 0x40000000L 27038#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L 27039//CGTT_PC_CLK_CTRL 27040#define CGTT_PC_CLK_CTRL__ON_DELAY__SHIFT 0x0 27041#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 27042#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x12 27043#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x18 27044#define CGTT_PC_CLK_CTRL__PC_WRITE_CLK_EN_OVERRIDE__SHIFT 0x19 27045#define CGTT_PC_CLK_CTRL__PC_READ_CLK_EN_OVERRIDE__SHIFT 0x1a 27046#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b 27047#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c 27048#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d 27049#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e 27050#define CGTT_PC_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f 27051#define CGTT_PC_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 27052#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 27053#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0x00FC0000L 27054#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x01000000L 27055#define CGTT_PC_CLK_CTRL__PC_WRITE_CLK_EN_OVERRIDE_MASK 0x02000000L 27056#define CGTT_PC_CLK_CTRL__PC_READ_CLK_EN_OVERRIDE_MASK 0x04000000L 27057#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE_MASK 0x08000000L 27058#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000L 27059#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000L 27060#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000L 27061#define CGTT_PC_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L 27062//CGTT_BCI_CLK_CTRL 27063#define CGTT_BCI_CLK_CTRL__ON_DELAY__SHIFT 0x0 27064#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 27065#define CGTT_BCI_CLK_CTRL__RESERVED__SHIFT 0xc 27066#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 27067#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 27068#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 27069#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 27070#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 27071#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 27072#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 27073#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 27074#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE__SHIFT 0x18 27075#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE__SHIFT 0x19 27076#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE__SHIFT 0x1a 27077#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b 27078#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c 27079#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d 27080#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e 27081#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f 27082#define CGTT_BCI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 27083#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 27084#define CGTT_BCI_CLK_CTRL__RESERVED_MASK 0x0000F000L 27085#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L 27086#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L 27087#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L 27088#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L 27089#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L 27090#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L 27091#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L 27092#define CGTT_BCI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L 27093#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE_MASK 0x01000000L 27094#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE_MASK 0x02000000L 27095#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE_MASK 0x04000000L 27096#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE_MASK 0x08000000L 27097#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000L 27098#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000L 27099#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000L 27100#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L 27101//CGTT_VGT_CLK_CTRL 27102#define CGTT_VGT_CLK_CTRL__ON_DELAY__SHIFT 0x0 27103#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 27104#define CGTT_VGT_CLK_CTRL__PERF_ENABLE__SHIFT 0xf 27105#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 27106#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 27107#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 27108#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 27109#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 27110#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 27111#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 27112#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE9__SHIFT 0x18 27113#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE8__SHIFT 0x19 27114#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x1a 27115#define CGTT_VGT_CLK_CTRL__PRIMGEN_OVERRIDE__SHIFT 0x1b 27116#define CGTT_VGT_CLK_CTRL__TESS_OVERRIDE__SHIFT 0x1c 27117#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE__SHIFT 0x1d 27118#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e 27119#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f 27120#define CGTT_VGT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 27121#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 27122#define CGTT_VGT_CLK_CTRL__PERF_ENABLE_MASK 0x00008000L 27123#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L 27124#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L 27125#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L 27126#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L 27127#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L 27128#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L 27129#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L 27130#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE9_MASK 0x01000000L 27131#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE8_MASK 0x02000000L 27132#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x04000000L 27133#define CGTT_VGT_CLK_CTRL__PRIMGEN_OVERRIDE_MASK 0x08000000L 27134#define CGTT_VGT_CLK_CTRL__TESS_OVERRIDE_MASK 0x10000000L 27135#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE_MASK 0x20000000L 27136#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L 27137#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L 27138//CGTT_IA_CLK_CTRL 27139#define CGTT_IA_CLK_CTRL__ON_DELAY__SHIFT 0x0 27140#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 27141#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 27142#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 27143#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 27144#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 27145#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 27146#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 27147#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 27148#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 27149#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 27150#define CGTT_IA_CLK_CTRL__PERF_ENABLE__SHIFT 0x19 27151#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 27152#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 27153#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 27154#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e 27155#define CGTT_IA_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f 27156#define CGTT_IA_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 27157#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 27158#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L 27159#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L 27160#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L 27161#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L 27162#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L 27163#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L 27164#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L 27165#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L 27166#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L 27167#define CGTT_IA_CLK_CTRL__PERF_ENABLE_MASK 0x02000000L 27168#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L 27169#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L 27170#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L 27171#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L 27172#define CGTT_IA_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L 27173//CGTT_WD_CLK_CTRL 27174#define CGTT_WD_CLK_CTRL__ON_DELAY__SHIFT 0x0 27175#define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 27176#define CGTT_WD_CLK_CTRL__PERF_ENABLE__SHIFT 0xf 27177#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 27178#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 27179#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 27180#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 27181#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 27182#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 27183#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 27184#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE8__SHIFT 0x19 27185#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x1a 27186#define CGTT_WD_CLK_CTRL__PRIMGEN_OVERRIDE__SHIFT 0x1b 27187#define CGTT_WD_CLK_CTRL__TESS_OVERRIDE__SHIFT 0x1c 27188#define CGTT_WD_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1d 27189#define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE__SHIFT 0x1e 27190#define CGTT_WD_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f 27191#define CGTT_WD_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 27192#define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 27193#define CGTT_WD_CLK_CTRL__PERF_ENABLE_MASK 0x00008000L 27194#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L 27195#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L 27196#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L 27197#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L 27198#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L 27199#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L 27200#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L 27201#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE8_MASK 0x02000000L 27202#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x04000000L 27203#define CGTT_WD_CLK_CTRL__PRIMGEN_OVERRIDE_MASK 0x08000000L 27204#define CGTT_WD_CLK_CTRL__TESS_OVERRIDE_MASK 0x10000000L 27205#define CGTT_WD_CLK_CTRL__CORE_OVERRIDE_MASK 0x20000000L 27206#define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE_MASK 0x40000000L 27207#define CGTT_WD_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L 27208//CGTT_PA_CLK_CTRL 27209#define CGTT_PA_CLK_CTRL__ON_DELAY__SHIFT 0x0 27210#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 27211#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 27212#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 27213#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 27214#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 27215#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 27216#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 27217#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 27218#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 27219#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 27220#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 27221#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 27222#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 27223#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE__SHIFT 0x1d 27224#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE__SHIFT 0x1e 27225#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE__SHIFT 0x1f 27226#define CGTT_PA_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 27227#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 27228#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L 27229#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L 27230#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L 27231#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L 27232#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L 27233#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L 27234#define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L 27235#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L 27236#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L 27237#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L 27238#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L 27239#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L 27240#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE_MASK 0x20000000L 27241#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE_MASK 0x40000000L 27242#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE_MASK 0x80000000L 27243//CGTT_SC_CLK_CTRL0 27244#define CGTT_SC_CLK_CTRL0__ON_DELAY__SHIFT 0x0 27245#define CGTT_SC_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 27246#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_STALL_OVERRIDE__SHIFT 0x10 27247#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE5__SHIFT 0x11 27248#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE4__SHIFT 0x12 27249#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE3__SHIFT 0x13 27250#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE2__SHIFT 0x14 27251#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE1__SHIFT 0x15 27252#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE0__SHIFT 0x16 27253#define CGTT_SC_CLK_CTRL0__REG_CLK_STALL_OVERRIDE__SHIFT 0x17 27254#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_OVERRIDE__SHIFT 0x18 27255#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x19 27256#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1a 27257#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1b 27258#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1c 27259#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1d 27260#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1e 27261#define CGTT_SC_CLK_CTRL0__REG_CLK_OVERRIDE__SHIFT 0x1f 27262#define CGTT_SC_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL 27263#define CGTT_SC_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L 27264#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_STALL_OVERRIDE_MASK 0x00010000L 27265#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE5_MASK 0x00020000L 27266#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE4_MASK 0x00040000L 27267#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE3_MASK 0x00080000L 27268#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE2_MASK 0x00100000L 27269#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE1_MASK 0x00200000L 27270#define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE0_MASK 0x00400000L 27271#define CGTT_SC_CLK_CTRL0__REG_CLK_STALL_OVERRIDE_MASK 0x00800000L 27272#define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_OVERRIDE_MASK 0x01000000L 27273#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x02000000L 27274#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x04000000L 27275#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x08000000L 27276#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x10000000L 27277#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x20000000L 27278#define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x40000000L 27279#define CGTT_SC_CLK_CTRL0__REG_CLK_OVERRIDE_MASK 0x80000000L 27280//CGTT_SC_CLK_CTRL1 27281#define CGTT_SC_CLK_CTRL1__ON_DELAY__SHIFT 0x0 27282#define CGTT_SC_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x4 27283#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE__SHIFT 0x11 27284#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_STALL_OVERRIDE__SHIFT 0x12 27285#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_STALL_OVERRIDE__SHIFT 0x13 27286#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_STALL_OVERRIDE__SHIFT 0x14 27287#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_STALL_OVERRIDE__SHIFT 0x15 27288#define CGTT_SC_CLK_CTRL1__PBB_CLK_STALL_OVERRIDE__SHIFT 0x16 27289#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE__SHIFT 0x19 27290#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_OVERRIDE__SHIFT 0x1a 27291#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_OVERRIDE__SHIFT 0x1b 27292#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_OVERRIDE__SHIFT 0x1c 27293#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_OVERRIDE__SHIFT 0x1d 27294#define CGTT_SC_CLK_CTRL1__PBB_CLK_OVERRIDE__SHIFT 0x1e 27295#define CGTT_SC_CLK_CTRL1__ON_DELAY_MASK 0x0000000FL 27296#define CGTT_SC_CLK_CTRL1__OFF_HYSTERESIS_MASK 0x00000FF0L 27297#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE_MASK 0x00020000L 27298#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_STALL_OVERRIDE_MASK 0x00040000L 27299#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_STALL_OVERRIDE_MASK 0x00080000L 27300#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_STALL_OVERRIDE_MASK 0x00100000L 27301#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_STALL_OVERRIDE_MASK 0x00200000L 27302#define CGTT_SC_CLK_CTRL1__PBB_CLK_STALL_OVERRIDE_MASK 0x00400000L 27303#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE_MASK 0x02000000L 27304#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_OVERRIDE_MASK 0x04000000L 27305#define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_OVERRIDE_MASK 0x08000000L 27306#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_OVERRIDE_MASK 0x10000000L 27307#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_OVERRIDE_MASK 0x20000000L 27308#define CGTT_SC_CLK_CTRL1__PBB_CLK_OVERRIDE_MASK 0x40000000L 27309//CGTT_SQ_CLK_CTRL 27310#define CGTT_SQ_CLK_CTRL__ON_DELAY__SHIFT 0x0 27311#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 27312#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 27313#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 27314#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 27315#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 27316#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 27317#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 27318#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 27319#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 27320#define CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x1d 27321#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e 27322#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f 27323#define CGTT_SQ_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 27324#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 27325#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L 27326#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L 27327#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L 27328#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L 27329#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L 27330#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L 27331#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L 27332#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L 27333#define CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE_MASK 0x20000000L 27334#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L 27335#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L 27336//CGTT_SQG_CLK_CTRL 27337#define CGTT_SQG_CLK_CTRL__ON_DELAY__SHIFT 0x0 27338#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 27339#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 27340#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 27341#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 27342#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 27343#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 27344#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 27345#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 27346#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 27347#define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE__SHIFT 0x1c 27348#define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x1d 27349#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e 27350#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f 27351#define CGTT_SQG_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 27352#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 27353#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L 27354#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L 27355#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L 27356#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L 27357#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L 27358#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L 27359#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L 27360#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L 27361#define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE_MASK 0x10000000L 27362#define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE_MASK 0x20000000L 27363#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L 27364#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L 27365//SQ_ALU_CLK_CTRL 27366#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0 27367#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10 27368#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0x0000FFFFL 27369#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xFFFF0000L 27370//SQ_TEX_CLK_CTRL 27371#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0 27372#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10 27373#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0x0000FFFFL 27374#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xFFFF0000L 27375//SQ_LDS_CLK_CTRL 27376#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0 27377#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10 27378#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0x0000FFFFL 27379#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xFFFF0000L 27380//SQ_POWER_THROTTLE 27381#define SQ_POWER_THROTTLE__MIN_POWER__SHIFT 0x0 27382#define SQ_POWER_THROTTLE__MAX_POWER__SHIFT 0x10 27383#define SQ_POWER_THROTTLE__PHASE_OFFSET__SHIFT 0x1e 27384#define SQ_POWER_THROTTLE__MIN_POWER_MASK 0x00003FFFL 27385#define SQ_POWER_THROTTLE__MAX_POWER_MASK 0x3FFF0000L 27386#define SQ_POWER_THROTTLE__PHASE_OFFSET_MASK 0xC0000000L 27387//SQ_POWER_THROTTLE2 27388#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA__SHIFT 0x0 27389#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 27390#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b 27391#define SQ_POWER_THROTTLE2__USE_REF_CLOCK__SHIFT 0x1f 27392#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK 0x00003FFFL 27393#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L 27394#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L 27395#define SQ_POWER_THROTTLE2__USE_REF_CLOCK_MASK 0x80000000L 27396//CGTT_SX_CLK_CTRL0 27397#define CGTT_SX_CLK_CTRL0__ON_DELAY__SHIFT 0x0 27398#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 27399#define CGTT_SX_CLK_CTRL0__RESERVED__SHIFT 0xc 27400#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE7__SHIFT 0x10 27401#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE6__SHIFT 0x11 27402#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE5__SHIFT 0x12 27403#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE4__SHIFT 0x13 27404#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE3__SHIFT 0x14 27405#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE2__SHIFT 0x15 27406#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE1__SHIFT 0x16 27407#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE0__SHIFT 0x17 27408#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7__SHIFT 0x18 27409#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT 0x19 27410#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x1a 27411#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1b 27412#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1c 27413#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1d 27414#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e 27415#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f 27416#define CGTT_SX_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL 27417#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L 27418#define CGTT_SX_CLK_CTRL0__RESERVED_MASK 0x0000F000L 27419#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE7_MASK 0x00010000L 27420#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE6_MASK 0x00020000L 27421#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE5_MASK 0x00040000L 27422#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE4_MASK 0x00080000L 27423#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE3_MASK 0x00100000L 27424#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE2_MASK 0x00200000L 27425#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE1_MASK 0x00400000L 27426#define CGTT_SX_CLK_CTRL0__SOFT_STALL_OVERRIDE0_MASK 0x00800000L 27427#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7_MASK 0x01000000L 27428#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6_MASK 0x02000000L 27429#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x04000000L 27430#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x08000000L 27431#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x10000000L 27432#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x20000000L 27433#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000L 27434#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000L 27435//CGTT_SX_CLK_CTRL1 27436#define CGTT_SX_CLK_CTRL1__ON_DELAY__SHIFT 0x0 27437#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x4 27438#define CGTT_SX_CLK_CTRL1__RESERVED__SHIFT 0xc 27439#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE7__SHIFT 0x10 27440#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE6__SHIFT 0x11 27441#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE5__SHIFT 0x12 27442#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE4__SHIFT 0x13 27443#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE3__SHIFT 0x14 27444#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE2__SHIFT 0x15 27445#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE1__SHIFT 0x16 27446#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE0__SHIFT 0x17 27447#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6__SHIFT 0x19 27448#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5__SHIFT 0x1a 27449#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4__SHIFT 0x1b 27450#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3__SHIFT 0x1c 27451#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2__SHIFT 0x1d 27452#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1__SHIFT 0x1e 27453#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0__SHIFT 0x1f 27454#define CGTT_SX_CLK_CTRL1__ON_DELAY_MASK 0x0000000FL 27455#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS_MASK 0x00000FF0L 27456#define CGTT_SX_CLK_CTRL1__RESERVED_MASK 0x0000F000L 27457#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE7_MASK 0x00010000L 27458#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE6_MASK 0x00020000L 27459#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE5_MASK 0x00040000L 27460#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE4_MASK 0x00080000L 27461#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE3_MASK 0x00100000L 27462#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE2_MASK 0x00200000L 27463#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE1_MASK 0x00400000L 27464#define CGTT_SX_CLK_CTRL1__SOFT_STALL_OVERRIDE0_MASK 0x00800000L 27465#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6_MASK 0x02000000L 27466#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5_MASK 0x04000000L 27467#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4_MASK 0x08000000L 27468#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3_MASK 0x10000000L 27469#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2_MASK 0x20000000L 27470#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1_MASK 0x40000000L 27471#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0_MASK 0x80000000L 27472//CGTT_SX_CLK_CTRL2 27473#define CGTT_SX_CLK_CTRL2__ON_DELAY__SHIFT 0x0 27474#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS__SHIFT 0x4 27475#define CGTT_SX_CLK_CTRL2__RESERVED__SHIFT 0xd 27476#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE7__SHIFT 0x10 27477#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE6__SHIFT 0x11 27478#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE5__SHIFT 0x12 27479#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE4__SHIFT 0x13 27480#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE3__SHIFT 0x14 27481#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE2__SHIFT 0x15 27482#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE1__SHIFT 0x16 27483#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE0__SHIFT 0x17 27484#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6__SHIFT 0x19 27485#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5__SHIFT 0x1a 27486#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4__SHIFT 0x1b 27487#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3__SHIFT 0x1c 27488#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2__SHIFT 0x1d 27489#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1__SHIFT 0x1e 27490#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0__SHIFT 0x1f 27491#define CGTT_SX_CLK_CTRL2__ON_DELAY_MASK 0x0000000FL 27492#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS_MASK 0x00000FF0L 27493#define CGTT_SX_CLK_CTRL2__RESERVED_MASK 0x0000E000L 27494#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE7_MASK 0x00010000L 27495#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE6_MASK 0x00020000L 27496#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE5_MASK 0x00040000L 27497#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE4_MASK 0x00080000L 27498#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE3_MASK 0x00100000L 27499#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE2_MASK 0x00200000L 27500#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE1_MASK 0x00400000L 27501#define CGTT_SX_CLK_CTRL2__SOFT_STALL_OVERRIDE0_MASK 0x00800000L 27502#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6_MASK 0x02000000L 27503#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5_MASK 0x04000000L 27504#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4_MASK 0x08000000L 27505#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3_MASK 0x10000000L 27506#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2_MASK 0x20000000L 27507#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1_MASK 0x40000000L 27508#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0_MASK 0x80000000L 27509//CGTT_SX_CLK_CTRL3 27510#define CGTT_SX_CLK_CTRL3__ON_DELAY__SHIFT 0x0 27511#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS__SHIFT 0x4 27512#define CGTT_SX_CLK_CTRL3__RESERVED__SHIFT 0xd 27513#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE7__SHIFT 0x10 27514#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE6__SHIFT 0x11 27515#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE5__SHIFT 0x12 27516#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE4__SHIFT 0x13 27517#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE3__SHIFT 0x14 27518#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE2__SHIFT 0x15 27519#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE1__SHIFT 0x16 27520#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE0__SHIFT 0x17 27521#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6__SHIFT 0x19 27522#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5__SHIFT 0x1a 27523#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4__SHIFT 0x1b 27524#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3__SHIFT 0x1c 27525#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2__SHIFT 0x1d 27526#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1__SHIFT 0x1e 27527#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0__SHIFT 0x1f 27528#define CGTT_SX_CLK_CTRL3__ON_DELAY_MASK 0x0000000FL 27529#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS_MASK 0x00000FF0L 27530#define CGTT_SX_CLK_CTRL3__RESERVED_MASK 0x0000E000L 27531#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE7_MASK 0x00010000L 27532#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE6_MASK 0x00020000L 27533#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE5_MASK 0x00040000L 27534#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE4_MASK 0x00080000L 27535#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE3_MASK 0x00100000L 27536#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE2_MASK 0x00200000L 27537#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE1_MASK 0x00400000L 27538#define CGTT_SX_CLK_CTRL3__SOFT_STALL_OVERRIDE0_MASK 0x00800000L 27539#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6_MASK 0x02000000L 27540#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5_MASK 0x04000000L 27541#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4_MASK 0x08000000L 27542#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3_MASK 0x10000000L 27543#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2_MASK 0x20000000L 27544#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1_MASK 0x40000000L 27545#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0_MASK 0x80000000L 27546//CGTT_SX_CLK_CTRL4 27547#define CGTT_SX_CLK_CTRL4__ON_DELAY__SHIFT 0x0 27548#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS__SHIFT 0x4 27549#define CGTT_SX_CLK_CTRL4__RESERVED__SHIFT 0xc 27550#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE7__SHIFT 0x10 27551#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE6__SHIFT 0x11 27552#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE5__SHIFT 0x12 27553#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE4__SHIFT 0x13 27554#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE3__SHIFT 0x14 27555#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE2__SHIFT 0x15 27556#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE1__SHIFT 0x16 27557#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE0__SHIFT 0x17 27558#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6__SHIFT 0x19 27559#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5__SHIFT 0x1a 27560#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4__SHIFT 0x1b 27561#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3__SHIFT 0x1c 27562#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2__SHIFT 0x1d 27563#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1__SHIFT 0x1e 27564#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0__SHIFT 0x1f 27565#define CGTT_SX_CLK_CTRL4__ON_DELAY_MASK 0x0000000FL 27566#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS_MASK 0x00000FF0L 27567#define CGTT_SX_CLK_CTRL4__RESERVED_MASK 0x0000F000L 27568#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE7_MASK 0x00010000L 27569#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE6_MASK 0x00020000L 27570#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE5_MASK 0x00040000L 27571#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE4_MASK 0x00080000L 27572#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE3_MASK 0x00100000L 27573#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE2_MASK 0x00200000L 27574#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE1_MASK 0x00400000L 27575#define CGTT_SX_CLK_CTRL4__SOFT_STALL_OVERRIDE0_MASK 0x00800000L 27576#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6_MASK 0x02000000L 27577#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5_MASK 0x04000000L 27578#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4_MASK 0x08000000L 27579#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3_MASK 0x10000000L 27580#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2_MASK 0x20000000L 27581#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1_MASK 0x40000000L 27582#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0_MASK 0x80000000L 27583//TD_CGTT_CTRL 27584#define TD_CGTT_CTRL__ON_DELAY__SHIFT 0x0 27585#define TD_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4 27586#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 27587#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 27588#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 27589#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 27590#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 27591#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 27592#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 27593#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 27594#define TD_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 27595#define TD_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 27596#define TD_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 27597#define TD_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 27598#define TD_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 27599#define TD_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 27600#define TD_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 27601#define TD_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 27602#define TD_CGTT_CTRL__ON_DELAY_MASK 0x0000000FL 27603#define TD_CGTT_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 27604#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L 27605#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L 27606#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L 27607#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L 27608#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L 27609#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L 27610#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L 27611#define TD_CGTT_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L 27612#define TD_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L 27613#define TD_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L 27614#define TD_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L 27615#define TD_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L 27616#define TD_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L 27617#define TD_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L 27618#define TD_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L 27619#define TD_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L 27620//TA_CGTT_CTRL 27621#define TA_CGTT_CTRL__ON_DELAY__SHIFT 0x0 27622#define TA_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4 27623#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 27624#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 27625#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 27626#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 27627#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 27628#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 27629#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 27630#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 27631#define TA_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 27632#define TA_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 27633#define TA_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 27634#define TA_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 27635#define TA_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 27636#define TA_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 27637#define TA_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 27638#define TA_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 27639#define TA_CGTT_CTRL__ON_DELAY_MASK 0x0000000FL 27640#define TA_CGTT_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 27641#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L 27642#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L 27643#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L 27644#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L 27645#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L 27646#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L 27647#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L 27648#define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L 27649#define TA_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L 27650#define TA_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L 27651#define TA_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L 27652#define TA_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L 27653#define TA_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L 27654#define TA_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L 27655#define TA_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L 27656#define TA_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L 27657//CGTT_TCPI_CLK_CTRL 27658#define CGTT_TCPI_CLK_CTRL__ON_DELAY__SHIFT 0x0 27659#define CGTT_TCPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 27660#define CGTT_TCPI_CLK_CTRL__SPARE__SHIFT 0xc 27661#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 27662#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 27663#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 27664#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 27665#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 27666#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 27667#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 27668#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 27669#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 27670#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 27671#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 27672#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 27673#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 27674#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 27675#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 27676#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 27677#define CGTT_TCPI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 27678#define CGTT_TCPI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 27679#define CGTT_TCPI_CLK_CTRL__SPARE_MASK 0x0000F000L 27680#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L 27681#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L 27682#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L 27683#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L 27684#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L 27685#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L 27686#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L 27687#define CGTT_TCPI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L 27688#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L 27689#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L 27690#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L 27691#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L 27692#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L 27693#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L 27694#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L 27695#define CGTT_TCPI_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L 27696//CGTT_TCI_CLK_CTRL 27697#define CGTT_TCI_CLK_CTRL__ON_DELAY__SHIFT 0x0 27698#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 27699#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 27700#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 27701#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 27702#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 27703#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 27704#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 27705#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 27706#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 27707#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 27708#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 27709#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 27710#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 27711#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 27712#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 27713#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 27714#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 27715#define CGTT_TCI_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 27716#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 27717#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L 27718#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L 27719#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L 27720#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L 27721#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L 27722#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L 27723#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L 27724#define CGTT_TCI_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L 27725#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L 27726#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L 27727#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L 27728#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L 27729#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L 27730#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L 27731#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L 27732#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L 27733//CGTT_GDS_CLK_CTRL 27734#define CGTT_GDS_CLK_CTRL__ON_DELAY__SHIFT 0x0 27735#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 27736#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 27737#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 27738#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 27739#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 27740#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 27741#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 27742#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 27743#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 27744#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 27745#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 27746#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 27747#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 27748#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 27749#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 27750#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 27751#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 27752#define CGTT_GDS_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 27753#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 27754#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L 27755#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L 27756#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L 27757#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L 27758#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L 27759#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L 27760#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L 27761#define CGTT_GDS_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L 27762#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L 27763#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L 27764#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L 27765#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L 27766#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L 27767#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L 27768#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L 27769#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L 27770//DB_CGTT_CLK_CTRL_0 27771#define DB_CGTT_CLK_CTRL_0__ON_DELAY__SHIFT 0x0 27772#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS__SHIFT 0x4 27773#define DB_CGTT_CLK_CTRL_0__RESERVED__SHIFT 0xc 27774#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE7__SHIFT 0x10 27775#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE6__SHIFT 0x11 27776#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE5__SHIFT 0x12 27777#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE4__SHIFT 0x13 27778#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE3__SHIFT 0x14 27779#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE2__SHIFT 0x15 27780#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE1__SHIFT 0x16 27781#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE0__SHIFT 0x17 27782#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7__SHIFT 0x18 27783#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6__SHIFT 0x19 27784#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5__SHIFT 0x1a 27785#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4__SHIFT 0x1b 27786#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3__SHIFT 0x1c 27787#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2__SHIFT 0x1d 27788#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1__SHIFT 0x1e 27789#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0__SHIFT 0x1f 27790#define DB_CGTT_CLK_CTRL_0__ON_DELAY_MASK 0x0000000FL 27791#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS_MASK 0x00000FF0L 27792#define DB_CGTT_CLK_CTRL_0__RESERVED_MASK 0x0000F000L 27793#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE7_MASK 0x00010000L 27794#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE6_MASK 0x00020000L 27795#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE5_MASK 0x00040000L 27796#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE4_MASK 0x00080000L 27797#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE3_MASK 0x00100000L 27798#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE2_MASK 0x00200000L 27799#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE1_MASK 0x00400000L 27800#define DB_CGTT_CLK_CTRL_0__SOFT_STALL_OVERRIDE0_MASK 0x00800000L 27801#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7_MASK 0x01000000L 27802#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6_MASK 0x02000000L 27803#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5_MASK 0x04000000L 27804#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4_MASK 0x08000000L 27805#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3_MASK 0x10000000L 27806#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2_MASK 0x20000000L 27807#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1_MASK 0x40000000L 27808#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0_MASK 0x80000000L 27809//CB_CGTT_SCLK_CTRL 27810#define CB_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 27811#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 27812#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 27813#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 27814#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 27815#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 27816#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 27817#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 27818#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 27819#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 27820#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 27821#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 27822#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 27823#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 27824#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 27825#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 27826#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 27827#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 27828#define CB_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL 27829#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 27830#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L 27831#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L 27832#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L 27833#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L 27834#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L 27835#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L 27836#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L 27837#define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L 27838#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L 27839#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L 27840#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L 27841#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L 27842#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L 27843#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L 27844#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L 27845#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L 27846//TCC_CGTT_SCLK_CTRL 27847#define TCC_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 27848#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 27849#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 27850#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 27851#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 27852#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 27853#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 27854#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 27855#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 27856#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 27857#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 27858#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 27859#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 27860#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 27861#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 27862#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 27863#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 27864#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 27865#define TCC_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL 27866#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 27867#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L 27868#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L 27869#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L 27870#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L 27871#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L 27872#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L 27873#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L 27874#define TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L 27875#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L 27876#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L 27877#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L 27878#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L 27879#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L 27880#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L 27881#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L 27882#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L 27883//TCA_CGTT_SCLK_CTRL 27884#define TCA_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 27885#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 27886#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 27887#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 27888#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 27889#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 27890#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 27891#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 27892#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 27893#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 27894#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 27895#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 27896#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 27897#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 27898#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 27899#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 27900#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 27901#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 27902#define TCA_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL 27903#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 27904#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L 27905#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L 27906#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L 27907#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L 27908#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L 27909#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L 27910#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L 27911#define TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L 27912#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L 27913#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L 27914#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L 27915#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L 27916#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L 27917#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L 27918#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L 27919#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L 27920//CGTT_CP_CLK_CTRL 27921#define CGTT_CP_CLK_CTRL__ON_DELAY__SHIFT 0x0 27922#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 27923#define CGTT_CP_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf 27924#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 27925#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 27926#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 27927#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 27928#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 27929#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 27930#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 27931#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 27932#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d 27933#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e 27934#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f 27935#define CGTT_CP_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 27936#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 27937#define CGTT_CP_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L 27938#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L 27939#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L 27940#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L 27941#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L 27942#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L 27943#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L 27944#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L 27945#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L 27946#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L 27947#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L 27948#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L 27949//CGTT_CPF_CLK_CTRL 27950#define CGTT_CPF_CLK_CTRL__ON_DELAY__SHIFT 0x0 27951#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 27952#define CGTT_CPF_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf 27953#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 27954#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 27955#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 27956#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 27957#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 27958#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 27959#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 27960#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 27961#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d 27962#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e 27963#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f 27964#define CGTT_CPF_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 27965#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 27966#define CGTT_CPF_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L 27967#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L 27968#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L 27969#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L 27970#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L 27971#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L 27972#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L 27973#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L 27974#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L 27975#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L 27976#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L 27977#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L 27978//CGTT_CPC_CLK_CTRL 27979#define CGTT_CPC_CLK_CTRL__ON_DELAY__SHIFT 0x0 27980#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 27981#define CGTT_CPC_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf 27982#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 27983#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 27984#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 27985#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 27986#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 27987#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 27988#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 27989#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 27990#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d 27991#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e 27992#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f 27993#define CGTT_CPC_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 27994#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 27995#define CGTT_CPC_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L 27996#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L 27997#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L 27998#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L 27999#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L 28000#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
28001#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L 28002#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L 28003#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L 28004#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L 28005#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L 28006#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L 28007//RLC_PWR_CTRL 28008#define RLC_PWR_CTRL__MON_CGPG_RTN_EN__SHIFT 0x0 28009#define RLC_PWR_CTRL__RESERVED__SHIFT 0x1 28010#define RLC_PWR_CTRL__DLDO_STATUS__SHIFT 0x8 28011#define RLC_PWR_CTRL__MON_CGPG_RTN_EN_MASK 0x00000001L 28012#define RLC_PWR_CTRL__RESERVED_MASK 0x000000FEL 28013#define RLC_PWR_CTRL__DLDO_STATUS_MASK 0x00000100L 28014//CGTT_RLC_CLK_CTRL 28015#define CGTT_RLC_CLK_CTRL__ON_DELAY__SHIFT 0x0 28016#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 28017#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 28018#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 28019#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 28020#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 28021#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 28022#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 28023#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 28024#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 28025#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e 28026#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f 28027#define CGTT_RLC_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 28028#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 28029#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L 28030#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L 28031#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L 28032#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L 28033#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L 28034#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L 28035#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L 28036#define CGTT_RLC_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L 28037#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L 28038#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L 28039//RLC_GFX_RM_CNTL 28040#define RLC_GFX_RM_CNTL__RLC_GFX_RM_VALID__SHIFT 0x0 28041#define RLC_GFX_RM_CNTL__RESERVED__SHIFT 0x1 28042#define RLC_GFX_RM_CNTL__RLC_GFX_RM_VALID_MASK 0x00000001L 28043#define RLC_GFX_RM_CNTL__RESERVED_MASK 0xFFFFFFFEL 28044//RMI_CGTT_SCLK_CTRL 28045#define RMI_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 28046#define RMI_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 28047#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 28048#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 28049#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 28050#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 28051#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 28052#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 28053#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 28054#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 28055#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 28056#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 28057#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 28058#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 28059#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 28060#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 28061#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 28062#define RMI_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL 28063#define RMI_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 28064#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L 28065#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L 28066#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L 28067#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L 28068#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L 28069#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L 28070#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L 28071#define RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L 28072#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L 28073#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L 28074#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L 28075#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L 28076#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L 28077#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L 28078#define RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L 28079//CGTT_TCPF_CLK_CTRL 28080#define CGTT_TCPF_CLK_CTRL__ON_DELAY__SHIFT 0x0 28081#define CGTT_TCPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 28082#define CGTT_TCPF_CLK_CTRL__SPARE__SHIFT 0xc 28083#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 28084#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 28085#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 28086#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 28087#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 28088#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 28089#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 28090#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 28091#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 28092#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 28093#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 28094#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 28095#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 28096#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 28097#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 28098#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 28099#define CGTT_TCPF_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 28100#define CGTT_TCPF_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 28101#define CGTT_TCPF_CLK_CTRL__SPARE_MASK 0x0000F000L 28102#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L 28103#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L 28104#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L 28105#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L 28106#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L 28107#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L 28108#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L 28109#define CGTT_TCPF_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L 28110#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L 28111#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L 28112#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L 28113#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L 28114#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L 28115#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L 28116#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L 28117#define CGTT_TCPF_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L 28118 28119 28120// addressBlock: gc_ea_pwrdec 28121//GCEA_CGTT_CLK_CTRL 28122#define GCEA_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 28123#define GCEA_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 28124#define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 28125#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e 28126#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f 28127#define GCEA_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 28128#define GCEA_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 28129#define GCEA_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 28130#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L 28131#define GCEA_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L 28132 28133 28134// addressBlock: gc_utcl2_vmsharedhvdec 28135//MC_VM_FB_SIZE_OFFSET_VF0 28136#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT 0x0 28137#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT 0x10 28138#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK 0x0000FFFFL 28139#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK 0xFFFF0000L 28140//MC_VM_FB_SIZE_OFFSET_VF1 28141#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT 0x0 28142#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT 0x10 28143#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK 0x0000FFFFL 28144#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK 0xFFFF0000L 28145//MC_VM_FB_SIZE_OFFSET_VF2 28146#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT 0x0 28147#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT 0x10 28148#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK 0x0000FFFFL 28149#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK 0xFFFF0000L 28150//MC_VM_FB_SIZE_OFFSET_VF3 28151#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT 0x0 28152#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT 0x10 28153#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK 0x0000FFFFL 28154#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK 0xFFFF0000L 28155//MC_VM_FB_SIZE_OFFSET_VF4 28156#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT 0x0 28157#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT 0x10 28158#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK 0x0000FFFFL 28159#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK 0xFFFF0000L 28160//MC_VM_FB_SIZE_OFFSET_VF5 28161#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT 0x0 28162#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT 0x10 28163#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK 0x0000FFFFL 28164#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK 0xFFFF0000L 28165//MC_VM_FB_SIZE_OFFSET_VF6 28166#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT 0x0 28167#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT 0x10 28168#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK 0x0000FFFFL 28169#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK 0xFFFF0000L 28170//MC_VM_FB_SIZE_OFFSET_VF7 28171#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT 0x0 28172#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT 0x10 28173#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK 0x0000FFFFL 28174#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK 0xFFFF0000L 28175//MC_VM_FB_SIZE_OFFSET_VF8 28176#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT 0x0 28177#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT 0x10 28178#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK 0x0000FFFFL 28179#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK 0xFFFF0000L 28180//MC_VM_FB_SIZE_OFFSET_VF9 28181#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT 0x0 28182#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT 0x10 28183#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK 0x0000FFFFL 28184#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK 0xFFFF0000L 28185//MC_VM_FB_SIZE_OFFSET_VF10 28186#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT 0x0 28187#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT 0x10 28188#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK 0x0000FFFFL 28189#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK 0xFFFF0000L 28190//MC_VM_FB_SIZE_OFFSET_VF11 28191#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT 0x0 28192#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT 0x10 28193#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK 0x0000FFFFL 28194#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK 0xFFFF0000L 28195//MC_VM_FB_SIZE_OFFSET_VF12 28196#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT 0x0 28197#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT 0x10 28198#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK 0x0000FFFFL 28199#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK 0xFFFF0000L 28200//MC_VM_FB_SIZE_OFFSET_VF13 28201#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT 0x0 28202#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT 0x10 28203#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK 0x0000FFFFL 28204#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK 0xFFFF0000L 28205//MC_VM_FB_SIZE_OFFSET_VF14 28206#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT 0x0 28207#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT 0x10 28208#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK 0x0000FFFFL 28209#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK 0xFFFF0000L 28210//MC_VM_FB_SIZE_OFFSET_VF15 28211#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT 0x0 28212#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT 0x10 28213#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK 0x0000FFFFL 28214#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK 0xFFFF0000L 28215//VM_IOMMU_MMIO_CNTRL_1 28216#define VM_IOMMU_MMIO_CNTRL_1__MARC_EN__SHIFT 0x8 28217#define VM_IOMMU_MMIO_CNTRL_1__MARC_EN_MASK 0x00000100L 28218//MC_VM_MARC_BASE_LO_0 28219#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT 0xc 28220#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK 0xFFFFF000L 28221//MC_VM_MARC_BASE_LO_1 28222#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT 0xc 28223#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK 0xFFFFF000L 28224//MC_VM_MARC_BASE_LO_2 28225#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT 0xc 28226#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK 0xFFFFF000L 28227//MC_VM_MARC_BASE_LO_3 28228#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT 0xc 28229#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK 0xFFFFF000L 28230//MC_VM_MARC_BASE_HI_0 28231#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT 0x0 28232#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK 0x000FFFFFL 28233//MC_VM_MARC_BASE_HI_1 28234#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT 0x0 28235#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK 0x000FFFFFL 28236//MC_VM_MARC_BASE_HI_2 28237#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT 0x0 28238#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK 0x000FFFFFL 28239//MC_VM_MARC_BASE_HI_3 28240#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT 0x0 28241#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK 0x000FFFFFL 28242//MC_VM_MARC_RELOC_LO_0 28243#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT 0x0 28244#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT 0x1 28245#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT 0xc 28246#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK 0x00000001L 28247#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK 0x00000002L 28248#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK 0xFFFFF000L 28249//MC_VM_MARC_RELOC_LO_1 28250#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT 0x0 28251#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT 0x1 28252#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT 0xc 28253#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK 0x00000001L 28254#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK 0x00000002L 28255#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK 0xFFFFF000L 28256//MC_VM_MARC_RELOC_LO_2 28257#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT 0x0 28258#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT 0x1 28259#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT 0xc 28260#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK 0x00000001L 28261#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK 0x00000002L 28262#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK 0xFFFFF000L 28263//MC_VM_MARC_RELOC_LO_3 28264#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT 0x0 28265#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT 0x1 28266#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT 0xc 28267#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK 0x00000001L 28268#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK 0x00000002L 28269#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK 0xFFFFF000L 28270//MC_VM_MARC_RELOC_HI_0 28271#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT 0x0 28272#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK 0x000FFFFFL 28273//MC_VM_MARC_RELOC_HI_1 28274#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT 0x0 28275#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK 0x000FFFFFL 28276//MC_VM_MARC_RELOC_HI_2 28277#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT 0x0 28278#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK 0x000FFFFFL 28279//MC_VM_MARC_RELOC_HI_3 28280#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT 0x0 28281#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK 0x000FFFFFL 28282//MC_VM_MARC_LEN_LO_0 28283#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT 0xc 28284#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK 0xFFFFF000L 28285//MC_VM_MARC_LEN_LO_1 28286#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT 0xc 28287#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK 0xFFFFF000L 28288//MC_VM_MARC_LEN_LO_2 28289#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT 0xc 28290#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK 0xFFFFF000L 28291//MC_VM_MARC_LEN_LO_3 28292#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT 0xc 28293#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK 0xFFFFF000L 28294//MC_VM_MARC_LEN_HI_0 28295#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT 0x0 28296#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK 0x000FFFFFL 28297//MC_VM_MARC_LEN_HI_1 28298#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT 0x0 28299#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK 0x000FFFFFL 28300//MC_VM_MARC_LEN_HI_2 28301#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT 0x0 28302#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK 0x000FFFFFL 28303//MC_VM_MARC_LEN_HI_3 28304#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT 0x0 28305#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK 0x000FFFFFL 28306//VM_IOMMU_CONTROL_REGISTER 28307#define VM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT 0x0 28308#define VM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK 0x00000001L 28309//VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 28310#define VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT 0xd 28311#define VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK 0x00002000L 28312//VM_PCIE_ATS_CNTL 28313#define VM_PCIE_ATS_CNTL__STU__SHIFT 0x10 28314#define VM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f 28315#define VM_PCIE_ATS_CNTL__STU_MASK 0x001F0000L 28316#define VM_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L 28317//VM_PCIE_ATS_CNTL_VF_0 28318#define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT 0x1f 28319#define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK 0x80000000L 28320//VM_PCIE_ATS_CNTL_VF_1 28321#define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT 0x1f 28322#define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK 0x80000000L 28323//VM_PCIE_ATS_CNTL_VF_2 28324#define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT 0x1f 28325#define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK 0x80000000L 28326//VM_PCIE_ATS_CNTL_VF_3 28327#define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT 0x1f 28328#define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK 0x80000000L 28329//VM_PCIE_ATS_CNTL_VF_4 28330#define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT 0x1f 28331#define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK 0x80000000L 28332//VM_PCIE_ATS_CNTL_VF_5 28333#define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT 0x1f 28334#define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK 0x80000000L 28335//VM_PCIE_ATS_CNTL_VF_6 28336#define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT 0x1f 28337#define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK 0x80000000L 28338//VM_PCIE_ATS_CNTL_VF_7 28339#define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT 0x1f 28340#define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK 0x80000000L 28341//VM_PCIE_ATS_CNTL_VF_8 28342#define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT 0x1f 28343#define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK 0x80000000L 28344//VM_PCIE_ATS_CNTL_VF_9 28345#define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT 0x1f 28346#define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK 0x80000000L 28347//VM_PCIE_ATS_CNTL_VF_10 28348#define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT 0x1f 28349#define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK 0x80000000L 28350//VM_PCIE_ATS_CNTL_VF_11 28351#define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT 0x1f 28352#define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK 0x80000000L 28353//VM_PCIE_ATS_CNTL_VF_12 28354#define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT 0x1f 28355#define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK 0x80000000L 28356//VM_PCIE_ATS_CNTL_VF_13 28357#define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT 0x1f 28358#define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK 0x80000000L 28359//VM_PCIE_ATS_CNTL_VF_14 28360#define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT 0x1f 28361#define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK 0x80000000L 28362//VM_PCIE_ATS_CNTL_VF_15 28363#define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT 0x1f 28364#define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK 0x80000000L 28365//UTCL2_CGTT_CLK_CTRL 28366#define UTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 28367#define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 28368#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA__SHIFT 0xc 28369#define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf 28370#define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 28371#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 28372#define UTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 28373#define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 28374#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA_MASK 0x00007000L 28375#define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L 28376#define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L 28377#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L 28378 28379 28380// addressBlock: gc_hypdec 28381//CP_HYP_PFP_UCODE_ADDR 28382#define CP_HYP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 28383#define CP_HYP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFFL 28384//CP_PFP_UCODE_ADDR 28385#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 28386#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFFL 28387//CP_HYP_PFP_UCODE_DATA 28388#define CP_HYP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0 28389#define CP_HYP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL 28390//CP_PFP_UCODE_DATA 28391#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0 28392#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL 28393//CP_HYP_ME_UCODE_ADDR 28394#define CP_HYP_ME_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 28395#define CP_HYP_ME_UCODE_ADDR__UCODE_ADDR_MASK 0x00001FFFL 28396//CP_ME_RAM_RADDR 28397#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT 0x0 28398#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK 0x00001FFFL 28399//CP_ME_RAM_WADDR 28400#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT 0x0 28401#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK 0x00001FFFL 28402//CP_HYP_ME_UCODE_DATA 28403#define CP_HYP_ME_UCODE_DATA__UCODE_DATA__SHIFT 0x0 28404#define CP_HYP_ME_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL 28405//CP_ME_RAM_DATA 28406#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT 0x0 28407#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK 0xFFFFFFFFL 28408//CP_CE_UCODE_ADDR 28409#define CP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 28410#define CP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0x00000FFFL 28411//CP_HYP_CE_UCODE_ADDR 28412#define CP_HYP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 28413#define CP_HYP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0x00000FFFL 28414//CP_CE_UCODE_DATA 28415#define CP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x0 28416#define CP_CE_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL 28417//CP_HYP_CE_UCODE_DATA 28418#define CP_HYP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x0 28419#define CP_HYP_CE_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL 28420//CP_HYP_MEC1_UCODE_ADDR 28421#define CP_HYP_MEC1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 28422#define CP_HYP_MEC1_UCODE_ADDR__UCODE_ADDR_MASK 0x0001FFFFL 28423//CP_MEC_ME1_UCODE_ADDR 28424#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 28425#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR_MASK 0x0001FFFFL 28426//CP_HYP_MEC1_UCODE_DATA 28427#define CP_HYP_MEC1_UCODE_DATA__UCODE_DATA__SHIFT 0x0 28428#define CP_HYP_MEC1_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL 28429//CP_MEC_ME1_UCODE_DATA 28430#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA__SHIFT 0x0 28431#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL 28432//CP_HYP_MEC2_UCODE_ADDR 28433#define CP_HYP_MEC2_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 28434#define CP_HYP_MEC2_UCODE_ADDR__UCODE_ADDR_MASK 0x0001FFFFL 28435//CP_MEC_ME2_UCODE_ADDR 28436#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 28437#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR_MASK 0x0001FFFFL 28438//CP_HYP_MEC2_UCODE_DATA 28439#define CP_HYP_MEC2_UCODE_DATA__UCODE_DATA__SHIFT 0x0 28440#define CP_HYP_MEC2_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL 28441//CP_MEC_ME2_UCODE_DATA 28442#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA__SHIFT 0x0 28443#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL 28444//RLC_GPM_UCODE_ADDR 28445#define RLC_GPM_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 28446#define RLC_GPM_UCODE_ADDR__RESERVED__SHIFT 0xe 28447#define RLC_GPM_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFFL 28448#define RLC_GPM_UCODE_ADDR__RESERVED_MASK 0xFFFFC000L 28449//RLC_GPM_UCODE_DATA 28450#define RLC_GPM_UCODE_DATA__UCODE_DATA__SHIFT 0x0 28451#define RLC_GPM_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL 28452//GRBM_GFX_INDEX_SR_SELECT 28453#define GRBM_GFX_INDEX_SR_SELECT__INDEX__SHIFT 0x0 28454#define GRBM_GFX_INDEX_SR_SELECT__INDEX_MASK 0x00000007L 28455//GRBM_GFX_INDEX_SR_DATA 28456#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX__SHIFT 0x0 28457#define GRBM_GFX_INDEX_SR_DATA__SH_INDEX__SHIFT 0x8 28458#define GRBM_GFX_INDEX_SR_DATA__SE_INDEX__SHIFT 0x10 28459#define GRBM_GFX_INDEX_SR_DATA__SH_BROADCAST_WRITES__SHIFT 0x1d 28460#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e 28461#define GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES__SHIFT 0x1f 28462#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX_MASK 0x000000FFL 28463#define GRBM_GFX_INDEX_SR_DATA__SH_INDEX_MASK 0x0000FF00L 28464#define GRBM_GFX_INDEX_SR_DATA__SE_INDEX_MASK 0x00FF0000L 28465#define GRBM_GFX_INDEX_SR_DATA__SH_BROADCAST_WRITES_MASK 0x20000000L 28466#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES_MASK 0x40000000L 28467#define GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES_MASK 0x80000000L 28468//GRBM_GFX_CNTL_SR_SELECT 28469#define GRBM_GFX_CNTL_SR_SELECT__INDEX__SHIFT 0x0 28470#define GRBM_GFX_CNTL_SR_SELECT__INDEX_MASK 0x00000007L 28471//GRBM_GFX_CNTL_SR_DATA 28472#define GRBM_GFX_CNTL_SR_DATA__PIPEID__SHIFT 0x0 28473#define GRBM_GFX_CNTL_SR_DATA__MEID__SHIFT 0x2 28474#define GRBM_GFX_CNTL_SR_DATA__VMID__SHIFT 0x4 28475#define GRBM_GFX_CNTL_SR_DATA__QUEUEID__SHIFT 0x8 28476#define GRBM_GFX_CNTL_SR_DATA__PIPEID_MASK 0x00000003L 28477#define GRBM_GFX_CNTL_SR_DATA__MEID_MASK 0x0000000CL 28478#define GRBM_GFX_CNTL_SR_DATA__VMID_MASK 0x000000F0L 28479#define GRBM_GFX_CNTL_SR_DATA__QUEUEID_MASK 0x00000700L 28480//GRBM_CAM_INDEX 28481#define GRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x0 28482#define GRBM_CAM_INDEX__CAM_INDEX_MASK 0x00000007L 28483//GRBM_HYP_CAM_INDEX 28484#define GRBM_HYP_CAM_INDEX__CAM_INDEX__SHIFT 0x0 28485#define GRBM_HYP_CAM_INDEX__CAM_INDEX_MASK 0x00000007L 28486//GRBM_CAM_DATA 28487#define GRBM_CAM_DATA__CAM_ADDR__SHIFT 0x0 28488#define GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10 28489#define GRBM_CAM_DATA__CAM_ADDR_MASK 0x0000FFFFL 28490#define GRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xFFFF0000L 28491//GRBM_HYP_CAM_DATA 28492#define GRBM_HYP_CAM_DATA__CAM_ADDR__SHIFT 0x0 28493#define GRBM_HYP_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10 28494#define GRBM_HYP_CAM_DATA__CAM_ADDR_MASK 0x0000FFFFL 28495#define GRBM_HYP_CAM_DATA__CAM_REMAPADDR_MASK 0xFFFF0000L 28496//RLC_GPU_IOV_VF_ENABLE 28497#define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE__SHIFT 0x0 28498#define RLC_GPU_IOV_VF_ENABLE__RESERVED__SHIFT 0x1 28499#define RLC_GPU_IOV_VF_ENABLE__VF_NUM__SHIFT 0x10 28500#define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE_MASK 0x00000001L 28501#define RLC_GPU_IOV_VF_ENABLE__RESERVED_MASK 0x0000FFFEL 28502#define RLC_GPU_IOV_VF_ENABLE__VF_NUM_MASK 0xFFFF0000L 28503//RLC_GFX_RM_CNTL_ADJ 28504#define RLC_GFX_RM_CNTL_ADJ__RLC_GFX_RM_VALID__SHIFT 0x0 28505#define RLC_GFX_RM_CNTL_ADJ__RESERVED__SHIFT 0x1 28506#define RLC_GFX_RM_CNTL_ADJ__RLC_GFX_RM_VALID_MASK 0x00000001L 28507#define RLC_GFX_RM_CNTL_ADJ__RESERVED_MASK 0xFFFFFFFEL 28508//RLC_GPU_IOV_CFG_REG6 28509#define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE__SHIFT 0x0 28510#define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION__SHIFT 0x7 28511#define RLC_GPU_IOV_CFG_REG6__RESERVED__SHIFT 0x8 28512#define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET__SHIFT 0xa 28513#define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE_MASK 0x0000007FL 28514#define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION_MASK 0x00000080L 28515#define RLC_GPU_IOV_CFG_REG6__RESERVED_MASK 0x00000300L 28516#define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET_MASK 0xFFFFFC00L 28517//RLC_GPU_IOV_CFG_REG8 28518#define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS__SHIFT 0x0 28519#define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS_MASK 0xFFFFFFFFL 28520//RLC_RLCV_TIMER_INT_0 28521#define RLC_RLCV_TIMER_INT_0__TIMER__SHIFT 0x0 28522#define RLC_RLCV_TIMER_INT_0__TIMER_MASK 0xFFFFFFFFL 28523//RLC_RLCV_TIMER_CTRL 28524#define RLC_RLCV_TIMER_CTRL__TIMER_0_EN__SHIFT 0x0 28525#define RLC_RLCV_TIMER_CTRL__RESERVED__SHIFT 0x1 28526#define RLC_RLCV_TIMER_CTRL__TIMER_0_EN_MASK 0x00000001L 28527#define RLC_RLCV_TIMER_CTRL__RESERVED_MASK 0xFFFFFFFEL 28528//RLC_RLCV_TIMER_STAT 28529#define RLC_RLCV_TIMER_STAT__TIMER_0_STAT__SHIFT 0x0 28530#define RLC_RLCV_TIMER_STAT__RESERVED__SHIFT 0x1 28531#define RLC_RLCV_TIMER_STAT__TIMER_0_STAT_MASK 0x00000001L 28532#define RLC_RLCV_TIMER_STAT__RESERVED_MASK 0xFFFFFFFEL 28533//RLC_GPU_IOV_VF_DOORBELL_STATUS 28534#define RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS__SHIFT 0x0 28535#define RLC_GPU_IOV_VF_DOORBELL_STATUS__RESERVED__SHIFT 0x10 28536#define RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS__SHIFT 0x1f 28537#define RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_MASK 0x0000FFFFL 28538#define RLC_GPU_IOV_VF_DOORBELL_STATUS__RESERVED_MASK 0x7FFF0000L 28539#define RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS_MASK 0x80000000L 28540//RLC_GPU_IOV_VF_DOORBELL_STATUS_SET 28541#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET__SHIFT 0x0 28542#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__RESERVED__SHIFT 0x10 28543#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET__SHIFT 0x1f 28544#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET_MASK 0x0000FFFFL 28545#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__RESERVED_MASK 0x7FFF0000L 28546#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET_MASK 0x80000000L 28547//RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR 28548#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR__SHIFT 0x0 28549#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__RESERVED__SHIFT 0x10 28550#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR__SHIFT 0x1f 28551#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR_MASK 0x0000FFFFL 28552#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__RESERVED_MASK 0x7FFF0000L 28553#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR_MASK 0x80000000L 28554//RLC_GPU_IOV_VF_MASK 28555#define RLC_GPU_IOV_VF_MASK__VF_MASK__SHIFT 0x0 28556#define RLC_GPU_IOV_VF_MASK__RESERVED__SHIFT 0x10 28557#define RLC_GPU_IOV_VF_MASK__VF_MASK_MASK 0x0000FFFFL 28558#define RLC_GPU_IOV_VF_MASK__RESERVED_MASK 0xFFFF0000L 28559//RLC_HYP_SEMAPHORE_2 28560#define RLC_HYP_SEMAPHORE_2__CLIENT_ID__SHIFT 0x0 28561#define RLC_HYP_SEMAPHORE_2__RESERVED__SHIFT 0x5 28562#define RLC_HYP_SEMAPHORE_2__CLIENT_ID_MASK 0x0000001FL 28563#define RLC_HYP_SEMAPHORE_2__RESERVED_MASK 0xFFFFFFE0L 28564//RLC_HYP_SEMAPHORE_3 28565#define RLC_HYP_SEMAPHORE_3__CLIENT_ID__SHIFT 0x0 28566#define RLC_HYP_SEMAPHORE_3__RESERVED__SHIFT 0x5 28567#define RLC_HYP_SEMAPHORE_3__CLIENT_ID_MASK 0x0000001FL 28568#define RLC_HYP_SEMAPHORE_3__RESERVED_MASK 0xFFFFFFE0L 28569//RLC_CLK_CNTL 28570#define RLC_CLK_CNTL__RLC_SRM_CLK_CNTL__SHIFT 0x0 28571#define RLC_CLK_CNTL__RLC_SPM_CLK_CNTL__SHIFT 0x1 28572#define RLC_CLK_CNTL__RESERVED__SHIFT 0x2 28573#define RLC_CLK_CNTL__RLC_SRM_CLK_CNTL_MASK 0x00000001L 28574#define RLC_CLK_CNTL__RLC_SPM_CLK_CNTL_MASK 0x00000002L 28575#define RLC_CLK_CNTL__RESERVED_MASK 0xFFFFFFFCL 28576//RLC_GPU_IOV_SCH_BLOCK 28577#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID__SHIFT 0x0 28578#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver__SHIFT 0x4 28579#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size__SHIFT 0x8 28580#define RLC_GPU_IOV_SCH_BLOCK__RESERVED__SHIFT 0x10 28581#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID_MASK 0x0000000FL 28582#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver_MASK 0x000000F0L 28583#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size_MASK 0x00007F00L 28584#define RLC_GPU_IOV_SCH_BLOCK__RESERVED_MASK 0x7FFF0000L 28585//RLC_GPU_IOV_CFG_REG1 28586#define RLC_GPU_IOV_CFG_REG1__CMD_TYPE__SHIFT 0x0 28587#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE__SHIFT 0x4 28588#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN__SHIFT 0x5 28589#define RLC_GPU_IOV_CFG_REG1__RESERVED__SHIFT 0x6 28590#define RLC_GPU_IOV_CFG_REG1__FCN_ID__SHIFT 0x8 28591#define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID__SHIFT 0x10 28592#define RLC_GPU_IOV_CFG_REG1__RESERVED1__SHIFT 0x18 28593#define RLC_GPU_IOV_CFG_REG1__CMD_TYPE_MASK 0x0000000FL 28594#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_MASK 0x00000010L 28595#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN_MASK 0x00000020L 28596#define RLC_GPU_IOV_CFG_REG1__RESERVED_MASK 0x000000C0L 28597#define RLC_GPU_IOV_CFG_REG1__FCN_ID_MASK 0x0000FF00L 28598#define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID_MASK 0x00FF0000L 28599#define RLC_GPU_IOV_CFG_REG1__RESERVED1_MASK 0xFF000000L 28600//RLC_GPU_IOV_CFG_REG2 28601#define RLC_GPU_IOV_CFG_REG2__CMD_STATUS__SHIFT 0x0 28602#define RLC_GPU_IOV_CFG_REG2__RESERVED__SHIFT 0x4 28603#define RLC_GPU_IOV_CFG_REG2__CMD_STATUS_MASK 0x0000000FL 28604#define RLC_GPU_IOV_CFG_REG2__RESERVED_MASK 0xFFFFFFF0L 28605//RLC_GPU_IOV_VM_BUSY_STATUS 28606#define RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 28607#define RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL 28608//RLC_GPU_IOV_SCH_0 28609#define RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS__SHIFT 0x0 28610#define RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS_MASK 0xFFFFFFFFL 28611//RLC_GPU_IOV_ACTIVE_FCN_ID 28612#define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID__SHIFT 0x0 28613#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 28614#define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF__SHIFT 0x1f 28615#define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID_MASK 0x0000000FL 28616#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L 28617#define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF_MASK 0x80000000L 28618//RLC_GPU_IOV_SCH_3 28619#define RLC_GPU_IOV_SCH_3__Time_Quanta_Def__SHIFT 0x0 28620#define RLC_GPU_IOV_SCH_3__Time_Quanta_Def_MASK 0xFFFFFFFFL 28621//RLC_GPU_IOV_SCH_1 28622#define RLC_GPU_IOV_SCH_1__DATA__SHIFT 0x0 28623#define RLC_GPU_IOV_SCH_1__DATA_MASK 0xFFFFFFFFL 28624//RLC_GPU_IOV_SCH_2 28625#define RLC_GPU_IOV_SCH_2__DATA__SHIFT 0x0 28626#define RLC_GPU_IOV_SCH_2__DATA_MASK 0xFFFFFFFFL 28627//RLC_GPU_IOV_UCODE_ADDR 28628#define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 28629#define RLC_GPU_IOV_UCODE_ADDR__RESERVED__SHIFT 0xc 28630#define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR_MASK 0x00000FFFL 28631#define RLC_GPU_IOV_UCODE_ADDR__RESERVED_MASK 0xFFFFF000L 28632//RLC_GPU_IOV_UCODE_DATA 28633#define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA__SHIFT 0x0 28634#define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL 28635//RLC_GPU_IOV_SCRATCH_ADDR 28636#define RLC_GPU_IOV_SCRATCH_ADDR__ADDR__SHIFT 0x0 28637#define RLC_GPU_IOV_SCRATCH_ADDR__RESERVED__SHIFT 0x9 28638#define RLC_GPU_IOV_SCRATCH_ADDR__ADDR_MASK 0x000001FFL 28639#define RLC_GPU_IOV_SCRATCH_ADDR__RESERVED_MASK 0xFFFFFE00L 28640//RLC_GPU_IOV_SCRATCH_DATA 28641#define RLC_GPU_IOV_SCRATCH_DATA__DATA__SHIFT 0x0 28642#define RLC_GPU_IOV_SCRATCH_DATA__DATA_MASK 0xFFFFFFFFL 28643//RLC_GPU_IOV_F32_CNTL 28644#define RLC_GPU_IOV_F32_CNTL__ENABLE__SHIFT 0x0 28645#define RLC_GPU_IOV_F32_CNTL__RESERVED__SHIFT 0x1 28646#define RLC_GPU_IOV_F32_CNTL__ENABLE_MASK 0x00000001L 28647#define RLC_GPU_IOV_F32_CNTL__RESERVED_MASK 0xFFFFFFFEL 28648//RLC_GPU_IOV_F32_RESET 28649#define RLC_GPU_IOV_F32_RESET__RESET__SHIFT 0x0 28650#define RLC_GPU_IOV_F32_RESET__RESERVED__SHIFT 0x1 28651#define RLC_GPU_IOV_F32_RESET__RESET_MASK 0x00000001L 28652#define RLC_GPU_IOV_F32_RESET__RESERVED_MASK 0xFFFFFFFEL 28653//RLC_GPU_IOV_SDMA0_STATUS 28654#define RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED__SHIFT 0x0 28655#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED__SHIFT 0x1 28656#define RLC_GPU_IOV_SDMA0_STATUS__SAVED__SHIFT 0x8 28657#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED1__SHIFT 0x9 28658#define RLC_GPU_IOV_SDMA0_STATUS__RESTORED__SHIFT 0xc 28659#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED2__SHIFT 0xd 28660#define RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED_MASK 0x00000001L 28661#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED_MASK 0x000000FEL 28662#define RLC_GPU_IOV_SDMA0_STATUS__SAVED_MASK 0x00000100L 28663#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED1_MASK 0x00000E00L 28664#define RLC_GPU_IOV_SDMA0_STATUS__RESTORED_MASK 0x00001000L 28665#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED2_MASK 0xFFFFE000L 28666//RLC_GPU_IOV_SDMA1_STATUS 28667#define RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED__SHIFT 0x0 28668#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED__SHIFT 0x1 28669#define RLC_GPU_IOV_SDMA1_STATUS__SAVED__SHIFT 0x8 28670#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED1__SHIFT 0x9 28671#define RLC_GPU_IOV_SDMA1_STATUS__RESTORED__SHIFT 0xc 28672#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED2__SHIFT 0xd 28673#define RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED_MASK 0x00000001L 28674#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED_MASK 0x000000FEL 28675#define RLC_GPU_IOV_SDMA1_STATUS__SAVED_MASK 0x00000100L 28676#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED1_MASK 0x00000E00L 28677#define RLC_GPU_IOV_SDMA1_STATUS__RESTORED_MASK 0x00001000L 28678#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED2_MASK 0xFFFFE000L 28679//RLC_GPU_IOV_SMU_RESPONSE 28680#define RLC_GPU_IOV_SMU_RESPONSE__RESP__SHIFT 0x0 28681#define RLC_GPU_IOV_SMU_RESPONSE__RESP_MASK 0xFFFFFFFFL 28682//RLC_GPU_IOV_VIRT_RESET_REQ 28683#define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR__SHIFT 0x0 28684#define RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED__SHIFT 0x10 28685#define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR__SHIFT 0x1f 28686#define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR_MASK 0x0000FFFFL 28687#define RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED_MASK 0x7FFF0000L 28688#define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR_MASK 0x80000000L 28689//RLC_GPU_IOV_RLC_RESPONSE 28690#define RLC_GPU_IOV_RLC_RESPONSE__RESP__SHIFT 0x0 28691#define RLC_GPU_IOV_RLC_RESPONSE__RESP_MASK 0xFFFFFFFFL 28692//RLC_GPU_IOV_INT_DISABLE 28693#define RLC_GPU_IOV_INT_DISABLE__DISABLE__SHIFT 0x0 28694#define RLC_GPU_IOV_INT_DISABLE__DISABLE_MASK 0xFFFFFFFFL 28695//RLC_GPU_IOV_INT_FORCE 28696#define RLC_GPU_IOV_INT_FORCE__FORCE__SHIFT 0x0 28697#define RLC_GPU_IOV_INT_FORCE__FORCE_MASK 0xFFFFFFFFL 28698//RLC_GPU_IOV_SDMA0_BUSY_STATUS 28699#define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 28700#define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL 28701//RLC_GPU_IOV_SDMA1_BUSY_STATUS 28702#define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 28703#define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL 28704 28705 28706// addressBlock: gccacind 28707//GC_CAC_CNTL 28708#define GC_CAC_CNTL__CAC_ENABLE__SHIFT 0x0 28709#define GC_CAC_CNTL__CAC_THRESHOLD__SHIFT 0x1 28710#define GC_CAC_CNTL__CAC_BLOCK_ID__SHIFT 0x11 28711#define GC_CAC_CNTL__CAC_SIGNAL_ID__SHIFT 0x17 28712#define GC_CAC_CNTL__UNUSED_0__SHIFT 0x1f 28713#define GC_CAC_CNTL__CAC_ENABLE_MASK 0x00000001L 28714#define GC_CAC_CNTL__CAC_THRESHOLD_MASK 0x0001FFFEL 28715#define GC_CAC_CNTL__CAC_BLOCK_ID_MASK 0x007E0000L 28716#define GC_CAC_CNTL__CAC_SIGNAL_ID_MASK 0x7F800000L 28717#define GC_CAC_CNTL__UNUSED_0_MASK 0x80000000L 28718//GC_CAC_OVR_SEL 28719#define GC_CAC_OVR_SEL__CAC_OVR_SEL__SHIFT 0x0 28720#define GC_CAC_OVR_SEL__CAC_OVR_SEL_MASK 0xFFFFFFFFL 28721//GC_CAC_OVR_VAL 28722#define GC_CAC_OVR_VAL__CAC_OVR_VAL__SHIFT 0x0 28723#define GC_CAC_OVR_VAL__CAC_OVR_VAL_MASK 0xFFFFFFFFL 28724//GC_CAC_WEIGHT_BCI_0 28725#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG0__SHIFT 0x0 28726#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG1__SHIFT 0x10 28727#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG0_MASK 0x0000FFFFL 28728#define GC_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG1_MASK 0xFFFF0000L 28729//GC_CAC_WEIGHT_CB_0 28730#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG0__SHIFT 0x0 28731#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG1__SHIFT 0x10 28732#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG0_MASK 0x0000FFFFL 28733#define GC_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG1_MASK 0xFFFF0000L 28734//GC_CAC_WEIGHT_CB_1 28735#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG2__SHIFT 0x0 28736#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG3__SHIFT 0x10 28737#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG2_MASK 0x0000FFFFL 28738#define GC_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG3_MASK 0xFFFF0000L 28739//GC_CAC_WEIGHT_CP_0 28740#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG0__SHIFT 0x0 28741#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG1__SHIFT 0x10 28742#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG0_MASK 0x0000FFFFL 28743#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG1_MASK 0xFFFF0000L 28744//GC_CAC_WEIGHT_CP_1 28745#define GC_CAC_WEIGHT_CP_1__WEIGHT_CP_SIG2__SHIFT 0x0 28746#define GC_CAC_WEIGHT_CP_1__UNUSED_0__SHIFT 0x10 28747#define GC_CAC_WEIGHT_CP_1__WEIGHT_CP_SIG2_MASK 0x0000FFFFL 28748#define GC_CAC_WEIGHT_CP_1__UNUSED_0_MASK 0xFFFF0000L 28749//GC_CAC_WEIGHT_DB_0 28750#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG0__SHIFT 0x0 28751#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG1__SHIFT 0x10 28752#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG0_MASK 0x0000FFFFL 28753#define GC_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG1_MASK 0xFFFF0000L 28754//GC_CAC_WEIGHT_DB_1 28755#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG2__SHIFT 0x0 28756#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG3__SHIFT 0x10 28757#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG2_MASK 0x0000FFFFL 28758#define GC_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG3_MASK 0xFFFF0000L 28759//GC_CAC_WEIGHT_GDS_0 28760#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG0__SHIFT 0x0 28761#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG1__SHIFT 0x10 28762#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG0_MASK 0x0000FFFFL 28763#define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG1_MASK 0xFFFF0000L 28764//GC_CAC_WEIGHT_GDS_1 28765#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG2__SHIFT 0x0 28766#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG3__SHIFT 0x10 28767#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG2_MASK 0x0000FFFFL 28768#define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG3_MASK 0xFFFF0000L 28769//GC_CAC_WEIGHT_IA_0 28770#define GC_CAC_WEIGHT_IA_0__WEIGHT_IA_SIG0__SHIFT 0x0 28771#define GC_CAC_WEIGHT_IA_0__UNUSED_0__SHIFT 0x10 28772#define GC_CAC_WEIGHT_IA_0__WEIGHT_IA_SIG0_MASK 0x0000FFFFL 28773#define GC_CAC_WEIGHT_IA_0__UNUSED_0_MASK 0xFFFF0000L 28774//GC_CAC_WEIGHT_LDS_0 28775#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG0__SHIFT 0x0 28776#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG1__SHIFT 0x10 28777#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG0_MASK 0x0000FFFFL 28778#define GC_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG1_MASK 0xFFFF0000L 28779//GC_CAC_WEIGHT_LDS_1 28780#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG2__SHIFT 0x0 28781#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG3__SHIFT 0x10 28782#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG2_MASK 0x0000FFFFL 28783#define GC_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG3_MASK 0xFFFF0000L 28784//GC_CAC_WEIGHT_PA_0 28785#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG0__SHIFT 0x0 28786#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG1__SHIFT 0x10 28787#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG0_MASK 0x0000FFFFL 28788#define GC_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG1_MASK 0xFFFF0000L 28789//GC_CAC_WEIGHT_PC_0 28790#define GC_CAC_WEIGHT_PC_0__WEIGHT_PC_SIG0__SHIFT 0x0 28791#define GC_CAC_WEIGHT_PC_0__UNUSED_0__SHIFT 0x10 28792#define GC_CAC_WEIGHT_PC_0__WEIGHT_PC_SIG0_MASK 0x0000FFFFL 28793#define GC_CAC_WEIGHT_PC_0__UNUSED_0_MASK 0xFFFF0000L 28794//GC_CAC_WEIGHT_SC_0 28795#define GC_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG0__SHIFT 0x0 28796#define GC_CAC_WEIGHT_SC_0__UNUSED_0__SHIFT 0x10 28797#define GC_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG0_MASK 0x0000FFFFL 28798#define GC_CAC_WEIGHT_SC_0__UNUSED_0_MASK 0xFFFF0000L 28799//GC_CAC_WEIGHT_SPI_0 28800#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG0__SHIFT 0x0 28801#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG1__SHIFT 0x10 28802#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG0_MASK 0x0000FFFFL 28803#define GC_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG1_MASK 0xFFFF0000L 28804//GC_CAC_WEIGHT_SPI_1 28805#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG2__SHIFT 0x0 28806#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG3__SHIFT 0x10 28807#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG2_MASK 0x0000FFFFL 28808#define GC_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG3_MASK 0xFFFF0000L 28809//GC_CAC_WEIGHT_SPI_2 28810#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG4__SHIFT 0x0 28811#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG5__SHIFT 0x10 28812#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG4_MASK 0x0000FFFFL 28813#define GC_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG5_MASK 0xFFFF0000L 28814//GC_CAC_WEIGHT_SQ_0 28815#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG0__SHIFT 0x0 28816#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG1__SHIFT 0x10 28817#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG0_MASK 0x0000FFFFL 28818#define GC_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG1_MASK 0xFFFF0000L 28819//GC_CAC_WEIGHT_SQ_1 28820#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG2__SHIFT 0x0 28821#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG3__SHIFT 0x10 28822#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG2_MASK 0x0000FFFFL 28823#define GC_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG3_MASK 0xFFFF0000L 28824//GC_CAC_WEIGHT_SQ_2 28825#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG4__SHIFT 0x0 28826#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG5__SHIFT 0x10 28827#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG4_MASK 0x0000FFFFL 28828#define GC_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG5_MASK 0xFFFF0000L 28829//GC_CAC_WEIGHT_SQ_3 28830#define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG6__SHIFT 0x0 28831#define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG7__SHIFT 0x10 28832#define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG6_MASK 0x0000FFFFL 28833#define GC_CAC_WEIGHT_SQ_3__WEIGHT_SQ_SIG7_MASK 0xFFFF0000L 28834//GC_CAC_WEIGHT_SQ_4 28835#define GC_CAC_WEIGHT_SQ_4__WEIGHT_SQ_SIG8__SHIFT 0x0 28836#define GC_CAC_WEIGHT_SQ_4__UNUSED_0__SHIFT 0x10 28837#define GC_CAC_WEIGHT_SQ_4__WEIGHT_SQ_SIG8_MASK 0x0000FFFFL 28838#define GC_CAC_WEIGHT_SQ_4__UNUSED_0_MASK 0xFFFF0000L 28839//GC_CAC_WEIGHT_SX_0 28840#define GC_CAC_WEIGHT_SX_0__WEIGHT_SX_SIG0__SHIFT 0x0 28841#define GC_CAC_WEIGHT_SX_0__UNUSED_0__SHIFT 0x10 28842#define GC_CAC_WEIGHT_SX_0__WEIGHT_SX_SIG0_MASK 0x0000FFFFL 28843#define GC_CAC_WEIGHT_SX_0__UNUSED_0_MASK 0xFFFF0000L 28844//GC_CAC_WEIGHT_SXRB_0 28845#define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG0__SHIFT 0x0 28846#define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG1__SHIFT 0x10 28847#define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG0_MASK 0x0000FFFFL 28848#define GC_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG1_MASK 0xFFFF0000L 28849//GC_CAC_WEIGHT_TA_0 28850#define GC_CAC_WEIGHT_TA_0__WEIGHT_TA_SIG0__SHIFT 0x0 28851#define GC_CAC_WEIGHT_TA_0__UNUSED_0__SHIFT 0x10 28852#define GC_CAC_WEIGHT_TA_0__WEIGHT_TA_SIG0_MASK 0x0000FFFFL 28853#define GC_CAC_WEIGHT_TA_0__UNUSED_0_MASK 0xFFFF0000L 28854//GC_CAC_WEIGHT_TCC_0 28855#define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG0__SHIFT 0x0 28856#define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG1__SHIFT 0x10 28857#define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG0_MASK 0x0000FFFFL 28858#define GC_CAC_WEIGHT_TCC_0__WEIGHT_TCC_SIG1_MASK 0xFFFF0000L 28859//GC_CAC_WEIGHT_TCC_1 28860#define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG2__SHIFT 0x0 28861#define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG3__SHIFT 0x10 28862#define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG2_MASK 0x0000FFFFL 28863#define GC_CAC_WEIGHT_TCC_1__WEIGHT_TCC_SIG3_MASK 0xFFFF0000L 28864//GC_CAC_WEIGHT_TCC_2 28865#define GC_CAC_WEIGHT_TCC_2__WEIGHT_TCC_SIG4__SHIFT 0x0 28866#define GC_CAC_WEIGHT_TCC_2__UNUSED_0__SHIFT 0x10 28867#define GC_CAC_WEIGHT_TCC_2__WEIGHT_TCC_SIG4_MASK 0x0000FFFFL 28868#define GC_CAC_WEIGHT_TCC_2__UNUSED_0_MASK 0xFFFF0000L 28869//GC_CAC_WEIGHT_TCP_0 28870#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG0__SHIFT 0x0 28871#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG1__SHIFT 0x10 28872#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG0_MASK 0x0000FFFFL 28873#define GC_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG1_MASK 0xFFFF0000L 28874//GC_CAC_WEIGHT_TCP_1 28875#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG2__SHIFT 0x0 28876#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG3__SHIFT 0x10 28877#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG2_MASK 0x0000FFFFL 28878#define GC_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG3_MASK 0xFFFF0000L 28879//GC_CAC_WEIGHT_TCP_2 28880#define GC_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG4__SHIFT 0x0 28881#define GC_CAC_WEIGHT_TCP_2__UNUSED_0__SHIFT 0x10 28882#define GC_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG4_MASK 0x0000FFFFL 28883#define GC_CAC_WEIGHT_TCP_2__UNUSED_0_MASK 0xFFFF0000L 28884//GC_CAC_WEIGHT_TD_0 28885#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG0__SHIFT 0x0 28886#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG1__SHIFT 0x10 28887#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG0_MASK 0x0000FFFFL 28888#define GC_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG1_MASK 0xFFFF0000L 28889//GC_CAC_WEIGHT_TD_1 28890#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG2__SHIFT 0x0 28891#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG3__SHIFT 0x10 28892#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG2_MASK 0x0000FFFFL 28893#define GC_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG3_MASK 0xFFFF0000L 28894//GC_CAC_WEIGHT_TD_2 28895#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG4__SHIFT 0x0 28896#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG5__SHIFT 0x10 28897#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG4_MASK 0x0000FFFFL 28898#define GC_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG5_MASK 0xFFFF0000L 28899//GC_CAC_WEIGHT_VGT_0 28900#define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG0__SHIFT 0x0 28901#define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG1__SHIFT 0x10 28902#define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG0_MASK 0x0000FFFFL 28903#define GC_CAC_WEIGHT_VGT_0__WEIGHT_VGT_SIG1_MASK 0xFFFF0000L 28904//GC_CAC_WEIGHT_VGT_1 28905#define GC_CAC_WEIGHT_VGT_1__WEIGHT_VGT_SIG2__SHIFT 0x0 28906#define GC_CAC_WEIGHT_VGT_1__UNUSED_0__SHIFT 0x10 28907#define GC_CAC_WEIGHT_VGT_1__WEIGHT_VGT_SIG2_MASK 0x0000FFFFL 28908#define GC_CAC_WEIGHT_VGT_1__UNUSED_0_MASK 0xFFFF0000L 28909//GC_CAC_WEIGHT_WD_0 28910#define GC_CAC_WEIGHT_WD_0__WEIGHT_WD_SIG0__SHIFT 0x0 28911#define GC_CAC_WEIGHT_WD_0__UNUSED_0__SHIFT 0x10 28912#define GC_CAC_WEIGHT_WD_0__WEIGHT_WD_SIG0_MASK 0x0000FFFFL 28913#define GC_CAC_WEIGHT_WD_0__UNUSED_0_MASK 0xFFFF0000L 28914//GC_CAC_WEIGHT_CU_0 28915#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0__SHIFT 0x0 28916#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG1__SHIFT 0x10 28917#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0_MASK 0x0000FFFFL 28918#define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG1_MASK 0xFFFF0000L 28919//GC_CAC_WEIGHT_CU_1 28920#define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG2__SHIFT 0x0 28921#define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG3__SHIFT 0x10 28922#define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG2_MASK 0x0000FFFFL 28923#define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG3_MASK 0xFFFF0000L 28924//GC_CAC_WEIGHT_CU_2 28925#define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG4__SHIFT 0x0 28926#define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG5__SHIFT 0x10 28927#define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG4_MASK 0x0000FFFFL 28928#define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG5_MASK 0xFFFF0000L 28929//GC_CAC_WEIGHT_CU_3 28930#define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG6__SHIFT 0x0 28931#define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG7__SHIFT 0x10 28932#define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG6_MASK 0x0000FFFFL 28933#define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG7_MASK 0xFFFF0000L 28934//GC_CAC_WEIGHT_CU_4 28935#define GC_CAC_WEIGHT_CU_4__WEIGHT_CU_SIG8__SHIFT 0x0 28936#define GC_CAC_WEIGHT_CU_4__WEIGHT_CU_SIG9__SHIFT 0x10 28937#define GC_CAC_WEIGHT_CU_4__WEIGHT_CU_SIG8_MASK 0x0000FFFFL 28938#define GC_CAC_WEIGHT_CU_4__WEIGHT_CU_SIG9_MASK 0xFFFF0000L 28939//GC_CAC_WEIGHT_CU_5 28940#define GC_CAC_WEIGHT_CU_5__WEIGHT_CU_SIG10__SHIFT 0x0 28941#define GC_CAC_WEIGHT_CU_5__WEIGHT_CU_SIG11__SHIFT 0x10 28942#define GC_CAC_WEIGHT_CU_5__WEIGHT_CU_SIG10_MASK 0x0000FFFFL 28943#define GC_CAC_WEIGHT_CU_5__WEIGHT_CU_SIG11_MASK 0xFFFF0000L 28944//GC_CAC_ACC_BCI0 28945#define GC_CAC_ACC_BCI0__ACCUMULATOR_31_0__SHIFT 0x0 28946#define GC_CAC_ACC_BCI0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 28947//GC_CAC_ACC_CB0 28948#define GC_CAC_ACC_CB0__ACCUMULATOR_31_0__SHIFT 0x0 28949#define GC_CAC_ACC_CB0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 28950//GC_CAC_ACC_CB1 28951#define GC_CAC_ACC_CB1__ACCUMULATOR_31_0__SHIFT 0x0 28952#define GC_CAC_ACC_CB1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 28953//GC_CAC_ACC_CB2 28954#define GC_CAC_ACC_CB2__ACCUMULATOR_31_0__SHIFT 0x0 28955#define GC_CAC_ACC_CB2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 28956//GC_CAC_ACC_CB3 28957#define GC_CAC_ACC_CB3__ACCUMULATOR_31_0__SHIFT 0x0 28958#define GC_CAC_ACC_CB3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 28959//GC_CAC_ACC_CP0 28960#define GC_CAC_ACC_CP0__ACCUMULATOR_31_0__SHIFT 0x0 28961#define GC_CAC_ACC_CP0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 28962//GC_CAC_ACC_CP1 28963#define GC_CAC_ACC_CP1__ACCUMULATOR_31_0__SHIFT 0x0 28964#define GC_CAC_ACC_CP1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 28965//GC_CAC_ACC_CP2 28966#define GC_CAC_ACC_CP2__ACCUMULATOR_31_0__SHIFT 0x0 28967#define GC_CAC_ACC_CP2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 28968//GC_CAC_ACC_DB0 28969#define GC_CAC_ACC_DB0__ACCUMULATOR_31_0__SHIFT 0x0 28970#define GC_CAC_ACC_DB0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 28971//GC_CAC_ACC_DB1 28972#define GC_CAC_ACC_DB1__ACCUMULATOR_31_0__SHIFT 0x0 28973#define GC_CAC_ACC_DB1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 28974//GC_CAC_ACC_DB2 28975#define GC_CAC_ACC_DB2__ACCUMULATOR_31_0__SHIFT 0x0 28976#define GC_CAC_ACC_DB2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 28977//GC_CAC_ACC_DB3 28978#define GC_CAC_ACC_DB3__ACCUMULATOR_31_0__SHIFT 0x0 28979#define GC_CAC_ACC_DB3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 28980//GC_CAC_ACC_GDS0 28981#define GC_CAC_ACC_GDS0__ACCUMULATOR_31_0__SHIFT 0x0 28982#define GC_CAC_ACC_GDS0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 28983//GC_CAC_ACC_GDS1 28984#define GC_CAC_ACC_GDS1__ACCUMULATOR_31_0__SHIFT 0x0 28985#define GC_CAC_ACC_GDS1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 28986//GC_CAC_ACC_GDS2 28987#define GC_CAC_ACC_GDS2__ACCUMULATOR_31_0__SHIFT 0x0 28988#define GC_CAC_ACC_GDS2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 28989//GC_CAC_ACC_GDS3 28990#define GC_CAC_ACC_GDS3__ACCUMULATOR_31_0__SHIFT 0x0 28991#define GC_CAC_ACC_GDS3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 28992//GC_CAC_ACC_IA0 28993#define GC_CAC_ACC_IA0__ACCUMULATOR_31_0__SHIFT 0x0 28994#define GC_CAC_ACC_IA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 28995//GC_CAC_ACC_LDS0 28996#define GC_CAC_ACC_LDS0__ACCUMULATOR_31_0__SHIFT 0x0 28997#define GC_CAC_ACC_LDS0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 28998//GC_CAC_ACC_LDS1 28999#define GC_CAC_ACC_LDS1__ACCUMULATOR_31_0__SHIFT 0x0 29000#define GC_CAC_ACC_LDS1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL
29001//GC_CAC_ACC_LDS2 29002#define GC_CAC_ACC_LDS2__ACCUMULATOR_31_0__SHIFT 0x0 29003#define GC_CAC_ACC_LDS2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29004//GC_CAC_ACC_LDS3 29005#define GC_CAC_ACC_LDS3__ACCUMULATOR_31_0__SHIFT 0x0 29006#define GC_CAC_ACC_LDS3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29007//GC_CAC_ACC_PA0 29008#define GC_CAC_ACC_PA0__ACCUMULATOR_31_0__SHIFT 0x0 29009#define GC_CAC_ACC_PA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29010//GC_CAC_ACC_PA1 29011#define GC_CAC_ACC_PA1__ACCUMULATOR_31_0__SHIFT 0x0 29012#define GC_CAC_ACC_PA1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29013//GC_CAC_ACC_PC0 29014#define GC_CAC_ACC_PC0__ACCUMULATOR_31_0__SHIFT 0x0 29015#define GC_CAC_ACC_PC0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29016//GC_CAC_ACC_SC0 29017#define GC_CAC_ACC_SC0__ACCUMULATOR_31_0__SHIFT 0x0 29018#define GC_CAC_ACC_SC0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29019//GC_CAC_ACC_SPI0 29020#define GC_CAC_ACC_SPI0__ACCUMULATOR_31_0__SHIFT 0x0 29021#define GC_CAC_ACC_SPI0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29022//GC_CAC_ACC_SPI1 29023#define GC_CAC_ACC_SPI1__ACCUMULATOR_31_0__SHIFT 0x0 29024#define GC_CAC_ACC_SPI1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29025//GC_CAC_ACC_SPI2 29026#define GC_CAC_ACC_SPI2__ACCUMULATOR_31_0__SHIFT 0x0 29027#define GC_CAC_ACC_SPI2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29028//GC_CAC_ACC_SPI3 29029#define GC_CAC_ACC_SPI3__ACCUMULATOR_31_0__SHIFT 0x0 29030#define GC_CAC_ACC_SPI3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29031//GC_CAC_ACC_SPI4 29032#define GC_CAC_ACC_SPI4__ACCUMULATOR_31_0__SHIFT 0x0 29033#define GC_CAC_ACC_SPI4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29034//GC_CAC_ACC_SPI5 29035#define GC_CAC_ACC_SPI5__ACCUMULATOR_31_0__SHIFT 0x0 29036#define GC_CAC_ACC_SPI5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29037//GC_CAC_WEIGHT_PG_0 29038#define GC_CAC_WEIGHT_PG_0__WEIGHT_PG_SIG0__SHIFT 0x0 29039#define GC_CAC_WEIGHT_PG_0__unused__SHIFT 0x10 29040#define GC_CAC_WEIGHT_PG_0__WEIGHT_PG_SIG0_MASK 0x0000FFFFL 29041#define GC_CAC_WEIGHT_PG_0__unused_MASK 0xFFFF0000L 29042//GC_CAC_ACC_PG0 29043#define GC_CAC_ACC_PG0__ACCUMULATOR_31_0__SHIFT 0x0 29044#define GC_CAC_ACC_PG0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29045//GC_CAC_OVRD_PG 29046#define GC_CAC_OVRD_PG__OVRRD_SELECT__SHIFT 0x0 29047#define GC_CAC_OVRD_PG__OVRRD_VALUE__SHIFT 0x10 29048#define GC_CAC_OVRD_PG__OVRRD_SELECT_MASK 0x0000FFFFL 29049#define GC_CAC_OVRD_PG__OVRRD_VALUE_MASK 0xFFFF0000L 29050//GC_CAC_WEIGHT_UTCL2_ATCL2_0 29051#define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG0__SHIFT 0x0 29052#define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG1__SHIFT 0x10 29053#define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG0_MASK 0x0000FFFFL 29054#define GC_CAC_WEIGHT_UTCL2_ATCL2_0__WEIGHT_UTCL2_ATCL2_SIG1_MASK 0xFFFF0000L 29055//GC_CAC_ACC_EA0 29056#define GC_CAC_ACC_EA0__ACCUMULATOR_31_0__SHIFT 0x0 29057#define GC_CAC_ACC_EA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29058//GC_CAC_ACC_EA1 29059#define GC_CAC_ACC_EA1__ACCUMULATOR_31_0__SHIFT 0x0 29060#define GC_CAC_ACC_EA1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29061//GC_CAC_ACC_EA2 29062#define GC_CAC_ACC_EA2__ACCUMULATOR_31_0__SHIFT 0x0 29063#define GC_CAC_ACC_EA2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29064//GC_CAC_ACC_EA3 29065#define GC_CAC_ACC_EA3__ACCUMULATOR_31_0__SHIFT 0x0 29066#define GC_CAC_ACC_EA3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29067//GC_CAC_ACC_UTCL2_ATCL20 29068#define GC_CAC_ACC_UTCL2_ATCL20__ACCUMULATOR_31_0__SHIFT 0x0 29069#define GC_CAC_ACC_UTCL2_ATCL20__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29070//GC_CAC_OVRD_EA 29071#define GC_CAC_OVRD_EA__OVRRD_SELECT__SHIFT 0x0 29072#define GC_CAC_OVRD_EA__OVRRD_VALUE__SHIFT 0x6 29073#define GC_CAC_OVRD_EA__OVRRD_SELECT_MASK 0x0000003FL 29074#define GC_CAC_OVRD_EA__OVRRD_VALUE_MASK 0x00000FC0L 29075//GC_CAC_OVRD_UTCL2_ATCL2 29076#define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_SELECT__SHIFT 0x0 29077#define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_VALUE__SHIFT 0x5 29078#define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_SELECT_MASK 0x0000001FL 29079#define GC_CAC_OVRD_UTCL2_ATCL2__OVRRD_VALUE_MASK 0x000003E0L 29080//GC_CAC_WEIGHT_EA_0 29081#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG0__SHIFT 0x0 29082#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG1__SHIFT 0x10 29083#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG0_MASK 0x0000FFFFL 29084#define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG1_MASK 0xFFFF0000L 29085//GC_CAC_WEIGHT_EA_1 29086#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG2__SHIFT 0x0 29087#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG3__SHIFT 0x10 29088#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG2_MASK 0x0000FFFFL 29089#define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG3_MASK 0xFFFF0000L 29090//GC_CAC_WEIGHT_RMI_0 29091#define GC_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG0__SHIFT 0x0 29092#define GC_CAC_WEIGHT_RMI_0__UNUSED__SHIFT 0x10 29093#define GC_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG0_MASK 0x0000FFFFL 29094#define GC_CAC_WEIGHT_RMI_0__UNUSED_MASK 0xFFFF0000L 29095//GC_CAC_ACC_RMI0 29096#define GC_CAC_ACC_RMI0__ACCUMULATOR_31_0__SHIFT 0x0 29097#define GC_CAC_ACC_RMI0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29098//GC_CAC_OVRD_RMI 29099#define GC_CAC_OVRD_RMI__OVRRD_SELECT__SHIFT 0x0 29100#define GC_CAC_OVRD_RMI__OVRRD_VALUE__SHIFT 0x1 29101#define GC_CAC_OVRD_RMI__OVRRD_SELECT_MASK 0x00000001L 29102#define GC_CAC_OVRD_RMI__OVRRD_VALUE_MASK 0x00000002L 29103//GC_CAC_WEIGHT_UTCL2_ATCL2_1 29104#define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG2__SHIFT 0x0 29105#define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG3__SHIFT 0x10 29106#define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG2_MASK 0x0000FFFFL 29107#define GC_CAC_WEIGHT_UTCL2_ATCL2_1__WEIGHT_UTCL2_ATCL2_SIG3_MASK 0xFFFF0000L 29108//GC_CAC_ACC_UTCL2_ATCL21 29109#define GC_CAC_ACC_UTCL2_ATCL21__ACCUMULATOR_31_0__SHIFT 0x0 29110#define GC_CAC_ACC_UTCL2_ATCL21__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29111//GC_CAC_ACC_UTCL2_ATCL22 29112#define GC_CAC_ACC_UTCL2_ATCL22__ACCUMULATOR_31_0__SHIFT 0x0 29113#define GC_CAC_ACC_UTCL2_ATCL22__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29114//GC_CAC_ACC_UTCL2_ATCL23 29115#define GC_CAC_ACC_UTCL2_ATCL23__ACCUMULATOR_31_0__SHIFT 0x0 29116#define GC_CAC_ACC_UTCL2_ATCL23__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29117//GC_CAC_ACC_EA4 29118#define GC_CAC_ACC_EA4__ACCUMULATOR_31_0__SHIFT 0x0 29119#define GC_CAC_ACC_EA4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29120//GC_CAC_ACC_EA5 29121#define GC_CAC_ACC_EA5__ACCUMULATOR_31_0__SHIFT 0x0 29122#define GC_CAC_ACC_EA5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29123//GC_CAC_WEIGHT_EA_2 29124#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG4__SHIFT 0x0 29125#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG5__SHIFT 0x10 29126#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG4_MASK 0x0000FFFFL 29127#define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG5_MASK 0xFFFF0000L 29128//GC_CAC_ACC_SQ0_LOWER 29129#define GC_CAC_ACC_SQ0_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 29130#define GC_CAC_ACC_SQ0_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29131//GC_CAC_ACC_SQ0_UPPER 29132#define GC_CAC_ACC_SQ0_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 29133#define GC_CAC_ACC_SQ0_UPPER__UNUSED_0__SHIFT 0x8 29134#define GC_CAC_ACC_SQ0_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL 29135#define GC_CAC_ACC_SQ0_UPPER__UNUSED_0_MASK 0xFFFFFF00L 29136//GC_CAC_ACC_SQ1_LOWER 29137#define GC_CAC_ACC_SQ1_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 29138#define GC_CAC_ACC_SQ1_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29139//GC_CAC_ACC_SQ1_UPPER 29140#define GC_CAC_ACC_SQ1_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 29141#define GC_CAC_ACC_SQ1_UPPER__UNUSED_0__SHIFT 0x8 29142#define GC_CAC_ACC_SQ1_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL 29143#define GC_CAC_ACC_SQ1_UPPER__UNUSED_0_MASK 0xFFFFFF00L 29144//GC_CAC_ACC_SQ2_LOWER 29145#define GC_CAC_ACC_SQ2_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 29146#define GC_CAC_ACC_SQ2_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29147//GC_CAC_ACC_SQ2_UPPER 29148#define GC_CAC_ACC_SQ2_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 29149#define GC_CAC_ACC_SQ2_UPPER__UNUSED_0__SHIFT 0x8 29150#define GC_CAC_ACC_SQ2_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL 29151#define GC_CAC_ACC_SQ2_UPPER__UNUSED_0_MASK 0xFFFFFF00L 29152//GC_CAC_ACC_SQ3_LOWER 29153#define GC_CAC_ACC_SQ3_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 29154#define GC_CAC_ACC_SQ3_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29155//GC_CAC_ACC_SQ3_UPPER 29156#define GC_CAC_ACC_SQ3_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 29157#define GC_CAC_ACC_SQ3_UPPER__UNUSED_0__SHIFT 0x8 29158#define GC_CAC_ACC_SQ3_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL 29159#define GC_CAC_ACC_SQ3_UPPER__UNUSED_0_MASK 0xFFFFFF00L 29160//GC_CAC_ACC_SQ4_LOWER 29161#define GC_CAC_ACC_SQ4_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 29162#define GC_CAC_ACC_SQ4_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29163//GC_CAC_ACC_SQ4_UPPER 29164#define GC_CAC_ACC_SQ4_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 29165#define GC_CAC_ACC_SQ4_UPPER__UNUSED_0__SHIFT 0x8 29166#define GC_CAC_ACC_SQ4_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL 29167#define GC_CAC_ACC_SQ4_UPPER__UNUSED_0_MASK 0xFFFFFF00L 29168//GC_CAC_ACC_SQ5_LOWER 29169#define GC_CAC_ACC_SQ5_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 29170#define GC_CAC_ACC_SQ5_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29171//GC_CAC_ACC_SQ5_UPPER 29172#define GC_CAC_ACC_SQ5_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 29173#define GC_CAC_ACC_SQ5_UPPER__UNUSED_0__SHIFT 0x8 29174#define GC_CAC_ACC_SQ5_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL 29175#define GC_CAC_ACC_SQ5_UPPER__UNUSED_0_MASK 0xFFFFFF00L 29176//GC_CAC_ACC_SQ6_LOWER 29177#define GC_CAC_ACC_SQ6_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 29178#define GC_CAC_ACC_SQ6_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29179//GC_CAC_ACC_SQ6_UPPER 29180#define GC_CAC_ACC_SQ6_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 29181#define GC_CAC_ACC_SQ6_UPPER__UNUSED_0__SHIFT 0x8 29182#define GC_CAC_ACC_SQ6_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL 29183#define GC_CAC_ACC_SQ6_UPPER__UNUSED_0_MASK 0xFFFFFF00L 29184//GC_CAC_ACC_SQ7_LOWER 29185#define GC_CAC_ACC_SQ7_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 29186#define GC_CAC_ACC_SQ7_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29187//GC_CAC_ACC_SQ7_UPPER 29188#define GC_CAC_ACC_SQ7_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 29189#define GC_CAC_ACC_SQ7_UPPER__UNUSED_0__SHIFT 0x8 29190#define GC_CAC_ACC_SQ7_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL 29191#define GC_CAC_ACC_SQ7_UPPER__UNUSED_0_MASK 0xFFFFFF00L 29192//GC_CAC_ACC_SQ8_LOWER 29193#define GC_CAC_ACC_SQ8_LOWER__ACCUMULATOR_31_0__SHIFT 0x0 29194#define GC_CAC_ACC_SQ8_LOWER__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29195//GC_CAC_ACC_SQ8_UPPER 29196#define GC_CAC_ACC_SQ8_UPPER__ACCUMULATOR_39_32__SHIFT 0x0 29197#define GC_CAC_ACC_SQ8_UPPER__UNUSED_0__SHIFT 0x8 29198#define GC_CAC_ACC_SQ8_UPPER__ACCUMULATOR_39_32_MASK 0x000000FFL 29199#define GC_CAC_ACC_SQ8_UPPER__UNUSED_0_MASK 0xFFFFFF00L 29200//GC_CAC_ACC_SX0 29201#define GC_CAC_ACC_SX0__ACCUMULATOR_31_0__SHIFT 0x0 29202#define GC_CAC_ACC_SX0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29203//GC_CAC_ACC_SXRB0 29204#define GC_CAC_ACC_SXRB0__ACCUMULATOR_31_0__SHIFT 0x0 29205#define GC_CAC_ACC_SXRB0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29206//GC_CAC_ACC_SXRB1 29207#define GC_CAC_ACC_SXRB1__ACCUMULATOR_31_0__SHIFT 0x0 29208#define GC_CAC_ACC_SXRB1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29209//GC_CAC_ACC_TA0 29210#define GC_CAC_ACC_TA0__ACCUMULATOR_31_0__SHIFT 0x0 29211#define GC_CAC_ACC_TA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29212//GC_CAC_ACC_TCC0 29213#define GC_CAC_ACC_TCC0__ACCUMULATOR_31_0__SHIFT 0x0 29214#define GC_CAC_ACC_TCC0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29215//GC_CAC_ACC_TCC1 29216#define GC_CAC_ACC_TCC1__ACCUMULATOR_31_0__SHIFT 0x0 29217#define GC_CAC_ACC_TCC1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29218//GC_CAC_ACC_TCC2 29219#define GC_CAC_ACC_TCC2__ACCUMULATOR_31_0__SHIFT 0x0 29220#define GC_CAC_ACC_TCC2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29221//GC_CAC_ACC_TCC3 29222#define GC_CAC_ACC_TCC3__ACCUMULATOR_31_0__SHIFT 0x0 29223#define GC_CAC_ACC_TCC3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29224//GC_CAC_ACC_TCC4 29225#define GC_CAC_ACC_TCC4__ACCUMULATOR_31_0__SHIFT 0x0 29226#define GC_CAC_ACC_TCC4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29227//GC_CAC_ACC_TCP0 29228#define GC_CAC_ACC_TCP0__ACCUMULATOR_31_0__SHIFT 0x0 29229#define GC_CAC_ACC_TCP0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29230//GC_CAC_ACC_TCP1 29231#define GC_CAC_ACC_TCP1__ACCUMULATOR_31_0__SHIFT 0x0 29232#define GC_CAC_ACC_TCP1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29233//GC_CAC_ACC_TCP2 29234#define GC_CAC_ACC_TCP2__ACCUMULATOR_31_0__SHIFT 0x0 29235#define GC_CAC_ACC_TCP2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29236//GC_CAC_ACC_TCP3 29237#define GC_CAC_ACC_TCP3__ACCUMULATOR_31_0__SHIFT 0x0 29238#define GC_CAC_ACC_TCP3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29239//GC_CAC_ACC_TCP4 29240#define GC_CAC_ACC_TCP4__ACCUMULATOR_31_0__SHIFT 0x0 29241#define GC_CAC_ACC_TCP4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29242//GC_CAC_ACC_TD0 29243#define GC_CAC_ACC_TD0__ACCUMULATOR_31_0__SHIFT 0x0 29244#define GC_CAC_ACC_TD0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29245//GC_CAC_ACC_TD1 29246#define GC_CAC_ACC_TD1__ACCUMULATOR_31_0__SHIFT 0x0 29247#define GC_CAC_ACC_TD1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29248//GC_CAC_ACC_TD2 29249#define GC_CAC_ACC_TD2__ACCUMULATOR_31_0__SHIFT 0x0 29250#define GC_CAC_ACC_TD2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29251//GC_CAC_ACC_TD3 29252#define GC_CAC_ACC_TD3__ACCUMULATOR_31_0__SHIFT 0x0 29253#define GC_CAC_ACC_TD3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29254//GC_CAC_ACC_TD4 29255#define GC_CAC_ACC_TD4__ACCUMULATOR_31_0__SHIFT 0x0 29256#define GC_CAC_ACC_TD4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29257//GC_CAC_ACC_TD5 29258#define GC_CAC_ACC_TD5__ACCUMULATOR_31_0__SHIFT 0x0 29259#define GC_CAC_ACC_TD5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29260//GC_CAC_ACC_VGT0 29261#define GC_CAC_ACC_VGT0__ACCUMULATOR_31_0__SHIFT 0x0 29262#define GC_CAC_ACC_VGT0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29263//GC_CAC_ACC_VGT1 29264#define GC_CAC_ACC_VGT1__ACCUMULATOR_31_0__SHIFT 0x0 29265#define GC_CAC_ACC_VGT1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29266//GC_CAC_ACC_VGT2 29267#define GC_CAC_ACC_VGT2__ACCUMULATOR_31_0__SHIFT 0x0 29268#define GC_CAC_ACC_VGT2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29269//GC_CAC_ACC_WD0 29270#define GC_CAC_ACC_WD0__ACCUMULATOR_31_0__SHIFT 0x0 29271#define GC_CAC_ACC_WD0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29272//GC_CAC_ACC_CU0 29273#define GC_CAC_ACC_CU0__ACCUMULATOR_31_0__SHIFT 0x0 29274#define GC_CAC_ACC_CU0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29275//GC_CAC_ACC_CU1 29276#define GC_CAC_ACC_CU1__ACCUMULATOR_31_0__SHIFT 0x0 29277#define GC_CAC_ACC_CU1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29278//GC_CAC_ACC_CU2 29279#define GC_CAC_ACC_CU2__ACCUMULATOR_31_0__SHIFT 0x0 29280#define GC_CAC_ACC_CU2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29281//GC_CAC_ACC_CU3 29282#define GC_CAC_ACC_CU3__ACCUMULATOR_31_0__SHIFT 0x0 29283#define GC_CAC_ACC_CU3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29284//GC_CAC_ACC_CU4 29285#define GC_CAC_ACC_CU4__ACCUMULATOR_31_0__SHIFT 0x0 29286#define GC_CAC_ACC_CU4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29287//GC_CAC_ACC_CU5 29288#define GC_CAC_ACC_CU5__ACCUMULATOR_31_0__SHIFT 0x0 29289#define GC_CAC_ACC_CU5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29290//GC_CAC_ACC_CU6 29291#define GC_CAC_ACC_CU6__ACCUMULATOR_31_0__SHIFT 0x0 29292#define GC_CAC_ACC_CU6__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29293//GC_CAC_ACC_CU7 29294#define GC_CAC_ACC_CU7__ACCUMULATOR_31_0__SHIFT 0x0 29295#define GC_CAC_ACC_CU7__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29296//GC_CAC_ACC_CU8 29297#define GC_CAC_ACC_CU8__ACCUMULATOR_31_0__SHIFT 0x0 29298#define GC_CAC_ACC_CU8__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29299//GC_CAC_ACC_CU9 29300#define GC_CAC_ACC_CU9__ACCUMULATOR_31_0__SHIFT 0x0 29301#define GC_CAC_ACC_CU9__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29302//GC_CAC_ACC_CU10 29303#define GC_CAC_ACC_CU10__ACCUMULATOR_31_0__SHIFT 0x0 29304#define GC_CAC_ACC_CU10__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29305//GC_CAC_OVRD_BCI 29306#define GC_CAC_OVRD_BCI__OVRRD_SELECT__SHIFT 0x0 29307#define GC_CAC_OVRD_BCI__OVRRD_VALUE__SHIFT 0x2 29308#define GC_CAC_OVRD_BCI__OVRRD_SELECT_MASK 0x00000003L 29309#define GC_CAC_OVRD_BCI__OVRRD_VALUE_MASK 0x0000000CL 29310//GC_CAC_OVRD_CB 29311#define GC_CAC_OVRD_CB__OVRRD_SELECT__SHIFT 0x0 29312#define GC_CAC_OVRD_CB__OVRRD_VALUE__SHIFT 0x4 29313#define GC_CAC_OVRD_CB__OVRRD_SELECT_MASK 0x0000000FL 29314#define GC_CAC_OVRD_CB__OVRRD_VALUE_MASK 0x000000F0L 29315//GC_CAC_OVRD_CP 29316#define GC_CAC_OVRD_CP__OVRRD_SELECT__SHIFT 0x0 29317#define GC_CAC_OVRD_CP__OVRRD_VALUE__SHIFT 0x3 29318#define GC_CAC_OVRD_CP__OVRRD_SELECT_MASK 0x00000007L 29319#define GC_CAC_OVRD_CP__OVRRD_VALUE_MASK 0x00000038L 29320//GC_CAC_OVRD_DB 29321#define GC_CAC_OVRD_DB__OVRRD_SELECT__SHIFT 0x0 29322#define GC_CAC_OVRD_DB__OVRRD_VALUE__SHIFT 0x4 29323#define GC_CAC_OVRD_DB__OVRRD_SELECT_MASK 0x0000000FL 29324#define GC_CAC_OVRD_DB__OVRRD_VALUE_MASK 0x000000F0L 29325//GC_CAC_OVRD_GDS 29326#define GC_CAC_OVRD_GDS__OVRRD_SELECT__SHIFT 0x0 29327#define GC_CAC_OVRD_GDS__OVRRD_VALUE__SHIFT 0x4 29328#define GC_CAC_OVRD_GDS__OVRRD_SELECT_MASK 0x0000000FL 29329#define GC_CAC_OVRD_GDS__OVRRD_VALUE_MASK 0x000000F0L 29330//GC_CAC_OVRD_IA 29331#define GC_CAC_OVRD_IA__OVRRD_SELECT__SHIFT 0x0 29332#define GC_CAC_OVRD_IA__OVRRD_VALUE__SHIFT 0x1 29333#define GC_CAC_OVRD_IA__OVRRD_SELECT_MASK 0x00000001L 29334#define GC_CAC_OVRD_IA__OVRRD_VALUE_MASK 0x00000002L 29335//GC_CAC_OVRD_LDS 29336#define GC_CAC_OVRD_LDS__OVRRD_SELECT__SHIFT 0x0 29337#define GC_CAC_OVRD_LDS__OVRRD_VALUE__SHIFT 0x4 29338#define GC_CAC_OVRD_LDS__OVRRD_SELECT_MASK 0x0000000FL 29339#define GC_CAC_OVRD_LDS__OVRRD_VALUE_MASK 0x000000F0L 29340//GC_CAC_OVRD_PA 29341#define GC_CAC_OVRD_PA__OVRRD_SELECT__SHIFT 0x0 29342#define GC_CAC_OVRD_PA__OVRRD_VALUE__SHIFT 0x2 29343#define GC_CAC_OVRD_PA__OVRRD_SELECT_MASK 0x00000003L 29344#define GC_CAC_OVRD_PA__OVRRD_VALUE_MASK 0x0000000CL 29345//GC_CAC_OVRD_PC 29346#define GC_CAC_OVRD_PC__OVRRD_SELECT__SHIFT 0x0 29347#define GC_CAC_OVRD_PC__OVRRD_VALUE__SHIFT 0x1 29348#define GC_CAC_OVRD_PC__OVRRD_SELECT_MASK 0x00000001L 29349#define GC_CAC_OVRD_PC__OVRRD_VALUE_MASK 0x00000002L 29350//GC_CAC_OVRD_SC 29351#define GC_CAC_OVRD_SC__OVRRD_SELECT__SHIFT 0x0 29352#define GC_CAC_OVRD_SC__OVRRD_VALUE__SHIFT 0x1 29353#define GC_CAC_OVRD_SC__OVRRD_SELECT_MASK 0x00000001L 29354#define GC_CAC_OVRD_SC__OVRRD_VALUE_MASK 0x00000002L 29355//GC_CAC_OVRD_SPI 29356#define GC_CAC_OVRD_SPI__OVRRD_SELECT__SHIFT 0x0 29357#define GC_CAC_OVRD_SPI__OVRRD_VALUE__SHIFT 0x6 29358#define GC_CAC_OVRD_SPI__OVRRD_SELECT_MASK 0x0000003FL 29359#define GC_CAC_OVRD_SPI__OVRRD_VALUE_MASK 0x00000FC0L 29360//GC_CAC_OVRD_CU 29361#define GC_CAC_OVRD_CU__OVRRD_SELECT__SHIFT 0x0 29362#define GC_CAC_OVRD_CU__OVRRD_VALUE__SHIFT 0x1 29363#define GC_CAC_OVRD_CU__OVRRD_SELECT_MASK 0x00000001L 29364#define GC_CAC_OVRD_CU__OVRRD_VALUE_MASK 0x00000002L 29365//GC_CAC_OVRD_SQ 29366#define GC_CAC_OVRD_SQ__OVRRD_SELECT__SHIFT 0x0 29367#define GC_CAC_OVRD_SQ__OVRRD_VALUE__SHIFT 0x9 29368#define GC_CAC_OVRD_SQ__OVRRD_SELECT_MASK 0x000001FFL 29369#define GC_CAC_OVRD_SQ__OVRRD_VALUE_MASK 0x0003FE00L 29370//GC_CAC_OVRD_SX 29371#define GC_CAC_OVRD_SX__OVRRD_SELECT__SHIFT 0x0 29372#define GC_CAC_OVRD_SX__OVRRD_VALUE__SHIFT 0x1 29373#define GC_CAC_OVRD_SX__OVRRD_SELECT_MASK 0x00000001L 29374#define GC_CAC_OVRD_SX__OVRRD_VALUE_MASK 0x00000002L 29375//GC_CAC_OVRD_SXRB 29376#define GC_CAC_OVRD_SXRB__OVRRD_SELECT__SHIFT 0x0 29377#define GC_CAC_OVRD_SXRB__OVRRD_VALUE__SHIFT 0x1 29378#define GC_CAC_OVRD_SXRB__OVRRD_SELECT_MASK 0x00000001L 29379#define GC_CAC_OVRD_SXRB__OVRRD_VALUE_MASK 0x00000002L 29380//GC_CAC_OVRD_TA 29381#define GC_CAC_OVRD_TA__OVRRD_SELECT__SHIFT 0x0 29382#define GC_CAC_OVRD_TA__OVRRD_VALUE__SHIFT 0x1 29383#define GC_CAC_OVRD_TA__OVRRD_SELECT_MASK 0x00000001L 29384#define GC_CAC_OVRD_TA__OVRRD_VALUE_MASK 0x00000002L 29385//GC_CAC_OVRD_TCC 29386#define GC_CAC_OVRD_TCC__OVRRD_SELECT__SHIFT 0x0 29387#define GC_CAC_OVRD_TCC__OVRRD_VALUE__SHIFT 0x5 29388#define GC_CAC_OVRD_TCC__OVRRD_SELECT_MASK 0x0000001FL 29389#define GC_CAC_OVRD_TCC__OVRRD_VALUE_MASK 0x000003E0L 29390//GC_CAC_OVRD_TCP 29391#define GC_CAC_OVRD_TCP__OVRRD_SELECT__SHIFT 0x0 29392#define GC_CAC_OVRD_TCP__OVRRD_VALUE__SHIFT 0x5 29393#define GC_CAC_OVRD_TCP__OVRRD_SELECT_MASK 0x0000001FL 29394#define GC_CAC_OVRD_TCP__OVRRD_VALUE_MASK 0x000003E0L 29395//GC_CAC_OVRD_TD 29396#define GC_CAC_OVRD_TD__OVRRD_SELECT__SHIFT 0x0 29397#define GC_CAC_OVRD_TD__OVRRD_VALUE__SHIFT 0x6 29398#define GC_CAC_OVRD_TD__OVRRD_SELECT_MASK 0x0000003FL 29399#define GC_CAC_OVRD_TD__OVRRD_VALUE_MASK 0x00000FC0L 29400//GC_CAC_OVRD_VGT 29401#define GC_CAC_OVRD_VGT__OVRRD_SELECT__SHIFT 0x0 29402#define GC_CAC_OVRD_VGT__OVRRD_VALUE__SHIFT 0x3 29403#define GC_CAC_OVRD_VGT__OVRRD_SELECT_MASK 0x00000007L 29404#define GC_CAC_OVRD_VGT__OVRRD_VALUE_MASK 0x00000038L 29405//GC_CAC_OVRD_WD 29406#define GC_CAC_OVRD_WD__OVRRD_SELECT__SHIFT 0x0 29407#define GC_CAC_OVRD_WD__OVRRD_VALUE__SHIFT 0x1 29408#define GC_CAC_OVRD_WD__OVRRD_SELECT_MASK 0x00000001L 29409#define GC_CAC_OVRD_WD__OVRRD_VALUE_MASK 0x00000002L 29410//GC_CAC_ACC_BCI1 29411#define GC_CAC_ACC_BCI1__ACCUMULATOR_31_0__SHIFT 0x0 29412#define GC_CAC_ACC_BCI1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29413//GC_CAC_WEIGHT_UTCL2_ATCL2_2 29414#define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG4__SHIFT 0x0 29415#define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG5__SHIFT 0x10 29416#define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG4_MASK 0x0000FFFFL 29417#define GC_CAC_WEIGHT_UTCL2_ATCL2_2__WEIGHT_UTCL2_ATCL2_SIG5_MASK 0xFFFF0000L 29418//GC_CAC_WEIGHT_UTCL2_ROUTER_0 29419#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG0__SHIFT 0x0 29420#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG1__SHIFT 0x10 29421#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG0_MASK 0x0000FFFFL 29422#define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG1_MASK 0xFFFF0000L 29423//GC_CAC_WEIGHT_UTCL2_ROUTER_1 29424#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG2__SHIFT 0x0 29425#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG3__SHIFT 0x10 29426#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG2_MASK 0x0000FFFFL 29427#define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG3_MASK 0xFFFF0000L 29428//GC_CAC_WEIGHT_UTCL2_ROUTER_2 29429#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG4__SHIFT 0x0 29430#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG5__SHIFT 0x10 29431#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG4_MASK 0x0000FFFFL 29432#define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG5_MASK 0xFFFF0000L 29433//GC_CAC_WEIGHT_UTCL2_ROUTER_3 29434#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG6__SHIFT 0x0 29435#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG7__SHIFT 0x10 29436#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG6_MASK 0x0000FFFFL 29437#define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG7_MASK 0xFFFF0000L 29438//GC_CAC_WEIGHT_UTCL2_ROUTER_4 29439#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG8__SHIFT 0x0 29440#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG9__SHIFT 0x10 29441#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG8_MASK 0x0000FFFFL 29442#define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG9_MASK 0xFFFF0000L 29443//GC_CAC_WEIGHT_UTCL2_VML2_0 29444#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG0__SHIFT 0x0 29445#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG1__SHIFT 0x10 29446#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG0_MASK 0x0000FFFFL 29447#define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG1_MASK 0xFFFF0000L 29448//GC_CAC_WEIGHT_UTCL2_VML2_1 29449#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG2__SHIFT 0x0 29450#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG3__SHIFT 0x10 29451#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG2_MASK 0x0000FFFFL 29452#define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG3_MASK 0xFFFF0000L 29453//GC_CAC_WEIGHT_UTCL2_VML2_2 29454#define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG4__SHIFT 0x0 29455#define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG5__SHIFT 0x10 29456#define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG4_MASK 0x0000FFFFL 29457#define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG5_MASK 0xFFFF0000L 29458//GC_CAC_ACC_UTCL2_ATCL24 29459#define GC_CAC_ACC_UTCL2_ATCL24__ACCUMULATOR_31_0__SHIFT 0x0 29460#define GC_CAC_ACC_UTCL2_ATCL24__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29461//GC_CAC_ACC_UTCL2_ROUTER0 29462#define GC_CAC_ACC_UTCL2_ROUTER0__ACCUMULATOR_31_0__SHIFT 0x0 29463#define GC_CAC_ACC_UTCL2_ROUTER0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29464//GC_CAC_ACC_UTCL2_ROUTER1 29465#define GC_CAC_ACC_UTCL2_ROUTER1__ACCUMULATOR_31_0__SHIFT 0x0 29466#define GC_CAC_ACC_UTCL2_ROUTER1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29467//GC_CAC_ACC_UTCL2_ROUTER2 29468#define GC_CAC_ACC_UTCL2_ROUTER2__ACCUMULATOR_31_0__SHIFT 0x0 29469#define GC_CAC_ACC_UTCL2_ROUTER2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29470//GC_CAC_ACC_UTCL2_ROUTER3 29471#define GC_CAC_ACC_UTCL2_ROUTER3__ACCUMULATOR_31_0__SHIFT 0x0 29472#define GC_CAC_ACC_UTCL2_ROUTER3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29473//GC_CAC_ACC_UTCL2_ROUTER4 29474#define GC_CAC_ACC_UTCL2_ROUTER4__ACCUMULATOR_31_0__SHIFT 0x0 29475#define GC_CAC_ACC_UTCL2_ROUTER4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29476//GC_CAC_ACC_UTCL2_ROUTER5 29477#define GC_CAC_ACC_UTCL2_ROUTER5__ACCUMULATOR_31_0__SHIFT 0x0 29478#define GC_CAC_ACC_UTCL2_ROUTER5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29479//GC_CAC_ACC_UTCL2_ROUTER6 29480#define GC_CAC_ACC_UTCL2_ROUTER6__ACCUMULATOR_31_0__SHIFT 0x0 29481#define GC_CAC_ACC_UTCL2_ROUTER6__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29482//GC_CAC_ACC_UTCL2_ROUTER7 29483#define GC_CAC_ACC_UTCL2_ROUTER7__ACCUMULATOR_31_0__SHIFT 0x0 29484#define GC_CAC_ACC_UTCL2_ROUTER7__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29485//GC_CAC_ACC_UTCL2_ROUTER8 29486#define GC_CAC_ACC_UTCL2_ROUTER8__ACCUMULATOR_31_0__SHIFT 0x0 29487#define GC_CAC_ACC_UTCL2_ROUTER8__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29488//GC_CAC_ACC_UTCL2_ROUTER9 29489#define GC_CAC_ACC_UTCL2_ROUTER9__ACCUMULATOR_31_0__SHIFT 0x0 29490#define GC_CAC_ACC_UTCL2_ROUTER9__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29491//GC_CAC_ACC_UTCL2_VML20 29492#define GC_CAC_ACC_UTCL2_VML20__ACCUMULATOR_31_0__SHIFT 0x0 29493#define GC_CAC_ACC_UTCL2_VML20__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29494//GC_CAC_ACC_UTCL2_VML21 29495#define GC_CAC_ACC_UTCL2_VML21__ACCUMULATOR_31_0__SHIFT 0x0 29496#define GC_CAC_ACC_UTCL2_VML21__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29497//GC_CAC_ACC_UTCL2_VML22 29498#define GC_CAC_ACC_UTCL2_VML22__ACCUMULATOR_31_0__SHIFT 0x0 29499#define GC_CAC_ACC_UTCL2_VML22__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29500//GC_CAC_ACC_UTCL2_VML23 29501#define GC_CAC_ACC_UTCL2_VML23__ACCUMULATOR_31_0__SHIFT 0x0 29502#define GC_CAC_ACC_UTCL2_VML23__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29503//GC_CAC_ACC_UTCL2_VML24 29504#define GC_CAC_ACC_UTCL2_VML24__ACCUMULATOR_31_0__SHIFT 0x0 29505#define GC_CAC_ACC_UTCL2_VML24__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29506//GC_CAC_OVRD_UTCL2_ROUTER 29507#define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_SELECT__SHIFT 0x0 29508#define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_VALUE__SHIFT 0xa 29509#define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_SELECT_MASK 0x000003FFL 29510#define GC_CAC_OVRD_UTCL2_ROUTER__OVRRD_VALUE_MASK 0x000FFC00L 29511//GC_CAC_OVRD_UTCL2_VML2 29512#define GC_CAC_OVRD_UTCL2_VML2__OVRRD_SELECT__SHIFT 0x0 29513#define GC_CAC_OVRD_UTCL2_VML2__OVRRD_VALUE__SHIFT 0x5 29514#define GC_CAC_OVRD_UTCL2_VML2__OVRRD_SELECT_MASK 0x0000001FL 29515#define GC_CAC_OVRD_UTCL2_VML2__OVRRD_VALUE_MASK 0x000003E0L 29516//GC_CAC_WEIGHT_UTCL2_WALKER_0 29517#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG0__SHIFT 0x0 29518#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG1__SHIFT 0x10 29519#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG0_MASK 0x0000FFFFL 29520#define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG1_MASK 0xFFFF0000L 29521//GC_CAC_WEIGHT_UTCL2_WALKER_1 29522#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG2__SHIFT 0x0 29523#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG3__SHIFT 0x10 29524#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG2_MASK 0x0000FFFFL 29525#define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG3_MASK 0xFFFF0000L 29526//GC_CAC_WEIGHT_UTCL2_WALKER_2 29527#define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG4__SHIFT 0x0 29528#define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG5__SHIFT 0x10 29529#define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG4_MASK 0x0000FFFFL 29530#define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG5_MASK 0xFFFF0000L 29531//GC_CAC_ACC_UTCL2_WALKER0 29532#define GC_CAC_ACC_UTCL2_WALKER0__ACCUMULATOR_31_0__SHIFT 0x0 29533#define GC_CAC_ACC_UTCL2_WALKER0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29534//GC_CAC_ACC_UTCL2_WALKER1 29535#define GC_CAC_ACC_UTCL2_WALKER1__ACCUMULATOR_31_0__SHIFT 0x0 29536#define GC_CAC_ACC_UTCL2_WALKER1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29537//GC_CAC_ACC_UTCL2_WALKER2 29538#define GC_CAC_ACC_UTCL2_WALKER2__ACCUMULATOR_31_0__SHIFT 0x0 29539#define GC_CAC_ACC_UTCL2_WALKER2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29540//GC_CAC_ACC_UTCL2_WALKER3 29541#define GC_CAC_ACC_UTCL2_WALKER3__ACCUMULATOR_31_0__SHIFT 0x0 29542#define GC_CAC_ACC_UTCL2_WALKER3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29543//GC_CAC_ACC_UTCL2_WALKER4 29544#define GC_CAC_ACC_UTCL2_WALKER4__ACCUMULATOR_31_0__SHIFT 0x0 29545#define GC_CAC_ACC_UTCL2_WALKER4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL 29546//GC_CAC_OVRD_UTCL2_WALKER 29547#define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_SELECT__SHIFT 0x0 29548#define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_VALUE__SHIFT 0x5 29549#define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_SELECT_MASK 0x0000001FL 29550#define GC_CAC_OVRD_UTCL2_WALKER__OVRRD_VALUE_MASK 0x000003E0L 29551 29552 29553// addressBlock: secacind 29554//SE_CAC_CNTL 29555#define SE_CAC_CNTL__CAC_ENABLE__SHIFT 0x0 29556#define SE_CAC_CNTL__CAC_THRESHOLD__SHIFT 0x1 29557#define SE_CAC_CNTL__CAC_BLOCK_ID__SHIFT 0x11 29558#define SE_CAC_CNTL__CAC_SIGNAL_ID__SHIFT 0x17 29559#define SE_CAC_CNTL__UNUSED_0__SHIFT 0x1f 29560#define SE_CAC_CNTL__CAC_ENABLE_MASK 0x00000001L 29561#define SE_CAC_CNTL__CAC_THRESHOLD_MASK 0x0001FFFEL 29562#define SE_CAC_CNTL__CAC_BLOCK_ID_MASK 0x007E0000L 29563#define SE_CAC_CNTL__CAC_SIGNAL_ID_MASK 0x7F800000L 29564#define SE_CAC_CNTL__UNUSED_0_MASK 0x80000000L 29565//SE_CAC_OVR_SEL 29566#define SE_CAC_OVR_SEL__CAC_OVR_SEL__SHIFT 0x0 29567#define SE_CAC_OVR_SEL__CAC_OVR_SEL_MASK 0xFFFFFFFFL 29568//SE_CAC_OVR_VAL 29569#define SE_CAC_OVR_VAL__CAC_OVR_VAL__SHIFT 0x0 29570#define SE_CAC_OVR_VAL__CAC_OVR_VAL_MASK 0xFFFFFFFFL 29571 29572 29573// addressBlock: sqind 29574//SQ_WAVE_MODE 29575#define SQ_WAVE_MODE__FP_ROUND__SHIFT 0x0 29576#define SQ_WAVE_MODE__FP_DENORM__SHIFT 0x4 29577#define SQ_WAVE_MODE__DX10_CLAMP__SHIFT 0x8 29578#define SQ_WAVE_MODE__IEEE__SHIFT 0x9 29579#define SQ_WAVE_MODE__LOD_CLAMPED__SHIFT 0xa 29580#define SQ_WAVE_MODE__EXCP_EN__SHIFT 0xc 29581#define SQ_WAVE_MODE__FP16_OVFL__SHIFT 0x17 29582#define SQ_WAVE_MODE__POPS_PACKER0__SHIFT 0x18 29583#define SQ_WAVE_MODE__POPS_PACKER1__SHIFT 0x19 29584#define SQ_WAVE_MODE__DISABLE_PERF__SHIFT 0x1a 29585#define SQ_WAVE_MODE__GPR_IDX_EN__SHIFT 0x1b 29586#define SQ_WAVE_MODE__VSKIP__SHIFT 0x1c 29587#define SQ_WAVE_MODE__CSP__SHIFT 0x1d 29588#define SQ_WAVE_MODE__FP_ROUND_MASK 0x0000000FL 29589#define SQ_WAVE_MODE__FP_DENORM_MASK 0x000000F0L 29590#define SQ_WAVE_MODE__DX10_CLAMP_MASK 0x00000100L 29591#define SQ_WAVE_MODE__IEEE_MASK 0x00000200L 29592#define SQ_WAVE_MODE__LOD_CLAMPED_MASK 0x00000400L 29593#define SQ_WAVE_MODE__EXCP_EN_MASK 0x001FF000L 29594#define SQ_WAVE_MODE__FP16_OVFL_MASK 0x00800000L 29595#define SQ_WAVE_MODE__POPS_PACKER0_MASK 0x01000000L 29596#define SQ_WAVE_MODE__POPS_PACKER1_MASK 0x02000000L 29597#define SQ_WAVE_MODE__DISABLE_PERF_MASK 0x04000000L 29598#define SQ_WAVE_MODE__GPR_IDX_EN_MASK 0x08000000L 29599#define SQ_WAVE_MODE__VSKIP_MASK 0x10000000L 29600#define SQ_WAVE_MODE__CSP_MASK 0xE0000000L 29601//SQ_WAVE_STATUS 29602#define SQ_WAVE_STATUS__SCC__SHIFT 0x0 29603#define SQ_WAVE_STATUS__SPI_PRIO__SHIFT 0x1 29604#define SQ_WAVE_STATUS__USER_PRIO__SHIFT 0x3 29605#define SQ_WAVE_STATUS__PRIV__SHIFT 0x5 29606#define SQ_WAVE_STATUS__TRAP_EN__SHIFT 0x6 29607#define SQ_WAVE_STATUS__TTRACE_EN__SHIFT 0x7 29608#define SQ_WAVE_STATUS__EXPORT_RDY__SHIFT 0x8 29609#define SQ_WAVE_STATUS__EXECZ__SHIFT 0x9 29610#define SQ_WAVE_STATUS__VCCZ__SHIFT 0xa 29611#define SQ_WAVE_STATUS__IN_TG__SHIFT 0xb 29612#define SQ_WAVE_STATUS__IN_BARRIER__SHIFT 0xc 29613#define SQ_WAVE_STATUS__HALT__SHIFT 0xd 29614#define SQ_WAVE_STATUS__TRAP__SHIFT 0xe 29615#define SQ_WAVE_STATUS__TTRACE_CU_EN__SHIFT 0xf 29616#define SQ_WAVE_STATUS__VALID__SHIFT 0x10 29617#define SQ_WAVE_STATUS__ECC_ERR__SHIFT 0x11 29618#define SQ_WAVE_STATUS__SKIP_EXPORT__SHIFT 0x12 29619#define SQ_WAVE_STATUS__PERF_EN__SHIFT 0x13 29620#define SQ_WAVE_STATUS__ALLOW_REPLAY__SHIFT 0x16 29621#define SQ_WAVE_STATUS__FATAL_HALT__SHIFT 0x17 29622#define SQ_WAVE_STATUS__MUST_EXPORT__SHIFT 0x1b 29623#define SQ_WAVE_STATUS__SCC_MASK 0x00000001L 29624#define SQ_WAVE_STATUS__SPI_PRIO_MASK 0x00000006L 29625#define SQ_WAVE_STATUS__USER_PRIO_MASK 0x00000018L 29626#define SQ_WAVE_STATUS__PRIV_MASK 0x00000020L 29627#define SQ_WAVE_STATUS__TRAP_EN_MASK 0x00000040L 29628#define SQ_WAVE_STATUS__TTRACE_EN_MASK 0x00000080L 29629#define SQ_WAVE_STATUS__EXPORT_RDY_MASK 0x00000100L 29630#define SQ_WAVE_STATUS__EXECZ_MASK 0x00000200L 29631#define SQ_WAVE_STATUS__VCCZ_MASK 0x00000400L 29632#define SQ_WAVE_STATUS__IN_TG_MASK 0x00000800L 29633#define SQ_WAVE_STATUS__IN_BARRIER_MASK 0x00001000L 29634#define SQ_WAVE_STATUS__HALT_MASK 0x00002000L 29635#define SQ_WAVE_STATUS__TRAP_MASK 0x00004000L 29636#define SQ_WAVE_STATUS__TTRACE_CU_EN_MASK 0x00008000L 29637#define SQ_WAVE_STATUS__VALID_MASK 0x00010000L 29638#define SQ_WAVE_STATUS__ECC_ERR_MASK 0x00020000L 29639#define SQ_WAVE_STATUS__SKIP_EXPORT_MASK 0x00040000L 29640#define SQ_WAVE_STATUS__PERF_EN_MASK 0x00080000L 29641#define SQ_WAVE_STATUS__ALLOW_REPLAY_MASK 0x00400000L 29642#define SQ_WAVE_STATUS__FATAL_HALT_MASK 0x00800000L 29643#define SQ_WAVE_STATUS__MUST_EXPORT_MASK 0x08000000L 29644//SQ_WAVE_TRAPSTS 29645#define SQ_WAVE_TRAPSTS__EXCP__SHIFT 0x0 29646#define SQ_WAVE_TRAPSTS__SAVECTX__SHIFT 0xa 29647#define SQ_WAVE_TRAPSTS__ILLEGAL_INST__SHIFT 0xb 29648#define SQ_WAVE_TRAPSTS__EXCP_HI__SHIFT 0xc 29649#define SQ_WAVE_TRAPSTS__EXCP_CYCLE__SHIFT 0x10 29650#define SQ_WAVE_TRAPSTS__XNACK_ERROR__SHIFT 0x1c 29651#define SQ_WAVE_TRAPSTS__DP_RATE__SHIFT 0x1d 29652#define SQ_WAVE_TRAPSTS__EXCP_MASK 0x000001FFL 29653#define SQ_WAVE_TRAPSTS__SAVECTX_MASK 0x00000400L 29654#define SQ_WAVE_TRAPSTS__ILLEGAL_INST_MASK 0x00000800L 29655#define SQ_WAVE_TRAPSTS__EXCP_HI_MASK 0x00007000L 29656#define SQ_WAVE_TRAPSTS__EXCP_CYCLE_MASK 0x003F0000L 29657#define SQ_WAVE_TRAPSTS__XNACK_ERROR_MASK 0x10000000L 29658#define SQ_WAVE_TRAPSTS__DP_RATE_MASK 0xE0000000L 29659//SQ_WAVE_HW_ID 29660#define SQ_WAVE_HW_ID__WAVE_ID__SHIFT 0x0 29661#define SQ_WAVE_HW_ID__SIMD_ID__SHIFT 0x4 29662#define SQ_WAVE_HW_ID__PIPE_ID__SHIFT 0x6 29663#define SQ_WAVE_HW_ID__CU_ID__SHIFT 0x8 29664#define SQ_WAVE_HW_ID__SH_ID__SHIFT 0xc 29665#define SQ_WAVE_HW_ID__SE_ID__SHIFT 0xd 29666#define SQ_WAVE_HW_ID__TG_ID__SHIFT 0x10 29667#define SQ_WAVE_HW_ID__VM_ID__SHIFT 0x14 29668#define SQ_WAVE_HW_ID__QUEUE_ID__SHIFT 0x18 29669#define SQ_WAVE_HW_ID__STATE_ID__SHIFT 0x1b 29670#define SQ_WAVE_HW_ID__ME_ID__SHIFT 0x1e 29671#define SQ_WAVE_HW_ID__WAVE_ID_MASK 0x0000000FL 29672#define SQ_WAVE_HW_ID__SIMD_ID_MASK 0x00000030L 29673#define SQ_WAVE_HW_ID__PIPE_ID_MASK 0x000000C0L 29674#define SQ_WAVE_HW_ID__CU_ID_MASK 0x00000F00L 29675#define SQ_WAVE_HW_ID__SH_ID_MASK 0x00001000L 29676#define SQ_WAVE_HW_ID__SE_ID_MASK 0x00006000L 29677#define SQ_WAVE_HW_ID__TG_ID_MASK 0x000F0000L 29678#define SQ_WAVE_HW_ID__VM_ID_MASK 0x00F00000L 29679#define SQ_WAVE_HW_ID__QUEUE_ID_MASK 0x07000000L 29680#define SQ_WAVE_HW_ID__STATE_ID_MASK 0x38000000L 29681#define SQ_WAVE_HW_ID__ME_ID_MASK 0xC0000000L 29682//SQ_WAVE_GPR_ALLOC 29683#define SQ_WAVE_GPR_ALLOC__VGPR_BASE__SHIFT 0x0 29684#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE__SHIFT 0x8 29685#define SQ_WAVE_GPR_ALLOC__SGPR_BASE__SHIFT 0x10 29686#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE__SHIFT 0x18 29687#define SQ_WAVE_GPR_ALLOC__VGPR_BASE_MASK 0x0000003FL 29688#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE_MASK 0x00003F00L 29689#define SQ_WAVE_GPR_ALLOC__SGPR_BASE_MASK 0x003F0000L 29690#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE_MASK 0x0F000000L 29691//SQ_WAVE_LDS_ALLOC 29692#define SQ_WAVE_LDS_ALLOC__LDS_BASE__SHIFT 0x0 29693#define SQ_WAVE_LDS_ALLOC__LDS_SIZE__SHIFT 0xc 29694#define SQ_WAVE_LDS_ALLOC__LDS_BASE_MASK 0x000000FFL 29695#define SQ_WAVE_LDS_ALLOC__LDS_SIZE_MASK 0x001FF000L 29696//SQ_WAVE_IB_STS 29697#define SQ_WAVE_IB_STS__VM_CNT__SHIFT 0x0 29698#define SQ_WAVE_IB_STS__EXP_CNT__SHIFT 0x4 29699#define SQ_WAVE_IB_STS__LGKM_CNT__SHIFT 0x8 29700#define SQ_WAVE_IB_STS__VALU_CNT__SHIFT 0xc 29701#define SQ_WAVE_IB_STS__FIRST_REPLAY__SHIFT 0xf 29702#define SQ_WAVE_IB_STS__RCNT__SHIFT 0x10 29703#define SQ_WAVE_IB_STS__VM_CNT_HI__SHIFT 0x16 29704#define SQ_WAVE_IB_STS__VM_CNT_MASK 0x0000000FL 29705#define SQ_WAVE_IB_STS__EXP_CNT_MASK 0x00000070L 29706#define SQ_WAVE_IB_STS__LGKM_CNT_MASK 0x00000F00L 29707#define SQ_WAVE_IB_STS__VALU_CNT_MASK 0x00007000L 29708#define SQ_WAVE_IB_STS__FIRST_REPLAY_MASK 0x00008000L 29709#define SQ_WAVE_IB_STS__RCNT_MASK 0x001F0000L 29710#define SQ_WAVE_IB_STS__VM_CNT_HI_MASK 0x00C00000L 29711//SQ_WAVE_PC_LO 29712#define SQ_WAVE_PC_LO__PC_LO__SHIFT 0x0 29713#define SQ_WAVE_PC_LO__PC_LO_MASK 0xFFFFFFFFL 29714//SQ_WAVE_PC_HI 29715#define SQ_WAVE_PC_HI__PC_HI__SHIFT 0x0 29716#define SQ_WAVE_PC_HI__PC_HI_MASK 0x0000FFFFL 29717//SQ_WAVE_INST_DW0 29718#define SQ_WAVE_INST_DW0__INST_DW0__SHIFT 0x0 29719#define SQ_WAVE_INST_DW0__INST_DW0_MASK 0xFFFFFFFFL 29720//SQ_WAVE_INST_DW1 29721#define SQ_WAVE_INST_DW1__INST_DW1__SHIFT 0x0 29722#define SQ_WAVE_INST_DW1__INST_DW1_MASK 0xFFFFFFFFL 29723//SQ_WAVE_IB_DBG0 29724#define SQ_WAVE_IB_DBG0__IBUF_ST__SHIFT 0x0 29725#define SQ_WAVE_IB_DBG0__PC_INVALID__SHIFT 0x3 29726#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW__SHIFT 0x4 29727#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT__SHIFT 0x5 29728#define SQ_WAVE_IB_DBG0__IBUF_RPTR__SHIFT 0x8 29729#define SQ_WAVE_IB_DBG0__IBUF_WPTR__SHIFT 0xa 29730#define SQ_WAVE_IB_DBG0__INST_STR_ST__SHIFT 0x10 29731#define SQ_WAVE_IB_DBG0__ECC_ST__SHIFT 0x18 29732#define SQ_WAVE_IB_DBG0__IS_HYB__SHIFT 0x1a 29733#define SQ_WAVE_IB_DBG0__HYB_CNT__SHIFT 0x1b 29734#define SQ_WAVE_IB_DBG0__KILL__SHIFT 0x1d 29735#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH__SHIFT 0x1e 29736#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_HI__SHIFT 0x1f 29737#define SQ_WAVE_IB_DBG0__IBUF_ST_MASK 0x00000007L 29738#define SQ_WAVE_IB_DBG0__PC_INVALID_MASK 0x00000008L 29739#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW_MASK 0x00000010L 29740#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_MASK 0x000000E0L 29741#define SQ_WAVE_IB_DBG0__IBUF_RPTR_MASK 0x00000300L 29742#define SQ_WAVE_IB_DBG0__IBUF_WPTR_MASK 0x00000C00L 29743#define SQ_WAVE_IB_DBG0__INST_STR_ST_MASK 0x000F0000L 29744#define SQ_WAVE_IB_DBG0__ECC_ST_MASK 0x03000000L 29745#define SQ_WAVE_IB_DBG0__IS_HYB_MASK 0x04000000L 29746#define SQ_WAVE_IB_DBG0__HYB_CNT_MASK 0x18000000L 29747#define SQ_WAVE_IB_DBG0__KILL_MASK 0x20000000L 29748#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH_MASK 0x40000000L 29749#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_HI_MASK 0x80000000L 29750//SQ_WAVE_IB_DBG1 29751#define SQ_WAVE_IB_DBG1__IXNACK__SHIFT 0x0 29752#define SQ_WAVE_IB_DBG1__XNACK__SHIFT 0x1 29753#define SQ_WAVE_IB_DBG1__TA_NEED_RESET__SHIFT 0x2 29754#define SQ_WAVE_IB_DBG1__XCNT__SHIFT 0x4 29755#define SQ_WAVE_IB_DBG1__QCNT__SHIFT 0xb 29756#define SQ_WAVE_IB_DBG1__RCNT__SHIFT 0x12 29757#define SQ_WAVE_IB_DBG1__MISC_CNT__SHIFT 0x19 29758#define SQ_WAVE_IB_DBG1__IXNACK_MASK 0x00000001L 29759#define SQ_WAVE_IB_DBG1__XNACK_MASK 0x00000002L 29760#define SQ_WAVE_IB_DBG1__TA_NEED_RESET_MASK 0x00000004L 29761#define SQ_WAVE_IB_DBG1__XCNT_MASK 0x000001F0L 29762#define SQ_WAVE_IB_DBG1__QCNT_MASK 0x0000F800L 29763#define SQ_WAVE_IB_DBG1__RCNT_MASK 0x007C0000L 29764#define SQ_WAVE_IB_DBG1__MISC_CNT_MASK 0xFE000000L 29765//SQ_WAVE_FLUSH_IB 29766#define SQ_WAVE_FLUSH_IB__UNUSED__SHIFT 0x0 29767#define SQ_WAVE_FLUSH_IB__UNUSED_MASK 0xFFFFFFFFL 29768//SQ_WAVE_TTMP0 29769#define SQ_WAVE_TTMP0__DATA__SHIFT 0x0 29770#define SQ_WAVE_TTMP0__DATA_MASK 0xFFFFFFFFL 29771//SQ_WAVE_TTMP1 29772#define SQ_WAVE_TTMP1__DATA__SHIFT 0x0 29773#define SQ_WAVE_TTMP1__DATA_MASK 0xFFFFFFFFL 29774//SQ_WAVE_TTMP2 29775#define SQ_WAVE_TTMP2__DATA__SHIFT 0x0 29776#define SQ_WAVE_TTMP2__DATA_MASK 0xFFFFFFFFL 29777//SQ_WAVE_TTMP3 29778#define SQ_WAVE_TTMP3__DATA__SHIFT 0x0 29779#define SQ_WAVE_TTMP3__DATA_MASK 0xFFFFFFFFL 29780//SQ_WAVE_TTMP4 29781#define SQ_WAVE_TTMP4__DATA__SHIFT 0x0 29782#define SQ_WAVE_TTMP4__DATA_MASK 0xFFFFFFFFL 29783//SQ_WAVE_TTMP5 29784#define SQ_WAVE_TTMP5__DATA__SHIFT 0x0 29785#define SQ_WAVE_TTMP5__DATA_MASK 0xFFFFFFFFL 29786//SQ_WAVE_TTMP6 29787#define SQ_WAVE_TTMP6__DATA__SHIFT 0x0 29788#define SQ_WAVE_TTMP6__DATA_MASK 0xFFFFFFFFL 29789//SQ_WAVE_TTMP7 29790#define SQ_WAVE_TTMP7__DATA__SHIFT 0x0 29791#define SQ_WAVE_TTMP7__DATA_MASK 0xFFFFFFFFL 29792//SQ_WAVE_TTMP8 29793#define SQ_WAVE_TTMP8__DATA__SHIFT 0x0 29794#define SQ_WAVE_TTMP8__DATA_MASK 0xFFFFFFFFL 29795//SQ_WAVE_TTMP9 29796#define SQ_WAVE_TTMP9__DATA__SHIFT 0x0 29797#define SQ_WAVE_TTMP9__DATA_MASK 0xFFFFFFFFL 29798//SQ_WAVE_TTMP10 29799#define SQ_WAVE_TTMP10__DATA__SHIFT 0x0 29800#define SQ_WAVE_TTMP10__DATA_MASK 0xFFFFFFFFL 29801//SQ_WAVE_TTMP11 29802#define SQ_WAVE_TTMP11__DATA__SHIFT 0x0 29803#define SQ_WAVE_TTMP11__DATA_MASK 0xFFFFFFFFL 29804//SQ_WAVE_TTMP12 29805#define SQ_WAVE_TTMP12__DATA__SHIFT 0x0 29806#define SQ_WAVE_TTMP12__DATA_MASK 0xFFFFFFFFL 29807//SQ_WAVE_TTMP13 29808#define SQ_WAVE_TTMP13__DATA__SHIFT 0x0 29809#define SQ_WAVE_TTMP13__DATA_MASK 0xFFFFFFFFL 29810//SQ_WAVE_TTMP14 29811#define SQ_WAVE_TTMP14__DATA__SHIFT 0x0 29812#define SQ_WAVE_TTMP14__DATA_MASK 0xFFFFFFFFL 29813//SQ_WAVE_TTMP15 29814#define SQ_WAVE_TTMP15__DATA__SHIFT 0x0 29815#define SQ_WAVE_TTMP15__DATA_MASK 0xFFFFFFFFL 29816//SQ_WAVE_M0 29817#define SQ_WAVE_M0__M0__SHIFT 0x0 29818#define SQ_WAVE_M0__M0_MASK 0xFFFFFFFFL 29819//SQ_WAVE_EXEC_LO 29820#define SQ_WAVE_EXEC_LO__EXEC_LO__SHIFT 0x0 29821#define SQ_WAVE_EXEC_LO__EXEC_LO_MASK 0xFFFFFFFFL 29822//SQ_WAVE_EXEC_HI 29823#define SQ_WAVE_EXEC_HI__EXEC_HI__SHIFT 0x0 29824#define SQ_WAVE_EXEC_HI__EXEC_HI_MASK 0xFFFFFFFFL 29825//SQ_INTERRUPT_WORD_AUTO_CTXID 29826#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE__SHIFT 0x0 29827#define SQ_INTERRUPT_WORD_AUTO_CTXID__WLT__SHIFT 0x1 29828#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_BUF_FULL__SHIFT 0x2 29829#define SQ_INTERRUPT_WORD_AUTO_CTXID__REG_TIMESTAMP__SHIFT 0x3 29830#define SQ_INTERRUPT_WORD_AUTO_CTXID__CMD_TIMESTAMP__SHIFT 0x4 29831#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_CMD_OVERFLOW__SHIFT 0x5 29832#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_REG_OVERFLOW__SHIFT 0x6 29833#define SQ_INTERRUPT_WORD_AUTO_CTXID__IMMED_OVERFLOW__SHIFT 0x7 29834#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_UTC_ERROR__SHIFT 0x8 29835#define SQ_INTERRUPT_WORD_AUTO_CTXID__SE_ID__SHIFT 0x18 29836#define SQ_INTERRUPT_WORD_AUTO_CTXID__ENCODING__SHIFT 0x1a 29837#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_MASK 0x0000001L 29838#define SQ_INTERRUPT_WORD_AUTO_CTXID__WLT_MASK 0x0000002L 29839#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_BUF_FULL_MASK 0x0000004L 29840#define SQ_INTERRUPT_WORD_AUTO_CTXID__REG_TIMESTAMP_MASK 0x0000008L 29841#define SQ_INTERRUPT_WORD_AUTO_CTXID__CMD_TIMESTAMP_MASK 0x0000010L 29842#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_CMD_OVERFLOW_MASK 0x0000020L 29843#define SQ_INTERRUPT_WORD_AUTO_CTXID__HOST_REG_OVERFLOW_MASK 0x0000040L 29844#define SQ_INTERRUPT_WORD_AUTO_CTXID__IMMED_OVERFLOW_MASK 0x0000080L 29845#define SQ_INTERRUPT_WORD_AUTO_CTXID__THREAD_TRACE_UTC_ERROR_MASK 0x0000100L 29846#define SQ_INTERRUPT_WORD_AUTO_CTXID__SE_ID_MASK 0x3000000L 29847#define SQ_INTERRUPT_WORD_AUTO_CTXID__ENCODING_MASK 0xC000000L 29848//SQ_INTERRUPT_WORD_AUTO_HI 29849#define SQ_INTERRUPT_WORD_AUTO_HI__SE_ID__SHIFT 0x8 29850#define SQ_INTERRUPT_WORD_AUTO_HI__ENCODING__SHIFT 0xa 29851#define SQ_INTERRUPT_WORD_AUTO_HI__SE_ID_MASK 0x300L 29852#define SQ_INTERRUPT_WORD_AUTO_HI__ENCODING_MASK 0xC00L 29853//SQ_INTERRUPT_WORD_AUTO_LO 29854#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE__SHIFT 0x0 29855#define SQ_INTERRUPT_WORD_AUTO_LO__WLT__SHIFT 0x1 29856#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_BUF_FULL__SHIFT 0x2 29857#define SQ_INTERRUPT_WORD_AUTO_LO__REG_TIMESTAMP__SHIFT 0x3 29858#define SQ_INTERRUPT_WORD_AUTO_LO__CMD_TIMESTAMP__SHIFT 0x4 29859#define SQ_INTERRUPT_WORD_AUTO_LO__HOST_CMD_OVERFLOW__SHIFT 0x5 29860#define SQ_INTERRUPT_WORD_AUTO_LO__HOST_REG_OVERFLOW__SHIFT 0x6 29861#define SQ_INTERRUPT_WORD_AUTO_LO__IMMED_OVERFLOW__SHIFT 0x7 29862#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_UTC_ERROR__SHIFT 0x8 29863#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_MASK 0x001L 29864#define SQ_INTERRUPT_WORD_AUTO_LO__WLT_MASK 0x002L 29865#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_BUF_FULL_MASK 0x004L 29866#define SQ_INTERRUPT_WORD_AUTO_LO__REG_TIMESTAMP_MASK 0x008L 29867#define SQ_INTERRUPT_WORD_AUTO_LO__CMD_TIMESTAMP_MASK 0x010L 29868#define SQ_INTERRUPT_WORD_AUTO_LO__HOST_CMD_OVERFLOW_MASK 0x020L 29869#define SQ_INTERRUPT_WORD_AUTO_LO__HOST_REG_OVERFLOW_MASK 0x040L 29870#define SQ_INTERRUPT_WORD_AUTO_LO__IMMED_OVERFLOW_MASK 0x080L 29871#define SQ_INTERRUPT_WORD_AUTO_LO__THREAD_TRACE_UTC_ERROR_MASK 0x100L 29872//SQ_INTERRUPT_WORD_CMN_CTXID 29873#define SQ_INTERRUPT_WORD_CMN_CTXID__SE_ID__SHIFT 0x18 29874#define SQ_INTERRUPT_WORD_CMN_CTXID__ENCODING__SHIFT 0x1a 29875#define SQ_INTERRUPT_WORD_CMN_CTXID__SE_ID_MASK 0x3000000L 29876#define SQ_INTERRUPT_WORD_CMN_CTXID__ENCODING_MASK 0xC000000L 29877//SQ_INTERRUPT_WORD_CMN_HI 29878#define SQ_INTERRUPT_WORD_CMN_HI__SE_ID__SHIFT 0x8 29879#define SQ_INTERRUPT_WORD_CMN_HI__ENCODING__SHIFT 0xa 29880#define SQ_INTERRUPT_WORD_CMN_HI__SE_ID_MASK 0x300L 29881#define SQ_INTERRUPT_WORD_CMN_HI__ENCODING_MASK 0xC00L 29882//SQ_INTERRUPT_WORD_WAVE_CTXID 29883#define SQ_INTERRUPT_WORD_WAVE_CTXID__DATA__SHIFT 0x0 29884#define SQ_INTERRUPT_WORD_WAVE_CTXID__SH_ID__SHIFT 0xc 29885#define SQ_INTERRUPT_WORD_WAVE_CTXID__PRIV__SHIFT 0xd 29886#define SQ_INTERRUPT_WORD_WAVE_CTXID__WAVE_ID__SHIFT 0xe 29887#define SQ_INTERRUPT_WORD_WAVE_CTXID__SIMD_ID__SHIFT 0x12 29888#define SQ_INTERRUPT_WORD_WAVE_CTXID__CU_ID__SHIFT 0x14 29889#define SQ_INTERRUPT_WORD_WAVE_CTXID__SE_ID__SHIFT 0x18 29890#define SQ_INTERRUPT_WORD_WAVE_CTXID__ENCODING__SHIFT 0x1a 29891#define SQ_INTERRUPT_WORD_WAVE_CTXID__DATA_MASK 0x0000FFFL 29892#define SQ_INTERRUPT_WORD_WAVE_CTXID__SH_ID_MASK 0x0001000L 29893#define SQ_INTERRUPT_WORD_WAVE_CTXID__PRIV_MASK 0x0002000L 29894#define SQ_INTERRUPT_WORD_WAVE_CTXID__WAVE_ID_MASK 0x003C000L 29895#define SQ_INTERRUPT_WORD_WAVE_CTXID__SIMD_ID_MASK 0x00C0000L 29896#define SQ_INTERRUPT_WORD_WAVE_CTXID__CU_ID_MASK 0x0F00000L 29897#define SQ_INTERRUPT_WORD_WAVE_CTXID__SE_ID_MASK 0x3000000L 29898#define SQ_INTERRUPT_WORD_WAVE_CTXID__ENCODING_MASK 0xC000000L 29899//SQ_INTERRUPT_WORD_WAVE_HI 29900#define SQ_INTERRUPT_WORD_WAVE_HI__CU_ID__SHIFT 0x0 29901#define SQ_INTERRUPT_WORD_WAVE_HI__VM_ID__SHIFT 0x4 29902#define SQ_INTERRUPT_WORD_WAVE_HI__SE_ID__SHIFT 0x8 29903#define SQ_INTERRUPT_WORD_WAVE_HI__ENCODING__SHIFT 0xa 29904#define SQ_INTERRUPT_WORD_WAVE_HI__CU_ID_MASK 0x00FL 29905#define SQ_INTERRUPT_WORD_WAVE_HI__VM_ID_MASK 0x0F0L 29906#define SQ_INTERRUPT_WORD_WAVE_HI__SE_ID_MASK 0x300L 29907#define SQ_INTERRUPT_WORD_WAVE_HI__ENCODING_MASK 0xC00L 29908//SQ_INTERRUPT_WORD_WAVE_LO 29909#define SQ_INTERRUPT_WORD_WAVE_LO__DATA__SHIFT 0x0 29910#define SQ_INTERRUPT_WORD_WAVE_LO__SH_ID__SHIFT 0x18 29911#define SQ_INTERRUPT_WORD_WAVE_LO__PRIV__SHIFT 0x19 29912#define SQ_INTERRUPT_WORD_WAVE_LO__WAVE_ID__SHIFT 0x1a 29913#define SQ_INTERRUPT_WORD_WAVE_LO__SIMD_ID__SHIFT 0x1e 29914#define SQ_INTERRUPT_WORD_WAVE_LO__DATA_MASK 0x00FFFFFFL 29915#define SQ_INTERRUPT_WORD_WAVE_LO__SH_ID_MASK 0x01000000L 29916#define SQ_INTERRUPT_WORD_WAVE_LO__PRIV_MASK 0x02000000L 29917#define SQ_INTERRUPT_WORD_WAVE_LO__WAVE_ID_MASK 0x3C000000L 29918#define SQ_INTERRUPT_WORD_WAVE_LO__SIMD_ID_MASK 0xC0000000L 29919 29920 29921 29922 29923 29924 29925 29926 29927// addressBlock: didtind 29928//DIDT_SQ_CTRL0 29929#define DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 29930#define DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT 0x1 29931#define DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT 0x3 29932#define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4 29933#define DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5 29934#define DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6 29935#define DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7 29936#define DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8 29937#define DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18 29938#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19 29939#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a 29940#define DIDT_SQ_CTRL0__UNUSED_0__SHIFT 0x1b 29941#define DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L 29942#define DIDT_SQ_CTRL0__PHASE_OFFSET_MASK 0x00000006L 29943#define DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L 29944#define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L 29945#define DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L 29946#define DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L 29947#define DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L 29948#define DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L 29949#define DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L 29950#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L 29951#define DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L 29952#define DIDT_SQ_CTRL0__UNUSED_0_MASK 0xF8000000L 29953//DIDT_SQ_CTRL1 29954#define DIDT_SQ_CTRL1__MIN_POWER__SHIFT 0x0 29955#define DIDT_SQ_CTRL1__MAX_POWER__SHIFT 0x10 29956#define DIDT_SQ_CTRL1__MIN_POWER_MASK 0x0000FFFFL 29957#define DIDT_SQ_CTRL1__MAX_POWER_MASK 0xFFFF0000L 29958//DIDT_SQ_CTRL2 29959#define DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 29960#define DIDT_SQ_CTRL2__UNUSED_0__SHIFT 0xe 29961#define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 29962#define DIDT_SQ_CTRL2__UNUSED_1__SHIFT 0x1a 29963#define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b 29964#define DIDT_SQ_CTRL2__UNUSED_2__SHIFT 0x1f 29965#define DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL 29966#define DIDT_SQ_CTRL2__UNUSED_0_MASK 0x0000C000L 29967#define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L 29968#define DIDT_SQ_CTRL2__UNUSED_1_MASK 0x04000000L 29969#define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L 29970#define DIDT_SQ_CTRL2__UNUSED_2_MASK 0x80000000L 29971//DIDT_SQ_STALL_CTRL 29972#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0 29973#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6 29974#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc 29975#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12 29976#define DIDT_SQ_STALL_CTRL__UNUSED_0__SHIFT 0x18 29977#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL 29978#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L 29979#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L 29980#define DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L 29981#define DIDT_SQ_STALL_CTRL__UNUSED_0_MASK 0xFF000000L 29982//DIDT_SQ_TUNING_CTRL 29983#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0 29984#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe 29985#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL 29986#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L 29987//DIDT_SQ_STALL_AUTO_RELEASE_CTRL 29988#define DIDT_SQ_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0 29989#define DIDT_SQ_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL 29990//DIDT_SQ_CTRL3 29991#define DIDT_SQ_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0 29992#define DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1 29993#define DIDT_SQ_CTRL3__THROTTLE_POLICY__SHIFT 0x2 29994#define DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 29995#define DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9 29996#define DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe 29997#define DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16 29998#define DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17 29999#define DIDT_SQ_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18 30000#define DIDT_SQ_CTRL3__DIDT_STALL_SEL__SHIFT 0x19
30001#define DIDT_SQ_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b 30002#define DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c 30003#define DIDT_SQ_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L 30004#define DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L 30005#define DIDT_SQ_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL 30006#define DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L 30007#define DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L 30008#define DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L 30009#define DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L 30010#define DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L 30011#define DIDT_SQ_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L 30012#define DIDT_SQ_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L 30013#define DIDT_SQ_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L 30014#define DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L 30015//DIDT_SQ_STALL_PATTERN_1_2 30016#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0 30017#define DIDT_SQ_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf 30018#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10 30019#define DIDT_SQ_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f 30020#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL 30021#define DIDT_SQ_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L 30022#define DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L 30023#define DIDT_SQ_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L 30024//DIDT_SQ_STALL_PATTERN_3_4 30025#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0 30026#define DIDT_SQ_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf 30027#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10 30028#define DIDT_SQ_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f 30029#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL 30030#define DIDT_SQ_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L 30031#define DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L 30032#define DIDT_SQ_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L 30033//DIDT_SQ_STALL_PATTERN_5_6 30034#define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0 30035#define DIDT_SQ_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf 30036#define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10 30037#define DIDT_SQ_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f 30038#define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL 30039#define DIDT_SQ_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L 30040#define DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L 30041#define DIDT_SQ_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L 30042//DIDT_SQ_STALL_PATTERN_7 30043#define DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0 30044#define DIDT_SQ_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf 30045#define DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL 30046#define DIDT_SQ_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L 30047//DIDT_SQ_WEIGHT0_3 30048#define DIDT_SQ_WEIGHT0_3__WEIGHT0__SHIFT 0x0 30049#define DIDT_SQ_WEIGHT0_3__WEIGHT1__SHIFT 0x8 30050#define DIDT_SQ_WEIGHT0_3__WEIGHT2__SHIFT 0x10 30051#define DIDT_SQ_WEIGHT0_3__WEIGHT3__SHIFT 0x18 30052#define DIDT_SQ_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL 30053#define DIDT_SQ_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L 30054#define DIDT_SQ_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L 30055#define DIDT_SQ_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L 30056//DIDT_SQ_WEIGHT4_7 30057#define DIDT_SQ_WEIGHT4_7__WEIGHT4__SHIFT 0x0 30058#define DIDT_SQ_WEIGHT4_7__WEIGHT5__SHIFT 0x8 30059#define DIDT_SQ_WEIGHT4_7__WEIGHT6__SHIFT 0x10 30060#define DIDT_SQ_WEIGHT4_7__WEIGHT7__SHIFT 0x18 30061#define DIDT_SQ_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL 30062#define DIDT_SQ_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L 30063#define DIDT_SQ_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L 30064#define DIDT_SQ_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L 30065//DIDT_SQ_WEIGHT8_11 30066#define DIDT_SQ_WEIGHT8_11__WEIGHT8__SHIFT 0x0 30067#define DIDT_SQ_WEIGHT8_11__WEIGHT9__SHIFT 0x8 30068#define DIDT_SQ_WEIGHT8_11__WEIGHT10__SHIFT 0x10 30069#define DIDT_SQ_WEIGHT8_11__WEIGHT11__SHIFT 0x18 30070#define DIDT_SQ_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL 30071#define DIDT_SQ_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L 30072#define DIDT_SQ_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L 30073#define DIDT_SQ_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L 30074//DIDT_SQ_EDC_CTRL 30075#define DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT 0x0 30076#define DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT 0x1 30077#define DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2 30078#define DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3 30079#define DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 30080#define DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9 30081#define DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11 30082#define DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT 0x12 30083#define DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13 30084#define DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15 30085#define DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16 30086#define DIDT_SQ_EDC_CTRL__UNUSED_0__SHIFT 0x17 30087#define DIDT_SQ_EDC_CTRL__EDC_EN_MASK 0x00000001L 30088#define DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L 30089#define DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L 30090#define DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L 30091#define DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L 30092#define DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L 30093#define DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L 30094#define DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L 30095#define DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L 30096#define DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L 30097#define DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L 30098#define DIDT_SQ_EDC_CTRL__UNUSED_0_MASK 0xFF800000L 30099//DIDT_SQ_EDC_THRESHOLD 30100#define DIDT_SQ_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0 30101#define DIDT_SQ_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL 30102//DIDT_SQ_EDC_STALL_PATTERN_1_2 30103#define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0 30104#define DIDT_SQ_EDC_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf 30105#define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10 30106#define DIDT_SQ_EDC_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f 30107#define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL 30108#define DIDT_SQ_EDC_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L 30109#define DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L 30110#define DIDT_SQ_EDC_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L 30111//DIDT_SQ_EDC_STALL_PATTERN_3_4 30112#define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0 30113#define DIDT_SQ_EDC_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf 30114#define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10 30115#define DIDT_SQ_EDC_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f 30116#define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL 30117#define DIDT_SQ_EDC_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L 30118#define DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L 30119#define DIDT_SQ_EDC_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L 30120//DIDT_SQ_EDC_STALL_PATTERN_5_6 30121#define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0 30122#define DIDT_SQ_EDC_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf 30123#define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10 30124#define DIDT_SQ_EDC_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f 30125#define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL 30126#define DIDT_SQ_EDC_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L 30127#define DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L 30128#define DIDT_SQ_EDC_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L 30129//DIDT_SQ_EDC_STALL_PATTERN_7 30130#define DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0 30131#define DIDT_SQ_EDC_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf 30132#define DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL 30133#define DIDT_SQ_EDC_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L 30134//DIDT_SQ_EDC_STATUS 30135#define DIDT_SQ_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0 30136#define DIDT_SQ_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1 30137#define DIDT_SQ_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L 30138#define DIDT_SQ_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL 30139//DIDT_SQ_EDC_STALL_DELAY_1 30140#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0__SHIFT 0x0 30141#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1__SHIFT 0x6 30142#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2__SHIFT 0xc 30143#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3__SHIFT 0x12 30144#define DIDT_SQ_EDC_STALL_DELAY_1__UNUSED__SHIFT 0x18 30145#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0_MASK 0x0000003FL 30146#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1_MASK 0x00000FC0L 30147#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2_MASK 0x0003F000L 30148#define DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3_MASK 0x00FC0000L 30149#define DIDT_SQ_EDC_STALL_DELAY_1__UNUSED_MASK 0xFF000000L 30150//DIDT_SQ_EDC_STALL_DELAY_2 30151#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4__SHIFT 0x0 30152#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ5__SHIFT 0x6 30153#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ6__SHIFT 0xc 30154#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ7__SHIFT 0x12 30155#define DIDT_SQ_EDC_STALL_DELAY_2__UNUSED__SHIFT 0x18 30156#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4_MASK 0x0000003FL 30157#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ5_MASK 0x00000FC0L 30158#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ6_MASK 0x0003F000L 30159#define DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ7_MASK 0x00FC0000L 30160#define DIDT_SQ_EDC_STALL_DELAY_2__UNUSED_MASK 0xFF000000L 30161//DIDT_SQ_EDC_STALL_DELAY_3 30162#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ8__SHIFT 0x0 30163#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ9__SHIFT 0x6 30164#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ10__SHIFT 0xc 30165#define DIDT_SQ_EDC_STALL_DELAY_3__UNUSED__SHIFT 0x12 30166#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ8_MASK 0x0000003FL 30167#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ9_MASK 0x00000FC0L 30168#define DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ10_MASK 0x0003F000L 30169#define DIDT_SQ_EDC_STALL_DELAY_3__UNUSED_MASK 0xFFFC0000L 30170//DIDT_SQ_EDC_OVERFLOW 30171#define DIDT_SQ_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0 30172#define DIDT_SQ_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1 30173#define DIDT_SQ_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L 30174#define DIDT_SQ_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL 30175//DIDT_SQ_EDC_ROLLING_POWER_DELTA 30176#define DIDT_SQ_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0 30177#define DIDT_SQ_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL 30178//DIDT_DB_CTRL0 30179#define DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 30180#define DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT 0x1 30181#define DIDT_DB_CTRL0__DIDT_CTRL_RST__SHIFT 0x3 30182#define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4 30183#define DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5 30184#define DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6 30185#define DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7 30186#define DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8 30187#define DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18 30188#define DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19 30189#define DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a 30190#define DIDT_DB_CTRL0__UNUSED_0__SHIFT 0x1b 30191#define DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L 30192#define DIDT_DB_CTRL0__PHASE_OFFSET_MASK 0x00000006L 30193#define DIDT_DB_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L 30194#define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L 30195#define DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L 30196#define DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L 30197#define DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L 30198#define DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L 30199#define DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L 30200#define DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L 30201#define DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L 30202#define DIDT_DB_CTRL0__UNUSED_0_MASK 0xF8000000L 30203//DIDT_DB_CTRL1 30204#define DIDT_DB_CTRL1__MIN_POWER__SHIFT 0x0 30205#define DIDT_DB_CTRL1__MAX_POWER__SHIFT 0x10 30206#define DIDT_DB_CTRL1__MIN_POWER_MASK 0x0000FFFFL 30207#define DIDT_DB_CTRL1__MAX_POWER_MASK 0xFFFF0000L 30208//DIDT_DB_CTRL2 30209#define DIDT_DB_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 30210#define DIDT_DB_CTRL2__UNUSED_0__SHIFT 0xe 30211#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 30212#define DIDT_DB_CTRL2__UNUSED_1__SHIFT 0x1a 30213#define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b 30214#define DIDT_DB_CTRL2__UNUSED_2__SHIFT 0x1f 30215#define DIDT_DB_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL 30216#define DIDT_DB_CTRL2__UNUSED_0_MASK 0x0000C000L 30217#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L 30218#define DIDT_DB_CTRL2__UNUSED_1_MASK 0x04000000L 30219#define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L 30220#define DIDT_DB_CTRL2__UNUSED_2_MASK 0x80000000L 30221//DIDT_DB_STALL_CTRL 30222#define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0 30223#define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6 30224#define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc 30225#define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12 30226#define DIDT_DB_STALL_CTRL__UNUSED_0__SHIFT 0x18 30227#define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL 30228#define DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L 30229#define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L 30230#define DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L 30231#define DIDT_DB_STALL_CTRL__UNUSED_0_MASK 0xFF000000L 30232//DIDT_DB_TUNING_CTRL 30233#define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0 30234#define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe 30235#define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL 30236#define DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L 30237//DIDT_DB_STALL_AUTO_RELEASE_CTRL 30238#define DIDT_DB_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0 30239#define DIDT_DB_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL 30240//DIDT_DB_CTRL3 30241#define DIDT_DB_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0 30242#define DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1 30243#define DIDT_DB_CTRL3__THROTTLE_POLICY__SHIFT 0x2 30244#define DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 30245#define DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9 30246#define DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe 30247#define DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16 30248#define DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17 30249#define DIDT_DB_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18 30250#define DIDT_DB_CTRL3__DIDT_STALL_SEL__SHIFT 0x19 30251#define DIDT_DB_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b 30252#define DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c 30253#define DIDT_DB_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L 30254#define DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L 30255#define DIDT_DB_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL 30256#define DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L 30257#define DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L 30258#define DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L 30259#define DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L 30260#define DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L 30261#define DIDT_DB_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L 30262#define DIDT_DB_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L 30263#define DIDT_DB_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L 30264#define DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L 30265//DIDT_DB_STALL_PATTERN_1_2 30266#define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0 30267#define DIDT_DB_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf 30268#define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10 30269#define DIDT_DB_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f 30270#define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL 30271#define DIDT_DB_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L 30272#define DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L 30273#define DIDT_DB_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L 30274//DIDT_DB_STALL_PATTERN_3_4 30275#define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0 30276#define DIDT_DB_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf 30277#define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10 30278#define DIDT_DB_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f 30279#define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL 30280#define DIDT_DB_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L 30281#define DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L 30282#define DIDT_DB_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L 30283//DIDT_DB_STALL_PATTERN_5_6 30284#define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0 30285#define DIDT_DB_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf 30286#define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10 30287#define DIDT_DB_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f 30288#define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL 30289#define DIDT_DB_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L 30290#define DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L 30291#define DIDT_DB_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L 30292//DIDT_DB_STALL_PATTERN_7 30293#define DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0 30294#define DIDT_DB_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf 30295#define DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL 30296#define DIDT_DB_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L 30297//DIDT_DB_WEIGHT0_3 30298#define DIDT_DB_WEIGHT0_3__WEIGHT0__SHIFT 0x0 30299#define DIDT_DB_WEIGHT0_3__WEIGHT1__SHIFT 0x8 30300#define DIDT_DB_WEIGHT0_3__WEIGHT2__SHIFT 0x10 30301#define DIDT_DB_WEIGHT0_3__WEIGHT3__SHIFT 0x18 30302#define DIDT_DB_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL 30303#define DIDT_DB_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L 30304#define DIDT_DB_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L 30305#define DIDT_DB_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L 30306//DIDT_DB_WEIGHT4_7 30307#define DIDT_DB_WEIGHT4_7__WEIGHT4__SHIFT 0x0 30308#define DIDT_DB_WEIGHT4_7__WEIGHT5__SHIFT 0x8 30309#define DIDT_DB_WEIGHT4_7__WEIGHT6__SHIFT 0x10 30310#define DIDT_DB_WEIGHT4_7__WEIGHT7__SHIFT 0x18 30311#define DIDT_DB_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL 30312#define DIDT_DB_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L 30313#define DIDT_DB_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L 30314#define DIDT_DB_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L 30315//DIDT_DB_WEIGHT8_11 30316#define DIDT_DB_WEIGHT8_11__WEIGHT8__SHIFT 0x0 30317#define DIDT_DB_WEIGHT8_11__WEIGHT9__SHIFT 0x8 30318#define DIDT_DB_WEIGHT8_11__WEIGHT10__SHIFT 0x10 30319#define DIDT_DB_WEIGHT8_11__WEIGHT11__SHIFT 0x18 30320#define DIDT_DB_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL 30321#define DIDT_DB_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L 30322#define DIDT_DB_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L 30323#define DIDT_DB_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L 30324//DIDT_DB_EDC_CTRL 30325#define DIDT_DB_EDC_CTRL__EDC_EN__SHIFT 0x0 30326#define DIDT_DB_EDC_CTRL__EDC_SW_RST__SHIFT 0x1 30327#define DIDT_DB_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2 30328#define DIDT_DB_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3 30329#define DIDT_DB_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 30330#define DIDT_DB_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9 30331#define DIDT_DB_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11 30332#define DIDT_DB_EDC_CTRL__GC_EDC_EN__SHIFT 0x12 30333#define DIDT_DB_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13 30334#define DIDT_DB_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15 30335#define DIDT_DB_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16 30336#define DIDT_DB_EDC_CTRL__UNUSED_0__SHIFT 0x17 30337#define DIDT_DB_EDC_CTRL__EDC_EN_MASK 0x00000001L 30338#define DIDT_DB_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L 30339#define DIDT_DB_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L 30340#define DIDT_DB_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L 30341#define DIDT_DB_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L 30342#define DIDT_DB_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L 30343#define DIDT_DB_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L 30344#define DIDT_DB_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L 30345#define DIDT_DB_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L 30346#define DIDT_DB_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L 30347#define DIDT_DB_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L 30348#define DIDT_DB_EDC_CTRL__UNUSED_0_MASK 0xFF800000L 30349//DIDT_DB_EDC_THRESHOLD 30350#define DIDT_DB_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0 30351#define DIDT_DB_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL 30352//DIDT_DB_EDC_STALL_PATTERN_1_2 30353#define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0 30354#define DIDT_DB_EDC_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf 30355#define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10 30356#define DIDT_DB_EDC_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f 30357#define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL 30358#define DIDT_DB_EDC_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L 30359#define DIDT_DB_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L 30360#define DIDT_DB_EDC_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L 30361//DIDT_DB_EDC_STALL_PATTERN_3_4 30362#define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0 30363#define DIDT_DB_EDC_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf 30364#define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10 30365#define DIDT_DB_EDC_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f 30366#define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL 30367#define DIDT_DB_EDC_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L 30368#define DIDT_DB_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L 30369#define DIDT_DB_EDC_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L 30370//DIDT_DB_EDC_STALL_PATTERN_5_6 30371#define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0 30372#define DIDT_DB_EDC_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf 30373#define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10 30374#define DIDT_DB_EDC_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f 30375#define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL 30376#define DIDT_DB_EDC_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L 30377#define DIDT_DB_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L 30378#define DIDT_DB_EDC_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L 30379//DIDT_DB_EDC_STALL_PATTERN_7 30380#define DIDT_DB_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0 30381#define DIDT_DB_EDC_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf 30382#define DIDT_DB_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL 30383#define DIDT_DB_EDC_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L 30384//DIDT_DB_EDC_STATUS 30385#define DIDT_DB_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0 30386#define DIDT_DB_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1 30387#define DIDT_DB_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L 30388#define DIDT_DB_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL 30389//DIDT_DB_EDC_STALL_DELAY_1 30390#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB0__SHIFT 0x0 30391#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB1__SHIFT 0x3 30392#define DIDT_DB_EDC_STALL_DELAY_1__UNUSED__SHIFT 0x6 30393#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB0_MASK 0x00000007L 30394#define DIDT_DB_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DB1_MASK 0x00000038L 30395#define DIDT_DB_EDC_STALL_DELAY_1__UNUSED_MASK 0xFFFFFFC0L 30396//DIDT_DB_EDC_OVERFLOW 30397#define DIDT_DB_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0 30398#define DIDT_DB_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1 30399#define DIDT_DB_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L 30400#define DIDT_DB_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL 30401//DIDT_DB_EDC_ROLLING_POWER_DELTA 30402#define DIDT_DB_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0 30403#define DIDT_DB_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL 30404//DIDT_TD_CTRL0 30405#define DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 30406#define DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT 0x1 30407#define DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT 0x3 30408#define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4 30409#define DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5 30410#define DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6 30411#define DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7 30412#define DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8 30413#define DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18 30414#define DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19 30415#define DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a 30416#define DIDT_TD_CTRL0__UNUSED_0__SHIFT 0x1b 30417#define DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L 30418#define DIDT_TD_CTRL0__PHASE_OFFSET_MASK 0x00000006L 30419#define DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L 30420#define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L 30421#define DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L 30422#define DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L 30423#define DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L 30424#define DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L 30425#define DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L 30426#define DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L 30427#define DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L 30428#define DIDT_TD_CTRL0__UNUSED_0_MASK 0xF8000000L 30429//DIDT_TD_CTRL1 30430#define DIDT_TD_CTRL1__MIN_POWER__SHIFT 0x0 30431#define DIDT_TD_CTRL1__MAX_POWER__SHIFT 0x10 30432#define DIDT_TD_CTRL1__MIN_POWER_MASK 0x0000FFFFL 30433#define DIDT_TD_CTRL1__MAX_POWER_MASK 0xFFFF0000L 30434//DIDT_TD_CTRL2 30435#define DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 30436#define DIDT_TD_CTRL2__UNUSED_0__SHIFT 0xe 30437#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 30438#define DIDT_TD_CTRL2__UNUSED_1__SHIFT 0x1a 30439#define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b 30440#define DIDT_TD_CTRL2__UNUSED_2__SHIFT 0x1f 30441#define DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL 30442#define DIDT_TD_CTRL2__UNUSED_0_MASK 0x0000C000L 30443#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L 30444#define DIDT_TD_CTRL2__UNUSED_1_MASK 0x04000000L 30445#define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L 30446#define DIDT_TD_CTRL2__UNUSED_2_MASK 0x80000000L 30447//DIDT_TD_STALL_CTRL 30448#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0 30449#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6 30450#define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc 30451#define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12 30452#define DIDT_TD_STALL_CTRL__UNUSED_0__SHIFT 0x18 30453#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL 30454#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L 30455#define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L 30456#define DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L 30457#define DIDT_TD_STALL_CTRL__UNUSED_0_MASK 0xFF000000L 30458//DIDT_TD_TUNING_CTRL 30459#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0 30460#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe 30461#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL 30462#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L 30463//DIDT_TD_STALL_AUTO_RELEASE_CTRL 30464#define DIDT_TD_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0 30465#define DIDT_TD_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL 30466//DIDT_TD_CTRL3 30467#define DIDT_TD_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0 30468#define DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1 30469#define DIDT_TD_CTRL3__THROTTLE_POLICY__SHIFT 0x2 30470#define DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 30471#define DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9 30472#define DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe 30473#define DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16 30474#define DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17 30475#define DIDT_TD_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18 30476#define DIDT_TD_CTRL3__DIDT_STALL_SEL__SHIFT 0x19 30477#define DIDT_TD_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b 30478#define DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c 30479#define DIDT_TD_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L 30480#define DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L 30481#define DIDT_TD_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL 30482#define DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L 30483#define DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L 30484#define DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L 30485#define DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L 30486#define DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L 30487#define DIDT_TD_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L 30488#define DIDT_TD_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L 30489#define DIDT_TD_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L 30490#define DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L 30491//DIDT_TD_STALL_PATTERN_1_2 30492#define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0 30493#define DIDT_TD_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf 30494#define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10 30495#define DIDT_TD_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f 30496#define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL 30497#define DIDT_TD_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L 30498#define DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L 30499#define DIDT_TD_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L 30500//DIDT_TD_STALL_PATTERN_3_4 30501#define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0 30502#define DIDT_TD_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf 30503#define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10 30504#define DIDT_TD_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f 30505#define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL 30506#define DIDT_TD_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L 30507#define DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L 30508#define DIDT_TD_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L 30509//DIDT_TD_STALL_PATTERN_5_6 30510#define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0 30511#define DIDT_TD_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf 30512#define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10 30513#define DIDT_TD_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f 30514#define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL 30515#define DIDT_TD_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L 30516#define DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L 30517#define DIDT_TD_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L 30518//DIDT_TD_STALL_PATTERN_7 30519#define DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0 30520#define DIDT_TD_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf 30521#define DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL 30522#define DIDT_TD_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L 30523//DIDT_TD_WEIGHT0_3 30524#define DIDT_TD_WEIGHT0_3__WEIGHT0__SHIFT 0x0 30525#define DIDT_TD_WEIGHT0_3__WEIGHT1__SHIFT 0x8 30526#define DIDT_TD_WEIGHT0_3__WEIGHT2__SHIFT 0x10 30527#define DIDT_TD_WEIGHT0_3__WEIGHT3__SHIFT 0x18 30528#define DIDT_TD_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL 30529#define DIDT_TD_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L 30530#define DIDT_TD_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L 30531#define DIDT_TD_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L 30532//DIDT_TD_WEIGHT4_7 30533#define DIDT_TD_WEIGHT4_7__WEIGHT4__SHIFT 0x0 30534#define DIDT_TD_WEIGHT4_7__WEIGHT5__SHIFT 0x8 30535#define DIDT_TD_WEIGHT4_7__WEIGHT6__SHIFT 0x10 30536#define DIDT_TD_WEIGHT4_7__WEIGHT7__SHIFT 0x18 30537#define DIDT_TD_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL 30538#define DIDT_TD_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L 30539#define DIDT_TD_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L 30540#define DIDT_TD_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L 30541//DIDT_TD_WEIGHT8_11 30542#define DIDT_TD_WEIGHT8_11__WEIGHT8__SHIFT 0x0 30543#define DIDT_TD_WEIGHT8_11__WEIGHT9__SHIFT 0x8 30544#define DIDT_TD_WEIGHT8_11__WEIGHT10__SHIFT 0x10 30545#define DIDT_TD_WEIGHT8_11__WEIGHT11__SHIFT 0x18 30546#define DIDT_TD_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL 30547#define DIDT_TD_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L 30548#define DIDT_TD_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L 30549#define DIDT_TD_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L 30550//DIDT_TD_EDC_CTRL 30551#define DIDT_TD_EDC_CTRL__EDC_EN__SHIFT 0x0 30552#define DIDT_TD_EDC_CTRL__EDC_SW_RST__SHIFT 0x1 30553#define DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2 30554#define DIDT_TD_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3 30555#define DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 30556#define DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9 30557#define DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11 30558#define DIDT_TD_EDC_CTRL__GC_EDC_EN__SHIFT 0x12 30559#define DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13 30560#define DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15 30561#define DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16 30562#define DIDT_TD_EDC_CTRL__UNUSED_0__SHIFT 0x17 30563#define DIDT_TD_EDC_CTRL__EDC_EN_MASK 0x00000001L 30564#define DIDT_TD_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L 30565#define DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L 30566#define DIDT_TD_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L 30567#define DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L 30568#define DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L 30569#define DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L 30570#define DIDT_TD_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L 30571#define DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L 30572#define DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L 30573#define DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L 30574#define DIDT_TD_EDC_CTRL__UNUSED_0_MASK 0xFF800000L 30575//DIDT_TD_EDC_THRESHOLD 30576#define DIDT_TD_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0 30577#define DIDT_TD_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL 30578//DIDT_TD_EDC_STALL_PATTERN_1_2 30579#define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0 30580#define DIDT_TD_EDC_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf 30581#define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10 30582#define DIDT_TD_EDC_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f 30583#define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL 30584#define DIDT_TD_EDC_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L 30585#define DIDT_TD_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L 30586#define DIDT_TD_EDC_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L 30587//DIDT_TD_EDC_STALL_PATTERN_3_4 30588#define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0 30589#define DIDT_TD_EDC_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf 30590#define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10 30591#define DIDT_TD_EDC_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f 30592#define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL 30593#define DIDT_TD_EDC_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L 30594#define DIDT_TD_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L 30595#define DIDT_TD_EDC_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L 30596//DIDT_TD_EDC_STALL_PATTERN_5_6 30597#define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0 30598#define DIDT_TD_EDC_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf 30599#define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10 30600#define DIDT_TD_EDC_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f 30601#define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL 30602#define DIDT_TD_EDC_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L 30603#define DIDT_TD_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L 30604#define DIDT_TD_EDC_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L 30605//DIDT_TD_EDC_STALL_PATTERN_7 30606#define DIDT_TD_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0 30607#define DIDT_TD_EDC_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf 30608#define DIDT_TD_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL 30609#define DIDT_TD_EDC_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L 30610//DIDT_TD_EDC_STATUS 30611#define DIDT_TD_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0 30612#define DIDT_TD_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1 30613#define DIDT_TD_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L 30614#define DIDT_TD_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL 30615//DIDT_TD_EDC_STALL_DELAY_1 30616#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD0__SHIFT 0x0 30617#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD1__SHIFT 0x6 30618#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD2__SHIFT 0xc 30619#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD3__SHIFT 0x12 30620#define DIDT_TD_EDC_STALL_DELAY_1__UNUSED__SHIFT 0x18 30621#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD0_MASK 0x0000003FL 30622#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD1_MASK 0x00000FC0L 30623#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD2_MASK 0x0003F000L 30624#define DIDT_TD_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TD3_MASK 0x00FC0000L 30625#define DIDT_TD_EDC_STALL_DELAY_1__UNUSED_MASK 0xFF000000L 30626//DIDT_TD_EDC_STALL_DELAY_2 30627#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD4__SHIFT 0x0 30628#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD5__SHIFT 0x6 30629#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD6__SHIFT 0xc 30630#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD7__SHIFT 0x12 30631#define DIDT_TD_EDC_STALL_DELAY_2__UNUSED__SHIFT 0x18 30632#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD4_MASK 0x0000003FL 30633#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD5_MASK 0x00000FC0L 30634#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD6_MASK 0x0003F000L 30635#define DIDT_TD_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TD7_MASK 0x00FC0000L 30636#define DIDT_TD_EDC_STALL_DELAY_2__UNUSED_MASK 0xFF000000L 30637//DIDT_TD_EDC_STALL_DELAY_3 30638#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD8__SHIFT 0x0 30639#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD9__SHIFT 0x6 30640#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD10__SHIFT 0xc 30641#define DIDT_TD_EDC_STALL_DELAY_3__UNUSED__SHIFT 0x12 30642#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD8_MASK 0x0000003FL 30643#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD9_MASK 0x00000FC0L 30644#define DIDT_TD_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TD10_MASK 0x0003F000L 30645#define DIDT_TD_EDC_STALL_DELAY_3__UNUSED_MASK 0xFFFC0000L 30646//DIDT_TD_EDC_OVERFLOW 30647#define DIDT_TD_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0 30648#define DIDT_TD_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1 30649#define DIDT_TD_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L 30650#define DIDT_TD_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL 30651//DIDT_TD_EDC_ROLLING_POWER_DELTA 30652#define DIDT_TD_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0 30653#define DIDT_TD_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL 30654//DIDT_TCP_CTRL0 30655#define DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 30656#define DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT 0x1 30657#define DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT 0x3 30658#define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4 30659#define DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5 30660#define DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6 30661#define DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7 30662#define DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8 30663#define DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18 30664#define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19 30665#define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a 30666#define DIDT_TCP_CTRL0__UNUSED_0__SHIFT 0x1b 30667#define DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L 30668#define DIDT_TCP_CTRL0__PHASE_OFFSET_MASK 0x00000006L 30669#define DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L 30670#define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L 30671#define DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L 30672#define DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L 30673#define DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L 30674#define DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L 30675#define DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L 30676#define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L 30677#define DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L 30678#define DIDT_TCP_CTRL0__UNUSED_0_MASK 0xF8000000L 30679//DIDT_TCP_CTRL1 30680#define DIDT_TCP_CTRL1__MIN_POWER__SHIFT 0x0 30681#define DIDT_TCP_CTRL1__MAX_POWER__SHIFT 0x10 30682#define DIDT_TCP_CTRL1__MIN_POWER_MASK 0x0000FFFFL 30683#define DIDT_TCP_CTRL1__MAX_POWER_MASK 0xFFFF0000L 30684//DIDT_TCP_CTRL2 30685#define DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 30686#define DIDT_TCP_CTRL2__UNUSED_0__SHIFT 0xe 30687#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 30688#define DIDT_TCP_CTRL2__UNUSED_1__SHIFT 0x1a 30689#define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b 30690#define DIDT_TCP_CTRL2__UNUSED_2__SHIFT 0x1f 30691#define DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL 30692#define DIDT_TCP_CTRL2__UNUSED_0_MASK 0x0000C000L 30693#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L 30694#define DIDT_TCP_CTRL2__UNUSED_1_MASK 0x04000000L 30695#define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L 30696#define DIDT_TCP_CTRL2__UNUSED_2_MASK 0x80000000L 30697//DIDT_TCP_STALL_CTRL 30698#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0 30699#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6 30700#define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc 30701#define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12 30702#define DIDT_TCP_STALL_CTRL__UNUSED_0__SHIFT 0x18 30703#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL 30704#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L 30705#define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L 30706#define DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L 30707#define DIDT_TCP_STALL_CTRL__UNUSED_0_MASK 0xFF000000L 30708//DIDT_TCP_TUNING_CTRL 30709#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0 30710#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe 30711#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL 30712#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L 30713//DIDT_TCP_STALL_AUTO_RELEASE_CTRL 30714#define DIDT_TCP_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0 30715#define DIDT_TCP_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL 30716//DIDT_TCP_CTRL3 30717#define DIDT_TCP_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0 30718#define DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1 30719#define DIDT_TCP_CTRL3__THROTTLE_POLICY__SHIFT 0x2 30720#define DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 30721#define DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9 30722#define DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe 30723#define DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16 30724#define DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17 30725#define DIDT_TCP_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18 30726#define DIDT_TCP_CTRL3__DIDT_STALL_SEL__SHIFT 0x19 30727#define DIDT_TCP_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b 30728#define DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c 30729#define DIDT_TCP_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L 30730#define DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L 30731#define DIDT_TCP_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL 30732#define DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L 30733#define DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L 30734#define DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L 30735#define DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L 30736#define DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L 30737#define DIDT_TCP_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L 30738#define DIDT_TCP_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L 30739#define DIDT_TCP_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L 30740#define DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L 30741//DIDT_TCP_STALL_PATTERN_1_2 30742#define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0 30743#define DIDT_TCP_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf 30744#define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10 30745#define DIDT_TCP_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f 30746#define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL 30747#define DIDT_TCP_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L 30748#define DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L 30749#define DIDT_TCP_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L 30750//DIDT_TCP_STALL_PATTERN_3_4 30751#define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0 30752#define DIDT_TCP_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf 30753#define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10 30754#define DIDT_TCP_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f 30755#define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL 30756#define DIDT_TCP_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L 30757#define DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L 30758#define DIDT_TCP_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L 30759//DIDT_TCP_STALL_PATTERN_5_6 30760#define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0 30761#define DIDT_TCP_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf 30762#define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10 30763#define DIDT_TCP_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f 30764#define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL 30765#define DIDT_TCP_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L 30766#define DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L 30767#define DIDT_TCP_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L 30768//DIDT_TCP_STALL_PATTERN_7 30769#define DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0 30770#define DIDT_TCP_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf 30771#define DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL 30772#define DIDT_TCP_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L 30773//DIDT_TCP_WEIGHT0_3 30774#define DIDT_TCP_WEIGHT0_3__WEIGHT0__SHIFT 0x0 30775#define DIDT_TCP_WEIGHT0_3__WEIGHT1__SHIFT 0x8 30776#define DIDT_TCP_WEIGHT0_3__WEIGHT2__SHIFT 0x10 30777#define DIDT_TCP_WEIGHT0_3__WEIGHT3__SHIFT 0x18 30778#define DIDT_TCP_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL 30779#define DIDT_TCP_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L 30780#define DIDT_TCP_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L 30781#define DIDT_TCP_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L 30782//DIDT_TCP_WEIGHT4_7 30783#define DIDT_TCP_WEIGHT4_7__WEIGHT4__SHIFT 0x0 30784#define DIDT_TCP_WEIGHT4_7__WEIGHT5__SHIFT 0x8 30785#define DIDT_TCP_WEIGHT4_7__WEIGHT6__SHIFT 0x10 30786#define DIDT_TCP_WEIGHT4_7__WEIGHT7__SHIFT 0x18 30787#define DIDT_TCP_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL 30788#define DIDT_TCP_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L 30789#define DIDT_TCP_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L 30790#define DIDT_TCP_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L 30791//DIDT_TCP_WEIGHT8_11 30792#define DIDT_TCP_WEIGHT8_11__WEIGHT8__SHIFT 0x0 30793#define DIDT_TCP_WEIGHT8_11__WEIGHT9__SHIFT 0x8 30794#define DIDT_TCP_WEIGHT8_11__WEIGHT10__SHIFT 0x10 30795#define DIDT_TCP_WEIGHT8_11__WEIGHT11__SHIFT 0x18 30796#define DIDT_TCP_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL 30797#define DIDT_TCP_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L 30798#define DIDT_TCP_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L 30799#define DIDT_TCP_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L 30800//DIDT_TCP_EDC_CTRL 30801#define DIDT_TCP_EDC_CTRL__EDC_EN__SHIFT 0x0 30802#define DIDT_TCP_EDC_CTRL__EDC_SW_RST__SHIFT 0x1 30803#define DIDT_TCP_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2 30804#define DIDT_TCP_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3 30805#define DIDT_TCP_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 30806#define DIDT_TCP_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9 30807#define DIDT_TCP_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11 30808#define DIDT_TCP_EDC_CTRL__GC_EDC_EN__SHIFT 0x12 30809#define DIDT_TCP_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13 30810#define DIDT_TCP_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15 30811#define DIDT_TCP_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16 30812#define DIDT_TCP_EDC_CTRL__UNUSED_0__SHIFT 0x17 30813#define DIDT_TCP_EDC_CTRL__EDC_EN_MASK 0x00000001L 30814#define DIDT_TCP_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L 30815#define DIDT_TCP_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L 30816#define DIDT_TCP_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L 30817#define DIDT_TCP_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L 30818#define DIDT_TCP_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L 30819#define DIDT_TCP_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L 30820#define DIDT_TCP_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L 30821#define DIDT_TCP_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L 30822#define DIDT_TCP_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L 30823#define DIDT_TCP_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L 30824#define DIDT_TCP_EDC_CTRL__UNUSED_0_MASK 0xFF800000L 30825//DIDT_TCP_EDC_THRESHOLD 30826#define DIDT_TCP_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0 30827#define DIDT_TCP_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL 30828//DIDT_TCP_EDC_STALL_PATTERN_1_2 30829#define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0 30830#define DIDT_TCP_EDC_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf 30831#define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10 30832#define DIDT_TCP_EDC_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f 30833#define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL 30834#define DIDT_TCP_EDC_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L 30835#define DIDT_TCP_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L 30836#define DIDT_TCP_EDC_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L 30837//DIDT_TCP_EDC_STALL_PATTERN_3_4 30838#define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0 30839#define DIDT_TCP_EDC_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf 30840#define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10 30841#define DIDT_TCP_EDC_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f 30842#define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL 30843#define DIDT_TCP_EDC_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L 30844#define DIDT_TCP_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L 30845#define DIDT_TCP_EDC_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L 30846//DIDT_TCP_EDC_STALL_PATTERN_5_6 30847#define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0 30848#define DIDT_TCP_EDC_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf 30849#define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10 30850#define DIDT_TCP_EDC_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f 30851#define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL 30852#define DIDT_TCP_EDC_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L 30853#define DIDT_TCP_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L 30854#define DIDT_TCP_EDC_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L 30855//DIDT_TCP_EDC_STALL_PATTERN_7 30856#define DIDT_TCP_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0 30857#define DIDT_TCP_EDC_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf 30858#define DIDT_TCP_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL 30859#define DIDT_TCP_EDC_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L 30860//DIDT_TCP_EDC_STATUS 30861#define DIDT_TCP_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0 30862#define DIDT_TCP_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1 30863#define DIDT_TCP_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L 30864#define DIDT_TCP_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL 30865//DIDT_TCP_EDC_STALL_DELAY_1 30866#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP0__SHIFT 0x0 30867#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP1__SHIFT 0x6 30868#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP2__SHIFT 0xc 30869#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP3__SHIFT 0x12 30870#define DIDT_TCP_EDC_STALL_DELAY_1__UNUSED__SHIFT 0x18 30871#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP0_MASK 0x0000003FL 30872#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP1_MASK 0x00000FC0L 30873#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP2_MASK 0x0003F000L 30874#define DIDT_TCP_EDC_STALL_DELAY_1__EDC_STALL_DELAY_TCP3_MASK 0x00FC0000L 30875#define DIDT_TCP_EDC_STALL_DELAY_1__UNUSED_MASK 0xFF000000L 30876//DIDT_TCP_EDC_STALL_DELAY_2 30877#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP4__SHIFT 0x0 30878#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP5__SHIFT 0x6 30879#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP6__SHIFT 0xc 30880#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP7__SHIFT 0x12 30881#define DIDT_TCP_EDC_STALL_DELAY_2__UNUSED__SHIFT 0x18 30882#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP4_MASK 0x0000003FL 30883#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP5_MASK 0x00000FC0L 30884#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP6_MASK 0x0003F000L 30885#define DIDT_TCP_EDC_STALL_DELAY_2__EDC_STALL_DELAY_TCP7_MASK 0x00FC0000L 30886#define DIDT_TCP_EDC_STALL_DELAY_2__UNUSED_MASK 0xFF000000L 30887//DIDT_TCP_EDC_STALL_DELAY_3 30888#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP8__SHIFT 0x0 30889#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP9__SHIFT 0x6 30890#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP10__SHIFT 0xc 30891#define DIDT_TCP_EDC_STALL_DELAY_3__UNUSED__SHIFT 0x12 30892#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP8_MASK 0x0000003FL 30893#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP9_MASK 0x00000FC0L 30894#define DIDT_TCP_EDC_STALL_DELAY_3__EDC_STALL_DELAY_TCP10_MASK 0x0003F000L 30895#define DIDT_TCP_EDC_STALL_DELAY_3__UNUSED_MASK 0xFFFC0000L 30896//DIDT_TCP_EDC_OVERFLOW 30897#define DIDT_TCP_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0 30898#define DIDT_TCP_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1 30899#define DIDT_TCP_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L 30900#define DIDT_TCP_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL 30901//DIDT_TCP_EDC_ROLLING_POWER_DELTA 30902#define DIDT_TCP_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0 30903#define DIDT_TCP_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL 30904//DIDT_DBR_CTRL0 30905#define DIDT_DBR_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 30906#define DIDT_DBR_CTRL0__PHASE_OFFSET__SHIFT 0x1 30907#define DIDT_DBR_CTRL0__DIDT_CTRL_RST__SHIFT 0x3 30908#define DIDT_DBR_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x4 30909#define DIDT_DBR_CTRL0__DIDT_STALL_CTRL_EN__SHIFT 0x5 30910#define DIDT_DBR_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT 0x6 30911#define DIDT_DBR_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT 0x7 30912#define DIDT_DBR_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT 0x8 30913#define DIDT_DBR_CTRL0__DIDT_AUTO_MPD_EN__SHIFT 0x18 30914#define DIDT_DBR_CTRL0__DIDT_STALL_EVENT_EN__SHIFT 0x19 30915#define DIDT_DBR_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT 0x1a 30916#define DIDT_DBR_CTRL0__UNUSED_0__SHIFT 0x1b 30917#define DIDT_DBR_CTRL0__DIDT_CTRL_EN_MASK 0x00000001L 30918#define DIDT_DBR_CTRL0__PHASE_OFFSET_MASK 0x00000006L 30919#define DIDT_DBR_CTRL0__DIDT_CTRL_RST_MASK 0x00000008L 30920#define DIDT_DBR_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x00000010L 30921#define DIDT_DBR_CTRL0__DIDT_STALL_CTRL_EN_MASK 0x00000020L 30922#define DIDT_DBR_CTRL0__DIDT_TUNING_CTRL_EN_MASK 0x00000040L 30923#define DIDT_DBR_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK 0x00000080L 30924#define DIDT_DBR_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK 0x00FFFF00L 30925#define DIDT_DBR_CTRL0__DIDT_AUTO_MPD_EN_MASK 0x01000000L 30926#define DIDT_DBR_CTRL0__DIDT_STALL_EVENT_EN_MASK 0x02000000L 30927#define DIDT_DBR_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK 0x04000000L 30928#define DIDT_DBR_CTRL0__UNUSED_0_MASK 0xF8000000L 30929//DIDT_DBR_CTRL1 30930#define DIDT_DBR_CTRL1__MIN_POWER__SHIFT 0x0 30931#define DIDT_DBR_CTRL1__MAX_POWER__SHIFT 0x10 30932#define DIDT_DBR_CTRL1__MIN_POWER_MASK 0x0000FFFFL 30933#define DIDT_DBR_CTRL1__MAX_POWER_MASK 0xFFFF0000L 30934//DIDT_DBR_CTRL2 30935#define DIDT_DBR_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 30936#define DIDT_DBR_CTRL2__UNUSED_0__SHIFT 0xe 30937#define DIDT_DBR_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 30938#define DIDT_DBR_CTRL2__UNUSED_1__SHIFT 0x1a 30939#define DIDT_DBR_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b 30940#define DIDT_DBR_CTRL2__UNUSED_2__SHIFT 0x1f 30941#define DIDT_DBR_CTRL2__MAX_POWER_DELTA_MASK 0x00003FFFL 30942#define DIDT_DBR_CTRL2__UNUSED_0_MASK 0x0000C000L 30943#define DIDT_DBR_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x03FF0000L 30944#define DIDT_DBR_CTRL2__UNUSED_1_MASK 0x04000000L 30945#define DIDT_DBR_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000L 30946#define DIDT_DBR_CTRL2__UNUSED_2_MASK 0x80000000L 30947//DIDT_DBR_STALL_CTRL 30948#define DIDT_DBR_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT 0x0 30949#define DIDT_DBR_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT 0x6 30950#define DIDT_DBR_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT 0xc 30951#define DIDT_DBR_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT 0x12 30952#define DIDT_DBR_STALL_CTRL__UNUSED_0__SHIFT 0x18 30953#define DIDT_DBR_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK 0x0000003FL 30954#define DIDT_DBR_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK 0x00000FC0L 30955#define DIDT_DBR_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK 0x0003F000L 30956#define DIDT_DBR_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK 0x00FC0000L 30957#define DIDT_DBR_STALL_CTRL__UNUSED_0_MASK 0xFF000000L 30958//DIDT_DBR_TUNING_CTRL 30959#define DIDT_DBR_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT 0x0 30960#define DIDT_DBR_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT 0xe 30961#define DIDT_DBR_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK 0x00003FFFL 30962#define DIDT_DBR_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK 0x0FFFC000L 30963//DIDT_DBR_STALL_AUTO_RELEASE_CTRL 30964#define DIDT_DBR_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME__SHIFT 0x0 30965#define DIDT_DBR_STALL_AUTO_RELEASE_CTRL__DIDT_STALL_AUTO_RELEASE_TIME_MASK 0x00FFFFFFL 30966//DIDT_DBR_CTRL3 30967#define DIDT_DBR_CTRL3__GC_DIDT_ENABLE__SHIFT 0x0 30968#define DIDT_DBR_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT 0x1 30969#define DIDT_DBR_CTRL3__THROTTLE_POLICY__SHIFT 0x2 30970#define DIDT_DBR_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 30971#define DIDT_DBR_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT 0x9 30972#define DIDT_DBR_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0xe 30973#define DIDT_DBR_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT 0x16 30974#define DIDT_DBR_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT 0x17 30975#define DIDT_DBR_CTRL3__QUALIFY_STALL_EN__SHIFT 0x18 30976#define DIDT_DBR_CTRL3__DIDT_STALL_SEL__SHIFT 0x19 30977#define DIDT_DBR_CTRL3__DIDT_FORCE_STALL__SHIFT 0x1b 30978#define DIDT_DBR_CTRL3__DIDT_STALL_DELAY_EN__SHIFT 0x1c 30979#define DIDT_DBR_CTRL3__GC_DIDT_ENABLE_MASK 0x00000001L 30980#define DIDT_DBR_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK 0x00000002L 30981#define DIDT_DBR_CTRL3__THROTTLE_POLICY_MASK 0x0000000CL 30982#define DIDT_DBR_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L 30983#define DIDT_DBR_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK 0x00003E00L 30984#define DIDT_DBR_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x003FC000L 30985#define DIDT_DBR_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK 0x00400000L 30986#define DIDT_DBR_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK 0x00800000L 30987#define DIDT_DBR_CTRL3__QUALIFY_STALL_EN_MASK 0x01000000L 30988#define DIDT_DBR_CTRL3__DIDT_STALL_SEL_MASK 0x06000000L 30989#define DIDT_DBR_CTRL3__DIDT_FORCE_STALL_MASK 0x08000000L 30990#define DIDT_DBR_CTRL3__DIDT_STALL_DELAY_EN_MASK 0x10000000L 30991//DIDT_DBR_STALL_PATTERN_1_2 30992#define DIDT_DBR_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0 30993#define DIDT_DBR_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf 30994#define DIDT_DBR_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10 30995#define DIDT_DBR_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f 30996#define DIDT_DBR_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL 30997#define DIDT_DBR_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L 30998#define DIDT_DBR_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L 30999#define DIDT_DBR_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L 31000//DIDT_DBR_STALL_PATTERN_3_4
31001#define DIDT_DBR_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0 31002#define DIDT_DBR_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf 31003#define DIDT_DBR_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10 31004#define DIDT_DBR_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f 31005#define DIDT_DBR_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL 31006#define DIDT_DBR_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L 31007#define DIDT_DBR_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L 31008#define DIDT_DBR_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L 31009//DIDT_DBR_STALL_PATTERN_5_6 31010#define DIDT_DBR_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0 31011#define DIDT_DBR_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf 31012#define DIDT_DBR_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10 31013#define DIDT_DBR_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f 31014#define DIDT_DBR_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL 31015#define DIDT_DBR_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L 31016#define DIDT_DBR_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L 31017#define DIDT_DBR_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L 31018//DIDT_DBR_STALL_PATTERN_7 31019#define DIDT_DBR_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0 31020#define DIDT_DBR_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf 31021#define DIDT_DBR_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL 31022#define DIDT_DBR_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L 31023//DIDT_DBR_WEIGHT0_3 31024#define DIDT_DBR_WEIGHT0_3__WEIGHT0__SHIFT 0x0 31025#define DIDT_DBR_WEIGHT0_3__WEIGHT1__SHIFT 0x8 31026#define DIDT_DBR_WEIGHT0_3__WEIGHT2__SHIFT 0x10 31027#define DIDT_DBR_WEIGHT0_3__WEIGHT3__SHIFT 0x18 31028#define DIDT_DBR_WEIGHT0_3__WEIGHT0_MASK 0x000000FFL 31029#define DIDT_DBR_WEIGHT0_3__WEIGHT1_MASK 0x0000FF00L 31030#define DIDT_DBR_WEIGHT0_3__WEIGHT2_MASK 0x00FF0000L 31031#define DIDT_DBR_WEIGHT0_3__WEIGHT3_MASK 0xFF000000L 31032//DIDT_DBR_WEIGHT4_7 31033#define DIDT_DBR_WEIGHT4_7__WEIGHT4__SHIFT 0x0 31034#define DIDT_DBR_WEIGHT4_7__WEIGHT5__SHIFT 0x8 31035#define DIDT_DBR_WEIGHT4_7__WEIGHT6__SHIFT 0x10 31036#define DIDT_DBR_WEIGHT4_7__WEIGHT7__SHIFT 0x18 31037#define DIDT_DBR_WEIGHT4_7__WEIGHT4_MASK 0x000000FFL 31038#define DIDT_DBR_WEIGHT4_7__WEIGHT5_MASK 0x0000FF00L 31039#define DIDT_DBR_WEIGHT4_7__WEIGHT6_MASK 0x00FF0000L 31040#define DIDT_DBR_WEIGHT4_7__WEIGHT7_MASK 0xFF000000L 31041//DIDT_DBR_WEIGHT8_11 31042#define DIDT_DBR_WEIGHT8_11__WEIGHT8__SHIFT 0x0 31043#define DIDT_DBR_WEIGHT8_11__WEIGHT9__SHIFT 0x8 31044#define DIDT_DBR_WEIGHT8_11__WEIGHT10__SHIFT 0x10 31045#define DIDT_DBR_WEIGHT8_11__WEIGHT11__SHIFT 0x18 31046#define DIDT_DBR_WEIGHT8_11__WEIGHT8_MASK 0x000000FFL 31047#define DIDT_DBR_WEIGHT8_11__WEIGHT9_MASK 0x0000FF00L 31048#define DIDT_DBR_WEIGHT8_11__WEIGHT10_MASK 0x00FF0000L 31049#define DIDT_DBR_WEIGHT8_11__WEIGHT11_MASK 0xFF000000L 31050//DIDT_DBR_EDC_CTRL 31051#define DIDT_DBR_EDC_CTRL__EDC_EN__SHIFT 0x0 31052#define DIDT_DBR_EDC_CTRL__EDC_SW_RST__SHIFT 0x1 31053#define DIDT_DBR_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2 31054#define DIDT_DBR_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3 31055#define DIDT_DBR_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 31056#define DIDT_DBR_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0x9 31057#define DIDT_DBR_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0x11 31058#define DIDT_DBR_EDC_CTRL__GC_EDC_EN__SHIFT 0x12 31059#define DIDT_DBR_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT 0x13 31060#define DIDT_DBR_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT 0x15 31061#define DIDT_DBR_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT 0x16 31062#define DIDT_DBR_EDC_CTRL__UNUSED_0__SHIFT 0x17 31063#define DIDT_DBR_EDC_CTRL__EDC_EN_MASK 0x00000001L 31064#define DIDT_DBR_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L 31065#define DIDT_DBR_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L 31066#define DIDT_DBR_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L 31067#define DIDT_DBR_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000001F0L 31068#define DIDT_DBR_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x0001FE00L 31069#define DIDT_DBR_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00020000L 31070#define DIDT_DBR_EDC_CTRL__GC_EDC_EN_MASK 0x00040000L 31071#define DIDT_DBR_EDC_CTRL__GC_EDC_STALL_POLICY_MASK 0x00180000L 31072#define DIDT_DBR_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK 0x00200000L 31073#define DIDT_DBR_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK 0x00400000L 31074#define DIDT_DBR_EDC_CTRL__UNUSED_0_MASK 0xFF800000L 31075//DIDT_DBR_EDC_THRESHOLD 31076#define DIDT_DBR_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0 31077#define DIDT_DBR_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL 31078//DIDT_DBR_EDC_STALL_PATTERN_1_2 31079#define DIDT_DBR_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0 31080#define DIDT_DBR_EDC_STALL_PATTERN_1_2__UNUSED_0__SHIFT 0xf 31081#define DIDT_DBR_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10 31082#define DIDT_DBR_EDC_STALL_PATTERN_1_2__UNUSED_1__SHIFT 0x1f 31083#define DIDT_DBR_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL 31084#define DIDT_DBR_EDC_STALL_PATTERN_1_2__UNUSED_0_MASK 0x00008000L 31085#define DIDT_DBR_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L 31086#define DIDT_DBR_EDC_STALL_PATTERN_1_2__UNUSED_1_MASK 0x80000000L 31087//DIDT_DBR_EDC_STALL_PATTERN_3_4 31088#define DIDT_DBR_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0 31089#define DIDT_DBR_EDC_STALL_PATTERN_3_4__UNUSED_0__SHIFT 0xf 31090#define DIDT_DBR_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10 31091#define DIDT_DBR_EDC_STALL_PATTERN_3_4__UNUSED_1__SHIFT 0x1f 31092#define DIDT_DBR_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL 31093#define DIDT_DBR_EDC_STALL_PATTERN_3_4__UNUSED_0_MASK 0x00008000L 31094#define DIDT_DBR_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L 31095#define DIDT_DBR_EDC_STALL_PATTERN_3_4__UNUSED_1_MASK 0x80000000L 31096//DIDT_DBR_EDC_STALL_PATTERN_5_6 31097#define DIDT_DBR_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0 31098#define DIDT_DBR_EDC_STALL_PATTERN_5_6__UNUSED_0__SHIFT 0xf 31099#define DIDT_DBR_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10 31100#define DIDT_DBR_EDC_STALL_PATTERN_5_6__UNUSED_1__SHIFT 0x1f 31101#define DIDT_DBR_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL 31102#define DIDT_DBR_EDC_STALL_PATTERN_5_6__UNUSED_0_MASK 0x00008000L 31103#define DIDT_DBR_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L 31104#define DIDT_DBR_EDC_STALL_PATTERN_5_6__UNUSED_1_MASK 0x80000000L 31105//DIDT_DBR_EDC_STALL_PATTERN_7 31106#define DIDT_DBR_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0 31107#define DIDT_DBR_EDC_STALL_PATTERN_7__UNUSED_0__SHIFT 0xf 31108#define DIDT_DBR_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL 31109#define DIDT_DBR_EDC_STALL_PATTERN_7__UNUSED_0_MASK 0xFFFF8000L 31110//DIDT_DBR_EDC_STATUS 31111#define DIDT_DBR_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0 31112#define DIDT_DBR_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1 31113#define DIDT_DBR_EDC_STATUS__UNUSED_0__SHIFT 0x4 31114#define DIDT_DBR_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L 31115#define DIDT_DBR_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL 31116#define DIDT_DBR_EDC_STATUS__UNUSED_0_MASK 0xFFFFFFF0L 31117//DIDT_DBR_EDC_STALL_DELAY_1 31118#define DIDT_DBR_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DBR0__SHIFT 0x0 31119#define DIDT_DBR_EDC_STALL_DELAY_1__UNUSED__SHIFT 0x1 31120#define DIDT_DBR_EDC_STALL_DELAY_1__EDC_STALL_DELAY_DBR0_MASK 0x00000001L 31121#define DIDT_DBR_EDC_STALL_DELAY_1__UNUSED_MASK 0xFFFFFFFEL 31122//DIDT_DBR_EDC_OVERFLOW 31123#define DIDT_DBR_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0 31124#define DIDT_DBR_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1 31125#define DIDT_DBR_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L 31126#define DIDT_DBR_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL 31127//DIDT_DBR_EDC_ROLLING_POWER_DELTA 31128#define DIDT_DBR_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0 31129#define DIDT_DBR_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL 31130//DIDT_SQ_STALL_EVENT_COUNTER 31131#define DIDT_SQ_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0 31132#define DIDT_SQ_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL 31133//DIDT_DB_STALL_EVENT_COUNTER 31134#define DIDT_DB_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0 31135#define DIDT_DB_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL 31136//DIDT_TD_STALL_EVENT_COUNTER 31137#define DIDT_TD_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0 31138#define DIDT_TD_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL 31139//DIDT_TCP_STALL_EVENT_COUNTER 31140#define DIDT_TCP_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0 31141#define DIDT_TCP_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL 31142//DIDT_DBR_STALL_EVENT_COUNTER 31143#define DIDT_DBR_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER__SHIFT 0x0 31144#define DIDT_DBR_STALL_EVENT_COUNTER__DIDT_STALL_EVENT_COUNTER_MASK 0xFFFFFFFFL 31145 31146 31147 31148 31149 31150#endif 31151