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23#ifndef _HWMGR_H_
24#define _HWMGR_H_
25
26#include <linux/seq_file.h>
27#include "amd_powerplay.h"
28#include "hardwaremanager.h"
29#include "hwmgr_ppt.h"
30#include "ppatomctrl.h"
31#include "power_state.h"
32#include "smu_helper.h"
33
34struct pp_hwmgr;
35struct phm_fan_speed_info;
36struct pp_atomctrl_voltage_table;
37
38#define VOLTAGE_SCALE 4
39#define VOLTAGE_VID_OFFSET_SCALE1 625
40#define VOLTAGE_VID_OFFSET_SCALE2 100
41
42enum DISPLAY_GAP {
43 DISPLAY_GAP_VBLANK_OR_WM = 0,
44 DISPLAY_GAP_VBLANK = 1,
45 DISPLAY_GAP_WATERMARK = 2,
46 DISPLAY_GAP_IGNORE = 3
47};
48typedef enum DISPLAY_GAP DISPLAY_GAP;
49
50struct vi_dpm_level {
51 bool enabled;
52 uint32_t value;
53 uint32_t param1;
54};
55
56struct vi_dpm_table {
57 uint32_t count;
58 struct vi_dpm_level dpm_level[1];
59};
60
61#define PCIE_PERF_REQ_REMOVE_REGISTRY 0
62#define PCIE_PERF_REQ_FORCE_LOWPOWER 1
63#define PCIE_PERF_REQ_GEN1 2
64#define PCIE_PERF_REQ_GEN2 3
65#define PCIE_PERF_REQ_GEN3 4
66
67enum PHM_BackEnd_Magic {
68 PHM_Dummy_Magic = 0xAA5555AA,
69 PHM_RV770_Magic = 0xDCBAABCD,
70 PHM_Kong_Magic = 0x239478DF,
71 PHM_NIslands_Magic = 0x736C494E,
72 PHM_Sumo_Magic = 0x8339FA11,
73 PHM_SIslands_Magic = 0x369431AC,
74 PHM_Trinity_Magic = 0x96751873,
75 PHM_CIslands_Magic = 0x38AC78B0,
76 PHM_Kv_Magic = 0xDCBBABC0,
77 PHM_VIslands_Magic = 0x20130307,
78 PHM_Cz_Magic = 0x67DCBA25,
79 PHM_Rv_Magic = 0x20161121
80};
81
82struct phm_set_power_state_input {
83 const struct pp_hw_power_state *pcurrent_state;
84 const struct pp_hw_power_state *pnew_state;
85};
86
87struct phm_clock_array {
88 uint32_t count;
89 uint32_t values[1];
90};
91
92struct phm_clock_voltage_dependency_record {
93 uint32_t clk;
94 uint32_t v;
95};
96
97struct phm_vceclock_voltage_dependency_record {
98 uint32_t ecclk;
99 uint32_t evclk;
100 uint32_t v;
101};
102
103struct phm_uvdclock_voltage_dependency_record {
104 uint32_t vclk;
105 uint32_t dclk;
106 uint32_t v;
107};
108
109struct phm_samuclock_voltage_dependency_record {
110 uint32_t samclk;
111 uint32_t v;
112};
113
114struct phm_acpclock_voltage_dependency_record {
115 uint32_t acpclk;
116 uint32_t v;
117};
118
119struct phm_clock_voltage_dependency_table {
120 uint32_t count;
121 struct phm_clock_voltage_dependency_record entries[1];
122};
123
124struct phm_phase_shedding_limits_record {
125 uint32_t Voltage;
126 uint32_t Sclk;
127 uint32_t Mclk;
128};
129
130struct phm_uvd_clock_voltage_dependency_record {
131 uint32_t vclk;
132 uint32_t dclk;
133 uint32_t v;
134};
135
136struct phm_uvd_clock_voltage_dependency_table {
137 uint8_t count;
138 struct phm_uvd_clock_voltage_dependency_record entries[1];
139};
140
141struct phm_acp_clock_voltage_dependency_record {
142 uint32_t acpclk;
143 uint32_t v;
144};
145
146struct phm_acp_clock_voltage_dependency_table {
147 uint32_t count;
148 struct phm_acp_clock_voltage_dependency_record entries[1];
149};
150
151struct phm_vce_clock_voltage_dependency_record {
152 uint32_t ecclk;
153 uint32_t evclk;
154 uint32_t v;
155};
156
157struct phm_phase_shedding_limits_table {
158 uint32_t count;
159 struct phm_phase_shedding_limits_record entries[1];
160};
161
162struct phm_vceclock_voltage_dependency_table {
163 uint8_t count;
164 struct phm_vceclock_voltage_dependency_record entries[1];
165};
166
167struct phm_uvdclock_voltage_dependency_table {
168 uint8_t count;
169 struct phm_uvdclock_voltage_dependency_record entries[1];
170};
171
172struct phm_samuclock_voltage_dependency_table {
173 uint8_t count;
174 struct phm_samuclock_voltage_dependency_record entries[1];
175};
176
177struct phm_acpclock_voltage_dependency_table {
178 uint32_t count;
179 struct phm_acpclock_voltage_dependency_record entries[1];
180};
181
182struct phm_vce_clock_voltage_dependency_table {
183 uint8_t count;
184 struct phm_vce_clock_voltage_dependency_record entries[1];
185};
186
187struct pp_smumgr_func {
188 int (*smu_init)(struct pp_hwmgr *hwmgr);
189 int (*smu_fini)(struct pp_hwmgr *hwmgr);
190 int (*start_smu)(struct pp_hwmgr *hwmgr);
191 int (*check_fw_load_finish)(struct pp_hwmgr *hwmgr,
192 uint32_t firmware);
193 int (*request_smu_load_fw)(struct pp_hwmgr *hwmgr);
194 int (*request_smu_load_specific_fw)(struct pp_hwmgr *hwmgr,
195 uint32_t firmware);
196 uint32_t (*get_argument)(struct pp_hwmgr *hwmgr);
197 int (*send_msg_to_smc)(struct pp_hwmgr *hwmgr, uint16_t msg);
198 int (*send_msg_to_smc_with_parameter)(struct pp_hwmgr *hwmgr,
199 uint16_t msg, uint32_t parameter);
200 int (*download_pptable_settings)(struct pp_hwmgr *hwmgr,
201 void **table);
202 int (*upload_pptable_settings)(struct pp_hwmgr *hwmgr);
203 int (*update_smc_table)(struct pp_hwmgr *hwmgr, uint32_t type);
204 int (*process_firmware_header)(struct pp_hwmgr *hwmgr);
205 int (*update_sclk_threshold)(struct pp_hwmgr *hwmgr);
206 int (*thermal_setup_fan_table)(struct pp_hwmgr *hwmgr);
207 int (*thermal_avfs_enable)(struct pp_hwmgr *hwmgr);
208 int (*init_smc_table)(struct pp_hwmgr *hwmgr);
209 int (*populate_all_graphic_levels)(struct pp_hwmgr *hwmgr);
210 int (*populate_all_memory_levels)(struct pp_hwmgr *hwmgr);
211 int (*initialize_mc_reg_table)(struct pp_hwmgr *hwmgr);
212 uint32_t (*get_offsetof)(uint32_t type, uint32_t member);
213 uint32_t (*get_mac_definition)(uint32_t value);
214 bool (*is_dpm_running)(struct pp_hwmgr *hwmgr);
215 bool (*is_hw_avfs_present)(struct pp_hwmgr *hwmgr);
216 int (*update_dpm_settings)(struct pp_hwmgr *hwmgr, void *profile_setting);
217 int (*smc_table_manager)(struct pp_hwmgr *hwmgr, uint8_t *table, uint16_t table_id, bool rw);
218};
219
220struct pp_hwmgr_func {
221 int (*backend_init)(struct pp_hwmgr *hw_mgr);
222 int (*backend_fini)(struct pp_hwmgr *hw_mgr);
223 int (*asic_setup)(struct pp_hwmgr *hw_mgr);
224 int (*get_power_state_size)(struct pp_hwmgr *hw_mgr);
225
226 int (*apply_state_adjust_rules)(struct pp_hwmgr *hwmgr,
227 struct pp_power_state *prequest_ps,
228 const struct pp_power_state *pcurrent_ps);
229
230 int (*apply_clocks_adjust_rules)(struct pp_hwmgr *hwmgr);
231
232 int (*force_dpm_level)(struct pp_hwmgr *hw_mgr,
233 enum amd_dpm_forced_level level);
234
235 int (*dynamic_state_management_enable)(
236 struct pp_hwmgr *hw_mgr);
237 int (*dynamic_state_management_disable)(
238 struct pp_hwmgr *hw_mgr);
239
240 int (*patch_boot_state)(struct pp_hwmgr *hwmgr,
241 struct pp_hw_power_state *hw_ps);
242
243 int (*get_pp_table_entry)(struct pp_hwmgr *hwmgr,
244 unsigned long, struct pp_power_state *);
245 int (*get_num_of_pp_table_entries)(struct pp_hwmgr *hwmgr);
246 int (*powerdown_uvd)(struct pp_hwmgr *hwmgr);
247 void (*powergate_vce)(struct pp_hwmgr *hwmgr, bool bgate);
248 void (*powergate_uvd)(struct pp_hwmgr *hwmgr, bool bgate);
249 void (*powergate_acp)(struct pp_hwmgr *hwmgr, bool bgate);
250 uint32_t (*get_mclk)(struct pp_hwmgr *hwmgr, bool low);
251 uint32_t (*get_sclk)(struct pp_hwmgr *hwmgr, bool low);
252 int (*power_state_set)(struct pp_hwmgr *hwmgr,
253 const void *state);
254 int (*enable_clock_power_gating)(struct pp_hwmgr *hwmgr);
255 int (*notify_smc_display_config_after_ps_adjustment)(struct pp_hwmgr *hwmgr);
256 int (*pre_display_config_changed)(struct pp_hwmgr *hwmgr);
257 int (*display_config_changed)(struct pp_hwmgr *hwmgr);
258 int (*disable_clock_power_gating)(struct pp_hwmgr *hwmgr);
259 int (*update_clock_gatings)(struct pp_hwmgr *hwmgr,
260 const uint32_t *msg_id);
261 int (*set_max_fan_rpm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm);
262 int (*set_max_fan_pwm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm);
263 int (*stop_thermal_controller)(struct pp_hwmgr *hwmgr);
264 int (*get_fan_speed_info)(struct pp_hwmgr *hwmgr, struct phm_fan_speed_info *fan_speed_info);
265 void (*set_fan_control_mode)(struct pp_hwmgr *hwmgr, uint32_t mode);
266 uint32_t (*get_fan_control_mode)(struct pp_hwmgr *hwmgr);
267 int (*set_fan_speed_percent)(struct pp_hwmgr *hwmgr, uint32_t percent);
268 int (*get_fan_speed_percent)(struct pp_hwmgr *hwmgr, uint32_t *speed);
269 int (*set_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t percent);
270 int (*get_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t *speed);
271 int (*reset_fan_speed_to_default)(struct pp_hwmgr *hwmgr);
272 int (*uninitialize_thermal_controller)(struct pp_hwmgr *hwmgr);
273 int (*register_irq_handlers)(struct pp_hwmgr *hwmgr);
274 bool (*check_smc_update_required_for_display_configuration)(struct pp_hwmgr *hwmgr);
275 int (*check_states_equal)(struct pp_hwmgr *hwmgr,
276 const struct pp_hw_power_state *pstate1,
277 const struct pp_hw_power_state *pstate2,
278 bool *equal);
279 int (*set_cpu_power_state)(struct pp_hwmgr *hwmgr);
280 int (*store_cc6_data)(struct pp_hwmgr *hwmgr, uint32_t separation_time,
281 bool cc6_disable, bool pstate_disable,
282 bool pstate_switch_disable);
283 int (*get_dal_power_level)(struct pp_hwmgr *hwmgr,
284 struct amd_pp_simple_clock_info *info);
285 int (*get_performance_level)(struct pp_hwmgr *, const struct pp_hw_power_state *,
286 PHM_PerformanceLevelDesignation, uint32_t, PHM_PerformanceLevel *);
287 int (*get_current_shallow_sleep_clocks)(struct pp_hwmgr *hwmgr,
288 const struct pp_hw_power_state *state, struct pp_clock_info *clock_info);
289 int (*get_clock_by_type)(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks);
290 int (*get_clock_by_type_with_latency)(struct pp_hwmgr *hwmgr,
291 enum amd_pp_clock_type type,
292 struct pp_clock_levels_with_latency *clocks);
293 int (*get_clock_by_type_with_voltage)(struct pp_hwmgr *hwmgr,
294 enum amd_pp_clock_type type,
295 struct pp_clock_levels_with_voltage *clocks);
296 int (*set_watermarks_for_clocks_ranges)(struct pp_hwmgr *hwmgr, void *clock_ranges);
297 int (*display_clock_voltage_request)(struct pp_hwmgr *hwmgr,
298 struct pp_display_clock_request *clock);
299 int (*get_max_high_clocks)(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks);
300 int (*power_off_asic)(struct pp_hwmgr *hwmgr);
301 int (*force_clock_level)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, uint32_t mask);
302 int (*print_clock_levels)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, char *buf);
303 int (*powergate_gfx)(struct pp_hwmgr *hwmgr, bool enable);
304 int (*get_sclk_od)(struct pp_hwmgr *hwmgr);
305 int (*set_sclk_od)(struct pp_hwmgr *hwmgr, uint32_t value);
306 int (*get_mclk_od)(struct pp_hwmgr *hwmgr);
307 int (*set_mclk_od)(struct pp_hwmgr *hwmgr, uint32_t value);
308 int (*read_sensor)(struct pp_hwmgr *hwmgr, int idx, void *value, int *size);
309 int (*avfs_control)(struct pp_hwmgr *hwmgr, bool enable);
310 int (*disable_smc_firmware_ctf)(struct pp_hwmgr *hwmgr);
311 int (*set_active_display_count)(struct pp_hwmgr *hwmgr, uint32_t count);
312 int (*set_min_deep_sleep_dcefclk)(struct pp_hwmgr *hwmgr, uint32_t clock);
313 int (*start_thermal_controller)(struct pp_hwmgr *hwmgr, struct PP_TemperatureRange *range);
314 int (*notify_cac_buffer_info)(struct pp_hwmgr *hwmgr,
315 uint32_t virtual_addr_low,
316 uint32_t virtual_addr_hi,
317 uint32_t mc_addr_low,
318 uint32_t mc_addr_hi,
319 uint32_t size);
320 int (*update_nbdpm_pstate)(struct pp_hwmgr *hwmgr,
321 bool enable,
322 bool lock);
323 int (*get_thermal_temperature_range)(struct pp_hwmgr *hwmgr,
324 struct PP_TemperatureRange *range);
325 int (*get_power_profile_mode)(struct pp_hwmgr *hwmgr, char *buf);
326 int (*set_power_profile_mode)(struct pp_hwmgr *hwmgr, long *input, uint32_t size);
327 int (*odn_edit_dpm_table)(struct pp_hwmgr *hwmgr,
328 enum PP_OD_DPM_TABLE_COMMAND type,
329 long *input, uint32_t size);
330 int (*set_power_limit)(struct pp_hwmgr *hwmgr, uint32_t n);
331 int (*powergate_mmhub)(struct pp_hwmgr *hwmgr);
332 int (*smus_notify_pwe)(struct pp_hwmgr *hwmgr);
333 int (*powergate_sdma)(struct pp_hwmgr *hwmgr, bool bgate);
334 int (*enable_mgpu_fan_boost)(struct pp_hwmgr *hwmgr);
335 int (*set_hard_min_dcefclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock);
336 int (*set_hard_min_fclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock);
337};
338
339struct pp_table_func {
340 int (*pptable_init)(struct pp_hwmgr *hw_mgr);
341 int (*pptable_fini)(struct pp_hwmgr *hw_mgr);
342 int (*pptable_get_number_of_vce_state_table_entries)(struct pp_hwmgr *hw_mgr);
343 int (*pptable_get_vce_state_table_entry)(
344 struct pp_hwmgr *hwmgr,
345 unsigned long i,
346 struct amd_vce_state *vce_state,
347 void **clock_info,
348 unsigned long *flag);
349};
350
351union phm_cac_leakage_record {
352 struct {
353 uint16_t Vddc;
354 uint32_t Leakage;
355 };
356 struct {
357 uint16_t Vddc1;
358 uint16_t Vddc2;
359 uint16_t Vddc3;
360 };
361};
362
363struct phm_cac_leakage_table {
364 uint32_t count;
365 union phm_cac_leakage_record entries[1];
366};
367
368struct phm_samu_clock_voltage_dependency_record {
369 uint32_t samclk;
370 uint32_t v;
371};
372
373
374struct phm_samu_clock_voltage_dependency_table {
375 uint8_t count;
376 struct phm_samu_clock_voltage_dependency_record entries[1];
377};
378
379struct phm_cac_tdp_table {
380 uint16_t usTDP;
381 uint16_t usConfigurableTDP;
382 uint16_t usTDC;
383 uint16_t usBatteryPowerLimit;
384 uint16_t usSmallPowerLimit;
385 uint16_t usLowCACLeakage;
386 uint16_t usHighCACLeakage;
387 uint16_t usMaximumPowerDeliveryLimit;
388 uint16_t usEDCLimit;
389 uint16_t usOperatingTempMinLimit;
390 uint16_t usOperatingTempMaxLimit;
391 uint16_t usOperatingTempStep;
392 uint16_t usOperatingTempHyst;
393 uint16_t usDefaultTargetOperatingTemp;
394 uint16_t usTargetOperatingTemp;
395 uint16_t usPowerTuneDataSetID;
396 uint16_t usSoftwareShutdownTemp;
397 uint16_t usClockStretchAmount;
398 uint16_t usTemperatureLimitHotspot;
399 uint16_t usTemperatureLimitLiquid1;
400 uint16_t usTemperatureLimitLiquid2;
401 uint16_t usTemperatureLimitVrVddc;
402 uint16_t usTemperatureLimitVrMvdd;
403 uint16_t usTemperatureLimitPlx;
404 uint8_t ucLiquid1_I2C_address;
405 uint8_t ucLiquid2_I2C_address;
406 uint8_t ucLiquid_I2C_Line;
407 uint8_t ucVr_I2C_address;
408 uint8_t ucVr_I2C_Line;
409 uint8_t ucPlx_I2C_address;
410 uint8_t ucPlx_I2C_Line;
411 uint32_t usBoostPowerLimit;
412 uint8_t ucCKS_LDO_REFSEL;
413};
414
415struct phm_tdp_table {
416 uint16_t usTDP;
417 uint16_t usConfigurableTDP;
418 uint16_t usTDC;
419 uint16_t usBatteryPowerLimit;
420 uint16_t usSmallPowerLimit;
421 uint16_t usLowCACLeakage;
422 uint16_t usHighCACLeakage;
423 uint16_t usMaximumPowerDeliveryLimit;
424 uint16_t usEDCLimit;
425 uint16_t usOperatingTempMinLimit;
426 uint16_t usOperatingTempMaxLimit;
427 uint16_t usOperatingTempStep;
428 uint16_t usOperatingTempHyst;
429 uint16_t usDefaultTargetOperatingTemp;
430 uint16_t usTargetOperatingTemp;
431 uint16_t usPowerTuneDataSetID;
432 uint16_t usSoftwareShutdownTemp;
433 uint16_t usClockStretchAmount;
434 uint16_t usTemperatureLimitTedge;
435 uint16_t usTemperatureLimitHotspot;
436 uint16_t usTemperatureLimitLiquid1;
437 uint16_t usTemperatureLimitLiquid2;
438 uint16_t usTemperatureLimitHBM;
439 uint16_t usTemperatureLimitVrVddc;
440 uint16_t usTemperatureLimitVrMvdd;
441 uint16_t usTemperatureLimitPlx;
442 uint8_t ucLiquid1_I2C_address;
443 uint8_t ucLiquid2_I2C_address;
444 uint8_t ucLiquid_I2C_Line;
445 uint8_t ucVr_I2C_address;
446 uint8_t ucVr_I2C_Line;
447 uint8_t ucPlx_I2C_address;
448 uint8_t ucPlx_I2C_Line;
449 uint8_t ucLiquid_I2C_LineSDA;
450 uint8_t ucVr_I2C_LineSDA;
451 uint8_t ucPlx_I2C_LineSDA;
452 uint32_t usBoostPowerLimit;
453 uint16_t usBoostStartTemperature;
454 uint16_t usBoostStopTemperature;
455 uint32_t ulBoostClock;
456};
457
458struct phm_ppm_table {
459 uint8_t ppm_design;
460 uint16_t cpu_core_number;
461 uint32_t platform_tdp;
462 uint32_t small_ac_platform_tdp;
463 uint32_t platform_tdc;
464 uint32_t small_ac_platform_tdc;
465 uint32_t apu_tdp;
466 uint32_t dgpu_tdp;
467 uint32_t dgpu_ulv_power;
468 uint32_t tj_max;
469};
470
471struct phm_vq_budgeting_record {
472 uint32_t ulCUs;
473 uint32_t ulSustainableSOCPowerLimitLow;
474 uint32_t ulSustainableSOCPowerLimitHigh;
475 uint32_t ulMinSclkLow;
476 uint32_t ulMinSclkHigh;
477 uint8_t ucDispConfig;
478 uint32_t ulDClk;
479 uint32_t ulEClk;
480 uint32_t ulSustainableSclk;
481 uint32_t ulSustainableCUs;
482};
483
484struct phm_vq_budgeting_table {
485 uint8_t numEntries;
486 struct phm_vq_budgeting_record entries[1];
487};
488
489struct phm_clock_and_voltage_limits {
490 uint32_t sclk;
491 uint32_t mclk;
492 uint32_t gfxclk;
493 uint16_t vddc;
494 uint16_t vddci;
495 uint16_t vddgfx;
496 uint16_t vddmem;
497};
498
499
500
501struct phm_ppt_v1_information {
502 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk;
503 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_mclk;
504 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_socclk;
505 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dcefclk;
506 struct phm_clock_array *valid_sclk_values;
507 struct phm_clock_array *valid_mclk_values;
508 struct phm_clock_array *valid_socclk_values;
509 struct phm_clock_array *valid_dcefclk_values;
510 struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
511 struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
512 struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl;
513 struct phm_ppm_table *ppm_parameter_table;
514 struct phm_cac_tdp_table *cac_dtp_table;
515 struct phm_tdp_table *tdp_table;
516 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_dep_table;
517 struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
518 struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table;
519 struct phm_ppt_v1_voltage_lookup_table *vddmem_lookup_table;
520 struct phm_ppt_v1_pcie_table *pcie_table;
521 struct phm_ppt_v1_gpio_table *gpio_table;
522 uint16_t us_ulv_voltage_offset;
523 uint16_t us_ulv_smnclk_did;
524 uint16_t us_ulv_mp1clk_did;
525 uint16_t us_ulv_gfxclk_bypass;
526 uint16_t us_gfxclk_slew_rate;
527 uint16_t us_min_gfxclk_freq_limit;
528};
529
530struct phm_ppt_v2_information {
531 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk;
532 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_mclk;
533 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_socclk;
534 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dcefclk;
535 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_pixclk;
536 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dispclk;
537 struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_phyclk;
538 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_dep_table;
539
540 struct phm_clock_voltage_dependency_table *vddc_dep_on_dalpwrl;
541
542 struct phm_clock_array *valid_sclk_values;
543 struct phm_clock_array *valid_mclk_values;
544 struct phm_clock_array *valid_socclk_values;
545 struct phm_clock_array *valid_dcefclk_values;
546
547 struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
548 struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
549
550 struct phm_ppm_table *ppm_parameter_table;
551 struct phm_cac_tdp_table *cac_dtp_table;
552 struct phm_tdp_table *tdp_table;
553
554 struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
555 struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table;
556 struct phm_ppt_v1_voltage_lookup_table *vddmem_lookup_table;
557 struct phm_ppt_v1_voltage_lookup_table *vddci_lookup_table;
558
559 struct phm_ppt_v1_pcie_table *pcie_table;
560
561 uint16_t us_ulv_voltage_offset;
562 uint16_t us_ulv_smnclk_did;
563 uint16_t us_ulv_mp1clk_did;
564 uint16_t us_ulv_gfxclk_bypass;
565 uint16_t us_gfxclk_slew_rate;
566 uint16_t us_min_gfxclk_freq_limit;
567
568 uint8_t uc_gfx_dpm_voltage_mode;
569 uint8_t uc_soc_dpm_voltage_mode;
570 uint8_t uc_uclk_dpm_voltage_mode;
571 uint8_t uc_uvd_dpm_voltage_mode;
572 uint8_t uc_vce_dpm_voltage_mode;
573 uint8_t uc_mp0_dpm_voltage_mode;
574 uint8_t uc_dcef_dpm_voltage_mode;
575};
576
577struct phm_ppt_v3_information
578{
579 uint8_t uc_thermal_controller_type;
580
581 uint16_t us_small_power_limit1;
582 uint16_t us_small_power_limit2;
583 uint16_t us_boost_power_limit;
584
585 uint16_t us_od_turbo_power_limit;
586 uint16_t us_od_powersave_power_limit;
587 uint16_t us_software_shutdown_temp;
588
589 uint32_t *power_saving_clock_max;
590 uint32_t *power_saving_clock_min;
591
592 uint8_t *od_feature_capabilities;
593 uint32_t *od_settings_max;
594 uint32_t *od_settings_min;
595
596 void *smc_pptable;
597};
598
599struct phm_dynamic_state_info {
600 struct phm_clock_voltage_dependency_table *vddc_dependency_on_sclk;
601 struct phm_clock_voltage_dependency_table *vddci_dependency_on_mclk;
602 struct phm_clock_voltage_dependency_table *vddc_dependency_on_mclk;
603 struct phm_clock_voltage_dependency_table *mvdd_dependency_on_mclk;
604 struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl;
605 struct phm_clock_array *valid_sclk_values;
606 struct phm_clock_array *valid_mclk_values;
607 struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
608 struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
609 uint32_t mclk_sclk_ratio;
610 uint32_t sclk_mclk_delta;
611 uint32_t vddc_vddci_delta;
612 uint32_t min_vddc_for_pcie_gen2;
613 struct phm_cac_leakage_table *cac_leakage_table;
614 struct phm_phase_shedding_limits_table *vddc_phase_shed_limits_table;
615
616 struct phm_vce_clock_voltage_dependency_table
617 *vce_clock_voltage_dependency_table;
618 struct phm_uvd_clock_voltage_dependency_table
619 *uvd_clock_voltage_dependency_table;
620 struct phm_acp_clock_voltage_dependency_table
621 *acp_clock_voltage_dependency_table;
622 struct phm_samu_clock_voltage_dependency_table
623 *samu_clock_voltage_dependency_table;
624
625 struct phm_ppm_table *ppm_parameter_table;
626 struct phm_cac_tdp_table *cac_dtp_table;
627 struct phm_clock_voltage_dependency_table *vdd_gfx_dependency_on_sclk;
628};
629
630struct pp_fan_info {
631 bool bNoFan;
632 uint8_t ucTachometerPulsesPerRevolution;
633 uint32_t ulMinRPM;
634 uint32_t ulMaxRPM;
635};
636
637struct pp_advance_fan_control_parameters {
638 uint16_t usTMin;
639 uint16_t usTMed;
640 uint16_t usTHigh;
641 uint16_t usPWMMin;
642 uint16_t usPWMMed;
643 uint16_t usPWMHigh;
644 uint8_t ucTHyst;
645 uint32_t ulCycleDelay;
646 uint16_t usTMax;
647 uint8_t ucFanControlMode;
648 uint16_t usFanPWMMinLimit;
649 uint16_t usFanPWMMaxLimit;
650 uint16_t usFanPWMStep;
651 uint16_t usDefaultMaxFanPWM;
652 uint16_t usFanOutputSensitivity;
653 uint16_t usDefaultFanOutputSensitivity;
654 uint16_t usMaxFanPWM;
655 uint16_t usFanRPMMinLimit;
656 uint16_t usFanRPMMaxLimit;
657 uint16_t usFanRPMStep;
658 uint16_t usDefaultMaxFanRPM;
659 uint16_t usMaxFanRPM;
660 uint16_t usFanCurrentLow;
661 uint16_t usFanCurrentHigh;
662 uint16_t usFanRPMLow;
663 uint16_t usFanRPMHigh;
664 uint32_t ulMinFanSCLKAcousticLimit;
665 uint8_t ucTargetTemperature;
666 uint8_t ucMinimumPWMLimit;
667 uint16_t usFanGainEdge;
668 uint16_t usFanGainHotspot;
669 uint16_t usFanGainLiquid;
670 uint16_t usFanGainVrVddc;
671 uint16_t usFanGainVrMvdd;
672 uint16_t usFanGainPlx;
673 uint16_t usFanGainHbm;
674 uint8_t ucEnableZeroRPM;
675 uint8_t ucFanStopTemperature;
676 uint8_t ucFanStartTemperature;
677 uint32_t ulMaxFanSCLKAcousticLimit;
678 uint32_t ulTargetGfxClk;
679 uint16_t usZeroRPMStartTemperature;
680 uint16_t usZeroRPMStopTemperature;
681};
682
683struct pp_thermal_controller_info {
684 uint8_t ucType;
685 uint8_t ucI2cLine;
686 uint8_t ucI2cAddress;
687 struct pp_fan_info fanInfo;
688 struct pp_advance_fan_control_parameters advanceFanControlParameters;
689};
690
691struct phm_microcode_version_info {
692 uint32_t SMC;
693 uint32_t DMCU;
694 uint32_t MC;
695 uint32_t NB;
696};
697
698enum PP_TABLE_VERSION {
699 PP_TABLE_V0 = 0,
700 PP_TABLE_V1,
701 PP_TABLE_V2,
702 PP_TABLE_MAX
703};
704
705
706
707
708#define Workload_Policy_Max 6
709
710struct pp_hwmgr {
711 void *adev;
712 uint32_t chip_family;
713 uint32_t chip_id;
714 uint32_t smu_version;
715 bool not_vf;
716 bool pm_en;
717 struct mutex smu_lock;
718
719 uint32_t pp_table_version;
720 void *device;
721 struct pp_smumgr *smumgr;
722 const void *soft_pp_table;
723 uint32_t soft_pp_table_size;
724 void *hardcode_pp_table;
725 bool need_pp_table_upload;
726
727 struct amd_vce_state vce_states[AMD_MAX_VCE_LEVELS];
728 uint32_t num_vce_state_tables;
729
730 enum amd_dpm_forced_level dpm_level;
731 enum amd_dpm_forced_level saved_dpm_level;
732 enum amd_dpm_forced_level request_dpm_level;
733 uint32_t usec_timeout;
734 void *pptable;
735 struct phm_platform_descriptor platform_descriptor;
736 void *backend;
737
738 void *smu_backend;
739 const struct pp_smumgr_func *smumgr_funcs;
740 bool is_kicker;
741
742 enum PP_DAL_POWERLEVEL dal_power_level;
743 struct phm_dynamic_state_info dyn_state;
744 const struct pp_hwmgr_func *hwmgr_func;
745 const struct pp_table_func *pptable_func;
746
747 struct pp_power_state *ps;
748 uint32_t num_ps;
749 struct pp_thermal_controller_info thermal_controller;
750 bool fan_ctrl_is_in_default_mode;
751 uint32_t fan_ctrl_default_mode;
752 bool fan_ctrl_enabled;
753 uint32_t tmin;
754 struct phm_microcode_version_info microcode_version_info;
755 uint32_t ps_size;
756 struct pp_power_state *current_ps;
757 struct pp_power_state *request_ps;
758 struct pp_power_state *boot_ps;
759 struct pp_power_state *uvd_ps;
760 const struct amd_pp_display_configuration *display_config;
761 uint32_t feature_mask;
762 bool avfs_supported;
763
764 bool en_umd_pstate;
765 uint32_t power_profile_mode;
766 uint32_t default_power_profile_mode;
767 uint32_t pstate_sclk;
768 uint32_t pstate_mclk;
769 bool od_enabled;
770 uint32_t power_limit;
771 uint32_t default_power_limit;
772 uint32_t workload_mask;
773 uint32_t workload_prority[Workload_Policy_Max];
774 uint32_t workload_setting[Workload_Policy_Max];
775};
776
777int hwmgr_early_init(struct pp_hwmgr *hwmgr);
778int hwmgr_sw_init(struct pp_hwmgr *hwmgr);
779int hwmgr_sw_fini(struct pp_hwmgr *hwmgr);
780int hwmgr_hw_init(struct pp_hwmgr *hwmgr);
781int hwmgr_hw_fini(struct pp_hwmgr *hwmgr);
782int hwmgr_suspend(struct pp_hwmgr *hwmgr);
783int hwmgr_resume(struct pp_hwmgr *hwmgr);
784
785int hwmgr_handle_task(struct pp_hwmgr *hwmgr,
786 enum amd_pp_task task_id,
787 enum amd_pm_state_type *user_state);
788
789
790#define PHM_ENTIRE_REGISTER_MASK 0xFFFFFFFFU
791
792
793#endif
794
