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13#ifndef _ANALOGIX_DP_CORE_H
14#define _ANALOGIX_DP_CORE_H
15
16#include <drm/drm_crtc.h>
17#include <drm/drm_dp_helper.h>
18
19#define DP_TIMEOUT_LOOP_COUNT 100
20#define MAX_CR_LOOP 5
21#define MAX_EQ_LOOP 5
22#define MAX_PLL_LOCK_LOOP 5
23
24
25#define DP_TIMEOUT_TRAINING_US 22000
26#define DP_TIMEOUT_PSR_LOOP_MS 300
27
28
29#define DPCD_ENHANCED_FRAME_CAP(x) (((x) >> 7) & 0x1)
30#define DPCD_MAX_LANE_COUNT(x) ((x) & 0x1f)
31
32
33#define DPCD_LANE_COUNT_SET(x) ((x) & 0x1f)
34
35
36#define DPCD_PRE_EMPHASIS_SET(x) (((x) & 0x3) << 3)
37#define DPCD_PRE_EMPHASIS_GET(x) (((x) >> 3) & 0x3)
38#define DPCD_VOLTAGE_SWING_SET(x) (((x) & 0x3) << 0)
39#define DPCD_VOLTAGE_SWING_GET(x) (((x) >> 0) & 0x3)
40
41enum link_lane_count_type {
42 LANE_COUNT1 = 1,
43 LANE_COUNT2 = 2,
44 LANE_COUNT4 = 4
45};
46
47enum link_training_state {
48 START,
49 CLOCK_RECOVERY,
50 EQUALIZER_TRAINING,
51 FINISHED,
52 FAILED
53};
54
55enum voltage_swing_level {
56 VOLTAGE_LEVEL_0,
57 VOLTAGE_LEVEL_1,
58 VOLTAGE_LEVEL_2,
59 VOLTAGE_LEVEL_3,
60};
61
62enum pre_emphasis_level {
63 PRE_EMPHASIS_LEVEL_0,
64 PRE_EMPHASIS_LEVEL_1,
65 PRE_EMPHASIS_LEVEL_2,
66 PRE_EMPHASIS_LEVEL_3,
67};
68
69enum pattern_set {
70 PRBS7,
71 D10_2,
72 TRAINING_PTN1,
73 TRAINING_PTN2,
74 DP_NONE
75};
76
77enum color_space {
78 COLOR_RGB,
79 COLOR_YCBCR422,
80 COLOR_YCBCR444
81};
82
83enum color_depth {
84 COLOR_6,
85 COLOR_8,
86 COLOR_10,
87 COLOR_12
88};
89
90enum color_coefficient {
91 COLOR_YCBCR601,
92 COLOR_YCBCR709
93};
94
95enum dynamic_range {
96 VESA,
97 CEA
98};
99
100enum pll_status {
101 PLL_UNLOCKED,
102 PLL_LOCKED
103};
104
105enum clock_recovery_m_value_type {
106 CALCULATED_M,
107 REGISTER_M
108};
109
110enum video_timing_recognition_type {
111 VIDEO_TIMING_FROM_CAPTURE,
112 VIDEO_TIMING_FROM_REGISTER
113};
114
115enum analog_power_block {
116 AUX_BLOCK,
117 CH0_BLOCK,
118 CH1_BLOCK,
119 CH2_BLOCK,
120 CH3_BLOCK,
121 ANALOG_TOTAL,
122 POWER_ALL
123};
124
125enum dp_irq_type {
126 DP_IRQ_TYPE_HP_CABLE_IN = BIT(0),
127 DP_IRQ_TYPE_HP_CABLE_OUT = BIT(1),
128 DP_IRQ_TYPE_HP_CHANGE = BIT(2),
129 DP_IRQ_TYPE_UNKNOWN = BIT(3),
130};
131
132struct video_info {
133 char *name;
134
135 bool h_sync_polarity;
136 bool v_sync_polarity;
137 bool interlaced;
138
139 enum color_space color_space;
140 enum dynamic_range dynamic_range;
141 enum color_coefficient ycbcr_coeff;
142 enum color_depth color_depth;
143
144 int max_link_rate;
145 enum link_lane_count_type max_lane_count;
146};
147
148struct link_train {
149 int eq_loop;
150 int cr_loop[4];
151
152 u8 link_rate;
153 u8 lane_count;
154 u8 training_lane[4];
155
156 enum link_training_state lt_state;
157};
158
159struct analogix_dp_device {
160 struct drm_encoder *encoder;
161 struct device *dev;
162 struct drm_device *drm_dev;
163 struct drm_connector connector;
164 struct drm_bridge *bridge;
165 struct drm_dp_aux aux;
166 struct clk *clock;
167 unsigned int irq;
168 void __iomem *reg_base;
169
170 struct video_info video_info;
171 struct link_train link_train;
172 struct phy *phy;
173 int dpms_mode;
174 int hpd_gpio;
175 bool force_hpd;
176 bool psr_enable;
177 bool fast_train_enable;
178
179 struct mutex panel_lock;
180 bool panel_is_modeset;
181
182 struct analogix_dp_plat_data *plat_data;
183};
184
185
186void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable);
187void analogix_dp_stop_video(struct analogix_dp_device *dp);
188void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable);
189void analogix_dp_init_analog_param(struct analogix_dp_device *dp);
190void analogix_dp_init_interrupt(struct analogix_dp_device *dp);
191void analogix_dp_reset(struct analogix_dp_device *dp);
192void analogix_dp_swreset(struct analogix_dp_device *dp);
193void analogix_dp_config_interrupt(struct analogix_dp_device *dp);
194void analogix_dp_mute_hpd_interrupt(struct analogix_dp_device *dp);
195void analogix_dp_unmute_hpd_interrupt(struct analogix_dp_device *dp);
196enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp);
197void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable);
198void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
199 enum analog_power_block block,
200 bool enable);
201int analogix_dp_init_analog_func(struct analogix_dp_device *dp);
202void analogix_dp_init_hpd(struct analogix_dp_device *dp);
203void analogix_dp_force_hpd(struct analogix_dp_device *dp);
204enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp);
205void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp);
206void analogix_dp_reset_aux(struct analogix_dp_device *dp);
207void analogix_dp_init_aux(struct analogix_dp_device *dp);
208int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp);
209void analogix_dp_enable_sw_function(struct analogix_dp_device *dp);
210void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype);
211void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype);
212void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count);
213void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count);
214void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp,
215 bool enable);
216void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
217 enum pattern_set pattern);
218void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp,
219 u32 level);
220void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp,
221 u32 level);
222void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp,
223 u32 level);
224void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp,
225 u32 level);
226void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp,
227 u32 training_lane);
228void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp,
229 u32 training_lane);
230void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp,
231 u32 training_lane);
232void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp,
233 u32 training_lane);
234u32 analogix_dp_get_lane0_link_training(struct analogix_dp_device *dp);
235u32 analogix_dp_get_lane1_link_training(struct analogix_dp_device *dp);
236u32 analogix_dp_get_lane2_link_training(struct analogix_dp_device *dp);
237u32 analogix_dp_get_lane3_link_training(struct analogix_dp_device *dp);
238void analogix_dp_reset_macro(struct analogix_dp_device *dp);
239void analogix_dp_init_video(struct analogix_dp_device *dp);
240
241void analogix_dp_set_video_color_format(struct analogix_dp_device *dp);
242int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp);
243void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp,
244 enum clock_recovery_m_value_type type,
245 u32 m_value,
246 u32 n_value);
247void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type);
248void analogix_dp_enable_video_master(struct analogix_dp_device *dp,
249 bool enable);
250void analogix_dp_start_video(struct analogix_dp_device *dp);
251int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp);
252void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp);
253void analogix_dp_enable_scrambling(struct analogix_dp_device *dp);
254void analogix_dp_disable_scrambling(struct analogix_dp_device *dp);
255void analogix_dp_enable_psr_crc(struct analogix_dp_device *dp);
256int analogix_dp_send_psr_spd(struct analogix_dp_device *dp,
257 struct edp_vsc_psr *vsc, bool blocking);
258ssize_t analogix_dp_transfer(struct analogix_dp_device *dp,
259 struct drm_dp_aux_msg *msg);
260
261#endif
262
