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21#include <linux/i2c.h>
22#include <linux/pm_runtime.h>
23
24#include <drm/drmP.h>
25#include "psb_intel_reg.h"
26#include "gma_display.h"
27#include "framebuffer.h"
28#include "mdfld_output.h"
29#include "mdfld_dsi_output.h"
30
31
32static int ksel = KSEL_CRYSTAL_19;
33
34struct psb_intel_range_t {
35 int min, max;
36};
37
38struct mrst_limit_t {
39 struct psb_intel_range_t dot, m, p1;
40};
41
42struct mrst_clock_t {
43
44 int dot;
45 int m;
46 int p1;
47};
48
49#define COUNT_MAX 0x10000000
50
51void mdfldWaitForPipeDisable(struct drm_device *dev, int pipe)
52{
53 struct drm_psb_private *dev_priv = dev->dev_private;
54 const struct psb_offset *map = &dev_priv->regmap[pipe];
55 int count, temp;
56
57 switch (pipe) {
58 case 0:
59 case 1:
60 case 2:
61 break;
62 default:
63 DRM_ERROR("Illegal Pipe Number.\n");
64 return;
65 }
66
67
68 gma_wait_for_vblank(dev);
69 return;
70
71
72 for (count = 0; count < COUNT_MAX; count++) {
73 temp = REG_READ(map->conf);
74 if ((temp & PIPEACONF_PIPE_STATE) == 0)
75 break;
76 }
77}
78
79void mdfldWaitForPipeEnable(struct drm_device *dev, int pipe)
80{
81 struct drm_psb_private *dev_priv = dev->dev_private;
82 const struct psb_offset *map = &dev_priv->regmap[pipe];
83 int count, temp;
84
85 switch (pipe) {
86 case 0:
87 case 1:
88 case 2:
89 break;
90 default:
91 DRM_ERROR("Illegal Pipe Number.\n");
92 return;
93 }
94
95
96 gma_wait_for_vblank(dev);
97 return;
98
99
100 for (count = 0; count < COUNT_MAX; count++) {
101 temp = REG_READ(map->conf);
102 if (temp & PIPEACONF_PIPE_STATE)
103 break;
104 }
105}
106
107
108
109
110
111static int psb_intel_panel_fitter_pipe(struct drm_device *dev)
112{
113 u32 pfit_control;
114
115 pfit_control = REG_READ(PFIT_CONTROL);
116
117
118 if ((pfit_control & PFIT_ENABLE) == 0)
119 return -1;
120
121
122 return (pfit_control >> 29) & 0x3;
123}
124
125static struct drm_device globle_dev;
126
127void mdfld__intel_plane_set_alpha(int enable)
128{
129 struct drm_device *dev = &globle_dev;
130 int dspcntr_reg = DSPACNTR;
131 u32 dspcntr;
132
133 dspcntr = REG_READ(dspcntr_reg);
134
135 if (enable) {
136 dspcntr &= ~DISPPLANE_32BPP_NO_ALPHA;
137 dspcntr |= DISPPLANE_32BPP;
138 } else {
139 dspcntr &= ~DISPPLANE_32BPP;
140 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
141 }
142
143 REG_WRITE(dspcntr_reg, dspcntr);
144}
145
146static int check_fb(struct drm_framebuffer *fb)
147{
148 if (!fb)
149 return 0;
150
151 switch (fb->format->cpp[0] * 8) {
152 case 8:
153 case 16:
154 case 24:
155 case 32:
156 return 0;
157 default:
158 DRM_ERROR("Unknown color depth\n");
159 return -EINVAL;
160 }
161}
162
163static int mdfld__intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
164 struct drm_framebuffer *old_fb)
165{
166 struct drm_device *dev = crtc->dev;
167 struct drm_psb_private *dev_priv = dev->dev_private;
168 struct drm_framebuffer *fb = crtc->primary->fb;
169 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
170 int pipe = gma_crtc->pipe;
171 const struct psb_offset *map = &dev_priv->regmap[pipe];
172 unsigned long start, offset;
173 u32 dspcntr;
174 int ret;
175
176 memcpy(&globle_dev, dev, sizeof(struct drm_device));
177
178 dev_dbg(dev->dev, "pipe = 0x%x.\n", pipe);
179
180
181 if (!fb) {
182 dev_dbg(dev->dev, "No FB bound\n");
183 return 0;
184 }
185
186 ret = check_fb(fb);
187 if (ret)
188 return ret;
189
190 if (pipe > 2) {
191 DRM_ERROR("Illegal Pipe Number.\n");
192 return -EINVAL;
193 }
194
195 if (!gma_power_begin(dev, true))
196 return 0;
197
198 start = to_gtt_range(fb->obj[0])->offset;
199 offset = y * fb->pitches[0] + x * fb->format->cpp[0];
200
201 REG_WRITE(map->stride, fb->pitches[0]);
202 dspcntr = REG_READ(map->cntr);
203 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
204
205 switch (fb->format->cpp[0] * 8) {
206 case 8:
207 dspcntr |= DISPPLANE_8BPP;
208 break;
209 case 16:
210 if (fb->format->depth == 15)
211 dspcntr |= DISPPLANE_15_16BPP;
212 else
213 dspcntr |= DISPPLANE_16BPP;
214 break;
215 case 24:
216 case 32:
217 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
218 break;
219 }
220 REG_WRITE(map->cntr, dspcntr);
221
222 dev_dbg(dev->dev, "Writing base %08lX %08lX %d %d\n",
223 start, offset, x, y);
224 REG_WRITE(map->linoff, offset);
225 REG_READ(map->linoff);
226 REG_WRITE(map->surf, start);
227 REG_READ(map->surf);
228
229 gma_power_end(dev);
230
231 return 0;
232}
233
234
235
236
237
238void mdfld_disable_crtc(struct drm_device *dev, int pipe)
239{
240 struct drm_psb_private *dev_priv = dev->dev_private;
241 const struct psb_offset *map = &dev_priv->regmap[pipe];
242 u32 temp;
243
244 dev_dbg(dev->dev, "pipe = %d\n", pipe);
245
246
247 if (pipe != 1)
248 mdfld_dsi_gen_fifo_ready(dev, MIPI_GEN_FIFO_STAT_REG(pipe),
249 HS_CTRL_FIFO_EMPTY | HS_DATA_FIFO_EMPTY);
250
251
252 temp = REG_READ(map->cntr);
253 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
254 REG_WRITE(map->cntr,
255 temp & ~DISPLAY_PLANE_ENABLE);
256
257 REG_WRITE(map->base, REG_READ(map->base));
258 REG_READ(map->base);
259 }
260
261
262
263
264 temp = REG_READ(map->conf);
265 if ((temp & PIPEACONF_ENABLE) != 0) {
266 temp &= ~PIPEACONF_ENABLE;
267 temp |= PIPECONF_PLANE_OFF | PIPECONF_CURSOR_OFF;
268 REG_WRITE(map->conf, temp);
269 REG_READ(map->conf);
270
271
272 mdfldWaitForPipeDisable(dev, pipe);
273 }
274
275 temp = REG_READ(map->dpll);
276 if (temp & DPLL_VCO_ENABLE) {
277 if ((pipe != 1 &&
278 !((REG_READ(PIPEACONF) | REG_READ(PIPECCONF))
279 & PIPEACONF_ENABLE)) || pipe == 1) {
280 temp &= ~(DPLL_VCO_ENABLE);
281 REG_WRITE(map->dpll, temp);
282 REG_READ(map->dpll);
283
284
285 udelay(500);
286
287 if (!(temp & MDFLD_PWR_GATE_EN)) {
288
289 REG_WRITE(map->dpll, temp | MDFLD_PWR_GATE_EN);
290
291 udelay(5000);
292 }
293 }
294 }
295
296}
297
298
299
300
301
302
303
304static void mdfld_crtc_dpms(struct drm_crtc *crtc, int mode)
305{
306 struct drm_device *dev = crtc->dev;
307 struct drm_psb_private *dev_priv = dev->dev_private;
308 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
309 int pipe = gma_crtc->pipe;
310 const struct psb_offset *map = &dev_priv->regmap[pipe];
311 u32 pipeconf = dev_priv->pipeconf[pipe];
312 u32 temp;
313 int timeout = 0;
314
315 dev_dbg(dev->dev, "mode = %d, pipe = %d\n", mode, pipe);
316
317
318
319
320 if (!gma_power_begin(dev, true))
321 return;
322
323
324
325
326 switch (mode) {
327 case DRM_MODE_DPMS_ON:
328 case DRM_MODE_DPMS_STANDBY:
329 case DRM_MODE_DPMS_SUSPEND:
330
331 temp = REG_READ(map->dpll);
332
333 if ((temp & DPLL_VCO_ENABLE) == 0) {
334
335
336 if (temp & MDFLD_PWR_GATE_EN) {
337 temp &= ~MDFLD_PWR_GATE_EN;
338 REG_WRITE(map->dpll, temp);
339
340 udelay(500);
341 }
342
343 REG_WRITE(map->dpll, temp);
344 REG_READ(map->dpll);
345
346 udelay(500);
347
348 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);
349 REG_READ(map->dpll);
350
351
352
353
354
355
356 while ((pipe != 2) && (timeout < 20000) &&
357 !(REG_READ(map->conf) & PIPECONF_DSIPLL_LOCK)) {
358 udelay(150);
359 timeout++;
360 }
361 }
362
363
364 temp = REG_READ(map->cntr);
365 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
366 REG_WRITE(map->cntr,
367 temp | DISPLAY_PLANE_ENABLE);
368
369 REG_WRITE(map->base, REG_READ(map->base));
370 }
371
372
373 temp = REG_READ(map->conf);
374 if ((temp & PIPEACONF_ENABLE) == 0) {
375 REG_WRITE(map->conf, pipeconf);
376
377
378 mdfldWaitForPipeEnable(dev, pipe);
379 }
380
381
382
383 if (pipe == 0 || pipe == 2) {
384 REG_WRITE(map->status, REG_READ(map->status));
385 msleep(100);
386 if (PIPE_VBLANK_STATUS & REG_READ(map->status))
387 dev_dbg(dev->dev, "OK");
388 else {
389 dev_dbg(dev->dev, "STUCK!!!!");
390
391 temp = REG_READ(map->cntr);
392 REG_WRITE(map->cntr,
393 temp & ~DISPLAY_PLANE_ENABLE);
394 REG_WRITE(map->base, REG_READ(map->base));
395
396 REG_WRITE(0xb048, 1);
397 msleep(100);
398 temp = REG_READ(map->conf);
399 temp &= ~PIPEACONF_ENABLE;
400 REG_WRITE(map->conf, temp);
401 msleep(100);
402 REG_WRITE(MIPI_DEVICE_READY_REG(pipe), 0);
403 msleep(100);
404 REG_WRITE(0xb004, REG_READ(0xb004));
405
406 REG_WRITE(MIPI_DEVICE_READY_REG(pipe), 1);
407 temp = REG_READ(map->cntr);
408 REG_WRITE(map->cntr,
409 temp | DISPLAY_PLANE_ENABLE);
410 REG_WRITE(map->base, REG_READ(map->base));
411
412 REG_WRITE(0xb048, 2);
413 msleep(100);
414 temp = REG_READ(map->conf);
415 temp |= PIPEACONF_ENABLE;
416 REG_WRITE(map->conf, temp);
417 }
418 }
419
420 gma_crtc_load_lut(crtc);
421
422
423
424
425
426 break;
427 case DRM_MODE_DPMS_OFF:
428
429
430
431 if (pipe != 1)
432 mdfld_dsi_gen_fifo_ready(dev,
433 MIPI_GEN_FIFO_STAT_REG(pipe),
434 HS_CTRL_FIFO_EMPTY | HS_DATA_FIFO_EMPTY);
435
436
437 REG_WRITE(VGACNTRL, VGA_DISP_DISABLE);
438
439
440 temp = REG_READ(map->cntr);
441 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
442 REG_WRITE(map->cntr,
443 temp & ~DISPLAY_PLANE_ENABLE);
444
445 REG_WRITE(map->base, REG_READ(map->base));
446 REG_READ(map->base);
447 }
448
449
450 temp = REG_READ(map->conf);
451 if ((temp & PIPEACONF_ENABLE) != 0) {
452 temp &= ~PIPEACONF_ENABLE;
453 temp |= PIPECONF_PLANE_OFF | PIPECONF_CURSOR_OFF;
454 REG_WRITE(map->conf, temp);
455 REG_READ(map->conf);
456
457
458 mdfldWaitForPipeDisable(dev, pipe);
459 }
460
461 temp = REG_READ(map->dpll);
462 if (temp & DPLL_VCO_ENABLE) {
463 if ((pipe != 1 && !((REG_READ(PIPEACONF)
464 | REG_READ(PIPECCONF)) & PIPEACONF_ENABLE))
465 || pipe == 1) {
466 temp &= ~(DPLL_VCO_ENABLE);
467 REG_WRITE(map->dpll, temp);
468 REG_READ(map->dpll);
469
470
471 udelay(500);
472 }
473 }
474 break;
475 }
476 gma_power_end(dev);
477}
478
479
480#define MDFLD_LIMT_DPLL_19 0
481#define MDFLD_LIMT_DPLL_25 1
482#define MDFLD_LIMT_DPLL_83 2
483#define MDFLD_LIMT_DPLL_100 3
484#define MDFLD_LIMT_DSIPLL_19 4
485#define MDFLD_LIMT_DSIPLL_25 5
486#define MDFLD_LIMT_DSIPLL_83 6
487#define MDFLD_LIMT_DSIPLL_100 7
488
489#define MDFLD_DOT_MIN 19750
490#define MDFLD_DOT_MAX 120000
491#define MDFLD_DPLL_M_MIN_19 113
492#define MDFLD_DPLL_M_MAX_19 155
493#define MDFLD_DPLL_P1_MIN_19 2
494#define MDFLD_DPLL_P1_MAX_19 10
495#define MDFLD_DPLL_M_MIN_25 101
496#define MDFLD_DPLL_M_MAX_25 130
497#define MDFLD_DPLL_P1_MIN_25 2
498#define MDFLD_DPLL_P1_MAX_25 10
499#define MDFLD_DPLL_M_MIN_83 64
500#define MDFLD_DPLL_M_MAX_83 64
501#define MDFLD_DPLL_P1_MIN_83 2
502#define MDFLD_DPLL_P1_MAX_83 2
503#define MDFLD_DPLL_M_MIN_100 64
504#define MDFLD_DPLL_M_MAX_100 64
505#define MDFLD_DPLL_P1_MIN_100 2
506#define MDFLD_DPLL_P1_MAX_100 2
507#define MDFLD_DSIPLL_M_MIN_19 131
508#define MDFLD_DSIPLL_M_MAX_19 175
509#define MDFLD_DSIPLL_P1_MIN_19 3
510#define MDFLD_DSIPLL_P1_MAX_19 8
511#define MDFLD_DSIPLL_M_MIN_25 97
512#define MDFLD_DSIPLL_M_MAX_25 140
513#define MDFLD_DSIPLL_P1_MIN_25 3
514#define MDFLD_DSIPLL_P1_MAX_25 9
515#define MDFLD_DSIPLL_M_MIN_83 33
516#define MDFLD_DSIPLL_M_MAX_83 92
517#define MDFLD_DSIPLL_P1_MIN_83 2
518#define MDFLD_DSIPLL_P1_MAX_83 3
519#define MDFLD_DSIPLL_M_MIN_100 97
520#define MDFLD_DSIPLL_M_MAX_100 140
521#define MDFLD_DSIPLL_P1_MIN_100 3
522#define MDFLD_DSIPLL_P1_MAX_100 9
523
524static const struct mrst_limit_t mdfld_limits[] = {
525 {
526 .dot = {.min = MDFLD_DOT_MIN, .max = MDFLD_DOT_MAX},
527 .m = {.min = MDFLD_DPLL_M_MIN_19, .max = MDFLD_DPLL_M_MAX_19},
528 .p1 = {.min = MDFLD_DPLL_P1_MIN_19, .max = MDFLD_DPLL_P1_MAX_19},
529 },
530 {
531 .dot = {.min = MDFLD_DOT_MIN, .max = MDFLD_DOT_MAX},
532 .m = {.min = MDFLD_DPLL_M_MIN_25, .max = MDFLD_DPLL_M_MAX_25},
533 .p1 = {.min = MDFLD_DPLL_P1_MIN_25, .max = MDFLD_DPLL_P1_MAX_25},
534 },
535 {
536 .dot = {.min = MDFLD_DOT_MIN, .max = MDFLD_DOT_MAX},
537 .m = {.min = MDFLD_DPLL_M_MIN_83, .max = MDFLD_DPLL_M_MAX_83},
538 .p1 = {.min = MDFLD_DPLL_P1_MIN_83, .max = MDFLD_DPLL_P1_MAX_83},
539 },
540 {
541 .dot = {.min = MDFLD_DOT_MIN, .max = MDFLD_DOT_MAX},
542 .m = {.min = MDFLD_DPLL_M_MIN_100, .max = MDFLD_DPLL_M_MAX_100},
543 .p1 = {.min = MDFLD_DPLL_P1_MIN_100, .max = MDFLD_DPLL_P1_MAX_100},
544 },
545 {
546 .dot = {.min = MDFLD_DOT_MIN, .max = MDFLD_DOT_MAX},
547 .m = {.min = MDFLD_DSIPLL_M_MIN_19, .max = MDFLD_DSIPLL_M_MAX_19},
548 .p1 = {.min = MDFLD_DSIPLL_P1_MIN_19, .max = MDFLD_DSIPLL_P1_MAX_19},
549 },
550 {
551 .dot = {.min = MDFLD_DOT_MIN, .max = MDFLD_DOT_MAX},
552 .m = {.min = MDFLD_DSIPLL_M_MIN_25, .max = MDFLD_DSIPLL_M_MAX_25},
553 .p1 = {.min = MDFLD_DSIPLL_P1_MIN_25, .max = MDFLD_DSIPLL_P1_MAX_25},
554 },
555 {
556 .dot = {.min = MDFLD_DOT_MIN, .max = MDFLD_DOT_MAX},
557 .m = {.min = MDFLD_DSIPLL_M_MIN_83, .max = MDFLD_DSIPLL_M_MAX_83},
558 .p1 = {.min = MDFLD_DSIPLL_P1_MIN_83, .max = MDFLD_DSIPLL_P1_MAX_83},
559 },
560 {
561 .dot = {.min = MDFLD_DOT_MIN, .max = MDFLD_DOT_MAX},
562 .m = {.min = MDFLD_DSIPLL_M_MIN_100, .max = MDFLD_DSIPLL_M_MAX_100},
563 .p1 = {.min = MDFLD_DSIPLL_P1_MIN_100, .max = MDFLD_DSIPLL_P1_MAX_100},
564 },
565};
566
567#define MDFLD_M_MIN 21
568#define MDFLD_M_MAX 180
569static const u32 mdfld_m_converts[] = {
570
571 224, 368, 440, 220, 366, 439, 219, 365, 182, 347,
572 173, 342, 171, 85, 298, 149, 74, 37, 18, 265,
573 388, 194, 353, 432, 216, 108, 310, 155, 333, 166,
574 83, 41, 276, 138, 325, 162, 337, 168, 340, 170,
575 341, 426, 469, 234, 373, 442, 221, 110, 311, 411,
576 461, 486, 243, 377, 188, 350, 175, 343, 427, 213,
577 106, 53, 282, 397, 354, 227, 113, 56, 284, 142,
578 71, 35, 273, 136, 324, 418, 465, 488, 500, 506,
579 253, 126, 63, 287, 399, 455, 483, 241, 376, 444,
580 478, 495, 503, 251, 381, 446, 479, 239, 375, 443,
581 477, 238, 119, 315, 157, 78, 295, 147, 329, 420,
582 210, 105, 308, 154, 77, 38, 275, 137, 68, 290,
583 145, 328, 164, 82, 297, 404, 458, 485, 498, 249,
584 380, 190, 351, 431, 471, 235, 117, 314, 413, 206,
585 103, 51, 25, 12, 262, 387, 193, 96, 48, 280,
586 396, 198, 99, 305, 152, 76, 294, 403, 457, 228,
587};
588
589static const struct mrst_limit_t *mdfld_limit(struct drm_crtc *crtc)
590{
591 const struct mrst_limit_t *limit = NULL;
592 struct drm_device *dev = crtc->dev;
593 struct drm_psb_private *dev_priv = dev->dev_private;
594
595 if (gma_pipe_has_type(crtc, INTEL_OUTPUT_MIPI)
596 || gma_pipe_has_type(crtc, INTEL_OUTPUT_MIPI2)) {
597 if ((ksel == KSEL_CRYSTAL_19) || (ksel == KSEL_BYPASS_19))
598 limit = &mdfld_limits[MDFLD_LIMT_DSIPLL_19];
599 else if (ksel == KSEL_BYPASS_25)
600 limit = &mdfld_limits[MDFLD_LIMT_DSIPLL_25];
601 else if ((ksel == KSEL_BYPASS_83_100) &&
602 (dev_priv->core_freq == 166))
603 limit = &mdfld_limits[MDFLD_LIMT_DSIPLL_83];
604 else if ((ksel == KSEL_BYPASS_83_100) &&
605 (dev_priv->core_freq == 100 ||
606 dev_priv->core_freq == 200))
607 limit = &mdfld_limits[MDFLD_LIMT_DSIPLL_100];
608 } else if (gma_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
609 if ((ksel == KSEL_CRYSTAL_19) || (ksel == KSEL_BYPASS_19))
610 limit = &mdfld_limits[MDFLD_LIMT_DPLL_19];
611 else if (ksel == KSEL_BYPASS_25)
612 limit = &mdfld_limits[MDFLD_LIMT_DPLL_25];
613 else if ((ksel == KSEL_BYPASS_83_100) &&
614 (dev_priv->core_freq == 166))
615 limit = &mdfld_limits[MDFLD_LIMT_DPLL_83];
616 else if ((ksel == KSEL_BYPASS_83_100) &&
617 (dev_priv->core_freq == 100 ||
618 dev_priv->core_freq == 200))
619 limit = &mdfld_limits[MDFLD_LIMT_DPLL_100];
620 } else {
621 limit = NULL;
622 dev_dbg(dev->dev, "mdfld_limit Wrong display type.\n");
623 }
624
625 return limit;
626}
627
628
629static void mdfld_clock(int refclk, struct mrst_clock_t *clock)
630{
631 clock->dot = (refclk * clock->m) / clock->p1;
632}
633
634
635
636
637
638static bool
639mdfldFindBestPLL(struct drm_crtc *crtc, int target, int refclk,
640 struct mrst_clock_t *best_clock)
641{
642 struct mrst_clock_t clock;
643 const struct mrst_limit_t *limit = mdfld_limit(crtc);
644 int err = target;
645
646 memset(best_clock, 0, sizeof(*best_clock));
647
648 for (clock.m = limit->m.min; clock.m <= limit->m.max; clock.m++) {
649 for (clock.p1 = limit->p1.min; clock.p1 <= limit->p1.max;
650 clock.p1++) {
651 int this_err;
652
653 mdfld_clock(refclk, &clock);
654
655 this_err = abs(clock.dot - target);
656 if (this_err < err) {
657 *best_clock = clock;
658 err = this_err;
659 }
660 }
661 }
662 return err != target;
663}
664
665static int mdfld_crtc_mode_set(struct drm_crtc *crtc,
666 struct drm_display_mode *mode,
667 struct drm_display_mode *adjusted_mode,
668 int x, int y,
669 struct drm_framebuffer *old_fb)
670{
671 struct drm_device *dev = crtc->dev;
672 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
673 struct drm_psb_private *dev_priv = dev->dev_private;
674 int pipe = gma_crtc->pipe;
675 const struct psb_offset *map = &dev_priv->regmap[pipe];
676 int refclk = 0;
677 int clk_n = 0, clk_p2 = 0, clk_byte = 1, clk = 0, m_conv = 0,
678 clk_tmp = 0;
679 struct mrst_clock_t clock;
680 bool ok;
681 u32 dpll = 0, fp = 0;
682 bool is_mipi = false, is_mipi2 = false, is_hdmi = false;
683 struct drm_mode_config *mode_config = &dev->mode_config;
684 struct gma_encoder *gma_encoder = NULL;
685 uint64_t scalingType = DRM_MODE_SCALE_FULLSCREEN;
686 struct drm_encoder *encoder;
687 struct drm_connector *connector;
688 int timeout = 0;
689 int ret;
690
691 dev_dbg(dev->dev, "pipe = 0x%x\n", pipe);
692
693#if 0
694 if (pipe == 1) {
695 if (!gma_power_begin(dev, true))
696 return 0;
697 android_hdmi_crtc_mode_set(crtc, mode, adjusted_mode,
698 x, y, old_fb);
699 goto mrst_crtc_mode_set_exit;
700 }
701#endif
702
703 ret = check_fb(crtc->primary->fb);
704 if (ret)
705 return ret;
706
707 dev_dbg(dev->dev, "adjusted_hdisplay = %d\n",
708 adjusted_mode->hdisplay);
709 dev_dbg(dev->dev, "adjusted_vdisplay = %d\n",
710 adjusted_mode->vdisplay);
711 dev_dbg(dev->dev, "adjusted_hsync_start = %d\n",
712 adjusted_mode->hsync_start);
713 dev_dbg(dev->dev, "adjusted_hsync_end = %d\n",
714 adjusted_mode->hsync_end);
715 dev_dbg(dev->dev, "adjusted_htotal = %d\n",
716 adjusted_mode->htotal);
717 dev_dbg(dev->dev, "adjusted_vsync_start = %d\n",
718 adjusted_mode->vsync_start);
719 dev_dbg(dev->dev, "adjusted_vsync_end = %d\n",
720 adjusted_mode->vsync_end);
721 dev_dbg(dev->dev, "adjusted_vtotal = %d\n",
722 adjusted_mode->vtotal);
723 dev_dbg(dev->dev, "adjusted_clock = %d\n",
724 adjusted_mode->clock);
725 dev_dbg(dev->dev, "hdisplay = %d\n",
726 mode->hdisplay);
727 dev_dbg(dev->dev, "vdisplay = %d\n",
728 mode->vdisplay);
729
730 if (!gma_power_begin(dev, true))
731 return 0;
732
733 memcpy(&gma_crtc->saved_mode, mode,
734 sizeof(struct drm_display_mode));
735 memcpy(&gma_crtc->saved_adjusted_mode, adjusted_mode,
736 sizeof(struct drm_display_mode));
737
738 list_for_each_entry(connector, &mode_config->connector_list, head) {
739 encoder = connector->encoder;
740 if (!encoder)
741 continue;
742
743 if (encoder->crtc != crtc)
744 continue;
745
746 gma_encoder = gma_attached_encoder(connector);
747
748 switch (gma_encoder->type) {
749 case INTEL_OUTPUT_MIPI:
750 is_mipi = true;
751 break;
752 case INTEL_OUTPUT_MIPI2:
753 is_mipi2 = true;
754 break;
755 case INTEL_OUTPUT_HDMI:
756 is_hdmi = true;
757 break;
758 }
759 }
760
761
762 REG_WRITE(VGACNTRL, VGA_DISP_DISABLE);
763
764
765 if (psb_intel_panel_fitter_pipe(dev) == pipe)
766 REG_WRITE(PFIT_CONTROL, 0);
767
768
769
770
771 if (pipe == 1) {
772
773
774
775
776
777
778
779
780
781
782
783 REG_WRITE(map->size, ((min(mode->crtc_vdisplay, adjusted_mode->crtc_vdisplay) - 1) << 16)
784 | (min(mode->crtc_hdisplay, adjusted_mode->crtc_hdisplay) - 1));
785
786 REG_WRITE(map->src, ((mode->crtc_hdisplay - 1) << 16)
787 | (mode->crtc_vdisplay - 1));
788 } else {
789 REG_WRITE(map->size,
790 ((mode->crtc_vdisplay - 1) << 16) |
791 (mode->crtc_hdisplay - 1));
792 REG_WRITE(map->src,
793 ((mode->crtc_hdisplay - 1) << 16) |
794 (mode->crtc_vdisplay - 1));
795 }
796
797 REG_WRITE(map->pos, 0);
798
799 if (gma_encoder)
800 drm_object_property_get_value(&connector->base,
801 dev->mode_config.scaling_mode_property, &scalingType);
802
803 if (scalingType == DRM_MODE_SCALE_NO_SCALE) {
804
805
806
807
808 int offsetX = 0, offsetY = 0;
809
810 offsetX = (adjusted_mode->crtc_hdisplay -
811 mode->crtc_hdisplay) / 2;
812 offsetY = (adjusted_mode->crtc_vdisplay -
813 mode->crtc_vdisplay) / 2;
814
815 REG_WRITE(map->htotal, (mode->crtc_hdisplay - 1) |
816 ((adjusted_mode->crtc_htotal - 1) << 16));
817 REG_WRITE(map->vtotal, (mode->crtc_vdisplay - 1) |
818 ((adjusted_mode->crtc_vtotal - 1) << 16));
819 REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start -
820 offsetX - 1) |
821 ((adjusted_mode->crtc_hblank_end - offsetX - 1) << 16));
822 REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start -
823 offsetX - 1) |
824 ((adjusted_mode->crtc_hsync_end - offsetX - 1) << 16));
825 REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start -
826 offsetY - 1) |
827 ((adjusted_mode->crtc_vblank_end - offsetY - 1) << 16));
828 REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start -
829 offsetY - 1) |
830 ((adjusted_mode->crtc_vsync_end - offsetY - 1) << 16));
831 } else {
832 REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) |
833 ((adjusted_mode->crtc_htotal - 1) << 16));
834 REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) |
835 ((adjusted_mode->crtc_vtotal - 1) << 16));
836 REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) |
837 ((adjusted_mode->crtc_hblank_end - 1) << 16));
838 REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) |
839 ((adjusted_mode->crtc_hsync_end - 1) << 16));
840 REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) |
841 ((adjusted_mode->crtc_vblank_end - 1) << 16));
842 REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) |
843 ((adjusted_mode->crtc_vsync_end - 1) << 16));
844 }
845
846
847 {
848 const struct drm_crtc_helper_funcs *crtc_funcs =
849 crtc->helper_private;
850 crtc_funcs->mode_set_base(crtc, x, y, old_fb);
851 }
852
853
854 dev_priv->pipeconf[pipe] = PIPEACONF_ENABLE;
855
856
857 dev_priv->dspcntr[pipe] = REG_READ(map->cntr);
858 dev_priv->dspcntr[pipe] |= pipe << DISPPLANE_SEL_PIPE_POS;
859 dev_priv->dspcntr[pipe] |= DISPLAY_PLANE_ENABLE;
860
861 if (is_mipi2)
862 goto mrst_crtc_mode_set_exit;
863 clk = adjusted_mode->clock;
864
865 if (is_hdmi) {
866 if ((ksel == KSEL_CRYSTAL_19) || (ksel == KSEL_BYPASS_19)) {
867 refclk = 19200;
868
869 if (is_mipi || is_mipi2)
870 clk_n = 1, clk_p2 = 8;
871 else if (is_hdmi)
872 clk_n = 1, clk_p2 = 10;
873 } else if (ksel == KSEL_BYPASS_25) {
874 refclk = 25000;
875
876 if (is_mipi || is_mipi2)
877 clk_n = 1, clk_p2 = 8;
878 else if (is_hdmi)
879 clk_n = 1, clk_p2 = 10;
880 } else if ((ksel == KSEL_BYPASS_83_100) &&
881 dev_priv->core_freq == 166) {
882 refclk = 83000;
883
884 if (is_mipi || is_mipi2)
885 clk_n = 4, clk_p2 = 8;
886 else if (is_hdmi)
887 clk_n = 4, clk_p2 = 10;
888 } else if ((ksel == KSEL_BYPASS_83_100) &&
889 (dev_priv->core_freq == 100 ||
890 dev_priv->core_freq == 200)) {
891 refclk = 100000;
892 if (is_mipi || is_mipi2)
893 clk_n = 4, clk_p2 = 8;
894 else if (is_hdmi)
895 clk_n = 4, clk_p2 = 10;
896 }
897
898 if (is_mipi)
899 clk_byte = dev_priv->bpp / 8;
900 else if (is_mipi2)
901 clk_byte = dev_priv->bpp2 / 8;
902
903 clk_tmp = clk * clk_n * clk_p2 * clk_byte;
904
905 dev_dbg(dev->dev, "clk = %d, clk_n = %d, clk_p2 = %d.\n",
906 clk, clk_n, clk_p2);
907 dev_dbg(dev->dev, "adjusted_mode->clock = %d, clk_tmp = %d.\n",
908 adjusted_mode->clock, clk_tmp);
909
910 ok = mdfldFindBestPLL(crtc, clk_tmp, refclk, &clock);
911
912 if (!ok) {
913 DRM_ERROR
914 ("mdfldFindBestPLL fail in mdfld_crtc_mode_set.\n");
915 } else {
916 m_conv = mdfld_m_converts[(clock.m - MDFLD_M_MIN)];
917
918 dev_dbg(dev->dev, "dot clock = %d,"
919 "m = %d, p1 = %d, m_conv = %d.\n",
920 clock.dot, clock.m,
921 clock.p1, m_conv);
922 }
923
924 dpll = REG_READ(map->dpll);
925
926 if (dpll & DPLL_VCO_ENABLE) {
927 dpll &= ~DPLL_VCO_ENABLE;
928 REG_WRITE(map->dpll, dpll);
929 REG_READ(map->dpll);
930
931
932
933 udelay(500);
934
935
936 REG_WRITE(map->fp0, 0);
937 dpll &= ~MDFLD_P1_MASK;
938 REG_WRITE(map->dpll, dpll);
939
940 udelay(500);
941 }
942
943
944
945 if (dpll & MDFLD_PWR_GATE_EN) {
946 dpll &= ~MDFLD_PWR_GATE_EN;
947 REG_WRITE(map->dpll, dpll);
948
949 udelay(500);
950 }
951 dpll = 0;
952
953#if 0
954 if (ksel == KSEL_CRYSTAL_19 || ksel == KSEL_BYPASS_19 ||
955 ksel == KSEL_BYPASS_25)
956 dpll &= ~MDFLD_INPUT_REF_SEL;
957 else if (ksel == KSEL_BYPASS_83_100)
958 dpll |= MDFLD_INPUT_REF_SEL;
959#endif
960
961 if (is_hdmi)
962 dpll |= MDFLD_VCO_SEL;
963
964 fp = (clk_n / 2) << 16;
965 fp |= m_conv;
966
967
968 dpll |= (1 << (clock.p1 - 2)) << 17;
969
970#if 0
971 dpll = 0x00050000;
972 fp = 0x000001be;
973#endif
974#if 0
975 dpll = 0x02010000;
976 fp = 0x000000d2;
977#endif
978 } else {
979#if 0
980 dpll = 0x00020000;
981 fp = 0x00000156;
982#endif
983
984 dpll = 0x00800000;
985 fp = 0x000000c1;
986 }
987
988 REG_WRITE(map->fp0, fp);
989 REG_WRITE(map->dpll, dpll);
990
991 udelay(500);
992
993 dpll |= DPLL_VCO_ENABLE;
994 REG_WRITE(map->dpll, dpll);
995 REG_READ(map->dpll);
996
997
998 while (timeout < 20000 &&
999 !(REG_READ(map->conf) & PIPECONF_DSIPLL_LOCK)) {
1000 udelay(150);
1001 timeout++;
1002 }
1003
1004 if (is_mipi)
1005 goto mrst_crtc_mode_set_exit;
1006
1007 dev_dbg(dev->dev, "is_mipi = 0x%x\n", is_mipi);
1008
1009 REG_WRITE(map->conf, dev_priv->pipeconf[pipe]);
1010 REG_READ(map->conf);
1011
1012
1013 REG_WRITE(map->cntr, dev_priv->dspcntr[pipe]);
1014 gma_wait_for_vblank(dev);
1015
1016mrst_crtc_mode_set_exit:
1017
1018 gma_power_end(dev);
1019
1020 return 0;
1021}
1022
1023const struct drm_crtc_helper_funcs mdfld_helper_funcs = {
1024 .dpms = mdfld_crtc_dpms,
1025 .mode_set = mdfld_crtc_mode_set,
1026 .mode_set_base = mdfld__intel_pipe_set_base,
1027 .prepare = gma_crtc_prepare,
1028 .commit = gma_crtc_commit,
1029};
1030