1
2
3
4
5
6
7
8
9#ifndef VC4_REGS_H
10#define VC4_REGS_H
11
12#include <linux/bitops.h>
13
14#define VC4_MASK(high, low) ((u32)GENMASK(high, low))
15
16#define VC4_SET_FIELD(value, field) \
17 ({ \
18 uint32_t fieldval = (value) << field##_SHIFT; \
19 WARN_ON((fieldval & ~field##_MASK) != 0); \
20 fieldval & field##_MASK; \
21 })
22
23#define VC4_GET_FIELD(word, field) (((word) & field##_MASK) >> \
24 field##_SHIFT)
25
26#define V3D_IDENT0 0x00000
27# define V3D_EXPECTED_IDENT0 \
28 ((2 << 24) | \
29 ('V' << 0) | \
30 ('3' << 8) | \
31 ('D' << 16))
32
33#define V3D_IDENT1 0x00004
34
35# define V3D_IDENT1_VPM_SIZE_MASK VC4_MASK(31, 28)
36# define V3D_IDENT1_VPM_SIZE_SHIFT 28
37# define V3D_IDENT1_NSEM_MASK VC4_MASK(23, 16)
38# define V3D_IDENT1_NSEM_SHIFT 16
39# define V3D_IDENT1_TUPS_MASK VC4_MASK(15, 12)
40# define V3D_IDENT1_TUPS_SHIFT 12
41# define V3D_IDENT1_QUPS_MASK VC4_MASK(11, 8)
42# define V3D_IDENT1_QUPS_SHIFT 8
43# define V3D_IDENT1_NSLC_MASK VC4_MASK(7, 4)
44# define V3D_IDENT1_NSLC_SHIFT 4
45# define V3D_IDENT1_REV_MASK VC4_MASK(3, 0)
46# define V3D_IDENT1_REV_SHIFT 0
47
48#define V3D_IDENT2 0x00008
49#define V3D_SCRATCH 0x00010
50#define V3D_L2CACTL 0x00020
51# define V3D_L2CACTL_L2CCLR BIT(2)
52# define V3D_L2CACTL_L2CDIS BIT(1)
53# define V3D_L2CACTL_L2CENA BIT(0)
54
55#define V3D_SLCACTL 0x00024
56# define V3D_SLCACTL_T1CC_MASK VC4_MASK(27, 24)
57# define V3D_SLCACTL_T1CC_SHIFT 24
58# define V3D_SLCACTL_T0CC_MASK VC4_MASK(19, 16)
59# define V3D_SLCACTL_T0CC_SHIFT 16
60# define V3D_SLCACTL_UCC_MASK VC4_MASK(11, 8)
61# define V3D_SLCACTL_UCC_SHIFT 8
62# define V3D_SLCACTL_ICC_MASK VC4_MASK(3, 0)
63# define V3D_SLCACTL_ICC_SHIFT 0
64
65#define V3D_INTCTL 0x00030
66#define V3D_INTENA 0x00034
67#define V3D_INTDIS 0x00038
68# define V3D_INT_SPILLUSE BIT(3)
69# define V3D_INT_OUTOMEM BIT(2)
70# define V3D_INT_FLDONE BIT(1)
71# define V3D_INT_FRDONE BIT(0)
72
73#define V3D_CT0CS 0x00100
74#define V3D_CT1CS 0x00104
75#define V3D_CTNCS(n) (V3D_CT0CS + 4 * n)
76# define V3D_CTRSTA BIT(15)
77# define V3D_CTSEMA BIT(12)
78# define V3D_CTRTSD BIT(8)
79# define V3D_CTRUN BIT(5)
80# define V3D_CTSUBS BIT(4)
81# define V3D_CTERR BIT(3)
82# define V3D_CTMODE BIT(0)
83
84#define V3D_CT0EA 0x00108
85#define V3D_CT1EA 0x0010c
86#define V3D_CTNEA(n) (V3D_CT0EA + 4 * (n))
87#define V3D_CT0CA 0x00110
88#define V3D_CT1CA 0x00114
89#define V3D_CTNCA(n) (V3D_CT0CA + 4 * (n))
90#define V3D_CT00RA0 0x00118
91#define V3D_CT01RA0 0x0011c
92#define V3D_CTNRA0(n) (V3D_CT00RA0 + 4 * (n))
93#define V3D_CT0LC 0x00120
94#define V3D_CT1LC 0x00124
95#define V3D_CTNLC(n) (V3D_CT0LC + 4 * (n))
96#define V3D_CT0PC 0x00128
97#define V3D_CT1PC 0x0012c
98#define V3D_CTNPC(n) (V3D_CT0PC + 4 * (n))
99
100#define V3D_PCS 0x00130
101# define V3D_BMOOM BIT(8)
102# define V3D_RMBUSY BIT(3)
103# define V3D_RMACTIVE BIT(2)
104# define V3D_BMBUSY BIT(1)
105# define V3D_BMACTIVE BIT(0)
106
107#define V3D_BFC 0x00134
108#define V3D_RFC 0x00138
109#define V3D_BPCA 0x00300
110#define V3D_BPCS 0x00304
111#define V3D_BPOA 0x00308
112#define V3D_BPOS 0x0030c
113#define V3D_BXCF 0x00310
114#define V3D_SQRSV0 0x00410
115#define V3D_SQRSV1 0x00414
116#define V3D_SQCNTL 0x00418
117#define V3D_SRQPC 0x00430
118#define V3D_SRQUA 0x00434
119#define V3D_SRQUL 0x00438
120#define V3D_SRQCS 0x0043c
121#define V3D_VPACNTL 0x00500
122#define V3D_VPMBASE 0x00504
123#define V3D_PCTRC 0x00670
124#define V3D_PCTRE 0x00674
125# define V3D_PCTRE_EN BIT(31)
126#define V3D_PCTR(x) (0x00680 + ((x) * 8))
127#define V3D_PCTRS(x) (0x00684 + ((x) * 8))
128#define V3D_DBGE 0x00f00
129#define V3D_FDBGO 0x00f04
130#define V3D_FDBGB 0x00f08
131#define V3D_FDBGR 0x00f0c
132#define V3D_FDBGS 0x00f10
133#define V3D_ERRSTAT 0x00f20
134
135#define PV_CONTROL 0x00
136# define PV_CONTROL_FORMAT_MASK VC4_MASK(23, 21)
137# define PV_CONTROL_FORMAT_SHIFT 21
138# define PV_CONTROL_FORMAT_24 0
139# define PV_CONTROL_FORMAT_DSIV_16 1
140# define PV_CONTROL_FORMAT_DSIC_16 2
141# define PV_CONTROL_FORMAT_DSIV_18 3
142# define PV_CONTROL_FORMAT_DSIV_24 4
143
144# define PV_CONTROL_FIFO_LEVEL_MASK VC4_MASK(20, 15)
145# define PV_CONTROL_FIFO_LEVEL_SHIFT 15
146# define PV_CONTROL_CLR_AT_START BIT(14)
147# define PV_CONTROL_TRIGGER_UNDERFLOW BIT(13)
148# define PV_CONTROL_WAIT_HSTART BIT(12)
149# define PV_CONTROL_PIXEL_REP_MASK VC4_MASK(5, 4)
150# define PV_CONTROL_PIXEL_REP_SHIFT 4
151# define PV_CONTROL_CLK_SELECT_DSI 0
152# define PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI 1
153# define PV_CONTROL_CLK_SELECT_VEC 2
154# define PV_CONTROL_CLK_SELECT_MASK VC4_MASK(3, 2)
155# define PV_CONTROL_CLK_SELECT_SHIFT 2
156# define PV_CONTROL_FIFO_CLR BIT(1)
157# define PV_CONTROL_EN BIT(0)
158
159#define PV_V_CONTROL 0x04
160# define PV_VCONTROL_ODD_DELAY_MASK VC4_MASK(22, 6)
161# define PV_VCONTROL_ODD_DELAY_SHIFT 6
162# define PV_VCONTROL_ODD_FIRST BIT(5)
163# define PV_VCONTROL_INTERLACE BIT(4)
164# define PV_VCONTROL_DSI BIT(3)
165# define PV_VCONTROL_COMMAND BIT(2)
166# define PV_VCONTROL_CONTINUOUS BIT(1)
167# define PV_VCONTROL_VIDEN BIT(0)
168
169#define PV_VSYNCD_EVEN 0x08
170
171#define PV_HORZA 0x0c
172# define PV_HORZA_HBP_MASK VC4_MASK(31, 16)
173# define PV_HORZA_HBP_SHIFT 16
174# define PV_HORZA_HSYNC_MASK VC4_MASK(15, 0)
175# define PV_HORZA_HSYNC_SHIFT 0
176
177#define PV_HORZB 0x10
178# define PV_HORZB_HFP_MASK VC4_MASK(31, 16)
179# define PV_HORZB_HFP_SHIFT 16
180# define PV_HORZB_HACTIVE_MASK VC4_MASK(15, 0)
181# define PV_HORZB_HACTIVE_SHIFT 0
182
183#define PV_VERTA 0x14
184# define PV_VERTA_VBP_MASK VC4_MASK(31, 16)
185# define PV_VERTA_VBP_SHIFT 16
186# define PV_VERTA_VSYNC_MASK VC4_MASK(15, 0)
187# define PV_VERTA_VSYNC_SHIFT 0
188
189#define PV_VERTB 0x18
190# define PV_VERTB_VFP_MASK VC4_MASK(31, 16)
191# define PV_VERTB_VFP_SHIFT 16
192# define PV_VERTB_VACTIVE_MASK VC4_MASK(15, 0)
193# define PV_VERTB_VACTIVE_SHIFT 0
194
195#define PV_VERTA_EVEN 0x1c
196#define PV_VERTB_EVEN 0x20
197
198#define PV_INTEN 0x24
199#define PV_INTSTAT 0x28
200# define PV_INT_VID_IDLE BIT(9)
201# define PV_INT_VFP_END BIT(8)
202# define PV_INT_VFP_START BIT(7)
203# define PV_INT_VACT_START BIT(6)
204# define PV_INT_VBP_START BIT(5)
205# define PV_INT_VSYNC_START BIT(4)
206# define PV_INT_HFP_START BIT(3)
207# define PV_INT_HACT_START BIT(2)
208# define PV_INT_HBP_START BIT(1)
209# define PV_INT_HSYNC_START BIT(0)
210
211#define PV_STAT 0x2c
212
213#define PV_HACT_ACT 0x30
214
215#define SCALER_DISPCTRL 0x00000000
216
217# define SCALER_DISPCTRL_ENABLE BIT(31)
218# define SCALER_DISPCTRL_DSP2EISLUR BIT(15)
219# define SCALER_DISPCTRL_DSP1EISLUR BIT(14)
220# define SCALER_DISPCTRL_DSP3_MUX_MASK VC4_MASK(19, 18)
221# define SCALER_DISPCTRL_DSP3_MUX_SHIFT 18
222
223
224
225
226
227# define SCALER_DISPCTRL_DSP0EISLUR BIT(13)
228# define SCALER_DISPCTRL_DSP2EIEOLN BIT(12)
229# define SCALER_DISPCTRL_DSP2EIEOF BIT(11)
230# define SCALER_DISPCTRL_DSP1EIEOLN BIT(10)
231# define SCALER_DISPCTRL_DSP1EIEOF BIT(9)
232
233
234
235# define SCALER_DISPCTRL_DSP0EIEOLN BIT(8)
236
237# define SCALER_DISPCTRL_DSP0EIEOF BIT(7)
238
239# define SCALER_DISPCTRL_SLVRDEIRQ BIT(6)
240# define SCALER_DISPCTRL_SLVWREIRQ BIT(5)
241# define SCALER_DISPCTRL_DMAEIRQ BIT(4)
242# define SCALER_DISPCTRL_DISP2EIRQ BIT(3)
243# define SCALER_DISPCTRL_DISP1EIRQ BIT(2)
244
245
246
247# define SCALER_DISPCTRL_DISP0EIRQ BIT(1)
248
249# define SCALER_DISPCTRL_SCLEIRQ BIT(0)
250
251#define SCALER_DISPSTAT 0x00000004
252# define SCALER_DISPSTAT_COBLOW2 BIT(29)
253# define SCALER_DISPSTAT_EOLN2 BIT(28)
254# define SCALER_DISPSTAT_ESFRAME2 BIT(27)
255# define SCALER_DISPSTAT_ESLINE2 BIT(26)
256# define SCALER_DISPSTAT_EUFLOW2 BIT(25)
257# define SCALER_DISPSTAT_EOF2 BIT(24)
258
259# define SCALER_DISPSTAT_COBLOW1 BIT(21)
260# define SCALER_DISPSTAT_EOLN1 BIT(20)
261# define SCALER_DISPSTAT_ESFRAME1 BIT(19)
262# define SCALER_DISPSTAT_ESLINE1 BIT(18)
263# define SCALER_DISPSTAT_EUFLOW1 BIT(17)
264# define SCALER_DISPSTAT_EOF1 BIT(16)
265
266# define SCALER_DISPSTAT_RESP_MASK VC4_MASK(15, 14)
267# define SCALER_DISPSTAT_RESP_SHIFT 14
268# define SCALER_DISPSTAT_RESP_OKAY 0
269# define SCALER_DISPSTAT_RESP_EXOKAY 1
270# define SCALER_DISPSTAT_RESP_SLVERR 2
271# define SCALER_DISPSTAT_RESP_DECERR 3
272
273# define SCALER_DISPSTAT_COBLOW0 BIT(13)
274
275# define SCALER_DISPSTAT_EOLN0 BIT(12)
276
277
278
279# define SCALER_DISPSTAT_ESFRAME0 BIT(11)
280
281
282
283# define SCALER_DISPSTAT_ESLINE0 BIT(10)
284
285
286
287# define SCALER_DISPSTAT_EUFLOW0 BIT(9)
288
289# define SCALER_DISPSTAT_EOF0 BIT(8)
290
291
292# define SCALER_DISPSTAT_DMA_ERROR BIT(7)
293
294# define SCALER_DISPSTAT_IRQSLVRD BIT(6)
295
296# define SCALER_DISPSTAT_IRQSLVWR BIT(5)
297
298
299
300# define SCALER_DISPSTAT_IRQDMA BIT(4)
301# define SCALER_DISPSTAT_IRQDISP2 BIT(3)
302# define SCALER_DISPSTAT_IRQDISP1 BIT(2)
303
304
305
306# define SCALER_DISPSTAT_IRQDISP0 BIT(1)
307
308# define SCALER_DISPSTAT_IRQSCL BIT(0)
309
310#define SCALER_DISPID 0x00000008
311#define SCALER_DISPECTRL 0x0000000c
312#define SCALER_DISPPROF 0x00000010
313#define SCALER_DISPDITHER 0x00000014
314#define SCALER_DISPEOLN 0x00000018
315#define SCALER_DISPLIST0 0x00000020
316#define SCALER_DISPLIST1 0x00000024
317#define SCALER_DISPLIST2 0x00000028
318#define SCALER_DISPLSTAT 0x0000002c
319#define SCALER_DISPLISTX(x) (SCALER_DISPLIST0 + \
320 (x) * (SCALER_DISPLIST1 - \
321 SCALER_DISPLIST0))
322
323#define SCALER_DISPLACT0 0x00000030
324#define SCALER_DISPLACT1 0x00000034
325#define SCALER_DISPLACT2 0x00000038
326#define SCALER_DISPLACTX(x) (SCALER_DISPLACT0 + \
327 (x) * (SCALER_DISPLACT1 - \
328 SCALER_DISPLACT0))
329
330#define SCALER_DISPCTRL0 0x00000040
331# define SCALER_DISPCTRLX_ENABLE BIT(31)
332# define SCALER_DISPCTRLX_RESET BIT(30)
333
334
335
336# define SCALER_DISPCTRLX_ONESHOT BIT(29)
337
338
339
340# define SCALER_DISPCTRLX_ONECTX BIT(28)
341
342# define SCALER_DISPCTRLX_FIFO32 BIT(27)
343
344
345
346# define SCALER_DISPCTRLX_FIFOREG BIT(26)
347
348# define SCALER_DISPCTRLX_WIDTH_MASK VC4_MASK(23, 12)
349# define SCALER_DISPCTRLX_WIDTH_SHIFT 12
350# define SCALER_DISPCTRLX_HEIGHT_MASK VC4_MASK(11, 0)
351# define SCALER_DISPCTRLX_HEIGHT_SHIFT 0
352
353#define SCALER_DISPBKGND0 0x00000044
354# define SCALER_DISPBKGND_AUTOHS BIT(31)
355# define SCALER_DISPBKGND_INTERLACE BIT(30)
356# define SCALER_DISPBKGND_GAMMA BIT(29)
357# define SCALER_DISPBKGND_TESTMODE_MASK VC4_MASK(28, 25)
358# define SCALER_DISPBKGND_TESTMODE_SHIFT 25
359
360
361
362
363# define SCALER_DISPBKGND_FILL BIT(24)
364
365#define SCALER_DISPSTAT0 0x00000048
366# define SCALER_DISPSTATX_MODE_MASK VC4_MASK(31, 30)
367# define SCALER_DISPSTATX_MODE_SHIFT 30
368# define SCALER_DISPSTATX_MODE_DISABLED 0
369# define SCALER_DISPSTATX_MODE_INIT 1
370# define SCALER_DISPSTATX_MODE_RUN 2
371# define SCALER_DISPSTATX_MODE_EOF 3
372# define SCALER_DISPSTATX_FULL BIT(29)
373# define SCALER_DISPSTATX_EMPTY BIT(28)
374# define SCALER_DISPSTATX_FRAME_COUNT_MASK VC4_MASK(17, 12)
375# define SCALER_DISPSTATX_FRAME_COUNT_SHIFT 12
376# define SCALER_DISPSTATX_LINE_MASK VC4_MASK(11, 0)
377# define SCALER_DISPSTATX_LINE_SHIFT 0
378
379#define SCALER_DISPBASE0 0x0000004c
380
381
382
383
384# define SCALER_DISPBASEX_TOP_MASK VC4_MASK(31, 16)
385# define SCALER_DISPBASEX_TOP_SHIFT 16
386
387
388
389# define SCALER_DISPBASEX_BASE_MASK VC4_MASK(15, 0)
390# define SCALER_DISPBASEX_BASE_SHIFT 0
391
392#define SCALER_DISPCTRL1 0x00000050
393#define SCALER_DISPBKGND1 0x00000054
394#define SCALER_DISPBKGNDX(x) (SCALER_DISPBKGND0 + \
395 (x) * (SCALER_DISPBKGND1 - \
396 SCALER_DISPBKGND0))
397#define SCALER_DISPSTAT1 0x00000058
398#define SCALER_DISPSTATX(x) (SCALER_DISPSTAT0 + \
399 (x) * (SCALER_DISPSTAT1 - \
400 SCALER_DISPSTAT0))
401#define SCALER_DISPBASE1 0x0000005c
402#define SCALER_DISPBASEX(x) (SCALER_DISPBASE0 + \
403 (x) * (SCALER_DISPBASE1 - \
404 SCALER_DISPBASE0))
405#define SCALER_DISPCTRL2 0x00000060
406#define SCALER_DISPCTRLX(x) (SCALER_DISPCTRL0 + \
407 (x) * (SCALER_DISPCTRL1 - \
408 SCALER_DISPCTRL0))
409#define SCALER_DISPBKGND2 0x00000064
410#define SCALER_DISPSTAT2 0x00000068
411#define SCALER_DISPBASE2 0x0000006c
412#define SCALER_DISPALPHA2 0x00000070
413#define SCALER_GAMADDR 0x00000078
414# define SCALER_GAMADDR_AUTOINC BIT(31)
415
416
417
418# define SCALER_GAMADDR_SRAMENB BIT(30)
419
420#define SCALER_OLEDOFFS 0x00000080
421
422# define SCALER_OLEDOFFS_YUVCLAMP BIT(31)
423
424
425# define SCALER_OLEDOFFS_DISPFIFO_MASK VC4_MASK(25, 24)
426# define SCALER_OLEDOFFS_DISPFIFO_SHIFT 24
427# define SCALER_OLEDOFFS_DISPFIFO_DISABLED 0
428# define SCALER_OLEDOFFS_DISPFIFO_0 1
429# define SCALER_OLEDOFFS_DISPFIFO_1 2
430# define SCALER_OLEDOFFS_DISPFIFO_2 3
431
432
433# define SCALER_OLEDOFFS_RED_MASK VC4_MASK(23, 16)
434# define SCALER_OLEDOFFS_RED_SHIFT 16
435# define SCALER_OLEDOFFS_GREEN_MASK VC4_MASK(15, 8)
436# define SCALER_OLEDOFFS_GREEN_SHIFT 8
437# define SCALER_OLEDOFFS_BLUE_MASK VC4_MASK(7, 0)
438# define SCALER_OLEDOFFS_BLUE_SHIFT 0
439
440
441#define SCALER_OLEDCOEF0 0x00000084
442# define SCALER_OLEDCOEF0_B_TO_R_MASK VC4_MASK(29, 20)
443# define SCALER_OLEDCOEF0_B_TO_R_SHIFT 20
444# define SCALER_OLEDCOEF0_B_TO_G_MASK VC4_MASK(19, 10)
445# define SCALER_OLEDCOEF0_B_TO_G_SHIFT 10
446# define SCALER_OLEDCOEF0_B_TO_B_MASK VC4_MASK(9, 0)
447# define SCALER_OLEDCOEF0_B_TO_B_SHIFT 0
448
449#define SCALER_OLEDCOEF1 0x00000088
450# define SCALER_OLEDCOEF1_G_TO_R_MASK VC4_MASK(29, 20)
451# define SCALER_OLEDCOEF1_G_TO_R_SHIFT 20
452# define SCALER_OLEDCOEF1_G_TO_G_MASK VC4_MASK(19, 10)
453# define SCALER_OLEDCOEF1_G_TO_G_SHIFT 10
454# define SCALER_OLEDCOEF1_G_TO_B_MASK VC4_MASK(9, 0)
455# define SCALER_OLEDCOEF1_G_TO_B_SHIFT 0
456
457#define SCALER_OLEDCOEF2 0x0000008c
458# define SCALER_OLEDCOEF2_R_TO_R_MASK VC4_MASK(29, 20)
459# define SCALER_OLEDCOEF2_R_TO_R_SHIFT 20
460# define SCALER_OLEDCOEF2_R_TO_G_MASK VC4_MASK(19, 10)
461# define SCALER_OLEDCOEF2_R_TO_G_SHIFT 10
462# define SCALER_OLEDCOEF2_R_TO_B_MASK VC4_MASK(9, 0)
463# define SCALER_OLEDCOEF2_R_TO_B_SHIFT 0
464
465
466
467
468#define SCALER_DISPSLAVE0 0x000000c0
469#define SCALER_DISPSLAVE1 0x000000c9
470#define SCALER_DISPSLAVE2 0x000000d0
471# define SCALER_DISPSLAVE_ISSUE_VSTART BIT(31)
472# define SCALER_DISPSLAVE_ISSUE_HSTART BIT(30)
473
474# define SCALER_DISPSLAVE_EOL BIT(26)
475
476# define SCALER_DISPSLAVE_EMPTY BIT(25)
477
478# define SCALER_DISPSLAVE_VALID BIT(24)
479# define SCALER_DISPSLAVE_RGB_MASK VC4_MASK(23, 0)
480# define SCALER_DISPSLAVE_RGB_SHIFT 0
481
482#define SCALER_GAMDATA 0x000000e0
483#define SCALER_DLIST_START 0x00002000
484#define SCALER_DLIST_SIZE 0x00004000
485
486#define VC4_HDMI_CORE_REV 0x000
487
488#define VC4_HDMI_SW_RESET_CONTROL 0x004
489# define VC4_HDMI_SW_RESET_FORMAT_DETECT BIT(1)
490# define VC4_HDMI_SW_RESET_HDMI BIT(0)
491
492#define VC4_HDMI_HOTPLUG_INT 0x008
493
494#define VC4_HDMI_HOTPLUG 0x00c
495# define VC4_HDMI_HOTPLUG_CONNECTED BIT(0)
496
497
498
499
500#define VC4_HDMI_MAI_CHANNEL_MAP 0x090
501
502#define VC4_HDMI_MAI_CONFIG 0x094
503# define VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE BIT(27)
504# define VC4_HDMI_MAI_CONFIG_BIT_REVERSE BIT(26)
505# define VC4_HDMI_MAI_CHANNEL_MASK_MASK VC4_MASK(15, 0)
506# define VC4_HDMI_MAI_CHANNEL_MASK_SHIFT 0
507
508
509#define VC4_HDMI_MAI_FORMAT 0x098
510
511#define VC4_HDMI_AUDIO_PACKET_CONFIG 0x09c
512# define VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT BIT(29)
513# define VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS BIT(24)
514# define VC4_HDMI_AUDIO_PACKET_FORCE_SAMPLE_PRESENT BIT(19)
515# define VC4_HDMI_AUDIO_PACKET_FORCE_B_FRAME BIT(18)
516# define VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER_MASK VC4_MASK(13, 10)
517# define VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER_SHIFT 10
518
519# define VC4_HDMI_AUDIO_PACKET_AUDIO_LAYOUT BIT(9)
520
521# define VC4_HDMI_AUDIO_PACKET_FORCE_AUDIO_LAYOUT BIT(8)
522# define VC4_HDMI_AUDIO_PACKET_CEA_MASK_MASK VC4_MASK(7, 0)
523# define VC4_HDMI_AUDIO_PACKET_CEA_MASK_SHIFT 0
524
525#define VC4_HDMI_RAM_PACKET_CONFIG 0x0a0
526# define VC4_HDMI_RAM_PACKET_ENABLE BIT(16)
527
528#define VC4_HDMI_RAM_PACKET_STATUS 0x0a4
529
530#define VC4_HDMI_CRP_CFG 0x0a8
531
532
533
534# define VC4_HDMI_CRP_USE_MAI_BUS_SYNC_FOR_CTS BIT(26)
535
536# define VC4_HDMI_CRP_CFG_DISABLE BIT(25)
537
538
539
540# define VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN BIT(24)
541# define VC4_HDMI_CRP_CFG_N_MASK VC4_MASK(19, 0)
542# define VC4_HDMI_CRP_CFG_N_SHIFT 0
543
544
545#define VC4_HDMI_CTS_0 0x0ac
546#define VC4_HDMI_CTS_1 0x0b0
547
548
549
550#define VC4_HDMI_CTS_PERIOD_0 0x0b4
551#define VC4_HDMI_CTS_PERIOD_1 0x0b8
552
553#define VC4_HDMI_HORZA 0x0c4
554# define VC4_HDMI_HORZA_VPOS BIT(14)
555# define VC4_HDMI_HORZA_HPOS BIT(13)
556
557# define VC4_HDMI_HORZA_HAP_MASK VC4_MASK(12, 0)
558# define VC4_HDMI_HORZA_HAP_SHIFT 0
559
560#define VC4_HDMI_HORZB 0x0c8
561
562# define VC4_HDMI_HORZB_HBP_MASK VC4_MASK(29, 20)
563# define VC4_HDMI_HORZB_HBP_SHIFT 20
564
565# define VC4_HDMI_HORZB_HSP_MASK VC4_MASK(19, 10)
566# define VC4_HDMI_HORZB_HSP_SHIFT 10
567
568# define VC4_HDMI_HORZB_HFP_MASK VC4_MASK(9, 0)
569# define VC4_HDMI_HORZB_HFP_SHIFT 0
570
571#define VC4_HDMI_FIFO_CTL 0x05c
572# define VC4_HDMI_FIFO_CTL_RECENTER_DONE BIT(14)
573# define VC4_HDMI_FIFO_CTL_USE_EMPTY BIT(13)
574# define VC4_HDMI_FIFO_CTL_ON_VB BIT(7)
575# define VC4_HDMI_FIFO_CTL_RECENTER BIT(6)
576# define VC4_HDMI_FIFO_CTL_FIFO_RESET BIT(5)
577# define VC4_HDMI_FIFO_CTL_USE_PLL_LOCK BIT(4)
578# define VC4_HDMI_FIFO_CTL_INV_CLK_XFR BIT(3)
579# define VC4_HDMI_FIFO_CTL_CAPTURE_PTR BIT(2)
580# define VC4_HDMI_FIFO_CTL_USE_FULL BIT(1)
581# define VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N BIT(0)
582# define VC4_HDMI_FIFO_VALID_WRITE_MASK 0xefff
583
584#define VC4_HDMI_SCHEDULER_CONTROL 0x0c0
585# define VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT BIT(15)
586# define VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS BIT(5)
587# define VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT BIT(3)
588# define VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE BIT(1)
589# define VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI BIT(0)
590
591#define VC4_HDMI_VERTA0 0x0cc
592#define VC4_HDMI_VERTA1 0x0d4
593
594# define VC4_HDMI_VERTA_VSP_MASK VC4_MASK(24, 20)
595# define VC4_HDMI_VERTA_VSP_SHIFT 20
596
597# define VC4_HDMI_VERTA_VFP_MASK VC4_MASK(19, 13)
598# define VC4_HDMI_VERTA_VFP_SHIFT 13
599
600# define VC4_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0)
601# define VC4_HDMI_VERTA_VAL_SHIFT 0
602
603#define VC4_HDMI_VERTB0 0x0d0
604#define VC4_HDMI_VERTB1 0x0d8
605
606# define VC4_HDMI_VERTB_VSPO_MASK VC4_MASK(21, 9)
607# define VC4_HDMI_VERTB_VSPO_SHIFT 9
608
609# define VC4_HDMI_VERTB_VBP_MASK VC4_MASK(8, 0)
610# define VC4_HDMI_VERTB_VBP_SHIFT 0
611
612#define VC4_HDMI_CEC_CNTRL_1 0x0e8
613
614# define VC4_HDMI_CEC_TX_EOM BIT(31)
615
616
617
618
619# define VC4_HDMI_CEC_TX_STATUS_GOOD BIT(30)
620# define VC4_HDMI_CEC_RX_EOM BIT(29)
621# define VC4_HDMI_CEC_RX_STATUS_GOOD BIT(28)
622
623# define VC4_HDMI_CEC_REC_WRD_CNT_MASK VC4_MASK(27, 24)
624# define VC4_HDMI_CEC_REC_WRD_CNT_SHIFT 24
625
626
627
628
629
630
631
632# define VC4_HDMI_CEC_RX_CONTINUE BIT(23)
633# define VC4_HDMI_CEC_TX_CONTINUE BIT(22)
634
635# define VC4_HDMI_CEC_CLEAR_RECEIVE_OFF BIT(21)
636
637
638
639# define VC4_HDMI_CEC_START_XMIT_BEGIN BIT(20)
640# define VC4_HDMI_CEC_MESSAGE_LENGTH_MASK VC4_MASK(19, 16)
641# define VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT 16
642
643# define VC4_HDMI_CEC_ADDR_MASK VC4_MASK(15, 12)
644# define VC4_HDMI_CEC_ADDR_SHIFT 12
645
646
647# define VC4_HDMI_CEC_DIV_CLK_CNT_MASK VC4_MASK(11, 0)
648# define VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT 0
649
650
651
652
653#define VC4_HDMI_CEC_CNTRL_2 0x0ec
654# define VC4_HDMI_CEC_CNT_TO_1500_US_MASK VC4_MASK(30, 24)
655# define VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT 24
656# define VC4_HDMI_CEC_CNT_TO_1300_US_MASK VC4_MASK(23, 17)
657# define VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT 17
658# define VC4_HDMI_CEC_CNT_TO_800_US_MASK VC4_MASK(16, 11)
659# define VC4_HDMI_CEC_CNT_TO_800_US_SHIFT 11
660# define VC4_HDMI_CEC_CNT_TO_600_US_MASK VC4_MASK(10, 5)
661# define VC4_HDMI_CEC_CNT_TO_600_US_SHIFT 5
662# define VC4_HDMI_CEC_CNT_TO_400_US_MASK VC4_MASK(4, 0)
663# define VC4_HDMI_CEC_CNT_TO_400_US_SHIFT 0
664
665#define VC4_HDMI_CEC_CNTRL_3 0x0f0
666# define VC4_HDMI_CEC_CNT_TO_2750_US_MASK VC4_MASK(31, 24)
667# define VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT 24
668# define VC4_HDMI_CEC_CNT_TO_2400_US_MASK VC4_MASK(23, 16)
669# define VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT 16
670# define VC4_HDMI_CEC_CNT_TO_2050_US_MASK VC4_MASK(15, 8)
671# define VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT 8
672# define VC4_HDMI_CEC_CNT_TO_1700_US_MASK VC4_MASK(7, 0)
673# define VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT 0
674
675#define VC4_HDMI_CEC_CNTRL_4 0x0f4
676# define VC4_HDMI_CEC_CNT_TO_4300_US_MASK VC4_MASK(31, 24)
677# define VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT 24
678# define VC4_HDMI_CEC_CNT_TO_3900_US_MASK VC4_MASK(23, 16)
679# define VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT 16
680# define VC4_HDMI_CEC_CNT_TO_3600_US_MASK VC4_MASK(15, 8)
681# define VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT 8
682# define VC4_HDMI_CEC_CNT_TO_3500_US_MASK VC4_MASK(7, 0)
683# define VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT 0
684
685#define VC4_HDMI_CEC_CNTRL_5 0x0f8
686# define VC4_HDMI_CEC_TX_SW_RESET BIT(27)
687# define VC4_HDMI_CEC_RX_SW_RESET BIT(26)
688# define VC4_HDMI_CEC_PAD_SW_RESET BIT(25)
689# define VC4_HDMI_CEC_MUX_TP_OUT_CEC BIT(24)
690# define VC4_HDMI_CEC_RX_CEC_INT BIT(23)
691# define VC4_HDMI_CEC_CLK_PRELOAD_MASK VC4_MASK(22, 16)
692# define VC4_HDMI_CEC_CLK_PRELOAD_SHIFT 16
693# define VC4_HDMI_CEC_CNT_TO_4700_US_MASK VC4_MASK(15, 8)
694# define VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT 8
695# define VC4_HDMI_CEC_CNT_TO_4500_US_MASK VC4_MASK(7, 0)
696# define VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT 0
697
698
699
700
701#define VC4_HDMI_CEC_TX_DATA_1 0x0fc
702#define VC4_HDMI_CEC_TX_DATA_2 0x100
703#define VC4_HDMI_CEC_TX_DATA_3 0x104
704#define VC4_HDMI_CEC_TX_DATA_4 0x108
705#define VC4_HDMI_CEC_RX_DATA_1 0x10c
706#define VC4_HDMI_CEC_RX_DATA_2 0x110
707#define VC4_HDMI_CEC_RX_DATA_3 0x114
708#define VC4_HDMI_CEC_RX_DATA_4 0x118
709
710#define VC4_HDMI_TX_PHY_RESET_CTL 0x2c0
711
712#define VC4_HDMI_TX_PHY_CTL0 0x2c4
713# define VC4_HDMI_TX_PHY_RNG_PWRDN BIT(25)
714
715
716#define VC4_HDMI_CPU_STATUS 0x340
717#define VC4_HDMI_CPU_SET 0x344
718#define VC4_HDMI_CPU_CLEAR 0x348
719# define VC4_HDMI_CPU_CEC BIT(6)
720# define VC4_HDMI_CPU_HOTPLUG BIT(0)
721
722#define VC4_HDMI_CPU_MASK_STATUS 0x34c
723#define VC4_HDMI_CPU_MASK_SET 0x350
724#define VC4_HDMI_CPU_MASK_CLEAR 0x354
725
726#define VC4_HDMI_GCP(x) (0x400 + ((x) * 0x4))
727#define VC4_HDMI_RAM_PACKET(x) (0x400 + ((x) * 0x24))
728#define VC4_HDMI_PACKET_STRIDE 0x24
729
730#define VC4_HD_M_CTL 0x00c
731
732# define VC4_HD_CECRXD BIT(9)
733
734# define VC4_HD_CECOVR BIT(8)
735# define VC4_HD_M_REGISTER_FILE_STANDBY (3 << 6)
736# define VC4_HD_M_RAM_STANDBY (3 << 4)
737# define VC4_HD_M_SW_RST BIT(2)
738# define VC4_HD_M_ENABLE BIT(0)
739
740#define VC4_HD_MAI_CTL 0x014
741
742
743
744# define VC4_HD_MAI_CTL_DLATE BIT(15)
745# define VC4_HD_MAI_CTL_BUSY BIT(14)
746# define VC4_HD_MAI_CTL_CHALIGN BIT(13)
747# define VC4_HD_MAI_CTL_WHOLSMP BIT(12)
748# define VC4_HD_MAI_CTL_FULL BIT(11)
749# define VC4_HD_MAI_CTL_EMPTY BIT(10)
750# define VC4_HD_MAI_CTL_FLUSH BIT(9)
751
752
753
754# define VC4_HD_MAI_CTL_PAREN BIT(8)
755# define VC4_HD_MAI_CTL_CHNUM_MASK VC4_MASK(7, 4)
756# define VC4_HD_MAI_CTL_CHNUM_SHIFT 4
757# define VC4_HD_MAI_CTL_ENABLE BIT(3)
758
759# define VC4_HD_MAI_CTL_ERRORE BIT(2)
760
761# define VC4_HD_MAI_CTL_ERRORF BIT(1)
762
763# define VC4_HD_MAI_CTL_RESET BIT(0)
764
765#define VC4_HD_MAI_THR 0x018
766# define VC4_HD_MAI_THR_PANICHIGH_MASK VC4_MASK(29, 24)
767# define VC4_HD_MAI_THR_PANICHIGH_SHIFT 24
768# define VC4_HD_MAI_THR_PANICLOW_MASK VC4_MASK(21, 16)
769# define VC4_HD_MAI_THR_PANICLOW_SHIFT 16
770# define VC4_HD_MAI_THR_DREQHIGH_MASK VC4_MASK(13, 8)
771# define VC4_HD_MAI_THR_DREQHIGH_SHIFT 8
772# define VC4_HD_MAI_THR_DREQLOW_MASK VC4_MASK(5, 0)
773# define VC4_HD_MAI_THR_DREQLOW_SHIFT 0
774
775
776#define VC4_HD_MAI_FMT 0x01c
777
778
779
780
781#define VC4_HD_MAI_DATA 0x020
782
783
784
785
786#define VC4_HD_MAI_SMP 0x02c
787# define VC4_HD_MAI_SMP_N_MASK VC4_MASK(31, 8)
788# define VC4_HD_MAI_SMP_N_SHIFT 8
789# define VC4_HD_MAI_SMP_M_MASK VC4_MASK(7, 0)
790# define VC4_HD_MAI_SMP_M_SHIFT 0
791
792#define VC4_HD_VID_CTL 0x038
793# define VC4_HD_VID_CTL_ENABLE BIT(31)
794# define VC4_HD_VID_CTL_UNDERFLOW_ENABLE BIT(30)
795# define VC4_HD_VID_CTL_FRAME_COUNTER_RESET BIT(29)
796# define VC4_HD_VID_CTL_VSYNC_LOW BIT(28)
797# define VC4_HD_VID_CTL_HSYNC_LOW BIT(27)
798
799#define VC4_HD_CSC_CTL 0x040
800# define VC4_HD_CSC_CTL_ORDER_MASK VC4_MASK(7, 5)
801# define VC4_HD_CSC_CTL_ORDER_SHIFT 5
802# define VC4_HD_CSC_CTL_ORDER_RGB 0
803# define VC4_HD_CSC_CTL_ORDER_BGR 1
804# define VC4_HD_CSC_CTL_ORDER_BRG 2
805# define VC4_HD_CSC_CTL_ORDER_GRB 3
806# define VC4_HD_CSC_CTL_ORDER_GBR 4
807# define VC4_HD_CSC_CTL_ORDER_RBG 5
808# define VC4_HD_CSC_CTL_PADMSB BIT(4)
809# define VC4_HD_CSC_CTL_MODE_MASK VC4_MASK(3, 2)
810# define VC4_HD_CSC_CTL_MODE_SHIFT 2
811# define VC4_HD_CSC_CTL_MODE_RGB_TO_SD_YPRPB 0
812# define VC4_HD_CSC_CTL_MODE_RGB_TO_HD_YPRPB 1
813# define VC4_HD_CSC_CTL_MODE_CUSTOM 3
814# define VC4_HD_CSC_CTL_RGB2YCC BIT(1)
815# define VC4_HD_CSC_CTL_ENABLE BIT(0)
816
817#define VC4_HD_CSC_12_11 0x044
818#define VC4_HD_CSC_14_13 0x048
819#define VC4_HD_CSC_22_21 0x04c
820#define VC4_HD_CSC_24_23 0x050
821#define VC4_HD_CSC_32_31 0x054
822#define VC4_HD_CSC_34_33 0x058
823
824#define VC4_HD_FRAME_COUNT 0x068
825
826
827#define HVS_BOOTLOADER_DLIST_END 32
828
829enum hvs_pixel_format {
830
831 HVS_PIXEL_FORMAT_RGB332 = 0,
832
833 HVS_PIXEL_FORMAT_RGBA4444 = 1,
834 HVS_PIXEL_FORMAT_RGB555 = 2,
835 HVS_PIXEL_FORMAT_RGBA5551 = 3,
836 HVS_PIXEL_FORMAT_RGB565 = 4,
837
838 HVS_PIXEL_FORMAT_RGB888 = 5,
839 HVS_PIXEL_FORMAT_RGBA6666 = 6,
840
841 HVS_PIXEL_FORMAT_RGBA8888 = 7,
842
843 HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE = 8,
844 HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE = 9,
845 HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE = 10,
846 HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE = 11,
847 HVS_PIXEL_FORMAT_H264 = 12,
848 HVS_PIXEL_FORMAT_PALETTE = 13,
849 HVS_PIXEL_FORMAT_YUV444_RGB = 14,
850 HVS_PIXEL_FORMAT_AYUV444_RGB = 15,
851};
852
853
854
855
856#define HVS_PIXEL_ORDER_RGBA 0
857#define HVS_PIXEL_ORDER_BGRA 1
858#define HVS_PIXEL_ORDER_ARGB 2
859#define HVS_PIXEL_ORDER_ABGR 3
860
861#define HVS_PIXEL_ORDER_XBRG 0
862#define HVS_PIXEL_ORDER_XRBG 1
863#define HVS_PIXEL_ORDER_XRGB 2
864#define HVS_PIXEL_ORDER_XBGR 3
865
866#define HVS_PIXEL_ORDER_XYCBCR 0
867#define HVS_PIXEL_ORDER_XYCRCB 1
868#define HVS_PIXEL_ORDER_YXCBCR 2
869#define HVS_PIXEL_ORDER_YXCRCB 3
870
871#define SCALER_CTL0_END BIT(31)
872#define SCALER_CTL0_VALID BIT(30)
873
874#define SCALER_CTL0_SIZE_MASK VC4_MASK(29, 24)
875#define SCALER_CTL0_SIZE_SHIFT 24
876
877#define SCALER_CTL0_TILING_MASK VC4_MASK(21, 20)
878#define SCALER_CTL0_TILING_SHIFT 20
879#define SCALER_CTL0_TILING_LINEAR 0
880#define SCALER_CTL0_TILING_64B 1
881#define SCALER_CTL0_TILING_128B 2
882#define SCALER_CTL0_TILING_256B_OR_T 3
883
884#define SCALER_CTL0_ALPHA_MASK BIT(19)
885#define SCALER_CTL0_HFLIP BIT(16)
886#define SCALER_CTL0_VFLIP BIT(15)
887
888#define SCALER_CTL0_KEY_MODE_MASK VC4_MASK(18, 17)
889#define SCALER_CTL0_KEY_MODE_SHIFT 17
890#define SCALER_CTL0_KEY_DISABLED 0
891#define SCALER_CTL0_KEY_LUMA_OR_COMMON_RGB 1
892#define SCALER_CTL0_KEY_MATCH 2
893#define SCALER_CTL0_KEY_REPLACE 3
894
895#define SCALER_CTL0_ORDER_MASK VC4_MASK(14, 13)
896#define SCALER_CTL0_ORDER_SHIFT 13
897
898#define SCALER_CTL0_RGBA_EXPAND_MASK VC4_MASK(12, 11)
899#define SCALER_CTL0_RGBA_EXPAND_SHIFT 11
900#define SCALER_CTL0_RGBA_EXPAND_ZERO 0
901#define SCALER_CTL0_RGBA_EXPAND_LSB 1
902#define SCALER_CTL0_RGBA_EXPAND_MSB 2
903#define SCALER_CTL0_RGBA_EXPAND_ROUND 3
904
905#define SCALER_CTL0_SCL1_MASK VC4_MASK(10, 8)
906#define SCALER_CTL0_SCL1_SHIFT 8
907
908#define SCALER_CTL0_SCL0_MASK VC4_MASK(7, 5)
909#define SCALER_CTL0_SCL0_SHIFT 5
910
911#define SCALER_CTL0_SCL_H_PPF_V_PPF 0
912#define SCALER_CTL0_SCL_H_TPZ_V_PPF 1
913#define SCALER_CTL0_SCL_H_PPF_V_TPZ 2
914#define SCALER_CTL0_SCL_H_TPZ_V_TPZ 3
915#define SCALER_CTL0_SCL_H_PPF_V_NONE 4
916#define SCALER_CTL0_SCL_H_NONE_V_PPF 5
917#define SCALER_CTL0_SCL_H_NONE_V_TPZ 6
918#define SCALER_CTL0_SCL_H_TPZ_V_NONE 7
919
920
921#define SCALER_CTL0_UNITY BIT(4)
922
923#define SCALER_CTL0_PIXEL_FORMAT_MASK VC4_MASK(3, 0)
924#define SCALER_CTL0_PIXEL_FORMAT_SHIFT 0
925
926#define SCALER_POS0_FIXED_ALPHA_MASK VC4_MASK(31, 24)
927#define SCALER_POS0_FIXED_ALPHA_SHIFT 24
928
929#define SCALER_POS0_START_Y_MASK VC4_MASK(23, 12)
930#define SCALER_POS0_START_Y_SHIFT 12
931
932#define SCALER_POS0_START_X_MASK VC4_MASK(11, 0)
933#define SCALER_POS0_START_X_SHIFT 0
934
935#define SCALER_POS1_SCL_HEIGHT_MASK VC4_MASK(27, 16)
936#define SCALER_POS1_SCL_HEIGHT_SHIFT 16
937
938#define SCALER_POS1_SCL_WIDTH_MASK VC4_MASK(11, 0)
939#define SCALER_POS1_SCL_WIDTH_SHIFT 0
940
941#define SCALER_POS2_ALPHA_MODE_MASK VC4_MASK(31, 30)
942#define SCALER_POS2_ALPHA_MODE_SHIFT 30
943#define SCALER_POS2_ALPHA_MODE_PIPELINE 0
944#define SCALER_POS2_ALPHA_MODE_FIXED 1
945#define SCALER_POS2_ALPHA_MODE_FIXED_NONZERO 2
946#define SCALER_POS2_ALPHA_MODE_FIXED_OVER_0x07 3
947#define SCALER_POS2_ALPHA_PREMULT BIT(29)
948#define SCALER_POS2_ALPHA_MIX BIT(28)
949
950#define SCALER_POS2_HEIGHT_MASK VC4_MASK(27, 16)
951#define SCALER_POS2_HEIGHT_SHIFT 16
952
953#define SCALER_POS2_WIDTH_MASK VC4_MASK(11, 0)
954#define SCALER_POS2_WIDTH_SHIFT 0
955
956
957
958
959
960
961#define SCALER_CSC0_COEF_CR_BLU_MASK VC4_MASK(31, 24)
962#define SCALER_CSC0_COEF_CR_BLU_SHIFT 24
963
964#define SCALER_CSC0_COEF_YY_OFS_MASK VC4_MASK(23, 16)
965#define SCALER_CSC0_COEF_YY_OFS_SHIFT 16
966
967#define SCALER_CSC0_COEF_CB_OFS_MASK VC4_MASK(15, 8)
968#define SCALER_CSC0_COEF_CB_OFS_SHIFT 8
969
970#define SCALER_CSC0_COEF_CR_OFS_MASK VC4_MASK(7, 0)
971#define SCALER_CSC0_COEF_CR_OFS_SHIFT 0
972#define SCALER_CSC0_ITR_R_601_5 0x00f00000
973#define SCALER_CSC0_ITR_R_709_3 0x00f00000
974#define SCALER_CSC0_JPEG_JFIF 0x00000000
975
976
977#define SCALER_CSC1_COEF_CB_GRN_MASK VC4_MASK(31, 22)
978#define SCALER_CSC1_COEF_CB_GRN_SHIFT 22
979
980#define SCALER_CSC1_COEF_CR_GRN_MASK VC4_MASK(21, 12)
981#define SCALER_CSC1_COEF_CR_GRN_SHIFT 12
982
983#define SCALER_CSC1_COEF_YY_ALL_MASK VC4_MASK(11, 2)
984#define SCALER_CSC1_COEF_YY_ALL_SHIFT 2
985
986#define SCALER_CSC1_COEF_CR_BLU_MASK VC4_MASK(1, 0)
987#define SCALER_CSC1_COEF_CR_BLU_SHIFT 0
988#define SCALER_CSC1_ITR_R_601_5 0xe73304a8
989#define SCALER_CSC1_ITR_R_709_3 0xf2b784a8
990#define SCALER_CSC1_JPEG_JFIF 0xea34a400
991
992
993#define SCALER_CSC2_COEF_CB_RED_MASK VC4_MASK(29, 20)
994#define SCALER_CSC2_COEF_CB_RED_SHIFT 20
995
996#define SCALER_CSC2_COEF_CR_RED_MASK VC4_MASK(19, 10)
997#define SCALER_CSC2_COEF_CR_RED_SHIFT 10
998
999#define SCALER_CSC2_COEF_CB_BLU_MASK VC4_MASK(19, 10)
1000#define SCALER_CSC2_COEF_CB_BLU_SHIFT 10
1001#define SCALER_CSC2_ITR_R_601_5 0x00066204
1002#define SCALER_CSC2_ITR_R_709_3 0x00072a1c
1003#define SCALER_CSC2_JPEG_JFIF 0x000599c5
1004
1005#define SCALER_TPZ0_VERT_RECALC BIT(31)
1006#define SCALER_TPZ0_SCALE_MASK VC4_MASK(28, 8)
1007#define SCALER_TPZ0_SCALE_SHIFT 8
1008#define SCALER_TPZ0_IPHASE_MASK VC4_MASK(7, 0)
1009#define SCALER_TPZ0_IPHASE_SHIFT 0
1010#define SCALER_TPZ1_RECIP_MASK VC4_MASK(15, 0)
1011#define SCALER_TPZ1_RECIP_SHIFT 0
1012
1013
1014
1015
1016#define SCALER_PPF_NOINTERP BIT(31)
1017
1018
1019
1020#define SCALER_PPF_AGC BIT(30)
1021#define SCALER_PPF_SCALE_MASK VC4_MASK(24, 8)
1022#define SCALER_PPF_SCALE_SHIFT 8
1023#define SCALER_PPF_IPHASE_MASK VC4_MASK(6, 0)
1024#define SCALER_PPF_IPHASE_SHIFT 0
1025
1026#define SCALER_PPF_KERNEL_OFFSET_MASK VC4_MASK(13, 0)
1027#define SCALER_PPF_KERNEL_OFFSET_SHIFT 0
1028#define SCALER_PPF_KERNEL_UNCACHED BIT(31)
1029
1030
1031#define SCALER_SRC_PITCH_MASK VC4_MASK(15, 0)
1032#define SCALER_SRC_PITCH_SHIFT 0
1033
1034
1035#define SCALER_TILE_SKIP_0_MASK VC4_MASK(18, 16)
1036#define SCALER_TILE_SKIP_0_SHIFT 16
1037#define SCALER_TILE_HEIGHT_MASK VC4_MASK(15, 0)
1038#define SCALER_TILE_HEIGHT_SHIFT 0
1039
1040
1041#define SCALER_PITCH0_SINK_PIX_MASK VC4_MASK(31, 26)
1042#define SCALER_PITCH0_SINK_PIX_SHIFT 26
1043
1044
1045#define SCALER_PITCH0_TILE_WIDTH_L_MASK VC4_MASK(22, 16)
1046#define SCALER_PITCH0_TILE_WIDTH_L_SHIFT 16
1047#define SCALER_PITCH0_TILE_LINE_DIR BIT(15)
1048#define SCALER_PITCH0_TILE_INITIAL_LINE_DIR BIT(14)
1049
1050#define SCALER_PITCH0_TILE_Y_OFFSET_MASK VC4_MASK(13, 8)
1051#define SCALER_PITCH0_TILE_Y_OFFSET_SHIFT 8
1052#define SCALER_PITCH0_TILE_WIDTH_R_MASK VC4_MASK(6, 0)
1053#define SCALER_PITCH0_TILE_WIDTH_R_SHIFT 0
1054
1055#endif
1056