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9#include <linux/device.h>
10#include <linux/kernel.h>
11#include <linux/slab.h>
12#include <linux/sysfs.h>
13#include <linux/spi/spi.h>
14#include <linux/regulator/consumer.h>
15#include <linux/err.h>
16#include <linux/module.h>
17#include <linux/bitops.h>
18
19#include <linux/iio/iio.h>
20#include <linux/iio/sysfs.h>
21#include <linux/iio/buffer.h>
22#include <linux/iio/trigger_consumer.h>
23#include <linux/iio/triggered_buffer.h>
24
25struct ad7476_state;
26
27struct ad7476_chip_info {
28 unsigned int int_vref_uv;
29 struct iio_chan_spec channel[2];
30 void (*reset)(struct ad7476_state *);
31};
32
33struct ad7476_state {
34 struct spi_device *spi;
35 const struct ad7476_chip_info *chip_info;
36 struct regulator *reg;
37 struct spi_transfer xfer;
38 struct spi_message msg;
39
40
41
42
43
44
45 unsigned char data[ALIGN(2, sizeof(s64)) + sizeof(s64)]
46 ____cacheline_aligned;
47};
48
49enum ad7476_supported_device_ids {
50 ID_AD7091R,
51 ID_AD7276,
52 ID_AD7277,
53 ID_AD7278,
54 ID_AD7466,
55 ID_AD7467,
56 ID_AD7468,
57 ID_AD7495,
58 ID_AD7940,
59 ID_ADC081S,
60 ID_ADC101S,
61 ID_ADC121S,
62};
63
64static irqreturn_t ad7476_trigger_handler(int irq, void *p)
65{
66 struct iio_poll_func *pf = p;
67 struct iio_dev *indio_dev = pf->indio_dev;
68 struct ad7476_state *st = iio_priv(indio_dev);
69 int b_sent;
70
71 b_sent = spi_sync(st->spi, &st->msg);
72 if (b_sent < 0)
73 goto done;
74
75 iio_push_to_buffers_with_timestamp(indio_dev, st->data,
76 iio_get_time_ns(indio_dev));
77done:
78 iio_trigger_notify_done(indio_dev->trig);
79
80 return IRQ_HANDLED;
81}
82
83static void ad7091_reset(struct ad7476_state *st)
84{
85
86 spi_read(st->spi, st->data, 1);
87}
88
89static int ad7476_scan_direct(struct ad7476_state *st)
90{
91 int ret;
92
93 ret = spi_sync(st->spi, &st->msg);
94 if (ret)
95 return ret;
96
97 return be16_to_cpup((__be16 *)st->data);
98}
99
100static int ad7476_read_raw(struct iio_dev *indio_dev,
101 struct iio_chan_spec const *chan,
102 int *val,
103 int *val2,
104 long m)
105{
106 int ret;
107 struct ad7476_state *st = iio_priv(indio_dev);
108 int scale_uv;
109
110 switch (m) {
111 case IIO_CHAN_INFO_RAW:
112 ret = iio_device_claim_direct_mode(indio_dev);
113 if (ret)
114 return ret;
115 ret = ad7476_scan_direct(st);
116 iio_device_release_direct_mode(indio_dev);
117
118 if (ret < 0)
119 return ret;
120 *val = (ret >> st->chip_info->channel[0].scan_type.shift) &
121 GENMASK(st->chip_info->channel[0].scan_type.realbits - 1, 0);
122 return IIO_VAL_INT;
123 case IIO_CHAN_INFO_SCALE:
124 if (!st->chip_info->int_vref_uv) {
125 scale_uv = regulator_get_voltage(st->reg);
126 if (scale_uv < 0)
127 return scale_uv;
128 } else {
129 scale_uv = st->chip_info->int_vref_uv;
130 }
131 *val = scale_uv / 1000;
132 *val2 = chan->scan_type.realbits;
133 return IIO_VAL_FRACTIONAL_LOG2;
134 }
135 return -EINVAL;
136}
137
138#define _AD7476_CHAN(bits, _shift, _info_mask_sep) \
139 { \
140 .type = IIO_VOLTAGE, \
141 .indexed = 1, \
142 .info_mask_separate = _info_mask_sep, \
143 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
144 .scan_type = { \
145 .sign = 'u', \
146 .realbits = (bits), \
147 .storagebits = 16, \
148 .shift = (_shift), \
149 .endianness = IIO_BE, \
150 }, \
151}
152
153#define ADC081S_CHAN(bits) _AD7476_CHAN((bits), 12 - (bits), \
154 BIT(IIO_CHAN_INFO_RAW))
155#define AD7476_CHAN(bits) _AD7476_CHAN((bits), 13 - (bits), \
156 BIT(IIO_CHAN_INFO_RAW))
157#define AD7940_CHAN(bits) _AD7476_CHAN((bits), 15 - (bits), \
158 BIT(IIO_CHAN_INFO_RAW))
159#define AD7091R_CHAN(bits) _AD7476_CHAN((bits), 16 - (bits), 0)
160
161static const struct ad7476_chip_info ad7476_chip_info_tbl[] = {
162 [ID_AD7091R] = {
163 .channel[0] = AD7091R_CHAN(12),
164 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
165 .reset = ad7091_reset,
166 },
167 [ID_AD7276] = {
168 .channel[0] = AD7940_CHAN(12),
169 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
170 },
171 [ID_AD7277] = {
172 .channel[0] = AD7940_CHAN(10),
173 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
174 },
175 [ID_AD7278] = {
176 .channel[0] = AD7940_CHAN(8),
177 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
178 },
179 [ID_AD7466] = {
180 .channel[0] = AD7476_CHAN(12),
181 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
182 },
183 [ID_AD7467] = {
184 .channel[0] = AD7476_CHAN(10),
185 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
186 },
187 [ID_AD7468] = {
188 .channel[0] = AD7476_CHAN(8),
189 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
190 },
191 [ID_AD7495] = {
192 .channel[0] = AD7476_CHAN(12),
193 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
194 .int_vref_uv = 2500000,
195 },
196 [ID_AD7940] = {
197 .channel[0] = AD7940_CHAN(14),
198 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
199 },
200 [ID_ADC081S] = {
201 .channel[0] = ADC081S_CHAN(8),
202 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
203 },
204 [ID_ADC101S] = {
205 .channel[0] = ADC081S_CHAN(10),
206 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
207 },
208 [ID_ADC121S] = {
209 .channel[0] = ADC081S_CHAN(12),
210 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
211 },
212};
213
214static const struct iio_info ad7476_info = {
215 .read_raw = &ad7476_read_raw,
216};
217
218static int ad7476_probe(struct spi_device *spi)
219{
220 struct ad7476_state *st;
221 struct iio_dev *indio_dev;
222 int ret;
223
224 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
225 if (!indio_dev)
226 return -ENOMEM;
227
228 st = iio_priv(indio_dev);
229 st->chip_info =
230 &ad7476_chip_info_tbl[spi_get_device_id(spi)->driver_data];
231
232 st->reg = devm_regulator_get(&spi->dev, "vcc");
233 if (IS_ERR(st->reg))
234 return PTR_ERR(st->reg);
235
236 ret = regulator_enable(st->reg);
237 if (ret)
238 return ret;
239
240 spi_set_drvdata(spi, indio_dev);
241
242 st->spi = spi;
243
244
245 indio_dev->dev.parent = &spi->dev;
246 indio_dev->dev.of_node = spi->dev.of_node;
247 indio_dev->name = spi_get_device_id(spi)->name;
248 indio_dev->modes = INDIO_DIRECT_MODE;
249 indio_dev->channels = st->chip_info->channel;
250 indio_dev->num_channels = 2;
251 indio_dev->info = &ad7476_info;
252
253
254 st->xfer.rx_buf = &st->data;
255 st->xfer.len = st->chip_info->channel[0].scan_type.storagebits / 8;
256
257 spi_message_init(&st->msg);
258 spi_message_add_tail(&st->xfer, &st->msg);
259
260 ret = iio_triggered_buffer_setup(indio_dev, NULL,
261 &ad7476_trigger_handler, NULL);
262 if (ret)
263 goto error_disable_reg;
264
265 if (st->chip_info->reset)
266 st->chip_info->reset(st);
267
268 ret = iio_device_register(indio_dev);
269 if (ret)
270 goto error_ring_unregister;
271 return 0;
272
273error_ring_unregister:
274 iio_triggered_buffer_cleanup(indio_dev);
275error_disable_reg:
276 regulator_disable(st->reg);
277
278 return ret;
279}
280
281static int ad7476_remove(struct spi_device *spi)
282{
283 struct iio_dev *indio_dev = spi_get_drvdata(spi);
284 struct ad7476_state *st = iio_priv(indio_dev);
285
286 iio_device_unregister(indio_dev);
287 iio_triggered_buffer_cleanup(indio_dev);
288 regulator_disable(st->reg);
289
290 return 0;
291}
292
293static const struct spi_device_id ad7476_id[] = {
294 {"ad7091r", ID_AD7091R},
295 {"ad7273", ID_AD7277},
296 {"ad7274", ID_AD7276},
297 {"ad7276", ID_AD7276},
298 {"ad7277", ID_AD7277},
299 {"ad7278", ID_AD7278},
300 {"ad7466", ID_AD7466},
301 {"ad7467", ID_AD7467},
302 {"ad7468", ID_AD7468},
303 {"ad7475", ID_AD7466},
304 {"ad7476", ID_AD7466},
305 {"ad7476a", ID_AD7466},
306 {"ad7477", ID_AD7467},
307 {"ad7477a", ID_AD7467},
308 {"ad7478", ID_AD7468},
309 {"ad7478a", ID_AD7468},
310 {"ad7495", ID_AD7495},
311 {"ad7910", ID_AD7467},
312 {"ad7920", ID_AD7466},
313 {"ad7940", ID_AD7940},
314 {"adc081s", ID_ADC081S},
315 {"adc101s", ID_ADC101S},
316 {"adc121s", ID_ADC121S},
317 {}
318};
319MODULE_DEVICE_TABLE(spi, ad7476_id);
320
321static struct spi_driver ad7476_driver = {
322 .driver = {
323 .name = "ad7476",
324 },
325 .probe = ad7476_probe,
326 .remove = ad7476_remove,
327 .id_table = ad7476_id,
328};
329module_spi_driver(ad7476_driver);
330
331MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
332MODULE_DESCRIPTION("Analog Devices AD7476 and similar 1-channel ADCs");
333MODULE_LICENSE("GPL v2");
334
